From 34ae21319e2e5c34d1e210e36231f695581ae05a Mon Sep 17 00:00:00 2001
From: tobozo <tobozo@users.noreply.github.com>
Date: Wed, 2 Mar 2022 15:00:07 +0100
Subject: added Absolute Mouse report struct

---
 src/class/hid/hid.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src')

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 940454bd9..667ee79aa 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -300,6 +300,20 @@ typedef struct TU_ATTR_PACKED
   int8_t  pan;     // using AC Pan
 } hid_mouse_report_t;
 
+
+// Absolute Mouse: same as the Standard (relative) Mouse Report but
+// with int16_t instead of int8_t for X and Y coordinates.
+typedef struct TU_ATTR_PACKED
+{
+    uint8_t buttons; /**< buttons mask for currently pressed buttons in the mouse. */
+    int16_t x;       /**< Current x position of the mouse. */
+    int16_t y;       /**< Current y position of the mouse. */
+    int8_t wheel;    /**< Current delta wheel movement on the mouse. */
+    int8_t pan;      // using AC Pan
+} abs_mouse_report_t;
+
+  
+  
 /// Standard Mouse Buttons Bitmap
 typedef enum
 {
-- 
cgit v1.3.1


From 8c79b8924eabf441f40a8ce3cab8828688575b6d Mon Sep 17 00:00:00 2001
From: tobozo <tobozo@users.noreply.github.com>
Date: Wed, 2 Mar 2022 15:01:18 +0100
Subject: added Absolute Mouse descriptor template

---
 src/class/hid/hid_device.h | 49 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

(limited to 'src')

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 078b67349..547a78f4f 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -266,6 +266,55 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     HID_COLLECTION_END                                            , \
   HID_COLLECTION_END \
 
+// Absolute Mouse Report Descriptor Template
+#define TUD_HID_REPORT_DESC_ABSMOUSE(...) \
+  HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP      )                   ,\
+  HID_USAGE      ( HID_USAGE_DESKTOP_MOUSE     )                   ,\
+  HID_COLLECTION ( HID_COLLECTION_APPLICATION  )                   ,\
+    /* Report ID if any */\
+    __VA_ARGS__ \
+    HID_USAGE      ( HID_USAGE_DESKTOP_POINTER )                   ,\
+    HID_COLLECTION ( HID_COLLECTION_PHYSICAL   )                   ,\
+      HID_USAGE_PAGE  ( HID_USAGE_PAGE_BUTTON  )                   ,\
+        HID_USAGE_MIN   ( 1                                      ) ,\
+        HID_USAGE_MAX   ( 5                                      ) ,\
+        HID_LOGICAL_MIN ( 0                                      ) ,\
+        HID_LOGICAL_MAX ( 1                                      ) ,\
+        /* Left, Right, Middle, Backward, Forward buttons */ \
+        HID_REPORT_COUNT( 5                                      ) ,\
+        HID_REPORT_SIZE ( 1                                      ) ,\
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+        /* 3 bit padding */ \
+        HID_REPORT_COUNT( 1                                      ) ,\
+        HID_REPORT_SIZE ( 3                                      ) ,\
+        HID_INPUT       ( HID_CONSTANT                           ) ,\
+      HID_USAGE_PAGE  ( HID_USAGE_PAGE_DESKTOP )                   ,\
+        /* X, Y absolute position [0, 32767] */ \
+        HID_USAGE       ( HID_USAGE_DESKTOP_X                    ) ,\
+        HID_USAGE       ( HID_USAGE_DESKTOP_Y                    ) ,\
+        HID_LOGICAL_MIN  ( 0x00                                ) ,\
+        HID_LOGICAL_MAX_N( 0x7FFF, 2                           ) ,\
+        HID_REPORT_SIZE  ( 16                                  ) ,\
+        HID_REPORT_COUNT ( 2                                   ) ,\
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+        /* Vertical wheel scroll [-127, 127] */ \
+        HID_USAGE       ( HID_USAGE_DESKTOP_WHEEL                )  ,\
+        HID_LOGICAL_MIN ( 0x81                                   )  ,\
+        HID_LOGICAL_MAX ( 0x7f                                   )  ,\
+        HID_REPORT_COUNT( 1                                      )  ,\
+        HID_REPORT_SIZE ( 8                                      )  ,\
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_RELATIVE )  ,\
+      HID_USAGE_PAGE  ( HID_USAGE_PAGE_CONSUMER ), \
+       /* Horizontal wheel scroll [-127, 127] */ \
+        HID_USAGE_N     ( HID_USAGE_CONSUMER_AC_PAN, 2           ), \
+        HID_LOGICAL_MIN ( 0x81                                   ), \
+        HID_LOGICAL_MAX ( 0x7f                                   ), \
+        HID_REPORT_COUNT( 1                                      ), \
+        HID_REPORT_SIZE ( 8                                      ), \
+        HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_RELATIVE ), \
+    HID_COLLECTION_END                                            , \
+  HID_COLLECTION_END \
+     
 // Consumer Control Report Descriptor Template
 #define TUD_HID_REPORT_DESC_CONSUMER(...) \
   HID_USAGE_PAGE ( HID_USAGE_PAGE_CONSUMER    )              ,\
-- 
cgit v1.3.1


From 9526a0ff736ccc4c8a9791a8467d6a6de82c0c45 Mon Sep 17 00:00:00 2001
From: tobozo <tobozo@users.noreply.github.com>
Date: Wed, 2 Mar 2022 16:56:59 +0100
Subject: stick to struct naming convention

---
 src/class/hid/hid.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 667ee79aa..98c2ee0de 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -310,7 +310,7 @@ typedef struct TU_ATTR_PACKED
     int16_t y;       /**< Current y position of the mouse. */
     int8_t wheel;    /**< Current delta wheel movement on the mouse. */
     int8_t pan;      // using AC Pan
-} abs_mouse_report_t;
+} hid_abs_mouse_report_t;
 
   
   
-- 
cgit v1.3.1


From f931983469bf375eec9503b99e021b9b633bf23f Mon Sep 17 00:00:00 2001
From: Mark K Cowan <mark@battlesnake.co.uk>
Date: Sun, 23 Oct 2022 02:55:28 +0300
Subject: UAC2 supports interrupt-endpoint for providing control-change
 notifications to the host

---
 src/class/audio/audio_device.c | 58 +++++++++++++++++++++++++++++++++++++++---
 src/class/audio/audio_device.h | 46 +++++++++++++++++++++++++++++----
 2 files changed, 96 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a65d605b7..05339f9ce 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -341,7 +341,7 @@ typedef struct
 
   // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
 #endif
 
   // Decoding parameters - parameters are set when alternate AS interface is set by host
@@ -464,7 +464,7 @@ bool tud_audio_n_mounted(uint8_t func_id)
   if (audio->ep_in == 0) return false;
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
   if (audio->ep_int_ctr == 0) return false;
 #endif
 
@@ -813,11 +813,13 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff(uint8_t func_id, uint8_t ff_idx)
 #endif
 
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
 
 // If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_ctr_done_cb() is called in inform user
 uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint16_t len)
 {
+  TU_VERIFY(_audiod_fct[func_id].ep_int_ctr != 0);
+
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
   // We write directly into the EP's buffer - abort if previous transfer not complete
@@ -1079,6 +1081,52 @@ static inline bool audiod_fb_send(uint8_t rhport, audiod_function_t *audio)
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+static bool set_int_ctr_number(audiod_function_t *audio)
+{
+
+  uint8_t const *p_desc = audio->p_desc;
+  // Get pointer at end
+  uint8_t const *p_desc_end = audio->p_desc + audio->desc_length - TUD_AUDIO_DESC_IAD_LEN;
+
+
+  // p_desc starts at required interface with alternate setting zero
+  while (p_desc < p_desc_end)
+  {
+    // Find correct interface
+    if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == 0 && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == 0)
+    {
+
+      uint8_t foundEPs = 0, nEps = ((tusb_desc_interface_t const * )p_desc)->bNumEndpoints;
+      while (foundEPs < nEps && p_desc < p_desc_end)
+      {
+        // found :n endpoint
+        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+        {
+          tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+
+          uint8_t const ep_addr = desc_ep->bEndpointAddress;
+
+          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.xfer == 0x03)   // Check if usage is interrupt EP
+          {
+            audio->ep_int_ctr = ep_addr;
+            TU_ASSERT(usbd_edpt_open(audio->rhport, desc_ep));
+          }
+
+          foundEPs += 1;
+        }
+        p_desc = tu_desc_next(p_desc);
+      }
+      break;
+    }
+    p_desc = tu_desc_next(p_desc);
+  }
+
+  return true;
+
+}
+#endif
+
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
@@ -1484,6 +1532,10 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   // This is all we need so far - the EPs are setup by a later set_interface request (as per UAC2 specification)
   uint16_t drv_len = _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;    // - TUD_AUDIO_DESC_IAD_LEN since tinyUSB already handles the IAD descriptor
 
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+  TU_ASSERT(set_int_ctr_number(&_audiod_fct[i]));
+#endif
+
   return drv_len;
 }
 
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 0ef100fa4..0c394d235 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -191,9 +191,19 @@
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION     0                             // 0 or 1
 #endif
 
+// Enable/disable interrupt EP (required for notifying host of control changes)
+#ifndef CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+#define CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP                    0                             // Feedback - 0 or 1
+#endif
+
 // Audio interrupt control EP size - disabled if 0
 #ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-#define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0                             // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
+// Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+#define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     6
+#else
+#define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0
+#endif
 #endif
 
 #ifndef CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE
@@ -388,7 +398,7 @@ uint16_t tud_audio_n_write_support_ff             (uint8_t func_id, uint8_t ff_i
 tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_idx);
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
 uint16_t    tud_audio_int_ctr_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
 #endif
 
@@ -431,7 +441,7 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff        (uint8_t ff_idx);
 
 // INT CTR API
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
 static inline uint16_t tud_audio_int_ctr_write              (uint8_t const* buffer, uint16_t len);
 #endif
 
@@ -531,7 +541,33 @@ TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func
 
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+// UAC2 §9.6
+// Structure of "interrupt data message"
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t bInfo;
+  uint8_t bAttribute;
+  union TU_ATTR_PACKED
+  {
+    uint16_t wValue;
+    struct TU_ATTR_PACKED
+    {
+      uint8_t wValue_cn_or_mcn;
+      uint8_t wValue_cs;
+    };
+  };
+  union TU_ATTR_PACKED
+  {
+    uint16_t wIndex;
+    struct TU_ATTR_PACKED
+    {
+      uint8_t wIndex_ep_or_int;
+      uint8_t wIndex_entity_id;
+    };
+  };
+} audio_status_update_t;
+
 TU_ATTR_WEAK bool tud_audio_int_ctr_done_cb(uint8_t rhport, uint16_t n_bytes_copied);
 #endif
 
@@ -663,7 +699,7 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff(uint8_t ff_idx)
 
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
 static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t len)
 {
   return tud_audio_int_ctr_n_write(0, buffer, len);
-- 
cgit v1.3.1


From 025d3477e81e07ddc2db78193e8957cdb1050516 Mon Sep 17 00:00:00 2001
From: Mark K Cowan <mark@battlesnake.co.uk>
Date: Mon, 24 Oct 2022 20:41:09 +0300
Subject: fixed spec reference

---
 src/class/audio/audio_device.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 0c394d235..92a1e6585 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -542,8 +542,7 @@ TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-// UAC2 §9.6
-// Structure of "interrupt data message"
+// UAC2 §6.1 "interrupt data message"
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bInfo;
-- 
cgit v1.3.1


From 15ed45e1a33210c5e949801a77aabd544fa170ed Mon Sep 17 00:00:00 2001
From: Mark K Cowan <mark@battlesnake.co.uk>
Date: Wed, 26 Oct 2022 21:40:30 +0300
Subject: clean up descriptor search for interrupt endpoint

---
 src/class/audio/audio_device.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 05339f9ce..efa06cf70 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1090,40 +1090,36 @@ static bool set_int_ctr_number(audiod_function_t *audio)
   uint8_t const *p_desc_end = audio->p_desc + audio->desc_length - TUD_AUDIO_DESC_IAD_LEN;
 
 
-  // p_desc starts at required interface with alternate setting zero
-  while (p_desc < p_desc_end)
+  bool found = false;
+  while (!found && p_desc < p_desc_end)
   {
-    // Find correct interface
-    if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == 0 && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == 0)
+    // For each interface/alternate
+    if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE)
     {
-
       uint8_t foundEPs = 0, nEps = ((tusb_desc_interface_t const * )p_desc)->bNumEndpoints;
-      while (foundEPs < nEps && p_desc < p_desc_end)
+      while (!found && foundEPs < nEps && p_desc < p_desc_end)
       {
-        // found :n endpoint
+        // For each endpoint
         if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
         {
           tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-
           uint8_t const ep_addr = desc_ep->bEndpointAddress;
-
+          // If endpoint is input-direction and interrupt-type
           if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.xfer == 0x03)   // Check if usage is interrupt EP
           {
+            // Store endpoint number and open endpoint
             audio->ep_int_ctr = ep_addr;
             TU_ASSERT(usbd_edpt_open(audio->rhport, desc_ep));
+            found = true;
           }
-
           foundEPs += 1;
         }
         p_desc = tu_desc_next(p_desc);
       }
-      break;
     }
     p_desc = tu_desc_next(p_desc);
   }
-
-  return true;
-
+  return found;
 }
 #endif
 
-- 
cgit v1.3.1


From 9673d20901dd5419c82ccc14dd2fd300ca0fa8c4 Mon Sep 17 00:00:00 2001
From: Mark K Cowan <mark@battlesnake.co.uk>
Date: Wed, 26 Oct 2022 21:43:27 +0300
Subject: PanRe refactor applied: s{_int_ctr_}{_int_}g; s{_INT_CTR_}{_INT_}g;

---
 src/class/audio/audio_device.c | 38 +++++++++++++++++++-------------------
 src/class/audio/audio_device.h | 20 ++++++++++----------
 2 files changed, 29 insertions(+), 29 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index efa06cf70..4681e1ddb 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -283,8 +283,8 @@ typedef struct
 
 #endif
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  uint8_t ep_int_ctr;           // Audio control interrupt EP.
+#if CFG_TUD_AUDIO_INT_EPSIZE_IN
+  uint8_t ep_int;           // Audio control interrupt EP.
 #endif
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
@@ -340,8 +340,8 @@ typedef struct
 #endif
 
   // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
+#if CFG_TUD_AUDIO_INT_EPSIZE_IN
+  CFG_TUSB_MEM_ALIGN uint8_t ep_int_buf[CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE];
 #endif
 
   // Decoding parameters - parameters are set when alternate AS interface is set by host
@@ -465,7 +465,7 @@ bool tud_audio_n_mounted(uint8_t func_id)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-  if (audio->ep_int_ctr == 0) return false;
+  if (audio->ep_int == 0) return false;
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
@@ -815,23 +815,23 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff(uint8_t func_id, uint8_t ff_idx)
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
 
-// If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_ctr_done_cb() is called in inform user
-uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint16_t len)
+// If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_done_cb() is called in inform user
+uint16_t tud_audio_int_n_write(uint8_t func_id, uint8_t const* buffer, uint16_t len)
 {
-  TU_VERIFY(_audiod_fct[func_id].ep_int_ctr != 0);
+  TU_VERIFY(_audiod_fct[func_id].ep_int != 0);
 
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
   // We write directly into the EP's buffer - abort if previous transfer not complete
-  TU_VERIFY(!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr));
+  TU_VERIFY(!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int));
 
   // Check length
-  TU_VERIFY(len <= CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE);
+  TU_VERIFY(len <= CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE);
 
-  memcpy(_audiod_fct[func_id].ep_int_ctr_buf, buffer, len);
+  memcpy(_audiod_fct[func_id].ep_int_buf, buffer, len);
 
   // Schedule transmit
-  TU_VERIFY(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr, _audiod_fct[func_id].ep_int_ctr_buf, len));
+  TU_VERIFY(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int, _audiod_fct[func_id].ep_int_buf, len));
 
   return true;
 }
@@ -1082,7 +1082,7 @@ static inline bool audiod_fb_send(uint8_t rhport, audiod_function_t *audio)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-static bool set_int_ctr_number(audiod_function_t *audio)
+static bool set_int_number(audiod_function_t *audio)
 {
 
   uint8_t const *p_desc = audio->p_desc;
@@ -1108,7 +1108,7 @@ static bool set_int_ctr_number(audiod_function_t *audio)
           if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.xfer == 0x03)   // Check if usage is interrupt EP
           {
             // Store endpoint number and open endpoint
-            audio->ep_int_ctr = ep_addr;
+            audio->ep_int = ep_addr;
             TU_ASSERT(usbd_edpt_open(audio->rhport, desc_ep));
             found = true;
           }
@@ -1485,7 +1485,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   // Verify interrupt control EP is enabled if demanded by descriptor - this should be best some static check however - this check can be omitted
   if (itf_desc->bNumEndpoints == 1) // 0 or 1 EPs are allowed
   {
-    TU_VERIFY(CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN > 0);
+    TU_VERIFY(CFG_TUD_AUDIO_INT_EPSIZE_IN > 0);
   }
 
   // Alternate setting MUST be zero - this check can be omitted
@@ -1529,7 +1529,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   uint16_t drv_len = _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;    // - TUD_AUDIO_DESC_IAD_LEN since tinyUSB already handles the IAD descriptor
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-  TU_ASSERT(set_int_ctr_number(&_audiod_fct[i]));
+  TU_ASSERT(set_int_number(&_audiod_fct[i]));
 #endif
 
   return drv_len;
@@ -2030,10 +2030,10 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
   {
     audiod_function_t* audio = &_audiod_fct[func_id];
 
-#if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#if CFG_TUD_AUDIO_INT_EPSIZE_IN
 
     // Data transmission of control interrupt finished
-    if (audio->ep_int_ctr == ep_addr)
+    if (audio->ep_int == ep_addr)
     {
       // According to USB2 specification, maximum payload of interrupt EP is 8 bytes on low speed, 64 bytes on full speed, and 1024 bytes on high speed (but only if an alternate interface other than 0 is used - see specification p. 49)
       // In case there is nothing to send we have to return a NAK - this is taken care of by PHY ???
@@ -2042,7 +2042,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
       // I assume here, that things above are handled by PHY
       // All transmission is done - what remains to do is to inform job was completed
 
-      if (tud_audio_int_ctr_done_cb) TU_VERIFY(tud_audio_int_ctr_done_cb(rhport, (uint16_t) xferred_bytes));
+      if (tud_audio_int_done_cb) TU_VERIFY(tud_audio_int_done_cb(rhport, (uint16_t) xferred_bytes));
     }
 
 #endif
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 92a1e6585..2e39e6049 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -197,17 +197,17 @@
 #endif
 
 // Audio interrupt control EP size - disabled if 0
-#ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
+#ifndef CFG_TUD_AUDIO_INT_EPSIZE_IN
 // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-#define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     6
+#define CFG_TUD_AUDIO_INT_EPSIZE_IN                     6
 #else
-#define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0
+#define CFG_TUD_AUDIO_INT_EPSIZE_IN                     0
 #endif
 #endif
 
-#ifndef CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE
-#define CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE          6                             // Buffer size of audio control interrupt EP - 6 Bytes according to UAC 2 specification (p. 74)
+#ifndef CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE
+#define CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE          6                             // Buffer size of audio control interrupt EP - 6 Bytes according to UAC 2 specification (p. 74)
 #endif
 
 // Use software encoding/decoding
@@ -399,7 +399,7 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_i
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-uint16_t    tud_audio_int_ctr_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
+uint16_t    tud_audio_int_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
 #endif
 
 //--------------------------------------------------------------------+
@@ -442,7 +442,7 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff        (uint8_t ff_idx);
 // INT CTR API
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-static inline uint16_t tud_audio_int_ctr_write              (uint8_t const* buffer, uint16_t len);
+static inline uint16_t tud_audio_int_write              (uint8_t const* buffer, uint16_t len);
 #endif
 
 // Buffer control EP data and schedule a transmit
@@ -567,7 +567,7 @@ typedef struct TU_ATTR_PACKED
   };
 } audio_status_update_t;
 
-TU_ATTR_WEAK bool tud_audio_int_ctr_done_cb(uint8_t rhport, uint16_t n_bytes_copied);
+TU_ATTR_WEAK bool tud_audio_int_done_cb(uint8_t rhport, uint16_t n_bytes_copied);
 #endif
 
 // Invoked when audio set interface request received
@@ -699,9 +699,9 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff(uint8_t ff_idx)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t len)
+static inline uint16_t tud_audio_int_write(uint8_t const* buffer, uint16_t len)
 {
-  return tud_audio_int_ctr_n_write(0, buffer, len);
+  return tud_audio_int_n_write(0, buffer, len);
 }
 #endif
 
-- 
cgit v1.3.1


From 4c510c12b1d0a0bfb0726c0100ff22cd892aa1e8 Mon Sep 17 00:00:00 2001
From: Gunar Schorcht <gunar@schorcht.net>
Date: Mon, 27 Feb 2023 09:54:45 +0100
Subject: synopsys/dwc2: fix SOF interrupt handling

SOF is not a flag of the GOTGINT register but of the GINTSTS register. Therefore the flag must be written in the GINTSTS register instead of the GOTGINT register to clear the interrupt.
---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c6132a1f5..7d4f31c48 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -1288,7 +1288,7 @@ void dcd_int_handler(uint8_t rhport)
 
   if(int_status & GINTSTS_SOF)
   {
-    dwc2->gotgint = GINTSTS_SOF;
+    dwc2->gintsts = GINTSTS_SOF;
 
     if (_sof_en)
     {
-- 
cgit v1.3.1


From a77aaf7f9e8a86c904d0bf6e8994288f45b3b410 Mon Sep 17 00:00:00 2001
From: tobozo <tobozo@users.noreply.github.com>
Date: Thu, 30 Mar 2023 21:57:06 +0200
Subject: Added helpers for abs_mouse_report

---
 src/class/hid/hid_device.c | 13 +++++++++++++
 src/class/hid/hid_device.h | 12 +++++++++++-
 2 files changed, 24 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 9240fe2ca..7e28b2c94 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -146,6 +146,19 @@ bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id,
   return tud_hid_n_report(instance, report_id, &report, sizeof(report));
 }
 
+bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal)
+{
+  hid_abs_mouse_report_t report =
+  {
+    .buttons = buttons,
+    .x       = x,
+    .y       = y,
+    .wheel   = vertical,
+    .pan     = horizontal
+  };
+  return tud_hid_n_report(instance, report_id, &report, sizeof(report));
+}
+
 bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
                               int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
   hid_gamepad_report_t report =
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index cb794e964..40755afed 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -72,6 +72,16 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
 // use template layout report as defined by hid_mouse_report_t
 bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal);
 
+// ABSOLUTE MOUSE: convenient helper to send absolute mouse report if application
+// use template layout report as defined by hid_abs_mouse_report_t
+bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal);
+
+
+static inline bool tud_hid_abs_mouse_report(uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal)
+{
+  return tud_hid_n_abs_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
+}
+
 // Gamepad: convenient helper to send gamepad report if application
 // use template layout report TUD_HID_REPORT_DESC_GAMEPAD
 bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
@@ -314,7 +324,7 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
         HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_RELATIVE ), \
     HID_COLLECTION_END                                            , \
   HID_COLLECTION_END \
-     
+
 // Consumer Control Report Descriptor Template
 #define TUD_HID_REPORT_DESC_CONSUMER(...) \
   HID_USAGE_PAGE ( HID_USAGE_PAGE_CONSUMER    )              ,\
-- 
cgit v1.3.1


From 805ebb39249a7b96092a9c59d244152bc343d898 Mon Sep 17 00:00:00 2001
From: tobozo <tobozo@users.noreply.github.com>
Date: Thu, 30 Mar 2023 22:01:36 +0200
Subject: remove trailing space (satisfy pre-commit flow)

---
 src/class/hid/hid.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 3e238966f..fcaab7a50 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -312,8 +312,7 @@ typedef struct TU_ATTR_PACKED
     int8_t pan;      // using AC Pan
 } hid_abs_mouse_report_t;
 
-  
-  
+
 /// Standard Mouse Buttons Bitmap
 typedef enum
 {
-- 
cgit v1.3.1


From 5ade91780578bca10bae048a58fed4b788b553d1 Mon Sep 17 00:00:00 2001
From: Michiel van Leeuwen <michiel@embeddedacoustics.com>
Date: Fri, 28 Apr 2023 11:26:26 +0200
Subject: dwc2: configure fifo size to be twice the max_size

This is needed in order to always be able to fit a packet in the fifo.
Writing to the fifo is done from an interrupts that fires when the fifo is
half-empty, so the fifo must be twice the packet size.
---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c6132a1f5..bcd584953 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -534,6 +534,9 @@ void dcd_init (uint8_t rhport)
   int_mask = dwc2->gotgint;
   dwc2->gotgint |= int_mask;
 
+  // Configure TX FIFO to set the TX FIFO empty interrupt when half-empty
+  dwc2->gahbcfg &= ~GAHBCFG_TXFELVL;
+
   // Required as part of core initialization.
   // TODO: How should mode mismatch be handled? It will cause
   // the core to stop working/require reset.
@@ -645,7 +648,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
   xfer->interval = desc_edpt->bInterval;
 
-  uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4);
+  // The fifo-empty interrupt fires when the interrupt is half empty. In order
+  // to be able to write a packet at that point, the fifo must be twice the
+  // max_size.
+  uint16_t const fifo_size = tu_div_ceil(xfer->max_size * 2, 4);
 
   if(dir == TUSB_DIR_OUT)
   {
-- 
cgit v1.3.1


From 678edbe20320fe4d17437a9175ec8ff88f752ecb Mon Sep 17 00:00:00 2001
From: Michiel van Leeuwen <michiel@embeddedacoustics.com>
Date: Fri, 28 Apr 2023 11:39:39 +0200
Subject: Check correct interrupt flag

Fixes #1737
---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index bcd584953..d84014789 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -1322,7 +1322,7 @@ void dcd_int_handler(uint8_t rhport)
     do
     {
       handle_rxflvl_irq(rhport);
-    } while(dwc2->gotgint & GINTSTS_RXFLVL);
+    } while(dwc2->gintsts & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
     if (_out_ep_closed)
-- 
cgit v1.3.1


From be54870c3b2f7f1c14b0f5527f4928c8a4a4a7ae Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 10:02:24 +0200
Subject: renesas_ra: add support for HS port

---
 hw/bsp/ra/family.mk                    |  2 +
 src/portable/renesas/rusb2/dcd_rusb2.c | 76 ++++++++++++++++++++++++++++------
 src/portable/renesas/rusb2/hcd_rusb2.c | 46 ++++++++++++++------
 src/portable/renesas/rusb2/rusb2_ra.c  | 16 +++++++
 src/portable/renesas/rusb2/rusb2_ra.h  | 37 ++++++++++++++---
 5 files changed, 147 insertions(+), 30 deletions(-)
 create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c

(limited to 'src')

diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index d48272e61..3ed17f79f 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -22,6 +22,7 @@ CFLAGS += \
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
+	src/portable/renesas/rusb2/rusb2_ra.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
@@ -47,6 +48,7 @@ INC += \
 	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \
 	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \
 	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \
+	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all \
 	$(TOP)/$(FSP_MCU_DIR) \
 	$(TOP)/$(FSP_BOARD_DIR)
 
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 78584125f..9ae36e253 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -52,8 +52,10 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
 #else
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
+  #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE)
 #endif
 
 /* Start of definition of packed structs (used by the CCRX toolchain) */
@@ -81,6 +83,18 @@ typedef union TU_ATTR_PACKED {
   volatile uint16_t u16;
 } hw_fifo_t;
 
+typedef union TU_ATTR_PACKED {
+  struct {
+    volatile uint32_t  : 24;
+    volatile uint32_t u8: 8;
+  };
+  struct {
+    volatile uint32_t    : 16;
+    volatile uint32_t u16: 16;
+  };
+  volatile uint32_t u32;
+} hw_fifo32_t;
+
 typedef struct TU_ATTR_PACKED
 {
   void      *buf;      /* the start address of a transfer data buffer */
@@ -185,14 +199,18 @@ static inline void pipe_wait_for_ready(unsigned num)
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo;
+#else
   volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo;
+#endif
   uintptr_t addr = (uintptr_t)buf;
   while (len >= 2) {
     reg->u16 = *(const uint16_t *)addr;
     addr += 2;
     len  -= 2;
   }
-  if (len) {
+  if (len > 0) {
     reg->u8 = *(const uint8_t *)addr;
     ++addr;
   }
@@ -519,12 +537,17 @@ static void process_bus_reset(uint8_t rhport)
     ++ctr;
   }
   tu_varclr(&_dcd);
+
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true);
+#else
   dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+#endif
 }
 
 static void process_set_address(uint8_t rhport)
 {
-  const uint32_t addr = RUSB2->USBADDR_b.USBADDR;
+  const uint32_t addr = RUSB2->USBADDR & 0xFF;
   if (!addr) return;
   const tusb_control_request_t setup_packet = {
 #if defined(__CCRX__)
@@ -572,34 +595,53 @@ void dcd_init(uint8_t rhport)
 {
   (void)rhport;
 
-#if 0 // previously present in the rx driver before generalization
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-#endif
-
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  RUSB2->SYSCFG_b.HSE = 1;
+  RUSB2->PHYSET_b.DIRPD = 0;
+  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+  RUSB2->PHYSET_b.PLLRESET = 0;
+  //RUSB2->PHYSET_b.REPSTART = 1;
+  RUSB2->SYSCFG_b.DRPD = 0;
+  RUSB2->SYSCFG_b.USBE = 1;
+  RUSB2->LPSTS_b.SUSPENDM = 1;
+  while (!RUSB2->PLLSTA_b.PLLLOCK);
+  //RUSB2->BUSWAIT |= 0x0F00U;
+  //RUSB2->PHYSET_b.REPSEL = 1;
+  RUSB2->CFIFOSEL_b.MBW = 1;
+  RUSB2->D0FIFOSEL_b.MBW = 1;
+  RUSB2->D1FIFOSEL_b.MBW = 1;
+  RUSB2->INTSTS0 = 0;
+#else
   RUSB2->SYSCFG_b.SCKE = 1;
   while (!RUSB2->SYSCFG_b.SCKE) ;
   RUSB2->SYSCFG_b.DRPD = 0;
   RUSB2->SYSCFG_b.DCFM = 0;
   RUSB2->SYSCFG_b.USBE = 1;
+#endif
 
   // MCU specific PHY init
   rusb2_phy_init();
 
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
   RUSB2->PHYSLEW = 0x5;
   RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
 
+  #define USB_VDCEN                 (0x0080U) /* b7: Regulator ON/OFF control */
+  RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN));
+#endif
+
   /* Setup default control pipe */
   RUSB2->DCPMAXP_b.MXPS = 64;
   RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
           RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
-          RUSB2_INTSTS0_RESM_Msk;
+          RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
   RUSB2->BEMPENB = 1;
   RUSB2->BRDYENB = 1;
 
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
+  RUSB2->SYSCFG_b.DPRPU = 1;  /* necessary in this position */
+#endif
+
   if (RUSB2->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }
@@ -630,6 +672,10 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   (void)rhport;
+  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  RUSB2->SYSCFG_b.CNEN = 1;
+  R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS);
+  #endif
   RUSB2->SYSCFG_b.DPRPU = 1;
 }
 
@@ -672,6 +718,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   /* setup pipe */
   dcd_int_disable(rhport);
+  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  RUSB2->PIPEBUF = 0x7C08;
+  #endif
   RUSB2->PIPESEL = num;
   RUSB2->PIPEMAXP = mps;
   volatile uint16_t *ctr = get_pipectr(num);
@@ -826,6 +875,9 @@ void dcd_int_handler(uint8_t rhport)
       break;
     }
   }
+  if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
+    RUSB2->NRDYSTS = 0;
+  }
   if (is0 & RUSB2_INTSTS0_CTRT_Msk) {
     if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) {
       /* A setup packet has been received. */
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index e4743223e..03811d63f 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -48,8 +48,10 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
+  #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE)
 #else
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
+  #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE)
 #endif
 
 TU_ATTR_PACKED_BEGIN
@@ -477,31 +479,49 @@ bool hcd_init(uint8_t rhport)
 {
   (void)rhport;
 
-#if 0 // previously present in the rx driver before generalization
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-#endif
-
-  RUSB2->SYSCFG_b.SCKE = 1;
-  while (!RUSB2->SYSCFG_b.SCKE) ;
-  RUSB2->SYSCFG_b.DPRPU = 0;
-  RUSB2->SYSCFG_b.DRPD = 0;
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
+  RUSB2->SYSCFG_b.HSE = 1;
+  RUSB2->PHYSET_b.HSEB = 0;
+  RUSB2->PHYSET_b.DIRPD = 0;
+  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+  RUSB2->PHYSET_b.PLLRESET = 0;
+  RUSB2->LPSTS_b.SUSPENDM = 1;
+  while (!RUSB2->PLLSTA_b.PLLLOCK);
+  RUSB2->SYSCFG_b.DRPD = 1;
   RUSB2->SYSCFG_b.DCFM = 1;
+  RUSB2->SYSCFG_b.DPRPU = 0;
+  RUSB2->SYSCFG_b.CNEN = 1;
+  RUSB2->BUSWAIT |= 0x0F00U;
+  RUSB2->SOFCFG_b.INTL = 1;
+  RUSB2->DVSTCTR0_b.VBUSEN = 1;
+  RUSB2->CFIFOSEL_b.MBW = 1;
+  RUSB2->D0FIFOSEL_b.MBW = 1;
+  RUSB2->D1FIFOSEL_b.MBW = 1;
+  RUSB2->INTSTS0 = 0;
+  for (volatile int i = 0; i < 30000; ++i) ;
+  RUSB2->SYSCFG_b.USBE = 1;
+#else
+  /* HOST DEVICE Full SPEED */
+  RUSB2->SYSCFG_b.SCKE = 1;         /* USB Clock enable */
+  while (!RUSB2->SYSCFG_b.SCKE) ;
+  RUSB2->SYSCFG_b.DPRPU = 0;        /* D+ pull up enable - 0/disable in host mode */
+  RUSB2->SYSCFG_b.DRPD = 1;         /* D+/D- pull down - 1/in Host mode (pag.834)*/
+  RUSB2->SYSCFG_b.DCFM = 1;         /* HOST or Device - 1/HOST */
 
   RUSB2->DVSTCTR0_b.VBUSEN = 1;
 
   RUSB2->SYSCFG_b.DRPD = 1;
   for (volatile int i = 0; i < 30000; ++i) ;
   RUSB2->SYSCFG_b.USBE = 1;
+#endif
 
   // MCU specific PHY init
   rusb2_phy_init();
 
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)
   RUSB2->PHYSLEW = 0x5;
   RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
+#endif
 
   /* Setup default control pipe */
   RUSB2->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
new file mode 100644
index 000000000..2b6ce7b2f
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_ra.c
@@ -0,0 +1,16 @@
+#include "tusb_option.h"
+#include "rusb2_ra.h"
+
+#ifdef CFG_TUSB_RHPORT0_MODE
+IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn;
+void tud_set_irq_usbfs(IRQn_Type q) {
+  _usb_fs_irqn = q;
+}
+#endif
+
+#ifdef CFG_TUSB_RHPORT1_MODE
+IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn;
+void tud_set_irq_usbhs(IRQn_Type q) {
+  _usb_hs_irqn = q;
+}
+#endif
\ No newline at end of file
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 5785850cc..b18b506e5 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -34,18 +34,45 @@ extern "C" {
 /* renesas fsp api */
 #include "bsp_api.h"
 
-#define RUSB2_REG_BASE (0x40090000)
+extern IRQn_Type _usb_fs_irqn;
+extern IRQn_Type _usb_hs_irqn;
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_EnableIRQ(TU_IRQn);
+#ifdef CFG_TUSB_RHPORT1_MODE
+#if (CFG_TUSB_RHPORT1_MODE != 0)
+  if (rhport == 1) {
+    NVIC_EnableIRQ(_usb_hs_irqn);
+  }
+#endif
+#endif
+
+#ifdef CFG_TUSB_RHPORT0_MODE
+#if  (CFG_TUSB_RHPORT0_MODE != 0)
+  if (rhport == 0) {
+    NVIC_EnableIRQ(_usb_fs_irqn);
+  }
+#endif
+#endif
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_DisableIRQ(TU_IRQn);
+#ifdef CFG_TUSB_RHPORT1_MODE
+#if (CFG_TUSB_RHPORT1_MODE != 0)
+  if (rhport == 1) {
+    NVIC_DisableIRQ(_usb_hs_irqn);
+  }
+#endif
+#endif
+
+#ifdef CFG_TUSB_RHPORT0_MODE
+#if (CFG_TUSB_RHPORT0_MODE != 0)
+  if (rhport == 0) {
+    NVIC_DisableIRQ(_usb_fs_irqn);
+  }
+#endif
+#endif
 }
 
 // MCU specific PHY init
-- 
cgit v1.3.1


From 4afed62646d18dd96eef619d7d21b47a2422672f Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 10:05:29 +0200
Subject: renesas_ra: host: handle retry on attach()

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 03811d63f..9dd4f0a48 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -759,9 +759,10 @@ void hcd_int_handler(uint8_t rhport)
     7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
     20, 8, 19, 18};
 #endif
-
+  static unsigned char attach_attempt = 0;
   unsigned is1 = RUSB2->INTSTS1;
   unsigned is0 = RUSB2->INTSTS0;
+
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
   RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
   RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
@@ -772,12 +773,21 @@ void hcd_int_handler(uint8_t rhport)
   if (is1 & RUSB2_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
     RUSB2->DCPCTR_b.SQSET = 1;
+    attach_attempt = 0;
     hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
   if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
     hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
+    if(attach_attempt > 0) {
+      RUSB2->DVSTCTR0_b.UACT = 1;
+      _hcd.need_reset = true;
+      RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
+      hcd_event_device_attach(rhport, true);
+    }
+    attach_attempt--;
   }
   if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
+    attach_attempt = 10;
     RUSB2->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
     RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
-- 
cgit v1.3.1


From 5f7e7b4b0a9f65a401c679d5045b96b4b56755df Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 10:06:13 +0200
Subject: renesas_ra: support RA2A1 (FS only)

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9ae36e253..f3bda5205 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -41,6 +41,15 @@
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
+  #if defined(RENESAS_CORTEX_M23)
+    #define D0FIFO CFIFO
+    #define D0FIFOSEL CFIFOSEL
+    #define D0FIFOSEL_b CFIFOSEL_b
+    #define D1FIFOSEL CFIFOSEL
+    #define D1FIFOSEL_b CFIFOSEL_b
+    #define D0FIFOCTR CFIFOCTR
+    #define D0FIFOCTR_b CFIFOCTR_b
+  #endif
 #else
   #error "Unsupported MCU"
 #endif
@@ -121,6 +130,10 @@ typedef struct
 //--------------------------------------------------------------------+
 static dcd_data_t _dcd;
 
+#ifndef FIRST_BULK_PIPE
+#define FIRST_BULK_PIPE 3
+#endif
+
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -130,7 +143,7 @@ static unsigned find_pipe(unsigned xfer)
     }
     break;
   case TUSB_XFER_BULK:
-    for (int i = 3; i <= 5; ++i) {
+    for (int i = FIRST_BULK_PIPE; i <= 5; ++i) {
       if (0 == _dcd.pipe[i].ep) return  i;
     }
     for (int i = 1; i <= 1; ++i) {
-- 
cgit v1.3.1


From 6ff62c0fe85e825d077d7d803c657181769e542f Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 11:47:41 +0200
Subject: renesas: add fallback for targets not defining CFG_TUSB_RHPORT*_MODE

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 5 +++++
 src/portable/renesas/rusb2/hcd_rusb2.c | 5 +++++
 src/portable/renesas/rusb2/rusb2_ra.h  | 5 +++++
 3 files changed, 15 insertions(+)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index f3bda5205..f509dcc56 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -37,6 +37,11 @@
 #include "device/dcd.h"
 #include "rusb2_type.h"
 
+#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
+// fallback
+#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_DEVICE
+#endif
+
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 9dd4f0a48..1ec25f1e2 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -33,6 +33,11 @@
 #include "host/hcd.h"
 #include "rusb2_type.h"
 
+#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
+// fallback
+#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_HOST
+#endif
+
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index b18b506e5..874492304 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -37,6 +37,11 @@ extern "C" {
 extern IRQn_Type _usb_fs_irqn;
 extern IRQn_Type _usb_hs_irqn;
 
+#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
+// fallback
+#define CFG_TUSB_RHPORT0_MODE   ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST )
+#endif
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
 #ifdef CFG_TUSB_RHPORT1_MODE
-- 
cgit v1.3.1


From 75cf8e21a7e525eb24b7fd34fe5859cba331fcc2 Mon Sep 17 00:00:00 2001
From: Michiel van Leeuwen <michiel@embeddedacoustics.com>
Date: Thu, 4 May 2023 10:02:42 +0200
Subject: Use double-sized fifo only for IN endpoints

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index d84014789..c3d3ae085 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -648,10 +648,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
   xfer->interval = desc_edpt->bInterval;
 
-  // The fifo-empty interrupt fires when the interrupt is half empty. In order
-  // to be able to write a packet at that point, the fifo must be twice the
-  // max_size.
-  uint16_t const fifo_size = tu_div_ceil(xfer->max_size * 2, 4);
+  uint16_t fifo_size = tu_div_ceil(xfer->max_size, 4);
 
   if(dir == TUSB_DIR_OUT)
   {
@@ -697,6 +694,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // In FIFO is allocated by following rules:
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
+    // The fifo-empty interrupt fires when the interrupt is half empty. In order
+    // to be able to write a packet at that point, the fifo must be twice the
+    // max_size.
+    fifo_size = fifo_size * 2;
+
     // Check if free space is available
     TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size/4);
 
-- 
cgit v1.3.1


From 32f9f452afc4d431d51cb16a02f99d76c88f7fb9 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 17 May 2023 12:13:25 +0200
Subject: renesas: provide default for CFG_TUSB_RHPORT1_MODE

Should fix CI failure for Renesas RX family
---
 src/portable/renesas/rusb2/dcd_rusb2.c | 1 +
 src/portable/renesas/rusb2/hcd_rusb2.c | 1 +
 src/portable/renesas/rusb2/rusb2_ra.h  | 1 +
 3 files changed, 3 insertions(+)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index f509dcc56..2653d0da6 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -40,6 +40,7 @@
 #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
 // fallback
 #define CFG_TUSB_RHPORT0_MODE   OPT_MODE_DEVICE
+#define CFG_TUSB_RHPORT1_MODE   0
 #endif
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 1ec25f1e2..1e26c931d 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -36,6 +36,7 @@
 #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
 // fallback
 #define CFG_TUSB_RHPORT0_MODE   OPT_MODE_HOST
+#define CFG_TUSB_RHPORT1_MODE   0
 #endif
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 874492304..a1c58abe5 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -40,6 +40,7 @@ extern IRQn_Type _usb_hs_irqn;
 #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
 // fallback
 #define CFG_TUSB_RHPORT0_MODE   ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST )
+#define CFG_TUSB_RHPORT1_MODE   0
 #endif
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
-- 
cgit v1.3.1


From e8b7f21af6e5e994ece7c989202767732f23809e Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Thu, 1 Jun 2023 12:57:44 -0400
Subject: For FreeRTOS kernel-aware debugging, when queue registry is enabled,
 label tinyUSB queue

---
 src/osal/osal_freertos.h | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 477f64892..0b1b11589 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -169,11 +169,16 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION
-	return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
-#else
-  return xQueueCreate(qdef->depth, qdef->item_sz);
-#endif
+  osal_queue_t q;
+  #if configSUPPORT_STATIC_ALLOCATION
+    q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+  #else
+    q = xQueueCreate(qdef->depth, qdef->item_sz);
+  #endif
+  #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+    vQueueAddToRegistry(q, "tinyUSB");
+  #endif
+  return q;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-- 
cgit v1.3.1


From cdae66c8371e1c73d28279462fa8598a9daae5a7 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Mon, 5 Jun 2023 09:04:52 +0200
Subject: renesas_rx: fix compilation on latest GCC

__CCRX__ only applyes to version 4 of RX family compiler http://tool-support.renesas.com/autoupdate/support/onlinehelp/csp/V4.01.00/CS+.chm/Compiler-CCRX.chm/Output/ccrx04c0201y.html

__RX__ is one of the macros exported by latest gcc (gcc_8.3.0.202305_rx_elf)
---
 src/portable/renesas/rusb2/dcd_rusb2.c | 2 ++
 src/portable/renesas/rusb2/hcd_rusb2.c | 2 ++
 2 files changed, 4 insertions(+)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 2653d0da6..e9ac46517 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -67,6 +67,8 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif defined(__RX__)
+  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
 #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
   #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
 #else
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 1e26c931d..b97ffd7e9 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -54,6 +54,8 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif defined(__RX__)
+  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
 #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
   #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE)
 #else
-- 
cgit v1.3.1


From 2b735ee8f5476168d6b5ed1dc32edc52f4d3648a Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Mon, 5 Jun 2023 09:31:58 +0200
Subject: renesas_ra: fix wrong ifdef

Since CFG_TUSB_RHPORT1_MODE is always defined now for backwards compatibility
---
 src/portable/renesas/rusb2/rusb2_ra.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
index 2b6ce7b2f..ff2191b1f 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.c
+++ b/src/portable/renesas/rusb2/rusb2_ra.c
@@ -1,16 +1,16 @@
 #include "tusb_option.h"
 #include "rusb2_ra.h"
 
-#ifdef CFG_TUSB_RHPORT0_MODE
+#if (CFG_TUSB_RHPORT0_MODE != 0)
 IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn;
 void tud_set_irq_usbfs(IRQn_Type q) {
   _usb_fs_irqn = q;
 }
 #endif
 
-#ifdef CFG_TUSB_RHPORT1_MODE
+#if (CFG_TUSB_RHPORT1_MODE != 0)
 IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn;
 void tud_set_irq_usbhs(IRQn_Type q) {
   _usb_hs_irqn = q;
 }
-#endif
\ No newline at end of file
+#endif
-- 
cgit v1.3.1


From 11fba59319d81fb9502fbf399abb4fe27cf3fa29 Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Wed, 28 Jun 2023 17:25:22 -0400
Subject: Name queues for easier FreeRTOS debugging with task- and queue-aware
 debuggers

---
 src/device/usbd.c        | 4 ++--
 src/host/usbh.c          | 4 ++--
 src/osal/osal_freertos.h | 5 +++--
 3 files changed, 7 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 44c2530ce..b6c679b22 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -279,7 +279,7 @@ tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
+OSAL_QUEUE_DEF(usbd_int_set, usbd_events, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
 tu_static osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
@@ -410,7 +410,7 @@ bool tud_init (uint8_t rhport)
 #endif
 
   // Init device queue & task
-  _usbd_q = osal_queue_create(&_usbd_qdef);
+  _usbd_q = osal_queue_create(&usbd_events);
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
diff --git a/src/host/usbh.c b/src/host/usbh.c
index f3e9d3858..987ff7a6e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -219,7 +219,7 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
 // Event queue
 // usbh_int_set is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
+OSAL_QUEUE_DEF(usbh_int_set, usbh_events, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
 CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
@@ -330,7 +330,7 @@ bool tuh_init(uint8_t controller_id)
   TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t));
 
   // Event queue
-  _usbh_q = osal_queue_create( &_usbh_qdef );
+  _usbh_q = osal_queue_create( &usbh_events );
   TU_ASSERT(_usbh_q != NULL);
 
 #if OSAL_MUTEX_REQUIRED
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 0b1b11589..e83277eb3 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -56,7 +56,7 @@ typedef SemaphoreHandle_t osal_mutex_t;
 // _int_set is not used with an RTOS
 #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
   static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .pQueueName = #_name };
 
 typedef struct
 {
@@ -66,6 +66,7 @@ typedef struct
 #if configSUPPORT_STATIC_ALLOCATION
   StaticQueue_t sq;
 #endif
+  const char* pQueueName;
 }osal_queue_def_t;
 
 typedef QueueHandle_t osal_queue_t;
@@ -176,7 +177,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
     q = xQueueCreate(qdef->depth, qdef->item_sz);
   #endif
   #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
-    vQueueAddToRegistry(q, "tinyUSB");
+    vQueueAddToRegistry(q, qdef->pQueueName);
   #endif
   return q;
 }
-- 
cgit v1.3.1


From 0693462ebad20338de78aeb93d60d6c3c73a6ca7 Mon Sep 17 00:00:00 2001
From: Lars Pötter <kontakt@ing-poetter.de>
Date: Sun, 2 Jul 2023 09:02:24 +0200
Subject: made line ends consistent.

---
 src/class/cdc/cdc_host.c                     |  4 ++--
 src/class/video/video_device.c               | 16 +++++++-------
 src/common/tusb_fifo.c                       |  2 +-
 src/portable/dialog/da146xx/dcd_da146xx.c    |  2 +-
 src/portable/mentor/musb/dcd_musb.c          | 30 +++++++++++++-------------
 src/portable/mentor/musb/hcd_musb.c          |  8 +++----
 src/portable/nxp/khci/hcd_khci.c             | 16 +++++++-------
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  4 ++--
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  4 ++--
 src/portable/renesas/rusb2/hcd_rusb2.c       |  8 +++----
 src/portable/st/typec/typec_stm32.c          | 18 ++++++++--------
 src/portable/sunxi/dcd_sunxi_musb.c          | 32 ++++++++++++++--------------
 12 files changed, 72 insertions(+), 72 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ce9f27c33..e1af8d801 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -973,7 +973,7 @@ static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
-  TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor);
+  TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
   _ftdi_requested_baud = baudrate;
@@ -1108,7 +1108,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
 }
 
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\n", baudrate);
+  TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 91f452afc..16eae0ced 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -609,17 +609,17 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
-  TU_LOG2("    open VC %d\n", altnum);
+  TU_LOG2("    open VC %d\r\n", altnum);
   uint8_t const *beg = self->beg;
   uint8_t const *end = beg + self->len;
 
   /* The first descriptor is a video control interface descriptor. */
   uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
-  TU_LOG2("    cur %d\n", cur - beg);
+  TU_LOG2("    cur %d\r\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
-  TU_LOG2("    bInCollection %d\n", vc->ctl.bInCollection);
+  TU_LOG2("    bInCollection %d\r\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
@@ -628,7 +628,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
 
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
-  TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
+  TU_LOG2("    bNumEndpoints %d\r\n", vc->std.bNumEndpoints);
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
@@ -662,7 +662,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm)
 static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
   uint_fast8_t i;
-  TU_LOG2("    reopen VS %d\n", altnum);
+  TU_LOG2("    reopen VS %d\r\n", altnum);
   uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
@@ -672,7 +672,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     uint8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
     usbd_edpt_close(rhport, ep_adr);
     stm->desc.ep[i] = 0;
-    TU_LOG2("    close EP%02x\n", ep_adr);
+    TU_LOG2("    close EP%02x\r\n", ep_adr);
   }
 
   /* clear transfer management information */
@@ -709,12 +709,12 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     }
     TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
-    TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
+    TU_LOG2("    open EP%02x\r\n", _desc_ep_addr(cur));
   }
   if (altnum) {
     stm->state = VS_STATE_STREAMING;
   }
-  TU_LOG2("    done\n");
+  TU_LOG2("    done\r\n");
   return true;
 }
 
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index a52c92267..d6c3db4ce 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -539,7 +539,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
     // Advance index
     f->wr_idx = advance_index(f->depth, wr_idx, n);
 
-    TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx);
+    TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\r\n", f->wr_idx);
   }
 
   _ff_unlock(f->mutex_wr);
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 961da81d6..d1e85c2df 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -651,7 +651,7 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer)
   }
   if (txs & USB_USB_TXS1_REG_USB_TX_URUN_Msk)
   {
-    TU_LOG1("EP %d FIFO underrun\n", epnum);
+    TU_LOG1("EP %d FIFO underrun\r\n", epnum);
   }
   // Start next or repeated packet.
   start_tx_packet(xfer);
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 487761847..3c0114e41 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -317,7 +317,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
   const unsigned mps = regs->TXMAXP;
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
-  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  // TU_LOG1("   %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
   if (len) {
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
       pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN);
@@ -328,7 +328,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
     pipe->remaining = rem - len;
   }
   regs->TXCSRL = USB_TXCSRL1_TXRDY;
-  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
   return false;
 }
 
@@ -337,7 +337,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
   unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
   volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
-  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL);
 
   TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
 
@@ -399,14 +399,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
      * may have already finished and received the next setup packet
      * without calling this function, so we have no choice but to
      * invoke the callback function of status packet here. */
-    // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+    // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0);
     _dcd.status_out = 0;
     if (req == REQUEST_TYPE_INVALID) {
       dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
     } else {
       /* The next setup packet has already been received, it aborts
        * invoking callback function to avoid confusing TUSB stack. */
-      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+      TU_LOG1("Drop CONTROL_STAGE_ACK\r\n");
     }
     return true;
   }
@@ -431,16 +431,16 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
       } else {
         USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
       }
-      // TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+      // TU_LOG1(" IN USB0->CSRL0 = %x\r\n", USB0->CSRL0);
     } else {
-      // TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+      // TU_LOG1(" OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0);
       _dcd.pipe0.buf       = buffer;
       _dcd.pipe0.length    = len;
       _dcd.pipe0.remaining = len;
       USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
     }
   } else if (dir_in) {
-    // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+    // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\r\n", USB0->CSRL0);
     _dcd.pipe0.buf = NULL;
     _dcd.pipe0.length    = 0;
     _dcd.pipe0.remaining = 0;
@@ -454,7 +454,7 @@ static void process_ep0(uint8_t rhport)
 {
   uint_fast8_t csrl = USB0->CSRL0;
 
-  // TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl);
+  // TU_LOG1(" EP0 USB0->CSRL0 = %x\r\n", csrl);
 
   if (csrl & USB_CSRL0_STALLED) {
     /* Returned STALL packet to HOST. */
@@ -464,7 +464,7 @@ static void process_ep0(uint8_t rhport)
 
   unsigned req = _dcd.setup_packet.bmRequestType;
   if (csrl & USB_CSRL0_SETEND) {
-    TU_LOG1("   ABORT by the next packets\n");
+    TU_LOG1("   ABORT by the next packets\r\n");
     USB0->CSRL0 = USB_CSRL0_SETENDC;
     if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
       /* DATA stage was aborted by receiving STATUS or SETUP packet. */
@@ -539,14 +539,14 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
 
   volatile hw_endpoint_t *regs = edpt_regs(epn_minus1);
   if (dir_in) {
-    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
+    // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL);
     if (regs->TXCSRL & USB_TXCSRL1_STALLED) {
       regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN);
       return;
     }
     completed = handle_xfer_in(ep_addr);
   } else {
-    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
+    // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL);
     if (regs->RXCSRL & USB_RXCSRL1_STALLED) {
       regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER);
       return;
@@ -789,7 +789,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
@@ -807,7 +807,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   TU_ASSERT(epnum);
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
@@ -869,7 +869,7 @@ void dcd_int_handler(uint8_t rhport)
   is   = USB0->IS;   /* read and clear interrupt status */
   txis = USB0->TXIS; /* read and clear interrupt status */
   rxis = USB0->RXIS; /* read and clear interrupt status */
-  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+  // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
 
   is &= USB0->IE; /* Clear disabled interrupts */
   if (is & USB_IS_DISCON) {
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 9eb2e005e..7e67b8291 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -418,7 +418,7 @@ static void process_ep0(uint8_t rhport)
   (void)rhport;
 
   uint_fast8_t csrl = USB0->CSRL0;
-  // TU_LOG1(" EP0 CSRL = %x\n", csrl);
+  // TU_LOG1(" EP0 CSRL = %x\r\n", csrl);
 
   unsigned const dev_addr = USB0->TXFUNCADDR0;
   unsigned const req = _hcd.bmRequestType;
@@ -508,7 +508,7 @@ static void process_pipe_tx(uint8_t rhport, uint_fast8_t pipenum)
 
   volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
   unsigned const csrl = regs->TXCSRL;
-  // TU_LOG1(" TXCSRL%d = %x\n", pipenum, csrl);
+  // TU_LOG1(" TXCSRL%d = %x\r\n", pipenum, csrl);
   if (csrl & (USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) {
     if (csrl & USB_TXCSRL1_TXRDY)
       regs->TXCSRL = (csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) | USB_TXCSRL1_FLUSH;
@@ -537,7 +537,7 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum)
 
   volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
   unsigned const csrl = regs->RXCSRL;
-  // TU_LOG1(" RXCSRL%d = %x\n", pipenum, csrl);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", pipenum, csrl);
   if (csrl & (USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) {
     if (csrl & USB_RXCSRL1_RXRDY)
       regs->RXCSRL = (csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) | USB_RXCSRL1_FLUSH;
@@ -846,7 +846,7 @@ void hcd_int_handler(uint8_t rhport)
   is   = USB0->IS;   /* read and clear interrupt status */
   txis = USB0->TXIS; /* read and clear interrupt status */
   rxis = USB0->RXIS; /* read and clear interrupt status */
-  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+  // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
 
   is &= USB0->IE; /* Clear disabled interrupts */
   if (is & USB_IS_RESUME) {
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index f6029ee0d..fb978cac8 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -161,7 +161,7 @@ static int prepare_packets(int pipenum)
   buffer_descriptor_t *bd = _hcd.bdt[dir_tx];
   TU_ASSERT(0 == bd[odd].own, -1);
 
-  // TU_LOG1("  %p dir %d odd %d data %d\n", &bd[odd], dir_tx, odd, pipe->data);
+  // TU_LOG1("  %p dir %d odd %d data %d\r\n", &bd[odd], dir_tx, odd, pipe->data);
 
   ep->pipenum = pipenum;
 
@@ -251,7 +251,7 @@ static bool resume_transfer(int pipenum)
     flags |= USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPCTLDIS_MASK | USB_ENDPT_RETRYDIS_MASK;
     break;
   }
-  // TU_LOG1("  resume pipenum %d flags %x\n", pipenum, flags);
+  // TU_LOG1("  resume pipenum %d flags %x\r\n", pipenum, flags);
 
   KHCI->ENDPOINT[0].ENDPT = flags;
   KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | pipe->dev_addr;
@@ -302,7 +302,7 @@ static void process_tokdne(uint8_t rhport)
 
   int pipenum = ep->pipenum;
   int next_pipenum;
-  // TU_LOG1("TOKDNE %x PID %x pipe %d\n", s, pid, pipenum);
+  // TU_LOG1("TOKDNE %x PID %x pipe %d\r\n", s, pid, pipenum);
 
   xfer_result_t result;
   switch (pid) {
@@ -479,7 +479,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  // TU_LOG1("SETUP %u\n", dev_addr);
+  // TU_LOG1("SETUP %u\r\n", dev_addr);
   TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(0)));
 
   int pipenum = find_pipe(dev_addr, 0);
@@ -510,7 +510,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 {
   (void)rhport;
   uint8_t const ep_addr = ep_desc->bEndpointAddress;
-  // TU_LOG1("O %u %x\n", dev_addr, ep_addr);
+  // TU_LOG1("O %u %x\r\n", dev_addr, ep_addr);
   /* Find a free pipe */
   pipe_state_t *p = &_hcd.pipe[0];
   pipe_state_t *end = &_hcd.pipe[CFG_TUH_ENDPOINT_MAX * 2];
@@ -543,7 +543,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   (void)rhport;
-  // TU_LOG1("X %u %x %x %d\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen);
+  // TU_LOG1("X %u %x %x %d\r\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen);
 
   int pipenum = find_pipe(dev_addr, ep_addr);
   TU_ASSERT(0 <= pipenum);
@@ -580,7 +580,7 @@ void hcd_int_handler(uint8_t rhport)
   uint32_t is  = KHCI->ISTAT;
   uint32_t msk = KHCI->INTEN;
 
-  // TU_LOG1("S %lx\n", is);
+  // TU_LOG1("S %lx\r\n", is);
 
   /* clear disabled interrupts */
   KHCI->ISTAT = (is & ~msk & ~USB_ISTAT_TOKDNE_MASK) | USB_ISTAT_SOFTOK_MASK;
@@ -589,7 +589,7 @@ void hcd_int_handler(uint8_t rhport)
   if (is & USB_ISTAT_ERROR_MASK) {
     unsigned err = KHCI->ERRSTAT;
     if (err) {
-      TU_LOG1(" ERR %x\n", err);
+      TU_LOG1(" ERR %x\r\n", err);
       KHCI->ERRSTAT = err;
     } else {
       KHCI->INTEN &= ~USB_ISTAT_ERROR_MASK;
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 02f9968a7..51b8bf72d 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -219,7 +219,7 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   if ( status & USB_INTS_BUFF_STATUS_BITS )
   {
     handled |= USB_INTS_BUFF_STATUS_BITS;
-    TU_LOG(2, "Buffer complete\n");
+    TU_LOG(2, "Buffer complete\r\n");
     hw_handle_buff_status();
   }
 
@@ -227,7 +227,7 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   {
     handled |= USB_INTS_TRANS_COMPLETE_BITS;
     usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
-    TU_LOG(2, "Transfer complete\n");
+    TU_LOG(2, "Transfer complete\r\n");
     hw_trans_complete();
   }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 1f49665ff..53486a586 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -219,7 +219,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   if ( ep->active )
   {
     // TODO: Is this acceptable for interrupt packets?
-    TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr),
+    TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\r\n", tu_edpt_number(ep->ep_addr),
               ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
     hw_endpoint_reset_transfer(ep);
@@ -419,7 +419,7 @@ static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoi
   if (delta < 800 || delta > 998) {
     return false;
   }
-  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
+  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
   return true;
 }
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 0e6fa1618..886a6f6b8 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -409,7 +409,7 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
   (void)rhport;
   xfer_result_t result;
   uint16_t volatile *ctr = get_pipectr(num);
-  // TU_LOG1("NRDY %d %x\n", num, *ctr);
+  // TU_LOG1("NRDY %d %x\r\n", num, *ctr);
   switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
     default: return;
     case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
@@ -608,7 +608,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  //  TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR);
+  //  TU_LOG1("S %d %x\r\n", dev_addr, RUSB2->DCPCTR);
 
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
   TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ);
@@ -701,7 +701,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
 {
   bool r;
   hcd_int_disable(rhport);
-  // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen);
+  // TU_LOG1("X %d %x %u\r\n", dev_addr, ep_addr, buflen);
   r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen);
   hcd_int_enable(rhport);
   return r;
@@ -745,7 +745,7 @@ void hcd_int_handler(uint8_t rhport)
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
   RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
   RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
-  // TU_LOG1("IS %04x %04x\n", is0, is1);
+  // TU_LOG1("IS %04x %04x\r\n", is0, is1);
   is1 &= RUSB2->INTENB1;
   is0 &= RUSB2->INTENB0;
 
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index bf8b660f0..8da2e39ba 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -246,7 +246,7 @@ void tcd_int_handler(uint8_t rhport) {
     v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
     v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
 
-    TU_LOG3("VState CC1 = %lu, CC2 = %lu\n", v_cc[0], v_cc[1]);
+    TU_LOG3("VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]);
 
     uint32_t cr = UCPD1->CR;
 
@@ -255,15 +255,15 @@ void tcd_int_handler(uint8_t rhport) {
     // FIXME somehow CC2 is vstate is not correct, always 1 even not attached.
     // on DPOW1 board, it is connected to PA10 (USBPD_DBCC2), we probably miss something.
     if ((sr & UCPD_SR_TYPECEVT1) && (v_cc[0] == 3)) {
-      TU_LOG3("Attach CC1\n");
+      TU_LOG3("Attach CC1\r\n");
       cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
       cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
     } else if ((sr & UCPD_SR_TYPECEVT2) && (v_cc[1] == 3)) {
-      TU_LOG3("Attach CC2\n");
+      TU_LOG3("Attach CC2\r\n");
       cr &= ~UCPD_CR_CCENABLE;
       cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
     } else {
-      TU_LOG3("Detach\n");
+      TU_LOG3("Detach\r\n");
       cr &= ~UCPD_CR_PHYRXEN;
       cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
     }
@@ -290,7 +290,7 @@ void tcd_int_handler(uint8_t rhport) {
   //------------- RX -------------//
   if (sr & UCPD_SR_RXORDDET) {
     // SOP: Start of Packet.
-    TU_LOG3("SOP\n");
+    TU_LOG3("SOP\r\n");
     // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
 
     // ack
@@ -299,7 +299,7 @@ void tcd_int_handler(uint8_t rhport) {
 
   // Received full message
   if (sr & UCPD_SR_RXMSGEND) {
-    TU_LOG3("RX MSG END\n");
+    TU_LOG3("RX MSG END\r\n");
 
     // stop TX
     dma_stop(rhport, true);
@@ -328,7 +328,7 @@ void tcd_int_handler(uint8_t rhport) {
   }
 
   if (sr & UCPD_SR_RXOVR) {
-    TU_LOG3("RXOVR\n");
+    TU_LOG3("RXOVR\r\n");
     // ack
     UCPD1->ICR = UCPD_ICR_RXOVRCF;
   }
@@ -343,12 +343,12 @@ void tcd_int_handler(uint8_t rhport) {
     uint8_t result;
 
     if ( sr & UCPD_SR_TXMSGSENT ) {
-      TU_LOG3("TX MSG SENT\n");
+      TU_LOG3("TX MSG SENT\r\n");
       result = XFER_RESULT_SUCCESS;
       // ack
       UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
     }else {
-      TU_LOG3("TX Error\n");
+      TU_LOG3("TX Error\r\n");
       result = XFER_RESULT_FAILED;
       // ack
       UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index e26be775d..6cc1975a8 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -408,9 +408,9 @@ static inline unsigned free_block_size(free_block_t const *blk)
 #if 0
 static inline void print_block_list(free_block_t const *blk, unsigned num)
 {
-  TU_LOG1("*************\n");
+  TU_LOG1("*************\r\n");
   for (unsigned i = 0; i < num; ++i) {
-    TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
+    TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end);
     ++blk;
   }
 }
@@ -590,7 +590,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
   const unsigned mps = USBC_Readw(USBC_REG_TXMAXP(USBC0_BASE));
   const unsigned len = TU_MIN(mps, rem);
   uint8_t          *buf = pipe->buf;
-  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  // TU_LOG1("   %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
   if (len) {
     volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
@@ -602,7 +602,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
     pipe->remaining = rem - len;
   }
   __USBC_Dev_Tx_WriteDataComplete();
-  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
   return false;
 }
 
@@ -610,7 +610,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
 {
   unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
-  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL);
 
   TU_ASSERT(__USBC_Dev_Rx_IsReadDataReady());
 
@@ -677,14 +677,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
      * may have already finished and received the next setup packet
      * without calling this function, so we have no choice but to
      * invoke the callback function of status packet here. */
-    // TU_LOG1(" STATUS OUT CSRL0 = %x\n", CSRL0);
+    // TU_LOG1(" STATUS OUT CSRL0 = %x\r\n", CSRL0);
     _dcd.status_out = 0;
     if (req == REQUEST_TYPE_INVALID) {
       dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
     } else {
       /* The next setup packet has already been received, it aborts
        * invoking callback function to avoid confusing TUSB stack. */
-      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+      TU_LOG1("Drop CONTROL_STAGE_ACK\r\n");
     }
     return true;
   }
@@ -709,16 +709,16 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
       } else {
         __USBC_Dev_ep0_WriteDataHalf();
       }
-      // TU_LOG1(" IN CSRL0 = %x\n", CSRL0);
+      // TU_LOG1(" IN CSRL0 = %x\r\n", CSRL0);
     } else {
-      // TU_LOG1(" OUT CSRL0 = %x\n", CSRL0);
+      // TU_LOG1(" OUT CSRL0 = %x\r\n", CSRL0);
       _dcd.pipe0.buf       = buffer;
       _dcd.pipe0.length    = len;
       _dcd.pipe0.remaining = len;
       __USBC_Dev_ep0_ReadDataHalf();
     }
   } else if (dir_in) {
-    // TU_LOG1(" STATUS IN CSRL0 = %x\n", CSRL0);
+    // TU_LOG1(" STATUS IN CSRL0 = %x\r\n", CSRL0);
     _dcd.pipe0.buf = NULL;
     _dcd.pipe0.length    = 0;
     _dcd.pipe0.remaining = 0;
@@ -733,7 +733,7 @@ static void process_ep0(uint8_t rhport)
   USBC_SelectActiveEp(0);
   uint_fast8_t csrl = USBC_Readw(USBC_REG_CSR0(USBC0_BASE));
 
-  // TU_LOG1(" EP0 CSRL0 = %x\n", csrl);
+  // TU_LOG1(" EP0 CSRL0 = %x\r\n", csrl);
 
   if (csrl & USB_CSRL0_STALLED) {
     /* Returned STALL packet to HOST. */
@@ -743,7 +743,7 @@ static void process_ep0(uint8_t rhport)
 
   unsigned req = _dcd.setup_packet.bmRequestType;
   if (csrl & USB_CSRL0_SETEND) {
-    // TU_LOG1("   ABORT by the next packets\n");
+    // TU_LOG1("   ABORT by the next packets\r\n");
     USBC_Dev_Ctrl_ClearSetupEnd();
     if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
       /* DATA stage was aborted by receiving STATUS or SETUP packet. */
@@ -819,14 +819,14 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
   USBC_SelectActiveEp(epn);
 
   if (dir_in) {
-    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
+    // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL);
     if (__USBC_Dev_Tx_IsEpStall()) {
 	  __USBC_Dev_Tx_ClearStall();
       return;
     }
     completed = handle_xfer_in(ep_addr);
   } else {
-    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
+    // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL);
     if (__USBC_Dev_Rx_IsEpStall()) {
 	    __USBC_Dev_Rx_ClearStall();
       return;
@@ -1092,7 +1092,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   musb_int_mask();
 
@@ -1111,7 +1111,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   TU_ASSERT(epnum);
 
-- 
cgit v1.3.1


From 2029ca9536e7e889f0f420218136e7bd1ac091fc Mon Sep 17 00:00:00 2001
From: Lars Pötter <kontakt@ing-poetter.de>
Date: Sun, 2 Jul 2023 10:53:08 +0200
Subject: also fixed pico_trac() log messages.

---
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 4 ++--
 src/portable/raspberrypi/rp2040/dcd_rp2040.c   | 6 +++---
 src/portable/raspberrypi/rp2040/rp2040_usb.c   | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 264af2e7a..130716da4 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -150,11 +150,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 //    // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
 //    // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
 //    // on that device
-//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
+//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\r\n", dev_addr, ep_addr);
 //    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
 //    assert(ep);
 //    bool busy = ep->active;
-//    pico_trace("busy == %d\n", busy);
+//    pico_trace("busy == %d\r\n", busy);
 //    return busy;
 //}
 
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 479b17b67..e8cee73fd 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -189,7 +189,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by
 static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status = 0x%08lx\n", remaining_buffers);
+    pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers);
     uint bit = 1u;
     for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
     {
@@ -331,7 +331,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
   // SE0 for 2.5 us or more (will last at least 10ms)
   if ( status & USB_INTS_BUS_RESET_BITS )
   {
-    pico_trace("BUS RESET\n");
+    pico_trace("BUS RESET\r\n");
 
     handled |= USB_INTS_BUS_RESET_BITS;
 
@@ -565,7 +565,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
     (void) rhport;
 
-    pico_trace("dcd_edpt_close %02x\n", ep_addr);
+    pico_trace("dcd_edpt_close %02x\r\n", ep_addr);
     hw_endpoint_close(ep_addr);
 }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 53486a586..a512dc34f 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -276,7 +276,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uin
   // Short packet
   if (xferred_bytes < ep->wMaxPacketSize)
   {
-    pico_trace("  Short packet on buffer %d with %u bytes\n", buf_id, xferred_bytes);
+    pico_trace("  Short packet on buffer %d with %u bytes\r\n", buf_id, xferred_bytes);
     // Reduce total length as this is last packet
     ep->remaining_len = 0;
   }
@@ -352,7 +352,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
   // If we are done then notify tinyusb
   if (ep->remaining_len == 0)
   {
-    pico_trace("Completed transfer of %d bytes on ep %d %s\n",
+    pico_trace("Completed transfer of %d bytes on ep %d %s\r\n",
                ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
     // Notify caller we are done so it can notify the tinyusb stack
     hw_endpoint_lock_update(ep, -1);
-- 
cgit v1.3.1


From f79529c09c6e7c0d6ee5586633ceb8c83e345406 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Jul 2023 17:13:01 +0700
Subject: usb hs work with ra 6m5 ek

---
 .idea/runConfigurations/ra4m1.xml               |  10 ++
 .idea/runConfigurations/ra6m1.xml               |  10 ++
 .idea/runConfigurations/ra6m5.xml               |  10 ++
 hw/bsp/ra/board_cfg.h                           |  45 +++++++++
 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h |   4 +-
 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h |   4 +-
 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h |   4 +-
 hw/bsp/ra/boards/ra6m5_ek/board.cmake           |  20 +++-
 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h |   4 +-
 hw/bsp/ra/family.c                              | 118 ++++++++++++++++--------
 hw/bsp/ra/vector_data.h                         |  15 ++-
 src/common/tusb_mcu.h                           |   1 +
 src/portable/renesas/rusb2/dcd_rusb2.c          |   3 +-
 13 files changed, 188 insertions(+), 60 deletions(-)
 create mode 100644 .idea/runConfigurations/ra4m1.xml
 create mode 100644 .idea/runConfigurations/ra6m1.xml
 create mode 100644 .idea/runConfigurations/ra6m5.xml
 create mode 100644 hw/bsp/ra/board_cfg.h

(limited to 'src')

diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
new file mode 100644
index 000000000..22bb61949
--- /dev/null
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
new file mode 100644
index 000000000..438ac4063
--- /dev/null
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
new file mode 100644
index 000000000..02df11610
--- /dev/null
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h
new file mode 100644
index 000000000..baed46b5f
--- /dev/null
+++ b/hw/bsp/ra/board_cfg.h
@@ -0,0 +1,45 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _BOARD_CFG_H
+#define _BOARD_CFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+  #define BOARD_HAS_USB_HIGHSPEED
+#endif
+
+// for SystemInit()
+void bsp_init(void * p_args);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
index 19bb473eb..f0577b702 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -4,6 +4,7 @@
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #undef RA_NOT_DEFINED
 #define BSP_CFG_RTOS (0)
@@ -31,7 +32,4 @@
 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
index 6a47bccc6..47de7747d 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -7,6 +7,7 @@ extern "C" {
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #define RA_NOT_DEFINED 0
 #ifndef BSP_CFG_RTOS
@@ -56,9 +57,6 @@ extern "C" {
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
index 75a331fc2..b5ed53a3b 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -8,6 +8,7 @@ extern "C" {
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #define RA_NOT_DEFINED 0
 #ifndef BSP_CFG_RTOS
@@ -60,9 +61,6 @@ extern "C" {
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
index 42a4c7417..d934a0c0d 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -3,8 +3,22 @@ set(MCU_VARIANT ra6m5)
 
 set(JLINK_DEVICE R7FA6M5BH)
 
+# default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+set(PORT 1)
+endif()
+
 function(update_board TARGET)
-#  target_compile_definitions(${TARGET} PUBLIC)
-#  target_sources(${TARGET} PRIVATE)
-#  target_include_directories(${BOARD_TARGET} PUBLIC)
+  target_compile_definitions(${TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    )
+
+  if (PORT STREQUAL 1)
+    target_compile_definitions(${TARGET} PUBLIC
+      CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED
+      CFG_TUSB_RHPORT0_MODE=0
+      )
+  endif ()
 endfunction()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
index e41f603ad..a41536eda 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -7,6 +7,7 @@ extern "C" {
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #define RA_NOT_DEFINED 0
 #ifndef BSP_CFG_RTOS
@@ -56,9 +57,6 @@ extern "C" {
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 769678954..36b46beab 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -48,9 +48,9 @@
 #include "board.h"
 
 /* Key code for writing PRCR register. */
-#define BSP_PRV_PRCR_KEY	       (0xA500U)
+#define BSP_PRV_PRCR_KEY         (0xA500U)
 #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
-#define BSP_PRV_PRCR_LOCK	       ((BSP_PRV_PRCR_KEY) | 0x0U)
+#define BSP_PRV_PRCR_LOCK         ((BSP_PRV_PRCR_KEY) | 0x0U)
 
 static const ioport_cfg_t family_pin_cfg = {
     .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
@@ -62,25 +62,38 @@ static ioport_instance_ctrl_t port_ctrl;
 // Vector Data
 //--------------------------------------------------------------------+
 
-BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+BSP_DONT_REMOVE BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS)
+const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = {
     [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
     [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
     [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
     [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+    [4] = usbhs_interrupt_handler, /* USBHS INT (USBHS interrupt) */
+    [5] = usbhs_d0fifo_handler,    /* USBHS FIFO 0 (DMA transfer request 0) */
+    [6] = usbhs_d1fifo_handler,    /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
 };
+
 const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
-    [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
-    [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
-    [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
-    [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
+    [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),            /* USBFS INT (USBFS interrupt) */
+    [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME),         /* USBFS RESUME (USBFS resume interrupt) */
+    [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0),         /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1),         /* USBFS FIFO 1 (DMA transfer request 1) */
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+    [4] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME), /* USBHS USB INT RESUME (USBHS interrupt) */
+    [5] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0),         /* USBHS FIFO 0 (DMA transfer request 0) */
+    [6] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1),         /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
 };
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_init(void)
-{
+void board_init(void) {
   /* Configure pins. */
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
@@ -94,8 +107,8 @@ void board_init(void)
   // Enable USB module
   R_MSTP->MSTPCRB &= ~(1U << 11U); // FS
 
-#ifdef R_USB_HS0_BASE
-//  R_MSTP->MSTPCRB &= ~(1U << 12U); // HS
+#ifdef BOARD_HAS_USB_HIGHSPEED
+  R_MSTP->MSTPCRB &= ~(1U << 12U);
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
@@ -145,66 +158,93 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void usbfs_interrupt_handler(void)
-{
+
+#if CFG_TUD_ENABLED && defined(BOARD_TUD_RHPORT)
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#if CFG_TUH_ENABLED && defined(BOARD_TUH_RHPORT)
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
+//------------- USB0 FullSpeed -------------//
+void usbfs_interrupt_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUH_ENABLED
+  #if PORT_SUPPORT_HOST(0)
   tuh_int_handler(0);
-#endif
+  #endif
 
-#if CFG_TUD_ENABLED
+  #if PORT_SUPPORT_DEVICE(0)
   tud_int_handler(0);
-#endif
+  #endif
 }
 
-void usbfs_resume_handler(void)
-{
+void usbfs_resume_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUH_ENABLED
+  #if PORT_SUPPORT_HOST(0)
   tuh_int_handler(0);
-#endif
+  #endif
 
-#if CFG_TUD_ENABLED
+  #if PORT_SUPPORT_DEVICE(0)
   tud_int_handler(0);
-#endif
+  #endif
 }
 
-void usbfs_d0fifo_handler(void)
-{
+void usbfs_d0fifo_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
 
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
+void usbfs_d1fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
 
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
-#endif
+//------------- USB1 HighSpeed -------------//
+#ifdef BOARD_HAS_USB_HIGHSPEED
+
+void usbhs_interrupt_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+  #if PORT_SUPPORT_HOST(1)
+  tuh_int_handler(1);
+  #endif
+
+  #if PORT_SUPPORT_DEVICE(1)
+  tud_int_handler(1);
+  #endif
 }
 
-void usbfs_d1fifo_handler(void)
-{
+void usbhs_d0fifo_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
 
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
+void usbhs_d1fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
 
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
 #endif
-}
 
 //--------------------------------------------------------------------+
 // stdlib
diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h
index 3d8a24634..ca667faa3 100644
--- a/hw/bsp/ra/vector_data.h
+++ b/hw/bsp/ra/vector_data.h
@@ -6,22 +6,29 @@
 extern "C" {
 #endif
 
-#ifndef VECTOR_DATA_IRQ_COUNT
-  #define VECTOR_DATA_IRQ_COUNT 4
-#endif
-
 /* ISR prototypes */
 void usbfs_interrupt_handler(void);
 void usbfs_resume_handler(void);
 void usbfs_d0fifo_handler(void);
 void usbfs_d1fifo_handler(void);
 
+#ifdef BOARD_HAS_USB_HIGHSPEED
+void usbhs_interrupt_handler(void);
+void usbhs_d0fifo_handler(void);
+void usbhs_d1fifo_handler(void);
+#endif
+
 /* Vector table allocations */
 #define USBFS_INT_IRQn    0
 #define USBFS_RESUME_IRQn 1
 #define USBFS_FIFO_0_IRQn 2
 #define USBFS_FIFO_1_IRQn 3
 
+#define USBHS_USB_INT_RESUME_IRQn  4 /* USBHS USB INT RESUME (USBHS interrupt) */
+#define USBHS_FIFO_0_IRQn          5 /* USBHS FIFO 0 (DMA transfer request 0) */
+#define USBHS_FIFO_1_IRQn          6 /* USBHS FIFO 1 (DMA transfer request 1) */
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 9f3be78fd..496ebfc85 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -327,6 +327,7 @@
 // Renesas
 //--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX)
+  #define TUP_USBIP_RUSB2
   #define TUP_DCD_ENDPOINT_MAX    10
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index e9ac46517..83d2a34c6 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -31,8 +31,7 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \
-                        TU_CHECK_MCU(OPT_MCU_RAXXX))
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
 
 #include "device/dcd.h"
 #include "rusb2_type.h"
-- 
cgit v1.3.1


From 4f4c93594d8f82c18f9a1052c4da2e7c31fc1b8c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Jul 2023 17:51:36 +0700
Subject: minor pipe clean up

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 74 ++++++++++++++++++++--------------
 1 file changed, 43 insertions(+), 31 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 83d2a34c6..b58e0be01 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -93,20 +93,20 @@ typedef struct TU_ATTR_PACKED {
 
 typedef union TU_ATTR_PACKED {
   struct {
-    volatile uint16_t u8: 8;
-    volatile uint16_t   : 0;
+    volatile uint8_t u8;
+    volatile uint8_t reserved8;
   };
   volatile uint16_t u16;
 } hw_fifo_t;
 
 typedef union TU_ATTR_PACKED {
   struct {
-    volatile uint32_t  : 24;
-    volatile uint32_t u8: 8;
+    volatile uint8_t reserved8[3];
+    volatile uint8_t u8;
   };
   struct {
-    volatile uint32_t    : 16;
-    volatile uint32_t u16: 16;
+    volatile uint16_t reserved16;
+    volatile uint16_t u16;
   };
   volatile uint32_t u32;
 } hw_fifo32_t;
@@ -126,6 +126,19 @@ typedef struct TU_ATTR_PACKED
 TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 TU_ATTR_BIT_FIELD_ORDER_END
 
+// Transfer conditions specifiable for each pipe:
+// - Pipe 0: Control transfer with 64-byte single buffer
+// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
+//   to 2 KB and optional double buffer
+// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and
+//   optional double buffer
+// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer
+enum {
+  PIPE_1ST_BULK = 3,
+  PIPE_1ST_INTERRUPT = 6,
+  PIPE_COUNT = 10,
+};
+
 typedef struct
 {
   pipe_state_t pipe[10];
@@ -137,34 +150,33 @@ typedef struct
 //--------------------------------------------------------------------+
 static dcd_data_t _dcd;
 
-#ifndef FIRST_BULK_PIPE
-#define FIRST_BULK_PIPE 3
-#endif
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
-  case TUSB_XFER_ISOCHRONOUS:
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_BULK:
-    for (int i = FIRST_BULK_PIPE; i <= 5; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    for (int i = 1; i <= 1; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_INTERRUPT:
-    for (int i = 6; i <= 9; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  default:
-    /* No support for control transfer */
-    break;
+    case TUSB_XFER_ISOCHRONOUS:
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      break;
+
+    case TUSB_XFER_BULK:
+      for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      break;
+
+    default:
+      /* No support for control transfer */
+      break;
   }
   return 0;
 }
-- 
cgit v1.3.1


From f308435b649c37f0cffc1d5a566fb71c22b57aa1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Jul 2023 22:09:35 +0700
Subject: update ra type to include usbhs registers

---
 hw/bsp/ra/family.cmake                  |   1 -
 hw/bsp/ra/family.mk                     |   1 -
 src/portable/renesas/rusb2/rusb2_ra.c   |  16 --
 src/portable/renesas/rusb2/rusb2_ra.h   |  83 +++++----
 src/portable/renesas/rusb2/rusb2_type.h | 315 ++++++++++++++++++++------------
 5 files changed, 245 insertions(+), 171 deletions(-)
 delete mode 100644 src/portable/renesas/rusb2/rusb2_ra.c

(limited to 'src')

diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index f4e978230..74329165f 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -120,7 +120,6 @@ function(family_configure_example TARGET RTOS)
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
     ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
-    ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 9b6b02c02..b6e1bb0ae 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -18,7 +18,6 @@ CFLAGS += \
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
-  src/portable/renesas/rusb2/rusb2_ra.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
deleted file mode 100644
index ff2191b1f..000000000
--- a/src/portable/renesas/rusb2/rusb2_ra.c
+++ /dev/null
@@ -1,16 +0,0 @@
-#include "tusb_option.h"
-#include "rusb2_ra.h"
-
-#if (CFG_TUSB_RHPORT0_MODE != 0)
-IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn;
-void tud_set_irq_usbfs(IRQn_Type q) {
-  _usb_fs_irqn = q;
-}
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE != 0)
-IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn;
-void tud_set_irq_usbhs(IRQn_Type q) {
-  _usb_hs_irqn = q;
-}
-#endif
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 07fcafe6f..ca7c38907 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -47,55 +47,53 @@ extern "C" {
 #pragma GCC diagnostic pop
 #endif
 
-extern IRQn_Type _usb_fs_irqn;
-extern IRQn_Type _usb_hs_irqn;
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 
-#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
-// fallback
-#define CFG_TUSB_RHPORT0_MODE   ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST )
-#define CFG_TUSB_RHPORT1_MODE   0
+// IAR does not have __builtin_ctz
+#if defined(__ICCARM__)
+  #define __builtin_ctz(x)   __iar_builtin_CLZ(__iar_builtin_RBIT(x))
 #endif
 
-#if defined(__ICCARM__)
-  #define __builtin_ctz(x)             __iar_builtin_CLZ(__iar_builtin_RBIT(x))
+typedef struct {
+  uint32_t reg_base;
+  int32_t irqnum;
+}rusb2_controller_t;
+
+#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+  #define RUSB2_HAS_HIGHSPEED
+  #define RUSB2_CONTROLLER_COUNT 2
+#else
+  #define RUSB2_CONTROLLER_COUNT 1
 #endif
 
+// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
+static rusb2_controller_t rusb2_controller[] = {
+    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+    #ifdef RUSB2_HAS_HIGHSPEED
+    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+    #endif
+};
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
-#ifdef CFG_TUSB_RHPORT1_MODE
-#if (CFG_TUSB_RHPORT1_MODE != 0)
-  if (rhport == 1) {
-    NVIC_EnableIRQ(_usb_hs_irqn);
-  }
-#endif
-#endif
-
-#ifdef CFG_TUSB_RHPORT0_MODE
-#if  (CFG_TUSB_RHPORT0_MODE != 0)
-  if (rhport == 0) {
-    NVIC_EnableIRQ(_usb_fs_irqn);
-  }
-#endif
-#endif
+  #if RUSB2_CONTROLLER_COUNT > 1
+  NVIC_EnableIRQ(rusb2_controller[rhport].irqnum);
+  #else
+  (void) rhport;
+  NVIC_EnableIRQ(rusb2_controller[0].irqnum);
+  #endif
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
 {
-#ifdef CFG_TUSB_RHPORT1_MODE
-#if (CFG_TUSB_RHPORT1_MODE != 0)
-  if (rhport == 1) {
-    NVIC_DisableIRQ(_usb_hs_irqn);
-  }
-#endif
-#endif
-
-#ifdef CFG_TUSB_RHPORT0_MODE
-#if (CFG_TUSB_RHPORT0_MODE != 0)
-  if (rhport == 0) {
-    NVIC_DisableIRQ(_usb_fs_irqn);
-  }
-#endif
-#endif
+  #if RUSB2_CONTROLLER_COUNT > 1
+  NVIC_DisableIRQ(rusb2_controller[rhport].irqnum);
+  #else
+  (void) rhport;
+  NVIC_DisableIRQ(rusb2_controller[0].irqnum);
+  #endif
 }
 
 // MCU specific PHY init
@@ -103,6 +101,15 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
 {
 }
 
+void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  #if RUSB2_CONTROLLER_COUNT > 1
+  rusb2_controller[rhport].irqnum = irqnum;
+  #else
+  (void) rhport;
+  rusb2_controller[0].irqnum = irqnum;
+  #endif
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 90ba4f012..0928f5aeb 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -46,10 +46,10 @@ typedef struct {
     volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 8;
+      uint16_t                : 8;
       volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
       volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
-      uint16_t : 6;
+      uint16_t                : 6;
     } E_b;
   };
 
@@ -62,7 +62,8 @@ typedef struct {
   };
 } RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */
 
-/* LINK_REG Structure */
+
+/* RUSB2 Registers Structure */
 typedef struct {
   union {
     volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
@@ -74,7 +75,7 @@ typedef struct {
       volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
       volatile uint16_t DRPD  : 1; /* [5..5] D+/D- Line Resistor Control */
       volatile uint16_t DCFM  : 1; /* [6..6] Controller Function Select */
-      uint16_t                : 1;
+      volatile uint16_t HSE   : 1; // [7..7] High-Speed Operation Enable
       volatile uint16_t CNEN  : 1; /* [8..8] CNEN Single End Receiver Enable */
       uint16_t                : 1;
       volatile uint16_t SCKE  : 1; /* [10..10] USB Clock Enable */
@@ -87,7 +88,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
-      uint16_t : 12;
+      uint16_t                : 12;
     } BUSWAIT_b;
   };
 
@@ -98,8 +99,7 @@ typedef struct {
       volatile const uint16_t LNST   : 2; /* [1..0] USB Data Line Status Monitor */
       volatile const uint16_t IDMON  : 1; /* [2..2] External ID0 Input Pin Monitor */
       uint16_t                       : 2;
-      volatile const uint16_t
-        SOFEA                        : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
+      volatile const uint16_t SOFEA  : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
       volatile const uint16_t HTACT  : 1; /* [6..6] USB Host Sequencer Status Monitor */
       uint16_t                       : 7;
       volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
@@ -111,7 +111,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
-      uint16_t : 15;
+      uint16_t                        : 15;
     } PLLSTA_b;
   };
 
@@ -139,7 +139,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t UTST : 4; /* [3..0] Test Mode */
-      uint16_t : 12;
+      uint16_t               : 12;
     } TESTMODE_b;
   };
   volatile const uint16_t RESERVED1;
@@ -295,7 +295,7 @@ typedef struct {
     volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 8;
+      uint16_t                : 8;
       volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
       volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
       volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
@@ -316,7 +316,10 @@ typedef struct {
       volatile uint16_t SACKE      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */
       volatile uint16_t SIGNE      : 1; /* [5..5] Setup Transaction Error Interrupt Enable */
       volatile uint16_t EOFERRE    : 1; /* [6..6] EOF Error Detection Interrupt Enable */
-      uint16_t                     : 4;
+               uint16_t            : 1;
+      volatile uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
+      volatile uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
+               uint16_t            : 1;
       volatile uint16_t ATTCHE     : 1; /* [11..11] Connection Detection Interrupt Enable */
       volatile uint16_t DTCHE      : 1; /* [12..12] Disconnection Detection Interrupt Enable */
       uint16_t                     : 1;
@@ -340,7 +343,7 @@ typedef struct {
       volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
-      uint16_t : 6;
+      uint16_t                     : 6;
     } BRDYENB_b;
   };
 
@@ -358,7 +361,7 @@ typedef struct {
       volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
-      uint16_t : 6;
+      uint16_t                     : 6;
     } NRDYENB_b;
   };
 
@@ -376,7 +379,7 @@ typedef struct {
       volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
       volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
       volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
-      uint16_t : 6;
+      uint16_t                     : 6;
     } BEMPENB_b;
   };
 
@@ -390,7 +393,7 @@ typedef struct {
       volatile uint16_t BRDYM         : 1; /* [6..6] BRDY Interrupt Status Clear Timing */
       uint16_t                        : 1;
       volatile uint16_t TRNENSEL      : 1; /* [8..8] Transaction-Enabled Time Select */
-      uint16_t : 7;
+      uint16_t                        : 7;
     } SOFCFG_b;
   };
 
@@ -467,7 +470,7 @@ typedef struct {
       volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
-      uint16_t : 6;
+      uint16_t                    : 6;
     } BRDYSTS_b;
   };
 
@@ -485,7 +488,7 @@ typedef struct {
       volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
-      uint16_t : 6;
+      uint16_t                    : 6;
     } NRDYSTS_b;
   };
 
@@ -503,7 +506,7 @@ typedef struct {
       volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
       volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
       volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
-      uint16_t : 6;
+      uint16_t                    : 6;
     } BEMPSTS_b;
   };
 
@@ -609,7 +612,8 @@ typedef struct {
       volatile uint16_t SQCLR       : 1; /* [8..8] Sequence Toggle Bit Clear */
       uint16_t                      : 2;
       volatile uint16_t SUREQCLR    : 1; /* [11..11] SUREQ Bit Clear */
-      uint16_t                      : 2;
+      volatile uint16_t CSSTS       : 1; /* [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                  */
+      volatile uint16_t CSCLR       : 1; /* [13..13] Split Transaction CSPLIT Status Clear                            */
       volatile uint16_t SUREQ       : 1; /* [14..14] Setup Token Transmission */
       volatile const uint16_t BSTS  : 1; /* [15..15] Buffer Status */
     } DCPCTR_b;
@@ -621,7 +625,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
-      uint16_t : 12;
+      uint16_t                  : 12;
     } PIPESEL_b;
   };
   volatile const uint16_t RESERVED11;
@@ -634,21 +638,31 @@ typedef struct {
       volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
       uint16_t                 : 2;
       volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-      uint16_t                 : 1;
+      volatile uint16_t CNTMD  : 1; /* [8..8] Continuous Transfer Mode                                           */
       volatile uint16_t DBLB   : 1; /* [9..9] Double Buffer Mode */
       volatile uint16_t BFRE   : 1; /* [10..10] BRDY Interrupt Operation Specification */
       uint16_t                 : 3;
       volatile uint16_t TYPE   : 2; /* [15..14] Transfer Type */
     } PIPECFG_b;
   };
-  volatile const uint16_t RESERVED12;
+
+  union {
+    volatile uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Register                                       */
+
+    struct {
+      volatile uint16_t BUFNMB  : 8; // [7..0] Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h)
+      uint16_t                  : 2;
+      volatile uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes         */
+      uint16_t                  : 1;
+    } PIPEBUF_b;
+  };
 
   union {
     volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
 
     struct TU_ATTR_PACKED {
-      volatile uint16_t MXPS   : 9; /* [8..0] Maximum Packet Size */
-      uint16_t                 : 3;
+      volatile uint16_t MXPS   : 11; /* [10..0] Maximum Packet Size */
+      uint16_t                 : 1;
       volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
     } PIPEMAXP_b;
   };
@@ -694,11 +708,9 @@ typedef struct {
     struct TU_ATTR_PACKED {
       volatile uint16_t RPDME0           : 1; /* [0..0] D- Pin Pull-Down Control */
       volatile uint16_t IDPSRCE0         : 1; /* [1..1] D+ Pin IDPSRC Output Control */
-      volatile uint16_t
-        IDMSINKE0                        : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t IDMSINKE0        : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
       volatile uint16_t VDPSRCE0         : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
-      volatile uint16_t
-        IDPSINKE0                        : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t IDPSINKE0        : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
       volatile uint16_t VDMSRCE0         : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
       uint16_t                           : 1;
       volatile uint16_t BATCHGE0         : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
@@ -715,7 +727,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
-      uint16_t : 15;
+      uint16_t                  : 15;
     } UCKSEL_b;
   };
   volatile const uint16_t RESERVED18;
@@ -737,11 +749,11 @@ typedef struct {
     volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 6;
+      uint16_t                  : 6;
       volatile uint16_t USBSPD  : 2; /* [7..6] Transfer Speed of Communication Target Device */
       volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
       volatile uint16_t UPPHUB  : 4; /* [14..11] Communication Target Connecting Hub Register */
-      uint16_t : 1;
+      uint16_t                  : 1;
     } DEVADD_b[10];
   };
   volatile const uint32_t RESERVED21[3];
@@ -754,7 +766,7 @@ typedef struct {
       volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
       volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
       volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
-      uint32_t : 28;
+      uint32_t                  : 28;
     } PHYSLEW_b;
   };
   volatile const uint32_t RESERVED22[3];
@@ -763,9 +775,9 @@ typedef struct {
     volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 7;
+      uint16_t                : 7;
       volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
-      uint16_t : 8;
+      uint16_t                : 8;
     } LPCTRL_b;
   };
 
@@ -773,9 +785,9 @@ typedef struct {
     volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 14;
+      uint16_t                   : 14;
       volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
-      uint16_t : 1;
+      uint16_t                   : 1;
     } LPSTS_b;
   };
   volatile const uint32_t RESERVED23[15];
@@ -793,7 +805,7 @@ typedef struct {
       uint16_t                          : 2;
       volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
       volatile const uint16_t PDDETSTS  : 1; /* [9..9] PDDET Status */
-      uint16_t : 6;
+      uint16_t                          : 6;
     } BCCTRL_b;
   };
   volatile const uint16_t RESERVED24;
@@ -809,7 +821,7 @@ typedef struct {
       volatile uint16_t HIRDTHR    : 4; /* [11..8] L1 Response Negotiation Threshold Value */
       uint16_t                     : 2;
       volatile uint16_t L1EXTMD    : 1; /* [14..14] PHY Control Mode at L1 Return */
-      uint16_t : 1;
+      uint16_t                     : 1;
     } PL1CTRL1_b;
   };
 
@@ -817,10 +829,10 @@ typedef struct {
     volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 8;
+      uint16_t                  : 8;
       volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
       volatile uint16_t RWEMON  : 1;  /* [12..12] RWE Value Monitor */
-      uint16_t : 3;
+      uint16_t                  : 3;
     } PL1CTRL2_b;
   };
 
@@ -830,7 +842,7 @@ typedef struct {
     struct TU_ATTR_PACKED {
       volatile uint16_t L1REQ          : 1;       /* [0..0] L1 Transition Request */
       volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
-      uint16_t : 13;
+      uint16_t                         : 13;
     } HL1CTRL1_b;
   };
 
@@ -846,18 +858,48 @@ typedef struct {
       volatile uint16_t BESL   : 1; /* [15..15] BESL & Alternate HIRD */
     } HL1CTRL2_b;
   };
-  volatile const uint32_t RESERVED25[5];
+
+  volatile uint32_t RESERVED25_1;
+
+  union {
+    volatile uint16_t PHYTRIM1;          /*!< (@ 0x00000150) PHY Timing Register 1                                      */
+
+    struct {
+      volatile uint16_t DRISE      : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function              */
+      volatile uint16_t DFALL      : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function             */
+               uint16_t            : 3;
+      volatile uint16_t PCOMPENB   : 1; /*!< [7..7] PVDD Start-up Detection                                            */
+      volatile uint16_t HSIUP      : 4; /*!< [11..8] HS Output Level Setting                                           */
+      volatile uint16_t IMPOFFSET  : 3; /*!< [14..12] terminating resistance offset value setting.Offset value for adjusting the terminating resistance.                           */
+               uint16_t            : 1;
+    } PHYTRIM1_b;
+  };
+
+  union {
+    volatile uint16_t PHYTRIM2;         /*!< (@ 0x00000152) PHY Timing Register 2                                      */
+
+    struct {
+      volatile  uint16_t SQU      : 4; /*!< [3..0] Squelch Detection Level                                            */
+      uint16_t                    : 3;
+      volatile  uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode                                     */
+      volatile  uint16_t PDR      : 2; /*!< [9..8] HS Output Adjustment Function                                      */
+      uint16_t                    : 2;
+      volatile  uint16_t DIS      : 3; /*!< [14..12] Disconnect Detection Level                                       */
+      uint16_t                    : 1;
+    } PHYTRIM2_b;
+  };
+  volatile uint32_t RESERVED25_2[3];
 
   union {
     volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
 
     struct TU_ATTR_PACKED {
-      uint32_t : 20;
+      uint32_t                         : 20;
       volatile const uint32_t DOVCAHM  : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
       volatile const uint32_t DOVCBHM  : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
       uint32_t                         : 1;
       volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
-      uint32_t : 8;
+      uint32_t                         : 8;
     } DPUSR0R_b;
   };
 
@@ -865,7 +907,7 @@ typedef struct {
     volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
 
     struct TU_ATTR_PACKED {
-      uint32_t : 4;
+      uint32_t                        : 4;
       volatile uint32_t DOVCAHE       : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
       volatile uint32_t DOVCBHE       : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
       uint32_t                        : 1;
@@ -875,7 +917,7 @@ typedef struct {
       volatile const uint32_t DOVCBH  : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
       uint32_t                        : 1;
       volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
-      uint32_t : 8;
+      uint32_t                        : 8;
     } DPUSR1R_b;
   };
 
@@ -891,7 +933,7 @@ typedef struct {
       uint16_t                      : 2;
       volatile uint16_t DPINTE      : 1; /* [8..8] DP Interrupt Enable Clear */
       volatile uint16_t DMINTE      : 1; /* [9..9] DM Interrupt Enable Clear */
-      uint16_t : 6;
+      uint16_t                      : 6;
     } DPUSR2R_b;
   };
 
@@ -901,7 +943,7 @@ typedef struct {
     struct TU_ATTR_PACKED {
       volatile uint16_t FIXPHY   : 1; /* [0..0] USB Transceiver Control Fix */
       volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
-      uint16_t : 14;
+      uint16_t                   : 14;
     } DPUSRCR_b;
   };
   volatile const uint32_t RESERVED26[165];
@@ -924,7 +966,7 @@ typedef struct {
       volatile const uint32_t DOVCB0  : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
       uint32_t                        : 1;
       volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
-      uint32_t : 8;
+      uint32_t                        : 8;
     } DPUSR0R_FS_b;
   };
 
@@ -947,10 +989,10 @@ typedef struct {
       volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
       uint32_t                         : 1;
       volatile const uint32_t DVBINT0  : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
-      uint32_t : 8;
+      uint32_t                         : 8;
     } DPUSR1R_FS_b;
   };
-} RUSB2_REG_t; /* Size = 1032 (0x408) */
+} rusb2_reg_t; /* Size = 1032 (0x408) */
 
 TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_BIT_FIELD_ORDER_END
@@ -970,13 +1012,15 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_PIPE_TR_N_TRNCNT_Pos      (0UL)        /* TRNCNT (Bit 0) */
 #define RUSB2_PIPE_TR_N_TRNCNT_Msk      (0xffffUL)   /* TRNCNT (Bitfield-Mask: 0xffff) */
 
-// LINK_REG
+// Core Registers
 
 // SYSCFG
 #define RUSB2_SYSCFG_SCKE_Pos           (10UL)       /* SCKE (Bit 10) */
 #define RUSB2_SYSCFG_SCKE_Msk           (0x400UL)    /* SCKE (Bitfield-Mask: 0x01) */
 #define RUSB2_SYSCFG_CNEN_Pos           (8UL)        /* CNEN (Bit 8) */
 #define RUSB2_SYSCFG_CNEN_Msk           (0x100UL)    /* CNEN (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_HSE_Pos            (7UL)        /*!< HSE (Bit 7)                                           */
+#define RUSB2_SYSCFG_HSE_Msk            (0x80UL)     /*!< HSE (Bitfield-Mask: 0x01)                             */
 #define RUSB2_SYSCFG_DCFM_Pos           (6UL)        /* DCFM (Bit 6) */
 #define RUSB2_SYSCFG_DCFM_Msk           (0x40UL)     /* DCFM (Bitfield-Mask: 0x01) */
 #define RUSB2_SYSCFG_DRPD_Pos           (5UL)        /* DRPD (Bit 5) */
@@ -1135,6 +1179,10 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_INTENB1_DTCHE_Msk         (0x1000UL)   /* DTCHE (Bitfield-Mask: 0x01) */
 #define RUSB2_INTENB1_ATTCHE_Pos        (11UL)       /* ATTCHE (Bit 11) */
 #define RUSB2_INTENB1_ATTCHE_Msk        (0x800UL)    /* ATTCHE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_L1RSMENDE_Pos     (9UL)        /*!< L1RSMENDE (Bit 9)                                     */
+#define RUSB2_INTENB1_L1RSMENDE_Msk     (0x200UL)    /*!< L1RSMENDE (Bitfield-Mask: 0x01)                       */
+#define RUSB2_INTENB1_LPMENDE_Pos       (8UL)        /*!< LPMENDE (Bit 8)                                       */
+#define RUSB2_INTENB1_LPMENDE_Msk       (0x100UL)    /*!< LPMENDE (Bitfield-Mask: 0x01)                         */
 #define RUSB2_INTENB1_EOFERRE_Pos       (6UL)        /* EOFERRE (Bit 6) */
 #define RUSB2_INTENB1_EOFERRE_Msk       (0x40UL)     /* EOFERRE (Bitfield-Mask: 0x01) */
 #define RUSB2_INTENB1_SIGNE_Pos         (5UL)        /* SIGNE (Bit 5) */
@@ -1299,6 +1347,10 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_DCPCTR_BSTS_Msk           (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
 #define RUSB2_DCPCTR_SUREQ_Pos          (14UL)       /* SUREQ (Bit 14) */
 #define RUSB2_DCPCTR_SUREQ_Msk          (0x4000UL)   /* SUREQ (Bitfield-Mask: 0x01) */
+#define R_USB_HS0_DCPCTR_CSCLR_Pos      (13UL)       /*!< CSCLR (Bit 13)                                        */
+#define RUSB2_DCPCTR_CSCLR_Msk          (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
+#define RUSB2_DCPCTR_CSSTS_Pos          (12UL)       /*!< CSSTS (Bit 12)                                        */
+#define RUSB2_DCPCTR_CSSTS_Msk          (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
 #define RUSB2_DCPCTR_SUREQCLR_Pos       (11UL)       /* SUREQCLR (Bit 11) */
 #define RUSB2_DCPCTR_SUREQCLR_Msk       (0x800UL)    /* SUREQCLR (Bitfield-Mask: 0x01) */
 #define RUSB2_DCPCTR_SQCLR_Pos          (8UL)        /* SQCLR (Bit 8) */
@@ -1325,6 +1377,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_PIPECFG_BFRE_Msk          (0x400UL)    /* BFRE (Bitfield-Mask: 0x01) */
 #define RUSB2_PIPECFG_DBLB_Pos          (9UL)        /* DBLB (Bit 9) */
 #define RUSB2_PIPECFG_DBLB_Msk          (0x200UL)    /* DBLB (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_CNTMD_Pos         (8UL)        /*!< CNTMD (Bit 8)                                         */
+#define RUSB2_PIPECFG_CNTMD_Msk         (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
 #define RUSB2_PIPECFG_SHTNAK_Pos        (7UL)        /* SHTNAK (Bit 7) */
 #define RUSB2_PIPECFG_SHTNAK_Msk        (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
 #define RUSB2_PIPECFG_DIR_Pos           (4UL)        /* DIR (Bit 4) */
@@ -1332,6 +1386,12 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_PIPECFG_EPNUM_Pos         (0UL)        /* EPNUM (Bit 0) */
 #define RUSB2_PIPECFG_EPNUM_Msk         (0xfUL)      /* EPNUM (Bitfield-Mask: 0x0f) */
 
+// PIPEBUF
+#define RUSB2_PIPEBUF_BUFSIZE_Pos       (10UL)       /*!< BUFSIZE (Bit 10)                                      */
+#define RUSB2_PIPEBUF_BUFSIZE_Msk       (0x7c00UL)   /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
+#define RUSB2_PIPEBUF_BUFNMB_Pos        (0UL)        /*!< BUFNMB (Bit 0)                                        */
+#define RUSB2_PIPEBUF_BUFNMB_Msk        (0xffUL)     /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
+
 // PIPEMAXP
 #define RUSB2_PIPEMAXP_DEVSEL_Pos       (12UL)       /* DEVSEL (Bit 12) */
 #define RUSB2_PIPEMAXP_DEVSEL_Msk       (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
@@ -1478,6 +1538,28 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_HL1CTRL2_L1ADDR_Pos       (0UL)        /* L1ADDR (Bit 0) */
 #define RUSB2_HL1CTRL2_L1ADDR_Msk       (0xfUL)      /* L1ADDR (Bitfield-Mask: 0x0f) */
 
+// PHYTRIM1
+#define RUSB2_PHYTRIM1_IMPOFFSET_Pos    (12UL)       /*!< IMPOFFSET (Bit 12)                                    */
+#define RUSB2_PHYTRIM1_IMPOFFSET_Msk    (0x7000UL)   /*!< IMPOFFSET (Bitfield-Mask: 0x07)                       */
+#define RUSB2_PHYTRIM1_HSIUP_Pos        (8UL)        /*!< HSIUP (Bit 8)                                         */
+#define RUSB2_PHYTRIM1_HSIUP_Msk        (0xf00UL)    /*!< HSIUP (Bitfield-Mask: 0x0f)                           */
+#define RUSB2_PHYTRIM1_PCOMPENB_Pos     (7UL)        /*!< PCOMPENB (Bit 7)                                      */
+#define RUSB2_PHYTRIM1_PCOMPENB_Msk     (0x80UL)     /*!< PCOMPENB (Bitfield-Mask: 0x01)                        */
+#define RUSB2_PHYTRIM1_DFALL_Pos        (2UL)        /*!< DFALL (Bit 2)                                         */
+#define RUSB2_PHYTRIM1_DFALL_Msk        (0xcUL)      /*!< DFALL (Bitfield-Mask: 0x03)                           */
+#define RUSB2_PHYTRIM1_DRISE_Pos        (0UL)        /*!< DRISE (Bit 0)                                         */
+#define RUSB2_PHYTRIM1_DRISE_Msk        (0x3UL)      /*!< DRISE (Bitfield-Mask: 0x03)                           */
+
+// PHYTRIM2
+#define RUSB2_PHYTRIM2_DIS_Pos          (12UL)       /*!< DIS (Bit 12)                                          */
+#define RUSB2_PHYTRIM2_DIS_Msk          (0x7000UL)   /*!< DIS (Bitfield-Mask: 0x07)                             */
+#define RUSB2_PHYTRIM2_PDR_Pos          (8UL)        /*!< PDR (Bit 8)                                           */
+#define RUSB2_PHYTRIM2_PDR_Msk          (0x300UL)    /*!< PDR (Bitfield-Mask: 0x03)                             */
+#define RUSB2_PHYTRIM2_HSRXENMO_Pos     (7UL)        /*!< HSRXENMO (Bit 7)                                      */
+#define RUSB2_PHYTRIM2_HSRXENMO_Msk     (0x80UL)     /*!< HSRXENMO (Bitfield-Mask: 0x01)                        */
+#define RUSB2_PHYTRIM2_SQU_Pos          (0UL)        /*!< SQU (Bit 0)                                           */
+#define RUSB2_PHYTRIM2_SQU_Msk          (0xfUL)      /*!< SQU (Bitfield-Mask: 0x0f)                             */
+
 // DPUSR0R
 #define RUSB2_DPUSR0R_DVBSTSHM_Pos      (23UL)       /* DVBSTSHM (Bit 23) */
 #define RUSB2_DPUSR0R_DVBSTSHM_Msk      (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
@@ -1599,69 +1681,72 @@ TU_ATTR_BIT_FIELD_ORDER_END
 //--------------------------------------------------------------------+
 
 TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size");
-TU_VERIFY_STATIC(sizeof(RUSB2_REG_t) == 1032, "incorrect size");
-
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG     ) == 0x00000000, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT    ) == 0x00000002, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSSTS0    ) == 0x00000004, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PLLSTA     ) == 0x00000006, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DVSTCTR0   ) == 0x00000008, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, TESTMODE   ) == 0x0000000C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFO      ) == 0x00000014, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFO     ) == 0x00000018, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFO     ) == 0x0000001C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOSEL   ) == 0x00000020, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOCTR   ) == 0x00000022, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOSEL  ) == 0x00000028, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOCTR  ) == 0x0000002A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOSEL  ) == 0x0000002C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOCTR  ) == 0x0000002E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB0    ) == 0x00000030, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB1    ) == 0x00000032, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYENB    ) == 0x00000036, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYENB    ) == 0x00000038, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPENB    ) == 0x0000003A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SOFCFG     ) == 0x0000003C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSET     ) == 0x0000003E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS0    ) == 0x00000040, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS1    ) == 0x00000042, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYSTS    ) == 0x00000046, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYSTS    ) == 0x00000048, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPSTS    ) == 0x0000004A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, FRMNUM     ) == 0x0000004C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UFRMNUM    ) == 0x0000004E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBADDR    ) == 0x00000050, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBREQ     ) == 0x00000054, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBVAL     ) == 0x00000056, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBINDX    ) == 0x00000058, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBLENG    ) == 0x0000005A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCFG     ) == 0x0000005C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPMAXP    ) == 0x0000005E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCTR     ) == 0x00000060, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPESEL    ) == 0x00000064, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPECFG    ) == 0x00000068, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEMAXP   ) == 0x0000006C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEPERI   ) == 0x0000006E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_CTR   ) == 0x00000070, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_TR    ) == 0x00000090, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UCKSEL     ) == 0x000000C4, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBMC      ) == 0x000000CC, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DEVADD     ) == 0x000000D0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSLEW    ) == 0x000000F0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPCTRL     ) == 0x00000100, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPSTS      ) == 0x00000102, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BCCTRL     ) == 0x00000140, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL1   ) == 0x00000144, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL2   ) == 0x00000146, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL1   ) == 0x00000148, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL2   ) == 0x0000014A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R    ) == 0x00000160, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R    ) == 0x00000164, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR2R    ) == 0x00000168, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSRCR    ) == 0x0000016A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset");
+TU_VERIFY_STATIC(sizeof(rusb2_reg_t) == 1032, "incorrect size");
+
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSCFG     ) == 0x0000, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BUSWAIT    ) == 0x0002, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSSTS0    ) == 0x0004, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PLLSTA     ) == 0x0006, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DVSTCTR0   ) == 0x0008, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, TESTMODE   ) == 0x000C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFO      ) == 0x0014, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFO     ) == 0x0018, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFO     ) == 0x001C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOSEL   ) == 0x0020, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOCTR   ) == 0x0022, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOSEL  ) == 0x0028, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOCTR  ) == 0x002A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOSEL  ) == 0x002C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOCTR  ) == 0x002E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB0    ) == 0x0030, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB1    ) == 0x0032, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYENB    ) == 0x0036, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYENB    ) == 0x0038, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPENB    ) == 0x003A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SOFCFG     ) == 0x003C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSET     ) == 0x003E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS0    ) == 0x0040, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS1    ) == 0x0042, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYSTS    ) == 0x0046, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYSTS    ) == 0x0048, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPSTS    ) == 0x004A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, FRMNUM     ) == 0x004C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UFRMNUM    ) == 0x004E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBADDR    ) == 0x0050, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBREQ     ) == 0x0054, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBVAL     ) == 0x0056, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBINDX    ) == 0x0058, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBLENG    ) == 0x005A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCFG     ) == 0x005C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPMAXP    ) == 0x005E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCTR     ) == 0x0060, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPESEL    ) == 0x0064, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPECFG    ) == 0x0068, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEBUF    ) == 0x006A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEMAXP   ) == 0x006C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEPERI   ) == 0x006E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_CTR   ) == 0x0070, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_TR    ) == 0x0090, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBBCCTRL0 ) == 0x00B0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UCKSEL     ) == 0x00C4, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBMC      ) == 0x00CC, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DEVADD     ) == 0x00D0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSLEW    ) == 0x00F0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPCTRL     ) == 0x0100, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPSTS      ) == 0x0102, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BCCTRL     ) == 0x0140, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL1   ) == 0x0144, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL2   ) == 0x0146, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL1   ) == 0x0148, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL2   ) == 0x014A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM1   ) == 0x0150, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM2   ) == 0x0152, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R    ) == 0x0160, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R    ) == 0x0164, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR2R    ) == 0x0168, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSRCR    ) == 0x016A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R_FS ) == 0x0400, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R_FS ) == 0x0404, "incorrect offset");
 
 #ifdef __cplusplus
 }
-- 
cgit v1.3.1


From 95b77a0e7356b5f6625fbdb66f35415db3aac7a9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Jul 2023 15:54:07 +0700
Subject: add rusb2_module_start(), more update for multiple ports for dcd
 rusb2

---
 hw/bsp/ra/family.c                      |   7 -
 src/portable/renesas/rusb2/dcd_rusb2.c  | 280 +++++++++++++++++++-------------
 src/portable/renesas/rusb2/rusb2_ra.h   |  38 ++---
 src/portable/renesas/rusb2/rusb2_rx.h   |   6 +
 src/portable/renesas/rusb2/rusb2_type.h |   1 +
 5 files changed, 190 insertions(+), 142 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 36b46beab..2c21a9967 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -104,13 +104,6 @@ void board_init(void) {
   R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
 #endif
 
-  // Enable USB module
-  R_MSTP->MSTPCRB &= ~(1U << 11U); // FS
-
-#ifdef BOARD_HAS_USB_HIGHSPEED
-  R_MSTP->MSTPCRB &= ~(1U << 12U);
-#endif
-
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index b58e0be01..27d525b68 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -65,9 +65,9 @@
 
 /* LINK core registers */
 #if defined(__CCRX__)
-  #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+  #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE)
 #elif defined(__RX__)
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
+  #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE)
 #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
   #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
 #else
@@ -145,10 +145,15 @@ typedef struct
   uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
 } dcd_data_t;
 
+static dcd_data_t _dcd;
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-static dcd_data_t _dcd;
+
+TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) {
+  return rhport == 1;
+}
 
 static unsigned find_pipe(unsigned xfer)
 {
@@ -543,38 +548,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
 
 static void process_bus_reset(uint8_t rhport)
 {
-  RUSB2->BEMPENB = 1;
-  RUSB2->BRDYENB = 1;
-  RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  RUSB2->D1FIFOSEL = 0;
-  while (RUSB2->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_CTR[0]));
-  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_TR[0].E));
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  rusb->BEMPENB = 1;
+  rusb->BRDYENB = 1;
+  rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  rusb->D1FIFOSEL = 0;
+  while (rusb->D1FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_CTR[0]));
+  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_TR[0].E));
+
   for (int i = 1; i <= 5; ++i) {
-    RUSB2->PIPESEL = i;
-    RUSB2->PIPECFG = 0;
+    rusb->PIPESEL = i;
+    rusb->PIPECFG = 0;
     *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
     *tre = TU_BIT(8);
     tre += 2;
   }
+
   for (int i = 6; i <= 9; ++i) {
-    RUSB2->PIPESEL = i;
-    RUSB2->PIPECFG = 0;
+    rusb->PIPESEL = i;
+    rusb->PIPECFG = 0;
     *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
   }
   tu_varclr(&_dcd);
 
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true);
-#else
-  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
-#endif
+  TU_LOG3("Bus reset, RHST = %u\r\n", rusb->DVSTCTR0_b.RHST);
+  tusb_speed_t speed;
+  switch(rusb->DVSTCTR0 & RUSB2_DVSTCTR0_RHST_Msk) {
+    case RUSB2_DVSTCTR0_RHST_LS:
+      speed = TUSB_SPEED_LOW;
+      break;
+
+    case RUSB2_DVSTCTR0_RHST_FS:
+      speed = TUSB_SPEED_FULL;
+      break;
+
+    case RUSB2_DVSTCTR0_RHST_HS:
+      speed = TUSB_SPEED_HIGH;
+      break;
+
+    default:
+      TU_ASSERT(false, );
+  }
+
+  dcd_event_bus_reset(rhport, speed, true);
 }
 
 static void process_set_address(uint8_t rhport)
@@ -625,56 +652,63 @@ static void enable_interrupt(uint32_t pswi)
 
 void dcd_init(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  RUSB2->SYSCFG_b.HSE = 1;
-  RUSB2->PHYSET_b.DIRPD = 0;
-  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
-  RUSB2->PHYSET_b.PLLRESET = 0;
-  //RUSB2->PHYSET_b.REPSTART = 1;
-  RUSB2->SYSCFG_b.DRPD = 0;
-  RUSB2->SYSCFG_b.USBE = 1;
-  RUSB2->LPSTS_b.SUSPENDM = 1;
-  while (!RUSB2->PLLSTA_b.PLLLOCK);
-  //RUSB2->BUSWAIT |= 0x0F00U;
-  //RUSB2->PHYSET_b.REPSEL = 1;
-  RUSB2->CFIFOSEL_b.MBW = 1;
-  RUSB2->D0FIFOSEL_b.MBW = 1;
-  RUSB2->D1FIFOSEL_b.MBW = 1;
-  RUSB2->INTSTS0 = 0;
-#else
-  RUSB2->SYSCFG_b.SCKE = 1;
-  while (!RUSB2->SYSCFG_b.SCKE) ;
-  RUSB2->SYSCFG_b.DRPD = 0;
-  RUSB2->SYSCFG_b.DCFM = 0;
-  RUSB2->SYSCFG_b.USBE = 1;
-#endif
+  rusb2_module_start(rhport, true);
 
-  // MCU specific PHY init
-  rusb2_phy_init();
+  if ( is_highspeed(rhport) ) {
+    rusb->SYSCFG_b.HSE = 1;
 
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  RUSB2->PHYSLEW = 0x5;
-  RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
+    // leave CLKSEL as default (0x11) 24Mhz
 
-  #define USB_VDCEN                 (0x0080U) /* b7: Regulator ON/OFF control */
-  RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN));
-#endif
+    // Power and reset UTMI Phy
+    uint16_t physet = (rusb->PHYSET | RUSB2_PHYSET_PLLRESET_Msk) & ~RUSB2_PHYSET_DIRPD_Msk;
+    rusb->PHYSET = physet;
+    R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->PHYSET_b.PLLRESET = 0;
+
+    // set UTMI to operating mode and wait for PLL lock confirmation
+    rusb->LPSTS_b.SUSPENDM = 1;
+    while (!rusb->PLLSTA_b.PLLLOCK) {}
+
+    rusb->SYSCFG_b.DRPD = 0;
+    rusb->SYSCFG_b.USBE = 1;
+
+    // Set CPU bus wait time (fine tunne later)
+    // rusb2->BUSWAIT |= 0x0F00U;
+
+    rusb->PHYSET_b.REPSEL = 1;
+
+    rusb->CFIFOSEL_b.MBW = 1;
+    rusb->D0FIFOSEL_b.MBW = 1;
+    rusb->D1FIFOSEL_b.MBW = 1;
+  } else {
+    rusb->SYSCFG_b.SCKE = 1;
+    while (!rusb->SYSCFG_b.SCKE) {}
+    rusb->SYSCFG_b.DRPD = 0;
+    rusb->SYSCFG_b.DCFM = 0;
+    rusb->SYSCFG_b.USBE = 1;
+
+    // MCU specific PHY init
+    rusb2_phy_init();
+
+    rusb->PHYSLEW = 0x5;
+    rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
+
+    // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk);
+  }
 
   /* Setup default control pipe */
-  RUSB2->DCPMAXP_b.MXPS = 64;
-  RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
-          RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
-          RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
-  RUSB2->BEMPENB = 1;
-  RUSB2->BRDYENB = 1;
-
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  RUSB2->SYSCFG_b.DPRPU = 1;  /* necessary in this position */
-#endif
+  rusb->DCPMAXP_b.MXPS = 64;
+
+  rusb->INTSTS0 = 0;
+  rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
+                  RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
+                  RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
+  rusb->BEMPENB = 1;
+  rusb->BRDYENB = 1;
 
-  if (RUSB2->INTSTS0_b.VBSTS) {
+  if (rusb->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }
 }
@@ -697,24 +731,24 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
-  (void)rhport;
-  RUSB2->DVSTCTR0_b.WKUP = 1;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->DVSTCTR0_b.WKUP = 1;
 }
 
 void dcd_connect(uint8_t rhport)
 {
-  (void)rhport;
-  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  RUSB2->SYSCFG_b.CNEN = 1;
-  R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS);
-  #endif
-  RUSB2->SYSCFG_b.DPRPU = 1;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  if ( is_highspeed(rhport)) {
+    rusb->SYSCFG_b.CNEN = 1;
+  }
+  rusb->SYSCFG_b.DPRPU = 1;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
-  (void)rhport;
-  RUSB2->SYSCFG_b.DPRPU = 0;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->SYSCFG_b.DPRPU = 0;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -861,76 +895,94 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 void dcd_int_handler(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  uint16_t is0 = rusb->INTSTS0;
 
-  unsigned is0 = RUSB2->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk |
-                         RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk;
-  if (is0 & RUSB2_INTSTS0_VBINT_Msk) {
-    if (RUSB2->INTSTS0_b.VBSTS) {
+  rusb->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk |
+                     RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk;
+
+  // VBUS changes
+  if ( is0 & RUSB2_INTSTS0_VBINT_Msk ) {
+    if ( rusb->INTSTS0_b.VBSTS ) {
       dcd_connect(rhport);
     } else {
       dcd_disconnect(rhport);
     }
   }
-  if (is0 & RUSB2_INTSTS0_RESM_Msk) {
+
+  // Resumed
+  if ( is0 & RUSB2_INTSTS0_RESM_Msk ) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-#if (0==USE_SOF)
-    RUSB2->INTENB0_b.SOFE = 0;
+#if (0 == USE_SOF)
+    rusb->INTENB0_b.SOFE = 0;
 #endif
   }
-  if ((is0 & RUSB2_INTSTS0_SOFR_Msk) && RUSB2->INTENB0_b.SOFE) {
+
+  // SOF received
+  if ( (is0 & RUSB2_INTSTS0_SOFR_Msk) && rusb->INTENB0_b.SOFE ) {
     // USBD will exit suspended mode when SOF event is received
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
 #if (0 == USE_SOF)
-    RUSB2->INTENB0_b.SOFE = 0;
+    rusb->INTENB0_b.SOFE = 0;
 #endif
   }
-  if (is0 & RUSB2_INTSTS0_DVST_Msk) {
+
+  // Device state changes
+  if ( is0 & RUSB2_INTSTS0_DVST_Msk ) {
     switch (is0 & RUSB2_INTSTS0_DVSQ_Msk) {
-    case RUSB2_INTSTS0_DVSQ_STATE_DEF:
-      process_bus_reset(rhport);
-      break;
-    case RUSB2_INTSTS0_DVSQ_STATE_ADDR:
-      process_set_address(rhport);
-      break;
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP0:
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP1:
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP2:
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP3:
-       dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-#if (0==USE_SOF)
-      RUSB2->INTENB0_b.SOFE = 1;
+      case RUSB2_INTSTS0_DVSQ_STATE_DEF:
+        process_bus_reset(rhport);
+        break;
+
+      case RUSB2_INTSTS0_DVSQ_STATE_ADDR:
+        process_set_address(rhport);
+        break;
+
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP0:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP1:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP2:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP3:
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+#if (0 == USE_SOF)
+        rusb->INTENB0_b.SOFE = 1;
 #endif
-    default:
-      break;
+
+      default: break;
     }
   }
-  if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
-    RUSB2->NRDYSTS = 0;
+
+  if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
+    rusb->NRDYSTS = 0;
   }
-  if (is0 & RUSB2_INTSTS0_CTRT_Msk) {
-    if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) {
+
+  // Control transfer stage changes
+  if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) {
+    if ( is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA ) {
       /* A setup packet has been received. */
       process_setup_packet(rhport);
-    } else if (0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk)) {
+    } else if ( 0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk) ) {
       /* A ZLP has been sent/received. */
       process_status_completion(rhport);
     }
   }
-  if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
-    const unsigned s = RUSB2->BEMPSTS;
-    RUSB2->BEMPSTS = 0;
-    if (s & 1) {
+
+  // Buffer empty
+  if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) {
+    const unsigned s = rusb->BEMPSTS;
+    rusb->BEMPSTS = 0;
+    if ( s & 1 ) {
       process_pipe0_bemp(rhport);
     }
   }
-  if (is0 & RUSB2_INTSTS0_BRDY_Msk) {
-    const unsigned m = RUSB2->BRDYENB;
-    unsigned s = RUSB2->BRDYSTS & m;
+
+  // Buffer ready
+  if ( is0 & RUSB2_INTSTS0_BRDY_Msk ) {
+    const unsigned m = rusb->BRDYENB;
+    unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    RUSB2->BRDYSTS = ~s;
+    rusb->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       static const int Mod37BitPosition[] = {
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index ca7c38907..0dc59331a 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -76,38 +76,34 @@ static rusb2_controller_t rusb2_controller[] = {
     #endif
 };
 
-TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
-{
-  #if RUSB2_CONTROLLER_COUNT > 1
+#define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
+  uint32_t const mask = 1U << (11+rhport);
+  if (start) {
+    R_MSTP->MSTPCRB &= ~mask;
+  }else {
+    R_MSTP->MSTPCRB |= mask;
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) {
   NVIC_EnableIRQ(rusb2_controller[rhport].irqnum);
-  #else
-  (void) rhport;
-  NVIC_EnableIRQ(rusb2_controller[0].irqnum);
-  #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
-{
-  #if RUSB2_CONTROLLER_COUNT > 1
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) {
   NVIC_DisableIRQ(rusb2_controller[rhport].irqnum);
-  #else
-  (void) rhport;
-  NVIC_DisableIRQ(rusb2_controller[0].irqnum);
-  #endif
 }
 
 // MCU specific PHY init
-TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) {
 }
 
+//--------------------------------------------------------------------+
+// Application API for setting IRQ number
+//--------------------------------------------------------------------+
 void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
-  #if RUSB2_CONTROLLER_COUNT > 1
   rusb2_controller[rhport].irqnum = irqnum;
-  #else
-  (void) rhport;
-  rusb2_controller[0].irqnum = irqnum;
-  #endif
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index 397c0d56c..d7f4e0b42 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -37,6 +37,12 @@ extern "C" {
 
 #define RUSB2_REG_BASE (0x000A0000)
 
+// Start/Stop MSTP TODO implement later
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
+  (void) rhport;
+  (void) start;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 0928f5aeb..b704626f6 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -1653,6 +1653,7 @@ TU_ATTR_BIT_FIELD_ORDER_END
 
 #define RUSB2_DVSTCTR0_RHST_LS          (1U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
 #define RUSB2_DVSTCTR0_RHST_FS          (2U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+#define RUSB2_DVSTCTR0_RHST_HS          (3U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
 
 #define RUSB2_DEVADD_USBSPD_LS          (1U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
 #define RUSB2_DEVADD_USBSPD_FS          (2U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */
-- 
cgit v1.3.1


From 1eefc2b3ef2e268e839002a8b5221eebe26f6cd3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Jul 2023 19:35:42 +0700
Subject: more multiple ports update

---
 src/portable/renesas/rusb2/dcd_rusb2.c  | 344 ++++++++++++++++++--------------
 src/portable/renesas/rusb2/rusb2_rx.h   |   2 +
 src/portable/renesas/rusb2/rusb2_type.h |   9 +-
 3 files changed, 208 insertions(+), 147 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 27d525b68..833737181 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -63,22 +63,11 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-/* LINK core registers */
-#if defined(__CCRX__)
-  #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE)
-#elif defined(__RX__)
-  #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE)
-#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
-#else
-  #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE)
-#endif
-
 /* Start of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct TU_ATTR_PACKED {
+typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
   union {
     struct {
       uint16_t      : 8;
@@ -186,52 +175,53 @@ static unsigned find_pipe(unsigned xfer)
   return 0;
 }
 
-static volatile uint16_t* get_pipectr(unsigned num)
+static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
 {
   if (num) {
-    return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]);
+    return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
   } else {
-    return (volatile uint16_t*)&(RUSB2->DCPCTR);
+    return (volatile uint16_t*)&(rusb->DCPCTR);
   }
 }
 
-static volatile reg_pipetre_t* get_pipetre(unsigned num)
+static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E);
+    tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
   }
   return tre;
 }
 
 static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
 {
-  (void)rhport;
+  rusb2_reg_t *rusb = RUSB2_REG(rhport);
   const unsigned epn = tu_edpt_number(ep_addr);
+
   if (epn) {
     const unsigned dir = tu_edpt_dir(ep_addr);
     const unsigned num = _dcd.ep[dir][epn];
-    return get_pipectr(num);
+    return get_pipectr(rusb, num);
   } else {
-    return get_pipectr(0);
+    return get_pipectr(rusb, 0);
   }
 }
 
-static unsigned edpt0_max_packet_size(void)
+static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb)
 {
-  return RUSB2->DCPMAXP_b.MXPS;
+  return rusb->DCPMAXP_b.MXPS;
 }
 
-static unsigned edpt_max_packet_size(unsigned num)
+static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num)
 {
-  RUSB2->PIPESEL = num;
-  return RUSB2->PIPEMAXP;
+  rusb->PIPESEL = num;
+  return rusb->PIPEMAXP;
 }
 
-static inline void pipe_wait_for_ready(unsigned num)
+static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
 {
-  while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ;
-  while (!RUSB2->D0FIFOCTR_b.FRDY) ;
+  while ( rusb->D0FIFOSEL_b.CURPIPE != num ) {}
+  while ( !rusb->D0FIFOCTR_b.FRDY ) {}
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -284,61 +274,70 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
   ops[dir].tu_fifo_advance(f, total_len - rem);
 }
 
-static bool pipe0_xfer_in(void)
+static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
   const unsigned rem = pipe->remaining;
+
   if (!rem) {
     pipe->buf = NULL;
     return true;
   }
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned len = TU_MIN(mps, rem);
+
+  const uint16_t mps = edpt0_max_packet_size(rusb);
+  const uint16_t len = tu_min16(mps, rem);
   void          *buf = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+      pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
+
   pipe->remaining = rem - len;
   return false;
 }
 
-static bool pipe0_xfer_out(void)
+static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
   const unsigned rem = pipe->remaining;
 
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = RUSB2->CFIFOCTR_b.DTLN;
-  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  const uint16_t mps = edpt0_max_packet_size(rusb);
+  const uint16_t vld = rusb->CFIFOCTR_b.DTLN;
+  const uint16_t len = tu_min16(tu_min16(rem, mps), vld);
   void          *buf = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+      pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
+
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
+
   return false;
 }
 
-static bool pipe_xfer_in(unsigned num)
+static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_dcd.pipe[num];
   const unsigned rem  = pipe->remaining;
@@ -348,119 +347,141 @@ static bool pipe_xfer_in(unsigned num)
     return true;
   }
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned len  = TU_MIN(rem, mps);
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+  const uint16_t mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+  const uint16_t len  = tu_min16(rem, mps);
   void          *buf  = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+      pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
   pipe->remaining = rem - len;
+
   return false;
 }
 
-static bool pipe_xfer_out(unsigned num)
+static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_dcd.pipe[num];
-  const unsigned rem  = pipe->remaining;
+  const uint16_t rem  = pipe->remaining;
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned vld  = RUSB2->D0FIFOCTR_b.DTLN;
-  const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
+  const uint16_t mps = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+
+  const uint16_t vld  = rusb->D0FIFOCTR_b.DTLN;
+  const uint16_t len  = tu_min16(tu_min16(rem, mps), vld);
   void          *buf  = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+      pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return NULL != buf;
   }
+
   return false;
 }
 
 static void process_setup_packet(uint8_t rhport)
 {
-  uint16_t setup_packet[4];
-  if (0 == (RUSB2->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
-  RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
-  setup_packet[0] = tu_le16toh(RUSB2->USBREQ);
-  setup_packet[1] = RUSB2->USBVAL;
-  setup_packet[2] = RUSB2->USBINDX;
-  setup_packet[3] = RUSB2->USBLENG;
-  RUSB2->INTSTS0 = ~((uint16_t)RUSB2_INTSTS0_VALID_Msk);
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  if (0 == (rusb->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
+
+  rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  uint16_t setup_packet[4] = {
+      tu_htole16(rusb->USBREQ),
+      tu_htole16(rusb->USBVAL),
+      tu_htole16(rusb->USBINDX),
+      tu_htole16(rusb->USBLENG)
+  };
+
+  rusb->INTSTS0 = ~((uint16_t) RUSB2_INTSTS0_VALID_Msk);
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
 }
 
 static void process_status_completion(uint8_t rhport)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   uint8_t ep_addr;
   /* Check the data stage direction */
-  if (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
+  if (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
     /* IN transfer. */
     ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
   } else {
     /* OUT transfer. */
     ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
   }
+
   dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
 }
 
-static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+static bool process_pipe0_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
   /* configure fifo direction and access unit settings */
-  if (ep_addr) { /* IN, 2 bytes */
-    RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
-                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-    while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
-  } else { /* OUT, a byte */
-    RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
-    while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
+  if ( ep_addr ) {
+    /* IN, 2 bytes */
+    rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+                     (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+    while ( !(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ) {}
+  } else {
+    /* OUT, a byte */
+    rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while ( rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE ) {}
   }
 
   pipe_state_t *pipe = &_dcd.pipe[0];
   pipe->ff        = buffer_type;
   pipe->length    = total_bytes;
   pipe->remaining = total_bytes;
-  if (total_bytes) {
-    pipe->buf     = buffer;
-    if (ep_addr) { /* IN */
-      TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80));
-      pipe0_xfer_in();
+
+  if ( total_bytes ) {
+    pipe->buf = buffer;
+    if ( ep_addr ) {
+      /* IN */
+      TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
+      pipe0_xfer_in(rusb);
     }
-    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   } else {
     /* ZLP */
-    pipe->buf        = NULL;
-    RUSB2->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
+    pipe->buf = NULL;
+    rusb->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
   }
+
   return true;
 }
 
-static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+static bool process_pipe_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
   const unsigned epn = tu_edpt_number(ep_addr);
   const unsigned dir = tu_edpt_dir(ep_addr);
@@ -473,49 +494,55 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
   pipe->buf       = buffer;
   pipe->length    = total_bytes;
   pipe->remaining = total_bytes;
-  if (dir) { /* IN */
+
+  if (dir) {
+    /* IN */
     if (total_bytes) {
-      pipe_xfer_in(num);
-    } else { /* ZLP */
-      RUSB2->D0FIFOSEL = num;
-      pipe_wait_for_ready(num);
-      RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
-      RUSB2->D0FIFOSEL = 0;
-      while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+      pipe_xfer_in(rusb, num);
+    } else {
+      /* ZLP */
+      rusb->D0FIFOSEL = num;
+      pipe_wait_for_ready(rusb, num);
+      rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->D0FIFOSEL = 0;
+      /* if CURPIPE bits changes, check written value */
+      while (rusb->D0FIFOSEL_b.CURPIPE) {}
     }
   } else {
-#if defined(__CCRX__)
-    __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num);
-#else
-    volatile reg_pipetre_t *pt = get_pipetre(num);
-#endif
+    // OUT
+    volatile reg_pipetre_t *pt = get_pipetre(rusb, num);
+
     if (pt) {
-      const unsigned     mps = edpt_max_packet_size(num);
-      volatile uint16_t *ctr = get_pipectr(num);
+      const uint16_t     mps = edpt_max_packet_size(rusb, num);
+      volatile uint16_t *ctr = get_pipectr(rusb, num);
+
       if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
+
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (total_bytes + mps - 1) / mps;
       pt->TRENB = 1;
       *ctr = RUSB2_PIPE_CTR_PID_BUF;
     }
   }
-  //  TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
+
+  //  TU_LOG2("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
   return true;
 }
 
-static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
   const unsigned epn = tu_edpt_number(ep_addr);
   if (0 == epn) {
-    return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes);
+    return process_pipe0_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
   } else {
-    return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes);
+    return process_pipe_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
   }
 }
 
 static void process_pipe0_bemp(uint8_t rhport)
 {
-  bool completed = pipe0_xfer_in();
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  bool completed = pipe0_xfer_in(rusb);
   if (completed) {
     pipe_state_t *pipe = &_dcd.pipe[0];
     dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
@@ -525,17 +552,20 @@ static void process_pipe0_bemp(uint8_t rhport)
 
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   pipe_state_t  *pipe = &_dcd.pipe[num];
   const unsigned dir  = tu_edpt_dir(pipe->ep);
   bool completed;
 
-  if (dir) { /* IN */
-    completed = pipe_xfer_in(num);
+  if (dir) {
+    /* IN */
+    completed = pipe_xfer_in(rusb, num);
   } else {
+    // OUT
     if (num) {
-      completed = pipe_xfer_out(num);
+      completed = pipe_xfer_out(rusb, num);
     } else {
-      completed = pipe0_xfer_out();
+      completed = pipe0_xfer_out(rusb);
     }
   }
   if (completed) {
@@ -606,8 +636,10 @@ static void process_bus_reset(uint8_t rhport)
 
 static void process_set_address(uint8_t rhport)
 {
-  const uint32_t addr = RUSB2->USBADDR & 0xFF;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  const uint32_t addr = rusb->USBADDR & 0xFF;
   if (!addr) return;
+
   const tusb_control_request_t setup_packet = {
 #if defined(__CCRX__)
       .bmRequestType = { 0 },  /* Note: CCRX needs the braces over this struct member */
@@ -618,8 +650,9 @@ static void process_set_address(uint8_t rhport)
       .wValue        = addr,
       .wIndex        = 0,
       .wLength       = 0,
-    };
-  dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true);
+  };
+
+  dcd_event_setup_received(rhport, (const uint8_t *) &setup_packet, true);
 }
 
 /*------------------------------------------------------------------*/
@@ -704,7 +737,7 @@ void dcd_init(uint8_t rhport)
   rusb->INTSTS0 = 0;
   rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
                   RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
-                  RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
+                  RUSB2_INTSTS0_RESM_Msk;
   rusb->BEMPENB = 1;
   rusb->BRDYENB = 1;
 
@@ -766,33 +799,43 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 {
   (void)rhport;
 
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
   const unsigned ep_addr = ep_desc->bEndpointAddress;
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned dir     = tu_edpt_dir(ep_addr);
   const unsigned xfer    = ep_desc->bmAttributes.xfer;
 
   const unsigned mps = tu_edpt_packet_size(ep_desc);
-  if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
-    /* USBa supports up to 256 bytes */
-    return false;
+
+  if (xfer == TUSB_XFER_ISOCHRONOUS) {
+    // Fullspeed ISO is limit to 256 bytes
+    if ( !is_highspeed(rhport) && mps > 256) {
+      return false;
+    }
   }
 
   const unsigned num = find_pipe(xfer);
-  if (!num) return false;
+  TU_ASSERT(num);
+
   _dcd.pipe[num].ep = ep_addr;
   _dcd.ep[dir][epn] = num;
 
   /* setup pipe */
   dcd_int_disable(rhport);
-  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  RUSB2->PIPEBUF = 0x7C08;
-  #endif
-  RUSB2->PIPESEL = num;
-  RUSB2->PIPEMAXP = mps;
-  volatile uint16_t *ctr = get_pipectr(num);
+
+  if ( is_highspeed(rhport) ) {
+    // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
+    // depending on the allocation scheme
+    rusb->PIPEBUF = 0x7C08;
+  }
+
+  rusb->PIPESEL = num;
+  rusb->PIPEMAXP = mps;
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
   *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
   unsigned cfg = (dir << 4) | epn;
+
   if (xfer == TUSB_XFER_BULK) {
     cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk);
   } else if (xfer == TUSB_XFER_INTERRUPT) {
@@ -800,13 +843,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   } else {
     cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk);
   }
-  RUSB2->PIPECFG = cfg;
-  RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num);
-  RUSB2->BRDYENB |= TU_BIT(num);
+
+  rusb->PIPECFG = cfg;
+  rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  rusb->BRDYENB |= TU_BIT(num);
+
   if (dir || (xfer != TUSB_XFER_BULK)) {
     *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
-  // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP);
+
+  // TU_LOG1("O %d %x %x\r\n", rusb->PIPESEL, rusb->PIPECFG, rusb->PIPEMAXP);
   dcd_int_enable(rhport);
 
   return true;
@@ -826,26 +872,28 @@ void dcd_edpt_close_all(uint8_t rhport)
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
-  (void)rhport;
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
   const unsigned epn = tu_edpt_number(ep_addr);
   const unsigned dir = tu_edpt_dir(ep_addr);
   const unsigned num = _dcd.ep[dir][epn];
 
-  RUSB2->BRDYENB &= ~TU_BIT(num);
-  volatile uint16_t *ctr = get_pipectr(num);
+  rusb->BRDYENB &= ~TU_BIT(num);
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
   *ctr = 0;
-  RUSB2->PIPESEL = num;
-  RUSB2->PIPECFG = 0;
+  rusb->PIPESEL = num;
+  rusb->PIPECFG = 0;
   _dcd.pipe[num].ep = 0;
   _dcd.ep[dir][epn] = 0;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
-  bool r;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   dcd_int_disable(rhport);
-  r = process_edpt_xfer(0, ep_addr, buffer, total_bytes);
+  bool r = process_edpt_xfer(rusb, 0, ep_addr, buffer, total_bytes);
   dcd_int_enable(rhport);
+
   return r;
 }
 
@@ -853,10 +901,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
 {
   // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
   TU_ASSERT(ff->item_size == 1);
-  bool r;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   dcd_int_disable(rhport);
-  r = process_edpt_xfer(1, ep_addr, ff, total_bytes);
+  bool r = process_edpt_xfer(rusb, 1, ep_addr, ff, total_bytes);
   dcd_int_enable(rhport);
+
   return r;
 }
 
@@ -873,8 +923,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
   volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
   if (!ctr) return;
+
   dcd_int_disable(rhport);
   *ctr = RUSB2_PIPE_CTR_SQCLR_Msk;
 
@@ -882,8 +934,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
     *ctr = RUSB2_PIPE_CTR_PID_BUF;
   } else {
     const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
-    RUSB2->PIPESEL = num;
-    if (RUSB2->PIPECFG_b.TYPE != 1) {
+    rusb->PIPESEL = num;
+    if (rusb->PIPECFG_b.TYPE != 1) {
       *ctr = RUSB2_PIPE_CTR_PID_BUF;
     }
   }
@@ -953,9 +1005,9 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
 
-  if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
-    rusb->NRDYSTS = 0;
-  }
+//  if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
+//    rusb->NRDYSTS = 0;
+//  }
 
   // Control transfer stage changes
   if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) {
@@ -970,7 +1022,7 @@ void dcd_int_handler(uint8_t rhport)
 
   // Buffer empty
   if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) {
-    const unsigned s = rusb->BEMPSTS;
+    const uint16_t s = rusb->BEMPSTS;
     rusb->BEMPSTS = 0;
     if ( s & 1 ) {
       process_pipe0_bemp(rhport);
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index d7f4e0b42..21b2527c3 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -37,6 +37,8 @@ extern "C" {
 
 #define RUSB2_REG_BASE (0x000A0000)
 
+#define RUSB2_REG(_p)      ((rusb2_reg_t *) RUSB2_REG_BASE)
+
 // Start/Stop MSTP TODO implement later
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index b704626f6..7a5e37089 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -33,6 +33,13 @@
 extern "C" {
 #endif
 
+// CCRX specific attribute to generate a Code that Accesses Variables in the Declared Size
+#ifdef __CCRX__
+  #define _ccrx_evenaccess __evenaccess
+#else
+  #define _ccrx_evenaccess
+#endif
+
 /*--------------------------------------------------------------------*/
 /* Register Definitions                                           */
 /*--------------------------------------------------------------------*/
@@ -64,7 +71,7 @@ typedef struct {
 
 
 /* RUSB2 Registers Structure */
-typedef struct {
+typedef struct _ccrx_evenaccess {
   union {
     volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
 
-- 
cgit v1.3.1


From c53acb145589e2733b7d1abe012e85ae590bffb7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Jul 2023 20:10:58 +0700
Subject: fix build with rx

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 37 +++++++++++++++++++---------------
 src/portable/renesas/rusb2/rusb2_ra.h  |  4 ++--
 src/portable/renesas/rusb2/rusb2_rx.h  |  5 ++++-
 3 files changed, 27 insertions(+), 19 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 833737181..81b60b3bc 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -36,12 +36,6 @@
 #include "device/dcd.h"
 #include "rusb2_type.h"
 
-#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
-// fallback
-#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_DEVICE
-#define CFG_TUSB_RHPORT1_MODE   0
-#endif
-
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
@@ -86,7 +80,7 @@ typedef union TU_ATTR_PACKED {
     volatile uint8_t reserved8;
   };
   volatile uint16_t u16;
-} hw_fifo_t;
+} hw_fifo16_t;
 
 typedef union TU_ATTR_PACKED {
   struct {
@@ -140,9 +134,11 @@ static dcd_data_t _dcd;
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) {
-  return rhport == 1;
-}
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  #define is_highspeed_usbip(_p) (_p == 1)
+#else
+  #define is_highspeed_usbip(_p) (false)
+#endif
 
 static unsigned find_pipe(unsigned xfer)
 {
@@ -229,14 +225,17 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
   volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo;
 #else
-  volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo;
+  volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
 #endif
+
   uintptr_t addr = (uintptr_t)buf;
+
   while (len >= 2) {
     reg->u16 = *(const uint16_t *)addr;
     addr += 2;
     len  -= 2;
   }
+
   if (len > 0) {
     reg->u8 = *(const uint8_t *)addr;
     ++addr;
@@ -260,11 +259,14 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
     /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
     /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
   };
+
   tu_fifo_buffer_info_t info;
   ops[dir].tu_fifo_get_info(f, &info);
+
   unsigned total_len = len;
   len = TU_MIN(total_len, info.len_lin);
   ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+
   unsigned rem = total_len - len;
   if (rem) {
     len = TU_MIN(rem, info.len_wrap);
@@ -689,7 +691,8 @@ void dcd_init(uint8_t rhport)
 
   rusb2_module_start(rhport, true);
 
-  if ( is_highspeed(rhport) ) {
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  if ( is_highspeed_usbip(rhport) ) {
     rusb->SYSCFG_b.HSE = 1;
 
     // leave CLKSEL as default (0x11) 24Mhz
@@ -715,7 +718,9 @@ void dcd_init(uint8_t rhport)
     rusb->CFIFOSEL_b.MBW = 1;
     rusb->D0FIFOSEL_b.MBW = 1;
     rusb->D1FIFOSEL_b.MBW = 1;
-  } else {
+  } else
+#endif
+  {
     rusb->SYSCFG_b.SCKE = 1;
     while (!rusb->SYSCFG_b.SCKE) {}
     rusb->SYSCFG_b.DRPD = 0;
@@ -772,7 +777,7 @@ void dcd_connect(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
-  if ( is_highspeed(rhport)) {
+  if ( is_highspeed_usbip(rhport)) {
     rusb->SYSCFG_b.CNEN = 1;
   }
   rusb->SYSCFG_b.DPRPU = 1;
@@ -809,7 +814,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   if (xfer == TUSB_XFER_ISOCHRONOUS) {
     // Fullspeed ISO is limit to 256 bytes
-    if ( !is_highspeed(rhport) && mps > 256) {
+    if ( !is_highspeed_usbip(rhport) && mps > 256) {
       return false;
     }
   }
@@ -823,7 +828,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   /* setup pipe */
   dcd_int_disable(rhport);
 
-  if ( is_highspeed(rhport) ) {
+  if ( is_highspeed_usbip(rhport) ) {
     // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
     // depending on the allocation scheme
     rusb->PIPEBUF = 0x7C08;
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 0dc59331a..e04a99685 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -62,7 +62,7 @@ typedef struct {
 }rusb2_controller_t;
 
 #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
-  #define RUSB2_HAS_HIGHSPEED
+  #define RUSB2_SUPPORT_HIGHSPEED
   #define RUSB2_CONTROLLER_COUNT 2
 #else
   #define RUSB2_CONTROLLER_COUNT 1
@@ -71,7 +71,7 @@ typedef struct {
 // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
 static rusb2_controller_t rusb2_controller[] = {
     { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
-    #ifdef RUSB2_HAS_HIGHSPEED
+    #ifdef RUSB2_SUPPORT_HIGHSPEED
     { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
     #endif
 };
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index 21b2527c3..17b9a918c 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -37,7 +37,10 @@ extern "C" {
 
 #define RUSB2_REG_BASE (0x000A0000)
 
-#define RUSB2_REG(_p)      ((rusb2_reg_t *) RUSB2_REG_BASE)
+TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) {
+  (void) rhport;
+  return (rusb2_reg_t *) RUSB2_REG_BASE;
+}
 
 // Start/Stop MSTP TODO implement later
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
-- 
cgit v1.3.1


From 4c156100fafa682407f1a9a459d8b8800a029446 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 12:27:18 +0700
Subject: use unaligned access read for hw fifo

---
 src/common/tusb_common.h               | 18 ++++++--
 src/common/tusb_mcu.h                  | 12 ++++--
 src/portable/renesas/rusb2/dcd_rusb2.c | 77 +++++++++++++++++++++-------------
 3 files changed, 71 insertions(+), 36 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 957491aa9..576cb123f 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -260,11 +260,21 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_
 #else
 
 // MCU that could access unaligned memory natively
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32  (const void* mem) { return *((uint32_t const *) mem); }
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16  (const void* mem) { return *((uint16_t const *) mem); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) {
+  return *((uint32_t const *) mem);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) {
+  return *((uint16_t const *) mem);
+}
 
-TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; }
-TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; }
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) {
+  *((uint32_t *) mem) = value;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) {
+  *((uint16_t *) mem) = value;
+}
 
 #endif
 
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 496ebfc85..89f89182e 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -34,10 +34,16 @@
 
 //------------- Unaligned Memory Access -------------//
 
-// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
-#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
-  #define TUP_ARCH_STRICT_ALIGN   0
+#ifdef __ARM_ARCH
+  // ARM Architecture set __ARM_FEATURE_UNALIGNED to 1 for mcu supports unaligned access
+  #if defined(__ARM_FEATURE_UNALIGNED) && __ARM_FEATURE_UNALIGNED == 1
+    #define TUP_ARCH_STRICT_ALIGN   0
+  #else
+    #define TUP_ARCH_STRICT_ALIGN   1
+  #endif
 #else
+  // TODO default to strict align for others
+  // Should investigate other architecture such as risv, xtensa, mips for optimal setting
   #define TUP_ARCH_STRICT_ALIGN   1
 #endif
 
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 81b60b3bc..464929224 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -220,6 +220,11 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
   while ( !rusb->D0FIFOCTR_b.FRDY ) {}
 }
 
+//--------------------------------------------------------------------+
+// Pipe FIFO
+//--------------------------------------------------------------------+
+
+// Write data buffer --> hw fifo
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
 #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
@@ -228,54 +233,68 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
   volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
 #endif
 
-  uintptr_t addr = (uintptr_t)buf;
+  uint8_t const* buf8 = (uint8_t const*) buf;
 
   while (len >= 2) {
-    reg->u16 = *(const uint16_t *)addr;
-    addr += 2;
+    reg->u16 = tu_unaligned_read16(buf8);
+    buf8 += 2;
     len  -= 2;
   }
 
   if (len > 0) {
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
+    reg->u8 = *buf8;
+    ++buf8;
   }
 }
 
+// Read data buffer <-- hw fifo
 static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
 {
-  uint8_t *p   = (uint8_t*)buf;
+  uint8_t *p = (uint8_t*)buf;
   volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
   while (len--) *p++ = *reg;
 }
 
-static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
-{
-  static const struct {
-    void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
-    void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
-    void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
-  } ops[] = {
-    /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
-    /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
-  };
+// Write data sw fifo --> hw fifo
+static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_read_info(f, &info);
+
+  uint16_t count = tu_min16(total_len, info.len_lin);
+  pipe_write_packet(info.ptr_lin, fifo, count);
+
+  uint16_t rem = total_len - count;
+  if (rem) {
+    rem = tu_min16(rem, info.len_wrap);
+    pipe_write_packet(info.ptr_wrap, fifo, rem);
+    count += rem;
+  }
+
+  tu_fifo_advance_read_pointer(f, count);
+}
 
+// Read data sw fifo <-- hw fifo
+static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
   tu_fifo_buffer_info_t info;
-  ops[dir].tu_fifo_get_info(f, &info);
+  tu_fifo_get_write_info(f, &info);
 
-  unsigned total_len = len;
-  len = TU_MIN(total_len, info.len_lin);
-  ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+  uint16_t count = tu_min16(total_len, info.len_lin);
+  pipe_read_packet(info.ptr_lin, fifo, count);
 
-  unsigned rem = total_len - len;
+  uint16_t rem = total_len - count;
   if (rem) {
-    len = TU_MIN(rem, info.len_wrap);
-    ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
-    rem -= len;
+    rem = tu_min16(rem, info.len_wrap);
+    pipe_read_packet(info.ptr_wrap, fifo, rem);
+    count += rem;
   }
-  ops[dir].tu_fifo_advance(f, total_len - rem);
+
+  tu_fifo_advance_write_pointer(f, count);
 }
 
+//--------------------------------------------------------------------+
+// Pipe Transfer
+//--------------------------------------------------------------------+
+
 static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
@@ -292,7 +311,7 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN);
+      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
       pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -319,7 +338,7 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT);
+      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
       pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -357,7 +376,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN);
+      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
       pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -391,7 +410,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT);
+      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
       pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
-- 
cgit v1.3.1


From e0f1ba8b0e9cf46fabcddc72a61d5515df424edf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 16:07:11 +0700
Subject: fully work with multiple ports without CFG_TUSB_RHPORT0/1

---
 hw/bsp/family_support.cmake             |  4 +-
 hw/bsp/ra/boards/ra6m5_ek/board.cmake   |  7 ---
 src/portable/renesas/rusb2/dcd_rusb2.c  | 85 ++++++++++++++-------------------
 src/portable/renesas/rusb2/rusb2_type.h |  1 +
 4 files changed, 39 insertions(+), 58 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 5b97eb5e4..d8298c8ad 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -227,8 +227,8 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS)
 
   if (DEFINED LOG)
     target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG})
-    if (LOG STREQUAL "3")
-      # no inline for debug level 3
+    if (LOG STREQUAL "4")
+      # no inline for debug level 4
       target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=)
     endif ()
   endif()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
index d934a0c0d..5a615f9b0 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -14,11 +14,4 @@ function(update_board TARGET)
     # port 0 is fullspeed, port 1 is highspeed
     BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
     )
-
-  if (PORT STREQUAL 1)
-    target_compile_definitions(${TARGET} PUBLIC
-      CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED
-      CFG_TUSB_RHPORT0_MODE=0
-      )
-  endif ()
 endfunction()
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 464929224..3d3e52bfa 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -74,26 +74,6 @@ typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
   uint16_t TRN;
 } reg_pipetre_t;
 
-typedef union TU_ATTR_PACKED {
-  struct {
-    volatile uint8_t u8;
-    volatile uint8_t reserved8;
-  };
-  volatile uint16_t u16;
-} hw_fifo16_t;
-
-typedef union TU_ATTR_PACKED {
-  struct {
-    volatile uint8_t reserved8[3];
-    volatile uint8_t u8;
-  };
-  struct {
-    volatile uint16_t reserved16;
-    volatile uint16_t u16;
-  };
-  volatile uint32_t u32;
-} hw_fifo32_t;
-
 typedef struct TU_ATTR_PACKED
 {
   void      *buf;      /* the start address of a transfer data buffer */
@@ -135,9 +115,11 @@ static dcd_data_t _dcd;
 //--------------------------------------------------------------------+
 
 #ifdef RUSB2_SUPPORT_HIGHSPEED
-  #define is_highspeed_usbip(_p) (_p == 1)
+  #define is_highspeed_usbip(_p)     (_p == 1)
+  #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1))
 #else
-  #define is_highspeed_usbip(_p) (false)
+  #define is_highspeed_usbip(_p)     (false)
+  #define is_highspeed_regbase(_reg) (false)
 #endif
 
 static unsigned find_pipe(unsigned xfer)
@@ -225,48 +207,57 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
 //--------------------------------------------------------------------+
 
 // Write data buffer --> hw fifo
-static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
+static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
 {
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo;
-#else
-  volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
-#endif
+  (void) rusb;
+
+  volatile uint16_t *ff16;
+  volatile uint8_t *ff8;
+
+  // Highspeed FIFO is 32-bit
+  if ( is_highspeed_regbase(rusb) ) {
+    ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
+    ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
+  }else {
+    ff16 = (volatile uint16_t*) fifo;
+    ff8  = ((volatile uint8_t*) fifo);
+  }
 
   uint8_t const* buf8 = (uint8_t const*) buf;
 
   while (len >= 2) {
-    reg->u16 = tu_unaligned_read16(buf8);
+    *ff16 = tu_unaligned_read16(buf8);
     buf8 += 2;
     len  -= 2;
   }
 
   if (len > 0) {
-    reg->u8 = *buf8;
+    *ff8 = *buf8;
     ++buf8;
   }
 }
 
 // Read data buffer <-- hw fifo
-static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
+static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
 {
+  (void) rusb;
   uint8_t *p = (uint8_t*)buf;
   volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
   while (len--) *p++ = *reg;
 }
 
 // Write data sw fifo --> hw fifo
-static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+static void pipe_write_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
   tu_fifo_buffer_info_t info;
   tu_fifo_get_read_info(f, &info);
 
   uint16_t count = tu_min16(total_len, info.len_lin);
-  pipe_write_packet(info.ptr_lin, fifo, count);
+  pipe_write_packet(rusb, info.ptr_lin, fifo, count);
 
   uint16_t rem = total_len - count;
   if (rem) {
     rem = tu_min16(rem, info.len_wrap);
-    pipe_write_packet(info.ptr_wrap, fifo, rem);
+    pipe_write_packet(rusb, info.ptr_wrap, fifo, rem);
     count += rem;
   }
 
@@ -274,17 +265,17 @@ static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t tot
 }
 
 // Read data sw fifo <-- hw fifo
-static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
   tu_fifo_buffer_info_t info;
   tu_fifo_get_write_info(f, &info);
 
   uint16_t count = tu_min16(total_len, info.len_lin);
-  pipe_read_packet(info.ptr_lin, fifo, count);
+  pipe_read_packet(rusb, info.ptr_lin, fifo, count);
 
   uint16_t rem = total_len - count;
   if (rem) {
     rem = tu_min16(rem, info.len_wrap);
-    pipe_read_packet(info.ptr_wrap, fifo, rem);
+    pipe_read_packet(rusb, info.ptr_wrap, fifo, rem);
     count += rem;
   }
 
@@ -311,9 +302,9 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
-      pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_write_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -338,9 +329,9 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
-      pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_read_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -376,9 +367,9 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
-      pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_write_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -410,9 +401,9 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
-      pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_read_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -733,10 +724,6 @@ void dcd_init(uint8_t rhport)
     // rusb2->BUSWAIT |= 0x0F00U;
 
     rusb->PHYSET_b.REPSEL = 1;
-
-    rusb->CFIFOSEL_b.MBW = 1;
-    rusb->D0FIFOSEL_b.MBW = 1;
-    rusb->D1FIFOSEL_b.MBW = 1;
   } else
 #endif
   {
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 7a5e37089..28cec9999 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -1670,6 +1670,7 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_FIFOSEL_BIGEND            (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
 #define RUSB2_FIFOSEL_MBW_8BIT          (0U << RUSB2_CFIFOSEL_MBW_Pos)    /* 8-bit width */
 #define RUSB2_FIFOSEL_MBW_16BIT         (1U << RUSB2_CFIFOSEL_MBW_Pos)    /* 16-bit width */
+#define RUSB2_FIFOSEL_MBW_32BIT         (2U << RUSB2_CFIFOSEL_MBW_Pos)    /* 32-bit width */
 
 #define RUSB2_INTSTS0_CTSQ_CTRL_RDATA   (1U << RUSB2_INTSTS0_CTSQ_Pos)
 
-- 
cgit v1.3.1


From 88478a9d052edc364561da39382faef72f937ecb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 16:24:22 +0700
Subject: add PORT selection for makefile

---
 hw/bsp/ra/boards/ra6m5_ek/board.mk     |  3 +++
 hw/bsp/ra/family.cmake                 |  2 +-
 hw/bsp/ra/family.mk                    | 12 ++++++++++++
 src/portable/renesas/rusb2/dcd_rusb2.c |  4 ++++
 4 files changed, 20 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk
index 567908b63..a5c933764 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.mk
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk
@@ -4,4 +4,7 @@ MCU_VARIANT = ra6m5
 # For flash-jlink target
 JLINK_DEVICE = R7FA6M5BH
 
+# Port 1 is highspeed
+PORT ?= 1
+
 flash: flash-jlink
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index eb2d4958f..f09e86a72 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS RA CACHE INTERNAL "")
+set(FAMILY_MCUS RAXXX CACHE INTERNAL "")
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index b6e1bb0ae..f5097460a 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -3,8 +3,12 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
 FSP_RA = hw/mcu/renesas/fsp/ra/fsp
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
+PORT ?= 0
+
 CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_RAXXX \
+  -DBOARD_TUD_RHPORT=$(PORT) \
 	-Wno-error=undef \
 	-Wno-error=strict-prototypes \
 	-Wno-error=cast-align \
@@ -15,6 +19,14 @@ CFLAGS += \
 	-nostartfiles \
 	-ffreestanding
 
+ifeq ($(PORT), 1)
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+  $(info "Using PORT 1 HighSpeed")
+else
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+  $(info "Using PORT 0 FullSpeed")
+endif
+
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 3d3e52bfa..17d22f696 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -216,6 +216,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
 
   // Highspeed FIFO is 32-bit
   if ( is_highspeed_regbase(rusb) ) {
+    // TODO 32-bit access for better performance
     ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
     ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
   }else {
@@ -241,6 +242,9 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
 static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
 {
   (void) rusb;
+
+  // TODO 16/32-bit access for better performance
+
   uint8_t *p = (uint8_t*)buf;
   volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
   while (len--) *p++ = *reg;
-- 
cgit v1.3.1


From 0f53e746ffa21b6186809b2b896ddc74d38e9058 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 18:41:16 +0700
Subject: move check highspeed to rusb_ra

---
 src/portable/renesas/rusb2/dcd_rusb2.c  | 31 +++++--------------------------
 src/portable/renesas/rusb2/rusb2_ra.h   | 15 +++++++++++----
 src/portable/renesas/rusb2/rusb2_rx.h   |  9 +++++++++
 src/portable/renesas/rusb2/rusb2_type.h | 14 ++++++++++++++
 4 files changed, 39 insertions(+), 30 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 17d22f696..358e5644b 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -61,19 +61,6 @@
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
-  union {
-    struct {
-      uint16_t      : 8;
-      uint16_t TRCLR: 1;
-      uint16_t TRENB: 1;
-      uint16_t      : 0;
-    };
-    uint16_t TRE;
-  };
-  uint16_t TRN;
-} reg_pipetre_t;
-
 typedef struct TU_ATTR_PACKED
 {
   void      *buf;      /* the start address of a transfer data buffer */
@@ -114,14 +101,6 @@ static dcd_data_t _dcd;
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-#ifdef RUSB2_SUPPORT_HIGHSPEED
-  #define is_highspeed_usbip(_p)     (_p == 1)
-  #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1))
-#else
-  #define is_highspeed_usbip(_p)     (false)
-  #define is_highspeed_regbase(_reg) (false)
-#endif
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -215,7 +194,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
   volatile uint8_t *ff8;
 
   // Highspeed FIFO is 32-bit
-  if ( is_highspeed_regbase(rusb) ) {
+  if ( rusb2_is_highspeed_reg(rusb) ) {
     // TODO 32-bit access for better performance
     ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
     ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
@@ -706,7 +685,7 @@ void dcd_init(uint8_t rhport)
   rusb2_module_start(rhport, true);
 
 #ifdef RUSB2_SUPPORT_HIGHSPEED
-  if ( is_highspeed_usbip(rhport) ) {
+  if ( rusb2_is_highspeed_rhport(rhport) ) {
     rusb->SYSCFG_b.HSE = 1;
 
     // leave CLKSEL as default (0x11) 24Mhz
@@ -787,7 +766,7 @@ void dcd_connect(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
-  if ( is_highspeed_usbip(rhport)) {
+  if ( rusb2_is_highspeed_rhport(rhport)) {
     rusb->SYSCFG_b.CNEN = 1;
   }
   rusb->SYSCFG_b.DPRPU = 1;
@@ -824,7 +803,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   if (xfer == TUSB_XFER_ISOCHRONOUS) {
     // Fullspeed ISO is limit to 256 bytes
-    if ( !is_highspeed_usbip(rhport) && mps > 256) {
+    if ( !rusb2_is_highspeed_rhport(rhport) && mps > 256) {
       return false;
     }
   }
@@ -838,7 +817,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   /* setup pipe */
   dcd_int_disable(rhport);
 
-  if ( is_highspeed_usbip(rhport) ) {
+  if ( rusb2_is_highspeed_rhport(rhport) ) {
     // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
     // depending on the allocation scheme
     rusb->PIPEBUF = 0x7C08;
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index e04a99685..28b690512 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -47,15 +47,15 @@ extern "C" {
 #pragma GCC diagnostic pop
 #endif
 
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
 // IAR does not have __builtin_ctz
 #if defined(__ICCARM__)
   #define __builtin_ctz(x)   __iar_builtin_CLZ(__iar_builtin_RBIT(x))
 #endif
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 typedef struct {
   uint32_t reg_base;
   int32_t irqnum;
@@ -78,6 +78,13 @@ static rusb2_controller_t rusb2_controller[] = {
 
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
+#define rusb2_is_highspeed_rhport(_p)  (_p == 1)
+#define rusb2_is_highspeed_reg(_reg)   (_reg == RUSB2_REG(1))
+
+//--------------------------------------------------------------------+
+// RUSB2 API
+//--------------------------------------------------------------------+
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
   uint32_t const mask = 1U << (11+rhport);
   if (start) {
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index 17b9a918c..7bf4be47e 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -42,6 +42,15 @@ TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) {
   return (rusb2_reg_t *) RUSB2_REG_BASE;
 }
 
+
+#define rusb2_is_highspeed_rhport(_p)  (false)
+#define rusb2_is_highspeed_reg(_reg)   (false)
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+
 // Start/Stop MSTP TODO implement later
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 28cec9999..aceeb3c3e 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -48,6 +48,20 @@ extern "C" {
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
+// TODO same as RUSB2_PIPE_TR_t
+typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
+  union {
+    struct {
+      uint16_t      : 8;
+      uint16_t TRCLR: 1;
+      uint16_t TRENB: 1;
+      uint16_t      : 0;
+    };
+    uint16_t TRE;
+  };
+  uint16_t TRN;
+} reg_pipetre_t;
+
 typedef struct {
   union {
     volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
-- 
cgit v1.3.1


From 3fdd2a40b2103089e47609a05577fc84b786ec4f Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Fri, 2 Jun 2023 15:04:53 +0200
Subject: osal_none: make it possible to override the task delay function

---
 src/host/usbh.c      | 2 +-
 src/osal/osal_none.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 184bda23b..1418cfb79 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -256,7 +256,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-void osal_task_delay(uint32_t msec)
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
 {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 5f407378e..76e77c25d 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -37,7 +37,7 @@
 
 #if CFG_TUH_ENABLED
 // currently only needed/available in host mode
-void osal_task_delay(uint32_t msec);
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec);
 #endif
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From e2f28bc134446dc081766055171ca427afd4f564 Mon Sep 17 00:00:00 2001
From: emb4fun <git@emb4fun.de>
Date: Sun, 23 Jul 2023 10:53:22 +0200
Subject: Added support for the NXP K64 series

---
 hw/bsp/board_mcu.h               |  2 +-
 src/common/tusb_mcu.h            |  2 +-
 src/portable/nxp/khci/dcd_khci.c | 14 ++++++++++++++
 src/tusb_option.h                |  1 +
 4 files changed, 17 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index e5d2bb608..3928435f0 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -47,7 +47,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
   #include "fsl_device_registers.h"
 
-#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L)
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64)
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 9f3be78fd..4a0c5acef 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -97,7 +97,7 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
-#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L)
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64)
   #define TUP_USBIP_CHIPIDEA_FS
   #define TUP_USBIP_CHIPIDEA_FS_KINETIS
   #define TUP_DCD_ENDPOINT_MAX    16
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 52f4145f2..d957338ad 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -269,8 +269,22 @@ void dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
+#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K64)
+  uint32_t clk_recover_irc_en;
+  uint32_t clk_recover_ctrl;
+  
+  clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN;
+  clk_recover_ctrl   = KHCI->CLK_RECOVER_CTRL;
+
+  KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
+  while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
+  KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
+  KHCI->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
+#else
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+#endif  
 
   tu_memclr(&_dcd, sizeof(_dcd));
   KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c792efe6a..bbaa2a53a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -121,6 +121,7 @@
 #define OPT_MCU_KINETIS_KL       1200 ///< NXP KL series
 #define OPT_MCU_KINETIS_K32L     1201 ///< NXP K32L series
 #define OPT_MCU_KINETIS_K32      1201 ///< Alias to K32L
+#define OPT_MCU_KINETIS_K64      1202 ///< NXP K64 series
 
 #define OPT_MCU_MKL25ZXX         1200 ///< Alias to KL (obsolete)
 #define OPT_MCU_K32L2BXX         1201 ///< Alias to K32 (obsolete)
-- 
cgit v1.3.1


From ef69da054e4d373636818a52df4e3433152fa3bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 25 Jul 2023 12:03:54 +0700
Subject: use standard EHCI USB INT instead of chipidea async/period interrupt
 to be compatible with other EHCI implementation

---
 src/portable/ehci/ehci.c | 24 ++++++++----------------
 src/portable/ehci/ehci.h |  6 +-----
 2 files changed, 9 insertions(+), 21 deletions(-)

(limited to 'src')

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 241393a39..a9e184f22 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -307,8 +307,8 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   regs->status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE);
 
   // Enable interrupts
-  regs->inten  = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE |
-                 EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
+  regs->inten  = EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
+                 EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
 
   //------------- Asynchronous List -------------//
   ehci_qhd_t * const async_head = list_get_async_head(rhport);
@@ -768,28 +768,20 @@ void hcd_int_handler(uint8_t rhport)
     regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
   }
 
+  // A USB transfer is completed with error
   if (int_status & EHCI_INT_MASK_ERROR) {
     xfer_error_isr(rhport);
     regs->status = EHCI_INT_MASK_ERROR; // Acknowledge
   }
 
-  //------------- some QTD/SITD/ITD with IOC set is completed -------------//
-  if (int_status & EHCI_INT_MASK_NXP_ASYNC) {
-    async_list_xfer_complete_isr(list_get_async_head(rhport));
-    regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge
-  }
-
-  if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
-  {
-    for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2)
-    {
+  // A USB transfer is completed
+  if (int_status & EHCI_INT_MASK_USB) {
+    for ( uint32_t i = 1; i <= FRAMELIST_SIZE; i *= 2 ) {
       period_list_xfer_complete_isr(rhport, i);
     }
-    regs->status = EHCI_INT_MASK_NXP_PERIODIC; // Acknowledge
-  }
 
-  if (int_status & EHCI_INT_MASK_USB) {
-    // TODO standard EHCI xfer complete
+    async_list_xfer_complete_isr(list_get_async_head(rhport));
+
     regs->status = EHCI_INT_MASK_USB; // Acknowledge
   }
 
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index 05de80539..457adc1d3 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -278,14 +278,10 @@ enum {
   EHCI_INT_MASK_PERIODIC_SCHED_STATUS = TU_BIT(14),
   EHCI_INT_MASK_ASYNC_SCHED_STATUS    = TU_BIT(15),
 
-  EHCI_INT_MASK_NXP_ASYNC             = TU_BIT(18),
-  EHCI_INT_MASK_NXP_PERIODIC          = TU_BIT(19),
-
   EHCI_INT_MASK_ALL                   =
       EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
       EHCI_INT_MASK_FRAMELIST_ROLLOVER | EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR |
-      EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF |
-      EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
+      EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF
 };
 
 enum {
-- 
cgit v1.3.1


From dc74e634f93962512229ba7d4e14467c16125c0d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 25 Jul 2023 12:35:40 +0700
Subject: fix unaligned hub status_change

---
 src/host/hub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/host/hub.c b/src/host/hub.c
index 182bd6ce8..16dd534d2 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -45,8 +45,8 @@ typedef struct
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t port_count;
-  uint8_t status_change; // data from status change interrupt endpoint
 
+  CFG_TUH_MEM_ALIGN uint8_t status_change;
   CFG_TUH_MEM_ALIGN hub_port_status_response_t port_status;
   CFG_TUH_MEM_ALIGN hub_status_response_t hub_status;
 } hub_interface_t;
-- 
cgit v1.3.1


From 4deea875793ce78a24b069491bb83e59e310c476 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 25 Jul 2023 15:07:21 +0700
Subject: improve processing usb complete and error isr.

also merge them together
---
 hw/bsp/imxrt/family.cmake | 120 ++++++++++++------------
 src/CMakeLists.txt        |   1 +
 src/portable/ehci/ehci.c  | 228 ++++++++++++----------------------------------
 3 files changed, 120 insertions(+), 229 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index f1c5b0ab1..96ed4b030 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -22,69 +22,71 @@ set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
-      #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c
-      ${SDK_DIR}/drivers/common/fsl_common.c
-      ${SDK_DIR}/drivers/igpio/fsl_gpio.c
-      ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
-      ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      __ARMVFP__=0
-      __ARMFPV5__=0
-      XIP_EXTERNAL_FLASH=1
-      XIP_BOOT_HEADER_ENABLE=1
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-      #${SDK_DIR}/drivers/adc_12b1msps_sar
-      ${SDK_DIR}/drivers/common
-      ${SDK_DIR}/drivers/igpio
-      ${SDK_DIR}/drivers/lpspi
-      ${SDK_DIR}/drivers/lpuart
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
+    #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c
+    ${SDK_DIR}/drivers/common/fsl_common.c
+    ${SDK_DIR}/drivers/igpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
+    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __ARMVFP__=0
+    __ARMFPV5__=0
+    XIP_EXTERNAL_FLASH=1
+    XIP_BOOT_HEADER_ENABLE=1
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    #${SDK_DIR}/drivers/adc_12b1msps_sar
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/igpio
+    ${SDK_DIR}/drivers/lpspi
+    ${SDK_DIR}/drivers/lpuart
+    )
 
-    # LD_FILE and STARTUP_FILE can be defined in board.cmake
-    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
-      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
-      #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
-    endif ()
+  update_board(${BOARD_TARGET})
 
-    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
-      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
-      #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
-    endif ()
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+    #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+  endif ()
 
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-      )
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+    #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+  endif ()
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        # force linker to look for these symbols
-        -Wl,-uimage_vector_table
-        -Wl,-ug_boot_data
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      # force linker to look for these symbols
+      -Wl,-uimage_vector_table
+      -Wl,-ug_boot_data
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
   endif ()
 endfunction()
 
@@ -114,7 +116,7 @@ function(family_configure_example TARGET RTOS)
 
   # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX ${RTOS})
-  target_sources(${TARGET}-tinyusb PUBLIC
+  target_sources(${TARGET}-tinyusb PRIVATE
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
     ${TOP}/src/portable/ehci/ehci.c
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 8f7f38589..076e1e1eb 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -64,6 +64,7 @@ function(add_tinyusb TARGET)
       -Wnull-dereference
       -Wuninitialized
       -Wunused
+      -Wunused-function
       -Wreturn-type
       -Wredundant-decls
       )
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index a9e184f22..b84de5191 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -314,11 +314,11 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   ehci_qhd_t * const async_head = list_get_async_head(rhport);
   tu_memclr(async_head, sizeof(ehci_qhd_t));
 
-  async_head->next.address                    = (uint32_t) async_head; // circular list, next is itself
-  async_head->next.type                       = EHCI_QTYPE_QHD;
-  async_head->head_list_flag                  = 1;
-  async_head->qtd_overlay.halted              = 1; // inactive most of time
-  async_head->qtd_overlay.next.terminate      = 1; // TODO removed if verified
+  async_head->next.address               = (uint32_t) async_head; // circular list, next is itself
+  async_head->next.type                  = EHCI_QTYPE_QHD;
+  async_head->head_list_flag             = 1;
+  async_head->qtd_overlay.halted         = 1; // inactive most of time
+  async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified
 
   regs->async_list_addr = (uint32_t) async_head;
 
@@ -533,70 +533,74 @@ void async_advance_isr(uint8_t rhport)
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void port_connect_status_change_isr(uint8_t rhport)
-{
+void port_connect_status_change_isr(uint8_t rhport) {
   // NOTE There is an sequence plug->unplug->…..-> plug if device is powering with pre-plugged device
-  if (ehci_data.regs->portsc_bm.current_connect_status)
-  {
+  if ( ehci_data.regs->portsc_bm.current_connect_status ) {
     hcd_port_reset(rhport);
     hcd_event_device_attach(rhport, true);
-  }else // device unplugged
+  } else // device unplugged
   {
     hcd_event_device_remove(rhport, true);
   }
 }
 
+// Check queue head for potential transfer complete (successful or error)
 TU_ATTR_ALWAYS_INLINE static inline
 void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
-  // examine TD attached to queue head
-  ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+  hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t)); // HC may have updated the overlay
+  volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay;
 
-  if (qtd == NULL) {
-    return; // no TD attached
-  }
+  // process non-active (completed) QHD with attached (scheduled) TD
+  if ( !qtd_overlay->active && qhd->attached_qtd != NULL ) {
+    xfer_result_t xfer_result;
 
-  hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
+    if ( qtd_overlay->halted ) {
+      if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
+        // Error count = 0 often occurs when device disconnected, or other bus-related error
+        xfer_result = XFER_RESULT_FAILED;
+        TU_LOG3("  QHD xfer err count: %d\n", qtd_overlay->err_count);
+        // TU_BREAKPOINT(); // TODO skip unplugged device
+      }else {
+        // no error bits are set, endpoint is halted due to STALL
+        xfer_result = XFER_RESULT_STALLED;
+      }
+    } else {
+      xfer_result = XFER_RESULT_SUCCESS;
+    }
 
-  // TD is still active, no need to process
-  if (qtd->active) {
-    return;
-  }
+    ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); // HC may have written back TD
 
-  uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
-  uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
+    uint8_t const dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
+    uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
 
-  // invalidate dcache if IN transfer
-  if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
-    hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
-  }
+    // invalidate dcache if IN transfer with data
+    if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
+      hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
+    }
 
-  // remove and free TD before invoking callback
-  qhd_remove_qtd(qhd);
+    // remove and free TD before invoking callback
+    qhd_remove_qtd(qhd);
 
-  // notify usbh
-  uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
-  hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true);
+    // notify usbh
+    uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
+    hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
+  }
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
+void proccess_async_xfer_isr(ehci_qhd_t * const list_head)
 {
-  ehci_qhd_t *p_qhd = async_head;
-  do
-  {
-    hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
-
-    // halted or error is processed in error isr
-    if ( !p_qhd->qtd_overlay.halted ) {
-      qhd_xfer_complete_isr(p_qhd);
-    }
+  ehci_qhd_t *qhd = list_head;
 
-    p_qhd = qhd_next(p_qhd);
-  }while(p_qhd != async_head); // async list traversal, stop if loop around
+  do {
+    qhd_xfer_complete_isr(qhd);
+    qhd = qhd_next(qhd);
+  } while ( qhd != list_head ); // async list traversal, stop if loop around
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
+void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms)
 {
   uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
   ehci_link_t next_link = *list_get_period_head(rhport, interval_ms);
@@ -612,22 +616,13 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
     switch (next_link.type) {
       case EHCI_QTYPE_QHD: {
         ehci_qhd_t *qhd = (ehci_qhd_t *) entry_addr;
-        hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t));
-
-        if (!qhd->qtd_overlay.halted) {
-          qhd_xfer_complete_isr(qhd);
-        }
+        qhd_xfer_complete_isr(qhd);
       }
         break;
 
+      // TODO support hs/fs ISO
       case EHCI_QTYPE_ITD:
-        // TODO support hs ISO
-        break;
-
       case EHCI_QTYPE_SITD:
-        // TODO support split ISO
-        break;
-
       case EHCI_QTYPE_FSTN:
       default:
         break;
@@ -637,106 +632,6 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
   }
 }
 
-// TODO merge with qhd_xfer_complete_isr()
-TU_ATTR_ALWAYS_INLINE static inline
-void qhd_xfer_error_isr(ehci_qhd_t * qhd)
-{
-  volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay;
-
-  // TD has error
-  if (qtd_overlay->halted) {
-    xfer_result_t xfer_result;
-
-    if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
-      // Error count = 0 often occurs when device disconnected, or other bus-related error
-      xfer_result = XFER_RESULT_FAILED;
-    }else {
-      // no error bits are set, endpoint is halted due to STALL
-      xfer_result = XFER_RESULT_STALLED;
-    }
-
-//    if (XFER_RESULT_FAILED == xfer_result ) {
-//      TU_LOG1("  QHD xfer err count: %d\n", qtd_overlay->err_count);
-//      TU_BREAKPOINT(); // TODO skip unplugged device
-//    }
-
-    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd;
-    TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !?
-
-    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
-
-    uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
-    uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
-
-    // invalidate dcache if IN transfer
-    if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
-      hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
-    }
-
-    // remove and free TD before invoking callback
-    qhd_remove_qtd(qhd);
-
-    if (0 == qhd->ep_number ) {
-      // control cannot be halted
-      qhd->qtd_overlay.next.terminate      = 1;
-      qhd->qtd_overlay.alternate.terminate = 1;
-      qhd->qtd_overlay.halted              = 0;
-
-      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
-    }
-
-    // notify usbh
-    uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
-    hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
-  }
-}
-
-TU_ATTR_ALWAYS_INLINE static inline
-void xfer_error_isr(uint8_t rhport)
-{
-  //------------- async list -------------//
-  ehci_qhd_t * const async_head = list_get_async_head(rhport);
-  ehci_qhd_t *p_qhd = async_head;
-  do
-  {
-    hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
-    qhd_xfer_error_isr( p_qhd );
-    p_qhd = qhd_next(p_qhd);
-  }while(p_qhd != async_head); // async list traversal, stop if loop around
-
-  //------------- TODO refractor period list -------------//
-  uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
-  for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2)
-  {
-    ehci_link_t next_item = *list_get_period_head(rhport, interval_ms);
-
-    // TODO abstract max loop guard for period
-    while( !next_item.terminate &&
-           !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) )
-    {
-      switch ( next_item.type )
-      {
-        case EHCI_QTYPE_QHD:
-        {
-          ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
-          hcd_dcache_invalidate(p_qhd_int, sizeof(ehci_qhd_t));
-
-          qhd_xfer_error_isr(p_qhd_int);
-        }
-        break;
-
-				// TODO support hs/fs ISO
-        case EHCI_QTYPE_ITD:
-        case EHCI_QTYPE_SITD:
-        case EHCI_QTYPE_FSTN:
-        default: break;
-      }
-
-      next_item = *list_next(&next_item);
-    }
-  }
-}
-
 //------------- Host Controller Driver's Interrupt Handler -------------//
 void hcd_int_handler(uint8_t rhport)
 {
@@ -768,21 +663,16 @@ void hcd_int_handler(uint8_t rhport)
     regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
   }
 
-  // A USB transfer is completed with error
-  if (int_status & EHCI_INT_MASK_ERROR) {
-    xfer_error_isr(rhport);
-    regs->status = EHCI_INT_MASK_ERROR; // Acknowledge
-  }
+  // A USB transfer is completed (OK or error)
+  uint32_t const usb_int = int_status & (EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR);
+  if (usb_int) {
+    proccess_async_xfer_isr(list_get_async_head(rhport));
 
-  // A USB transfer is completed
-  if (int_status & EHCI_INT_MASK_USB) {
     for ( uint32_t i = 1; i <= FRAMELIST_SIZE; i *= 2 ) {
-      period_list_xfer_complete_isr(rhport, i);
+      process_period_xfer_isr(rhport, i);
     }
 
-    async_list_xfer_complete_isr(list_get_async_head(rhport));
-
-    regs->status = EHCI_INT_MASK_USB; // Acknowledge
+    regs->status = usb_int; // Acknowledge
   }
 
   //------------- There is some removed async previously -------------//
@@ -1011,8 +901,7 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t *qtd_find_free(void) {
   return NULL;
 }
 
-static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
-{
+static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) {
   tu_memclr(qtd, sizeof(ehci_qtd_t));
   qtd->used                = 1;
 
@@ -1026,8 +915,7 @@ static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
   qtd->expected_bytes      = total_bytes;
 
   qtd->buffer[0] = (uint32_t) buffer;
-  for(uint8_t i=1; i<5; i++)
-  {
+  for(uint8_t i=1; i<5; i++) {
     qtd->buffer[i] |= tu_align4k(qtd->buffer[i - 1] ) + 4096;
   }
 }
-- 
cgit v1.3.1


From fbaa148fe0f4a4b83f41efe9887a8909161710f6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 18 Jul 2023 15:22:09 +0700
Subject: updating hcd rusb2

- make osal_task_delay() as weak function in usbh
- implement osal_task_delay() in hcd rusb2 (may moved to other places)
---
 examples/device/cdc_msc_freertos/skip.txt       |   1 +
 examples/device/hid_composite_freertos/skip.txt |   1 +
 examples/dual/host_hid_to_device_cdc/only.txt   |   1 +
 hw/bsp/ra/boards/ra6m5_ek/board.cmake           |   7 +-
 hw/bsp/ra/family.cmake                          |   2 +-
 src/host/usbh.c                                 |   2 +-
 src/portable/renesas/rusb2/dcd_rusb2.c          |  12 ++-
 src/portable/renesas/rusb2/hcd_rusb2.c          | 123 +++++++++++-------------
 src/portable/renesas/rusb2/rusb2_ra.h           |   7 --
 9 files changed, 78 insertions(+), 78 deletions(-)

(limited to 'src')

diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index 49b8ee57b..a6f96b288 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -8,5 +8,6 @@ mcu:RP2040
 mcu:SAMD11
 mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
 family:broadcom_32bit
 family:broadcom_64bit
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index 49b8ee57b..a6f96b288 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -8,5 +8,6 @@ mcu:RP2040
 mcu:SAMD11
 mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
 family:broadcom_32bit
 family:broadcom_64bit
diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt
index 6ee8e3fde..d9700677f 100644
--- a/examples/dual/host_hid_to_device_cdc/only.txt
+++ b/examples/dual/host_hid_to_device_cdc/only.txt
@@ -1,3 +1,4 @@
 board:mimxrt1060_evk
 board:mimxrt1064_evk
 mcu:RP2040
+mcu:ra6m5
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
index 5a615f9b0..c91d48a32 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -3,15 +3,20 @@ set(MCU_VARIANT ra6m5)
 
 set(JLINK_DEVICE R7FA6M5BH)
 
-# default to PORT1 Highspeed
+# Device port default to PORT1 Highspeed
 if (NOT DEFINED PORT)
 set(PORT 1)
 endif()
 
+# Host port will be the other port
+set(HOST_PORT $<NOT:${PORT}>)
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
     # port 0 is fullspeed, port 1 is highspeed
     BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
     )
 endfunction()
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index f09e86a72..2c45b8d71 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS RAXXX CACHE INTERNAL "")
+set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "")
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 184bda23b..1418cfb79 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -256,7 +256,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-void osal_task_delay(uint32_t msec)
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
 {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 358e5644b..6fee4edd7 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -27,12 +27,12 @@
 
 #include "tusb_option.h"
 
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
+
 // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
-
 #include "device/dcd.h"
 #include "rusb2_type.h"
 
@@ -53,6 +53,13 @@
   #error "Unsupported MCU"
 #endif
 
+//--------------------------------------------------------------------+
+// Application API for setting IRQ number
+//--------------------------------------------------------------------+
+void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  rusb2_controller[rhport].irqnum = irqnum;
+}
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -681,7 +688,6 @@ static void enable_interrupt(uint32_t pswi)
 void dcd_init(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-
   rusb2_module_start(rhport, true);
 
 #ifdef RUSB2_SUPPORT_HIGHSPEED
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 4e5ff0359..656051e2b 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -27,8 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \
-                        TU_CHECK_MCU(OPT_MCU_RAXXX))
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_RUSB2)
 
 #include "host/hcd.h"
 #include "rusb2_type.h"
@@ -41,8 +40,14 @@
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
+
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
+
+  void osal_task_delay(uint32_t msec) {
+    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
+  }
+
 #else
   #error "Unsupported MCU"
 #endif
@@ -67,19 +72,6 @@
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct TU_ATTR_PACKED {
-  union {
-    struct {
-      uint16_t      : 8;
-      uint16_t TRCLR: 1;
-      uint16_t TRENB: 1;
-      uint16_t      : 0;
-    };
-    uint16_t TRE;
-  };
-  uint16_t TRN;
-} reg_pipetre_t;
-
 typedef union TU_ATTR_PACKED {
   struct {
     volatile uint16_t u8: 8;
@@ -308,8 +300,9 @@ static bool pipe_xfer_out(unsigned num)
     pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps)
+  if (len < mps) {
     RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+  }
   RUSB2->D0FIFOSEL = 0;
   while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
@@ -488,60 +481,60 @@ static void enable_interrupt(uint32_t pswi)
 
 bool hcd_init(uint8_t rhport)
 {
-  (void)rhport;
-
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
-  RUSB2->SYSCFG_b.HSE = 1;
-  RUSB2->PHYSET_b.HSEB = 0;
-  RUSB2->PHYSET_b.DIRPD = 0;
-  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
-  RUSB2->PHYSET_b.PLLRESET = 0;
-  RUSB2->LPSTS_b.SUSPENDM = 1;
-  while (!RUSB2->PLLSTA_b.PLLLOCK);
-  RUSB2->SYSCFG_b.DRPD = 1;
-  RUSB2->SYSCFG_b.DCFM = 1;
-  RUSB2->SYSCFG_b.DPRPU = 0;
-  RUSB2->SYSCFG_b.CNEN = 1;
-  RUSB2->BUSWAIT |= 0x0F00U;
-  RUSB2->SOFCFG_b.INTL = 1;
-  RUSB2->DVSTCTR0_b.VBUSEN = 1;
-  RUSB2->CFIFOSEL_b.MBW = 1;
-  RUSB2->D0FIFOSEL_b.MBW = 1;
-  RUSB2->D1FIFOSEL_b.MBW = 1;
-  RUSB2->INTSTS0 = 0;
-  for (volatile int i = 0; i < 30000; ++i) ;
-  RUSB2->SYSCFG_b.USBE = 1;
-#else
-  /* HOST DEVICE Full SPEED */
-  RUSB2->SYSCFG_b.SCKE = 1;         /* USB Clock enable */
-  while (!RUSB2->SYSCFG_b.SCKE) ;
-  RUSB2->SYSCFG_b.DPRPU = 0;        /* D+ pull up enable - 0/disable in host mode */
-  RUSB2->SYSCFG_b.DRPD = 1;         /* D+/D- pull down - 1/in Host mode (pag.834)*/
-  RUSB2->SYSCFG_b.DCFM = 1;         /* HOST or Device - 1/HOST */
-
-  RUSB2->DVSTCTR0_b.VBUSEN = 1;
-
-  RUSB2->SYSCFG_b.DRPD = 1;
-  for (volatile int i = 0; i < 30000; ++i) ;
-  RUSB2->SYSCFG_b.USBE = 1;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb2_module_start(rhport, true);
+
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  if (rusb2_is_highspeed_rhport(rhport) ) {
+    rusb->SYSCFG_b.HSE = 1;
+    rusb->PHYSET_b.HSEB = 0;
+    rusb->PHYSET_b.DIRPD = 0;
+    R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->PHYSET_b.PLLRESET = 0;
+    rusb->LPSTS_b.SUSPENDM = 1;
+    while ( !rusb->PLLSTA_b.PLLLOCK );
+    rusb->SYSCFG_b.DRPD = 1;
+    rusb->SYSCFG_b.DCFM = 1;
+    rusb->SYSCFG_b.DPRPU = 0;
+    rusb->SYSCFG_b.CNEN = 1;
+    rusb->BUSWAIT |= 0x0F00U;
+    rusb->SOFCFG_b.INTL = 1;
+    rusb->DVSTCTR0_b.VBUSEN = 1;
+    rusb->CFIFOSEL_b.MBW = 1;
+    rusb->D0FIFOSEL_b.MBW = 1;
+    rusb->D1FIFOSEL_b.MBW = 1;
+    rusb->INTSTS0 = 0;
+    for ( volatile int i = 0; i < 30000; ++i );
+    rusb->SYSCFG_b.USBE = 1;
+  } else
 #endif
+  {
+    rusb->SYSCFG_b.SCKE = 1;
+    while ( !rusb->SYSCFG_b.SCKE ) {}
+    rusb->SYSCFG_b.DCFM = 1;         // Host function
+    rusb->SYSCFG_b.DPRPU = 0;        // Disable D+ pull up
+    rusb->SYSCFG_b.DRPD = 1;         // Enable D+/D- pull down
 
-  // MCU specific PHY init
-  rusb2_phy_init();
+    rusb->DVSTCTR0_b.VBUSEN = 1;
+    for ( volatile int i = 0; i < 30000; ++i ) {} // FIXME do we need to wait here? how long ?
+    //R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->SYSCFG_b.USBE = 1;
 
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)
-  RUSB2->PHYSLEW = 0x5;
-  RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
-#endif
+    // MCU specific PHY init
+    rusb2_phy_init();
+
+    rusb->PHYSLEW = 0x5;
+    rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
+  }
 
   /* Setup default control pipe */
-  RUSB2->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
-  RUSB2->DCPMAXP = 64;
-  RUSB2->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk;
-  RUSB2->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk;
-  RUSB2->BEMPENB = 1;
-  RUSB2->NRDYENB = 1;
-  RUSB2->BRDYENB = 1;
+  rusb->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
+  rusb->DCPMAXP = 64;
+  rusb->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk;
+  rusb->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk;
+  rusb->BEMPENB = 1;
+  rusb->NRDYENB = 1;
+  rusb->BRDYENB = 1;
 
   return true;
 }
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 28b690512..8a4d2ad36 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -106,13 +106,6 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) {
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) {
 }
 
-//--------------------------------------------------------------------+
-// Application API for setting IRQ number
-//--------------------------------------------------------------------+
-void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
-  rusb2_controller[rhport].irqnum = irqnum;
-}
-
 #ifdef __cplusplus
 }
 #endif
-- 
cgit v1.3.1


From 6b6dcc6c099eeafaa6d76bf6133181874beabc0d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jul 2023 19:50:50 +0700
Subject: refactored multiple ports for hcd rusb2

---
 .idea/cmake.xml                              |  15 +-
 .idea/runConfigurations/ra6m5.xml            |   2 +-
 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug |   4 +-
 src/portable/renesas/rusb2/dcd_rusb2.c       |  37 +--
 src/portable/renesas/rusb2/hcd_rusb2.c       | 452 ++++++++++++++-------------
 5 files changed, 268 insertions(+), 242 deletions(-)

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 864ff615b..519623b71 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,7 +2,6 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
@@ -26,27 +25,27 @@
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
       <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
-      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk" />
-      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk" />
-      <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
+      <configuration PROFILE_NAME="metro m7 1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso18s37" />
+      <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69" />
+      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g0b1nucleo" />
       <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g474nucleo" />
       <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
       <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="metro m7" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
       <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
       <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
+      <configuration PROFILE_NAME="ra6m5" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
index 02df11610..89f9787a0 100644
--- a/.idea/runConfigurations/ra6m5.xml
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
index aebb29162..7b8ee9c95 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -20,7 +20,9 @@ void OnProjectLoad (void) {
   Project.SetTraceSource ("Trace Pins");
   Project.SetTracePortWidth (4);
 
-  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
+  //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
+  //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf");
+  File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf");
 }
 /*********************************************************************
 *
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 6fee4edd7..83f0fdc4a 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -83,6 +83,18 @@ typedef struct TU_ATTR_PACKED
 TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 TU_ATTR_BIT_FIELD_ORDER_END
 
+typedef struct
+{
+  pipe_state_t pipe[10];
+  uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
+} dcd_data_t;
+
+static dcd_data_t _dcd;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+
 // Transfer conditions specifiable for each pipe:
 // - Pipe 0: Control transfer with 64-byte single buffer
 // - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
@@ -96,18 +108,6 @@ enum {
   PIPE_COUNT = 10,
 };
 
-typedef struct
-{
-  pipe_state_t pipe[10];
-  uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
-} dcd_data_t;
-
-static dcd_data_t _dcd;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -746,20 +746,17 @@ void dcd_init(uint8_t rhport)
   }
 }
 
-void dcd_int_enable(uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   rusb2_int_enable(rhport);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   rusb2_int_disable(rhport);
 }
 
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void)rhport;
-  (void)dev_addr;
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 656051e2b..a4b534a05 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -52,23 +52,12 @@
   #error "Unsupported MCU"
 #endif
 
-#define TU_RUSB2_HCD_DBG   0
+#define TU_RUSB2_HCD_DBG   2
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-/* LINK core registers */
-#if defined(__CCRX__)
-  #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
-#elif defined(__RX__)
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
-#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
-  #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE)
-#else
-  #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE)
-#endif
-
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
@@ -108,79 +97,97 @@ typedef struct
 //--------------------------------------------------------------------+
 static hcd_data_t _hcd;
 
-static unsigned find_pipe(unsigned xfer)
-{
-  switch (xfer) {
-  case TUSB_XFER_ISOCHRONOUS:
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_BULK:
-    for (int i = 3; i <= 5; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_INTERRUPT:
-    for (int i = 6; i <= 9; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  default:
-    /* No support for control transfer */
-    break;
+// TODO merged with DCD
+// Transfer conditions specifiable for each pipe:
+// - Pipe 0: Control transfer with 64-byte single buffer
+// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
+//   to 2 KB and optional double buffer
+// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and
+//   optional double buffer
+// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer
+enum {
+  PIPE_1ST_BULK = 3,
+  PIPE_1ST_INTERRUPT = 6,
+  PIPE_COUNT = 10,
+};
+
+static unsigned find_pipe(unsigned xfer) {
+  switch ( xfer ) {
+    case TUSB_XFER_ISOCHRONOUS:
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      break;
+
+    case TUSB_XFER_BULK:
+      for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      break;
+
+    default:
+      /* No support for control transfer */
+      break;
   }
   return 0;
 }
 
-static volatile uint16_t* get_pipectr(unsigned num)
+static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
 {
   if (num) {
-    return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]);
+    return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
   } else {
-    return (volatile uint16_t*)&(RUSB2->DCPCTR);
+    return (volatile uint16_t*)&(rusb->DCPCTR);
   }
 }
 
-static volatile reg_pipetre_t* get_pipetre(unsigned num)
+static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E);
+    tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
   }
   return tre;
 }
 
-static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
+static volatile uint16_t* addr_to_pipectr(uint8_t rhport, uint8_t dev_addr, unsigned ep_addr)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   const unsigned epn = tu_edpt_number(ep_addr);
+
   if (epn) {
     const unsigned dir_in = tu_edpt_dir(ep_addr);
     const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
-    return get_pipectr(num);
+    return get_pipectr(rusb, num);
   } else {
-    return get_pipectr(0);
+    return get_pipectr(rusb, 0);
   }
 }
 
-static unsigned edpt0_max_packet_size(void)
+static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb)
 {
-  return RUSB2->DCPMAXP_b.MXPS;
+  return rusb->DCPMAXP_b.MXPS;
 }
 
-static unsigned edpt_max_packet_size(unsigned num)
+static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num)
 {
-  RUSB2->PIPESEL = num;
-  return RUSB2->PIPEMAXP_b.MXPS;
+  rusb->PIPESEL = num;
+  return rusb->PIPEMAXP_b.MXPS;
 }
 
-static inline void pipe_wait_for_ready(unsigned num)
+static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num)
 {
-  while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ;
-  while (!RUSB2->D0FIFOCTR_b.FRDY) ;
+  while (rusb->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!rusb->D0FIFOCTR_b.FRDY) {}
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -205,33 +212,33 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
   while (len--) *p++ = *reg;
 }
 
-static bool pipe0_xfer_in(void)
+static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_hcd.pipe[0];
   const unsigned rem = pipe->remaining;
 
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = RUSB2->CFIFOCTR_b.DTLN;
+  const unsigned mps = edpt0_max_packet_size(rusb);
+  const unsigned vld = rusb->CFIFOCTR_b.DTLN;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
-    pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+    pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   return false;
 }
 
-static bool pipe0_xfer_out(void)
+static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_hcd.pipe[0];
   const unsigned rem = pipe->remaining;
@@ -239,40 +246,40 @@ static bool pipe0_xfer_out(void)
     pipe->buf = NULL;
     return true;
   }
-  const unsigned mps = edpt0_max_packet_size();
+  const unsigned mps = edpt0_max_packet_size(rusb);
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+    pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
   pipe->remaining = rem - len;
   return false;
 }
 
-static bool pipe_xfer_in(unsigned num)
+static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned vld  = RUSB2->D0FIFOCTR_b.DTLN;
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
+  const unsigned mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+  const unsigned vld  = rusb->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+    pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -281,7 +288,7 @@ static bool pipe_xfer_in(unsigned num)
   return false;
 }
 
-static bool pipe_xfer_out(unsigned num)
+static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
@@ -291,37 +298,39 @@ static bool pipe_xfer_out(unsigned num)
     return true;
   }
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+  const unsigned mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+    pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
 
-static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+static bool process_pipe0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
 {
   (void)dev_addr;
+
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   const unsigned dir_in = tu_edpt_dir(ep_addr);
 
   /* configure fifo direction and access unit settings */
   if (dir_in) { /* IN, a byte */
-    RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
-    while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
+    rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
   } else { /* OUT, 2 bytes */
-    RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+    rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
                          (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-    while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
+    while (!(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
   }
 
   pipe_state_t *pipe = &_hcd.pipe[0];
@@ -331,26 +340,28 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
   if (buflen) {
     pipe->buf     = buffer;
     if (!dir_in) { /* OUT */
-      TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80));
-      pipe0_xfer_out();
+      TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
+      pipe0_xfer_out(rusb);
     }
   } else { /* ZLP */
     pipe->buf        = NULL;
     if (!dir_in) { /* OUT */
-      RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
     }
-    if (dir_in == RUSB2->DCPCFG_b.DIR) {
-      TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == RUSB2->DCPCTR_b.PID);
-      RUSB2->DCPCTR_b.SQSET = 1;
-      RUSB2->DCPCFG_b.DIR = dir_in ^ 1;
+    if (dir_in == rusb->DCPCFG_b.DIR) {
+      TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == rusb->DCPCTR_b.PID);
+      rusb->DCPCTR_b.SQSET = 1;
+      rusb->DCPCFG_b.DIR = dir_in ^ 1;
     }
   }
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   return true;
 }
 
-static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
+static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   const unsigned epn    = tu_edpt_number(ep_addr);
   const unsigned dir_in = tu_edpt_dir(ep_addr);
   const unsigned num    = _hcd.ep[dev_addr - 1][dir_in][epn - 1];
@@ -363,19 +374,19 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
   pipe->remaining = buflen;
   if (!dir_in) { /* OUT */
     if (buflen) {
-      pipe_xfer_out(num);
+      pipe_xfer_out(rusb, num);
     } else { /* ZLP */
-      RUSB2->D0FIFOSEL = num;
-      pipe_wait_for_ready(num);
-      RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
-      RUSB2->D0FIFOSEL = 0;
-      while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+      rusb->D0FIFOSEL = num;
+      pipe_wait_for_ready(rusb, num);
+      rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->D0FIFOSEL = 0;
+      while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
     }
   } else {
-    volatile uint16_t     *ctr = get_pipectr(num);
-    volatile reg_pipetre_t *pt = get_pipetre(num);
+    volatile uint16_t     *ctr = get_pipectr(rusb, num);
+    volatile reg_pipetre_t *pt = get_pipetre(rusb, num);
     if (pt) {
-      const unsigned     mps = edpt_max_packet_size(num);
+      const unsigned     mps = edpt_max_packet_size(rusb, num);
       if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (buflen + mps - 1) / mps;
@@ -386,20 +397,20 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
   return true;
 }
 
-static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+static bool process_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
 {
   const unsigned epn = tu_edpt_number(ep_addr);
   if (0 == epn) {
-    return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen);
+    return process_pipe0_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
   } else {
-    return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen);
+    return process_pipe_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
   }
 }
 
 static void process_pipe0_bemp(uint8_t rhport)
 {
-  (void)rhport;
-  bool completed = pipe0_xfer_out();
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  bool completed = pipe0_xfer_out(rusb);
   if (completed) {
     pipe_state_t *pipe = &_hcd.pipe[0];
     hcd_event_xfer_complete(pipe->dev,
@@ -411,9 +422,9 @@ static void process_pipe0_bemp(uint8_t rhport)
 
 static void process_pipe_nrdy(uint8_t rhport, unsigned num)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   xfer_result_t result;
-  uint16_t volatile *ctr = get_pipectr(num);
+  uint16_t volatile *ctr = get_pipectr(rusb, num);
   TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\n", num, *ctr);
   switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
     default: return;
@@ -429,19 +440,19 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
 
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   pipe_state_t  *pipe   = &_hcd.pipe[num];
   const unsigned dir_in = tu_edpt_dir(pipe->ep);
   bool completed;
 
   if (dir_in) { /* IN */
     if (num) {
-      completed = pipe_xfer_in(num);
+      completed = pipe_xfer_in(rusb, num);
     } else {
-      completed = pipe0_xfer_in();
+      completed = pipe0_xfer_in(rusb);
     }
   } else {
-    completed = pipe_xfer_out(num);
+    completed = pipe_xfer_out(rusb, num);
   }
   if (completed) {
     hcd_event_xfer_complete(pipe->dev, pipe->ep,
@@ -539,86 +550,88 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   rusb2_int_enable(rhport);
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   rusb2_int_disable(rhport);
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
-  return RUSB2->FRMNUM_b.FRNM;
+  return rusb->FRMNUM_b.FRNM;
 }
 
 /*--------------------------------------------------------------------+
  * Port API
  *--------------------------------------------------------------------+*/
-bool hcd_port_connect_status(uint8_t rhport)
-{
-  (void)rhport;
-  return RUSB2->INTSTS1_b.ATTCH ? true : false;
+bool hcd_port_connect_status(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  return rusb->INTSTS1_b.ATTCH ? true : false;
 }
 
-void hcd_port_reset(uint8_t rhport)
-{
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
-  while (RUSB2->DCPCTR_b.PBUSY) ;
+void hcd_port_reset(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+  while (rusb->DCPCTR_b.PBUSY) {}
+
   hcd_int_disable(rhport);
-  RUSB2->DVSTCTR0_b.UACT = 0;
-  if (RUSB2->DCPCTR_b.SUREQ) {
-    RUSB2->DCPCTR_b.SUREQCLR = 1;
+  rusb->DVSTCTR0_b.UACT = 0;
+  if (rusb->DCPCTR_b.SUREQ) {
+    rusb->DCPCTR_b.SUREQCLR = 1;
   }
   hcd_int_enable(rhport);
+
   /* Reset should be asserted 10-20ms. */
-  RUSB2->DVSTCTR0_b.USBRST = 1;
-  for (volatile int i = 0; i < 2400000; ++i) ;
-  RUSB2->DVSTCTR0_b.USBRST = 0;
-  RUSB2->DVSTCTR0_b.UACT = 1;
+  rusb->DVSTCTR0_b.USBRST = 1;
+  for (volatile int i = 0; i < 2400000; ++i) {}
+  rusb->DVSTCTR0_b.USBRST = 0;
+
+  rusb->DVSTCTR0_b.UACT = 1;
   _hcd.need_reset = false;
 }
 
-void hcd_port_reset_end(uint8_t rhport)
-{
+void hcd_port_reset_end(uint8_t rhport) {
   (void) rhport;
 }
 
-tusb_speed_t hcd_port_speed_get(uint8_t rhport)
-{
-  (void)rhport;
-  switch (RUSB2->DVSTCTR0_b.RHST) {
-    default: return TUSB_SPEED_INVALID;
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  switch (rusb->DVSTCTR0_b.RHST) {
+    case RUSB2_DVSTCTR0_RHST_HS: return TUSB_SPEED_HIGH;
     case RUSB2_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
-    case RUSB2_DVSTCTR0_RHST_LS:  return TUSB_SPEED_LOW;
+    case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW;
+    default: return TUSB_SPEED_INVALID;
   }
 }
 
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
-{
-  (void)rhport;
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   uint16_t volatile *ctr;
+
   TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */
   if (!dev_addr) return;
+
   _hcd.ctl_mps[dev_addr] = 0;
   uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0];
+
   for (int i = 0; i < 2 * 15; ++i, ++ep) {
     unsigned num = *ep;
     if (!num || (dev_addr != _hcd.pipe[num].dev)) continue;
 
-    ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1];
+    ctr = (uint16_t volatile*)&rusb->PIPE_CTR[num - 1];
     *ctr = 0;
-    RUSB2->NRDYENB &= ~TU_BIT(num);
-    RUSB2->BRDYENB &= ~TU_BIT(num);
-    RUSB2->PIPESEL = num;
-    RUSB2->PIPECFG = 0;
-    RUSB2->PIPEMAXP = 0;
+    rusb->NRDYENB &= ~TU_BIT(num);
+    rusb->BRDYENB &= ~TU_BIT(num);
+    rusb->PIPESEL = num;
+    rusb->PIPECFG = 0;
+    rusb->PIPEMAXP = 0;
 
     _hcd.pipe[num].ep  = 0;
     _hcd.pipe[num].dev = 0;
@@ -631,52 +644,54 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
  *--------------------------------------------------------------------+*/
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-  (void)rhport;
-  TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, RUSB2->DCPCTR);
-
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
-  TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ);
 
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, rusb->DCPCTR);
+
+  TU_ASSERT(0 == rusb->DCPCTR_b.SUREQ);
+
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
 
   _hcd.pipe[0].buf       = NULL;
   _hcd.pipe[0].length    = 8;
   _hcd.pipe[0].remaining = 0;
   _hcd.pipe[0].dev       = dev_addr;
 
-  while (RUSB2->DCPCTR_b.PBUSY) ;
-  RUSB2->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
+  while (rusb->DCPCTR_b.PBUSY) ;
+  rusb->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
 
   /* Set direction in advance for DATA stage */
   uint8_t const bmRequesttype = setup_packet[0];
-  RUSB2->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
+  rusb->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
 
   uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
-  RUSB2->USBREQ  = tu_htole16(p[0]);
-  RUSB2->USBVAL  = p[1];
-  RUSB2->USBINDX = p[2];
-  RUSB2->USBLENG = p[3];
+  rusb->USBREQ  = tu_htole16(p[0]);
+  rusb->USBVAL  = p[1];
+  rusb->USBINDX = p[2];
+  rusb->USBLENG = p[3];
 
-  RUSB2->DCPCTR_b.SUREQ = 1;
+  rusb->DCPCTR_b.SUREQ = 1;
   return true;
 }
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc)
 {
-  (void)rhport;
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
   const unsigned ep_addr = ep_desc->bEndpointAddress;
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
+
   if (0 == epn) {
-    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
     hcd_devtree_info_t devtree;
     hcd_devtree_get_info(dev_addr, &devtree);
-    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &RUSB2->DEVADD[0];
+    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &rusb->DEVADD[0];
     devadd += dev_addr;
-    while (RUSB2->DCPCTR_b.PBUSY) ;
-    RUSB2->DCPMAXP = (dev_addr << 12) | mps;
+    while (rusb->DCPCTR_b.PBUSY) {}
+    rusb->DCPMAXP = (dev_addr << 12) | mps;
     *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS;
     _hcd.ctl_mps[dev_addr] = mps;
     return true;
@@ -690,17 +705,20 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   }
   const unsigned num = find_pipe(xfer);
   if (!num) return false;
+
   _hcd.pipe[num].dev = dev_addr;
   _hcd.pipe[num].ep  = ep_addr;
   _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num;
 
   /* setup pipe */
   hcd_int_disable(rhport);
-  RUSB2->PIPESEL = num;
-  RUSB2->PIPEMAXP = (dev_addr << 12) | mps;
-  volatile uint16_t *ctr = get_pipectr(num);
+
+  rusb->PIPESEL = num;
+  rusb->PIPEMAXP = (dev_addr << 12) | mps;
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
   *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
+
   unsigned cfg = ((1 ^ dir_in) << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
     cfg |= RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk;
@@ -709,13 +727,16 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   } else {
     cfg |= RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk;
   }
-  RUSB2->PIPECFG = cfg;
-  RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num);
-  RUSB2->NRDYENB |= TU_BIT(num);
-  RUSB2->BRDYENB |= TU_BIT(num);
+
+  rusb->PIPECFG = cfg;
+  rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  rusb->NRDYENB |= TU_BIT(num);
+  rusb->BRDYENB |= TU_BIT(num);
+
   if (!dir_in) {
     *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
+
   hcd_int_enable(rhport);
 
   return true;
@@ -726,14 +747,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
   bool r;
   hcd_int_disable(rhport);
   TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\n", dev_addr, ep_addr, buflen);
-  r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen);
+  r = process_edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
   hcd_int_enable(rhport);
   return r;
 }
 
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
-  uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);
+  uint8_t rhport = 0; // FIXME change API
+  uint16_t volatile *ctr = addr_to_pipectr(rhport, dev_addr, ep_addr);
   TU_ASSERT(ctr);
 
   const uint32_t pid = *ctr & 0x3;
@@ -756,67 +778,73 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 void hcd_int_handler(uint8_t rhport)
 {
-  (void)rhport;
-#if defined(__CCRX__)
-  static const int Mod37BitPosition[] = {
-    -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
-    7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
-    20, 8, 19, 18};
-#endif
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   static unsigned char attach_attempt = 0;
-  unsigned is1 = RUSB2->INTSTS1;
-  unsigned is0 = RUSB2->INTSTS0;
+  unsigned is0 = rusb->INTSTS0;
+  unsigned is1 = rusb->INTSTS1;
 
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
-  RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
-  TU_LOG(TU_RUSB2_HCD_DBG, "IS %04x %04x\n", is0, is1);
-  is1 &= RUSB2->INTENB1;
-  is0 &= RUSB2->INTENB0;
+  rusb->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
+  rusb->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
+
+  TU_LOG3("IS %04x %04x\n", is0, is1);
+  is1 &= rusb->INTENB1;
+  is0 &= rusb->INTENB0;
 
   if (is1 & RUSB2_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
-    RUSB2->DCPCTR_b.SQSET = 1;
+    rusb->DCPCTR_b.SQSET = 1;
     attach_attempt = 0;
-    hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
+    hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
+
   if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
-    hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
+    hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
     if(attach_attempt > 0) {
-      RUSB2->DVSTCTR0_b.UACT = 1;
+      rusb->DVSTCTR0_b.UACT = 1;
       _hcd.need_reset = true;
-      RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
+      rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
       hcd_event_device_attach(rhport, true);
     }
     attach_attempt--;
   }
+
   if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
     attach_attempt = 10;
-    RUSB2->DVSTCTR0_b.UACT = 1;
+    rusb->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
-    RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
+    rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
     hcd_event_device_attach(rhport, true);
   }
+
   if (is1 & RUSB2_INTSTS1_DTCH_Msk) {
-    RUSB2->DVSTCTR0_b.UACT = 0;
-    if (RUSB2->DCPCTR_b.SUREQ) {
-      RUSB2->DCPCTR_b.SUREQCLR = 1;
+    rusb->DVSTCTR0_b.UACT = 0;
+    if (rusb->DCPCTR_b.SUREQ) {
+      rusb->DCPCTR_b.SUREQCLR = 1;
     }
-    RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk;
+    rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk;
     hcd_event_device_remove(rhport, true);
   }
 
   if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
-    const unsigned s = RUSB2->BEMPSTS;
-    RUSB2->BEMPSTS = 0;
+    const unsigned s = rusb->BEMPSTS;
+    rusb->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
+
+#if defined(__CCRX__)
+  static const int Mod37BitPosition[] = {
+    -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
+    7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
+    20, 8, 19, 18};
+#endif
+
   if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
-    const unsigned m = RUSB2->NRDYENB;
-    unsigned s = RUSB2->NRDYSTS & m;
-    RUSB2->NRDYSTS = ~s;
+    const unsigned m = rusb->NRDYENB;
+    unsigned s = rusb->NRDYSTS & m;
+    rusb->NRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
@@ -828,10 +856,10 @@ void hcd_int_handler(uint8_t rhport)
     }
   }
   if (is0 & RUSB2_INTSTS0_BRDY_Msk) {
-    const unsigned m = RUSB2->BRDYENB;
-    unsigned s = RUSB2->BRDYSTS & m;
+    const unsigned m = rusb->BRDYENB;
+    unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    RUSB2->BRDYSTS = ~s;
+    rusb->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
-- 
cgit v1.3.1


From c37a9571741cef0dcf0cd5a77e202ae741a2dd42 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jul 2023 19:56:48 +0700
Subject: correct hcd_edpt_clear_stall() API signature

---
 src/host/hcd.h                                 | 2 +-
 src/portable/mentor/musb/hcd_musb.c            | 4 ++--
 src/portable/nxp/khci/hcd_khci.c               | 4 ++--
 src/portable/ohci/ohci.c                       | 4 ++--
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 4 ++--
 src/portable/raspberrypi/rp2040/hcd_rp2040.c   | 4 ++--
 src/portable/renesas/rusb2/hcd_rusb2.c         | 4 ++--
 7 files changed, 13 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 50f1dcdcc..898e0c6a4 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -179,7 +179,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr);
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
 // USBH implemented API
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 5be67a186..5d1fba6d9 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -831,8 +831,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 }
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   unsigned const pipenum = find_pipe(dev_addr, ep_addr);
   if (!pipenum) return false;
   hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 6784049c5..928564e26 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -570,8 +570,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   if (!tu_edpt_number(ep_addr)) return true;
   int num = find_pipe(dev_addr, ep_addr);
   if (num < 0) return false;
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 9f3af4781..413e72037 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -556,8 +556,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
 
   p_ed->is_stalled = 0;
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index bb41ad638..45a3e80ef 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -163,8 +163,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 //    return busy;
 //}
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   (void) dev_addr;
   (void) ep_addr;
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 5091fa907..6db8e2a0a 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -625,8 +625,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   return true;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   (void) dev_addr;
   (void) ep_addr;
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 0a75d0b47..292d40da8 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -718,8 +718,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);
   TU_ASSERT(ctr);
 
-- 
cgit v1.3.1


From 10575c1b380136ce9381393c33e982cea7ef4731 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jul 2023 20:48:18 +0700
Subject: mising ehci

---
 src/host/hcd.h           | 2 +-
 src/portable/ehci/ehci.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 898e0c6a4..d77dd6e2f 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -179,7 +179,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr);
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
 // USBH implemented API
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 241393a39..979069cfa 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -502,8 +502,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return still_active; // true if removed an active transfer
 }
 
-bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport;
   ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr);
   qhd->qtd_overlay.halted = 0;
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
-- 
cgit v1.3.1


From 5a29db2787fea0ff9fe236d2631b2dcbc94aea50 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Jul 2023 15:52:55 +0700
Subject: add check for edpt_xfer() with halted, also reset data toggle when
 clear stall

---
 src/portable/ehci/ehci.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index b84de5191..02b843667 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -443,6 +443,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   ehci_qtd_t* qtd;
 
   if (epnum == 0) {
+    // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage
+    if (qhd->qtd_overlay.halted) {
+      qhd->qtd_overlay.halted = false;
+    }
+
     qtd = qtd_control(dev_addr);
     qtd_init(qtd, buffer, buflen);
 
@@ -450,6 +455,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     qtd->data_toggle = 1;
     qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
   } else {
+    // skip if endpoint is halted
+    TU_VERIFY(!qhd->qtd_overlay.halted);
+
     qtd = qtd_find_free();
     TU_ASSERT(qtd);
 
@@ -506,8 +514,9 @@ bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr)
 {
   ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr);
   qhd->qtd_overlay.halted = 0;
+  qhd->qtd_overlay.data_toggle = 0;
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
-  // TODO reset data toggle ?
+
   return true;
 }
 
@@ -881,8 +890,10 @@ static void qhd_remove_qtd(ehci_qhd_t *qhd) {
 
   qhd->attached_qtd = NULL;
   qhd->attached_buffer = 0;
+  hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
 
   qtd->used = 0; // free QTD
+  hcd_dcache_clean(qtd, sizeof(ehci_qtd_t));
 }
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 6021803d584a95efac5bc10f89ed970b2c1fa60e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Jul 2023 11:33:26 +0700
Subject: fix ci

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 13 ++++++-------
 src/portable/renesas/rusb2/rusb2_ra.h  |  9 ++++++---
 2 files changed, 12 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 83f0fdc4a..0380f36b9 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -49,17 +49,16 @@
     #define D0FIFOCTR CFIFOCTR
     #define D0FIFOCTR_b CFIFOCTR_b
   #endif
+
+  // Application API for setting IRQ number
+  void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+    rusb2_controller[rhport].irqnum = irqnum;
+  }
+
 #else
   #error "Unsupported MCU"
 #endif
 
-//--------------------------------------------------------------------+
-// Application API for setting IRQ number
-//--------------------------------------------------------------------+
-void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
-  rusb2_controller[rhport].irqnum = irqnum;
-}
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 8a4d2ad36..7ff272bbc 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -64,8 +64,14 @@ typedef struct {
 #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
   #define RUSB2_SUPPORT_HIGHSPEED
   #define RUSB2_CONTROLLER_COUNT 2
+
+  #define rusb2_is_highspeed_rhport(_p)  (_p == 1)
+  #define rusb2_is_highspeed_reg(_reg)   (_reg == RUSB2_REG(1))
 #else
   #define RUSB2_CONTROLLER_COUNT 1
+
+  #define rusb2_is_highspeed_rhport(_p)  (false)
+  #define rusb2_is_highspeed_reg(_reg)   (false)
 #endif
 
 // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
@@ -78,9 +84,6 @@ static rusb2_controller_t rusb2_controller[] = {
 
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
-#define rusb2_is_highspeed_rhport(_p)  (_p == 1)
-#define rusb2_is_highspeed_reg(_reg)   (_reg == RUSB2_REG(1))
-
 //--------------------------------------------------------------------+
 // RUSB2 API
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From e56d5443a8a87e932b22bc6315f30cd537fe0edf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Jul 2023 12:42:40 +0700
Subject: - revert usb address - more clean up

---
 src/portable/renesas/rusb2/dcd_rusb2.c |  6 +++---
 src/portable/renesas/rusb2/hcd_rusb2.c | 14 ++++----------
 2 files changed, 7 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 0380f36b9..9383923bd 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -51,7 +51,7 @@
   #endif
 
   // Application API for setting IRQ number
-  void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
     rusb2_controller[rhport].irqnum = irqnum;
   }
 
@@ -638,7 +638,7 @@ static void process_bus_reset(uint8_t rhport)
 static void process_set_address(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-  const uint32_t addr = rusb->USBADDR & 0xFF;
+  const uint16_t addr = rusb->USBADDR_b.USBADDR;
   if (!addr) return;
 
   const tusb_control_request_t setup_packet = {
@@ -821,7 +821,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   if ( rusb2_is_highspeed_rhport(rhport) ) {
     // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
-    // depending on the allocation scheme
+    //       depending on the allocation scheme
     rusb->PIPEBUF = 0x7C08;
   }
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index fef8bdf19..c5ed8ae55 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -32,21 +32,15 @@
 #include "host/hcd.h"
 #include "rusb2_type.h"
 
-#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
-// fallback
-#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_HOST
-#define CFG_TUSB_RHPORT1_MODE   0
-#endif
-
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
 
-  void osal_task_delay(uint32_t msec) {
-    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
-  }
+//  void osal_task_delay(uint32_t msec) {
+//    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
+//  }
 
 #else
   #error "Unsupported MCU"
@@ -785,7 +779,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 void hcd_int_handler(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-  static unsigned char attach_attempt = 0;
+  static unsigned char attach_attempt = 0; // TODO remove later
   unsigned is0 = rusb->INTSTS0;
   unsigned is1 = rusb->INTSTS1;
 
-- 
cgit v1.3.1


From feb58ebd54e68bc3b7f21b0d168417053c525f0a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Jul 2023 19:01:12 +0700
Subject: add uno r4 wih FLASH_IMAGE_START=0x4000, running but interrupt
 (systick) does not seems to work

---
 .idea/runConfigurations/ra4m1.xml                  |  2 +-
 .idea/runConfigurations/ra6m1.xml                  |  2 +-
 .idea/runConfigurations/ra6m5.xml                  |  2 +-
 .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h      | 18 ++---
 hw/bsp/ra/boards/uno_r4/board.cmake                | 11 +++
 hw/bsp/ra/boards/uno_r4/board.h                    | 53 +++++++++++++
 hw/bsp/ra/boards/uno_r4/board.mk                   |  9 +++
 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h      | 35 +++++++++
 .../boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h |  5 ++
 .../uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h     | 11 +++
 .../boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 87 ++++++++++++++++++++++
 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h    | 21 ++++++
 hw/bsp/ra/boards/uno_r4/uno_r4.ld                  | 25 +++++++
 hw/bsp/ra/family.mk                                |  3 +-
 src/portable/renesas/rusb2/hcd_rusb2.c             |  1 +
 15 files changed, 272 insertions(+), 13 deletions(-)
 create mode 100644 hw/bsp/ra/boards/uno_r4/board.cmake
 create mode 100644 hw/bsp/ra/boards/uno_r4/board.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/board.mk
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/uno_r4.ld

(limited to 'src')

diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
index 22bb61949..149a157c4 100644
--- a/.idea/runConfigurations/ra4m1.xml
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
index 438ac4063..57af9abd9 100644
--- a/.idea/runConfigurations/ra6m1.xml
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
index 89f9787a0..1a6358304 100644
--- a/.idea/runConfigurations/ra6m5.xml
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index 3bde2db0d..72cdb89e6 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -12,16 +12,16 @@
 #define BSP_MOCO_HZ                 (8000000)
 #define BSP_SUB_CLOCK_HZ            (32768)
 #if   BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ             (24000000)
+  #define BSP_HOCO_HZ             (24000000)
 #elif BSP_CFG_HOCO_FREQUENCY == 2
-                #define BSP_HOCO_HZ             (32000000)
-            #elif BSP_CFG_HOCO_FREQUENCY == 4
-                #define BSP_HOCO_HZ             (48000000)
-            #elif BSP_CFG_HOCO_FREQUENCY == 5
-                #define BSP_HOCO_HZ             (64000000)
-            #else
-                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-            #endif
+  #define BSP_HOCO_HZ             (32000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 4
+  #define BSP_HOCO_HZ             (48000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 5
+  #define BSP_HOCO_HZ             (64000000)
+#else
+  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
 #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
 
diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake
new file mode 100644
index 000000000..34780d776
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.cmake
@@ -0,0 +1,11 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m1)
+
+set(JLINK_DEVICE R7FA4M1AB)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h
new file mode 100644
index 000000000..72abda27f
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1          BSP_IO_PORT_01_PIN_11 // D13
+#define LED_STATE_ON  1
+
+#define SW1                   BSP_IO_PORT_01_PIN_10 // D12
+#define BUTTON_STATE_ACTIVE   0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+    {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+    {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+    // USB FS D+, D-, VBus
+    {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk
new file mode 100644
index 000000000..cbe6c782c
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.mk
@@ -0,0 +1,9 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra4m1
+
+LD_FILE = $(BOARD_PATH)/${BOARD}.ld
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M1AB
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..c1d1022cc
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#undef RA_NOT_DEFINED
+#define BSP_CFG_RTOS (0)
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x800)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
+
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE	(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE		(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..336918800
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CNE
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (262144)
+#define BSP_RAM_SIZE_BYTES (32768)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_QFN
+#define BSP_PACKAGE_PINS (48)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..fc604eb3b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,87 @@
+/* generated configuration header file through renesas e2 studio */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA4M1 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+  #define BSP_HOCO_HZ             (24000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+  #define BSP_HOCO_HZ             (32000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 4
+  #define BSP_HOCO_HZ             (48000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 5
+  #define BSP_HOCO_HZ             (64000000)
+#else
+  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+#define BSP_MCU_VBATT_SUPPORT       (1)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+            #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+            #else
+/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..63618ec4b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld
new file mode 100644
index 000000000..45f11dfb1
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/uno_r4.ld
@@ -0,0 +1,25 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x8000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x40000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x01010018;
+ID_CODE_LENGTH = 0x20;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x0;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+/* Uno R4 has bootloader */
+FLASH_IMAGE_START = 0x4000;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index f5097460a..a5325306d 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -59,9 +59,10 @@ INC += \
 
 ifndef LD_FILE
 LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld
-LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
 endif
 
+LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
+
 # For freeRTOS port source
 # hack to use the port provided by renesas
 FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index c5ed8ae55..7f49dc8a9 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -186,6 +186,7 @@ static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num)
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
+  // NOTE: unlike DCD, Highspeed 32-bit FIFO does not need to adjust the fifo address
   volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
   uintptr_t addr = (uintptr_t)buf;
   while (len >= 2) {
-- 
cgit v1.3.1


From 0d9973ef87a55276d14c2aa45647f92a8358e9a2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 31 Jul 2023 16:21:19 +0700
Subject: enable_irq since uno bootloader can disable it. systick triggered,
 however usb still not work with uno

---
 hw/bsp/ra/family.c                     | 4 ++++
 src/portable/renesas/rusb2/dcd_rusb2.c | 1 +
 2 files changed, 5 insertions(+)

(limited to 'src')

diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index b78fdedc7..096f0d0ff 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -92,6 +92,10 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
 //--------------------------------------------------------------------+
 
 void board_init(void) {
+  // Enable global interrupts in CPSR register since board with bootloader such as Arduino Uno R4
+  // can transfer CPU control with CPSR.I bit set to 0 (disable IRQ)
+  __enable_irq();
+
   /* Configure pins. */
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9383923bd..37fd93497 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -740,6 +740,7 @@ void dcd_init(uint8_t rhport)
   rusb->BEMPENB = 1;
   rusb->BRDYENB = 1;
 
+  // If VBUS (detect) pin is not used, application need to call tud_connect() manually after tud_init()
   if (rusb->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }
-- 
cgit v1.3.1


From cb47231518d8a33bb9c5ab710c819049274d443b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 31 Jul 2023 17:13:21 +0700
Subject: revert out of scope changes

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index c8eb91be3..15c48be47 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -258,7 +258,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
+void osal_task_delay(uint32_t msec)
 {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
-- 
cgit v1.3.1


From 3f788a4e5a7758ce51cbcadef4ac21e427cc3c56 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 31 Jul 2023 19:09:40 +0700
Subject: enable USBMC for uno r4, add board_init_after_tusb() API

add BOARD_UPPERCASE for board detection
---
 examples/device/audio_4_channel_mic/src/main.c    | 4 ++++
 examples/device/audio_test/src/main.c             | 4 ++++
 examples/device/audio_test_multi_rate/src/main.c  | 4 ++++
 examples/device/cdc_dual_ports/src/main.c         | 4 ++++
 examples/device/cdc_msc/src/main.c                | 4 ++++
 examples/device/cdc_msc_freertos/src/main.c       | 4 ++++
 examples/device/dfu/src/main.c                    | 4 ++++
 examples/device/dfu_runtime/src/main.c            | 4 ++++
 examples/device/dynamic_configuration/src/main.c  | 4 ++++
 examples/device/hid_boot_interface/src/main.c     | 4 ++++
 examples/device/hid_composite/src/main.c          | 4 ++++
 examples/device/hid_composite_freertos/src/main.c | 4 ++++
 examples/device/hid_generic_inout/src/main.c      | 4 ++++
 examples/device/hid_multiple_interface/src/main.c | 4 ++++
 examples/device/midi_test/src/main.c              | 4 ++++
 examples/device/msc_dual_lun/src/main.c           | 4 ++++
 examples/device/net_lwip_webserver/src/main.c     | 4 ++++
 examples/device/uac2_headset/src/main.c           | 4 ++++
 examples/device/usbtmc/src/main.c                 | 4 ++++
 examples/device/video_capture/src/main.c          | 4 ++++
 examples/device/webusb_serial/src/main.c          | 4 ++++
 examples/dual/host_hid_to_device_cdc/src/main.c   | 4 ++++
 examples/host/bare_api/src/main.c                 | 4 ++++
 examples/host/cdc_msc_hid/src/main.c              | 4 ++++
 examples/host/hid_controller/src/main.c           | 4 ++++
 examples/host/msc_file_explorer/src/main.c        | 5 +++++
 examples/make.mk                                  | 2 ++
 hw/bsp/board.h                                    | 3 +++
 hw/bsp/family_support.cmake                       | 5 +++++
 hw/bsp/ra/boards/uno_r4/board.mk                  | 2 +-
 hw/bsp/ra/family.c                                | 7 +++++++
 src/portable/renesas/rusb2/dcd_rusb2.c            | 2 --
 32 files changed, 123 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 2b9c5143d..f5fc884bd 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -84,6 +84,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // Init values
   sampFreq = AUDIO_SAMPLE_RATE;
   clkValid = 1;
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index b5ca41d36..6dc655416 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -85,6 +85,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // Init values
   sampFreq = AUDIO_SAMPLE_RATE;
   clkValid = 1;
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 078e783eb..637be2d40 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -99,6 +99,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // Init values
   sampFreq = sampleRatesList[0];
   clkValid = 1;
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 70eaea85d..7ceff73b3 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -42,6 +42,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index 6dad73cbf..87fc33181 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -58,6 +58,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0e8a24d02..6cfef9ef5 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -136,6 +136,10 @@ void usb_device_task(void* param)
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // RTOS forever loop
   while (1)
   {
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 5f37f25e1..bcd5b4942 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -77,6 +77,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 4ec3cb188..beef1037d 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -72,6 +72,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 578f01d8c..6c7789138 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -59,6 +59,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 1a155996a..47f68f8fa 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -59,6 +59,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 8d0e6bece..d4c5f5b3e 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -60,6 +60,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index ca02af100..bdbe26b86 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -138,6 +138,10 @@ void usb_device_task(void* param)
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // RTOS forever loop
   while (1)
   {
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5db8f5581..5b3e53b06 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -83,6 +83,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 72240b208..94f845a84 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -64,6 +64,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 2c3e9d954..c77207ca2 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -65,6 +65,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index c7f6de7bf..d8abb5151 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -57,6 +57,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 19a0eae9d..22543880e 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -232,6 +232,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   /* initialize lwip, dhcp-server, dns-server, and http */
   init_lwip();
   while (!netif_is_up(&netif_data));
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 19a3f7bae..c502eb10d 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -105,6 +105,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   TU_LOG1("Headset running\r\n");
 
   while (1)
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 2bba336f1..fa7de7570 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -57,6 +57,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 5654e0b61..b942dd30e 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -59,6 +59,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index eaca78c73..f63d0ccea 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -96,6 +96,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 817c63c70..5a31b9dda 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -83,6 +83,10 @@ int main(void)
   tud_init(BOARD_TUD_RHPORT);
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index bb7fa850e..7286befe0 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -67,6 +67,10 @@ int main(void)
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     // tinyusb host task
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 1f4acb822..51251be5c 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -48,6 +48,10 @@ int main(void)
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     // tinyusb host task
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 4dcc92587..a4ab2f711 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -54,6 +54,10 @@ int main(void)
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     // tinyusb host task
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index 7b1c2ef27..fc4b4e669 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -80,6 +80,11 @@ int main(void)
 
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   msc_app_init();
 
   while (1)
diff --git a/examples/make.mk b/examples/make.mk
index 3c3a920cc..4001a5359 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -116,6 +116,8 @@ INC += \
   $(TOP)/$(FAMILY_PATH) \
   $(TOP)/src \
 
+BOARD_UPPER = $(shell echo $(BOARD) | tr a-z A-Z)
+CFLAGS += -DBOARD_$(BOARD_UPPER)
 
 # Log level is mapped to TUSB DEBUG option
 ifneq ($(LOG),)
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 036556731..d782013bb 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -54,6 +54,9 @@
 // Initialize on-board peripherals : led, button, uart and USB
 void board_init(void);
 
+// Init board after tinyusb is initialized
+void board_init_after_tusb(void) TU_ATTR_WEAK;
+
 // Turn LED on or off
 void board_led_write(bool state);
 
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index d8298c8ad..db1ce988e 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -181,6 +181,11 @@ endfunction()
 function(family_configure_common TARGET RTOS)
   family_add_rtos(${TARGET} ${RTOS})
 
+  string(TOUPPER ${BOARD} BOARD_UPPER)
+  target_compile_definitions(${TARGET} PUBLIC
+    BOARD_${BOARD_UPPER}
+  )
+
   # run size after build
   add_custom_command(TARGET ${TARGET} POST_BUILD
     COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk
index cbe6c782c..b7075eec0 100644
--- a/hw/bsp/ra/boards/uno_r4/board.mk
+++ b/hw/bsp/ra/boards/uno_r4/board.mk
@@ -1,7 +1,7 @@
 CPU_CORE = cortex-m4
 MCU_VARIANT = ra4m1
 
-LD_FILE = $(BOARD_PATH)/${BOARD}.ld
+LD_FILE = ${BOARD_PATH}/${BOARD}.ld
 
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M1AB
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 096f0d0ff..e6213061d 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -124,6 +124,13 @@ void board_init(void) {
   board_led_write(false);
 }
 
+void board_init_after_tusb(void) {
+  // For board that use USB LDO regulator
+#if defined(BOARD_UNO_R4)
+  R_USB_FS0->USBMC |= R_USB_FS0_USBMC_VDCEN_Msk;
+#endif
+}
+
 void board_led_write(bool state) {
   R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
 }
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 37fd93497..9a3983f56 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -726,8 +726,6 @@ void dcd_init(uint8_t rhport)
 
     rusb->PHYSLEW = 0x5;
     rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
-
-    // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk);
   }
 
   /* Setup default control pipe */
-- 
cgit v1.3.1


From 965627e81c63a76bb80d8319cbd9adf931a00595 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Tue, 1 Aug 2023 11:41:33 +0200
Subject: rusb2: move dynamic irq function to c file

---
 hw/bsp/ra/family.cmake                 |  5 +++--
 hw/bsp/ra/family.mk                    |  1 +
 src/portable/renesas/rusb2/dcd_rusb2.c |  5 -----
 src/portable/renesas/rusb2/rusb2_ra.c  | 16 ++++++++++++++++
 src/portable/renesas/rusb2/rusb2_ra.h  |  9 +--------
 5 files changed, 21 insertions(+), 15 deletions(-)
 create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c

(limited to 'src')

diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 307e01da8..2d079dc94 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -114,8 +114,9 @@ function(family_configure_example TARGET RTOS)
     # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
-    ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
-    ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+  ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
+  ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+  ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index cf8e5d9e9..3394d41b4 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -32,6 +32,7 @@ endif
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
+	src/portable/renesas/rusb2/rusb2_ra.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9a3983f56..3ec1b70b5 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -50,11 +50,6 @@
     #define D0FIFOCTR_b CFIFOCTR_b
   #endif
 
-  // Application API for setting IRQ number
-  void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
-    rusb2_controller[rhport].irqnum = irqnum;
-  }
-
 #else
   #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
new file mode 100644
index 000000000..bbffd712e
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_ra.c
@@ -0,0 +1,16 @@
+#include "tusb_option.h"
+#include "device/dcd.h"
+#include "rusb2_type.h"
+#include "rusb2_ra.h"
+
+rusb2_controller_t rusb2_controller[] = {
+    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+    #ifdef RUSB2_SUPPORT_HIGHSPEED
+    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+    #endif
+};
+
+// Application API for setting IRQ number
+void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
+    rusb2_controller[rhport].irqnum = irqnum;
+}
\ No newline at end of file
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 7ff272bbc..4774d2e2c 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -74,14 +74,7 @@ typedef struct {
   #define rusb2_is_highspeed_reg(_reg)   (false)
 #endif
 
-// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
-static rusb2_controller_t rusb2_controller[] = {
-    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
-    #ifdef RUSB2_SUPPORT_HIGHSPEED
-    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
-    #endif
-};
-
+extern rusb2_controller_t rusb2_controller[];
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 04f1a34c39e109002c89e464103ebed6128c2903 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 1 Aug 2023 17:03:07 +0700
Subject: add rusb2_common.c for dynami irq

---
 hw/bsp/ra/family.cmake                    |  1 +
 hw/bsp/ra/family.mk                       |  1 +
 src/portable/renesas/rusb2/dcd_rusb2.c    |  5 ---
 src/portable/renesas/rusb2/hcd_rusb2.c    |  6 ---
 src/portable/renesas/rusb2/rusb2_common.c | 61 +++++++++++++++++++++++++++++++
 src/portable/renesas/rusb2/rusb2_ra.h     |  8 +---
 src/portable/renesas/rusb2/rusb2_type.h   |  1 +
 7 files changed, 65 insertions(+), 18 deletions(-)
 create mode 100644 src/portable/renesas/rusb2/rusb2_common.c

(limited to 'src')

diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 307e01da8..11bc7c668 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -116,6 +116,7 @@ function(family_configure_example TARGET RTOS)
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
     ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+    ${TOP}/src/portable/renesas/rusb2/rusb2_common.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 901808958..9afb38e06 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -34,6 +34,7 @@ endif
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
+	src/portable/renesas/rusb2/rusb2_common.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9a3983f56..3ec1b70b5 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -50,11 +50,6 @@
     #define D0FIFOCTR_b CFIFOCTR_b
   #endif
 
-  // Application API for setting IRQ number
-  void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
-    rusb2_controller[rhport].irqnum = irqnum;
-  }
-
 #else
   #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 7f49dc8a9..621320095 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -34,14 +34,8 @@
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
-
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
-
-//  void osal_task_delay(uint32_t msec) {
-//    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
-//  }
-
 #else
   #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/rusb2/rusb2_common.c b/src/portable/renesas/rusb2/rusb2_common.c
new file mode 100644
index 000000000..850060777
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_common.c
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if defined(TUP_USBIP_RUSB2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
+
+#include "rusb2_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+#include "rusb2_rx.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+#include "rusb2_ra.h"
+
+// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
+rusb2_controller_t rusb2_controller[] = {
+    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+    #ifdef RUSB2_SUPPORT_HIGHSPEED
+    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+    #endif
+};
+
+// Application API for setting IRQ number. May throw warnings for missing prototypes.
+void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  rusb2_controller[rhport].irqnum = irqnum;
+}
+
+//  void osal_task_delay(uint32_t msec) {
+//    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
+//  }
+
+#else
+  #error "Unsupported MCU"
+#endif
+
+
+#endif
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 7ff272bbc..259d3cbdb 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -74,13 +74,7 @@ typedef struct {
   #define rusb2_is_highspeed_reg(_reg)   (false)
 #endif
 
-// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
-static rusb2_controller_t rusb2_controller[] = {
-    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
-    #ifdef RUSB2_SUPPORT_HIGHSPEED
-    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
-    #endif
-};
+extern rusb2_controller_t rusb2_controller[];
 
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 005d7f2be..dd88f66a7 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -28,6 +28,7 @@
 #define _TUSB_RUSB2_TYPE_H_
 
 #include <stdint.h>
+#include <stddef.h>
 
 #ifdef __cplusplus
 extern "C" {
-- 
cgit v1.3.1


From edee46e7941f56f5024bf60d56921cfe10d1f7a5 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Tue, 1 Aug 2023 15:21:31 +0200
Subject: renesas: host: remove attach_attempt logic

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 10 ----------
 1 file changed, 10 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 621320095..f6683529a 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -774,7 +774,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 void hcd_int_handler(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-  static unsigned char attach_attempt = 0; // TODO remove later
   unsigned is0 = rusb->INTSTS0;
   unsigned is1 = rusb->INTSTS1;
 
@@ -789,23 +788,14 @@ void hcd_int_handler(uint8_t rhport)
   if (is1 & RUSB2_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
     rusb->DCPCTR_b.SQSET = 1;
-    attach_attempt = 0;
     hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
 
   if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
     hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
-    if(attach_attempt > 0) {
-      rusb->DVSTCTR0_b.UACT = 1;
-      _hcd.need_reset = true;
-      rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
-      hcd_event_device_attach(rhport, true);
-    }
-    attach_attempt--;
   }
 
   if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
-    attach_attempt = 10;
     rusb->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
     rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
-- 
cgit v1.3.1


From 979bf32266d379ec493ad31001b815d6a597b91e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Aug 2023 15:34:18 +0700
Subject: default class driver log level to CFG_TUH/TUD_LOG_LEVEL allow
 application to selectively disable usbd/usbh or driver log

---
 src/class/cdc/cdc_device.c     | 15 +++++++++++----
 src/class/cdc/cdc_host.c       |  9 ++++++---
 src/class/dfu/dfu_device.c     | 11 +++++++++--
 src/class/dfu/dfu_rt_device.c  | 13 ++++++++++---
 src/class/hid/hid_host.c       |  8 +++++---
 src/class/msc/msc_device.c     |  2 +-
 src/class/msc/msc_host.c       | 19 +++++++++++--------
 src/class/net/ncm_device.c     | 11 +++++++++--
 src/class/video/video_device.c | 23 +++++++++++++++--------
 src/host/usbh.c                |  7 -------
 src/host/usbh_classdriver.h    |  7 +++++++
 11 files changed, 84 insertions(+), 41 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index f658df4d0..70d9c2e24 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -33,6 +33,13 @@
 
 #include "cdc_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_CDC_LOG_LEVEL
+  #define CFG_TUD_CDC_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_CDC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -353,7 +360,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_SET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG2("  Set Line Coding\r\n");
+        TU_LOG_DRV("  Set Line Coding\r\n");
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
       else if ( stage == CONTROL_STAGE_ACK)
@@ -365,7 +372,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_GET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG2("  Get Line Coding\r\n");
+        TU_LOG_DRV("  Get Line Coding\r\n");
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
     break;
@@ -390,7 +397,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         // Disable fifo overwriting if DTR bit is set
         tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
 
-        TU_LOG2("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+        TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
 
         // Invoke callback
         if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
@@ -403,7 +410,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       }
       else if (stage == CONTROL_STAGE_ACK)
       {
-        TU_LOG2("  Send Break\r\n");
+        TU_LOG_DRV("  Send Break\r\n");
         if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue);
       }
     break;
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ce9f27c33..7f9ed18b3 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -33,9 +33,12 @@
 
 #include "cdc_host.h"
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define CDCH_DEBUG   2
-#define TU_LOG_DRV(...)   TU_LOG(CDCH_DEBUG, __VA_ARGS__)
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_CDC_LOG_LEVEL
+  #define CFG_TUH_CDC_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // Host CDC Interface
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index bffdb8376..3e7c13dea 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -37,6 +37,13 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_DFU_LOG_LEVEL
+  #define CFG_TUD_DFU_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_DFU_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
@@ -205,7 +212,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
 {
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
 
-  TU_LOG2("  DFU State  : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status));
+  TU_LOG_DRV("  DFU State  : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status));
 
   if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
   {
@@ -235,7 +242,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
   }
   else if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS )
   {
-    TU_LOG2("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
+    TU_LOG_DRV("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
 
     // Class request
     switch ( request->bRequest )
diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c
index 7b77b3f8f..a940d8d62 100644
--- a/src/class/dfu/dfu_rt_device.c
+++ b/src/class/dfu/dfu_rt_device.c
@@ -37,6 +37,13 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_DFU_RUNTIME_LOG_LEVEL
+  #define CFG_TUD_DFU_RUNTIME_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_DFU_RUNTIME_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
@@ -99,7 +106,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
   {
     case DFU_REQUEST_DETACH:
     {
-      TU_LOG2("  DFU RT Request: DETACH\r\n");
+      TU_LOG_DRV("  DFU RT Request: DETACH\r\n");
       tud_control_status(rhport, request);
       tud_dfu_runtime_reboot_to_dfu_cb();
     }
@@ -107,7 +114,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
 
     case DFU_REQUEST_GETSTATUS:
     {
-      TU_LOG2("  DFU RT Request: GETSTATUS\r\n");
+      TU_LOG_DRV("  DFU RT Request: GETSTATUS\r\n");
       dfu_status_response_t resp;
       // Status = OK, Poll timeout is ignored during RT, State = APP_IDLE, IString = 0
       TU_VERIFY(tu_memset_s(&resp, sizeof(resp), 0x00, sizeof(resp))==0);
@@ -117,7 +124,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
 
     default:
     {
-      TU_LOG2("  DFU RT Unexpected Request: %d\r\n", request->bRequest);
+      TU_LOG_DRV("  DFU RT Unexpected Request: %d\r\n", request->bRequest);
       return false; // stall unsupported request
     }
   }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 6abe298e5..4253170d4 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -33,10 +33,12 @@
 
 #include "hid_host.h"
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define HIDH_DEBUG   2
-#define TU_LOG_DRV(...)   TU_LOG(HIDH_DEBUG, __VA_ARGS__)
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_HID_LOG_LEVEL
+  #define CFG_TUH_HID_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
 
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_HID_LOG_LEVEL, __VA_ARGS__)
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index a602e9672..2589dcd2c 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -36,7 +36,7 @@
 
 // Level where CFG_TUSB_DEBUG must be at least for this driver is logged
 #ifndef CFG_TUD_MSC_LOG_LEVEL
-  #define CFG_TUD_MSC_LOG_LEVEL   2
+  #define CFG_TUD_MSC_LOG_LEVEL   CFG_TUD_LOG_LEVEL
 #endif
 
 #define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__)
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index d32c0adb0..a65208d69 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -33,9 +33,12 @@
 
 #include "msc_host.h"
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define MSCH_DEBUG   2
-#define TU_LOG_MSCH(...)   TU_LOG(MSCH_DEBUG, __VA_ARGS__)
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_MSC_LOG_LEVEL
+  #define CFG_TUH_MSC_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_MSC_LOG_LEVEL, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -308,7 +311,7 @@ void msch_close(uint8_t dev_addr)
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->configured, );
 
-  TU_LOG_MSCH("  MSCh close addr = %d\r\n", dev_addr);
+  TU_LOG_DRV("  MSCh close addr = %d\r\n", dev_addr);
 
   // invoke Application Callback
   if (p_msc->mounted) {
@@ -426,7 +429,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
   p_msc->configured = true;
 
   //------------- Get Max Lun -------------//
-  TU_LOG_MSCH("MSC Get Max Lun\r\n");
+  TU_LOG_DRV("MSC Get Max Lun\r\n");
   tusb_control_request_t const request =
   {
     .bmRequestType_bit =
@@ -465,7 +468,7 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   p_msc->max_lun++; // MAX LUN is minus 1 by specs
 
   // TODO multiple LUN support
-  TU_LOG_MSCH("SCSI Test Unit Ready\r\n");
+  TU_LOG_DRV("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
   tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
 }
@@ -478,14 +481,14 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d
   if (csw->status == 0)
   {
     // Unit is ready, read its capacity
-    TU_LOG_MSCH("SCSI Read Capacity\r\n");
+    TU_LOG_DRV("SCSI Read Capacity\r\n");
     tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0);
   }else
   {
     // Note: During enumeration, some device fails Test Unit Ready and require a few retries
     // with Request Sense to start working !!
     // TODO limit number of retries
-    TU_LOG_MSCH("SCSI Request Sense\r\n");
+    TU_LOG_DRV("SCSI Request Sense\r\n");
     TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0));
   }
 
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 611dc3348..226c42c4e 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -34,6 +34,13 @@
 #include "device/usbd_pvt.h"
 #include "net_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_NCM_LOG_LEVEL
+  #define CFG_TUD_NCM_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_NCM_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -473,13 +480,13 @@ bool tud_network_can_xmit(uint16_t size)
   TU_VERIFY(ncm_interface.itf_data_alt == 1);
 
   if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
-    TU_LOG2("NTB full [by count]\r\n");
+    TU_LOG_DRV("NTB full [by count]\r\n");
     return false;
   }
 
   size_t next_datagram_offset = ncm_interface.next_datagram_offset;
   if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
-    TU_LOG2("ntb full [by size]\r\n");
+    TU_LOG_DRV("ntb full [by size]\r\n");
     return false;
   }
 
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index e6fadf41b..abc43ccff 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -34,6 +34,13 @@
 
 #include "video_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_VIDEO_LOG_LEVEL
+  #define CFG_TUD_VIDEO_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_VIDEO_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -609,17 +616,17 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
-  TU_LOG2("    open VC %d\n", altnum);
+  TU_LOG_DRV("    open VC %d\n", altnum);
   uint8_t const *beg = self->beg;
   uint8_t const *end = beg + self->len;
 
   /* The first descriptor is a video control interface descriptor. */
   uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
-  TU_LOG2("    cur %d\n", cur - beg);
+  TU_LOG_DRV("    cur %d\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
-  TU_LOG2("    bInCollection %d\n", vc->ctl.bInCollection);
+  TU_LOG_DRV("    bInCollection %d\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
@@ -628,7 +635,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
 
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
-  TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
+  TU_LOG_DRV("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
@@ -662,7 +669,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm)
 static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
   uint_fast8_t i;
-  TU_LOG2("    reopen VS %d\n", altnum);
+  TU_LOG_DRV("    reopen VS %d\n", altnum);
   uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
@@ -672,7 +679,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     uint8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
     usbd_edpt_close(rhport, ep_adr);
     stm->desc.ep[i] = 0;
-    TU_LOG2("    close EP%02x\n", ep_adr);
+    TU_LOG_DRV("    close EP%02x\n", ep_adr);
   }
 
   /* clear transfer management information */
@@ -709,12 +716,12 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     }
     TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
-    TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
+    TU_LOG_DRV("    open EP%02x\n", _desc_ep_addr(cur));
   }
   if (altnum) {
     stm->state = VS_STATE_STREAMING;
   }
-  TU_LOG2("    done\n");
+  TU_LOG_DRV("    done\n");
   return true;
 }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index c8eb91be3..49f8c78f1 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -45,13 +45,6 @@
   #define CFG_TUH_INTERFACE_MAX   8
 #endif
 
-// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
-#ifndef CFG_TUH_LOG_LEVEL
-  #define CFG_TUH_LOG_LEVEL   2
-#endif
-
-#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
-
 //--------------------------------------------------------------------+
 // USBH-HCD common data structure
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index be9811641..308b4418a 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -35,6 +35,13 @@
  extern "C" {
 #endif
 
+// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
+#ifndef CFG_TUH_LOG_LEVEL
+  #define CFG_TUH_LOG_LEVEL   2
+#endif
+
+#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+
 enum {
   USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
 };
-- 
cgit v1.3.1


From 9560d0813f0872a1b8dfb337922b0ab5cc4cb811 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Wed, 2 Aug 2023 15:25:08 +0200
Subject: Set unmounted on configuration reset

---
 src/device/usbd.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 9429cf664..b4ca63c9c 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -965,7 +965,14 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
   }
 
   // invoke callback
-  if (tud_mount_cb) tud_mount_cb();
+  if (cfg_num)
+  {
+    if (tud_mount_cb) tud_mount_cb();
+  }
+  else
+  {
+    if (tud_umount_cb) tud_umount_cb();
+  }
 
   return true;
 }
-- 
cgit v1.3.1


From d09604d6364f4840669eda66a75f5df0926bb3e0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 11:07:23 +0700
Subject: Revert "Name queues for easier FreeRTOS debugging with task- and
 queue-aware debuggers"

This reverts commit 11fba59319d81fb9502fbf399abb4fe27cf3fa29.
---
 src/device/usbd.c        | 4 ++--
 src/host/usbh.c          | 4 ++--
 src/osal/osal_freertos.h | 5 ++---
 3 files changed, 6 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index b6c679b22..44c2530ce 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -279,7 +279,7 @@ tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbd_int_set, usbd_events, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
+OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
 tu_static osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
@@ -410,7 +410,7 @@ bool tud_init (uint8_t rhport)
 #endif
 
   // Init device queue & task
-  _usbd_q = osal_queue_create(&usbd_events);
+  _usbd_q = osal_queue_create(&_usbd_qdef);
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 987ff7a6e..f3e9d3858 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -219,7 +219,7 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
 // Event queue
 // usbh_int_set is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbh_int_set, usbh_events, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
+OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
 CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
@@ -330,7 +330,7 @@ bool tuh_init(uint8_t controller_id)
   TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t));
 
   // Event queue
-  _usbh_q = osal_queue_create( &usbh_events );
+  _usbh_q = osal_queue_create( &_usbh_qdef );
   TU_ASSERT(_usbh_q != NULL);
 
 #if OSAL_MUTEX_REQUIRED
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index e83277eb3..0b1b11589 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -56,7 +56,7 @@ typedef SemaphoreHandle_t osal_mutex_t;
 // _int_set is not used with an RTOS
 #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
   static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .pQueueName = #_name };
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
 
 typedef struct
 {
@@ -66,7 +66,6 @@ typedef struct
 #if configSUPPORT_STATIC_ALLOCATION
   StaticQueue_t sq;
 #endif
-  const char* pQueueName;
 }osal_queue_def_t;
 
 typedef QueueHandle_t osal_queue_t;
@@ -177,7 +176,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
     q = xQueueCreate(qdef->depth, qdef->item_sz);
   #endif
   #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
-    vQueueAddToRegistry(q, qdef->pQueueName);
+    vQueueAddToRegistry(q, "tinyUSB");
   #endif
   return q;
 }
-- 
cgit v1.3.1


From 473f37df958f74153f15c050c20d63f8defe89ed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 12:05:21 +0700
Subject: add osal queue name if needed

also mass change configQUEUE_REGISTRY_SIZE = 4
---
 .../src/FreeRTOSConfig/FreeRTOSConfig.h            |   2 +-
 .../src/FreeRTOSConfig/FreeRTOSConfig.h            |   2 +-
 hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h       |   2 +-
 hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h  |   2 +-
 hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h       |   2 +-
 hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h       |   2 +-
 hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h       |   2 +-
 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h         |   2 +-
 hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h         |   2 +-
 hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h          |   2 +-
 hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 src/osal/osal_freertos.h                           | 108 ++++++++++-----------
 18 files changed, 68 insertions(+), 74 deletions(-)

(limited to 'src')

diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 9bef9bbbf..69d638288 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 9bef9bbbf..69d638288 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
index f95927069..b65d8f1f9 100644
--- a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
index a46af1759..2a2bce261 100644
--- a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
index 1b3c64e0b..ea568dfc9 100644
--- a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               3
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
index 96611ca1c..a48b54576 100644
--- a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
index b1cef793e..fc0ab1f2d 100644
--- a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
index b1cef793e..fc0ab1f2d 100644
--- a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
index a56f243ea..efd26a3a7 100644
--- a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
index 8c39a2fb8..4ef5dd883 100644
--- a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
index fc2f9fc67..33440d288 100644
--- a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
index 5a6b2300b..580fe02bb 100644
--- a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
index 815e567dd..4615640ed 100644
--- a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
index c8736f6d1..02bfaf97a 100644
--- a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
index 95fcbb08a..17c2a0c5c 100644
--- a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
index 6881385a8..6a1f6c043 100644
--- a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
index e6a735ddd..c12b0dc85 100644
--- a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 0b1b11589..501e0bddd 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -52,53 +52,60 @@ extern "C" {
 
 typedef SemaphoreHandle_t osal_semaphore_t;
 typedef SemaphoreHandle_t osal_mutex_t;
-
-// _int_set is not used with an RTOS
-#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
-  static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+typedef QueueHandle_t osal_queue_t;
 
 typedef struct
 {
   uint16_t depth;
   uint16_t item_sz;
   void*    buf;
+
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  char const* name;
+#endif
+
 #if configSUPPORT_STATIC_ALLOCATION
   StaticQueue_t sq;
 #endif
-}osal_queue_def_t;
+} osal_queue_def_t;
 
-typedef QueueHandle_t osal_queue_t;
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  #define _OSAL_Q_NAME(_name) .name = #_name
+#else
+  #define _OSAL_Q_NAME(_name)
+#endif
+
+// _int_set is not used with an RTOS
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
+  static _type _name##_##buf[_depth];\
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, _OSAL_Q_NAME(_name) };
 
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec)
-{
-  if (msec == OSAL_TIMEOUT_WAIT_FOREVER) return portMAX_DELAY;
-  if (msec == 0) return 0;
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) {
+  if ( msec == OSAL_TIMEOUT_WAIT_FOREVER ) return portMAX_DELAY;
+  if ( msec == 0 ) return 0;
 
   uint32_t ticks = pdMS_TO_TICKS(msec);
 
   // configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms
   // we still need to delay at least 1 tick
-  if (ticks == 0) ticks =1 ;
+  if ( ticks == 0 ) ticks = 1;
 
   return ticks;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
-  vTaskDelay( pdMS_TO_TICKS(msec) );
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
+  vTaskDelay(pdMS_TO_TICKS(msec));
 }
 
 //--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) {
 #if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateBinaryStatic(semdef);
 #else
@@ -107,14 +114,10 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
-  if ( !in_isr )
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+  if ( !in_isr ) {
     return xSemaphoreGive(sem_hdl) != 0;
-  }
-  else
-  {
+  } else {
     BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
 
@@ -129,13 +132,11 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   return xSemaphoreTake(sem_hdl, _osal_ms2tick(msec));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
   xQueueReset(sem_hdl);
 }
 
@@ -143,8 +144,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 // MUTEX API (priority inheritance)
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
 #if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateMutexStatic(mdef);
 #else
@@ -153,13 +153,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return xSemaphoreGive(mutex_hdl);
 }
 
@@ -167,38 +165,35 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 // QUEUE API
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   osal_queue_t q;
-  #if configSUPPORT_STATIC_ALLOCATION
-    q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
-  #else
-    q = xQueueCreate(qdef->depth, qdef->item_sz);
-  #endif
-  #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
-    vQueueAddToRegistry(q, "tinyUSB");
-  #endif
+
+#if configSUPPORT_STATIC_ALLOCATION
+  q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+#else
+  q = xQueueCreate(qdef->depth, qdef->item_sz);
+#endif
+
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  vQueueAddToRegistry(q, qdef->name);
+#endif
+
   return q;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   return xQueueReceive(qhdl, data, _osal_ms2tick(msec));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
-  if ( !in_isr )
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
+  if ( !in_isr ) {
     return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0;
-  }
-  else
-  {
+  } else {
     BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
+    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 (IDF v5)
     if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
 #else
     portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
@@ -208,13 +203,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   return uxQueueMessagesWaiting(qhdl) == 0;
 }
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif
-- 
cgit v1.3.1


From a160da1f2b941741234f429417798b8df5c33294 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 17:19:47 +0700
Subject: add lpc43 family

---
 .github/workflows/cmake_arm.yml               |   2 +-
 examples/device/hid_boot_interface/src/main.c |   2 +-
 examples/typec/power_delivery/src/main.c      |   2 +-
 hw/bsp/board_api.h                            |   6 +-
 hw/bsp/ea4357/board.mk                        |  48 ----
 hw/bsp/ea4357/ea4357.c                        | 301 ----------------------
 hw/bsp/ea4357/lpc4357.ld                      | 324 ------------------------
 hw/bsp/ea4357/pca9532.c                       | 352 --------------------------
 hw/bsp/ea4357/pca9532.h                       |  94 -------
 hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h  | 165 ++++++++++++
 hw/bsp/lpc43/boards/ea4357/board.cmake        |  16 ++
 hw/bsp/lpc43/boards/ea4357/board.h            |  40 +++
 hw/bsp/lpc43/boards/ea4357/board.mk           |  11 +
 hw/bsp/lpc43/boards/ea4357/lpc4357.ld         | 324 ++++++++++++++++++++++++
 hw/bsp/lpc43/boards/ea4357/pca9532.c          | 352 ++++++++++++++++++++++++++
 hw/bsp/lpc43/boards/ea4357/pca9532.h          |  94 +++++++
 hw/bsp/lpc43/family.c                         | 312 +++++++++++++++++++++++
 hw/bsp/lpc43/family.cmake                     |  97 +++++++
 hw/bsp/lpc43/family.mk                        |  34 +++
 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h  |   9 +
 20 files changed, 1462 insertions(+), 1123 deletions(-)
 delete mode 100644 hw/bsp/ea4357/board.mk
 delete mode 100644 hw/bsp/ea4357/ea4357.c
 delete mode 100644 hw/bsp/ea4357/lpc4357.ld
 delete mode 100644 hw/bsp/ea4357/pca9532.c
 delete mode 100644 hw/bsp/ea4357/pca9532.h
 create mode 100644 hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/lpc43/boards/ea4357/board.cmake
 create mode 100644 hw/bsp/lpc43/boards/ea4357/board.h
 create mode 100644 hw/bsp/lpc43/boards/ea4357/board.mk
 create mode 100644 hw/bsp/lpc43/boards/ea4357/lpc4357.ld
 create mode 100644 hw/bsp/lpc43/boards/ea4357/pca9532.c
 create mode 100644 hw/bsp/lpc43/boards/ea4357/pca9532.h
 create mode 100644 hw/bsp/lpc43/family.c
 create mode 100644 hw/bsp/lpc43/family.cmake
 create mode 100644 hw/bsp/lpc43/family.mk

(limited to 'src')

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 276360650..5203337ec 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -35,7 +35,7 @@ jobs:
           # Alphabetical order
           - 'imxrt'
           - 'kinetis_kl'
-          - 'lpc18 lpc40'
+          - 'lpc18 lpc40 lpc43'
           - 'lpc55'
           - 'mcx'
           - 'ra'
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 1a155996a..18f301ff0 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index 08590aa74..489d01aa1 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index a7f3826d1..7249f618d 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -112,10 +112,14 @@ static inline void board_led_off(void) {
 static inline void board_delay(uint32_t ms) {
   uint32_t start_ms = board_millis();
   while ( board_millis() - start_ms < ms ) {
-    #if CFG_TUD_ENABLED
     // take chance to run usb background
+    #if CFG_TUD_ENABLED
     tud_task();
     #endif
+
+    #if CFG_TUH_ENABLED
+    tuh_task();
+    #endif
   }
 }
 
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
deleted file mode 100644
index 6fd229166..000000000
--- a/hw/bsp/ea4357/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib \
-  -DCORE_M4 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
-
-SRC_C += \
-	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
-	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
-	src/portable/ehci/ehci.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
-	$(MCU_DIR)/src/chip_18xx_43xx.c \
-	$(MCU_DIR)/src/clock_18xx_43xx.c \
-	$(MCU_DIR)/src/gpio_18xx_43xx.c \
-	$(MCU_DIR)/src/sysinit_18xx_43xx.c \
-	$(MCU_DIR)/src/i2c_18xx_43xx.c \
-	$(MCU_DIR)/src/i2cm_18xx_43xx.c \
-	$(MCU_DIR)/src/uart_18xx_43xx.c \
-	$(MCU_DIR)/src/fpu_init.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4357_M4
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/ea4357/ea4357.c
deleted file mode 100644
index 06975b8cc..000000000
--- a/hw/bsp/ea4357/ea4357.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "../board_api.h"
-#include "pca9532.h"
-
-#define UART_DEV        LPC_USART0
-#define UART_PORT       0x0f
-#define UART_PIN_TX     10
-#define UART_PIN_RX     11
-
-// P9_1 joystick down
-#define BUTTON_PORT     4
-#define BUTTON_PIN      13
-
-//static const struct {
-//  uint8_t mux_port;
-//  uint8_t mux_pin;
-//
-//  uint8_t gpio_port;
-//  uint8_t gpio_pin;
-//}buttons[] =
-//{
-//    {0x0a, 3, 4, 10 }, // Joystick up
-//    {0x09, 1, 4, 13 }, // Joystick down
-//    {0x0a, 2, 4, 9  }, // Joystick left
-//    {0x09, 0, 4, 12 }, // Joystick right
-//    {0x0a, 1, 4, 8  }, // Joystick press
-//    {0x02, 7, 0, 7  }, // SW6
-//};
-
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
-
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
-
-/* System configuration variables used by chip driver */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // Button ( Joystick down )
-  {0x9, 1,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)},
-
-  // UART
-  {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1},
-  {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1},
-
-  // USB
-};
-
-/* Pin clock mux values, re-used structure, value in first index is meaningless */
-static const PINMUX_GRP_T pinclockmuxing[] =
-{
-  {0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-#ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
-  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
-
-#if __FPU_USED == 1
-	fpuInit();
-#endif
-#endif // __USE_LPCOPEN
-
-	/* Setup system level pin muxing */
-	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-
-	/* Clock pins only, group field not used */
-	for (int i = 0; i <(int)  (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
-	{
-		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
-	}
-
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO_PORT);
-
-  // LED via pca9532 I2C
-  Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
-  Chip_I2C_Init(I2C0);
-  Chip_I2C_SetClockRate(I2C0, 100000);
-  Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
-
-  pca9532_init();
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
-
-  //------------- UART -------------//
-	Chip_UART_Init(UART_DEV);
-	Chip_UART_SetBaud(UART_DEV, CFG_BOARD_UART_BAUDRATE);
-	Chip_UART_ConfigData(UART_DEV, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS);
-	Chip_UART_TXEnable(UART_DEV);
-
-  //------------- USB -------------//
-  enum {
-    USBMODE_DEVICE = 2,
-    USBMODE_HOST   = 3
-  };
-
-  enum {
-    USBMODE_VBUS_LOW  = 0,
-    USBMODE_VBUS_HIGH = 1
-  };
-
-  /* From EA4357 user manual
-   *
-   * USB0 Device operation:
-   * - Insert jumpers in position 1-2 in JP17/JP18/JP19.
-   * - GPIO28 controls USB connect functionality
-   * - LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted by default.
-   * - LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS
-   * sensing.
-   *
-   * USB0 Host operation:
-   * - insert jumpers in position 2-3 in JP17/JP18/JP19.
-   * - USB Host power is controlled via distribution switch U20 (found in schematic page 11).
-   * - Signal GPIO26 is active low and enables +5V on VBUS2.
-   * - LED35 light whenever +5V is present on VBUS2.
-   * - GPIO55 is connected to status feedback from the distribution switch.
-   * - GPIO54 is used for VBUS sensing. 15Kohm pull-down resistors are always active
-   *
-   * Note:
-   * - Insert jumpers in position 2-3 in JP17/JP18/JP19
-   * - Insert jumpers in JP31 (OTG)
-   */
-#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0)
-  Chip_USB0_Init();
-#endif
-
-  /* From EA4357 user manual
-   *
-   * For USB1 Device:
-   * - a 1.5Kohm pull-up resistor is needed on the USB DP data signal. There are two methods to create this.
-   * JP15 is inserted and the pull-up resistor is always enabled. Alternatively, the pull-up resistor is activated
-   * inside the USB OTG chip (U31), and this has to be done via the I2C interface of GPIO52/GPIO53. In the latter case,
-   * JP15 shall not be inserted.
-   * - J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for
-   * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status
-   * of VBUS can be read via U31.
-   * - JP16 shall not be inserted.
-   *
-   * For USB1 Host:
-   * - 15Kohm pull-down resistors are needed on the USB data signals. These are activated inside the USB OTG chip (U31),
-   * and this has to be done via the I2C interface of GPIO52/GPIO53.
-   * - J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB
-   * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default
-   * since SJ5 is normally connected between pin 1-2.
-   * - LED34 lights green when +5V is available on J20.
-   * - JP15 shall not be inserted. JP16 has no effect
-   */
-#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1)
-  Chip_USB1_Init();
-#endif
-
-  // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
-  Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
-
-  #if PORT_SUPPORT_DEVICE(0)
-  // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
-  Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
-  #endif
-
-  // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
-  // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
-}
-
-//--------------------------------------------------------------------+
-// USB Interrupt Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(0)
-    tud_int_handler(0);
-  #endif
-
-  #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
-  #endif
-}
-
-void USB1_IRQHandler(void)
-{
-  #if PORT_SUPPORT_DEVICE(1)
-    tud_int_handler(1);
-  #endif
-
-  #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  if (state)
-  {
-    pca9532_setLeds( LED1, 0 );
-  }else
-  {
-    pca9532_setLeds( 0, LED1);
-  }
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  return Chip_UART_Read(UART_DEV, buf, len);
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
-    while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
-    Chip_UART_SendByte(UART_DEV, buf8[i]);
-  }
-
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/ea4357/lpc4357.ld b/hw/bsp/ea4357/lpc4357.ld
deleted file mode 100644
index e3dfbfda1..000000000
--- a/hw/bsp/ea4357/lpc4357.ld
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * GENERATED FILE - DO NOT EDIT
- * (c) Code Red Technologies Ltd, 2008-2013
- * (c) NXP Semiconductors 2013-2019
- * Generated linker script file for LPC4357
- * Created from linkscript.ldt by FMCreateLinkLibraries
- * Using Freemarker v2.3.23
- * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:48:43 PM
- */
-
-MEMORY
-{
-  /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
-}
-
-  /* Define a symbol for the top of each memory region */
-  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
-  __base_Flash = 0x1a000000 ; /* Flash */
-  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
-  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
-  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
-  __base_Flash2 = 0x1b000000 ; /* Flash2 */
-  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
-  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
-  __base_RAM = 0x10000000 ; /* RAM */
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
-  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
-  __base_RAM2 = 0x10080000 ; /* RAM2 */
-  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
-  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
-  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
-  __base_RAM3 = 0x20000000 ; /* RAM3 */
-  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
-  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
-  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
-  __base_RAM4 = 0x20008000 ; /* RAM4 */
-  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
-  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
-  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
-  __base_RAM5 = 0x2000c000 ; /* RAM5 */
-  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
-  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
-
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-    .text_Flash2 : ALIGN(4)
-    {
-       FILL(0xff)
-        *(.text_Flash2*) /* for compatibility with previous releases */
-        *(.text_MFlashB512*) /* for compatibility with previous releases */
-        *(.text.$Flash2*)
-        *(.text.$MFlashB512*)
-        *(.rodata.$Flash2*)
-        *(.rodata.$MFlashB512*)
-    } > MFlashB512
-
-    /* MAIN TEXT SECTION */
-    .text : ALIGN(4)
-    {
-        FILL(0xff)
-        __vectors_start__ = ABSOLUTE(.) ;
-        KEEP(*(.isr_vector))
-        /* Global Section Table */
-        . = ALIGN(4) ;
-        __section_table_start = .;
-        __data_section_table = .;
-        LONG(LOADADDR(.data));
-        LONG(    ADDR(.data));
-        LONG(  SIZEOF(.data));
-        LONG(LOADADDR(.data_RAM2));
-        LONG(    ADDR(.data_RAM2));
-        LONG(  SIZEOF(.data_RAM2));
-        LONG(LOADADDR(.data_RAM3));
-        LONG(    ADDR(.data_RAM3));
-        LONG(  SIZEOF(.data_RAM3));
-        LONG(LOADADDR(.data_RAM4));
-        LONG(    ADDR(.data_RAM4));
-        LONG(  SIZEOF(.data_RAM4));
-        LONG(LOADADDR(.data_RAM5));
-        LONG(    ADDR(.data_RAM5));
-        LONG(  SIZEOF(.data_RAM5));
-        __data_section_table_end = .;
-        __bss_section_table = .;
-        LONG(    ADDR(.bss));
-        LONG(  SIZEOF(.bss));
-        LONG(    ADDR(.bss_RAM2));
-        LONG(  SIZEOF(.bss_RAM2));
-        LONG(    ADDR(.bss_RAM3));
-        LONG(  SIZEOF(.bss_RAM3));
-        LONG(    ADDR(.bss_RAM4));
-        LONG(  SIZEOF(.bss_RAM4));
-        LONG(    ADDR(.bss_RAM5));
-        LONG(  SIZEOF(.bss_RAM5));
-        __bss_section_table_end = .;
-        __section_table_end = . ;
-        /* End of Global Section Table */
-
-        *(.after_vectors*)
-
-    } > MFlashA512
-
-    .text : ALIGN(4)
-    {
-       *(.text*)
-       *(.rodata .rodata.* .constdata .constdata.*)
-       . = ALIGN(4);
-    } > MFlashA512
-    /*
-     * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this.
-     */
-    .ARM.extab : ALIGN(4)
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > MFlashA512
-
-    __exidx_start = .;
-
-    .ARM.exidx : ALIGN(4)
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > MFlashA512
-    __exidx_end = .;
-
-    _etext = .;
-
-    /* DATA section for RamLoc40 */
-
-    .data_RAM2 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM2 = .) ;
-        *(.ramfunc.$RAM2)
-        *(.ramfunc.$RamLoc40)
-        *(.data.$RAM2*)
-        *(.data.$RamLoc40*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM2 = .) ;
-     } > RamLoc40 AT>MFlashA512
-    /* DATA section for RamAHB32 */
-
-    .data_RAM3 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM3 = .) ;
-        *(.ramfunc.$RAM3)
-        *(.ramfunc.$RamAHB32)
-        *(.data.$RAM3*)
-        *(.data.$RamAHB32*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM3 = .) ;
-     } > RamAHB32 AT>MFlashA512
-    /* DATA section for RamAHB16 */
-
-    .data_RAM4 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM4 = .) ;
-        *(.ramfunc.$RAM4)
-        *(.ramfunc.$RamAHB16)
-        *(.data.$RAM4*)
-        *(.data.$RamAHB16*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM4 = .) ;
-     } > RamAHB16 AT>MFlashA512
-    /* DATA section for RamAHB_ETB16 */
-
-    .data_RAM5 : ALIGN(4)
-    {
-        FILL(0xff)
-        PROVIDE(__start_data_RAM5 = .) ;
-        *(.ramfunc.$RAM5)
-        *(.ramfunc.$RamAHB_ETB16)
-        *(.data.$RAM5*)
-        *(.data.$RamAHB_ETB16*)
-        . = ALIGN(4) ;
-        PROVIDE(__end_data_RAM5 = .) ;
-     } > RamAHB_ETB16 AT>MFlashA512
-    /* MAIN DATA SECTION */
-    .uninit_RESERVED : ALIGN(4)
-    {
-        KEEP(*(.bss.$RESERVED*))
-        . = ALIGN(4) ;
-        _end_uninit_RESERVED = .;
-    } > RamLoc32
-
-    /* Main DATA section (RamLoc32) */
-    .data : ALIGN(4)
-    {
-       FILL(0xff)
-       _data = . ;
-       *(vtable)
-       *(.ramfunc*)
-       *(.data*)
-       . = ALIGN(4) ;
-       _edata = . ;
-    } > RamLoc32 AT>MFlashA512
-
-    /* BSS section for RamLoc40 */
-    .bss_RAM2 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM2 = .) ;
-       *(.bss.$RAM2*)
-       *(.bss.$RamLoc40*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc40
-
-    /* BSS section for RamAHB32 */
-    .bss_RAM3 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM3 = .) ;
-       *(.bss.$RAM3*)
-       *(.bss.$RamAHB32*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32
-
-    /* BSS section for RamAHB16 */
-    .bss_RAM4 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM4 = .) ;
-       *(.bss.$RAM4*)
-       *(.bss.$RamAHB16*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16
-
-    /* BSS section for RamAHB_ETB16 */
-    .bss_RAM5 : ALIGN(4)
-    {
-       PROVIDE(__start_bss_RAM5 = .) ;
-       *(.bss.$RAM5*)
-       *(.bss.$RamAHB_ETB16*)
-       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
-       PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16
-
-    /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4) ;
-        _ebss = .;
-        PROVIDE(end = .);
-    } > RamLoc32
-
-    /* NOINIT section for RamLoc40 */
-    .noinit_RAM2 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM2*)
-       *(.noinit.$RamLoc40*)
-       . = ALIGN(4) ;
-    } > RamLoc40
-
-    /* NOINIT section for RamAHB32 */
-    .noinit_RAM3 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM3*)
-       *(.noinit.$RamAHB32*)
-       . = ALIGN(4) ;
-    } > RamAHB32
-
-    /* NOINIT section for RamAHB16 */
-    .noinit_RAM4 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM4*)
-       *(.noinit.$RamAHB16*)
-       . = ALIGN(4) ;
-    } > RamAHB16
-
-    /* NOINIT section for RamAHB_ETB16 */
-    .noinit_RAM5 (NOLOAD) : ALIGN(4)
-    {
-       *(.noinit.$RAM5*)
-       *(.noinit.$RamAHB_ETB16*)
-       . = ALIGN(4) ;
-    } > RamAHB_ETB16
-
-    /* DEFAULT NOINIT SECTION */
-    .noinit (NOLOAD): ALIGN(4)
-    {
-        _noinit = .;
-        *(.noinit*)
-         . = ALIGN(4) ;
-        _end_noinit = .;
-    } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
-    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
-
-    /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 -
-                                         (_vStackTop
-                                         + (ResetISR + 1)
-                                         + (NMI_Handler + 1)
-                                         + (HardFault_Handler + 1)
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
-
-    /* Provide basic symbols giving location and size of main text
-     * block, including initial values of RW data sections. Note that
-     * these will need extending to give a complete picture with
-     * complex images (e.g multiple Flash banks).
-     */
-    _image_start = LOADADDR(.text);
-    _image_end = LOADADDR(.data) + SIZEOF(.data);
-    _image_size = _image_end - _image_start;
-}
diff --git a/hw/bsp/ea4357/pca9532.c b/hw/bsp/ea4357/pca9532.c
deleted file mode 100644
index 150167cde..000000000
--- a/hw/bsp/ea4357/pca9532.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*****************************************************************************
- *
- *   Copyright(C) 2011, Embedded Artists AB
- *   All rights reserved.
- *
- ******************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * Embedded Artists AB assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. Embedded Artists AB
- * reserves the right to make changes in the software without
- * notification. Embedded Artists AB also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- *****************************************************************************/
-
-/*
- * NOTE: I2C must have been initialized before calling any functions in this
- * file.
- */
-
-/******************************************************************************
- * Includes
- *****************************************************************************/
-
-//#include "board.h"
-#include "chip.h"
-
-#include "pca9532.h"
-
-/******************************************************************************
- * Defines and typedefs
- *****************************************************************************/
-
-#define I2C_PORT (LPC_I2C0)
-
-#define LS_MODE_ON     0x01
-#define LS_MODE_BLINK0 0x02
-#define LS_MODE_BLINK1 0x03
-
-/******************************************************************************
- * External global variables
- *****************************************************************************/
-
-
-/******************************************************************************
- * Local variables
- *****************************************************************************/
-
-static uint16_t blink0Shadow = 0;
-static uint16_t blink1Shadow = 0;
-static uint16_t ledStateShadow = 0;
-
-/******************************************************************************
- * Local Functions
- *****************************************************************************/
-
-static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
-{
-	I2CM_XFER_T i2cData;
-
-	i2cData.slaveAddr = addr;
-	i2cData.options = 0;
-	i2cData.status = 0;
-	i2cData.txBuff = buf;
-	i2cData.txSz = len;
-	i2cData.rxBuff = NULL;
-	i2cData.rxSz = 0;
-
-	if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
-		return ERROR;
-	}
-	return SUCCESS;
-}
-
-static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
-{
-	I2CM_XFER_T i2cData;
-
-	i2cData.slaveAddr = addr;
-	i2cData.options = 0;
-	i2cData.status = 0;
-	i2cData.txBuff = NULL;
-	i2cData.txSz = 0;
-	i2cData.rxBuff = buf;
-	i2cData.rxSz = len;
-
-	if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
-		return ERROR;
-	}
-	return SUCCESS;
-}
-
-static void setLsStates(uint16_t states, uint8_t* ls, uint8_t mode)
-{
-#define IS_LED_SET(bit, x) ( ( ((x) & (bit)) != 0 ) ? 1 : 0 )
-
-    int i = 0;
-
-    for (i = 0; i < 4; i++) {
-
-        ls[i] |= ( (IS_LED_SET(0x0001, states)*mode << 0)
-                | (IS_LED_SET(0x0002, states)*mode << 2)
-                | (IS_LED_SET(0x0004, states)*mode << 4)
-                | (IS_LED_SET(0x0008, states)*mode << 6) );
-
-        states >>= 4;
-    }
-}
-
-static void setLeds(void)
-{
-    uint8_t buf[5];
-    uint8_t ls[4] = {0,0,0,0};
-    uint16_t states = ledStateShadow;
-
-    /* LEDs in On/Off state */
-    setLsStates(states, ls, LS_MODE_ON);
-
-    /* set the LEDs that should blink */
-    setLsStates(blink0Shadow, ls, LS_MODE_BLINK0);
-    setLsStates(blink1Shadow, ls, LS_MODE_BLINK1);
-
-
-    buf[0] = PCA9532_LS0 | PCA9532_AUTO_INC;
-    buf[1] = ls[0];
-    buf[2] = ls[1];
-    buf[3] = ls[2];
-    buf[4] = ls[3];
-    I2CWrite(PCA9532_I2C_ADDR, buf, 5);
-}
-
-/******************************************************************************
- * Public Functions
- *****************************************************************************/
-
-/******************************************************************************
- *
- * Description:
- *    Initialize the PCA9532 Device
- *
- *****************************************************************************/
-void pca9532_init (void)
-{
-    /* nothing to initialize */
-}
-
-/******************************************************************************
- *
- * Description:
- *    Get the LED states
- *
- * Params:
- *    [in]  shadow  - TRUE if the states should be retrieved from the shadow
- *                    variables. The shadow variable are updated when any
- *                    of setLeds, setBlink0Leds and/or setBlink1Leds are
- *                    called.
- *
- *                    FALSE if the state should be retrieved from the PCA9532
- *                    device. A blinkin LED may be reported as on or off
- *                    depending on the state when calling the function.
- *
- * Returns:
- *      A mask where a 1 indicates that a LED is on (or blinking).
- *
- *****************************************************************************/
-uint16_t pca9532_getLedState (uint32_t shadow)
-{
-    uint8_t buf[2];
-    uint16_t ret = 0;
-
-    if (shadow) {
-        /* a blink LED is reported as on*/
-        ret = (ledStateShadow | blink0Shadow | blink1Shadow);
-    }
-    else {
-
-        /*
-         * A blinking LED may be reported as on or off depending on
-         * its state when reading the Input register.
-         */
-
-        buf[0] = PCA9532_INPUT0;
-        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
-
-        I2CRead(PCA9532_I2C_ADDR, buf, 1);
-        ret = buf[0];
-
-
-        buf[0] = PCA9532_INPUT1;
-        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
-
-        I2CRead(PCA9532_I2C_ADDR, buf, 1);
-        ret |= (buf[0] << 8);
-
-
-        /* invert since LEDs are active low */
-        ret = ((~ret) & 0xFFFF);
-    }
-
-    return (ret & ~PCA9532_NOT_USED);
-}
-
-
-/******************************************************************************
- *
- * Description:
- *    Set LED states (on or off).
- *
- * Params:
- *    [in]  ledOnMask  - The LEDs that should be turned on. This mask has
- *                       priority over ledOffMask
- *    [in]  ledOffMask - The LEDs that should be turned off.
- *
- *****************************************************************************/
-void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask)
-{
-    /* turn off leds */
-    ledStateShadow &= (~(ledOffMask) & 0xffff);
-
-    /* ledOnMask has priority over ledOffMask */
-    ledStateShadow |= ledOnMask;
-
-    /* turn off blinking */
-    blink0Shadow &= (~(ledOffMask) & 0xffff);
-    blink1Shadow &= (~(ledOffMask) & 0xffff);
-
-    setLeds();
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the blink period for PWM0. Valid values are 0 - 255 where 0
- *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
- *
- * Params:
- *    [in]  period  - the period for pwm0
- *
- *****************************************************************************/
-void pca9532_setBlink0Period(uint8_t period)
-{
-    uint8_t buf[2];
-
-    buf[0] = PCA9532_PSC0;
-    buf[1] = period;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the duty cycle for PWM0. Valid values are 0 - 100. 25 means the LED
- *    is on 25% of the period.
- *
- * Params:
- *    [in]  duty  - duty cycle
- *
- *****************************************************************************/
-void pca9532_setBlink0Duty(uint8_t duty)
-{
-    uint8_t buf[2];
-    uint32_t tmp = duty;
-    if (tmp > 100) {
-        tmp = 100;
-    }
-
-    tmp = (256 * tmp)/100;
-
-    buf[0] = PCA9532_PWM0;
-    buf[1] = tmp;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the LEDs that should blink with rate and duty cycle from PWM0.
- *    Blinking is turned off with pca9532_setLeds.
- *
- * Params:
- *    [in]  ledMask  - LEDs that should blink.
- *
- *****************************************************************************/
-void pca9532_setBlink0Leds(uint16_t ledMask)
-{
-    blink0Shadow |= ledMask;
-    setLeds();
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the blink period for PWM1. Valid values are 0 - 255 where 0
- *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
- *
- * Params:
- *    [in]  period  - The period for PWM1
- *
- *****************************************************************************/
-void pca9532_setBlink1Period(uint8_t period)
-{
-    uint8_t buf[2];
-
-    buf[0] = PCA9532_PSC1;
-    buf[1] = period;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the duty cycle for PWM1. Valid values are 0 - 100. 25 means the LED
- *    is on 25% of the period.
- *
- * Params:
- *    [in]  duty  - duty cycle.
- *
- *****************************************************************************/
-void pca9532_setBlink1Duty(uint8_t duty)
-{
-    uint8_t buf[2];
-
-    uint32_t tmp = duty;
-    if (tmp > 100) {
-        tmp = 100;
-    }
-
-    tmp = (256 * tmp)/100;
-
-    buf[0] = PCA9532_PWM1;
-    buf[1] = tmp;
-    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
-}
-
-/******************************************************************************
- *
- * Description:
- *    Set the LEDs that should blink with rate and duty cycle from PWM1.
- *    Blinking is turned off with pca9532_setLeds.
- *
- * Params:
- *    [in]  ledMask  - LEDs that should blink.
- *
- *****************************************************************************/
-void pca9532_setBlink1Leds(uint16_t ledMask)
-{
-    blink1Shadow |= ledMask;
-    setLeds();
-}
diff --git a/hw/bsp/ea4357/pca9532.h b/hw/bsp/ea4357/pca9532.h
deleted file mode 100644
index f21c1ff09..000000000
--- a/hw/bsp/ea4357/pca9532.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*****************************************************************************
- *
- *   Copyright(C) 2011, Embedded Artists AB
- *   All rights reserved.
- *
- ******************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * Embedded Artists AB assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. Embedded Artists AB
- * reserves the right to make changes in the software without
- * notification. Embedded Artists AB also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
- *****************************************************************************/
-#ifndef __PCA9532C_H
-#define __PCA9532C_H
-
-
-#define PCA9532_I2C_ADDR    (0xC0>>1)
-
-#define PCA9532_INPUT0 0x00
-#define PCA9532_INPUT1 0x01
-#define PCA9532_PSC0   0x02
-#define PCA9532_PWM0   0x03
-#define PCA9532_PSC1   0x04
-#define PCA9532_PWM1   0x05
-#define PCA9532_LS0    0x06
-#define PCA9532_LS1    0x07
-#define PCA9532_LS2    0x08
-#define PCA9532_LS3    0x09
-
-#define PCA9532_AUTO_INC 0x10
-
-
-/*
- * The Keys on the base board are mapped to LED0 -> LED3 on
- * the PCA9532.
- */
-
-#define KEY1 0x0001
-#define KEY2 0x0002
-#define KEY3 0x0004
-#define KEY4 0x0008
-
-#define KEY_MASK 0x000F
-
-/*
- * MMC Card Detect and MMC Write Protect are mapped to LED4
- * and LED5 on the PCA9532. Please note that WP is active low.
- */
-
-#define MMC_CD 0x0010
-#define MMC_WP 0x0020
-
-#define MMC_MASK  0x30
-
-/* NOTE: LED6 and LED7 on PCA9532 are not connected to anything */
-#define PCA9532_NOT_USED 0xC0
-
-/*
- * Below are the LED constants to use when enabling/disabling a LED.
- * The LED names are the names printed on the base board and not
- * the names from the PCA9532 device. base_LED1 -> LED8 on PCA9532,
- * base_LED2 -> LED9, and so on.
- */
-
-#define LED1 0x0100
-#define LED2 0x0200
-#define LED3 0x0400
-#define LED4 0x0800
-#define LED5 0x1000
-#define LED6 0x2000
-#define LED7 0x4000
-#define LED8 0x8000
-
-#define LED_MASK 0xFF00
-
-void pca9532_init (void);
-uint16_t pca9532_getLedState (uint32_t shadow);
-void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask);
-void pca9532_setBlink0Period(uint8_t period);
-void pca9532_setBlink0Duty(uint8_t duty);
-void pca9532_setBlink0Leds(uint16_t ledMask);
-void pca9532_setBlink1Period(uint8_t period);
-void pca9532_setBlink1Duty(uint8_t duty);
-void pca9532_setBlink1Leds(uint16_t ledMask);
-
-#endif /* end __PCA9532C_H */
-/****************************************************************************
-**                            End Of File
-*****************************************************************************/
diff --git a/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6f80413c0
--- /dev/null
+++ b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc43/boards/ea4357/board.cmake b/hw/bsp/lpc43/boards/ea4357/board.cmake
new file mode 100644
index 000000000..8f4588463
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT LPC4357)
+
+set(JLINK_DEVICE LPC4357_M4)
+set(PYOCD_TARGET LPC4357)
+set(NXPLINK_DEVICE LPC4357:LPC4357)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4357.ld)
+
+function(update_board TARGET)
+  # EA4357 use I2C GPIO expander for LED
+  target_sources(${TARGET} PRIVATE
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pca9532.c
+    ${SDK_DIR}/src/i2c_18xx_43xx.c
+    ${SDK_DIR}/src/i2cm_18xx_43xx.c
+    )
+endfunction()
diff --git a/hw/bsp/lpc43/boards/ea4357/board.h b/hw/bsp/lpc43/boards/ea4357/board.h
new file mode 100644
index 000000000..f026324ef
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.h
@@ -0,0 +1,40 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_EA4357_H
+#define _BOARD_EA4357_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pca9532.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc43/boards/ea4357/board.mk b/hw/bsp/lpc43/boards/ea4357/board.mk
new file mode 100644
index 000000000..d0eb08d6d
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.mk
@@ -0,0 +1,11 @@
+# EA4357 use I2C GPIO expander for LED
+SRC_C += \
+  ${BOARD_PATH}/pca9532.c \
+	${SDK_DIR}/src/i2c_18xx_43xx.c \
+	${SDK_DIR}/src/i2cm_18xx_43xx.c \
+
+LD_FILE = ${BOARD_PATH}/lpc4357.ld
+
+JLINK_DEVICE = LPC4357_M4
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc43/boards/ea4357/lpc4357.ld b/hw/bsp/lpc43/boards/ea4357/lpc4357.ld
new file mode 100644
index 000000000..e3dfbfda1
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/lpc4357.ld
@@ -0,0 +1,324 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2019
+ * Generated linker script file for LPC4357
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:48:43 PM
+ */
+
+MEMORY
+{
+  /* Define each memory region */
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+}
+
+  /* Define a symbol for the top of each memory region */
+  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+  __base_Flash = 0x1a000000 ; /* Flash */
+  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+  __base_Flash2 = 0x1b000000 ; /* Flash2 */
+  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+  __base_RAM2 = 0x10080000 ; /* RAM2 */
+  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+  __base_RAM4 = 0x20008000 ; /* RAM4 */
+  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+  __base_RAM5 = 0x2000c000 ; /* RAM5 */
+  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+    .text_Flash2 : ALIGN(4)
+    {
+       FILL(0xff)
+        *(.text_Flash2*) /* for compatibility with previous releases */
+        *(.text_MFlashB512*) /* for compatibility with previous releases */
+        *(.text.$Flash2*)
+        *(.text.$MFlashB512*)
+        *(.rodata.$Flash2*)
+        *(.rodata.$MFlashB512*)
+    } > MFlashB512
+
+    /* MAIN TEXT SECTION */
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        __vectors_start__ = ABSOLUTE(.) ;
+        KEEP(*(.isr_vector))
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data));
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2));
+        LONG(  SIZEOF(.data_RAM2));
+        LONG(LOADADDR(.data_RAM3));
+        LONG(    ADDR(.data_RAM3));
+        LONG(  SIZEOF(.data_RAM3));
+        LONG(LOADADDR(.data_RAM4));
+        LONG(    ADDR(.data_RAM4));
+        LONG(  SIZEOF(.data_RAM4));
+        LONG(LOADADDR(.data_RAM5));
+        LONG(    ADDR(.data_RAM5));
+        LONG(  SIZEOF(.data_RAM5));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        LONG(    ADDR(.bss_RAM3));
+        LONG(  SIZEOF(.bss_RAM3));
+        LONG(    ADDR(.bss_RAM4));
+        LONG(  SIZEOF(.bss_RAM4));
+        LONG(    ADDR(.bss_RAM5));
+        LONG(  SIZEOF(.bss_RAM5));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+
+        *(.after_vectors*)
+
+    } > MFlashA512
+
+    .text : ALIGN(4)
+    {
+       *(.text*)
+       *(.rodata .rodata.* .constdata .constdata.*)
+       . = ALIGN(4);
+    } > MFlashA512
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > MFlashA512
+
+    __exidx_start = .;
+
+    .ARM.exidx : ALIGN(4)
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > MFlashA512
+    __exidx_end = .;
+
+    _etext = .;
+
+    /* DATA section for RamLoc40 */
+
+    .data_RAM2 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM2 = .) ;
+        *(.ramfunc.$RAM2)
+        *(.ramfunc.$RamLoc40)
+        *(.data.$RAM2*)
+        *(.data.$RamLoc40*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM2 = .) ;
+     } > RamLoc40 AT>MFlashA512
+    /* DATA section for RamAHB32 */
+
+    .data_RAM3 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM3 = .) ;
+        *(.ramfunc.$RAM3)
+        *(.ramfunc.$RamAHB32)
+        *(.data.$RAM3*)
+        *(.data.$RamAHB32*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM3 = .) ;
+     } > RamAHB32 AT>MFlashA512
+    /* DATA section for RamAHB16 */
+
+    .data_RAM4 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM4 = .) ;
+        *(.ramfunc.$RAM4)
+        *(.ramfunc.$RamAHB16)
+        *(.data.$RAM4*)
+        *(.data.$RamAHB16*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM4 = .) ;
+     } > RamAHB16 AT>MFlashA512
+    /* DATA section for RamAHB_ETB16 */
+
+    .data_RAM5 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM5 = .) ;
+        *(.ramfunc.$RAM5)
+        *(.ramfunc.$RamAHB_ETB16)
+        *(.data.$RAM5*)
+        *(.data.$RamAHB_ETB16*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM5 = .) ;
+     } > RamAHB_ETB16 AT>MFlashA512
+    /* MAIN DATA SECTION */
+    .uninit_RESERVED : ALIGN(4)
+    {
+        KEEP(*(.bss.$RESERVED*))
+        . = ALIGN(4) ;
+        _end_uninit_RESERVED = .;
+    } > RamLoc32
+
+    /* Main DATA section (RamLoc32) */
+    .data : ALIGN(4)
+    {
+       FILL(0xff)
+       _data = . ;
+       *(vtable)
+       *(.ramfunc*)
+       *(.data*)
+       . = ALIGN(4) ;
+       _edata = . ;
+    } > RamLoc32 AT>MFlashA512
+
+    /* BSS section for RamLoc40 */
+    .bss_RAM2 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM2 = .) ;
+       *(.bss.$RAM2*)
+       *(.bss.$RamLoc40*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM2 = .) ;
+    } > RamLoc40
+
+    /* BSS section for RamAHB32 */
+    .bss_RAM3 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM3 = .) ;
+       *(.bss.$RAM3*)
+       *(.bss.$RamAHB32*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM3 = .) ;
+    } > RamAHB32
+
+    /* BSS section for RamAHB16 */
+    .bss_RAM4 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM4 = .) ;
+       *(.bss.$RAM4*)
+       *(.bss.$RamAHB16*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM4 = .) ;
+    } > RamAHB16
+
+    /* BSS section for RamAHB_ETB16 */
+    .bss_RAM5 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM5 = .) ;
+       *(.bss.$RAM5*)
+       *(.bss.$RamAHB_ETB16*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM5 = .) ;
+    } > RamAHB_ETB16
+
+    /* MAIN BSS SECTION */
+    .bss : ALIGN(4)
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(end = .);
+    } > RamLoc32
+
+    /* NOINIT section for RamLoc40 */
+    .noinit_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       *(.noinit.$RAM2*)
+       *(.noinit.$RamLoc40*)
+       . = ALIGN(4) ;
+    } > RamLoc40
+
+    /* NOINIT section for RamAHB32 */
+    .noinit_RAM3 (NOLOAD) : ALIGN(4)
+    {
+       *(.noinit.$RAM3*)
+       *(.noinit.$RamAHB32*)
+       . = ALIGN(4) ;
+    } > RamAHB32
+
+    /* NOINIT section for RamAHB16 */
+    .noinit_RAM4 (NOLOAD) : ALIGN(4)
+    {
+       *(.noinit.$RAM4*)
+       *(.noinit.$RamAHB16*)
+       . = ALIGN(4) ;
+    } > RamAHB16
+
+    /* NOINIT section for RamAHB_ETB16 */
+    .noinit_RAM5 (NOLOAD) : ALIGN(4)
+    {
+       *(.noinit.$RAM5*)
+       *(.noinit.$RamAHB_ETB16*)
+       . = ALIGN(4) ;
+    } > RamAHB_ETB16
+
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        *(.noinit*)
+         . = ALIGN(4) ;
+        _end_noinit = .;
+    } > RamLoc32
+    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+    /* ## Create checksum value (used in startup) ## */
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
+                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
+                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
+                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+                                         ) );
+
+    /* Provide basic symbols giving location and size of main text
+     * block, including initial values of RW data sections. Note that
+     * these will need extending to give a complete picture with
+     * complex images (e.g multiple Flash banks).
+     */
+    _image_start = LOADADDR(.text);
+    _image_end = LOADADDR(.data) + SIZEOF(.data);
+    _image_size = _image_end - _image_start;
+}
diff --git a/hw/bsp/lpc43/boards/ea4357/pca9532.c b/hw/bsp/lpc43/boards/ea4357/pca9532.c
new file mode 100644
index 000000000..150167cde
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/pca9532.c
@@ -0,0 +1,352 @@
+/*****************************************************************************
+ *
+ *   Copyright(C) 2011, Embedded Artists AB
+ *   All rights reserved.
+ *
+ ******************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * Embedded Artists AB assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. Embedded Artists AB
+ * reserves the right to make changes in the software without
+ * notification. Embedded Artists AB also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ *****************************************************************************/
+
+/*
+ * NOTE: I2C must have been initialized before calling any functions in this
+ * file.
+ */
+
+/******************************************************************************
+ * Includes
+ *****************************************************************************/
+
+//#include "board.h"
+#include "chip.h"
+
+#include "pca9532.h"
+
+/******************************************************************************
+ * Defines and typedefs
+ *****************************************************************************/
+
+#define I2C_PORT (LPC_I2C0)
+
+#define LS_MODE_ON     0x01
+#define LS_MODE_BLINK0 0x02
+#define LS_MODE_BLINK1 0x03
+
+/******************************************************************************
+ * External global variables
+ *****************************************************************************/
+
+
+/******************************************************************************
+ * Local variables
+ *****************************************************************************/
+
+static uint16_t blink0Shadow = 0;
+static uint16_t blink1Shadow = 0;
+static uint16_t ledStateShadow = 0;
+
+/******************************************************************************
+ * Local Functions
+ *****************************************************************************/
+
+static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
+{
+	I2CM_XFER_T i2cData;
+
+	i2cData.slaveAddr = addr;
+	i2cData.options = 0;
+	i2cData.status = 0;
+	i2cData.txBuff = buf;
+	i2cData.txSz = len;
+	i2cData.rxBuff = NULL;
+	i2cData.rxSz = 0;
+
+	if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
+		return ERROR;
+	}
+	return SUCCESS;
+}
+
+static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
+{
+	I2CM_XFER_T i2cData;
+
+	i2cData.slaveAddr = addr;
+	i2cData.options = 0;
+	i2cData.status = 0;
+	i2cData.txBuff = NULL;
+	i2cData.txSz = 0;
+	i2cData.rxBuff = buf;
+	i2cData.rxSz = len;
+
+	if (Chip_I2CM_XferBlocking(LPC_I2C0, &i2cData) == 0) {
+		return ERROR;
+	}
+	return SUCCESS;
+}
+
+static void setLsStates(uint16_t states, uint8_t* ls, uint8_t mode)
+{
+#define IS_LED_SET(bit, x) ( ( ((x) & (bit)) != 0 ) ? 1 : 0 )
+
+    int i = 0;
+
+    for (i = 0; i < 4; i++) {
+
+        ls[i] |= ( (IS_LED_SET(0x0001, states)*mode << 0)
+                | (IS_LED_SET(0x0002, states)*mode << 2)
+                | (IS_LED_SET(0x0004, states)*mode << 4)
+                | (IS_LED_SET(0x0008, states)*mode << 6) );
+
+        states >>= 4;
+    }
+}
+
+static void setLeds(void)
+{
+    uint8_t buf[5];
+    uint8_t ls[4] = {0,0,0,0};
+    uint16_t states = ledStateShadow;
+
+    /* LEDs in On/Off state */
+    setLsStates(states, ls, LS_MODE_ON);
+
+    /* set the LEDs that should blink */
+    setLsStates(blink0Shadow, ls, LS_MODE_BLINK0);
+    setLsStates(blink1Shadow, ls, LS_MODE_BLINK1);
+
+
+    buf[0] = PCA9532_LS0 | PCA9532_AUTO_INC;
+    buf[1] = ls[0];
+    buf[2] = ls[1];
+    buf[3] = ls[2];
+    buf[4] = ls[3];
+    I2CWrite(PCA9532_I2C_ADDR, buf, 5);
+}
+
+/******************************************************************************
+ * Public Functions
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * Description:
+ *    Initialize the PCA9532 Device
+ *
+ *****************************************************************************/
+void pca9532_init (void)
+{
+    /* nothing to initialize */
+}
+
+/******************************************************************************
+ *
+ * Description:
+ *    Get the LED states
+ *
+ * Params:
+ *    [in]  shadow  - TRUE if the states should be retrieved from the shadow
+ *                    variables. The shadow variable are updated when any
+ *                    of setLeds, setBlink0Leds and/or setBlink1Leds are
+ *                    called.
+ *
+ *                    FALSE if the state should be retrieved from the PCA9532
+ *                    device. A blinkin LED may be reported as on or off
+ *                    depending on the state when calling the function.
+ *
+ * Returns:
+ *      A mask where a 1 indicates that a LED is on (or blinking).
+ *
+ *****************************************************************************/
+uint16_t pca9532_getLedState (uint32_t shadow)
+{
+    uint8_t buf[2];
+    uint16_t ret = 0;
+
+    if (shadow) {
+        /* a blink LED is reported as on*/
+        ret = (ledStateShadow | blink0Shadow | blink1Shadow);
+    }
+    else {
+
+        /*
+         * A blinking LED may be reported as on or off depending on
+         * its state when reading the Input register.
+         */
+
+        buf[0] = PCA9532_INPUT0;
+        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
+
+        I2CRead(PCA9532_I2C_ADDR, buf, 1);
+        ret = buf[0];
+
+
+        buf[0] = PCA9532_INPUT1;
+        I2CWrite(PCA9532_I2C_ADDR, buf, 1);
+
+        I2CRead(PCA9532_I2C_ADDR, buf, 1);
+        ret |= (buf[0] << 8);
+
+
+        /* invert since LEDs are active low */
+        ret = ((~ret) & 0xFFFF);
+    }
+
+    return (ret & ~PCA9532_NOT_USED);
+}
+
+
+/******************************************************************************
+ *
+ * Description:
+ *    Set LED states (on or off).
+ *
+ * Params:
+ *    [in]  ledOnMask  - The LEDs that should be turned on. This mask has
+ *                       priority over ledOffMask
+ *    [in]  ledOffMask - The LEDs that should be turned off.
+ *
+ *****************************************************************************/
+void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask)
+{
+    /* turn off leds */
+    ledStateShadow &= (~(ledOffMask) & 0xffff);
+
+    /* ledOnMask has priority over ledOffMask */
+    ledStateShadow |= ledOnMask;
+
+    /* turn off blinking */
+    blink0Shadow &= (~(ledOffMask) & 0xffff);
+    blink1Shadow &= (~(ledOffMask) & 0xffff);
+
+    setLeds();
+}
+
+/******************************************************************************
+ *
+ * Description:
+ *    Set the blink period for PWM0. Valid values are 0 - 255 where 0
+ *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
+ *
+ * Params:
+ *    [in]  period  - the period for pwm0
+ *
+ *****************************************************************************/
+void pca9532_setBlink0Period(uint8_t period)
+{
+    uint8_t buf[2];
+
+    buf[0] = PCA9532_PSC0;
+    buf[1] = period;
+    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
+}
+
+/******************************************************************************
+ *
+ * Description:
+ *    Set the duty cycle for PWM0. Valid values are 0 - 100. 25 means the LED
+ *    is on 25% of the period.
+ *
+ * Params:
+ *    [in]  duty  - duty cycle
+ *
+ *****************************************************************************/
+void pca9532_setBlink0Duty(uint8_t duty)
+{
+    uint8_t buf[2];
+    uint32_t tmp = duty;
+    if (tmp > 100) {
+        tmp = 100;
+    }
+
+    tmp = (256 * tmp)/100;
+
+    buf[0] = PCA9532_PWM0;
+    buf[1] = tmp;
+    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
+}
+
+/******************************************************************************
+ *
+ * Description:
+ *    Set the LEDs that should blink with rate and duty cycle from PWM0.
+ *    Blinking is turned off with pca9532_setLeds.
+ *
+ * Params:
+ *    [in]  ledMask  - LEDs that should blink.
+ *
+ *****************************************************************************/
+void pca9532_setBlink0Leds(uint16_t ledMask)
+{
+    blink0Shadow |= ledMask;
+    setLeds();
+}
+
+/******************************************************************************
+ *
+ * Description:
+ *    Set the blink period for PWM1. Valid values are 0 - 255 where 0
+ *    means 152 Hz and 255 means 0.59 Hz. A value of 151 means 1 Hz.
+ *
+ * Params:
+ *    [in]  period  - The period for PWM1
+ *
+ *****************************************************************************/
+void pca9532_setBlink1Period(uint8_t period)
+{
+    uint8_t buf[2];
+
+    buf[0] = PCA9532_PSC1;
+    buf[1] = period;
+    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
+}
+
+/******************************************************************************
+ *
+ * Description:
+ *    Set the duty cycle for PWM1. Valid values are 0 - 100. 25 means the LED
+ *    is on 25% of the period.
+ *
+ * Params:
+ *    [in]  duty  - duty cycle.
+ *
+ *****************************************************************************/
+void pca9532_setBlink1Duty(uint8_t duty)
+{
+    uint8_t buf[2];
+
+    uint32_t tmp = duty;
+    if (tmp > 100) {
+        tmp = 100;
+    }
+
+    tmp = (256 * tmp)/100;
+
+    buf[0] = PCA9532_PWM1;
+    buf[1] = tmp;
+    I2CWrite(PCA9532_I2C_ADDR, buf, 2);
+}
+
+/******************************************************************************
+ *
+ * Description:
+ *    Set the LEDs that should blink with rate and duty cycle from PWM1.
+ *    Blinking is turned off with pca9532_setLeds.
+ *
+ * Params:
+ *    [in]  ledMask  - LEDs that should blink.
+ *
+ *****************************************************************************/
+void pca9532_setBlink1Leds(uint16_t ledMask)
+{
+    blink1Shadow |= ledMask;
+    setLeds();
+}
diff --git a/hw/bsp/lpc43/boards/ea4357/pca9532.h b/hw/bsp/lpc43/boards/ea4357/pca9532.h
new file mode 100644
index 000000000..f21c1ff09
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/pca9532.h
@@ -0,0 +1,94 @@
+/*****************************************************************************
+ *
+ *   Copyright(C) 2011, Embedded Artists AB
+ *   All rights reserved.
+ *
+ ******************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * Embedded Artists AB assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. Embedded Artists AB
+ * reserves the right to make changes in the software without
+ * notification. Embedded Artists AB also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ *****************************************************************************/
+#ifndef __PCA9532C_H
+#define __PCA9532C_H
+
+
+#define PCA9532_I2C_ADDR    (0xC0>>1)
+
+#define PCA9532_INPUT0 0x00
+#define PCA9532_INPUT1 0x01
+#define PCA9532_PSC0   0x02
+#define PCA9532_PWM0   0x03
+#define PCA9532_PSC1   0x04
+#define PCA9532_PWM1   0x05
+#define PCA9532_LS0    0x06
+#define PCA9532_LS1    0x07
+#define PCA9532_LS2    0x08
+#define PCA9532_LS3    0x09
+
+#define PCA9532_AUTO_INC 0x10
+
+
+/*
+ * The Keys on the base board are mapped to LED0 -> LED3 on
+ * the PCA9532.
+ */
+
+#define KEY1 0x0001
+#define KEY2 0x0002
+#define KEY3 0x0004
+#define KEY4 0x0008
+
+#define KEY_MASK 0x000F
+
+/*
+ * MMC Card Detect and MMC Write Protect are mapped to LED4
+ * and LED5 on the PCA9532. Please note that WP is active low.
+ */
+
+#define MMC_CD 0x0010
+#define MMC_WP 0x0020
+
+#define MMC_MASK  0x30
+
+/* NOTE: LED6 and LED7 on PCA9532 are not connected to anything */
+#define PCA9532_NOT_USED 0xC0
+
+/*
+ * Below are the LED constants to use when enabling/disabling a LED.
+ * The LED names are the names printed on the base board and not
+ * the names from the PCA9532 device. base_LED1 -> LED8 on PCA9532,
+ * base_LED2 -> LED9, and so on.
+ */
+
+#define LED1 0x0100
+#define LED2 0x0200
+#define LED3 0x0400
+#define LED4 0x0800
+#define LED5 0x1000
+#define LED6 0x2000
+#define LED7 0x4000
+#define LED8 0x8000
+
+#define LED_MASK 0xFF00
+
+void pca9532_init (void);
+uint16_t pca9532_getLedState (uint32_t shadow);
+void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask);
+void pca9532_setBlink0Period(uint8_t period);
+void pca9532_setBlink0Duty(uint8_t duty);
+void pca9532_setBlink0Leds(uint16_t ledMask);
+void pca9532_setBlink1Period(uint8_t period);
+void pca9532_setBlink1Duty(uint8_t duty);
+void pca9532_setBlink1Leds(uint16_t ledMask);
+
+#endif /* end __PCA9532C_H */
+/****************************************************************************
+**                            End Of File
+*****************************************************************************/
diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
new file mode 100644
index 000000000..ba3191d5f
--- /dev/null
+++ b/hw/bsp/lpc43/family.c
@@ -0,0 +1,312 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include "chip.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+#define UART_DEV        LPC_USART0
+#define UART_PORT       0x0f
+#define UART_PIN_TX     10
+#define UART_PIN_RX     11
+
+// P9_1 joystick down
+#define BUTTON_PORT     4
+#define BUTTON_PIN      13
+
+//static const struct {
+//  uint8_t mux_port;
+//  uint8_t mux_pin;
+//
+//  uint8_t gpio_port;
+//  uint8_t gpio_pin;
+//}buttons[] =
+//{
+//    {0x0a, 3, 4, 10 }, // Joystick up
+//    {0x09, 1, 4, 13 }, // Joystick down
+//    {0x0a, 2, 4, 9  }, // Joystick left
+//    {0x09, 0, 4, 12 }, // Joystick right
+//    {0x0a, 1, 4, 8  }, // Joystick press
+//    {0x02, 7, 0, 7  }, // SW6
+//};
+
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
+/*------------------------------------------------------------------*/
+/* BOARD API
+ *------------------------------------------------------------------*/
+
+/* System configuration variables used by chip driver */
+const uint32_t OscRateIn = 12000000;
+const uint32_t ExtRateIn = 0;
+
+static const PINMUX_GRP_T pinmuxing[] =
+{
+  // Button ( Joystick down )
+  {0x9, 1,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)},
+
+  // UART
+  {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1},
+  {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1},
+
+  // USB
+};
+
+/* Pin clock mux values, re-used structure, value in first index is meaningless */
+static const PINMUX_GRP_T pinclockmuxing[] =
+{
+  {0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+  {0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+  {0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+  {0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
+};
+
+// Invoked by startup code
+void SystemInit(void)
+{
+#ifdef __USE_LPCOPEN
+	extern void (* const g_pfnVectors[])(void);
+  unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
+	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+
+#if __FPU_USED == 1
+	fpuInit();
+#endif
+#endif // __USE_LPCOPEN
+
+	/* Setup system level pin muxing */
+	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+
+	/* Clock pins only, group field not used */
+	for (int i = 0; i <(int)  (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
+	{
+		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
+	}
+
+  Chip_SetupXtalClocking();
+}
+
+void board_init(void)
+{
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  Chip_GPIO_Init(LPC_GPIO_PORT);
+
+  // LED via pca9532 I2C
+  Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
+  Chip_I2C_Init(I2C0);
+  Chip_I2C_SetClockRate(I2C0, 100000);
+  Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
+
+  pca9532_init();
+
+  // Button
+  Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
+
+  //------------- UART -------------//
+	Chip_UART_Init(UART_DEV);
+	Chip_UART_SetBaud(UART_DEV, CFG_BOARD_UART_BAUDRATE);
+	Chip_UART_ConfigData(UART_DEV, UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS);
+	Chip_UART_TXEnable(UART_DEV);
+
+  //------------- USB -------------//
+  enum {
+    USBMODE_DEVICE = 2,
+    USBMODE_HOST   = 3
+  };
+
+  enum {
+    USBMODE_VBUS_LOW  = 0,
+    USBMODE_VBUS_HIGH = 1
+  };
+
+  /* From EA4357 user manual
+   *
+   * USB0 Device operation:
+   * - Insert jumpers in position 1-2 in JP17/JP18/JP19.
+   * - GPIO28 controls USB connect functionality
+   * - LED32 lights when the USB Device is connected. SJ4 has pads 1-2 shorted by default.
+   * - LED33 is controlled by GPIO27 and signals USB-up state. GPIO54 is used for VBUS
+   * sensing.
+   *
+   * USB0 Host operation:
+   * - insert jumpers in position 2-3 in JP17/JP18/JP19.
+   * - USB Host power is controlled via distribution switch U20 (found in schematic page 11).
+   * - Signal GPIO26 is active low and enables +5V on VBUS2.
+   * - LED35 light whenever +5V is present on VBUS2.
+   * - GPIO55 is connected to status feedback from the distribution switch.
+   * - GPIO54 is used for VBUS sensing. 15Kohm pull-down resistors are always active
+   *
+   * Note:
+   * - Insert jumpers in position 2-3 in JP17/JP18/JP19
+   * - Insert jumpers in JP31 (OTG)
+   */
+#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0)
+  Chip_USB0_Init();
+#endif
+
+  /* From EA4357 user manual
+   *
+   * For USB1 Device:
+   * - a 1.5Kohm pull-up resistor is needed on the USB DP data signal. There are two methods to create this.
+   * JP15 is inserted and the pull-up resistor is always enabled. Alternatively, the pull-up resistor is activated
+   * inside the USB OTG chip (U31), and this has to be done via the I2C interface of GPIO52/GPIO53. In the latter case,
+   * JP15 shall not be inserted.
+   * - J19 is the connector to use when USB Device is used. Normally it should be a USB-B connector for
+   * creating a USB Device interface, but the mini-AB connector can also be used in this case. The status
+   * of VBUS can be read via U31.
+   * - JP16 shall not be inserted.
+   *
+   * For USB1 Host:
+   * - 15Kohm pull-down resistors are needed on the USB data signals. These are activated inside the USB OTG chip (U31),
+   * and this has to be done via the I2C interface of GPIO52/GPIO53.
+   * - J20 is the connector to use when USB Host is used. In order to provide +5V to the external USB
+   * device connected to this connector (J20), channel A of U20 must be enabled. It is enabled by default
+   * since SJ5 is normally connected between pin 1-2.
+   * - LED34 lights green when +5V is available on J20.
+   * - JP15 shall not be inserted. JP16 has no effect
+   */
+#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1)
+  Chip_USB1_Init();
+#endif
+
+  // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
+  Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
+
+  #if PORT_SUPPORT_DEVICE(0)
+  // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
+  Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
+  #endif
+
+  // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required
+  // TODO Remove R170, R171, solder a pair of 15K to USB1 D+/D- to test with USB1 Host
+}
+
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  #if PORT_SUPPORT_DEVICE(0)
+    tud_int_handler(0);
+  #endif
+
+  #if PORT_SUPPORT_HOST(0)
+    tuh_int_handler(0);
+  #endif
+}
+
+void USB1_IRQHandler(void)
+{
+  #if PORT_SUPPORT_DEVICE(1)
+    tud_int_handler(1);
+  #endif
+
+  #if PORT_SUPPORT_HOST(1)
+    tuh_int_handler(1);
+  #endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  if (state)
+  {
+    pca9532_setLeds( LED1, 0 );
+  }else
+  {
+    pca9532_setLeds( 0, LED1);
+  }
+}
+
+uint32_t board_button_read(void)
+{
+  // active low
+  return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  return Chip_UART_Read(UART_DEV, buf, len);
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  uint8_t const* buf8 = (uint8_t const*) buf;
+  for(int i=0; i<len; i++)
+  {
+    while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
+    Chip_UART_SendByte(UART_DEV, buf8[i]);
+  }
+
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake
new file mode 100644
index 000000000..9fd78c9c2
--- /dev/null
+++ b/hw/bsp/lpc43/family.cmake
@@ -0,0 +1,97 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC43XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${SDK_DIR}/../gcc/cr_startup_lpc43xx.c
+      ${SDK_DIR}/src/chip_18xx_43xx.c
+      ${SDK_DIR}/src/clock_18xx_43xx.c
+      ${SDK_DIR}/src/fpu_init.c
+      ${SDK_DIR}/src/gpio_18xx_43xx.c
+      ${SDK_DIR}/src/sysinit_18xx_43xx.c
+      ${SDK_DIR}/src/uart_18xx_43xx.c
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -nostdlib
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      __USE_LPCOPEN
+      CORE_M4
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}/inc
+      ${SDK_DIR}/inc/config_43xx
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk
new file mode 100644
index 000000000..4a1c2fb3c
--- /dev/null
+++ b/hw/bsp/lpc43/family.mk
@@ -0,0 +1,34 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+SDK_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
+
+include ${TOP}/${BOARD_PATH}/board.mk
+CPU_CORE ?= cortex-m4
+
+CFLAGS += \
+  -flto \
+  -nostdlib \
+  -DCORE_M4 \
+  -D__USE_LPCOPEN \
+  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
+
+SRC_C += \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
+	${SDK_DIR}/../gcc/cr_startup_lpc43xx.c \
+	${SDK_DIR}/src/chip_18xx_43xx.c \
+	${SDK_DIR}/src/clock_18xx_43xx.c \
+	${SDK_DIR}/src/gpio_18xx_43xx.c \
+	${SDK_DIR}/src/sysinit_18xx_43xx.c \
+	${SDK_DIR}/src/i2c_18xx_43xx.c \
+	${SDK_DIR}/src/i2cm_18xx_43xx.c \
+	${SDK_DIR}/src/uart_18xx_43xx.c \
+	${SDK_DIR}/src/fpu_init.c
+
+INC += \
+  $(TOP)/$(BOARD_PATH) \
+	${TOP}/${SDK_DIR}/inc \
+	${TOP}/${SDK_DIR}/inc/config_43xx
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index 2e84c93e7..178eec419 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -27,9 +27,18 @@
 #ifndef _CI_HS_LPC18_43_H_
 #define _CI_HS_LPC18_43_H_
 
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 // LPCOpen for 18xx & 43xx
 #include "chip.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 static const ci_hs_controller_t _ci_controller[] =
 {
   { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
-- 
cgit v1.3.1


From 56e52037a8c2fe383a61587baece0ce1add33afb Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Tue, 18 Jul 2023 14:23:41 +0200
Subject: clean(ra_hcd): fix typos in the hcd library

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 55bf6de4d..790cd6b32 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -265,7 +265,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BCLR_Msk;
   }
   rusb->D0FIFOSEL = 0;
   while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
@@ -297,7 +297,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk;
   }
   rusb->D0FIFOSEL = 0;
   while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
@@ -367,7 +367,7 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr,
     } else { /* ZLP */
       rusb->D0FIFOSEL = num;
       pipe_wait_for_ready(rusb, num);
-      rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk;
       rusb->D0FIFOSEL = 0;
       while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
     }
-- 
cgit v1.3.1


From 1f95a417f271e627ec981be3d211eed8c37cb052 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Aug 2023 18:22:28 +0700
Subject: Add tuh_rhport_is_active() and tuh_rhport_reset_bus()

- also improve ehci bus reset
- seperate bus reset delay and contact debouncing delay in enumeration
---
 src/host/hcd.h                          |   5 +-
 src/host/hub.c                          |   2 +-
 src/host/usbh.c                         | 118 +++++++++++++++++---------------
 src/host/usbh.h                         |  39 ++++++-----
 src/portable/chipidea/ci_hs/hcd_ci_hs.c |  43 ++++++------
 src/portable/ehci/ehci.c                |  24 +++++--
 6 files changed, 128 insertions(+), 103 deletions(-)

(limited to 'src')

diff --git a/src/host/hcd.h b/src/host/hcd.h
index d77dd6e2f..9bcc1c6df 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -149,10 +149,11 @@ uint32_t hcd_frame_number(uint8_t rhport);
 // Get the current connect status of roothub port
 bool hcd_port_connect_status(uint8_t rhport);
 
-// Reset USB bus on the port
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport);
 
-// TODO implement later
+// Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport);
 
 // Get port link speed
diff --git a/src/host/hub.c b/src/host/hub.c
index 16dd534d2..ec30eb96a 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -330,7 +330,7 @@ static void connection_port_reset_complete (tuh_xfer_t* xfer);
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
   (void) ep_addr;
-  TU_ASSERT(result == XFER_RESULT_SUCCESS);
+  TU_VERIFY(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 49f8c78f1..cc7e38b45 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -181,9 +181,6 @@ static usbh_class_driver_t const usbh_class_drivers[] =
 };
 
 enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
-
-enum { RESET_DELAY = 500 };  // 200 USB specs say only 50ms but many devices require much longer
-
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 
@@ -251,40 +248,27 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
-{
+// weak and overridable
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec) {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
 }
 #endif
 
 //--------------------------------------------------------------------+
-// PUBLIC API (Parameter Verification is required)
+// Device API
 //--------------------------------------------------------------------+
 
-bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
-{
-  if (hcd_configure)
-  {
-    return hcd_configure(rhport, cfg_id, cfg_param);
-  }else
-  {
-    return false;
-  }
-}
-
-bool tuh_mounted(uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+bool tuh_mounted(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   TU_VERIFY(dev);
   return dev->configured;
 }
 
-bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
-{
+bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) {
   *vid = *pid = 0;
 
-  usbh_device_t const* dev = get_device(dev_addr);
+  usbh_device_t const *dev = get_device(dev_addr);
   TU_VERIFY(dev && dev->addressed && dev->vid != 0);
 
   *vid = dev->vid;
@@ -293,26 +277,48 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   return true;
 }
 
-tusb_speed_t tuh_speed_get (uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+tusb_speed_t tuh_speed_get(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   return (tusb_speed_t) (dev ? get_device(dev_addr)->speed : _dev0.speed);
 }
 
-static void clear_device(usbh_device_t* dev)
-{
+bool tuh_rhport_is_active(uint8_t rhport) {
+  return _usbh_controller == rhport;
+}
+
+bool tuh_rhport_reset_bus(uint8_t rhport, bool active) {
+  TU_VERIFY(tuh_rhport_is_active(rhport));
+  if ( active ) {
+    hcd_port_reset(rhport);
+  } else {
+    hcd_port_reset_end(rhport);
+  }
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// PUBLIC API (Parameter Verification is required)
+//--------------------------------------------------------------------+
+
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
+  if ( hcd_configure ) {
+    return hcd_configure(rhport, cfg_id, cfg_param);
+  } else {
+    return false;
+  }
+}
+
+static void clear_device(usbh_device_t* dev) {
   tu_memclr(dev, sizeof(usbh_device_t));
   memset(dev->itf2drv, TUSB_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping
   memset(dev->ep2drv , TUSB_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping
 }
 
-bool tuh_inited(void)
-{
+bool tuh_inited(void) {
   return _usbh_controller != TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_init(uint8_t controller_id)
-{
+bool tuh_init(uint8_t controller_id) {
   // skip if already initialized
   if ( tuh_inited() ) return true;
 
@@ -359,8 +365,7 @@ bool tuh_init(uint8_t controller_id)
   return true;
 }
 
-bool tuh_task_event_ready(void)
-{
+bool tuh_task_event_ready(void) {
   // Skip if stack is not initialized
   if ( !tuh_inited() ) return false;
 
@@ -385,8 +390,7 @@ bool tuh_task_event_ready(void)
     }
     @endcode
  */
-void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
-{
+void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
@@ -403,8 +407,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
       case HCD_EVENT_DEVICE_ATTACH:
         // due to the shared _usbh_ctrl_buf, we must complete enumerating
         // one device before enumerating another one.
-        if ( _dev0.enumerating )
-        {
+        if ( _dev0.enumerating ) {
           TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
 
           bool is_empty = osal_queue_empty(_usbh_q);
@@ -414,8 +417,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
             // Exit if this is the only event in the queue, otherwise we may loop forever
             return;
           }
-        }else
-        {
+        }else {
           TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
           _dev0.enumerating = 1;
           enum_new_device(&event);
@@ -428,8 +430,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
 
         #if CFG_TUH_HUB
         // TODO remove
-        if ( event.connection.hub_addr != 0)
-        {
+        if ( event.connection.hub_addr != 0) {
           // done with hub, waiting for next data on status pipe
           (void) hub_edpt_status_xfer( event.connection.hub_addr );
         }
@@ -1230,6 +1231,12 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
 // one device before enumerating another one.
 //--------------------------------------------------------------------+
 
+enum {
+  ENUM_RESET_DELAY = 50, // USB specs: 10 to 50ms
+  ENUM_CONTACT_DEBOUNCING_DELAY = 450, // when plug/unplug a device, physical connection can be bouncing and may
+                                       // generate a series of attach/detach event. This delay wait for stable connection
+};
+
 enum {
   ENUM_IDLE,
   ENUM_RESET_1,         // 1st reset when attached
@@ -1311,7 +1318,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
     break;
 
     case ENUM_HUB_GET_STATUS_2:
-      osal_task_delay(RESET_DELAY);
+      osal_task_delay(ENUM_RESET_DELAY);
       TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2), );
     break;
 
@@ -1468,12 +1475,14 @@ static bool enum_new_device(hcd_event_t* event)
   if (_dev0.hub_addr == 0)
   {
     // connected/disconnected directly with roothub
-    // wait until device is stable TODO non blocking
     hcd_port_reset(_dev0.rhport);
-    osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                  // sof of controller may not running while resetting
+    osal_task_delay(ENUM_RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
+                                        // sof of controller may not running while resetting
     hcd_port_reset_end( _dev0.rhport);
 
+    // wait until device connection is stable TODO non blocking
+    osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY);
+
     // device unplugged while delaying
     if ( !hcd_port_connect_status(_dev0.rhport) ) {
       enum_full_complete();
@@ -1489,6 +1498,7 @@ static bool enum_new_device(hcd_event_t* event)
     xfer.result    = XFER_RESULT_SUCCESS;
     xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
+
     process_enumeration(&xfer);
 
   }
@@ -1496,8 +1506,8 @@ static bool enum_new_device(hcd_event_t* event)
   else
   {
     // connected/disconnected via external hub
-    // wait until device is stable
-    osal_task_delay(RESET_DELAY);
+    // wait until device connection is stable TODO non blocking
+    osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY);
 
     // ENUM_HUB_GET_STATUS
     //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) );
@@ -1508,23 +1518,19 @@ static bool enum_new_device(hcd_event_t* event)
   return true;
 }
 
-static uint8_t get_new_address(bool is_hub)
-{
+static uint8_t get_new_address(bool is_hub) {
   uint8_t start;
   uint8_t end;
 
-  if ( is_hub )
-  {
+  if ( is_hub ) {
     start = CFG_TUH_DEVICE_MAX;
     end   = start + CFG_TUH_HUB;
-  }else
-  {
+  }else {
     start = 0;
     end   = start + CFG_TUH_DEVICE_MAX;
   }
 
-  for (uint8_t idx = start; idx < end; idx++)
-  {
+  for (uint8_t idx = start; idx < end; idx++) {
     if (!_usbh_devices[idx].connected) return (idx+1);
   }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 0d56f40c9..684e8240e 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -47,8 +47,7 @@ typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer);
 // it is advised to initialize it using member name
 // Note2: not all field is available/meaningful in callback,
 // some info is not saved by usbh to save SRAM
-struct tuh_xfer_s
-{
+struct tuh_xfer_s {
   uint8_t daddr;
   uint8_t ep_addr;
   uint8_t TU_RESERVED;      // reserved
@@ -56,8 +55,7 @@ struct tuh_xfer_s
 
   uint32_t actual_len;      // excluding setup packet
 
-  union
-  {
+  union {
     tusb_control_request_t const* setup; // setup packet pointer if control transfer
     uint32_t buflen;                     // expected length if not control transfer (not available in callback)
   };
@@ -70,15 +68,13 @@ struct tuh_xfer_s
 };
 
 // Subject to change
-typedef struct
-{
+typedef struct {
   uint8_t daddr;
   tusb_desc_interface_t desc;
 } tuh_itf_info_t;
 
 // ConfigID for tuh_config()
-enum
-{
+enum {
   TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 << 8 // cfg_param: pio_usb_configuration_t
 };
 
@@ -105,12 +101,12 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 // Should be called before tuh_init()
 // - cfg_id   : configure ID (TBD)
 // - cfg_param: configure data, structure depends on the ID
-bool tuh_configure(uint8_t controller_id, uint32_t cfg_id, const void* cfg_param);
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
 
 // Init host stack
-bool tuh_init(uint8_t controller_id);
+bool tuh_init(uint8_t rhport);
 
-// Check if host stack is already initialized
+// Check if host stack is already initialized with any roothub ports
 bool tuh_inited(void);
 
 // Task function should be called in main/rtos loop, extended version of tuh_task()
@@ -120,8 +116,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr);
 
 // Task function should be called in main/rtos loop
 TU_ATTR_ALWAYS_INLINE static inline
-void tuh_task(void)
-{
+void tuh_task(void) {
   tuh_task_ext(UINT32_MAX, false);
 }
 
@@ -135,8 +130,20 @@ extern void hcd_int_handler(uint8_t rhport);
 // Interrupt handler, name alias to HCD
 #define tuh_int_handler   hcd_int_handler
 
+// Check if roothub port is initialized and active as a host
+bool tuh_rhport_is_active(uint8_t rhport);
+
+// Assert/de-assert Bus Reset signal to roothub port. USB specs: it should last 10-50ms
+bool tuh_rhport_reset_bus(uint8_t rhport, bool active);
+
+//--------------------------------------------------------------------+
+// Device API
+//--------------------------------------------------------------------+
+
+// Get VID/PID of device
 bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);
 
+// Get speed of device
 tusb_speed_t tuh_speed_get(uint8_t daddr);
 
 // Check if device is connected and configured
@@ -144,8 +151,7 @@ bool tuh_mounted(uint8_t daddr);
 
 // Check if device is suspended
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_suspended(uint8_t daddr)
-{
+bool tuh_suspended(uint8_t daddr) {
   // TODO implement suspend & resume on host
   (void) daddr;
   return false;
@@ -153,8 +159,7 @@ bool tuh_suspended(uint8_t daddr)
 
 // Check if device is ready to communicate with
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_ready(uint8_t daddr)
-{
+bool tuh_ready(uint8_t daddr) {
   return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }
 
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 6ee91e18e..462cbd301 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -39,24 +39,27 @@
 #include "ci_hs_type.h"
 
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
-  #include "ci_hs_imxrt.h"
 
-  bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
-    return imxrt_dcache_clean(addr, data_size);
-  }
+#include "ci_hs_imxrt.h"
 
-  bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
-    return imxrt_dcache_invalidate(addr, data_size);
-  }
+bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean(addr, data_size);
+}
+
+bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_invalidate(addr, data_size);
+}
 
-  bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
-    return imxrt_dcache_clean_invalidate(addr, data_size);
-  }
+bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean_invalidate(addr, data_size);
+}
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
-  #include "ci_hs_lpc18_43.h"
+
+#include "ci_hs_lpc18_43.h"
+
 #else
-  #error "Unsupported MCUs"
+#error "Unsupported MCUs"
 #endif
 
 //--------------------------------------------------------------------+
@@ -67,25 +70,25 @@
 // Controller API
 //--------------------------------------------------------------------+
 
-bool hcd_init(uint8_t rhport)
-{
-  ci_hs_regs_t* hcd_reg = CI_HS_REG(rhport);
+bool hcd_init(uint8_t rhport) {
+  ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport);
 
   // Reset controller
   hcd_reg->USBCMD |= USBCMD_RESET;
-  while( hcd_reg->USBCMD & USBCMD_RESET ) {}
+  while ( hcd_reg->USBCMD & USBCMD_RESET ) {}
 
   // Set mode to device, must be set immediately after reset
 #if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
   // LPC18XX/43XX need to set VBUS Power Select to HIGH
   // RHPORT1 is fullspeed only (need external PHY for Highspeed)
   hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
-  if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+  if ( rhport == 1 ) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
 #else
   hcd_reg->USBMODE = USBMODE_CM_HOST;
 #endif
 
   // FIXME force full speed, still have issue with Highspeed enumeration
+  // probably due to physical connection bouncing when plug/unplug
   // 1. Have issue when plug/unplug devices, maybe the port is not reset properly
   // 2. Also does not seems to detect disconnection
   hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
@@ -93,13 +96,11 @@ bool hcd_init(uint8_t rhport)
   return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   CI_HCD_INT_ENABLE(rhport);
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   CI_HCD_INT_DISABLE(rhport);
 }
 
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 9be24c888..79811985c 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -188,6 +188,11 @@ void hcd_port_reset(uint8_t rhport)
 
   ehci_registers_t* regs = ehci_data.regs;
 
+  // skip if already in reset
+  if (regs->portsc_bm.port_reset) {
+    return;
+  }
+
   // mask out Write-1-to-Clear bits
   uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
 
@@ -202,16 +207,18 @@ void hcd_port_reset(uint8_t rhport)
 void hcd_port_reset_end(uint8_t rhport)
 {
   (void) rhport;
-
-#if 0 // TODO check if this is necessary
   ehci_registers_t* regs = ehci_data.regs;
 
+  // skip if reset is already complete
+  if (!regs->portsc_bm.port_reset) {
+    return;
+  }
+
   // mask out all change bits since they are Write 1 to clear
-  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
-  portsc &= ~(EHCI_PORTSC_MASK_PORT_RESET);
+  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
+  portsc &= ~EHCI_PORTSC_MASK_PORT_RESET;
 
   regs->portsc = portsc;
-#endif
 }
 
 bool hcd_port_connect_status(uint8_t rhport)
@@ -426,6 +433,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 
   hcd_dcache_clean(setup_packet, 8);
 
+  // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage
+  if (qhd->qtd_overlay.halted) {
+    qhd->qtd_overlay.halted = false;
+  }
+
   // attach TD to QHD -> start transferring
   qhd_attach_qtd(qhd, td);
 
@@ -662,7 +674,7 @@ void hcd_int_handler(uint8_t rhport)
   if (int_status & EHCI_INT_MASK_PORT_CHANGE) {
     // Including: Force port resume, over-current change, enable/disable change and connect status change.
     uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C;
-    print_portsc(regs);
+    // print_portsc(regs);
 
     if (regs->portsc_bm.connect_status_change) {
       port_connect_status_change_isr(rhport);
-- 
cgit v1.3.1


From 18646179d0c784660ca261fb675e21787451655b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Aug 2023 18:23:16 +0700
Subject: fix host msc get maxlun not using aligned section memory

---
 src/class/msc/msc_host.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index a65208d69..90a58d3d0 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -421,8 +421,7 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   return true;
 }
 
-bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
-{
+bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_ASSERT(p_msc->itf_num == itf_num);
 
@@ -430,10 +429,8 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
 
   //------------- Get Max Lun -------------//
   TU_LOG_DRV("MSC Get Max Lun\r\n");
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_IN
@@ -444,12 +441,11 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
     .wLength  = 1
   };
 
-  tuh_xfer_t xfer =
-  {
+  tuh_xfer_t xfer = {
     .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
-    .buffer      = &p_msc->max_lun,
+    .buffer      = _msch_buffer,
     .complete_cb = config_get_maxlun_complete,
     .user_data    = 0
   };
@@ -467,6 +463,8 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   p_msc->max_lun = (XFER_RESULT_SUCCESS == xfer->result) ? _msch_buffer[0] : 0;
   p_msc->max_lun++; // MAX LUN is minus 1 by specs
 
+  TU_LOG_DRV("  Max LUN = %u\r\n", p_msc->max_lun);
+
   // TODO multiple LUN support
   TU_LOG_DRV("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
-- 
cgit v1.3.1


From 4938971aad2f2a6adb71f4d8ce76e1d4b664092d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Aug 2023 19:09:36 +0700
Subject: code format

---
 hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug |  5 +-
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c   | 73 +++++++++---------------
 2 files changed, 29 insertions(+), 49 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
index 6e298c62d..f94960f09 100644
--- a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
+++ b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
@@ -10,7 +10,7 @@
 */
 void OnProjectLoad (void) {
   Project.AddSvdFile ("Cortex-M3.svd");
-  Project.AddSvdFile ("./LPC18xx.svd");
+  Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC18xx.svd");
 
   Project.SetDevice ("LPC1857");
   Project.SetHostIF ("USB", "");
@@ -20,7 +20,8 @@ void OnProjectLoad (void) {
   Project.SetTraceSource ("Trace Pins");
   Project.SetTracePortWidth (4);
 
-  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-mcb1800/cdc_msc.elf");
+  //File.Open ("../../../../../../examples/cmake-build-mcb1800/device/cdc_msc/cdc_msc.elf");
+  File.Open ("../../../../../../examples/cmake-build-mcb1800/host/cdc_msc_hid/cdc_msc_hid.elf");
 }
 /*********************************************************************
 *
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index adb83e97d..93bc1bf43 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -48,16 +48,14 @@ static pio_usb_configuration_t pio_host_cfg = PIO_USB_DEFAULT_CONFIG;
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
-bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
-{
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
   (void) rhport;
   TU_VERIFY(cfg_id == TUH_CFGID_RPI_PIO_USB_CONFIGURATION);
   memcpy(&pio_host_cfg, cfg_param, sizeof(pio_usb_configuration_t));
   return true;
 }
 
-bool hcd_init(uint8_t rhport)
-{
+bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
   // To run USB SOF interrupt in core1, call this init in core1
@@ -66,20 +64,17 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
-void hcd_port_reset(uint8_t rhport)
-{
+void hcd_port_reset(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_start(pio_rhport);
 }
 
-void hcd_port_reset_end(uint8_t rhport)
-{
+void hcd_port_reset_end(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_end(pio_rhport);
 }
 
-bool hcd_port_connect_status(uint8_t rhport)
-{
+bool hcd_port_connect_status(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
 
   root_port_t *root = PIO_USB_ROOT_PORT(pio_rhport);
@@ -88,33 +83,28 @@ bool hcd_port_connect_status(uint8_t rhport)
   return line_state != PORT_PIN_SE0;
 }
 
-tusb_speed_t hcd_port_speed_get(uint8_t rhport)
-{
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
   // TODO determine link speed
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return PIO_USB_ROOT_PORT(pio_rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
 }
 
 // Close all opened endpoint belong to this device
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
-{
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_close_device(pio_rhport, dev_addr);
 }
 
-uint32_t hcd_frame_number(uint8_t rhport)
-{
+uint32_t hcd_frame_number(uint8_t rhport) {
   (void) rhport;
   return pio_usb_host_get_frame_number();
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   (void) rhport;
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   (void) rhport;
 }
 
@@ -122,18 +112,16 @@ void hcd_int_disable(uint8_t rhport)
 // Endpoint API
 //--------------------------------------------------------------------+
 
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *desc_ep) {
   hcd_devtree_info_t dev_tree;
   hcd_devtree_get_info(dev_addr, &dev_tree);
   bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW);
 
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
-  return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
+  return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre);
 }
 
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
-{
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);
 }
@@ -143,8 +131,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return pio_usb_host_endpoint_abort_transfer(pio_rhport, dev_addr, ep_addr);
 }
 
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
-{
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_send_setup(pio_rhport, dev_addr, setup_packet);
 }
@@ -171,18 +158,16 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return true;
 }
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, xfer_result_t result, volatile uint32_t* ep_reg)
-{
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t *rport, xfer_result_t result,
+                                                               volatile uint32_t *ep_reg) {
   (void) rport;
   const uint32_t ep_all = *ep_reg;
 
-  for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)
-  {
+  for ( uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++ ) {
     uint32_t const mask = (1u << ep_idx);
 
-    if (ep_all & mask)
-    {
-      endpoint_t* ep = PIO_USB_ENDPOINT(ep_idx);
+    if ( ep_all & mask ) {
+      endpoint_t * ep = PIO_USB_ENDPOINT(ep_idx);
       hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true);
     }
   }
@@ -192,34 +177,28 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rpor
 }
 
 // IRQ Handler
-void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
-{
+void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) {
   uint8_t const tu_rhport = root_id + 1;
-  root_port_t* rport = PIO_USB_ROOT_PORT(root_id);
+  root_port_t *rport = PIO_USB_ROOT_PORT(root_id);
   uint32_t const ints = rport->ints;
 
-  if ( ints & PIO_USB_INTS_CONNECT_BITS )
-  {
+  if ( ints & PIO_USB_INTS_CONNECT_BITS ) {
     hcd_event_device_attach(tu_rhport, true);
   }
 
-  if ( ints & PIO_USB_INTS_DISCONNECT_BITS )
-  {
+  if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) {
     hcd_event_device_remove(tu_rhport, true);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_STALLED, &rport->ep_stalled);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error);
   }
 
-- 
cgit v1.3.1


From c959e65edde0b07b80c3e12f177afd938abbdcd6 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Mon, 7 Aug 2023 21:16:41 +0200
Subject: Fixing wrong callback placement

---
 src/device/usbd.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index b4ca63c9c..2daf91d77 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -711,7 +711,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
             }
 
             // switch to new configuration if not zero
-            if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
+            if ( cfg_num )
+            {
+              TU_ASSERT( process_set_config(rhport, cfg_num) );
+
+              if ( tud_mount_cb ) tud_mount_cb();
+            }
+            else
+            {
+              if ( tud_umount_cb ) tud_umount_cb();
+            }
           }
 
           _usbd_dev.cfg_num = cfg_num;
@@ -964,16 +973,6 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT);
   }
 
-  // invoke callback
-  if (cfg_num)
-  {
-    if (tud_mount_cb) tud_mount_cb();
-  }
-  else
-  {
-    if (tud_umount_cb) tud_umount_cb();
-  }
-
   return true;
 }
 
-- 
cgit v1.3.1


From 9602c06f8d52212b55b02533e188e91b7192c080 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Mon, 7 Aug 2023 21:25:50 +0200
Subject: Correcting comments

---
 src/device/usbd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 2daf91d77..156b92ce1 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -710,9 +710,10 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
               _usbd_dev.speed = speed; // restore speed
             }
 
-            // switch to new configuration if not zero
+            // Handle the new configuration and execute the corresponding callback
             if ( cfg_num )
             {
+              // switch to new configuration if not zero
               TU_ASSERT( process_set_config(rhport, cfg_num) );
 
               if ( tud_mount_cb ) tud_mount_cb();
-- 
cgit v1.3.1


From 6d877c31705e4343d30e2a6b65cbd230a3fe2001 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 8 Aug 2023 18:50:24 +0700
Subject: added cmake for lpc54, update lpc55

---
 hw/bsp/lpc54/boards/lpcxpresso54608/board.h        |  59 ++++++++
 hw/bsp/lpc54/boards/lpcxpresso54608/board.mk       |  18 +++
 hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake    |  22 +++
 hw/bsp/lpc54/family.cmake                          | 157 +++++++++++++++++++++
 hw/bsp/lpc55/boards/double_m33_express/board.cmake |   7 +-
 hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake    |   5 +
 hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake    |   7 +-
 hw/bsp/lpc55/family.cmake                          | 134 +++++++++++-------
 src/tusb_option.h                                  |   7 +-
 9 files changed, 356 insertions(+), 60 deletions(-)
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54608/board.h
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
 create mode 100644 hw/bsp/lpc54/family.cmake

(limited to 'src')

diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
new file mode 100644
index 000000000..8bbe18155
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
@@ -0,0 +1,59 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_LPCXPRESSO54608_H_
+#define BOARD_LPCXPRESSO54608_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              2
+#define LED_PIN               2
+#define LED_STATE_ON          0
+
+// WAKE button
+#define BUTTON_PORT           1
+#define BUTTON_PIN            1
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
+
+// USB0 VBUS
+#define USB0_VBUS_PINMUX      0, 22, IOCON_PIO_DIG_FUNC7_EN
+
+// XTAL
+//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
new file mode 100644
index 000000000..af2eaf507
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
@@ -0,0 +1,18 @@
+MCU_VARIANT = LPC54608
+MCU_CORE = LPC54608
+
+PORT ?= 1
+
+CFLAGS += -DCPU_LPC54608J512ET180
+CFLAGS += -Wno-error=double-promotion
+
+LD_FILE = $(MCU_DIR)/gcc/LPC54608J512_flash.ld
+
+LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
+
+JLINK_DEVICE = LPC54608J512
+PYOCD_TARGET = LPC54608
+
+#flash: flash-pyocd
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
new file mode 100644
index 000000000..1dea6f353
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
@@ -0,0 +1,22 @@
+set(MCU_VARIANT LPC54628)
+set(MCU_CORE LPC54628)
+
+set(JLINK_DEVICE LPC54628J512)
+set(PYOCD_TARGET LPC54628)
+set(NXPLINK_DEVICE LPC54628:LPCXpresso54628)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54628J512ET180
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
new file mode 100644
index 000000000..0512fe31f
--- /dev/null
+++ b/hw/bsp/lpc54/family.cmake
@@ -0,0 +1,157 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC54 CACHE INTERNAL "")
+
+if (NOT DEFINED PORT)
+  set(PORT 0)
+endif()
+
+# Host port will be the other port if available
+set(HOST_PORT $<NOT:${PORT}>)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      # driver
+      ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+      ${SDK_DIR}/drivers/common/fsl_common_arm.c
+      ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+      ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+      # mcu
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+      )
+
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+      BOARD_TUD_RHPORT=${PORT}
+      BOARD_TUH_RHPORT=${HOST_PORT}
+      )
+    # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+    if (PORT EQUAL 1)
+      target_compile_definitions(${BOARD_TARGET} PUBLIC
+        BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+        BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+        CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+        )
+    else ()
+      target_compile_definitions(${BOARD_TARGET} PUBLIC
+        BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+        BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+        CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+        )
+    endif ()
+
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${TOP}/lib/sct_neopixel
+      # driver
+      ${SDK_DIR}/drivers/common
+      ${SDK_DIR}/drivers/flexcomm
+      ${SDK_DIR}/drivers/lpc_iocon
+      ${SDK_DIR}/drivers/lpc_gpio
+      ${SDK_DIR}/drivers/lpuart
+      ${SDK_DIR}/drivers/sctimer
+      # mcu
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+    endif ()
+
+    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+    endif ()
+
+    target_sources(${BOARD_TARGET} PUBLIC
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    # external driver
+    ${TOP}/lib/sct_neopixel/sct_neopixel.c
+    )
+
+  # https://github.com/gsteiert/sct_neopixel/pull/1
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
+      COMPILE_FLAGS "-Wno-unused-parameter")
+  endif ()
+
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC54 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
index f84e629c7..3324ce888 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.cmake
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -7,10 +7,13 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
 
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
-    # port 1 is highspeed
-    BOARD_TUD_RHPORT=1
     )
 endfunction()
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
index d935b70e6..b3d0c3349 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -5,6 +5,11 @@ set(JLINK_DEVICE LPC55S28)
 set(PYOCD_TARGET LPC55S28)
 set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
 
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S28JBD100
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
index fd7cb6de6..3af6034ad 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -5,10 +5,13 @@ set(JLINK_DEVICE LPC55S69)
 set(PYOCD_TARGET LPC55S69)
 set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
-    # port 1 is highspeed
-    # BOARD_TUD_RHPORT=1
     )
 endfunction()
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index dfd08a732..dce197b2d 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -7,79 +7,105 @@ endif ()
 set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
 
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+if (NOT DEFINED PORT)
+  set(PORT 0)
+endif()
 
+# Host port will be the other port if available
+set(HOST_PORT $<NOT:${PORT}>)
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      # driver
-      ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
-      ${SDK_DIR}/drivers/common/fsl_common_arm.c
-      ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-      ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
-      # mcu
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
+    )
+  # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+  if (PORT EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+      CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${TOP}/lib/sct_neopixel
-      # driver
-      ${SDK_DIR}/drivers/common
-      ${SDK_DIR}/drivers/flexcomm
-      ${SDK_DIR}/drivers/lpc_iocon
-      ${SDK_DIR}/drivers/lpc_gpio
-      ${SDK_DIR}/drivers/lpuart
-      ${SDK_DIR}/drivers/sctimer
-      # mcu
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+  else ()
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
+    # mcu
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    )
 
-    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
-      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
-    endif ()
+  update_board(${BOARD_TARGET})
 
-    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
-      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
-    endif ()
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  endif ()
 
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-      )
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  endif ()
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        # linker file
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      # linker file
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
   endif ()
 endfunction()
 
@@ -117,7 +143,7 @@ function(family_configure_example TARGET RTOS)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX ${RTOS})
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC55 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
     )
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 7a4cfe51c..c72117850 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -51,8 +51,11 @@
 #define OPT_MCU_LPC40XX             7 ///< NXP LPC40xx
 #define OPT_MCU_LPC43XX             8 ///< NXP LPC43xx
 #define OPT_MCU_LPC51UXX            9 ///< NXP LPC51U6x
-#define OPT_MCU_LPC54XXX           10 ///< NXP LPC54xxx
-#define OPT_MCU_LPC55XX            11 ///< NXP LPC55xx
+#define OPT_MCU_LPC54              10 ///< NXP LPC54
+#define OPT_MCU_LPC55              11 ///< NXP LPC55
+// legacy naming
+#define OPT_MCU_LPC54XXX           OPT_MCU_LPC54
+#define OPT_MCU_LPC55XX            OPT_MCU_LPC55
 
 // NRF
 #define OPT_MCU_NRF5X             100 ///< Nordic nRF5x series
-- 
cgit v1.3.1


From b8b01c10758043d318716569e693912f3e02c75b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 8 Aug 2023 21:59:36 +0700
Subject: update to dcd ip3511 to add work-around for lpc54628 usb hs errata
 USB.1 and USB.2

msc is mounted, but device couldn't work reliably and got constant reset
due to other errata probably.
---
 .idea/cmake.xml                              |   4 +-
 hw/bsp/lpc54/family.c                        |   6 +-
 hw/bsp/lpc54/family.cmake                    |   1 +
 src/common/tusb_common.h                     |   5 +-
 src/common/tusb_mcu.h                        |   8 +-
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 266 ++++++++++++++++-----------
 6 files changed, 170 insertions(+), 120 deletions(-)

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 76143ba10..4a69d02cf 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -30,7 +30,8 @@
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69" />
+      <configuration PROFILE_NAME="lpc54628" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
@@ -51,6 +52,7 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
+      <configuration PROFILE_NAME="lpc54628 PORT0" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT -DPORT=0" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 108a7d783..7411c72d4 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -70,13 +70,11 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB1_IRQHandler(void)
-{
+void USB1_IRQHandler(void) {
   tud_int_handler(1);
 }
 
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index 0512fe31f..b016441c1 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -59,6 +59,7 @@ function(add_board_target BOARD_TARGET)
         BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
         BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
         CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+        #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
         )
     endif ()
 
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 25f85e501..c303c6eaf 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -159,11 +159,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16 (uint16_t x, uint16_t y) {
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; }
 
 //------------- Align -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) {
   return value & ((uint32_t) ~(alignment-1));
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4  (uint32_t value) { return (value & 0xFFFFFFFCUL); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align8  (uint32_t value) { return (value & 0xFFFFFFF8UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 89f89182e..35f94efbc 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -58,6 +58,7 @@
 // NXP
 //--------------------------------------------------------------------+
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
+  #define TUP_USBIP_IP3511
   #define TUP_DCD_ENDPOINT_MAX    5
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
@@ -66,14 +67,17 @@
   #define TUP_OHCI_RHPORTS        2
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
+   #define TUP_USBIP_IP3511
    #define TUP_DCD_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC54)
   // TODO USB0 has 5, USB1 has 6
+  #define TUP_USBIP_IP3511
   #define TUP_DCD_ENDPOINT_MAX    6
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC55)
   // TODO USB0 has 5, USB1 has 6
+  #define TUP_USBIP_IP3511
   #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 7ca698a93..f4ed09d83 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -34,18 +34,13 @@
  * - LPC54114
  * - LPC55s69
  */
-#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC13XX  || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC15XX  || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_IP3511)
 
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX
+#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
   // LPCOpen
   #include "chip.h"
 #else
@@ -80,7 +75,7 @@ typedef struct {
 enum {
   NBYTES_ISO_FS_MAX = 1023, // FS ISO
   NBYTES_ISO_HS_MAX = 1024, // HS ISO
-  NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt
+  NBYTES_CBI_FS_MAX = 64,   // FS control/bulk/interrupt. TODO some FS can do burst with higher size e.g 1024. Need to test
   NBYTES_CBI_HS_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
 };
 
@@ -90,26 +85,36 @@ enum {
 };
 
 enum {
-  CMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
-  CMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
-  CMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
-  CMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
-                                            // 23-22 is link speed (only available for HighSpeed port)
-  CMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
-  CMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
-  CMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
-  CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
+  DEVCMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
+  DEVCMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
+  DEVCMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
+  DEVCMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
+  DEVCMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
+                                               // 23-22 is link speed (only available for HighSpeed port)
+  DEVCMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
+  DEVCMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
+  DEVCMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
+  DEVCMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
 };
 
 enum {
-  CMDSTAT_SPEED_SHIFT = 22
+  DEVCMDSTAT_SPEED_SHIFT = 22
 };
 
 //--------------------------------------------------------------------+
 // Endpoint Command/Status List
 //--------------------------------------------------------------------+
 
+// EP Command/Status field definition
+enum {
+  EPCS_TYPE         = TU_BIT(26),
+  EPCS_RF_TV        = TU_BIT(27),
+  EPCS_TOGGLE_RESET = TU_BIT(28),
+  EPCS_STALL        = TU_BIT(29),
+  EPCS_DISABLED     = TU_BIT(30),
+  EPCS_ACTIVE       = TU_BIT(31),
+};
+
 // Endpoint Command/Status
 typedef union TU_ATTR_PACKED
 {
@@ -133,8 +138,8 @@ typedef union TU_ATTR_PACKED
 
   volatile struct {
     uint32_t TU_RESERVED  : 26;
-    uint32_t is_iso       : 1 ;
-    uint32_t toggle_mode  : 1 ;
+    uint32_t type         : 1 ;
+    uint32_t rf_tv        : 1 ; // rate feedback or toggle value
     uint32_t toggle_reset : 1 ;
     uint32_t stall        : 1 ;
     uint32_t disable      : 1 ;
@@ -180,6 +185,7 @@ typedef struct
 CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
 
 // Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug)
+// TODO find way to save memory
 CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 //--------------------------------------------------------------------+
@@ -188,59 +194,73 @@ CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 typedef struct
 {
-  dcd_registers_t* regs;        // registers
-  const tusb_speed_t max_speed; // max link speed
-  const IRQn_Type irqnum;       // IRQ number
-  const uint8_t ep_pairs;       // Max bi-directional Endpoints
+  dcd_registers_t* regs;   // registers
+  const bool is_highspeed; // max link speed
+  const IRQn_Type irqnum;  // IRQ number
+  const uint8_t ep_pairs;  // Max bi-directional Endpoints
 }dcd_controller_t;
 
 #ifdef INCLUDE_FSL_DEVICE_REGISTERS
 
-static const dcd_controller_t _dcd_controller[] =
-{
-    { .regs = (dcd_registers_t*) USB0_BASE  , .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
+static const dcd_controller_t _dcd_controller[] = {
+    { .regs = (dcd_registers_t*) USB0_BASE  , .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
   #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
-    { .regs = (dcd_registers_t*) USBHSD_BASE, .max_speed = TUSB_SPEED_HIGH, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
+    { .regs = (dcd_registers_t*) USBHSD_BASE, .is_highspeed = true, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
   #endif
 };
 
 #else
 
-static const dcd_controller_t _dcd_controller[] =
-{
-  { .regs = (dcd_registers_t*) LPC_USB0_BASE, .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = 5 },
+static const dcd_controller_t _dcd_controller[] = {
+  { .regs = (dcd_registers_t*) LPC_USB0_BASE, .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = 5 },
 };
 
 #endif
 
+#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
+  #define IP3511_HAS_HIGHSPEED
+#endif
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-static inline uint16_t get_buf_offset(void const * buffer)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t get_buf_offset(void const * buffer) {
   uint32_t addr = (uint32_t) buffer;
   TU_ASSERT( (addr & 0x3f) == 0, 0 );
   return ( (addr >> 6) & 0xFFFFUL ) ;
 }
 
-static inline uint8_t ep_addr2id(uint8_t ep_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t ep_addr2id(uint8_t ep_addr) {
   return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(ep_cmd_sts_t* ep_cs, bool is_highspeed) {
+  return is_highspeed ? (ep_cs[0].cmd_sts.type && !ep_cs[0].cmd_sts.rf_tv) : ep_cs->cmd_sts.type;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool ep_is_bulk(ep_cmd_sts_t* ep_cs) {
+  return (ep_cs[0].cmd_sts.type == 0) && (ep_cs[0].cmd_sts.rf_tv == 0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline ep_cmd_sts_t* get_ep_cs(uint8_t ep_id) {
+  return _dcd.ep[ep_id];
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool rhport_is_highspeed(uint8_t rhport) {
+  return _dcd_controller[rhport].is_highspeed;
+}
+
 //--------------------------------------------------------------------+
 // CONTROLLER API
 //--------------------------------------------------------------------+
 
-static void prepare_setup_packet(uint8_t rhport)
-{
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    _dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet);
-  }else
-  {
-    _dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet);
+static void prepare_setup_packet(uint8_t rhport) {
+  uint16_t const buf_offset = get_buf_offset(_dcd.setup_packet);
+  if ( _dcd_controller[rhport].is_highspeed ) {
+    _dcd.ep[0][1].buffer_hs.offset = buf_offset;
+  } else {
+    _dcd.ep[0][1].buffer_fs.offset = buf_offset;
   }
 }
 
@@ -268,8 +288,8 @@ void dcd_init(uint8_t rhport)
   dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment
   dcd_reg->INTSTAT     |= dcd_reg->INTSTAT; // clear all pending interrupt
   dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK;
-  dcd_reg->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
-                           CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+  dcd_reg->DEVCMDSTAT  |= DEVCMDSTAT_DEVICE_ENABLE_MASK | DEVCMDSTAT_DEVICE_CONNECT_MASK |
+                           DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
 
   NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum);
 }
@@ -291,7 +311,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   // Response with status first before changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
-  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
+  dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_ADDR_MASK;
   dcd_reg->DEVCMDSTAT |= dev_addr;
 }
 
@@ -303,13 +323,13 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -340,19 +360,39 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
   _dcd.ep[ep_id][0].cmd_sts.stall        = 0;
   _dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1;
-  _dcd.ep[ep_id][0].cmd_sts.toggle_mode  = 0;
+  _dcd.ep[ep_id][0].cmd_sts.rf_tv        = 0;
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   //------------- Prepare Queue Head -------------//
   uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
+  ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
 
   // Check if endpoint is available
-  TU_ASSERT( _dcd.ep[ep_id][0].cmd_sts.disable && _dcd.ep[ep_id][1].cmd_sts.disable );
+  TU_ASSERT( ep_cs[0].cmd_sts.disable && ep_cs[1].cmd_sts.disable );
 
   edpt_reset(rhport, ep_id);
-  _dcd.ep[ep_id][0].cmd_sts.is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+
+  switch (p_endpoint_desc->bmAttributes.xfer) {
+    case TUSB_XFER_ISOCHRONOUS:
+      ep_cs[0].cmd_sts.type = 1;
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      // What is interrupt endpoint in rate feedback mode ?
+      if ( rhport_is_highspeed(rhport) ) {
+        ep_cs[0].cmd_sts.type = 1;
+        ep_cs[0].cmd_sts.rf_tv = 1;
+      }
+      break;
+
+    case TUSB_XFER_BULK:
+      // nothing to do both type and rf_tv are 0
+      break;
+
+    default: break;
+  }
 
   // Enable EP interrupt
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -379,42 +419,50 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
 }
 
-static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
-{
+static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes) {
   uint16_t nbytes;
-
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].cmd_sts.is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
-    _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
-    _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
-  }else
-  {
-    nbytes = tu_min16(total_bytes, NBYTES_CBI_HS_MAX);
-    _dcd.ep[ep_id][0].buffer_hs.offset = buf_offset;
-    _dcd.ep[ep_id][0].buffer_hs.nbytes = nbytes;
+  ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
+
+  const bool is_iso = ep_is_iso(ep_cs, _dcd_controller[rhport].is_highspeed);
+
+  if ( rhport_is_highspeed(rhport) ) {
+    nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_HS_MAX : NBYTES_CBI_HS_MAX);
+    #if TU_CHECK_MCU(OPT_MCU_LPC54)
+    // LPC54 Errata USB.1: In USB high-speed device mode, the NBytes field does not decrement after BULK OUT transfer.
+    // Suggested Work-around: Program the NByte to the max packet size (512)
+    // Actual Work-around: round up NByte to multiple of 4.
+    // Note: this can cause buffer overflowed and corrupt data if host send more data than total_bytes
+    if ( (ep_id > 1) && (ep_id & 0x01) == 0 && ep_is_bulk(ep_cs) ) {
+      if ( nbytes & 0x03 ) {
+        nbytes = tu_align4(nbytes) + 4;
+      }
+    }
+    #endif
+
+    ep_cs[0].buffer_hs.offset = buf_offset;
+    ep_cs[0].buffer_hs.nbytes = nbytes;
+  }else {
+    nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
+    ep_cs[0].buffer_fs.offset = buf_offset;
+    ep_cs[0].buffer_fs.nbytes = nbytes;
   }
 
   _dcd.dma[ep_id].nbytes = nbytes;
-
-  _dcd.ep[ep_id][0].cmd_sts.active = 1;
+  ep_cs[0].cmd_sts.active = 1;
 }
 
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   uint8_t const ep_id = ep_addr2id(ep_addr);
 
+  if (!buffer || total_bytes == 0) {
+    // Although having no data, ZLPs can cause buffer overwritten to zeroes. Probably due to USB/DMA controller side
+    // effect/bug. Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
+    buffer = (uint8_t *) (uint32_t) dummy;
+  }
+
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  if (!buffer)
-  {
-    // Although having no data, ZLPs can cause buffer overwritten to zeroes.
-    // Probably due to USB/DMA controller side effect/bug.
-    // Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
-    buffer = (uint8_t*)(uint32_t)dummy;
-  }
-
   prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
 
   return true;
@@ -441,23 +489,19 @@ static void bus_reset(uint8_t rhport)
   dcd_reg->EPSKIP       = 0xFFFFFFFF;
 
   dcd_reg->INTSTAT      = dcd_reg->INTSTAT;                               // clear all pending interrupt
-  dcd_reg->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK;                    // clear setup received interrupt
+  dcd_reg->DEVCMDSTAT  |= DEVCMDSTAT_SETUP_RECEIVED_MASK;                    // clear setup received interrupt
   dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints
 }
 
-static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
-{
+static void process_xfer_isr(uint8_t rhport, uint32_t int_status) {
   uint8_t const max_ep = 2*_dcd_controller[rhport].ep_pairs;
 
-  for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ )
-  {
-    if ( tu_bit_test(int_status, ep_id) )
-    {
+  for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ ) {
+    if ( tu_bit_test(int_status, ep_id) ) {
       ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
       xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
 
-      if ( ep_id == 0 || ep_id == 1)
-      {
+      if ( ep_id <= 1 ) {
         // For control endpoint, we need to manually clear Active bit
         ep_cs->cmd_sts.active = 0;
       }
@@ -465,26 +509,29 @@ static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
       uint16_t buf_offset;
       uint16_t buf_nbytes;
 
-      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL)
-      {
-        buf_offset = ep_cs->buffer_fs.offset;
-        buf_nbytes = ep_cs->buffer_fs.nbytes;
-      }else
-      {
+      if ( rhport_is_highspeed(rhport) ) {
         buf_offset = ep_cs->buffer_hs.offset;
         buf_nbytes = ep_cs->buffer_hs.nbytes;
+
+        #if TU_CHECK_MCU(OPT_MCU_LPC54)
+        // LPC54 Errata USB.2: In USB high-speed device mode, the NBytes field is not correct after BULK IN transfer
+        // There is no work-around. For EP in transfer, the NByte value can be ignored after a packet is transmitted.
+        if ( (ep_id > 1) && (ep_id & 0x01) == 1 && ep_is_bulk(ep_cs) ) {
+          buf_nbytes = 0;
+        }
+        #endif
+      } else {
+        buf_offset = ep_cs->buffer_fs.offset;
+        buf_nbytes = ep_cs->buffer_fs.nbytes;
       }
 
       xfer_dma->xferred_bytes += xfer_dma->nbytes - buf_nbytes;
 
-      if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
-      {
+      if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) ) {
         // There is more data to transfer
         // buff_offset has been already increased by hw to correct value for next transfer
         prepare_ep_xfer(rhport, ep_id, buf_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
-      }
-      else
-      {
+      } else {
         // for detecting ZLP
         xfer_dma->total_bytes = xfer_dma->xferred_bytes;
 
@@ -511,19 +558,16 @@ void dcd_int_handler(uint8_t rhport)
   //------------- Device Status -------------//
   if ( int_status & INT_DEVICE_STATUS_MASK )
   {
-    dcd_reg->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
 
-    if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+    if ( cmd_stat & DEVCMDSTAT_RESET_CHANGE_MASK) // bus reset
     {
       bus_reset(rhport);
 
       tusb_speed_t speed = TUSB_SPEED_FULL;
-
-      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_HIGH)
-      {
+      if ( _dcd_controller[rhport].is_highspeed ) {
         // 0 : reserved, 1 : full, 2 : high, 3: super
-        if ( 2 == ((cmd_stat >> CMDSTAT_SPEED_SHIFT) & 0x3UL) )
-        {
+        if ( 2 == ((cmd_stat >> DEVCMDSTAT_SPEED_SHIFT) & 0x3UL) ) {
           speed= TUSB_SPEED_HIGH;
         }
       }
@@ -531,35 +575,35 @@ void dcd_int_handler(uint8_t rhport)
       dcd_event_bus_reset(rhport, speed, true);
     }
 
-    if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
+    if (cmd_stat & DEVCMDSTAT_CONNECT_CHANGE_MASK)
     {
       // device disconnect
-      if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
       {
         // debouncing as this can be set when device is powering
         dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
       }
     }
 
-    if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
+    if (cmd_stat & DEVCMDSTAT_SUSPEND_CHANGE_MASK)
     {
       // suspend signal, bus idle for more than 3ms
       // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
       {
-        dcd_event_bus_signal(rhport, (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
+        dcd_event_bus_signal(rhport, (cmd_stat & DEVCMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
       }
     }
   }
 
   // Setup Receive
-  if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
+  if ( tu_bit_test(int_status, 0) && (cmd_stat & DEVCMDSTAT_SETUP_RECEIVED_MASK) )
   {
     // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
     _dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0;
     _dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0;
 
-    dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+    dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_SETUP_RECEIVED_MASK;
 
     dcd_event_setup_received(rhport, _dcd.setup_packet, true);
 
-- 
cgit v1.3.1


From 798ff807b3361a5859945cb23c3d0fd7d1a5679f Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Fri, 11 Aug 2023 18:04:34 +0200
Subject: removed obsolete tud_network_link_state_cb()

---
 src/class/net/ncm_device.c |  7 -------
 src/class/net/net_device.h |  5 -----
 test/fuzz/net_fuzz.cc      | 10 +---------
 3 files changed, 1 insertion(+), 21 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 226c42c4e..dc086cf5c 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -337,11 +337,6 @@ static void ncm_report(void)
   }
 }
 
-TU_ATTR_WEAK void tud_network_link_state_cb(bool state)
-{
-  (void)state;
-}
-
 // Handle class control request
 // return false to stall control endpoint (e.g unsupported request)
 bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
@@ -381,8 +376,6 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
                 ncm_report();
               }
             }
-
-            tud_network_link_state_cb(ncm_interface.itf_data_alt);
           }
 
           tud_control_status(rhport, request);
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 399916355..454fde861 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -96,11 +96,6 @@ void tud_network_init_cb(void);
 // TODO removed later since it is not part of tinyusb stack
 extern uint8_t tud_network_mac_address[6];
 
-//------------- NCM -------------//
-
-// callback to client providing optional indication of internal state of network driver
-void tud_network_link_state_cb(bool state);
-
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
diff --git a/test/fuzz/net_fuzz.cc b/test/fuzz/net_fuzz.cc
index 63cd1ac98..468437b0c 100644
--- a/test/fuzz/net_fuzz.cc
+++ b/test/fuzz/net_fuzz.cc
@@ -69,14 +69,6 @@ void tud_network_init_cb(void) {
 // TODO removed later since it is not part of tinyusb stack
 uint8_t tud_network_mac_address[6] = {0};
 
-//------------- NCM -------------//
-
-// callback to client providing optional indication of internal state of network
-// driver
-void tud_network_link_state_cb(bool state) {
-  (void)state;
-  // NoOp.
-}
-}
+}   // extern "C"
 
 #endif
-- 
cgit v1.3.1


From bd51afb091f29cdab6520479a1a504409d95aac8 Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Mon, 14 Aug 2023 08:49:52 -0400
Subject: min on cdc r/w

---
 src/class/cdc/cdc_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 70d9c2e24..2c1fda4ff 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -150,7 +150,7 @@ uint32_t tud_cdc_n_available(uint8_t itf)
 uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) bufsize);
+  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
   _prep_out_transaction(p_cdc);
   return num_read;
 }
@@ -173,7 +173,7 @@ void tud_cdc_n_read_flush (uint8_t itf)
 uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize);
+  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
 
   // flush if queue more than packet size
   // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
-- 
cgit v1.3.1


From b5ba12119dccb123aa6e8798dc86d639af6703b9 Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Mon, 14 Aug 2023 09:01:30 -0400
Subject: UINT16_MAX stdint macro usage

---
 src/class/cdc/cdc_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 2c1fda4ff..c26264e60 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -150,7 +150,7 @@ uint32_t tud_cdc_n_available(uint8_t itf)
 uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
+  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
   _prep_out_transaction(p_cdc);
   return num_read;
 }
@@ -173,7 +173,7 @@ void tud_cdc_n_read_flush (uint8_t itf)
 uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
+  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
 
   // flush if queue more than packet size
   // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
-- 
cgit v1.3.1


From 9d942967414d7b95f3a132c284ef83f386a0c467 Mon Sep 17 00:00:00 2001
From: rppicomidi <rppicomidi@gmail.com>
Date: Mon, 14 Aug 2023 15:38:48 -0700
Subject: fix issue 2188: support usbh_app_driver_get_cb()

---
 README.rst                  |  2 ++
 src/host/usbh.c             | 86 ++++++++++++++++++++++++++++++++-------------
 src/host/usbh_classdriver.h |  8 +++++
 3 files changed, 72 insertions(+), 24 deletions(-)

(limited to 'src')

diff --git a/README.rst b/README.rst
index 78e8d87b0..d72cdb149 100644
--- a/README.rst
+++ b/README.rst
@@ -89,6 +89,8 @@ Host Stack
 - Mass Storage Class (MSC)
 - Hub with multiple-level support
 
+Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack.
+
 TypeC PD Stack
 ==============
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index cc7e38b45..af8142be3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -180,7 +180,7 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #endif
 };
 
-enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
+enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 
@@ -246,6 +246,21 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
+// Additional class drivers implemented by application
+tu_static usbh_class_driver_t const * _app_driver = NULL;
+tu_static uint8_t _app_driver_count = 0;
+tu_static uint8_t _total_driver_count = USBH_BUILTIN_DRIVER_COUNT;
+
+static usbh_class_driver_t const * usbh_get_driver(uint8_t drv_id)
+{
+  usbh_class_driver_t const * driver = NULL;
+  if ( drv_id < _app_driver_count )
+    driver = &_app_driver[drv_id];
+  else if ( drv_id < _total_driver_count )
+    driver = &usbh_class_drivers[drv_id - _app_driver_count];
+  return driver;
+}
+
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
 // weak and overridable
@@ -339,6 +354,12 @@ bool tuh_init(uint8_t controller_id) {
   _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
   TU_ASSERT(_usbh_mutex);
 #endif
+  // Get application driver if available
+  if ( usbh_app_driver_get_cb )
+  {
+    _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
+    _total_driver_count = USBH_BUILTIN_DRIVER_COUNT + _app_driver_count;
+  }
 
   // Device
   tu_memclr(&_dev0, sizeof(_dev0));
@@ -351,10 +372,14 @@ bool tuh_init(uint8_t controller_id) {
   }
 
   // Class drivers
-  for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+  for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
   {
-    TU_LOG_USBH("%s init\r\n", usbh_class_drivers[drv_id].name);
-    usbh_class_drivers[drv_id].init();
+    usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+    if ( driver )
+    {
+      TU_LOG_USBH("%s init\r\n", driver->name);
+      driver->init();
+    }
   }
 
   _usbh_controller = controller_id;;
@@ -482,12 +507,16 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
             }else
             #endif
             {
-              uint8_t const drv_id = dev->ep2drv[epnum][ep_dir];
-              if ( drv_id < USBH_CLASS_DRIVER_COUNT ) {
-                TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-                usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
+              uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
+              usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+              if ( driver )
+              {
+                TU_LOG_USBH("%s xfer callback\r\n", driver->name);
+                driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
                                                    event.xfer_complete.len);
-              } else {
+              }
+              else
+              {
                 // no driver/callback responsible for this transfer
                 TU_ASSERT(false,);
               }
@@ -1183,17 +1212,20 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
   uint8_t nop_count = 0;
 #endif
 
-  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
+  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++)
+  {
     usbh_device_t *dev = &_usbh_devices[dev_id];
     uint8_t const daddr = dev_id + 1;
 
     // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
     if (dev->rhport == rhport && dev->connected &&
         (hub_addr == 0 || dev->hub_addr == hub_addr) &&
-        (hub_port == 0 || dev->hub_port == hub_port)) {
+        (hub_port == 0 || dev->hub_port == hub_port))
+    {
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
-      if (is_hub_addr(daddr)) {
+      if (is_hub_addr(daddr))
+      {
         TU_LOG(CFG_TUH_LOG_LEVEL, "  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
@@ -1211,10 +1243,14 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       }
 
       // Close class driver
-      for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) {
-        usbh_class_drivers[drv_id].close(daddr);
+      for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
+      {
+        usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+        if ( driver )
+        {
+          driver->close(daddr);
+        }
       }
-
       hcd_device_close(rhport, daddr);
       clear_device(dev);
       // abort on-going control xfer if any
@@ -1643,11 +1679,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
-    for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+    uint8_t drv_id = 0;
+    for (; drv_id < _total_driver_count; drv_id++)
     {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
 
-      if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
+      if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
       {
         // open successfully
         TU_LOG_USBH("  %s opened\r\n", driver->name);
@@ -1668,11 +1705,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
         break; // exit driver find loop
       }
 
-      if( drv_id >= USBH_CLASS_DRIVER_COUNT )
-      {
-        TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
-               desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
-      }
+    }
+
+    if( drv_id >= _total_driver_count )
+    {
+      TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+            desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
     }
 
     // next Interface or IAD descriptor
@@ -1694,7 +1732,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
     uint8_t const drv_id = dev->itf2drv[itf_num];
     if (drv_id != TUSB_INDEX_INVALID_8)
     {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 308b4418a..7443b2d90 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -96,6 +96,14 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
 // Check if endpoint transferring is complete
 bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
 
+//--------------------------------------------------------------------+
+// USBH application additional driver API
+//--------------------------------------------------------------------+
+// Invoked when initializing host stack to get additional class drivers.
+// Can optionally implemented by application to extend/overwrite class driver support.
+// Note: The drivers array must be accessible at all time when stack is active
+usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
+
 #ifdef __cplusplus
  }
 #endif
-- 
cgit v1.3.1


From 1b33a315365184a74a8b5bbce5fdbdfc4dfe6f69 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Aug 2023 22:51:21 +0700
Subject: more minor clean up

- also rename usbh_classdriver.h to usbh_pvt.h to consitent with usbd
---
 src/class/cdc/cdc_host.c    |   2 +-
 src/class/hid/hid_host.c    |   2 +-
 src/class/msc/msc_host.c    |   2 +-
 src/device/usbd.c           |  31 +++++--------
 src/device/usbd_pvt.h       |   2 +-
 src/host/hub.c              |   2 +-
 src/host/usbh.c             |  84 ++++++++++++++++-----------------
 src/host/usbh_classdriver.h | 111 --------------------------------------------
 src/host/usbh_pvt.h         | 108 ++++++++++++++++++++++++++++++++++++++++++
 src/tusb.c                  |   2 +-
 10 files changed, 164 insertions(+), 182 deletions(-)
 delete mode 100644 src/host/usbh_classdriver.h
 create mode 100644 src/host/usbh_pvt.h

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 40ebd331d..53e15710e 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -29,7 +29,7 @@
 #if (CFG_TUH_ENABLED && CFG_TUH_CDC)
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "cdc_host.h"
 
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 4253170d4..a3551c85a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -29,7 +29,7 @@
 #if (CFG_TUH_ENABLED && CFG_TUH_HID)
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "hid_host.h"
 
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 90a58d3d0..da264142c 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -29,7 +29,7 @@
 #if CFG_TUH_ENABLED && CFG_TUH_MSC
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "msc_host.h"
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 156b92ce1..f0d9fba52 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -238,34 +238,25 @@ enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
 tu_static usbd_class_driver_t const * _app_driver = NULL;
 tu_static uint8_t _app_driver_count = 0;
 
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
+
 // virtually joins built-in and application drivers together.
 // Application is positioned first to allow overwriting built-in ones.
 static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 {
-  // Application drivers
-  if ( usbd_app_driver_get_cb )
-  {
-    if ( drvid < _app_driver_count ) return &_app_driver[drvid];
-    drvid -= _app_driver_count;
-  }
-
-  // when there is no built-in drivers BUILTIN_DRIVER_COUNT = 0 will cause -Wtype-limits warning
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wtype-limits"
-#endif
-
-  // Built-in drivers
-  if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid];
+  usbd_class_driver_t const * driver = NULL;
 
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
+  if ( drvid < _app_driver_count ) {
+    // Application drivers
+    driver = &_app_driver[drvid];
+  } else if ( drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0 ){
+    driver = &_usbd_driver[drvid - _app_driver_count];
+  }
 
-  return NULL;
+  return driver;
 }
 
-#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
+
 
 //--------------------------------------------------------------------+
 // DCD Event
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 940b2858b..16585167f 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -59,7 +59,7 @@ typedef struct
 } usbd_class_driver_t;
 
 // Invoked when initializing device stack to get additional class drivers.
-// Can optionally implemented by application to extend/overwrite class driver support.
+// Can be implemented by application to extend/overwrite class driver support.
 // Note: The drivers array must be accessible at all time when stack is active
 usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
 
diff --git a/src/host/hub.c b/src/host/hub.c
index ec30eb96a..32f5e0ac7 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -30,7 +30,7 @@
 
 #include "hcd.h"
 #include "usbh.h"
-#include "usbh_classdriver.h"
+#include "usbh_pvt.h"
 #include "hub.h"
 
 // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
diff --git a/src/host/usbh.c b/src/host/usbh.c
index af8142be3..739157b56 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -30,7 +30,7 @@
 
 #include "host/hcd.h"
 #include "tusb.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 #include "hub.h"
 
 //--------------------------------------------------------------------+
@@ -183,6 +183,23 @@ static usbh_class_driver_t const usbh_class_drivers[] =
 enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
+// Additional class drivers implemented by application
+tu_static usbh_class_driver_t const * _app_driver = NULL;
+tu_static uint8_t _app_driver_count = 0;
+
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + USBH_BUILTIN_DRIVER_COUNT)
+
+static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) {
+  usbh_class_driver_t const *driver = NULL;
+
+  if ( drv_id < _app_driver_count ) {
+    driver = &_app_driver[drv_id];
+  } else if ( drv_id < TOTAL_DRIVER_COUNT && USBH_BUILTIN_DRIVER_COUNT > 0) {
+    driver = &usbh_class_drivers[drv_id - _app_driver_count];
+  }
+
+  return driver;
+}
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -246,21 +263,6 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
-// Additional class drivers implemented by application
-tu_static usbh_class_driver_t const * _app_driver = NULL;
-tu_static uint8_t _app_driver_count = 0;
-tu_static uint8_t _total_driver_count = USBH_BUILTIN_DRIVER_COUNT;
-
-static usbh_class_driver_t const * usbh_get_driver(uint8_t drv_id)
-{
-  usbh_class_driver_t const * driver = NULL;
-  if ( drv_id < _app_driver_count )
-    driver = &_app_driver[drv_id];
-  else if ( drv_id < _total_driver_count )
-    driver = &usbh_class_drivers[drv_id - _app_driver_count];
-  return driver;
-}
-
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
 // weak and overridable
@@ -354,11 +356,10 @@ bool tuh_init(uint8_t controller_id) {
   _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
   TU_ASSERT(_usbh_mutex);
 #endif
+
   // Get application driver if available
-  if ( usbh_app_driver_get_cb )
-  {
+  if ( usbh_app_driver_get_cb ) {
     _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
-    _total_driver_count = USBH_BUILTIN_DRIVER_COUNT + _app_driver_count;
   }
 
   // Device
@@ -372,9 +373,9 @@ bool tuh_init(uint8_t controller_id) {
   }
 
   // Class drivers
-  for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
+  for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
   {
-    usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+    usbh_class_driver_t const * driver = get_driver(drv_id);
     if ( driver )
     {
       TU_LOG_USBH("%s init\r\n", driver->name);
@@ -508,12 +509,12 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
             #endif
             {
               uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-              usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+              usbh_class_driver_t const * driver = get_driver(drv_id);
               if ( driver )
               {
                 TU_LOG_USBH("%s xfer callback\r\n", driver->name);
                 driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
-                                                   event.xfer_complete.len);
+                                event.xfer_complete.len);
               }
               else
               {
@@ -1220,12 +1221,10 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
     // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
     if (dev->rhport == rhport && dev->connected &&
         (hub_addr == 0 || dev->hub_addr == hub_addr) &&
-        (hub_port == 0 || dev->hub_port == hub_port))
-    {
+        (hub_port == 0 || dev->hub_port == hub_port)) {
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
-      if (is_hub_addr(daddr))
-      {
+      if (is_hub_addr(daddr)) {
         TU_LOG(CFG_TUH_LOG_LEVEL, "  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
@@ -1243,14 +1242,11 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       }
 
       // Close class driver
-      for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
-      {
-        usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
-        if ( driver )
-        {
-          driver->close(daddr);
-        }
+      for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+        usbh_class_driver_t const * driver = get_driver(drv_id);
+        if ( driver ) driver->close(daddr);
       }
+
       hcd_device_close(rhport, daddr);
       clear_device(dev);
       // abort on-going control xfer if any
@@ -1679,10 +1675,9 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
-    uint8_t drv_id = 0;
-    for (; drv_id < _total_driver_count; drv_id++)
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
     {
-      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+      usbh_class_driver_t const * driver = get_driver(drv_id);
 
       if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
       {
@@ -1705,12 +1700,11 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
         break; // exit driver find loop
       }
 
-    }
-
-    if( drv_id >= _total_driver_count )
-    {
-      TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
-            desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
+      if ( drv_id == TOTAL_DRIVER_COUNT - 1 )
+      {
+        TU_LOG(CFG_TUH_LOG_LEVEL, "[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+               dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
+      }
     }
 
     // next Interface or IAD descriptor
@@ -1730,9 +1724,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
     // IAD binding interface such as CDCs should return itf_num + 1 when complete
     // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != TUSB_INDEX_INVALID_8)
+    usbh_class_driver_t const * driver = get_driver(drv_id);
+    if (driver)
     {
-      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
deleted file mode 100644
index 7443b2d90..000000000
--- a/src/host/usbh_classdriver.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef _TUSB_USBH_CLASSDRIVER_H_
-#define _TUSB_USBH_CLASSDRIVER_H_
-
-#include "osal/osal.h"
-#include "common/tusb_fifo.h"
-#include "common/tusb_private.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
-#ifndef CFG_TUH_LOG_LEVEL
-  #define CFG_TUH_LOG_LEVEL   2
-#endif
-
-#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
-
-enum {
-  USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
-};
-
-//--------------------------------------------------------------------+
-// Class Driver API
-//--------------------------------------------------------------------+
-
-typedef struct {
-  #if CFG_TUSB_DEBUG >= 2
-  char const* name;
-  #endif
-
-  void (* const init       )(void);
-  bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
-  bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
-  bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-  void (* const close      )(uint8_t dev_addr);
-} usbh_class_driver_t;
-
-// Call by class driver to tell USBH that it has complete the enumeration
-void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
-
-uint8_t usbh_get_rhport(uint8_t dev_addr);
-
-uint8_t* usbh_get_enum_buf(void);
-
-void usbh_int_set(bool enabled);
-
-//--------------------------------------------------------------------+
-// USBH Endpoint API
-//--------------------------------------------------------------------+
-
-// Submit a usb transfer with callback support, require CFG_TUH_API_EDPT_XFER
-bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-
-TU_ATTR_ALWAYS_INLINE
-static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0);
-}
-
-
-// Claim an endpoint before submitting a transfer.
-// If caller does not make any transfer, it must release endpoint for others.
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
-
-// Release claimed endpoint without submitting a transfer
-bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
-
-// Check if endpoint transferring is complete
-bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
-
-//--------------------------------------------------------------------+
-// USBH application additional driver API
-//--------------------------------------------------------------------+
-// Invoked when initializing host stack to get additional class drivers.
-// Can optionally implemented by application to extend/overwrite class driver support.
-// Note: The drivers array must be accessible at all time when stack is active
-usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
new file mode 100644
index 000000000..0b58a91bc
--- /dev/null
+++ b/src/host/usbh_pvt.h
@@ -0,0 +1,108 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_USBH_CLASSDRIVER_H_
+#define _TUSB_USBH_CLASSDRIVER_H_
+
+#include "osal/osal.h"
+#include "common/tusb_fifo.h"
+#include "common/tusb_private.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
+#ifndef CFG_TUH_LOG_LEVEL
+  #define CFG_TUH_LOG_LEVEL   2
+#endif
+
+#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+
+enum {
+  USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
+};
+
+//--------------------------------------------------------------------+
+// Class Driver API
+//--------------------------------------------------------------------+
+
+typedef struct {
+  #if CFG_TUSB_DEBUG >= 2
+  char const* name;
+  #endif
+
+  void (* const init       )(void);
+  bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
+  bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
+  bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+  void (* const close      )(uint8_t dev_addr);
+} usbh_class_driver_t;
+
+// Invoked when initializing host stack to get additional class drivers.
+// Can be implemented by application to extend/overwrite class driver support.
+// Note: The drivers array must be accessible at all time when stack is active
+usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
+
+// Call by class driver to tell USBH that it has complete the enumeration
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
+
+uint8_t usbh_get_rhport(uint8_t dev_addr);
+
+uint8_t* usbh_get_enum_buf(void);
+
+void usbh_int_set(bool enabled);
+
+//--------------------------------------------------------------------+
+// USBH Endpoint API
+//--------------------------------------------------------------------+
+
+// Submit a usb transfer with callback support, require CFG_TUH_API_EDPT_XFER
+bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+TU_ATTR_ALWAYS_INLINE
+static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0);
+}
+
+
+// Claim an endpoint before submitting a transfer.
+// If caller does not make any transfer, it must release endpoint for others.
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
+
+// Release claimed endpoint without submitting a transfer
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
+
+// Check if endpoint transferring is complete
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/tusb.c b/src/tusb.c
index 465b608b0..7b0a669a0 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -36,7 +36,7 @@
 #endif
 
 #if CFG_TUH_ENABLED
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 #endif
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 67a374d932cbe14bf1651bdd6fea82c2e2ecfa10 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Aug 2023 22:57:05 +0700
Subject: more rename

---
 src/host/usbh.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 739157b56..7cdcbda5e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -180,21 +180,21 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #endif
 };
 
-enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
+enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 // Additional class drivers implemented by application
 tu_static usbh_class_driver_t const * _app_driver = NULL;
 tu_static uint8_t _app_driver_count = 0;
 
-#define TOTAL_DRIVER_COUNT    (_app_driver_count + USBH_BUILTIN_DRIVER_COUNT)
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
 
 static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) {
   usbh_class_driver_t const *driver = NULL;
 
   if ( drv_id < _app_driver_count ) {
     driver = &_app_driver[drv_id];
-  } else if ( drv_id < TOTAL_DRIVER_COUNT && USBH_BUILTIN_DRIVER_COUNT > 0) {
+  } else if ( drv_id < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0) {
     driver = &usbh_class_drivers[drv_id - _app_driver_count];
   }
 
-- 
cgit v1.3.1


From b3c7fe1023d14d1e07eb21ca9a61438bff49a788 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Aug 2023 00:09:31 +0700
Subject: clear qhd halted bit if not caused by STALL protocol, allow for next
 transfer

---
 src/portable/ehci/ehci.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 79811985c..c5036b5a3 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -579,6 +579,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
       if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
         // Error count = 0 often occurs when device disconnected, or other bus-related error
         xfer_result = XFER_RESULT_FAILED;
+        qtd_overlay->halted = false; // clear halted bit if it is not caused by STALL
         TU_LOG3("  QHD xfer err count: %d\n", qtd_overlay->err_count);
         // TU_BREAKPOINT(); // TODO skip unplugged device
       }else {
-- 
cgit v1.3.1


From 0109ffbdcb22a358ecbc1476fbfb4e370e5bb4cc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Aug 2023 14:31:14 +0700
Subject: fix abort transfer does not release endpoint, also reset state if it
 is control transfer

---
 src/host/usbh.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7cdcbda5e..5423df669 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -738,19 +738,27 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
   usbh_device_t* dev = get_device(daddr);
   TU_VERIFY(dev);
 
+  TU_LOG_USBH("[%u] Aborted transfer on EP %02X\r\n", daddr, ep_addr);
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  // skip if not busy
-  TU_VERIFY(dev->ep_status[epnum][dir].busy);
-
-  bool const ret = hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr);
-  if (ret) {
-    // mark as ready if transfer is aborted
+  if ( epnum == 0 ) {
+    // control transfer: only 1 control at a time, check if we are aborting the current one
+    TU_VERIFY(daddr == _ctrl_xfer.daddr && _ctrl_xfer.stage != CONTROL_STAGE_IDLE);
+    TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr));
+    // reset control transfer state to idle
+    _set_control_xfer_stage(CONTROL_STAGE_IDLE);
+  } else {
+    // non-control skip if not busy
+    TU_VERIFY(dev->ep_status[epnum][dir].busy);
+    TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr));
+    // mark as ready and release endpoint if transfer is aborted
     dev->ep_status[epnum][dir].busy = false;
+    usbh_edpt_release(daddr, ep_addr);
   }
 
-  return ret;
+  return true;
 }
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From f4845e4e6cc2faca4e60cd83959850f27d3f3076 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Aug 2023 14:43:58 +0700
Subject: minor comment

---
 src/portable/ehci/ehci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index c5036b5a3..c93c33fc0 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -578,8 +578,9 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
     if ( qtd_overlay->halted ) {
       if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
         // Error count = 0 often occurs when device disconnected, or other bus-related error
+        // clear halted bit if not caused by STALL to allow more transfer
         xfer_result = XFER_RESULT_FAILED;
-        qtd_overlay->halted = false; // clear halted bit if it is not caused by STALL
+        qtd_overlay->halted = false;
         TU_LOG3("  QHD xfer err count: %d\n", qtd_overlay->err_count);
         // TU_BREAKPOINT(); // TODO skip unplugged device
       }else {
-- 
cgit v1.3.1


From 9257a0f562a1cb939a902e7c41de5032b0f7de19 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Aug 2023 12:48:12 +0700
Subject: - update nrf52 bsp for cmake - add empty
 tuh_int_handler/tud_int_handler if corresponidng stack not enabled - add
 hcd_template.c

---
 hw/bsp/nrf/boards/adafruit_clue/board.cmake        |   5 +
 hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake   |   5 +
 .../boards/circuitplayground_bluefruit/board.cmake |   5 +
 .../boards/feather_nrf52840_express/board.cmake    |   6 +
 .../nrf/boards/feather_nrf52840_sense/board.cmake  |   5 +
 hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake   |   5 +
 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake  |   5 +
 hw/bsp/nrf/boards/pca10056/board.cmake             |   3 -
 hw/bsp/nrf/boards/pca10059/board.cmake             |   5 +
 hw/bsp/nrf/boards/pca10095/board.cmake             |   4 -
 hw/bsp/nrf/boards/pca10100/board.cmake             |   5 +
 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake    |   5 +
 hw/bsp/nrf/family.cmake                            |  14 +-
 src/device/usbd.h                                  |   6 +-
 src/host/hcd.h                                     |  12 +-
 src/portable/template/dcd_template.c               |   4 +-
 src/portable/template/hcd_template.c               | 162 +++++++++++++++++++++
 src/tusb.h                                         |   9 +-
 18 files changed, 241 insertions(+), 24 deletions(-)
 create mode 100644 hw/bsp/nrf/boards/adafruit_clue/board.cmake
 create mode 100644 hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
 create mode 100644 hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
 create mode 100644 hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
 create mode 100644 hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
 create mode 100644 hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
 create mode 100644 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
 create mode 100644 hw/bsp/nrf/boards/pca10059/board.cmake
 create mode 100644 hw/bsp/nrf/boards/pca10100/board.cmake
 create mode 100644 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
 create mode 100644 src/portable/template/hcd_template.c

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.cmake b/hw/bsp/nrf/boards/adafruit_clue/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/adafruit_clue/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
new file mode 100644
index 000000000..93647063a
--- /dev/null
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/arduino_nano33_ble.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
new file mode 100644
index 000000000..0acbecf7a
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -0,0 +1,6 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
new file mode 100644
index 000000000..ffa5932c1
--- /dev/null
+++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/nrf52840_mdk_dongle.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
index b4fe39fc0..693d7beed 100644
--- a/hw/bsp/nrf/boards/pca10056/board.cmake
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -2,7 +2,4 @@ set(MCU_VARIANT nrf52840)
 set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    NRF52840_XXAA
-    )
 endfunction()
diff --git a/hw/bsp/nrf/boards/pca10059/board.cmake b/hw/bsp/nrf/boards/pca10059/board.cmake
new file mode 100644
index 000000000..c79eb5964
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10059/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/pca10059.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index 1e72243c9..ca5399a3a 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT nrf5340_application)
 set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
 
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    NRF5340_XXAA
-    NRF5340_XXAA_APPLICATION
-    )
   target_sources(${TARGET} PRIVATE
     ${NRFX_DIR}/drivers/src/nrfx_usbreg.c
     )
diff --git a/hw/bsp/nrf/boards/pca10100/board.cmake b/hw/bsp/nrf/boards/pca10100/board.cmake
new file mode 100644
index 000000000..c30026815
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10100/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52833)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52833_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
new file mode 100644
index 000000000..693d7beed
--- /dev/null
+++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 2b13249f4..6c24d3658 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -33,13 +33,20 @@ function(add_board_target BOARD_TARGET)
     add_library(${BOARD_TARGET} STATIC
       # driver
       ${NRFX_DIR}/drivers/src/nrfx_power.c
+      ${NRFX_DIR}/drivers/src/nrfx_spim.c
       ${NRFX_DIR}/drivers/src/nrfx_uarte.c
       # mcu
       ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c
       )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CONFIG_GPIO_AS_PINRESET
-      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC CONFIG_GPIO_AS_PINRESET)
+
+    if (MCU_VARIANT STREQUAL "nrf52840")
+      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52840_XXAA)
+    elseif (MCU_VARIANT STREQUAL "nrf52833")
+      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52833_XXAA)
+    elseif (MCU_VARIANT STREQUAL "nrf5340_application")
+      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF5340_XXAA NRF5340_XXAA_APPLICATION)
+    endif ()
 
     if (TRACE_ETM STREQUAL "1")
       # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace
@@ -115,6 +122,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
+    #${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index b11c1a09d..782f538fd 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -50,8 +50,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr);
 
 // Task function should be called in main/rtos loop
 TU_ATTR_ALWAYS_INLINE static inline
-void tud_task (void)
-{
+void tud_task (void) {
   tud_task_ext(UINT32_MAX, false);
 }
 
@@ -80,8 +79,7 @@ bool tud_suspended(void);
 
 // Check if device is ready to transfer
 TU_ATTR_ALWAYS_INLINE static inline
-bool tud_ready(void)
-{
+bool tud_ready(void) {
   return tud_mounted() && !tud_suspended();
 }
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 9bcc1c6df..1b5038ef4 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -198,8 +198,7 @@ extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
 
 // Helper to send device attach event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_device_attach(uint8_t rhport, bool in_isr)
-{
+void hcd_event_device_attach(uint8_t rhport, bool in_isr) {
   hcd_event_t event;
   event.rhport              = rhport;
   event.event_id            = HCD_EVENT_DEVICE_ATTACH;
@@ -211,8 +210,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr)
 
 // Helper to send device removal event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_device_remove(uint8_t rhport, bool in_isr)
-{
+void hcd_event_device_remove(uint8_t rhport, bool in_isr) {
   hcd_event_t event;
   event.rhport              = rhport;
   event.event_id            = HCD_EVENT_DEVICE_REMOVE;
@@ -224,10 +222,8 @@ void hcd_event_device_remove(uint8_t rhport, bool in_isr)
 
 // Helper to send USB transfer event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
-{
-  hcd_event_t event =
-  {
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr) {
+  hcd_event_t event = {
     .rhport   = 0, // TODO correct rhport
     .event_id = HCD_EVENT_XFER_COMPLETE,
     .dev_addr = dev_addr,
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
index 590dd9fcf..12d610bd6 100644
--- a/src/portable/template/dcd_template.c
+++ b/src/portable/template/dcd_template.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_NONE
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE
 
 #include "device/dcd.h"
 
@@ -141,4 +141,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   (void) ep_addr;
 }
 
+
+
 #endif
diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c
new file mode 100644
index 000000000..3e3b91558
--- /dev/null
+++ b/src/portable/template/hcd_template.c
@@ -0,0 +1,162 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE
+
+#include "host/hcd.h"
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+
+  return false;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport) {
+  (void) rhport;
+
+  return false;
+}
+
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void) rhport;
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void) rhport;
+
+  return false;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void) rhport;
+
+  return TUSB_SPEED_FULL;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_desc;
+
+  return false;
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  (void) buffer;
+  (void) buflen;
+
+  return false;
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) setup_packet;
+
+  return false;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+#endif
diff --git a/src/tusb.h b/src/tusb.h
index 37a521fa8..d6534ca28 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -64,7 +64,10 @@
   #if CFG_TUH_VENDOR
     #include "class/vendor/vendor_host.h"
   #endif
-
+#else
+  #ifndef tuh_int_handler
+  #define tuh_int_handler(_x)
+  #endif
 #endif
 
 //------------- DEVICE -------------//
@@ -118,6 +121,10 @@
   #if CFG_TUD_BTH
     #include "class/bth/bth_device.h"
   #endif
+#else
+  #ifndef tud_int_handler
+  #define tud_int_handler(_x)
+  #endif
 #endif
 
 
-- 
cgit v1.3.1


From 824e585e2b1f62d1ed03f480439e62e5410636b6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Aug 2023 14:06:57 +0700
Subject: ground works for hcd max3421e

---
 .../boards/feather_nrf52840_express/board.cmake    |   4 +-
 hw/bsp/nrf/boards/feather_nrf52840_express/board.h |   7 +
 hw/bsp/nrf/family.c                                |  80 ++++--
 hw/bsp/nrf/family.cmake                            |   2 +-
 hw/bsp/nrf/nrfx_config.h                           |   5 +-
 src/portable/analog/max3421e/hcd_max3421e.c        | 302 +++++++++++++++++++++
 6 files changed, 369 insertions(+), 31 deletions(-)
 create mode 100644 src/portable/analog/max3421e/hcd_max3421e.c

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
index 0acbecf7a..78ed98225 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -1,6 +1,6 @@
 set(MCU_VARIANT nrf52840)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
-# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+#set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
 endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 8e6ce3230..e19f88a3c 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -45,6 +45,13 @@
 #define UART_RX_PIN     24
 #define UART_TX_PIN     25
 
+// SPI for USB host shield
+#define SPI_SCK_PIN      14
+#define SPI_MOSI_PIN     13
+#define SPI_MISO_PIN     15
+#define SPI_CS_PIN       27
+#define MAX3241E_INT_PIN 26
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 9ca666e36..b6ed15122 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -40,6 +40,7 @@
 #include "hal/nrf_gpio.h"
 #include "drivers/include/nrfx_power.h"
 #include "drivers/include/nrfx_uarte.h"
+#include "drivers/include/nrfx_spim.h"
 
 #ifdef SOFTDEVICE_PRESENT
 #include "nrf_sdm.h"
@@ -54,8 +55,7 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
+void USBD_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -81,6 +81,7 @@ enum {
 #endif
 
 static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
 // tinyusb function that handles power event (detected, ready, removed)
 // We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
@@ -88,13 +89,11 @@ extern void tusb_hal_nrf_power_event(uint32_t event);
 
 
 // nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
-TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
-{
+TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
   tusb_hal_nrf_power_event((uint32_t) event);
 }
 
-void board_init(void)
-{
+void board_init(void) {
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
 
@@ -113,8 +112,7 @@ void board_init(void)
   SysTick_Config(SystemCoreClock/1000);
 
   // UART
-  nrfx_uarte_config_t uart_cfg =
-  {
+  nrfx_uarte_config_t uart_cfg = {
     .pseltxd   = UART_TX_PIN,
     .pselrxd   = UART_RX_PIN,
     .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
@@ -175,45 +173,78 @@ void board_init(void)
   if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
   if ( usb_reg & OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(USB_EVT_READY);
 #endif
+
+  (void) _spi;
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+  // USB host using max3421e usb controller via SPI
+  nrfx_spim_config_t cfg = {
+      .sck_pin        = SPI_SCK_PIN,
+      .mosi_pin       = SPI_MOSI_PIN,
+      .miso_pin       = SPI_MISO_PIN,
+      .ss_pin         = SPI_CS_PIN,
+      .ss_active_high = false,
+      .irq_priority   = 3,
+      .orc            = 0xFF,
+      // default setting 4 Mhz, Mode 0, MSB first
+      .frequency      = NRF_SPIM_FREQ_4M,
+      .mode           = NRF_SPIM_MODE_0,
+      .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
+  };
+
+  // no handler --> blocking
+  nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+#endif
+
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 //  return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
+int board_uart_write(void const *buf, int len) {
+  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
+#endif
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+// API: SPI transfer with MAX3421E, must be implemented by application
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+  (void) rhport;
+  nrfx_spim_xfer_desc_t xfer = {
+      .p_tx_buffer = tx_buf,
+      .tx_length   = tx_len,
+      .p_rx_buffer = rx_buf,
+      .rx_length   = rx_len,
+  };
+  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+}
 #endif
 
 #ifdef SOFTDEVICE_PRESENT
@@ -251,8 +282,7 @@ void SD_EVT_IRQHandler(void)
   }
 }
 
-void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
-{
+void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
   (void) id;
   (void) pc;
   (void) info;
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 6c24d3658..527251e71 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -122,7 +122,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
-    #${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
+    ${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
index 696a3fb04..d0f718c6c 100644
--- a/hw/bsp/nrf/nrfx_config.h
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -9,9 +9,8 @@
 #define NRFX_UARTE_ENABLED   1
 #define NRFX_UARTE0_ENABLED  1
 
-#define NRFX_UARTE1_ENABLED  0
-#define NRFX_UARTE2_ENABLED  0
-#define NRFX_UARTE3_ENABLED  0
+#define NRFX_SPIM_ENABLED    1
+#define NRFX_SPIM0_ENABLED   1
 
 #define NRFX_PRS_ENABLED     0
 #define NRFX_USBREG_ENABLED  1
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
new file mode 100644
index 000000000..7b9d73e4e
--- /dev/null
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -0,0 +1,302 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+
+#include "host/hcd.h"
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Command format is
+// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
+
+enum {
+  CMDBYTE_WRITE = 0x02,
+};
+
+enum {
+  RCVVFIFO_ADDR = 1u  << 3, // 0x08
+  SNDFIFO_ADDR  = 2u  << 3, // 0x10
+  SUDFIFO_ADDR  = 4u  << 3, // 0x20
+  RCVBC_ADDR    = 6u  << 3, // 0x30
+  SNDBC_ADDR    = 7u  << 3, // 0x38
+  USBIRQ_ADDR   = 13u << 3, // 0x68
+  USBIEN_ADDR   = 14u << 3, // 0x70
+  USBCTL_ADDR   = 15u << 3, // 0x78
+  CPUCTL_ADDR   = 16u << 3, // 0x80
+  PINCTL_ADDR   = 17u << 3, // 0x88
+  REVISION_ADDR = 18u << 3, // 0x90
+  HIRQ_ADDR     = 25u << 3, // 0xC8
+  HIEN_ADDR     = 26u << 3, // 0xD0
+  MODE_ADDR     = 27u << 3, // 0xD8
+  PERADDR_ADDR  = 28u << 3, // 0xE0
+  HCTL_ADDR     = 29u << 3, // 0xE8
+  HXFR_ADDR     = 30u << 3, // 0xF0
+  HRSL_ADDR     = 31u << 3, // 0xF8
+};
+
+enum {
+  USBIRQ_OSCOK_IRQ  = 1u << 0,
+  USBIRQ_NOVBUS_IRQ = 1u << 5,
+  USBIRQ_VBUS_IRQ   = 1u << 6,
+};
+
+enum {
+  USBCTL_PWRDOWN = 1u << 4,
+  USBCTL_CHIPRES = 1u << 5,
+};
+
+enum {
+  CPUCTL_IE        = 1u << 0,
+  CPUCTL_PULSEWID0 = 1u << 6,
+  CPUCTL_PULSEWID1 = 1u << 7,
+};
+
+enum {
+  PINCTL_GPXA     = 1u << 0,
+  PINCTL_GPXB     = 1u << 1,
+  PINCTL_POSINT   = 1u << 2,
+  PINCTL_INTLEVEL = 1u << 3,
+  PINCTL_FDUPSPI  = 1u << 4,
+};
+
+enum {
+  HIRQ_BUSEVENT_IRQ = 1u << 0,
+  HIRQ_RWU_IRQ      = 1u << 1,
+  HIRQ_RCVDAV_IRQ   = 1u << 2,
+  HIRQ_SNDBAV_IRQ   = 1u << 3,
+  HIRQ_SUSDN_IRQ    = 1u << 4,
+  HIRQ_CONDET_IRQ   = 1u << 5,
+  HIRQ_FRAME_IRQ    = 1u << 6,
+  HIRQ_HXFRDN_IRQ   = 1u << 7,
+};
+
+enum {
+  MODE_HOST      = 1u << 0,
+  MODE_LOWSPEED  = 1u << 1,
+  MODE_HUBPRE    = 1u << 2,
+  MODE_SOFKAENAB = 1u << 3,
+  MODE_SEPIRQ    = 1u << 4,
+  MODE_DELAYISO  = 1u << 5,
+  MODE_DMPULLDN  = 1u << 6,
+  MODE_DPPULLDN  = 1u << 7,
+};
+
+enum {
+  HCTL_BUSRST    = 1u << 1,
+  HCTL_FRMRST    = 1u << 2,
+  HCTL_SAMPLEBUS = 1u << 3,
+  HCTL_SIGRSM    = 1u << 4,
+  HCTL_RCVTOG0   = 1u << 5,
+  HCTL_RCVTOG1   = 1u << 6,
+  HCTL_SNDTOG0   = 1u << 7,
+  HCTL_SNDTOG1   = 1u << 8,
+};
+
+enum {
+  HXFR_EPNUM_MASK = 0x0f,
+  HXFR_SETUP      = 1u << 4,
+  HXFR_OUT_NIN    = 1u << 5,
+  HXFR_ISO        = 1u << 6,
+  HXFR_HS         = 1u << 7,
+};
+
+enum {
+  HRSL_RESULT_MASK = 0x0f,
+  HRSL_RCVTOGRD    = 1u << 4,
+  HRSL_SNDTOGRD    = 1u << 5,
+  HRSL_KSTATUS     = 1u << 6,
+  HRSL_JSTATUS     = 1u << 7,
+};
+
+// API: SPI transfer with MAX3421E, must be implemented by application
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
+
+// return HIRQ register since we are in full-duplex mode
+static uint8_t reg_write(uint8_t reg, uint8_t data) {
+  uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
+  uint8_t rx_buf[2] = {0, 0};
+  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  return rx_buf[0];
+}
+
+static uint8_t reg_read(uint8_t reg) {
+  uint8_t tx_buf[2] = {reg, 0};
+  uint8_t rx_buf[2] = {0, 0};
+  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
+}
+
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+
+  return false;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport) {
+  (void) rhport;
+
+  // full duplex, interrupt level (should be configurable)
+  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
+
+  // reset
+  reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
+  reg_write(USBCTL_ADDR, 0);
+  while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
+    // wait for oscillator to stabilize
+  }
+
+  // Mode: Host and DP/DM pull down
+  reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
+
+  // Connection detection
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */);
+
+  return false;
+}
+
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void) rhport;
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void) rhport;
+
+  return false;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void) rhport;
+
+  return TUSB_SPEED_FULL;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_desc;
+
+  return false;
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  (void) buffer;
+  (void) buflen;
+
+  return false;
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) setup_packet;
+
+  return false;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+#endif
-- 
cgit v1.3.1


From cacc96b25dc04865389357467b7a6d92d040ef36 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Aug 2023 17:39:10 +0700
Subject: adding connection event handling, add nrf gpio interrupt for max2341e
 interrupt pin

---
 hw/bsp/nrf/boards/feather_nrf52840_express/board.h |  2 +-
 hw/bsp/nrf/family.c                                | 55 +++++++++++-----
 hw/bsp/nrf/family.cmake                            |  2 +
 hw/bsp/nrf/nrfx_config.h                           |  2 +-
 hw/bsp/nrf/nrfx_glue.h                             | 69 ++++++++++++++++++++
 src/portable/analog/max3421e/hcd_max3421e.c        | 76 +++++++++++++++++++++-
 6 files changed, 184 insertions(+), 22 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index e19f88a3c..7f042142e 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -50,7 +50,7 @@
 #define SPI_MOSI_PIN     13
 #define SPI_MISO_PIN     15
 #define SPI_CS_PIN       27
-#define MAX3241E_INT_PIN 26
+#define MAX3241E_INTR_PIN 26
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index b6ed15122..e58ee845b 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -38,6 +38,7 @@
 
 #include "nrfx.h"
 #include "hal/nrf_gpio.h"
+#include "drivers/include/nrfx_gpiote.h"
 #include "drivers/include/nrfx_power.h"
 #include "drivers/include/nrfx_uarte.h"
 #include "drivers/include/nrfx_spim.h"
@@ -81,18 +82,45 @@ enum {
 #endif
 
 static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
-static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
 // tinyusb function that handles power event (detected, ready, removed)
 // We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
 extern void tusb_hal_nrf_power_event(uint32_t event);
 
-
 // nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
 TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
   tusb_hal_nrf_power_event((uint32_t) event);
 }
 
+//------------- Host using MAX2341E -------------//
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
+
+void max2342e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+  if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
+
+  tuh_int_handler(1);
+}
+
+// API: SPI transfer with MAX3421E, must be implemented by application
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+  (void) rhport;
+  nrfx_spim_xfer_desc_t xfer = {
+      .p_tx_buffer = tx_buf,
+      .tx_length   = tx_len,
+      .p_rx_buffer = rx_buf,
+      .rx_length   = rx_len,
+  };
+  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+}
+
+#endif
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 void board_init(void) {
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
@@ -174,7 +202,6 @@ void board_init(void) {
   if ( usb_reg & OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(USB_EVT_READY);
 #endif
 
-  (void) _spi;
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
@@ -193,6 +220,14 @@ void board_init(void) {
 
   // no handler --> blocking
   nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+
+  // max3421e interrupt pin
+  nrfx_gpiote_init(1);
+  nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
+  in_config.pull = NRF_GPIO_PIN_PULLUP;
+
+  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max2342e_int_handler);
+  nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true);
 #endif
 
 }
@@ -233,20 +268,6 @@ uint32_t board_millis(void) {
 
 #endif
 
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
-// API: SPI transfer with MAX3421E, must be implemented by application
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
-  (void) rhport;
-  nrfx_spim_xfer_desc_t xfer = {
-      .p_tx_buffer = tx_buf,
-      .tx_length   = tx_len,
-      .p_rx_buffer = rx_buf,
-      .rx_length   = rx_len,
-  };
-  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
-}
-#endif
-
 #ifdef SOFTDEVICE_PRESENT
 // process SOC event from SD
 uint32_t proc_soc(void)
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 527251e71..8bf7bcb52 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -32,6 +32,8 @@ function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
     add_library(${BOARD_TARGET} STATIC
       # driver
+      ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c
+      ${NRFX_DIR}/drivers/src/nrfx_gpiote.c
       ${NRFX_DIR}/drivers/src/nrfx_power.c
       ${NRFX_DIR}/drivers/src/nrfx_spim.c
       ${NRFX_DIR}/drivers/src/nrfx_uarte.c
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
index d0f718c6c..e3d0ea91b 100644
--- a/hw/bsp/nrf/nrfx_config.h
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -5,6 +5,7 @@
 #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  7
 
 #define NRFX_CLOCK_ENABLED   0
+#define NRFX_GPIOTE_ENABLED  1
 
 #define NRFX_UARTE_ENABLED   1
 #define NRFX_UARTE0_ENABLED  1
@@ -41,5 +42,4 @@
     #error "Unknown device."
 #endif
 
-
 #endif // NRFX_CONFIG_H__
diff --git a/hw/bsp/nrf/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h
index cdf49b4ab..ef756c670 100644
--- a/hw/bsp/nrf/nrfx_glue.h
+++ b/hw/bsp/nrf/nrfx_glue.h
@@ -220,6 +220,75 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number)
 
 /** @} */
 
+//------------------------------------------------------------------------------
+
+#include <soc/nrfx_atomic.h>
+
+/**
+ * @brief Atomic 32 bit unsigned type.
+ */
+#define nrfx_atomic_t               nrfx_atomic_u32_t
+
+/**
+ * @brief Stores value to an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value to store.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value)
+
+/**
+ * @brief Performs logical OR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of OR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value)   nrfx_atomic_u32_fetch_or(p_data, value)
+
+/**
+ * @brief Performs logical AND operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of AND operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value)   nrfx_atomic_u32_fetch_and(p_data, value)
+
+/**
+ * @brief Performs logical XOR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of XOR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value)   nrfx_atomic_u32_fetch_xor(p_data, value)
+
+/**
+ * @brief Performs logical ADD operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of ADD operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value)   nrfx_atomic_u32_fetch_add(p_data, value)
+
+/**
+ * @brief Performs logical SUB operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of SUB operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value)   nrfx_atomic_u32_fetch_sub(p_data, value)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
index 7b9d73e4e..a89581b9c 100644
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -136,6 +136,20 @@ enum {
   HRSL_JSTATUS     = 1u << 7,
 };
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+//typedef struct {
+//  uint8_t mode
+//} max2341e_data_t;
+//
+//max2341e_data_t max2341e_data;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 // API: SPI transfer with MAX3421E, must be implemented by application
 bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
 
@@ -144,6 +158,7 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) {
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
   tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
   return rx_buf[0];
 }
 
@@ -167,6 +182,48 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   return false;
 }
 
+tusb_speed_t handle_connect_irq(uint8_t rhport) {
+  (void) rhport;
+
+  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
+
+  tusb_speed_t speed;
+  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+
+  switch(jk) {
+    case 0x00:
+      // SEO is disconnected
+      speed = TUSB_SPEED_INVALID;
+      break;
+
+    case (HRSL_JSTATUS | HRSL_KSTATUS):
+      // SE1 is illegal
+      speed = TUSB_SPEED_INVALID;
+      break;
+
+    default: {
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      uint8_t const mode = reg_read(MODE_ADDR);
+      uint8_t const ls_bit = mode & MODE_LOWSPEED;
+
+      if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
+        speed = TUSB_SPEED_LOW;
+        new_mode |= MODE_LOWSPEED;
+      } else {
+        speed =  TUSB_SPEED_FULL;
+      }
+
+      new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device
+
+      break;
+    }
+  }
+
+  reg_write(MODE_ADDR, new_mode);
+  return speed;
+}
+
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
@@ -184,15 +241,28 @@ bool hcd_init(uint8_t rhport) {
   // Mode: Host and DP/DM pull down
   reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
-  // Connection detection
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */);
+  // Enable Connection IRQ
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ);
 
-  return false;
+  // Note: if device is already connected, CONDET IRQ may not be triggered. We need to detect it by sampling bus signal
+  reg_write(HCTL_ADDR, HCTL_SAMPLEBUS);
+  while( !(reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS) ) {}
+
+  handle_connect_irq(rhport);
+  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
+
+  // Enable Interrupt pin
+  reg_write(CPUCTL_ADDR, CPUCTL_IE);
+
+  return true;
 }
 
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport) {
   (void) rhport;
+
+  uint8_t hirq = reg_read(HIRQ_ADDR);
+  TU_LOG3_INT(hirq);
 }
 
 // Enable USB interrupt
-- 
cgit v1.3.1


From fca08c939c0d04b9485413166b69f8abac6fb083 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Sun, 20 Aug 2023 18:22:07 +0200
Subject: files taken from yapicoprobe

---
 src/class/net/ncm.h        |  106 +++-
 src/class/net/ncm_device.c | 1281 +++++++++++++++++++++++++++++++-------------
 src/class/net/net_device.h |   24 +-
 3 files changed, 997 insertions(+), 414 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h
index 96ba11fbc..313237747 100644
--- a/src/class/net/ncm.h
+++ b/src/class/net/ncm.h
@@ -30,10 +30,47 @@
 
 #include "common/tusb_common.h"
 
-#ifdef __cplusplus
- extern "C" {
+
+#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
+    /// must be >> MTU
+    #define CFG_TUD_NCM_IN_NTB_MAX_SIZE        3200
+#endif
+#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
+    /// must be >> MTU
+    #define CFG_TUD_NCM_OUT_NTB_MAX_SIZE       3200
+#endif
+
+#ifndef CFG_TUD_NCM_OUT_NTB_N
+    /// number of ntb buffers for reception side
+    /// 1  - good performance
+    /// 2  - up to 30% more performance with iperf with small packets
+    /// >2 - no performance gain
+    #define CFG_TUD_NCM_OUT_NTB_N              2
+#endif
+
+#ifndef CFG_TUD_NCM_IN_NTB_N
+    /// number of ntb buffers for transmission side
+    /// 1 - good performance but SystemView shows lost events (on load test)
+    /// 2 - up to 50% more performance with iperf with small packets, "tud_network_can_xmit: request blocked"
+    ///     happens from time to time with SystemView
+    /// 3 - "tud_network_can_xmit: request blocked" never happens
+    /// >2 - no performance gain
+    #define CFG_TUD_NCM_IN_NTB_N               3
+#endif
+
+#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+    /// this is for the transmission size for allocation of \a ndp16_datagram_t
+    #define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB  8
+#endif
+
+#ifndef CFG_TUD_NCM_ALIGNMENT
+    #define CFG_TUD_NCM_ALIGNMENT              4
+#endif
+#if (CFG_TUD_NCM_ALIGNMENT != 4)
+    #error "CFG_TUD_NCM_ALIGNMENT must be 4, otherwise the headers and start of datagrams have to be aligned (which they are currently not)"
 #endif
 
+
 // Table 4.3 Data Class Interface Protocol Codes
 typedef enum
 {
@@ -62,8 +99,67 @@ typedef enum
   NCM_SET_CRC_MODE                                 = 0x8A,
 } ncm_request_code_t;
 
-#ifdef __cplusplus
- }
-#endif
+
+#define NTH16_SIGNATURE      0x484D434E
+#define NDP16_SIGNATURE_NCM0 0x304D434E
+#define NDP16_SIGNATURE_NCM1 0x314D434E
+
+typedef struct TU_ATTR_PACKED {
+    uint16_t wLength;
+    uint16_t bmNtbFormatsSupported;
+    uint32_t dwNtbInMaxSize;
+    uint16_t wNdbInDivisor;
+    uint16_t wNdbInPayloadRemainder;
+    uint16_t wNdbInAlignment;
+    uint16_t wReserved;
+    uint32_t dwNtbOutMaxSize;
+    uint16_t wNdbOutDivisor;
+    uint16_t wNdbOutPayloadRemainder;
+    uint16_t wNdbOutAlignment;
+    uint16_t wNtbOutMaxDatagrams;
+} ntb_parameters_t;
+
+typedef struct TU_ATTR_PACKED {
+    uint32_t dwSignature;
+    uint16_t wHeaderLength;
+    uint16_t wSequence;
+    uint16_t wBlockLength;
+    uint16_t wNdpIndex;
+} nth16_t;
+
+typedef struct TU_ATTR_PACKED {
+    uint16_t wDatagramIndex;
+    uint16_t wDatagramLength;
+} ndp16_datagram_t;
+
+typedef struct TU_ATTR_PACKED {
+    uint32_t dwSignature;
+    uint16_t wLength;
+    uint16_t wNextNdpIndex;
+    //ndp16_datagram_t datagram[];
+} ndp16_t;
+
+typedef union TU_ATTR_PACKED {
+    struct {
+        nth16_t          nth;
+        ndp16_t          ndp;
+        ndp16_datagram_t ndp_datagram[CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1];
+    };
+    uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
+} xmit_ntb_t;
+
+typedef union TU_ATTR_PACKED {
+    struct {
+        nth16_t nth;
+        // only the header is at a guaranteed position
+    };
+    uint8_t data[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+} recv_ntb_t;
+
+struct ncm_notify_t {
+    tusb_control_request_t header;
+    uint32_t               downlink, uplink;
+};
+
 
 #endif
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 226c42c4e..f7a236e69 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -1,9 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2020 Jacob Berg Potter
- * Copyright (c) 2020 Peter Lawrence
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 Hardy Griech
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -26,493 +24,1004 @@
  * This file is part of the TinyUSB stack.
  */
 
+/**
+ * Small Glossary (from the spec)
+ * --------------
+ * Datagram - A collection of bytes forming a single item of information, passed as a unit from source to destination.
+ * NCM      - Network Control Model
+ * NDP      - NCM Datagram Pointer: NTB structure that delineates Datagrams (typically Ethernet frames) within an NTB
+ * NTB      - NCM Transfer Block: a data structure for efficient USB encapsulation of one or more datagrams
+ *            Each NTB is designed to be a single USB transfer
+ * NTH      - NTB Header: a data structure at the front of each NTB, which provides the information needed to validate
+ *            the NTB and begin decoding
+ *
+ * Some explanations
+ * -----------------
+ * - rhport        is the USB port of the device, in most cases "0"
+ * - itf_data_alt  if != 0 -> data xmit/recv are allowed (see spec)
+ * - ep_in         IN endpoints take data from the device intended to go in to the host (the device transmits)
+ * - ep_out        OUT endpoints send data out of the host to the device (the device receives)
+ */
+
 #include "tusb_option.h"
 
-#if ( CFG_TUD_ENABLED && CFG_TUD_NCM )
+#if ECLIPSE_GUI || ( CFG_TUD_ENABLED && CFG_TUD_NCM )
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
+
 #include "net_device.h"
+#include "ncm.h"
+
+
+#if !defined(tu_static)  ||  ECLIPSE_GUI
+    // TinyUSB <=0.15.0 does not know "tu_static"
+    #define tu_static static
+#endif
 
-// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
-#ifndef CFG_TUD_NCM_LOG_LEVEL
-  #define CFG_TUD_NCM_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#if 0
+    #define DEBUG_OUT(...)  printf(__VA_ARGS__)
+    #define DEBUG_OUT_ENABLED
+#else
+    #define DEBUG_OUT(...)
 #endif
 
-#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_NCM_LOG_LEVEL, __VA_ARGS__)
+#if 0
+    #define INFO_OUT(...)   printf(__VA_ARGS__)
+#else
+    #define INFO_OUT(...)
+#endif
+
+#if 1
+    #define ERROR_OUT(...)  printf(__VA_ARGS__)
+#else
+    #define ERROR_OUT(...)
+#endif
+
+// calculate alignment of xmit datagrams within an NTB
+#define XMIT_ALIGN_OFFSET(x)   ((CFG_TUD_NCM_ALIGNMENT - ((x) & (CFG_TUD_NCM_ALIGNMENT - 1))) & (CFG_TUD_NCM_ALIGNMENT - 1))
+
+//-----------------------------------------------------------------------------
+//
+// Module global things
+//
+#define XMIT_NTB_N         CFG_TUD_NCM_IN_NTB_N
+#define RECV_NTB_N         CFG_TUD_NCM_OUT_NTB_N
+
+typedef struct {
+    // general
+    uint8_t     ep_in;                             //!< endpoint for outgoing datagrams (naming is a little bit confusing)
+    uint8_t     ep_out;                            //!< endpoint for incoming datagrams (naming is a little bit confusing)
+    uint8_t     ep_notif;                          //!< endpoint for notifications
+    uint8_t     itf_num;                           //!< interface number
+    uint8_t     itf_data_alt;                      //!< ==0 -> no endpoints, i.e. no network traffic, ==1 -> normal operation with two endpoints (spec, chapter 5.3)
+    uint8_t     rhport;                            //!< storage of \a rhport because some callbacks are done without it
+
+    // recv handling
+    recv_ntb_t  recv_ntb[RECV_NTB_N];              //!< actual recv NTBs
+    recv_ntb_t *recv_free_ntb[RECV_NTB_N];         //!< free list of recv NTBs
+    recv_ntb_t *recv_ready_ntb[RECV_NTB_N];        //!< NTBs waiting for transmission to glue logic
+    recv_ntb_t *recv_tinyusb_ntb;                  //!< buffer for the running transfer TinyUSB -> driver
+    recv_ntb_t *recv_glue_ntb;                     //!< buffer for the running transfer driver -> glue logic
+    uint16_t               recv_glue_ntb_datagram_ndx;        //!< index into \a recv_glue_ntb_datagram
+
+    // xmit handling
+    xmit_ntb_t  xmit_ntb[XMIT_NTB_N];              //!< actual xmit NTBs
+    xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N];         //!< free list of xmit NTBs
+    xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N];        //!< NTBs waiting for transmission to TinyUSB
+    xmit_ntb_t *xmit_tinyusb_ntb;                  //!< buffer for the running transfer driver -> TinyUSB
+    xmit_ntb_t *xmit_glue_ntb;                     //!< buffer for the running transfer glue logic -> driver
+    uint16_t    xmit_sequence;                     //!< NTB sequence counter
+    uint16_t    xmit_glue_ntb_datagram_ndx;        //!< index into \a xmit_glue_ntb_datagram
+
+    // notification handling
+    enum {
+        NOTIFICATION_SPEED,
+        NOTIFICATION_CONNECTED,
+        NOTIFICATION_DONE
+    } notification_xmit_state;                     //!< state of notification transmission
+    bool        notification_xmit_is_running;      //!< notification is currently transmitted
+} ncm_interface_t;
+
 
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static ncm_interface_t ncm_interface;
 
-#define NTH16_SIGNATURE      0x484D434E
-#define NDP16_SIGNATURE_NCM0 0x304D434E
-#define NDP16_SIGNATURE_NCM1 0x314D434E
 
-typedef struct TU_ATTR_PACKED
+/**
+ * This is the NTB parameter structure
+ *
+ * \attention
+ *     We are lucky, that byte order is correct
+ */
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
+        .wLength                 = sizeof(ntb_parameters_t),
+        .bmNtbFormatsSupported   = 0x01,                                 // 16-bit NTB supported
+        .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
+        .wNdbInDivisor           = 4,
+        .wNdbInPayloadRemainder  = 0,
+        .wNdbInAlignment         = CFG_TUD_NCM_ALIGNMENT,
+        .wReserved               = 0,
+        .dwNtbOutMaxSize         = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
+        .wNdbOutDivisor          = 4,
+        .wNdbOutPayloadRemainder = 0,
+        .wNdbOutAlignment        = CFG_TUD_NCM_ALIGNMENT,
+        .wNtbOutMaxDatagrams     = 6                                     // 0=no limit
+};
+
+// Some confusing remarks about wNtbOutMaxDatagrams...
+//      ==1 -> SystemView packets/s goes up to 2000 and events are lost during startup
+//      ==0 -> SystemView runs fine, iperf shows in wireshark a lot of error
+//      ==6 -> SystemView runs fine, iperf also
+//      >6  -> iperf starts to show errors
+//      -> 6 seems to be the best value.  Why?  Don't know, perhaps only on my system?
+//      switch \a INFO_OUT on to see interesting values for this.
+//
+//      iperf:    for MSS in 100 200 400 800 1200 1450 1500; do iperf -c 192.168.14.1 -e -i 1 -M $MSS -l 8192 -P 1; sleep 2; done
+//      sysview:  SYSTICKS_PER_SEC=35000, IDLE_US=1000, PRINT_MOD=1000
+//
+
+//-----------------------------------------------------------------------------
+//
+// everything about notifications
+//
+tu_static struct ncm_notify_t ncm_notify_connected = {
+        .header = {
+                .bmRequestType_bit = {
+                        .recipient = TUSB_REQ_RCPT_INTERFACE,
+                        .type      = TUSB_REQ_TYPE_CLASS,
+                        .direction = TUSB_DIR_IN
+                },
+                .bRequest = CDC_NOTIF_NETWORK_CONNECTION,
+                .wValue   = 1 /* Connected */,
+                .wLength  = 0,
+        },
+};
+
+tu_static struct ncm_notify_t ncm_notify_speed_change = {
+        .header = {
+                .bmRequestType_bit = {
+                        .recipient = TUSB_REQ_RCPT_INTERFACE,
+                        .type      = TUSB_REQ_TYPE_CLASS,
+                        .direction = TUSB_DIR_IN
+                },
+                .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
+                .wLength  = 8,
+        },
+        .downlink = 1000000,
+        .uplink   = 1000000,
+};
+
+
+
+static void notification_xmit(uint8_t rhport, bool force_next)
+/**
+ * Transmit next notification to the host (if appropriate).
+ * Notifications are transferred to the host once during connection setup.
+ */
 {
-  uint16_t wLength;
-  uint16_t bmNtbFormatsSupported;
-  uint32_t dwNtbInMaxSize;
-  uint16_t wNdbInDivisor;
-  uint16_t wNdbInPayloadRemainder;
-  uint16_t wNdbInAlignment;
-  uint16_t wReserved;
-  uint32_t dwNtbOutMaxSize;
-  uint16_t wNdbOutDivisor;
-  uint16_t wNdbOutPayloadRemainder;
-  uint16_t wNdbOutAlignment;
-  uint16_t wNtbOutMaxDatagrams;
-} ntb_parameters_t;
-
-typedef struct TU_ATTR_PACKED
+    DEBUG_OUT("notification_xmit(%d, %d) - %d %d\n", force_next, rhport, ncm_interface.notification_xmit_state, ncm_interface.notification_xmit_is_running);
+
+    if ( !force_next  &&  ncm_interface.notification_xmit_is_running) {
+        return;
+    }
+
+    if (ncm_interface.notification_xmit_state == NOTIFICATION_SPEED) {
+        DEBUG_OUT("  NOTIFICATION_SPEED\n");
+        ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
+        usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t*) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
+        ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED;
+        ncm_interface.notification_xmit_is_running = true;
+    }
+    else if (ncm_interface.notification_xmit_state == NOTIFICATION_CONNECTED) {
+        DEBUG_OUT("  NOTIFICATION_CONNECTED\n");
+        ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
+        usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t*) &ncm_notify_connected, sizeof(ncm_notify_connected));
+        ncm_interface.notification_xmit_state = NOTIFICATION_DONE;
+        ncm_interface.notification_xmit_is_running = true;
+    }
+    else {
+        DEBUG_OUT("  NOTIFICATION_FINISHED\n");
+    }
+}   // notification_xmit
+
+
+//-----------------------------------------------------------------------------
+//
+// everything about packet transmission (driver -> TinyUSB)
+//
+
+
+static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb)
+/**
+ * Put NTB into the transmitter free list.
+ */
 {
-  uint32_t dwSignature;
-  uint16_t wHeaderLength;
-  uint16_t wSequence;
-  uint16_t wBlockLength;
-  uint16_t wNdpIndex;
-} nth16_t;
-
-typedef struct TU_ATTR_PACKED
+    DEBUG_OUT("xmit_put_ntb_into_free_list() - %p\n", ncm_interface.xmit_tinyusb_ntb);
+
+    if (free_ntb == NULL) {
+        // can happen due to ZLPs
+        return;
+    }
+
+    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
+        if (ncm_interface.xmit_free_ntb[i] == NULL) {
+            ncm_interface.xmit_free_ntb[i] = free_ntb;
+            return;
+        }
+    }
+    ERROR_OUT("xmit_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
+}   // xmit_put_ntb_into_free_list
+
+
+
+static xmit_ntb_t *xmit_get_free_ntb(void)
+/**
+ * Get an NTB from the free list
+ */
 {
-  uint16_t wDatagramIndex;
-  uint16_t wDatagramLength;
-} ndp16_datagram_t;
+    DEBUG_OUT("xmit_get_free_ntb()\n");
+
+    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
+        if (ncm_interface.xmit_free_ntb[i] != NULL) {
+            xmit_ntb_t *free = ncm_interface.xmit_free_ntb[i];
+            ncm_interface.xmit_free_ntb[i] = NULL;
+            return free;
+        }
+    }
+    return NULL;
+}   // xmit_get_free_ntb
 
-typedef struct TU_ATTR_PACKED
+
+
+static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb)
+/**
+ * Put a filled NTB into the ready list
+ */
 {
-  uint32_t dwSignature;
-  uint16_t wLength;
-  uint16_t wNextNdpIndex;
-  ndp16_datagram_t datagram[];
-} ndp16_t;
-
-typedef union TU_ATTR_PACKED {
-  struct {
-    nth16_t nth;
-    ndp16_t ndp;
-  };
-  uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
-} transmit_ntb_t;
-
-struct ecm_notify_struct
+    INFO_OUT("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->len);
+
+    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
+        if (ncm_interface.xmit_ready_ntb[i] == NULL) {
+            ncm_interface.xmit_ready_ntb[i] = ready_ntb;
+            return;
+        }
+    }
+    ERROR_OUT("xmit_put_ntb_into_ready_list: ready list full\n");  // this should not happen
+}   // xmit_put_ntb_into_ready_list
+
+
+
+static xmit_ntb_t *xmit_get_next_ready_ntb(void)
+/**
+ * Get the next NTB from the ready list (and remove it from the list).
+ * If the ready list is empty, return NULL.
+ */
 {
-  tusb_control_request_t header;
-  uint32_t downlink, uplink;
-};
+    xmit_ntb_t *r = NULL;
 
-typedef struct
+    r = ncm_interface.xmit_ready_ntb[0];
+    memmove(ncm_interface.xmit_ready_ntb + 0, ncm_interface.xmit_ready_ntb + 1, sizeof(ncm_interface.xmit_ready_ntb) - sizeof(ncm_interface.xmit_ready_ntb[0]));
+
+    DEBUG_OUT("recv_get_next_ready_ntb: %p\n", r);
+    return r;
+}   // xmit_get_next_ready_ntb
+
+
+
+static bool xmit_insert_required_zlp(uint8_t rhport, uint16_t xferred_bytes)
+/**
+ * Transmit a ZLP if required
+ *
+ * \note
+ *    Insertion of the ZLPs is a little bit different then described in the spec.
+ *    But the below implementation actually works.  Don't know if this is a spec
+ *    or TinyUSB issue.
+ *
+ * \pre
+ *    This must be called from netd_xfer_cb() so that ep_in is ready
+ */
 {
-  uint8_t itf_num;      // Index number of Management Interface, +1 for Data Interface
-  uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active
+    DEBUG_OUT("xmit_insert_required_zlp(%d,%d)\n", rhport, xferred_bytes);
 
-  uint8_t ep_notif;
-  uint8_t ep_in;
-  uint8_t ep_out;
+    if (xferred_bytes == 0  ||  xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE != 0) {
+        return false;
+    }
 
-  const ndp16_t *ndp;
-  uint8_t num_datagrams, current_datagram_index;
+    TU_ASSERT(ncm_interface.itf_data_alt == 1, false);
+    TU_ASSERT( !usbd_edpt_busy(rhport, ncm_interface.ep_in), false);
 
-  enum {
-    REPORT_SPEED,
-    REPORT_CONNECTED,
-    REPORT_DONE
-  } report_state;
-  bool report_pending;
+    INFO_OUT("xmit_insert_required_zlp! (%u)\n", (unsigned)xferred_bytes);
 
-  uint8_t  current_ntb;           // Index in transmit_ntb[] that is currently being filled with datagrams
-  uint8_t  datagram_count;        // Number of datagrams in transmit_ntb[current_ntb]
-  uint16_t next_datagram_offset;  // Offset in transmit_ntb[current_ntb].data to place the next datagram
-  uint16_t ntb_in_size;           // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE
-  uint8_t  max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+    // start transmission of the ZLP
+    usbd_edpt_xfer(rhport, ncm_interface.ep_in, NULL, 0);
 
-  uint16_t nth_sequence;          // Sequence number counter for transmitted NTBs
+    return true;
+}   // xmit_insert_required_zlp
 
-  bool transferring;
 
-} ncm_interface_t;
 
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
-    .wLength                 = sizeof(ntb_parameters_t),
-    .bmNtbFormatsSupported   = 0x01,
-    .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
-    .wNdbInDivisor           = 4,
-    .wNdbInPayloadRemainder  = 0,
-    .wNdbInAlignment         = CFG_TUD_NCM_ALIGNMENT,
-    .wReserved               = 0,
-    .dwNtbOutMaxSize         = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
-    .wNdbOutDivisor          = 4,
-    .wNdbOutPayloadRemainder = 0,
-    .wNdbOutAlignment        = CFG_TUD_NCM_ALIGNMENT,
-    .wNtbOutMaxDatagrams     = 0
-};
+static void xmit_start_if_possible(uint8_t rhport)
+/**
+ * Start transmission if it there is a waiting packet and if can be done from interface side.
+ */
+{
+    DEBUG_OUT("xmit_start_if_possible()\n");
 
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2];
+    if (ncm_interface.xmit_tinyusb_ntb != NULL) {
+        DEBUG_OUT("  !xmit_start_if_possible 1\n");
+        return;
+    }
+    if (ncm_interface.itf_data_alt != 1) {
+        ERROR_OUT("  !xmit_start_if_possible 2\n");
+        return;
+    }
+    if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
+        INFO_OUT("  !xmit_start_if_possible 3\n");
+        return;
+    }
 
-CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+    ncm_interface.xmit_tinyusb_ntb = xmit_get_next_ready_ntb();
+    if (ncm_interface.xmit_tinyusb_ntb == NULL) {
+        if (ncm_interface.xmit_glue_ntb == NULL  ||  ncm_interface.xmit_glue_ntb_datagram_ndx == 0) {
+            // -> really nothing is waiting
+            return;
+        }
+        ncm_interface.xmit_tinyusb_ntb = ncm_interface.xmit_glue_ntb;
+        ncm_interface.xmit_glue_ntb = NULL;
+    }
+
+#if DEBUG_OUT_ENABLED
+    {
+        uint16_t len = ncm_interface.xmit_tinyusb_ntb->ntb.nth.wBlockLength;
+        DEBUG_OUT(" %d\n", len);
+        for (int i = 0;  i < len;  ++i) {
+            DEBUG_OUT(" %02x", ncm_interface.xmit_tinyusb_ntb->data[i]);
+        }
+        DEBUG_OUT("\n");
+    }
+#endif
+
+    if (ncm_interface.xmit_glue_ntb_datagram_ndx != 1) {
+        DEBUG_OUT(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->len, ncm_interface.xmit_glue_ntb_datagram_ndx);
+    }
 
-tu_static ncm_interface_t ncm_interface;
+    // Kick off an endpoint transfer
+    usbd_edpt_xfer(0, ncm_interface.ep_in, ncm_interface.xmit_tinyusb_ntb->data, ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength);
+}   // xmit_start_if_possible
 
-/*
- * Set up the NTB state in ncm_interface to be ready to add datagrams.
+
+
+static bool xmit_requested_datagram_fits_into_current_ntb(uint16_t datagram_size)
+/**
+ * check if a new datagram fits into the current NTB
  */
-static void ncm_prepare_for_tx(void) {
-  ncm_interface.datagram_count = 0;
-  // datagrams start after all the headers
-  ncm_interface.next_datagram_offset = sizeof(nth16_t) + sizeof(ndp16_t)
-      + ((CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1) * sizeof(ndp16_datagram_t));
-}
+{
+    DEBUG_OUT("xmit_requested_datagram_fits_into_current_ntb(%d) - %p %p\n", datagram_size, ncm_interface.xmit_tinyusb_ntb, ncm_interface.xmit_glue_ntb);
 
-/*
- * If not already transmitting, start sending the current NTB to the host and swap buffers
- * to start filling the other one with datagrams.
+    if (ncm_interface.xmit_glue_ntb == NULL) {
+        return false;
+    }
+    if (ncm_interface.xmit_glue_ntb_datagram_ndx >= CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB) {
+        return false;
+    }
+    if (ncm_interface.xmit_glue_ntb->nth.wBlockLength + datagram_size + XMIT_ALIGN_OFFSET(datagram_size) > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+        return false;
+    }
+    return true;
+}   // xmit_requested_datagram_fits_into_current_ntb
+
+
+
+static bool xmit_setup_next_glue_ntb(void)
+/**
+ * Setup an NTB for the glue logic
  */
-static void ncm_start_tx(void) {
-  if (ncm_interface.transferring) {
-    return;
-  }
-
-  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
-  size_t ntb_length = ncm_interface.next_datagram_offset;
-
-  // Fill in NTB header
-  ntb->nth.dwSignature = NTH16_SIGNATURE;
-  ntb->nth.wHeaderLength = sizeof(nth16_t);
-  ntb->nth.wSequence = ncm_interface.nth_sequence++;
-  ntb->nth.wBlockLength = ntb_length;
-  ntb->nth.wNdpIndex = sizeof(nth16_t);
-
-  // Fill in NDP16 header and terminator
-  ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
-  ntb->ndp.wLength = sizeof(ndp16_t) + (ncm_interface.datagram_count + 1) * sizeof(ndp16_datagram_t);
-  ntb->ndp.wNextNdpIndex = 0;
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = 0;
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0;
-
-  // Kick off an endpoint transfer
-  usbd_edpt_xfer(0, ncm_interface.ep_in, ntb->data, ntb_length);
-  ncm_interface.transferring = true;
-
-  // Swap to the other NTB and clear it out
-  ncm_interface.current_ntb = 1 - ncm_interface.current_ntb;
-  ncm_prepare_for_tx();
-}
-
-tu_static struct ecm_notify_struct ncm_notify_connected =
 {
-    .header = {
-        .bmRequestType_bit = {
-          .recipient = TUSB_REQ_RCPT_INTERFACE,
-          .type      = TUSB_REQ_TYPE_CLASS,
-          .direction = TUSB_DIR_IN
-        },
-        .bRequest      = CDC_NOTIF_NETWORK_CONNECTION,
-        .wValue        = 1 /* Connected */,
-        .wLength       = 0,
-    },
-};
+    DEBUG_OUT("xmit_setup_next_glue_ntb - %p\n", ncm_interface.xmit_glue_ntb);
+
+    if (ncm_interface.xmit_glue_ntb != NULL) {
+        // put NTB into waiting list (the new datagram did not fit in)
+        xmit_put_ntb_into_ready_list(ncm_interface.xmit_glue_ntb);
+    }
+
+    ncm_interface.xmit_glue_ntb = xmit_get_free_ntb();              // get next buffer (if any)
+    if (ncm_interface.xmit_glue_ntb == NULL) {
+        DEBUG_OUT("  xmit_setup_next_glue_ntb - nothing free\n");   // should happen rarely
+        return false;
+    }
+
+    ncm_interface.xmit_glue_ntb_datagram_ndx = 0;
+
+    xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
+
+    // Fill in NTB header
+    ntb->nth.dwSignature   = NTH16_SIGNATURE;
+    ntb->nth.wHeaderLength = sizeof(ntb->nth);
+    ntb->nth.wSequence     = ncm_interface.xmit_sequence++;
+    ntb->nth.wBlockLength  = sizeof(ntb->nth) + sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+    ntb->nth.wNdpIndex     = sizeof(ntb->nth);
+
+    // Fill in NDP16 header and terminator
+    ntb->ndp.dwSignature   = NDP16_SIGNATURE_NCM0;
+    ntb->ndp.wLength       = sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+    ntb->ndp.wNextNdpIndex = 0;
+
+    memset(ntb->ndp_datagram, 0, sizeof(ntb->ndp_datagram));
+    return true;
+}   // xmit_setup_next_glue_ntb
+
 
-tu_static struct ecm_notify_struct ncm_notify_speed_change =
+//-----------------------------------------------------------------------------
+//
+// all the recv_*() stuff (TinyUSB -> driver -> glue logic)
+//
+
+
+static recv_ntb_t *recv_get_free_ntb(void)
+/**
+ * Return pointer to an available receive buffer or NULL.
+ * Returned buffer (if any) has the size \a CFG_TUD_NCM_OUT_NTB_MAX_SIZE.
+ */
 {
-    .header = {
-        .bmRequestType_bit = {
-          .recipient = TUSB_REQ_RCPT_INTERFACE,
-          .type      = TUSB_REQ_TYPE_CLASS,
-          .direction = TUSB_DIR_IN
-        },
-        .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
-        .wLength = 8,
-    },
-    .downlink = 10000000,
-    .uplink = 10000000,
-};
+    DEBUG_OUT("recv_get_free_ntb()\n");
 
-void tud_network_recv_renew(void)
+    for (int i = 0;  i < RECV_NTB_N;  ++i) {
+        if (ncm_interface.recv_free_ntb[i] != NULL) {
+            recv_ntb_t *free = ncm_interface.recv_free_ntb[i];
+            ncm_interface.recv_free_ntb[i] = NULL;
+            return free;
+        }
+    }
+    return NULL;
+}   // recv_get_free_ntb
+
+
+
+static recv_ntb_t *recv_get_next_ready_ntb(void)
+/**
+ * Get the next NTB from the ready list (and remove it from the list).
+ * If the ready list is empty, return NULL.
+ */
 {
-  if (!ncm_interface.num_datagrams)
-  {
-    usbd_edpt_xfer(0, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb));
-    return;
-  }
+    recv_ntb_t *r = NULL;
 
-  const ndp16_t *ndp = ncm_interface.ndp;
-  const int i = ncm_interface.current_datagram_index;
-  ncm_interface.current_datagram_index++;
-  ncm_interface.num_datagrams--;
+    r = ncm_interface.recv_ready_ntb[0];
+    memmove(ncm_interface.recv_ready_ntb + 0, ncm_interface.recv_ready_ntb + 1, sizeof(ncm_interface.recv_ready_ntb) - sizeof(ncm_interface.recv_ready_ntb[0]));
 
-  tud_network_recv_cb(receive_ntb + ndp->datagram[i].wDatagramIndex, ndp->datagram[i].wDatagramLength);
-}
+    DEBUG_OUT("recv_get_next_ready_ntb: %p\n", r);
+    return r;
+}   // recv_get_next_ready_ntb
 
-//--------------------------------------------------------------------+
-// USBD Driver API
-//--------------------------------------------------------------------+
 
-void netd_init(void)
+
+static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb)
+/**
+ *
+ */
 {
-  tu_memclr(&ncm_interface, sizeof(ncm_interface));
-  ncm_interface.ntb_in_size = CFG_TUD_NCM_IN_NTB_MAX_SIZE;
-  ncm_interface.max_datagrams_per_ntb = CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB;
-  ncm_prepare_for_tx();
-}
+    DEBUG_OUT("recv_put_ntb_into_free_list(%p)\n", free_ntb);
 
-void netd_reset(uint8_t rhport)
+    for (int i = 0;  i < RECV_NTB_N;  ++i) {
+        if (ncm_interface.recv_free_ntb[i] == NULL) {
+            ncm_interface.recv_free_ntb[i] = free_ntb;
+            return;
+        }
+    }
+    ERROR_OUT("recv_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
+}   // recv_put_ntb_into_free_list
+
+
+
+static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
+/**
+ * The \a ncm_interface.recv_tinyusb_ntb is filled,
+ * put this buffer into the waiting list and free the receive logic.
+ */
 {
-  (void) rhport;
+    DEBUG_OUT("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->len);
+
+    for (int i = 0;  i < RECV_NTB_N;  ++i) {
+        if (ncm_interface.recv_ready_ntb[i] == NULL) {
+            ncm_interface.recv_ready_ntb[i] = ready_ntb;
+            return;
+        }
+    }
+    ERROR_OUT("recv_put_ntb_into_ready_list: ready list full\n");  // this should not happen
+}   // recv_put_ntb_into_ready_list
+
 
-  netd_init();
-}
 
-uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
+static void recv_try_to_start_new_reception(uint8_t rhport)
+/**
+ * If possible, start a new reception TinyUSB -> driver.
+ * Return value is actually not of interest.
+ */
 {
-  // confirm interface hasn't already been allocated
-  TU_ASSERT(0 == ncm_interface.ep_notif, 0);
+    DEBUG_OUT("recv_try_to_start_new_reception(%d)\n", rhport);
 
-  //------------- Management Interface -------------//
-  ncm_interface.itf_num = itf_desc->bInterfaceNumber;
+    if (ncm_interface.itf_data_alt != 1) {
+        return;
+    }
+    if (ncm_interface.recv_tinyusb_ntb != NULL) {
+        return;
+    }
+    if (usbd_edpt_busy(ncm_interface.rhport, ncm_interface.ep_out)) {
+        return;
+    }
 
-  uint16_t drv_len = sizeof(tusb_desc_interface_t);
-  uint8_t const * p_desc = tu_desc_next( itf_desc );
+    ncm_interface.recv_tinyusb_ntb = recv_get_free_ntb();
+    if (ncm_interface.recv_tinyusb_ntb == NULL) {
+        return;
+    }
 
-  // Communication Functional Descriptors
-  while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
-  {
-    drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
-  }
+    // initiate transfer
+    DEBUG_OUT("  start reception\n");
+    bool r = usbd_edpt_xfer(0, ncm_interface.ep_out, ncm_interface.recv_tinyusb_ntb->data, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+    if ( !r) {
+        recv_put_ntb_into_free_list(ncm_interface.recv_tinyusb_ntb);
+        ncm_interface.recv_tinyusb_ntb = NULL;
+    }
+}   // recv_try_to_start_new_reception
 
-  // notification endpoint (if any)
-  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-  {
-    TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 );
 
-    ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
 
-    drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
-  }
+static bool recv_validate_datagram(const recv_ntb_t *ntb, uint16_t len)
+/**
+ * Validate incoming datagram.
+ * \return true if valid
+ *
+ * \note
+ *    \a ndp16->wNextNdpIndex != 0 is not supported
+ */
+{
+    const nth16_t *nth16 = &(ntb->nth);
 
-  //------------- Data Interface -------------//
-  // - CDC-NCM data interface has 2 alternate settings
-  //   - 0 : zero endpoints for inactive (default)
-  //   - 1 : IN & OUT endpoints for transfer of NTBs
-  TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
+    DEBUG_OUT("recv_validate_datagram(%p)\n", ntb);
 
-  do
-  {
-    tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc;
-    TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0);
+    //
+    // check header
+    //
+    if (nth16->wHeaderLength != sizeof(nth16_t))
+    {
+        ERROR_OUT("  ill nth16 length: %d\n", nth16->wHeaderLength);
+        return false;
+    }
+    if (nth16->dwSignature != NTH16_SIGNATURE) {
+        ERROR_OUT("  ill signature: 0x%08x\n", (unsigned)nth16->dwSignature);
+        return false;
+    }
+    if (len < sizeof(nth16_t) + sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
+        ERROR_OUT("  ill min len: %d\n", len);
+        return false;
+    }
+    if (nth16->wBlockLength > len) {
+        ERROR_OUT("  ill block length: %d > %d\n", nth16->wBlockLength, len);
+        return false;
+    }
+    if (nth16->wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+        ERROR_OUT("  ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+        return false;
+    }
+    if (nth16->wNdpIndex < sizeof(nth16)  ||  nth16->wNdpIndex > len - (sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t))) {
+        ERROR_OUT("  ill position of first ndp: %d (%d)\n", nth16->wNdpIndex, len);
+        return false;
+    }
 
-    drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
-  } while((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len));
+    //
+    // check (first) NDP(16)
+    //
+    const ndp16_t *ndp16 = (ndp16_t *)(ntb->data + nth16->wNdpIndex);
 
-  // Pair of endpoints
-  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0);
+    if (ndp16->wLength < sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
+        ERROR_OUT("  ill ndp16 length: %d\n", ndp16->wLength);
+        return false;
+    }
+    if (ndp16->dwSignature != NDP16_SIGNATURE_NCM0  &&  ndp16->dwSignature != NDP16_SIGNATURE_NCM1) {
+        ERROR_OUT("  ill signature: 0x%08x\n", (unsigned)ndp16->dwSignature);
+        return false;
+    }
+    if (ndp16->wNextNdpIndex != 0) {
+        ERROR_OUT("  cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
+        return false;
+    }
 
-  TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) );
+    const ndp16_datagram_t *ndp16_datagram = (ndp16_datagram_t *)(ntb->data + nth16->wNdpIndex + sizeof(ndp16_t));
+    int ndx = 0;
+    int max_ndx = (ndp16->wLength - sizeof(ndp16_t)) / sizeof(ndp16_datagram_t);
 
-  drv_len += 2*sizeof(tusb_desc_endpoint_t);
+    if (max_ndx > 2) {
+        // number of datagrams in NTB > 1
+        INFO_OUT("<< %d (%d)\n", max_ndx - 1, ntb->len);
+    }
+    if (ndp16_datagram[max_ndx-1].wDatagramIndex != 0  ||  ndp16_datagram[max_ndx-1].wDatagramLength != 0) {
+        INFO_OUT("  max_ndx != 0\n");
+        return false;
+    }
+    while (ndp16_datagram[ndx].wDatagramIndex != 0  &&  ndp16_datagram[ndx].wDatagramLength != 0) {
+        DEBUG_OUT("  << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
+        if (ndp16_datagram[ndx].wDatagramIndex > len) {
+            ERROR_OUT("  ill start of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
+            return false;
+        }
+        if (ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength > len) {
+            ERROR_OUT("  ill end of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
+            return false;
+        }
+        ++ndx;
+    }
+
+    for (int i = 0;  i < len;  ++i) {
+        DEBUG_OUT(" %02x", ntb->data[i]);
+    }
+    DEBUG_OUT("\n");
+
+    // -> ntb contains a valid packet structure
+    //    ok... I did not check for garbage within the datagram indices...
+    return true;
+}   // recv_validate_datagram
 
-  return drv_len;
-}
 
-static void ncm_report(void)
-{
-  uint8_t const rhport = 0;
-  if (ncm_interface.report_state == REPORT_SPEED) {
-    ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
-    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
-    ncm_interface.report_state = REPORT_CONNECTED;
-    ncm_interface.report_pending = true;
-  } else if (ncm_interface.report_state == REPORT_CONNECTED) {
-    ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
-    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
-    ncm_interface.report_state = REPORT_DONE;
-    ncm_interface.report_pending = true;
-  }
-}
-
-TU_ATTR_WEAK void tud_network_link_state_cb(bool state)
-{
-  (void)state;
-}
 
-// Handle class control request
-// return false to stall control endpoint (e.g unsupported request)
-bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
+static void recv_transfer_datagram_to_glue_logic(void)
+/**
+ * Transfer the next (pending) datagram to the glue logic and return receive buffer if empty.
+ */
 {
-  if ( stage != CONTROL_STAGE_SETUP ) return true;
-
-  switch ( request->bmRequestType_bit.type )
-  {
-    case TUSB_REQ_TYPE_STANDARD:
-      switch ( request->bRequest )
-      {
-        case TUSB_REQ_GET_INTERFACE:
-        {
-          uint8_t const req_itfnum = (uint8_t) request->wIndex;
-          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum);
-
-          tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
+    DEBUG_OUT("recv_transfer_datagram_to_glue_logic()\n");
+
+    if (ncm_interface.recv_glue_ntb == NULL) {
+        ncm_interface.recv_glue_ntb = recv_get_next_ready_ntb();
+        DEBUG_OUT("  new buffer for glue logic: %p\n", ncm_interface.recv_glue_ntb);
+        ncm_interface.recv_glue_ntb_datagram_ndx = 0;
+    }
+
+    if (ncm_interface.recv_glue_ntb != NULL) {
+        const ndp16_datagram_t *ndp16_datagram = (ndp16_datagram_t *)(ncm_interface.recv_glue_ntb->data
+                                                                    + ncm_interface.recv_glue_ntb->nth.wNdpIndex
+                                                                    + sizeof(ndp16_t));
+
+        if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex == 0) {
+            ERROR_OUT("  SOMETHING WENT WRONG 1\n");
         }
-          break;
-
-        case TUSB_REQ_SET_INTERFACE:
-        {
-          uint8_t const req_itfnum = (uint8_t) request->wIndex;
-          uint8_t const req_alt    = (uint8_t) request->wValue;
-
-          // Only valid for Data Interface with Alternate is either 0 or 1
-          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2);
-
-          if (req_alt != ncm_interface.itf_data_alt) {
-            ncm_interface.itf_data_alt = req_alt;
-
-            if (ncm_interface.itf_data_alt) {
-              if (!usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
-                tud_network_recv_renew(); // prepare for incoming datagrams
-              }
-              if (!ncm_interface.report_pending) {
-                ncm_report();
-              }
+        else if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength == 0) {
+            ERROR_OUT("  SOMETHING WENT WRONG 2\n");
+        }
+        else {
+            uint16_t datagramIndex  = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex;
+            uint16_t datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength;
+
+            DEBUG_OUT("  recv[%d] - %d %d\n", ncm_interface.recv_glue_ntb_datagram_ndx, datagramIndex, datagramLength);
+            if (tud_network_recv_cb(ncm_interface.recv_glue_ntb->data + datagramIndex, datagramLength)) {
+                //
+                // send datagram successfully to glue logic
+                //
+                DEBUG_OUT("    OK\n");
+                datagramIndex  = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramIndex;
+                datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramLength;
+
+                if (datagramIndex != 0  &&  datagramLength != 0) {
+                    // -> next datagram
+                    ++ncm_interface.recv_glue_ntb_datagram_ndx;
+                }
+                else {
+                    // end of datagrams reached
+                    recv_put_ntb_into_free_list(ncm_interface.recv_glue_ntb);
+                    ncm_interface.recv_glue_ntb = NULL;
+                }
             }
+        }
+    }
+}   // recv_transfer_datagram_to_glue_logic
 
-            tud_network_link_state_cb(ncm_interface.itf_data_alt);
-          }
 
-          tud_control_status(rhport, request);
-        }
-          break;
+//-----------------------------------------------------------------------------
+//
+// all the tud_network_*() stuff (glue logic -> driver)
+//
+
+
+bool tud_network_can_xmit(uint16_t size)
+/**
+ * Check if the glue logic is allowed to call tud_network_xmit().
+ * This function also fetches a next buffer if required, so that tud_network_xmit() is ready for copy
+ * and transmission operation.
+ */
+{
+    DEBUG_OUT("tud_network_can_xmit(%d)\n", size);
+
+    TU_ASSERT(size <= CFG_TUD_NCM_OUT_NTB_MAX_SIZE - (sizeof(nth16_t) + sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)), false);
+
+    if (xmit_requested_datagram_fits_into_current_ntb(size)  ||  xmit_setup_next_glue_ntb()) {
+        // -> everything is fine
+        return true;
+    }
+    xmit_start_if_possible(ncm_interface.rhport);
+    ERROR_OUT("  tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
+    return false;
+}   // tud_network_can_xmit
 
-          // unsupported request
-        default: return false;
-      }
-      break;
 
-    case TUSB_REQ_TYPE_CLASS:
-      TU_VERIFY (ncm_interface.itf_num == request->wIndex);
 
-      if (NCM_GET_NTB_PARAMETERS == request->bRequest)
-      {
-        tud_control_xfer(rhport, request, (void*)(uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
-      }
+void tud_network_xmit(void *ref, uint16_t arg)
+/**
+ * Put a datagram into a waiting NTB.
+ * If currently no transmission is started, then initiate transmission.
+ */
+{
+    DEBUG_OUT("tud_network_xmit(%p, %d)\n", ref, arg);
+
+    if (ncm_interface.xmit_glue_ntb == NULL) {
+        ERROR_OUT("tud_network_xmit: no buffer\n");             // must not happen (really)
+        return;
+    }
+
+    xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
+
+    // copy new datagram to the end of the current NTB
+    uint16_t size = tud_network_xmit_cb(ntb->data + ntb->nth.wBlockLength, ref, arg);
+
+    // correct NTB internals
+    ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramIndex  = ntb->nth.wBlockLength;
+    ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramLength = size;
+    ncm_interface.xmit_glue_ntb_datagram_ndx += 1;
 
-      break;
+    ntb->nth.wBlockLength += size + XMIT_ALIGN_OFFSET(size);
 
-      // unsupported request
-    default: return false;
-  }
+    if (ntb->nth.wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+        ERROR_OUT("tud_network_xmit: buffer overflow\n");       // must not happen (really)
+        return;
+    }
+
+    xmit_start_if_possible(ncm_interface.rhport);
+}   // tud_network_xmit
 
-  return true;
-}
 
-static void handle_incoming_datagram(uint32_t len)
+
+void tud_network_recv_renew(void)
+/**
+ * Keep the receive logic busy and transfer pending packets to the glue logic.
+ */
 {
-  uint32_t size = len;
+    DEBUG_OUT("tud_network_recv_renew()\n");
 
-  if (len == 0) {
-    return;
-  }
+    recv_transfer_datagram_to_glue_logic();
+    recv_try_to_start_new_reception(ncm_interface.rhport);
+}   // tud_network_recv_renew
 
-  TU_ASSERT(size >= sizeof(nth16_t), );
 
-  const nth16_t *hdr = (const nth16_t *)receive_ntb;
-  TU_ASSERT(hdr->dwSignature == NTH16_SIGNATURE, );
-  TU_ASSERT(hdr->wNdpIndex >= sizeof(nth16_t) && (hdr->wNdpIndex + sizeof(ndp16_t)) <= len, );
 
-  const ndp16_t *ndp = (const ndp16_t *)(receive_ntb + hdr->wNdpIndex);
-  TU_ASSERT(ndp->dwSignature == NDP16_SIGNATURE_NCM0 || ndp->dwSignature == NDP16_SIGNATURE_NCM1, );
-  TU_ASSERT(hdr->wNdpIndex + ndp->wLength <= len, );
+void tud_network_recv_renew_r(uint8_t rhport)
+/**
+ * Same as tud_network_recv_renew() but knows \a rhport
+ */
+{
+    DEBUG_OUT("tud_network_recv_renew_r(%d)\n", rhport);
 
-  int num_datagrams = (ndp->wLength - 12) / 4;
-  ncm_interface.current_datagram_index = 0;
-  ncm_interface.num_datagrams = 0;
-  ncm_interface.ndp = ndp;
-  for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++)
-  {
-    ncm_interface.num_datagrams++;
-  }
+    ncm_interface.rhport = rhport;
+    tud_network_recv_renew();
+}   // tud_network_recv_renew
 
-  tud_network_recv_renew();
-}
 
-bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+//-----------------------------------------------------------------------------
+//
+// all the netd_*() stuff (interface TinyUSB -> driver)
+//
+void netd_init(void)
+/**
+ * Initialize the driver data structures.
+ * Might be called several times.
+ */
 {
-  (void) rhport;
-  (void) result;
+    DEBUG_OUT("netd_init()\n");
 
-  /* new datagram receive_ntb */
-  if (ep_addr == ncm_interface.ep_out )
-  {
-    handle_incoming_datagram(xferred_bytes);
-  }
+    memset( &ncm_interface, 0, sizeof(ncm_interface));
 
-  /* data transmission finished */
-  if (ep_addr == ncm_interface.ep_in )
-  {
-    if (ncm_interface.transferring) {
-      ncm_interface.transferring = false;
+    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
+        ncm_interface.xmit_free_ntb[i] = ncm_interface.xmit_ntb + i;
     }
+    for (int i = 0;  i < RECV_NTB_N;  ++i) {
+        ncm_interface.recv_free_ntb[i] = ncm_interface.recv_ntb + i;
+    }
+}   // netd_init
+
 
-    // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now
-    if (ncm_interface.datagram_count && ncm_interface.itf_data_alt == 1) {
-      ncm_start_tx();
+
+void netd_reset(uint8_t rhport)
+/**
+ * Resets the port.
+ * In this driver this is the same as netd_init()
+ */
+{
+    DEBUG_OUT("netd_reset(%d)\n", rhport);
+
+    netd_init();
+}   // netd_reset
+
+
+
+uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+/**
+ * Open the USB interface.
+ * - parse the USB descriptor \a TUD_CDC_NCM_DESCRIPTOR for itfnum and endpoints
+ * - a specific order of elements in the descriptor is tested.
+ *
+ * \note
+ *   Actually all of the information could be read directly from \a itf_desc, because the
+ *   structure and the values are well known.  But we do it this way.
+ *
+ * \post
+ * - \a itf_num set
+ * - \a ep_notif, \a ep_in and \a ep_out are set
+ * - USB interface is open
+ */
+{
+    DEBUG_OUT("netd_open(%d,%p,%d)\n", rhport, itf_desc, max_len);
+
+    TU_ASSERT(ncm_interface.ep_notif == 0, 0);           // assure that the interface is only opened once
+
+    ncm_interface.itf_num = itf_desc->bInterfaceNumber;  // management interface
+
+    //
+    // skip the two first entries and the following TUSB_DESC_CS_INTERFACE entries
+    //
+    uint16_t drv_len = sizeof(tusb_desc_interface_t);
+    uint8_t const *p_desc = tu_desc_next(itf_desc);
+    while (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE  &&  drv_len <= max_len) {
+        drv_len += tu_desc_len(p_desc);
+        p_desc = tu_desc_next(p_desc);
     }
-  }
 
-  if (ep_addr == ncm_interface.ep_notif )
-  {
-    ncm_interface.report_pending = false;
-    ncm_report();
-  }
+    //
+    // get notification endpoint
+    //
+    TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+    TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const* ) p_desc), 0);
+    ncm_interface.ep_notif = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
+    drv_len += tu_desc_len(p_desc);
+    p_desc = tu_desc_next(p_desc);
 
-  return true;
-}
+    //
+    // skip the following TUSB_DESC_INTERFACE entries (which must be TUSB_CLASS_CDC_DATA)
+    //
+    while (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE  &&  drv_len <= max_len) {
+        tusb_desc_interface_t const *data_itf_desc = (tusb_desc_interface_t const*)p_desc;
+        TU_ASSERT(data_itf_desc->bInterfaceClass == TUSB_CLASS_CDC_DATA, 0);
 
-// poll network driver for its ability to accept another packet to transmit
-bool tud_network_can_xmit(uint16_t size)
+        drv_len += tu_desc_len(p_desc);
+        p_desc = tu_desc_next(p_desc);
+    }
+
+    //
+    // a TUSB_DESC_ENDPOINT (actually two) must follow, open these endpoints
+    //
+    TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+    TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in));
+    drv_len += 2 * sizeof(tusb_desc_endpoint_t);
+
+    return drv_len;
+}   // netd_open
+
+
+
+bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+/**
+ * Handle TinyUSB requests to process transfer events.
+ */
 {
-  TU_VERIFY(ncm_interface.itf_data_alt == 1);
+    DEBUG_OUT("netd_xfer_cb(%d,%d,%d,%u)\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
+
+    if (ep_addr == ncm_interface.ep_out) {
+        //
+        // new NTB received
+        // - make the NTB valid
+        // - if ready transfer datagrams to the glue logic for further processing
+        // - if there is a free receive buffer, initiate reception
+        //
+        DEBUG_OUT("  EP_OUT %d %d %d %u\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
+        if ( !recv_validate_datagram( ncm_interface.recv_tinyusb_ntb, xferred_bytes)) {
+            // verification failed: ignore NTB and return it to free
+            ERROR_OUT("  VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
+        }
+        else {
+            // packet ok -> put it into ready list
+            recv_put_ntb_into_ready_list(ncm_interface.recv_tinyusb_ntb);
+        }
+        ncm_interface.recv_tinyusb_ntb = NULL;
+        tud_network_recv_renew_r(rhport);
+    }
+    else if (ep_addr == ncm_interface.ep_in) {
+        //
+        // transmission of an NTB finished
+        // - free the transmitted NTB buffer
+        // - insert ZLPs when necessary
+        // - if there is another transmit NTB waiting, try to start transmission
+        //
+        DEBUG_OUT("  EP_IN %d %u\n", ncm_interface.itf_data_alt, (unsigned)xferred_bytes);
+        xmit_put_ntb_into_free_list(ncm_interface.xmit_tinyusb_ntb);
+        ncm_interface.xmit_tinyusb_ntb = NULL;
+        if ( !xmit_insert_required_zlp(rhport, xferred_bytes)) {
+            xmit_start_if_possible(rhport);
+        }
+    }
+    else if (ep_addr == ncm_interface.ep_notif) {
+        //
+        // next transfer on notification channel
+        //
+        DEBUG_OUT("  EP_NOTIF\n");
+        notification_xmit(rhport, true);
+    }
 
-  if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
-    TU_LOG_DRV("NTB full [by count]\r\n");
-    return false;
-  }
+    return true;
+}   // netd_xfer_cb
 
-  size_t next_datagram_offset = ncm_interface.next_datagram_offset;
-  if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
-    TU_LOG_DRV("ntb full [by size]\r\n");
-    return false;
-  }
 
-  return true;
-}
 
-void tud_network_xmit(void *ref, uint16_t arg)
+bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request)
+/**
+ * Respond to TinyUSB control requests.
+ * At startup transmission of notification packets are done here.
+ */
 {
-  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
-  size_t next_datagram_offset = ncm_interface.next_datagram_offset;
+    DEBUG_OUT("netd_control_xfer_cb(%d, %d, %p)\n", rhport, stage, request);
 
-  uint16_t size = tud_network_xmit_cb(ntb->data + next_datagram_offset, ref, arg);
+    if (stage != CONTROL_STAGE_SETUP) {
+        return true;
+    }
 
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = ncm_interface.next_datagram_offset;
-  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = size;
+    switch (request->bmRequestType_bit.type) {
+        case TUSB_REQ_TYPE_STANDARD:
+            switch (request->bRequest) {
+                case TUSB_REQ_GET_INTERFACE: {
+                    TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
+
+                    DEBUG_OUT("  TUSB_REQ_GET_INTERFACE - %d\n", ncm_interface.itf_data_alt);
+                    tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
+                }
+                break;
+
+                case TUSB_REQ_SET_INTERFACE: {
+                    TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex  &&  request->wValue < 2, false);
+
+                    ncm_interface.itf_data_alt = request->wValue;
+                    DEBUG_OUT("  TUSB_REQ_SET_INTERFACE - %d %d %d\n", ncm_interface.itf_data_alt, request->wIndex, ncm_interface.itf_num);
+
+                    if (ncm_interface.itf_data_alt == 1) {
+                        tud_network_recv_renew_r(rhport);
+                        notification_xmit(rhport, false);
+                    }
+                    tud_control_status(rhport, request);
+                }
+                break;
+
+                // unsupported request
+                default:
+                    return false;
+            }
+            break;
 
-  ncm_interface.datagram_count++;
-  next_datagram_offset += size;
+        case TUSB_REQ_TYPE_CLASS:
+            TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
 
-  // round up so the next datagram is aligned correctly
-  next_datagram_offset += (CFG_TUD_NCM_ALIGNMENT - 1);
-  next_datagram_offset -= (next_datagram_offset % CFG_TUD_NCM_ALIGNMENT);
+            DEBUG_OUT("  TUSB_REQ_TYPE_CLASS: %d\n", request->bRequest);
 
-  ncm_interface.next_datagram_offset = next_datagram_offset;
+            if (request->bRequest == NCM_GET_NTB_PARAMETERS) {
+                // transfer NTB parameters to host.
+                // TODO can one assume, that tud_control_xfer() succeeds?
+                DEBUG_OUT("    NCM_GET_NTB_PARAMETERS\n");
+                tud_control_xfer(rhport, request, (void*) (uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
+            }
+            break;
 
-  ncm_start_tx();
-}
+            // unsupported request
+        default:
+            return false ;
+    }
 
-#endif
+    return true;
+}   // netd_control_xfer_cb
+
+#endif   // ECLIPSE_GUI || ( CFG_TUD_ENABLED && CFG_TUD_NCM )
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 399916355..111c822fb 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -28,14 +28,13 @@
 #ifndef _TUSB_NET_DEVICE_H_
 #define _TUSB_NET_DEVICE_H_
 
+#include <stdint.h>
 #include "class/cdc/cdc.h"
 
 #if CFG_TUD_ECM_RNDIS && CFG_TUD_NCM
 #error "Cannot enable both ECM_RNDIS and NCM network drivers"
 #endif
 
-#include "ncm.h"
-
 /* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */
 #define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
@@ -44,21 +43,6 @@
 #define CFG_TUD_NET_MTU           1514
 #endif
 
-#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
-#define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
-#endif
-
-#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
-#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
-#endif
-
-#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
-#define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB 8
-#endif
-
-#ifndef CFG_TUD_NCM_ALIGNMENT
-#define CFG_TUD_NCM_ALIGNMENT 4
-#endif
 
 #ifdef __cplusplus
  extern "C" {
@@ -92,12 +76,6 @@ uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg);
 // client must provide this: initialize any network state back to the beginning
 void tud_network_init_cb(void);
 
-// client must provide this: 48-bit MAC address
-// TODO removed later since it is not part of tinyusb stack
-extern uint8_t tud_network_mac_address[6];
-
-//------------- NCM -------------//
-
 // callback to client providing optional indication of internal state of network driver
 void tud_network_link_state_cb(bool state);
 
-- 
cgit v1.3.1


From d5da303f450ce0e1004121af4a40a512371e9353 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Sun, 20 Aug 2023 18:22:07 +0200
Subject: moved some declarations

---
 src/class/net/ncm.h        |  7 -------
 src/class/net/net_device.h | 11 +++++++++++
 2 files changed, 11 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h
index 313237747..c768192a5 100644
--- a/src/class/net/ncm.h
+++ b/src/class/net/ncm.h
@@ -71,13 +71,6 @@
 #endif
 
 
-// Table 4.3 Data Class Interface Protocol Codes
-typedef enum
-{
-  NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01
-} ncm_data_interface_protocol_code_t;
-
-
 // Table 6.2 Class-Specific Request Codes for Network Control Model subclass
 typedef enum
 {
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 111c822fb..3342dac3d 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -44,6 +44,13 @@
 #endif
 
 
+// Table 4.3 Data Class Interface Protocol Codes
+typedef enum
+{
+  NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01
+} ncm_data_interface_protocol_code_t;
+
+
 #ifdef __cplusplus
  extern "C" {
 #endif
@@ -76,6 +83,10 @@ uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg);
 // client must provide this: initialize any network state back to the beginning
 void tud_network_init_cb(void);
 
+// client must provide this: 48-bit MAC address
+// TODO removed later since it is not part of tinyusb stack
+extern uint8_t tud_network_mac_address[6];
+
 // callback to client providing optional indication of internal state of network driver
 void tud_network_link_state_cb(bool state);
 
-- 
cgit v1.3.1


From e4c18c101cf5dc78f6bd1034aae7f0f7e22b7e47 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Sun, 20 Aug 2023 18:22:07 +0200
Subject: Copyright

---
 src/class/net/ncm_device.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index f7a236e69..28066b6af 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2023 Hardy Griech
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
-- 
cgit v1.3.1


From 28107326da6cbc462bf6644f1f6edd5d0bcb43b8 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Sun, 20 Aug 2023 18:22:07 +0200
Subject: bug fix recv/xmit_get_next_ready_ntb()

---
 src/class/net/ncm_device.c | 58 ++++++++++++++++++++++++----------------------
 1 file changed, 30 insertions(+), 28 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 28066b6af..65543fcab 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -254,7 +254,7 @@ static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb)
             return;
         }
     }
-    ERROR_OUT("xmit_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
+    ERROR_OUT("(EE) xmit_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
 }   // xmit_put_ntb_into_free_list
 
 
@@ -283,7 +283,7 @@ static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb)
  * Put a filled NTB into the ready list
  */
 {
-    INFO_OUT("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->len);
+    INFO_OUT("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
 
     for (int i = 0;  i < XMIT_NTB_N;  ++i) {
         if (ncm_interface.xmit_ready_ntb[i] == NULL) {
@@ -291,7 +291,7 @@ static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb)
             return;
         }
     }
-    ERROR_OUT("xmit_put_ntb_into_ready_list: ready list full\n");  // this should not happen
+    ERROR_OUT("(EE) xmit_put_ntb_into_ready_list: ready list full\n");  // this should not happen
 }   // xmit_put_ntb_into_ready_list
 
 
@@ -306,6 +306,7 @@ static xmit_ntb_t *xmit_get_next_ready_ntb(void)
 
     r = ncm_interface.xmit_ready_ntb[0];
     memmove(ncm_interface.xmit_ready_ntb + 0, ncm_interface.xmit_ready_ntb + 1, sizeof(ncm_interface.xmit_ready_ntb) - sizeof(ncm_interface.xmit_ready_ntb[0]));
+    ncm_interface.xmit_ready_ntb[XMIT_NTB_N - 1] = NULL;
 
     DEBUG_OUT("recv_get_next_ready_ntb: %p\n", r);
     return r;
@@ -357,7 +358,7 @@ static void xmit_start_if_possible(uint8_t rhport)
         return;
     }
     if (ncm_interface.itf_data_alt != 1) {
-        ERROR_OUT("  !xmit_start_if_possible 2\n");
+        ERROR_OUT("(II) !xmit_start_if_possible 2\n");
         return;
     }
     if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
@@ -375,9 +376,9 @@ static void xmit_start_if_possible(uint8_t rhport)
         ncm_interface.xmit_glue_ntb = NULL;
     }
 
-#if DEBUG_OUT_ENABLED
+#ifdef DEBUG_OUT_ENABLED
     {
-        uint16_t len = ncm_interface.xmit_tinyusb_ntb->ntb.nth.wBlockLength;
+        uint16_t len = ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength;
         DEBUG_OUT(" %d\n", len);
         for (int i = 0;  i < len;  ++i) {
             DEBUG_OUT(" %02x", ncm_interface.xmit_tinyusb_ntb->data[i]);
@@ -387,7 +388,7 @@ static void xmit_start_if_possible(uint8_t rhport)
 #endif
 
     if (ncm_interface.xmit_glue_ntb_datagram_ndx != 1) {
-        DEBUG_OUT(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->len, ncm_interface.xmit_glue_ntb_datagram_ndx);
+        DEBUG_OUT(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength, ncm_interface.xmit_glue_ntb_datagram_ndx);
     }
 
     // Kick off an endpoint transfer
@@ -492,6 +493,7 @@ static recv_ntb_t *recv_get_next_ready_ntb(void)
 
     r = ncm_interface.recv_ready_ntb[0];
     memmove(ncm_interface.recv_ready_ntb + 0, ncm_interface.recv_ready_ntb + 1, sizeof(ncm_interface.recv_ready_ntb) - sizeof(ncm_interface.recv_ready_ntb[0]));
+    ncm_interface.recv_ready_ntb[RECV_NTB_N - 1] = NULL;
 
     DEBUG_OUT("recv_get_next_ready_ntb: %p\n", r);
     return r;
@@ -512,7 +514,7 @@ static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb)
             return;
         }
     }
-    ERROR_OUT("recv_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
+    ERROR_OUT("(EE) recv_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
 }   // recv_put_ntb_into_free_list
 
 
@@ -523,7 +525,7 @@ static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
  * put this buffer into the waiting list and free the receive logic.
  */
 {
-    DEBUG_OUT("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->len);
+    DEBUG_OUT("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
 
     for (int i = 0;  i < RECV_NTB_N;  ++i) {
         if (ncm_interface.recv_ready_ntb[i] == NULL) {
@@ -531,7 +533,7 @@ static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
             return;
         }
     }
-    ERROR_OUT("recv_put_ntb_into_ready_list: ready list full\n");  // this should not happen
+    ERROR_OUT("(EE) recv_put_ntb_into_ready_list: ready list full\n");  // this should not happen
 }   // recv_put_ntb_into_ready_list
 
 
@@ -588,27 +590,27 @@ static bool recv_validate_datagram(const recv_ntb_t *ntb, uint16_t len)
     //
     if (nth16->wHeaderLength != sizeof(nth16_t))
     {
-        ERROR_OUT("  ill nth16 length: %d\n", nth16->wHeaderLength);
+        ERROR_OUT("(EE) ill nth16 length: %d\n", nth16->wHeaderLength);
         return false;
     }
     if (nth16->dwSignature != NTH16_SIGNATURE) {
-        ERROR_OUT("  ill signature: 0x%08x\n", (unsigned)nth16->dwSignature);
+        ERROR_OUT("(EE) ill signature: 0x%08x\n", (unsigned)nth16->dwSignature);
         return false;
     }
     if (len < sizeof(nth16_t) + sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
-        ERROR_OUT("  ill min len: %d\n", len);
+        ERROR_OUT("(EE) ill min len: %d\n", len);
         return false;
     }
     if (nth16->wBlockLength > len) {
-        ERROR_OUT("  ill block length: %d > %d\n", nth16->wBlockLength, len);
+        ERROR_OUT("(EE) ill block length: %d > %d\n", nth16->wBlockLength, len);
         return false;
     }
     if (nth16->wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        ERROR_OUT("  ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+        ERROR_OUT("(EE) ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
         return false;
     }
     if (nth16->wNdpIndex < sizeof(nth16)  ||  nth16->wNdpIndex > len - (sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t))) {
-        ERROR_OUT("  ill position of first ndp: %d (%d)\n", nth16->wNdpIndex, len);
+        ERROR_OUT("(EE) ill position of first ndp: %d (%d)\n", nth16->wNdpIndex, len);
         return false;
     }
 
@@ -618,15 +620,15 @@ static bool recv_validate_datagram(const recv_ntb_t *ntb, uint16_t len)
     const ndp16_t *ndp16 = (ndp16_t *)(ntb->data + nth16->wNdpIndex);
 
     if (ndp16->wLength < sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
-        ERROR_OUT("  ill ndp16 length: %d\n", ndp16->wLength);
+        ERROR_OUT("(EE) ill ndp16 length: %d\n", ndp16->wLength);
         return false;
     }
     if (ndp16->dwSignature != NDP16_SIGNATURE_NCM0  &&  ndp16->dwSignature != NDP16_SIGNATURE_NCM1) {
-        ERROR_OUT("  ill signature: 0x%08x\n", (unsigned)ndp16->dwSignature);
+        ERROR_OUT("(EE) ill signature: 0x%08x\n", (unsigned)ndp16->dwSignature);
         return false;
     }
     if (ndp16->wNextNdpIndex != 0) {
-        ERROR_OUT("  cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
+        ERROR_OUT("(EE) cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
         return false;
     }
 
@@ -636,7 +638,7 @@ static bool recv_validate_datagram(const recv_ntb_t *ntb, uint16_t len)
 
     if (max_ndx > 2) {
         // number of datagrams in NTB > 1
-        INFO_OUT("<< %d (%d)\n", max_ndx - 1, ntb->len);
+        INFO_OUT("<< %d (%d)\n", max_ndx - 1, ntb->nth.wBlockLength);
     }
     if (ndp16_datagram[max_ndx-1].wDatagramIndex != 0  ||  ndp16_datagram[max_ndx-1].wDatagramLength != 0) {
         INFO_OUT("  max_ndx != 0\n");
@@ -645,11 +647,11 @@ static bool recv_validate_datagram(const recv_ntb_t *ntb, uint16_t len)
     while (ndp16_datagram[ndx].wDatagramIndex != 0  &&  ndp16_datagram[ndx].wDatagramLength != 0) {
         DEBUG_OUT("  << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
         if (ndp16_datagram[ndx].wDatagramIndex > len) {
-            ERROR_OUT("  ill start of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
+            ERROR_OUT("(EE) ill start of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
             return false;
         }
         if (ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength > len) {
-            ERROR_OUT("  ill end of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
+            ERROR_OUT("(EE) ill end of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
             return false;
         }
         ++ndx;
@@ -686,10 +688,10 @@ static void recv_transfer_datagram_to_glue_logic(void)
                                                                     + sizeof(ndp16_t));
 
         if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex == 0) {
-            ERROR_OUT("  SOMETHING WENT WRONG 1\n");
+            ERROR_OUT("(EE) SOMETHING WENT WRONG 1\n");
         }
         else if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength == 0) {
-            ERROR_OUT("  SOMETHING WENT WRONG 2\n");
+            ERROR_OUT("(EE) SOMETHING WENT WRONG 2\n");
         }
         else {
             uint16_t datagramIndex  = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex;
@@ -741,7 +743,7 @@ bool tud_network_can_xmit(uint16_t size)
         return true;
     }
     xmit_start_if_possible(ncm_interface.rhport);
-    ERROR_OUT("  tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
+    ERROR_OUT("(II) tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
     return false;
 }   // tud_network_can_xmit
 
@@ -756,7 +758,7 @@ void tud_network_xmit(void *ref, uint16_t arg)
     DEBUG_OUT("tud_network_xmit(%p, %d)\n", ref, arg);
 
     if (ncm_interface.xmit_glue_ntb == NULL) {
-        ERROR_OUT("tud_network_xmit: no buffer\n");             // must not happen (really)
+        ERROR_OUT("(EE) tud_network_xmit: no buffer\n");             // must not happen (really)
         return;
     }
 
@@ -773,7 +775,7 @@ void tud_network_xmit(void *ref, uint16_t arg)
     ntb->nth.wBlockLength += size + XMIT_ALIGN_OFFSET(size);
 
     if (ntb->nth.wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        ERROR_OUT("tud_network_xmit: buffer overflow\n");       // must not happen (really)
+        ERROR_OUT("(II) tud_network_xmit: buffer overflow\n");       // must not happen (really)
         return;
     }
 
@@ -925,7 +927,7 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
         DEBUG_OUT("  EP_OUT %d %d %d %u\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
         if ( !recv_validate_datagram( ncm_interface.recv_tinyusb_ntb, xferred_bytes)) {
             // verification failed: ignore NTB and return it to free
-            ERROR_OUT("  VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
+            ERROR_OUT("(EE) VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
         }
         else {
             // packet ok -> put it into ready list
-- 
cgit v1.3.1


From 2c1addff4f853586c8d9590e3f93d79fc7c6e250 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Sun, 20 Aug 2023 18:27:06 +0200
Subject: defined(ECLIPSE_GUI)

---
 src/class/net/ncm_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 65543fcab..1c6f888cd 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -46,7 +46,7 @@
 
 #include "tusb_option.h"
 
-#if ECLIPSE_GUI || ( CFG_TUD_ENABLED && CFG_TUD_NCM )
+#if defined(ECLIPSE_GUI) || ( CFG_TUD_ENABLED && CFG_TUD_NCM )
 
 #include <stdbool.h>
 #include <stdint.h>
-- 
cgit v1.3.1


From b4134394166c1f77463b5cb62f28cff465fde174 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 22 Aug 2023 19:57:59 +0700
Subject: able to detect new device and start enumerating

---
 src/portable/analog/max3421e/hcd_max3421e.c | 70 +++++++++++++++++++++--------
 1 file changed, 51 insertions(+), 19 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
index a89581b9c..870c616a9 100644
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -140,11 +140,13 @@ enum {
 //
 //--------------------------------------------------------------------+
 
-//typedef struct {
-//  uint8_t mode
-//} max2341e_data_t;
-//
-//max2341e_data_t max2341e_data;
+typedef struct {
+  uint8_t mode;
+
+  volatile uint16_t frame_count;
+} max2341e_data_t;
+
+static max2341e_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
 //
@@ -168,6 +170,11 @@ static uint8_t reg_read(uint8_t reg) {
   return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
 }
 
+static inline uint8_t mode_write(uint8_t data) {
+  _hcd_data.mode = data;
+  return reg_write(MODE_ADDR, data);
+}
+
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -220,7 +227,8 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
     }
   }
 
-  reg_write(MODE_ADDR, new_mode);
+  mode_write(new_mode);
+  TU_LOG2_INT(speed);
   return speed;
 }
 
@@ -228,6 +236,8 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
+  tu_memclr(&_hcd_data, sizeof(_hcd_data));
+
   // full duplex, interrupt level (should be configurable)
   reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
 
@@ -239,17 +249,21 @@ bool hcd_init(uint8_t rhport) {
   }
 
   // Mode: Host and DP/DM pull down
-  reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
+  mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
   // Enable Connection IRQ
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ);
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ);
 
-  // Note: if device is already connected, CONDET IRQ may not be triggered. We need to detect it by sampling bus signal
+  #if 0
+  // Note: if device is already connected, CONDET IRQ may not be triggered.
+  // We need to detect it by sampling bus signal. FIXME not working
   reg_write(HCTL_ADDR, HCTL_SAMPLEBUS);
-  while( !(reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS) ) {}
+  while ( reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS ) {}
 
-  handle_connect_irq(rhport);
-  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
+  if ( TUSB_SPEED_INVALID != handle_connect_irq(rhport) ) {
+    reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); // clear connect irq
+  }
+  #endif
 
   // Enable Interrupt pin
   reg_write(CPUCTL_ADDR, CPUCTL_IE);
@@ -262,7 +276,26 @@ void hcd_int_handler(uint8_t rhport) {
   (void) rhport;
 
   uint8_t hirq = reg_read(HIRQ_ADDR);
-  TU_LOG3_INT(hirq);
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_CONDET_IRQ) {
+    tusb_speed_t speed = handle_connect_irq(rhport);
+
+    if (speed == TUSB_SPEED_INVALID) {
+      hcd_event_device_remove(rhport, true);
+    }else {
+      hcd_event_device_attach(rhport, true);
+    }
+  }
+
+  if (hirq & HIRQ_FRAME_IRQ) {
+    _hcd_data.frame_count++;
+  }
+
+  // clear all interrupt
+  if ( hirq ) {
+    reg_write(HIRQ_ADDR, hirq);
+  }
 }
 
 // Enable USB interrupt
@@ -278,8 +311,7 @@ void hcd_int_disable(uint8_t rhport) {
 // Get frame number (1ms)
 uint32_t hcd_frame_number(uint8_t rhport) {
   (void) rhport;
-
-  return 0;
+  return (uint32_t ) _hcd_data.frame_count;
 }
 
 //--------------------------------------------------------------------+
@@ -289,26 +321,26 @@ uint32_t hcd_frame_number(uint8_t rhport) {
 // Get the current connect status of roothub port
 bool hcd_port_connect_status(uint8_t rhport) {
   (void) rhport;
-
-  return false;
+  return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false;
 }
 
 // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
 // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport) {
   (void) rhport;
+  reg_write(HCTL_ADDR, HCTL_BUSRST);
 }
 
 // Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport) {
   (void) rhport;
+  reg_write(HCTL_ADDR, 0);
 }
 
 // Get port link speed
 tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
   (void) rhport;
-
-  return TUSB_SPEED_FULL;
+  return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
 }
 
 // HCD closes all opened endpoints belong to this device
-- 
cgit v1.3.1


From 274578ff46c31b231b3553dc9a20895646313130 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 22 Aug 2023 23:17:12 +0700
Subject: able to send setup packet

---
 hw/bsp/nrf/boards/feather_nrf52840_express/board.h |   8 +-
 hw/bsp/nrf/family.c                                |  36 ++++-
 src/host/hcd.h                                     |   2 +-
 src/host/usbh.c                                    |  32 ++--
 src/portable/analog/max3421e/hcd_max3421e.c        | 173 ++++++++++++++++-----
 5 files changed, 179 insertions(+), 72 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 7f042142e..e6e7590ac 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -46,10 +46,10 @@
 #define UART_TX_PIN     25
 
 // SPI for USB host shield
-#define SPI_SCK_PIN      14
-#define SPI_MOSI_PIN     13
-#define SPI_MISO_PIN     15
-#define SPI_CS_PIN       27
+#define MAX3421E_SCK_PIN  14
+#define MAX3421E_MOSI_PIN 13
+#define MAX3421E_MISO_PIN 15
+#define MAX3421E_CS_PIN   27
 #define MAX3241E_INTR_PIN 26
 
 #ifdef __cplusplus
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index e58ee845b..862f67bc7 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -96,22 +96,38 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
-void max2342e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
 
   tuh_int_handler(1);
 }
 
+static inline void max3421e_cs_assert(bool active) {
+  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
+}
+
+//--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+//--------------------------------------------------------------------+
+
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
+                               uint8_t * rx_buf, size_t rx_len, bool keep_cs) {
   (void) rhport;
+
+  max3421e_cs_assert(true);
+
   nrfx_spim_xfer_desc_t xfer = {
       .p_tx_buffer = tx_buf,
       .tx_length   = tx_len,
       .p_rx_buffer = rx_buf,
       .rx_length   = rx_len,
   };
-  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+
+  bool ret = (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
+
+  if ( !keep_cs ) max3421e_cs_assert(false);
+
+  return ret;
 }
 
 #endif
@@ -203,12 +219,16 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+  // manually manage CS
+  nrf_gpio_cfg_output(MAX3421E_CS_PIN);
+  max3421e_cs_assert(false);
+
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
-      .sck_pin        = SPI_SCK_PIN,
-      .mosi_pin       = SPI_MOSI_PIN,
-      .miso_pin       = SPI_MISO_PIN,
-      .ss_pin         = SPI_CS_PIN,
+      .sck_pin        = MAX3421E_SCK_PIN,
+      .mosi_pin       = MAX3421E_MOSI_PIN,
+      .miso_pin       = MAX3421E_MISO_PIN,
+      .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
       .ss_active_high = false,
       .irq_priority   = 3,
       .orc            = 0xFF,
@@ -226,7 +246,7 @@ void board_init(void) {
   nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
-  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max2342e_int_handler);
+  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
   nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true);
 #endif
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 1b5038ef4..079877b79 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -177,7 +177,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 5423df669..7a09f5b6e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -552,8 +552,7 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
 }
 
 // TODO timeout_ms is not supported yet
-bool tuh_control_xfer (tuh_xfer_t* xfer)
-{
+bool tuh_control_xfer (tuh_xfer_t* xfer) {
   // EP0 with setup packet
   TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
 
@@ -565,8 +564,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-  if (is_idle)
-  {
+  if (is_idle) {
     _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
     _ctrl_xfer.daddr       = daddr;
     _ctrl_xfer.actual_len  = 0;
@@ -588,11 +586,9 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup);
   TU_LOG_USBH("\r\n");
 
-  if (xfer->complete_cb)
-  {
+  if (xfer->complete_cb) {
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
-  }else
-  {
+  }else {
     // blocking if complete callback is not provided
     // change callback to internal blocking, and result as user argument
     volatile xfer_result_t result = XFER_RESULT_INVALID;
@@ -656,15 +652,13 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result)
   }
 }
 
-static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) ep_addr;
 
   const uint8_t rhport = usbh_get_rhport(dev_addr);
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
-  if (XFER_RESULT_SUCCESS != result)
-  {
+  if (XFER_RESULT_SUCCESS != result) {
     TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     #if CFG_TUSB_DEBUG == 1
     TU_LOG1_PTR(request);
@@ -673,13 +667,10 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);
-  }else
-  {
-    switch(_ctrl_xfer.stage)
-    {
+  }else {
+    switch(_ctrl_xfer.stage) {
       case CONTROL_STAGE_SETUP:
-        if (request->wLength)
-        {
+        if (request->wLength) {
           // DATA stage: initial data toggle is always 1
           _set_control_xfer_stage(CONTROL_STAGE_DATA);
           TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
@@ -688,8 +679,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         TU_ATTR_FALLTHROUGH;
 
       case CONTROL_STAGE_DATA:
-        if (request->wLength)
-        {
+        if (request->wLength) {
           TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
           TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
         }
@@ -1538,9 +1528,7 @@ static bool enum_new_device(hcd_event_t* event)
     xfer.result    = XFER_RESULT_SUCCESS;
     xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
-
     process_enumeration(&xfer);
-
   }
 #if CFG_TUH_HUB
   else
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
index 870c616a9..c9596f695 100644
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -136,30 +136,64 @@ enum {
   HRSL_JSTATUS     = 1u << 7,
 };
 
+enum {
+  HRSL_SUCCESS = 0,
+  HRSL_BUSY,
+  HRSL_BAD_REQ,
+  HRSL_UNDEF,
+  HRSL_NAK,
+  HRSL_STALL,
+  HRSL_TOG_ERR,
+  HRSL_WRONG_PID,
+  HRSL_BAD_BYTECOUNT,
+  HRSL_PID_ERR,
+  HRSL_PKT_ERR,
+  HRSL_CRC_ERR,
+  HRSL_K_ERR,
+  HRSL_J_ERR,
+  HRSL_TIMEOUT,
+  HRSL_BABBLE,
+};
+
+
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
 typedef struct {
+  // cached register
   uint8_t mode;
+  uint8_t peraddr;
+  uint8_t hxfr;
 
   volatile uint16_t frame_count;
+
+  struct {
+    uint16_t packet_size;
+    uint16_t total_len;
+    uint8_t xfer_type;
+  }ep[8][2];
 } max2341e_data_t;
 
 static max2341e_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
-//
+// API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
 
-// API: SPI transfer with MAX3421E, must be implemented by application
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
+                               uint8_t * rx_buf, size_t rx_len, bool keep_cs);
+//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 
 // return HIRQ register since we are in full-duplex mode
 static uint8_t reg_write(uint8_t reg, uint8_t data) {
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
-  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false);
   TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
   return rx_buf[0];
 }
@@ -167,7 +201,7 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) {
 static uint8_t reg_read(uint8_t reg) {
   uint8_t tx_buf[2] = {reg, 0};
   uint8_t rx_buf[2] = {0, 0};
-  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
+  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false) ? rx_buf[1] : 0;
 }
 
 static inline uint8_t mode_write(uint8_t data) {
@@ -175,6 +209,24 @@ static inline uint8_t mode_write(uint8_t data) {
   return reg_write(MODE_ADDR, data);
 }
 
+static inline uint8_t peraddr_write(uint8_t data) {
+  if ( _hcd_data.peraddr == data ) return 0; // no need to change address
+
+  _hcd_data.peraddr = data;
+  return reg_write(PERADDR_ADDR, data);
+}
+
+static inline uint8_t hxfr_write(uint8_t data) {
+  _hcd_data.hxfr = data;
+  return reg_write(HXFR_ADDR, data);
+}
+
+static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
+  uint8_t tx_buf[1] = {reg | CMDBYTE_WRITE};
+  tuh_max3421e_spi_xfer_api(0, tx_buf, 1, NULL, 0, true);
+  tuh_max3421e_spi_xfer_api(0, buffer, len, NULL, 0, false);
+}
+
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -252,7 +304,7 @@ bool hcd_init(uint8_t rhport) {
   mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
   // Enable Connection IRQ
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ);
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ);
 
   #if 0
   // Note: if device is already connected, CONDET IRQ may not be triggered.
@@ -271,33 +323,6 @@ bool hcd_init(uint8_t rhport) {
   return true;
 }
 
-// Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
-  (void) rhport;
-
-  uint8_t hirq = reg_read(HIRQ_ADDR);
-  TU_LOG3_HEX(hirq);
-
-  if (hirq & HIRQ_CONDET_IRQ) {
-    tusb_speed_t speed = handle_connect_irq(rhport);
-
-    if (speed == TUSB_SPEED_INVALID) {
-      hcd_event_device_remove(rhport, true);
-    }else {
-      hcd_event_device_attach(rhport, true);
-    }
-  }
-
-  if (hirq & HIRQ_FRAME_IRQ) {
-    _hcd_data.frame_count++;
-  }
-
-  // clear all interrupt
-  if ( hirq ) {
-    reg_write(HIRQ_ADDR, hirq);
-  }
-}
-
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport) {
   (void) rhport;
@@ -359,7 +384,12 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   (void) dev_addr;
   (void) ep_desc;
 
-  return false;
+  uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
+  uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
+
+  _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
+
+  return true;
 }
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
@@ -384,12 +414,18 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 }
 
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
+bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
   (void) rhport;
-  (void) dev_addr;
+  (void) daddr;
   (void) setup_packet;
 
-  return false;
+  _hcd_data.ep[0][0].total_len = 8;
+
+  peraddr_write(daddr);
+  fifo_write(SUDFIFO_ADDR, setup_packet, 8);
+  hxfr_write(HXFR_SETUP);
+
+  return true;
 }
 
 // clear stall, data toggle is also reset to DATA0
@@ -401,4 +437,67 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  uint8_t hirq = reg_read(HIRQ_ADDR);
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_CONDET_IRQ) {
+    tusb_speed_t speed = handle_connect_irq(rhport);
+
+    if (speed == TUSB_SPEED_INVALID) {
+      hcd_event_device_remove(rhport, true);
+    }else {
+      hcd_event_device_attach(rhport, true);
+    }
+  }
+
+  if (hirq & HIRQ_FRAME_IRQ) {
+    _hcd_data.frame_count++;
+  }
+
+  if (hirq & HIRQ_HXFRDN_IRQ) {
+    uint8_t const hrsl = reg_read(HRSL_ADDR);
+    uint8_t const result = hrsl & HRSL_RESULT_MASK;
+    uint8_t xfer_result;
+
+    TU_LOG3("HRSL: %02X\r\n", hrsl);
+    switch(result) {
+      case HRSL_SUCCESS:
+        xfer_result = XFER_RESULT_SUCCESS;
+        break;
+
+      case HRSL_STALL:
+        xfer_result = XFER_RESULT_STALLED;
+        break;
+
+      default:
+        xfer_result = XFER_RESULT_FAILED;
+        break;
+    }
+
+    uint8_t ep_dir = 0;
+    uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+    uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
+
+    if ( xfer_type & HXFR_SETUP ) {
+      // SETUP transfer
+      ep_dir = 0;
+    }else if ( !(xfer_type & HXFR_OUT_NIN) ) {
+      // IN transfer
+      ep_dir = 1;
+    }
+
+    uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
+    uint16_t xferred_len = _hcd_data.ep[ep_num][ep_dir].total_len;
+
+    hcd_event_xfer_complete(_hcd_data.peraddr, ep_addr, xferred_len, xfer_result, true);
+  }
+
+  // clear all interrupt
+  if ( hirq ) {
+    reg_write(HIRQ_ADDR, hirq);
+  }
+}
+
 #endif
-- 
cgit v1.3.1


From e3f3179924f7c84c4bb3e69234720f9afc178727 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Aug 2023 15:08:12 +0700
Subject: able to get 8 byte descriptor, but read(RCVBC) always return 0

- rename max3421e to max3421
- fix incorrect bitmask for HCTL, fix initial device connect
- fix bus reset cause connect IRQ
---
 hw/bsp/nrf/family.c                         |  24 +-
 hw/bsp/nrf/family.cmake                     |   2 +-
 src/host/hcd.h                              |   2 +-
 src/portable/analog/max3421/hcd_max3421.c   | 613 ++++++++++++++++++++++++++++
 src/portable/analog/max3421e/hcd_max3421e.c | 503 -----------------------
 5 files changed, 624 insertions(+), 520 deletions(-)
 create mode 100644 src/portable/analog/max3421/hcd_max3421.c
 delete mode 100644 src/portable/analog/max3421e/hcd_max3421e.c

(limited to 'src')

diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 862f67bc7..45a5166a7 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -93,7 +93,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 }
 
 //------------- Host using MAX2341E -------------//
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
 void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
@@ -102,19 +102,17 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   tuh_int_handler(1);
 }
 
-static inline void max3421e_cs_assert(bool active) {
-  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
-}
-
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
 
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
-                               uint8_t * rx_buf, size_t rx_len, bool keep_cs) {
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
+  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
+}
 
-  max3421e_cs_assert(true);
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+  (void) rhport;
 
   nrfx_spim_xfer_desc_t xfer = {
       .p_tx_buffer = tx_buf,
@@ -123,11 +121,7 @@ bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx
       .rx_length   = rx_len,
   };
 
-  bool ret = (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
-
-  if ( !keep_cs ) max3421e_cs_assert(false);
-
-  return ret;
+  return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
 }
 
 #endif
@@ -218,10 +212,10 @@ void board_init(void) {
   if ( usb_reg & OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(USB_EVT_READY);
 #endif
 
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
   // manually manage CS
   nrf_gpio_cfg_output(MAX3421E_CS_PIN);
-  max3421e_cs_assert(false);
+  tuh_max3421_spi_cs_api(0, false);
 
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 8bf7bcb52..ff6b882ce 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -124,7 +124,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
-    ${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
+    ${TOP}/src/portable/analog/max3421/hcd_max3421.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 079877b79..1f01a1a2f 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -170,7 +170,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
 
 // Abort a queued transfer. Note: it can only abort transfer that has not been started
 // Return true if a queued transfer is aborted, false if there is no transfer to abort
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
new file mode 100644
index 000000000..edcb6ca6f
--- /dev/null
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -0,0 +1,613 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+#include "host/hcd.h"
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Command format is
+// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
+
+enum {
+  CMDBYTE_WRITE = 0x02,
+};
+
+enum {
+  RCVVFIFO_ADDR = 1u  << 3, // 0x08
+  SNDFIFO_ADDR  = 2u  << 3, // 0x10
+  SUDFIFO_ADDR  = 4u  << 3, // 0x20
+  RCVBC_ADDR    = 6u  << 3, // 0x30
+  SNDBC_ADDR    = 7u  << 3, // 0x38
+  USBIRQ_ADDR   = 13u << 3, // 0x68
+  USBIEN_ADDR   = 14u << 3, // 0x70
+  USBCTL_ADDR   = 15u << 3, // 0x78
+  CPUCTL_ADDR   = 16u << 3, // 0x80
+  PINCTL_ADDR   = 17u << 3, // 0x88
+  REVISION_ADDR = 18u << 3, // 0x90
+  HIRQ_ADDR     = 25u << 3, // 0xC8
+  HIEN_ADDR     = 26u << 3, // 0xD0
+  MODE_ADDR     = 27u << 3, // 0xD8
+  PERADDR_ADDR  = 28u << 3, // 0xE0
+  HCTL_ADDR     = 29u << 3, // 0xE8
+  HXFR_ADDR     = 30u << 3, // 0xF0
+  HRSL_ADDR     = 31u << 3, // 0xF8
+};
+
+enum {
+  USBIRQ_OSCOK_IRQ  = 1u << 0,
+  USBIRQ_NOVBUS_IRQ = 1u << 5,
+  USBIRQ_VBUS_IRQ   = 1u << 6,
+};
+
+enum {
+  USBCTL_PWRDOWN = 1u << 4,
+  USBCTL_CHIPRES = 1u << 5,
+};
+
+enum {
+  CPUCTL_IE        = 1u << 0,
+  CPUCTL_PULSEWID0 = 1u << 6,
+  CPUCTL_PULSEWID1 = 1u << 7,
+};
+
+enum {
+  PINCTL_GPXA     = 1u << 0,
+  PINCTL_GPXB     = 1u << 1,
+  PINCTL_POSINT   = 1u << 2,
+  PINCTL_INTLEVEL = 1u << 3,
+  PINCTL_FDUPSPI  = 1u << 4,
+};
+
+enum {
+  HIRQ_BUSEVENT_IRQ = 1u << 0,
+  HIRQ_RWU_IRQ      = 1u << 1,
+  HIRQ_RCVDAV_IRQ   = 1u << 2,
+  HIRQ_SNDBAV_IRQ   = 1u << 3,
+  HIRQ_SUSDN_IRQ    = 1u << 4,
+  HIRQ_CONDET_IRQ   = 1u << 5,
+  HIRQ_FRAME_IRQ    = 1u << 6,
+  HIRQ_HXFRDN_IRQ   = 1u << 7,
+};
+
+enum {
+  MODE_HOST      = 1u << 0,
+  MODE_LOWSPEED  = 1u << 1,
+  MODE_HUBPRE    = 1u << 2,
+  MODE_SOFKAENAB = 1u << 3,
+  MODE_SEPIRQ    = 1u << 4,
+  MODE_DELAYISO  = 1u << 5,
+  MODE_DMPULLDN  = 1u << 6,
+  MODE_DPPULLDN  = 1u << 7,
+};
+
+enum {
+  HCTL_BUSRST    = 1u << 0,
+  HCTL_FRMRST    = 1u << 1,
+  HCTL_SAMPLEBUS = 1u << 2,
+  HCTL_SIGRSM    = 1u << 3,
+  HCTL_RCVTOG0   = 1u << 4,
+  HCTL_RCVTOG1   = 1u << 5,
+  HCTL_SNDTOG0   = 1u << 6,
+  HCTL_SNDTOG1   = 1u << 7,
+};
+
+enum {
+  HXFR_EPNUM_MASK = 0x0f,
+  HXFR_SETUP      = 1u << 4,
+  HXFR_OUT_NIN    = 1u << 5,
+  HXFR_ISO        = 1u << 6,
+  HXFR_HS         = 1u << 7,
+};
+
+enum {
+  HRSL_RESULT_MASK = 0x0f,
+  HRSL_RCVTOGRD    = 1u << 4,
+  HRSL_SNDTOGRD    = 1u << 5,
+  HRSL_KSTATUS     = 1u << 6,
+  HRSL_JSTATUS     = 1u << 7,
+};
+
+enum {
+  HRSL_SUCCESS = 0,
+  HRSL_BUSY,
+  HRSL_BAD_REQ,
+  HRSL_UNDEF,
+  HRSL_NAK,
+  HRSL_STALL,
+  HRSL_TOG_ERR,
+  HRSL_WRONG_PID,
+  HRSL_BAD_BYTECOUNT,
+  HRSL_PID_ERR,
+  HRSL_PKT_ERR,
+  HRSL_CRC_ERR,
+  HRSL_K_ERR,
+  HRSL_J_ERR,
+  HRSL_TIMEOUT,
+  HRSL_BABBLE,
+};
+
+enum {
+  DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ
+};
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+typedef struct {
+  uint8_t xfer_type;
+  uint8_t data_toggle;
+  uint16_t packet_size;
+
+  uint16_t total_len;
+  uint16_t xferred_len;
+  uint8_t* buf;
+} hcd_ep_t;
+
+typedef struct {
+  bool inited;
+
+  // cached register
+  uint8_t sndbc;
+  uint8_t mode;
+  uint8_t peraddr;
+  uint8_t hxfr;
+
+  volatile uint16_t frame_count;
+
+  hcd_ep_t ep[8][2];
+} max2341_data_t;
+
+static max2341_data_t _hcd_data;
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
+
+//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
+  reg |= CMDBYTE_WRITE;
+
+  tuh_max3421_spi_cs_api(0, true);
+
+  tuh_max3421_spi_xfer_api(0, &reg, 1, NULL, 0);
+  tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0);
+
+  tuh_max3421_spi_cs_api(0, false);
+}
+
+// return HIRQ register since we are in full-duplex mode
+static uint8_t reg_write(uint8_t reg, uint8_t data) {
+  uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
+  uint8_t rx_buf[2] = {0, 0};
+
+  tuh_max3421_spi_cs_api(0, true);
+  tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(0, false);
+
+  TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
+  return rx_buf[0];
+}
+
+static uint8_t reg_read(uint8_t reg) {
+  uint8_t tx_buf[2] = {reg, 0};
+  uint8_t rx_buf[2] = {0, 0};
+
+  tuh_max3421_spi_cs_api(0, true);
+  bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(0, false);
+
+  return ret ? rx_buf[1] : 0;
+}
+
+static inline uint8_t mode_write(uint8_t data) {
+  _hcd_data.mode = data;
+  return reg_write(MODE_ADDR, data);
+}
+
+static inline uint8_t peraddr_write(uint8_t data) {
+  if ( _hcd_data.peraddr == data ) return 0; // no need to change address
+
+  _hcd_data.peraddr = data;
+  return reg_write(PERADDR_ADDR, data);
+}
+
+static inline uint8_t hxfr_write(uint8_t data) {
+  _hcd_data.hxfr = data;
+  return reg_write(HXFR_ADDR, data);
+}
+
+static inline uint8_t sndbc_write(uint8_t data) {
+  _hcd_data.sndbc = data;
+  return reg_write(SNDBC_ADDR, data);
+}
+
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+
+  return false;
+}
+
+tusb_speed_t handle_connect_irq(uint8_t rhport) {
+  (void) rhport;
+
+  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
+
+  tusb_speed_t speed;
+  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+
+  switch(jk) {
+    case 0x00:
+      // SEO is disconnected
+      speed = TUSB_SPEED_INVALID;
+      break;
+
+    case (HRSL_JSTATUS | HRSL_KSTATUS):
+      // SE1 is illegal
+      speed = TUSB_SPEED_INVALID;
+      break;
+
+    default: {
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      uint8_t const mode = reg_read(MODE_ADDR);
+      uint8_t const ls_bit = mode & MODE_LOWSPEED;
+
+      if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
+        speed = TUSB_SPEED_LOW;
+        new_mode |= MODE_LOWSPEED;
+      } else {
+        speed =  TUSB_SPEED_FULL;
+      }
+
+      new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device
+
+      break;
+    }
+  }
+
+  mode_write(new_mode);
+  TU_LOG2_INT(speed);
+  return speed;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport) {
+  (void) rhport;
+
+  tu_memclr(&_hcd_data, sizeof(_hcd_data));
+
+  // full duplex, interrupt negative edge
+  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI);
+
+  // reset
+  reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
+  reg_write(USBCTL_ADDR, 0);
+  while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
+    // wait for oscillator to stabilize
+  }
+
+  // Mode: Host and DP/DM pull down
+  mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
+
+  // bus reset, this will trigger CONDET IRQ if device is already connected
+  reg_write(HCTL_ADDR, HCTL_BUSRST);
+
+  // clear all previously pending IRQ
+  reg_write(HIRQ_ADDR, 0xff);
+
+  _hcd_data.inited = true;
+
+  // Enable Connection IRQ
+  reg_write(HIEN_ADDR, DEFAULT_HIEN);
+
+  // Enable Interrupt pin
+  reg_write(CPUCTL_ADDR, CPUCTL_IE);
+
+  return true;
+}
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void) rhport;
+  return (uint32_t ) _hcd_data.frame_count;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void) rhport;
+  return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  (void) rhport;
+  // Bus reset will also trigger CONDET IRQ, disable it
+  uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
+  reg_write(HIEN_ADDR, hien);
+
+  reg_write(HCTL_ADDR, HCTL_BUSRST);
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+  reg_write(HCTL_ADDR, 0);
+
+  // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
+  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
+  reg_write(HIEN_ADDR, DEFAULT_HIEN);
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void) rhport;
+  return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_desc;
+
+  uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
+  uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
+
+  _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
+
+  return true;
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  (void) rhport;
+
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  uint8_t const ep_dir = tu_edpt_dir(ep_addr);
+
+  hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir];
+
+  ep->buf = buffer;
+  ep->total_len = buflen;
+  ep->xferred_len = 0;
+
+  uint8_t hirq = peraddr_write(daddr);
+
+  uint8_t hctl = 0;
+  uint8_t hxfr = ep_num;
+  if ( ep_num == 0 ) {
+    ep->data_toggle = 1;
+    if ( buffer == NULL || buflen == 0 ) {
+      // ZLP for ACK stage
+      hxfr |= HXFR_HS;
+    }
+  } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
+    hxfr |= HXFR_ISO;
+  }
+
+  if ( 0 == ep_dir ) {
+    // Page 12: Programming BULK-OUT Transfers
+    TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ);
+
+    uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
+    fifo_write(SNDFIFO_ADDR, buffer, xact_len);
+    reg_write(SNDBC_ADDR, xact_len);
+
+    hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+    hxfr |= HXFR_OUT_NIN;
+  } else {
+    // Page 13: Programming BULK-IN Transfers
+    hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+  }
+
+  reg_write(HCTL_ADDR, hctl);
+  hxfr_write(hxfr);
+
+  return true;
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
+  (void) rhport;
+
+  hcd_ep_t* ep = &_hcd_data.ep[0][0];
+  ep->total_len  = 8;
+  ep->xferred_len = 0;
+
+  peraddr_write(daddr);
+  fifo_write(SUDFIFO_ADDR, setup_packet, 8);
+  hxfr_write(HXFR_SETUP);
+
+  return true;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+static void handle_xfer_done(uint8_t rhport) {
+  (void) rhport;
+
+  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const result = hrsl & HRSL_RESULT_MASK;
+  uint8_t xfer_result;
+
+  TU_LOG3("HRSL: %02X\r\n", hrsl);
+  switch(result) {
+    case HRSL_SUCCESS:
+      xfer_result = XFER_RESULT_SUCCESS;
+      break;
+
+    case HRSL_STALL:
+      xfer_result = XFER_RESULT_STALLED;
+      break;
+
+    case HRSL_BAD_REQ:
+      // occurred when initialized without any pending transfer. Skip for now
+      return;
+
+    default:
+      xfer_result = XFER_RESULT_FAILED;
+      break;
+  }
+
+  uint8_t ep_dir = 0;
+  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+  uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
+
+  hcd_ep_t * ep;
+
+  if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
+    // SETUP or OUT transfer
+    ep_dir = 0;
+    ep = &_hcd_data.ep[ep_num][ep_dir];
+
+    uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc;
+    ep->xferred_len += xact_len;
+
+    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+      hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
+    }else {
+      // more to transfer
+    }
+  } else {
+    // IN transfer
+    ep_dir = 1;
+    ep = &_hcd_data.ep[ep_num][ep_dir];
+    uint8_t const xact_len = reg_read(RCVBC_ADDR);
+    ep->xferred_len += xact_len;
+
+    // short packet or all bytes transferred
+    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+      hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
+    }else {
+      // more to transfer
+    }
+  }
+}
+
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  // not initialized, do nothing
+  if ( !_hcd_data.inited ) return;
+
+  uint8_t hirq = reg_read(HIRQ_ADDR);
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_FRAME_IRQ) {
+    _hcd_data.frame_count++;
+  }
+
+  if (hirq & HIRQ_CONDET_IRQ) {
+    tusb_speed_t speed = handle_connect_irq(rhport);
+
+    if (speed == TUSB_SPEED_INVALID) {
+      hcd_event_device_remove(rhport, true);
+    }else {
+      hcd_event_device_attach(rhport, true);
+    }
+  }
+
+  if (hirq & HIRQ_HXFRDN_IRQ) {
+    handle_xfer_done(rhport);
+  }
+
+  if ( hirq & HIRQ_RCVDAV_IRQ ) {
+    TU_LOG3("RCVDAV\r\n");
+    TU_LOG3_INT(reg_read(RCVBC_ADDR));
+  }
+
+  // clear all interrupt execept SNDBAV_IRQ
+  hirq &= ~HIRQ_SNDBAV_IRQ;
+  if ( hirq ) {
+    reg_write(HIRQ_ADDR, hirq);
+  }
+}
+
+#endif
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
deleted file mode 100644
index c9596f695..000000000
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ /dev/null
@@ -1,503 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2023 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
-
-#include "host/hcd.h"
-
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
-// Command format is
-// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
-
-enum {
-  CMDBYTE_WRITE = 0x02,
-};
-
-enum {
-  RCVVFIFO_ADDR = 1u  << 3, // 0x08
-  SNDFIFO_ADDR  = 2u  << 3, // 0x10
-  SUDFIFO_ADDR  = 4u  << 3, // 0x20
-  RCVBC_ADDR    = 6u  << 3, // 0x30
-  SNDBC_ADDR    = 7u  << 3, // 0x38
-  USBIRQ_ADDR   = 13u << 3, // 0x68
-  USBIEN_ADDR   = 14u << 3, // 0x70
-  USBCTL_ADDR   = 15u << 3, // 0x78
-  CPUCTL_ADDR   = 16u << 3, // 0x80
-  PINCTL_ADDR   = 17u << 3, // 0x88
-  REVISION_ADDR = 18u << 3, // 0x90
-  HIRQ_ADDR     = 25u << 3, // 0xC8
-  HIEN_ADDR     = 26u << 3, // 0xD0
-  MODE_ADDR     = 27u << 3, // 0xD8
-  PERADDR_ADDR  = 28u << 3, // 0xE0
-  HCTL_ADDR     = 29u << 3, // 0xE8
-  HXFR_ADDR     = 30u << 3, // 0xF0
-  HRSL_ADDR     = 31u << 3, // 0xF8
-};
-
-enum {
-  USBIRQ_OSCOK_IRQ  = 1u << 0,
-  USBIRQ_NOVBUS_IRQ = 1u << 5,
-  USBIRQ_VBUS_IRQ   = 1u << 6,
-};
-
-enum {
-  USBCTL_PWRDOWN = 1u << 4,
-  USBCTL_CHIPRES = 1u << 5,
-};
-
-enum {
-  CPUCTL_IE        = 1u << 0,
-  CPUCTL_PULSEWID0 = 1u << 6,
-  CPUCTL_PULSEWID1 = 1u << 7,
-};
-
-enum {
-  PINCTL_GPXA     = 1u << 0,
-  PINCTL_GPXB     = 1u << 1,
-  PINCTL_POSINT   = 1u << 2,
-  PINCTL_INTLEVEL = 1u << 3,
-  PINCTL_FDUPSPI  = 1u << 4,
-};
-
-enum {
-  HIRQ_BUSEVENT_IRQ = 1u << 0,
-  HIRQ_RWU_IRQ      = 1u << 1,
-  HIRQ_RCVDAV_IRQ   = 1u << 2,
-  HIRQ_SNDBAV_IRQ   = 1u << 3,
-  HIRQ_SUSDN_IRQ    = 1u << 4,
-  HIRQ_CONDET_IRQ   = 1u << 5,
-  HIRQ_FRAME_IRQ    = 1u << 6,
-  HIRQ_HXFRDN_IRQ   = 1u << 7,
-};
-
-enum {
-  MODE_HOST      = 1u << 0,
-  MODE_LOWSPEED  = 1u << 1,
-  MODE_HUBPRE    = 1u << 2,
-  MODE_SOFKAENAB = 1u << 3,
-  MODE_SEPIRQ    = 1u << 4,
-  MODE_DELAYISO  = 1u << 5,
-  MODE_DMPULLDN  = 1u << 6,
-  MODE_DPPULLDN  = 1u << 7,
-};
-
-enum {
-  HCTL_BUSRST    = 1u << 1,
-  HCTL_FRMRST    = 1u << 2,
-  HCTL_SAMPLEBUS = 1u << 3,
-  HCTL_SIGRSM    = 1u << 4,
-  HCTL_RCVTOG0   = 1u << 5,
-  HCTL_RCVTOG1   = 1u << 6,
-  HCTL_SNDTOG0   = 1u << 7,
-  HCTL_SNDTOG1   = 1u << 8,
-};
-
-enum {
-  HXFR_EPNUM_MASK = 0x0f,
-  HXFR_SETUP      = 1u << 4,
-  HXFR_OUT_NIN    = 1u << 5,
-  HXFR_ISO        = 1u << 6,
-  HXFR_HS         = 1u << 7,
-};
-
-enum {
-  HRSL_RESULT_MASK = 0x0f,
-  HRSL_RCVTOGRD    = 1u << 4,
-  HRSL_SNDTOGRD    = 1u << 5,
-  HRSL_KSTATUS     = 1u << 6,
-  HRSL_JSTATUS     = 1u << 7,
-};
-
-enum {
-  HRSL_SUCCESS = 0,
-  HRSL_BUSY,
-  HRSL_BAD_REQ,
-  HRSL_UNDEF,
-  HRSL_NAK,
-  HRSL_STALL,
-  HRSL_TOG_ERR,
-  HRSL_WRONG_PID,
-  HRSL_BAD_BYTECOUNT,
-  HRSL_PID_ERR,
-  HRSL_PKT_ERR,
-  HRSL_CRC_ERR,
-  HRSL_K_ERR,
-  HRSL_J_ERR,
-  HRSL_TIMEOUT,
-  HRSL_BABBLE,
-};
-
-
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
-typedef struct {
-  // cached register
-  uint8_t mode;
-  uint8_t peraddr;
-  uint8_t hxfr;
-
-  volatile uint16_t frame_count;
-
-  struct {
-    uint16_t packet_size;
-    uint16_t total_len;
-    uint8_t xfer_type;
-  }ep[8][2];
-} max2341e_data_t;
-
-static max2341e_data_t _hcd_data;
-
-//--------------------------------------------------------------------+
-// API: SPI transfer with MAX3421E, must be implemented by application
-//--------------------------------------------------------------------+
-
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
-                               uint8_t * rx_buf, size_t rx_len, bool keep_cs);
-//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
-
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
-// return HIRQ register since we are in full-duplex mode
-static uint8_t reg_write(uint8_t reg, uint8_t data) {
-  uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
-  uint8_t rx_buf[2] = {0, 0};
-  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false);
-  TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
-  return rx_buf[0];
-}
-
-static uint8_t reg_read(uint8_t reg) {
-  uint8_t tx_buf[2] = {reg, 0};
-  uint8_t rx_buf[2] = {0, 0};
-  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false) ? rx_buf[1] : 0;
-}
-
-static inline uint8_t mode_write(uint8_t data) {
-  _hcd_data.mode = data;
-  return reg_write(MODE_ADDR, data);
-}
-
-static inline uint8_t peraddr_write(uint8_t data) {
-  if ( _hcd_data.peraddr == data ) return 0; // no need to change address
-
-  _hcd_data.peraddr = data;
-  return reg_write(PERADDR_ADDR, data);
-}
-
-static inline uint8_t hxfr_write(uint8_t data) {
-  _hcd_data.hxfr = data;
-  return reg_write(HXFR_ADDR, data);
-}
-
-static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
-  uint8_t tx_buf[1] = {reg | CMDBYTE_WRITE};
-  tuh_max3421e_spi_xfer_api(0, tx_buf, 1, NULL, 0, true);
-  tuh_max3421e_spi_xfer_api(0, buffer, len, NULL, 0, false);
-}
-
-
-//--------------------------------------------------------------------+
-// Controller API
-//--------------------------------------------------------------------+
-
-// optional hcd configuration, called by tuh_configure()
-bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
-  (void) rhport;
-  (void) cfg_id;
-  (void) cfg_param;
-
-  return false;
-}
-
-tusb_speed_t handle_connect_irq(uint8_t rhport) {
-  (void) rhport;
-
-  uint8_t const hrsl = reg_read(HRSL_ADDR);
-  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
-
-  tusb_speed_t speed;
-  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
-
-  switch(jk) {
-    case 0x00:
-      // SEO is disconnected
-      speed = TUSB_SPEED_INVALID;
-      break;
-
-    case (HRSL_JSTATUS | HRSL_KSTATUS):
-      // SE1 is illegal
-      speed = TUSB_SPEED_INVALID;
-      break;
-
-    default: {
-      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
-      uint8_t const mode = reg_read(MODE_ADDR);
-      uint8_t const ls_bit = mode & MODE_LOWSPEED;
-
-      if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
-        speed = TUSB_SPEED_LOW;
-        new_mode |= MODE_LOWSPEED;
-      } else {
-        speed =  TUSB_SPEED_FULL;
-      }
-
-      new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device
-
-      break;
-    }
-  }
-
-  mode_write(new_mode);
-  TU_LOG2_INT(speed);
-  return speed;
-}
-
-// Initialize controller to host mode
-bool hcd_init(uint8_t rhport) {
-  (void) rhport;
-
-  tu_memclr(&_hcd_data, sizeof(_hcd_data));
-
-  // full duplex, interrupt level (should be configurable)
-  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
-
-  // reset
-  reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
-  reg_write(USBCTL_ADDR, 0);
-  while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
-    // wait for oscillator to stabilize
-  }
-
-  // Mode: Host and DP/DM pull down
-  mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
-
-  // Enable Connection IRQ
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ);
-
-  #if 0
-  // Note: if device is already connected, CONDET IRQ may not be triggered.
-  // We need to detect it by sampling bus signal. FIXME not working
-  reg_write(HCTL_ADDR, HCTL_SAMPLEBUS);
-  while ( reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS ) {}
-
-  if ( TUSB_SPEED_INVALID != handle_connect_irq(rhport) ) {
-    reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); // clear connect irq
-  }
-  #endif
-
-  // Enable Interrupt pin
-  reg_write(CPUCTL_ADDR, CPUCTL_IE);
-
-  return true;
-}
-
-// Enable USB interrupt
-void hcd_int_enable (uint8_t rhport) {
-  (void) rhport;
-}
-
-// Disable USB interrupt
-void hcd_int_disable(uint8_t rhport) {
-  (void) rhport;
-}
-
-// Get frame number (1ms)
-uint32_t hcd_frame_number(uint8_t rhport) {
-  (void) rhport;
-  return (uint32_t ) _hcd_data.frame_count;
-}
-
-//--------------------------------------------------------------------+
-// Port API
-//--------------------------------------------------------------------+
-
-// Get the current connect status of roothub port
-bool hcd_port_connect_status(uint8_t rhport) {
-  (void) rhport;
-  return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false;
-}
-
-// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
-// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
-void hcd_port_reset(uint8_t rhport) {
-  (void) rhport;
-  reg_write(HCTL_ADDR, HCTL_BUSRST);
-}
-
-// Complete bus reset sequence, may be required by some controllers
-void hcd_port_reset_end(uint8_t rhport) {
-  (void) rhport;
-  reg_write(HCTL_ADDR, 0);
-}
-
-// Get port link speed
-tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
-  (void) rhport;
-  return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
-}
-
-// HCD closes all opened endpoints belong to this device
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
-  (void) rhport;
-  (void) dev_addr;
-}
-
-//--------------------------------------------------------------------+
-// Endpoints API
-//--------------------------------------------------------------------+
-
-// Open an endpoint
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_desc;
-
-  uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
-  uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
-
-  _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
-
-  return true;
-}
-
-// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-  (void) buffer;
-  (void) buflen;
-
-  return false;
-}
-
-// Abort a queued transfer. Note: it can only abort transfer that has not been started
-// Return true if a queued transfer is aborted, false if there is no transfer to abort
-bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-
-  return false;
-}
-
-// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
-  (void) rhport;
-  (void) daddr;
-  (void) setup_packet;
-
-  _hcd_data.ep[0][0].total_len = 8;
-
-  peraddr_write(daddr);
-  fifo_write(SUDFIFO_ADDR, setup_packet, 8);
-  hxfr_write(HXFR_SETUP);
-
-  return true;
-}
-
-// clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-
-  return false;
-}
-
-// Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
-  uint8_t hirq = reg_read(HIRQ_ADDR);
-  TU_LOG3_HEX(hirq);
-
-  if (hirq & HIRQ_CONDET_IRQ) {
-    tusb_speed_t speed = handle_connect_irq(rhport);
-
-    if (speed == TUSB_SPEED_INVALID) {
-      hcd_event_device_remove(rhport, true);
-    }else {
-      hcd_event_device_attach(rhport, true);
-    }
-  }
-
-  if (hirq & HIRQ_FRAME_IRQ) {
-    _hcd_data.frame_count++;
-  }
-
-  if (hirq & HIRQ_HXFRDN_IRQ) {
-    uint8_t const hrsl = reg_read(HRSL_ADDR);
-    uint8_t const result = hrsl & HRSL_RESULT_MASK;
-    uint8_t xfer_result;
-
-    TU_LOG3("HRSL: %02X\r\n", hrsl);
-    switch(result) {
-      case HRSL_SUCCESS:
-        xfer_result = XFER_RESULT_SUCCESS;
-        break;
-
-      case HRSL_STALL:
-        xfer_result = XFER_RESULT_STALLED;
-        break;
-
-      default:
-        xfer_result = XFER_RESULT_FAILED;
-        break;
-    }
-
-    uint8_t ep_dir = 0;
-    uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
-    uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
-
-    if ( xfer_type & HXFR_SETUP ) {
-      // SETUP transfer
-      ep_dir = 0;
-    }else if ( !(xfer_type & HXFR_OUT_NIN) ) {
-      // IN transfer
-      ep_dir = 1;
-    }
-
-    uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
-    uint16_t xferred_len = _hcd_data.ep[ep_num][ep_dir].total_len;
-
-    hcd_event_xfer_complete(_hcd_data.peraddr, ep_addr, xferred_len, xfer_result, true);
-  }
-
-  // clear all interrupt
-  if ( hirq ) {
-    reg_write(HIRQ_ADDR, hirq);
-  }
-}
-
-#endif
-- 
cgit v1.3.1


From 2c237b1ae4b3ffd38fc74df29da63b01348afd1d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Aug 2023 17:49:28 +0700
Subject: able to complete 1st get device descriptor and set address

---
 src/portable/analog/max3421/hcd_max3421.c | 180 +++++++++++++++++++++---------
 1 file changed, 126 insertions(+), 54 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index edcb6ca6f..467d7410a 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -156,7 +156,7 @@ enum {
 };
 
 enum {
-  DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ
+  DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
 };
 
 //--------------------------------------------------------------------+
@@ -178,6 +178,8 @@ typedef struct {
 
   // cached register
   uint8_t sndbc;
+  uint8_t hirq;
+  uint8_t hien;
   uint8_t mode;
   uint8_t peraddr;
   uint8_t hxfr;
@@ -203,60 +205,86 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_
 //--------------------------------------------------------------------+
 
 static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
+  uint8_t const rhport = 0;
+  uint8_t hirq;
   reg |= CMDBYTE_WRITE;
 
-  tuh_max3421_spi_cs_api(0, true);
+  tuh_max3421_spi_cs_api(rhport, true);
 
-  tuh_max3421_spi_xfer_api(0, &reg, 1, NULL, 0);
-  tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0);
+  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
+
+  tuh_max3421_spi_cs_api(rhport, false);
 
-  tuh_max3421_spi_cs_api(0, false);
 }
 
-// return HIRQ register since we are in full-duplex mode
-static uint8_t reg_write(uint8_t reg, uint8_t data) {
+static void fifo_read(uint8_t * buffer, uint16_t len) {
+  uint8_t const rhport = 0;
+  uint8_t hirq;
+  uint8_t const reg = RCVVFIFO_ADDR;
+
+  tuh_max3421_spi_cs_api(rhport, true);
+
+  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
+
+  tuh_max3421_spi_cs_api(rhport, false);
+}
+
+static void reg_write(uint8_t reg, uint8_t data) {
+  uint8_t const rhport = 0;
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(0, true);
-  tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(0, false);
+  tuh_max3421_spi_cs_api(rhport, true);
+  tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(rhport, false);
 
-  TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
-  return rx_buf[0];
+  // HIRQ register since we are in full-duplex mode
+  _hcd_data.hirq = rx_buf[0];
+  TU_LOG3_HEX(_hcd_data.hirq);
 }
 
 static uint8_t reg_read(uint8_t reg) {
+  uint8_t const rhport = 0;
   uint8_t tx_buf[2] = {reg, 0};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(0, true);
-  bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(0, false);
+  tuh_max3421_spi_cs_api(rhport, true);
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(rhport, false);
 
+  _hcd_data.hirq = rx_buf[0];
   return ret ? rx_buf[1] : 0;
 }
 
-static inline uint8_t mode_write(uint8_t data) {
+static inline void hien_write(uint8_t data) {
+  _hcd_data.hien = data;
+  reg_write(HIEN_ADDR, data);
+}
+
+static inline void mode_write(uint8_t data) {
   _hcd_data.mode = data;
-  return reg_write(MODE_ADDR, data);
+  reg_write(MODE_ADDR, data);
 }
 
-static inline uint8_t peraddr_write(uint8_t data) {
-  if ( _hcd_data.peraddr == data ) return 0; // no need to change address
+static inline void peraddr_write(uint8_t data) {
+  if ( _hcd_data.peraddr == data ) return; // no need to change address
 
   _hcd_data.peraddr = data;
-  return reg_write(PERADDR_ADDR, data);
+  reg_write(PERADDR_ADDR, data);
 }
 
-static inline uint8_t hxfr_write(uint8_t data) {
+static inline void hxfr_write(uint8_t data) {
   _hcd_data.hxfr = data;
-  return reg_write(HXFR_ADDR, data);
+  reg_write(HXFR_ADDR, data);
 }
 
-static inline uint8_t sndbc_write(uint8_t data) {
+static inline void sndbc_write(uint8_t data) {
   _hcd_data.sndbc = data;
-  return reg_write(SNDBC_ADDR, data);
+  reg_write(SNDBC_ADDR, data);
 }
 
 
@@ -335,16 +363,16 @@ bool hcd_init(uint8_t rhport) {
   // Mode: Host and DP/DM pull down
   mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
-  // bus reset, this will trigger CONDET IRQ if device is already connected
-  reg_write(HCTL_ADDR, HCTL_BUSRST);
+  // frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
+  reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST);
 
   // clear all previously pending IRQ
   reg_write(HIRQ_ADDR, 0xff);
 
   _hcd_data.inited = true;
 
-  // Enable Connection IRQ
-  reg_write(HIEN_ADDR, DEFAULT_HIEN);
+  // Enable IRQ
+  hien_write(DEFAULT_HIEN);
 
   // Enable Interrupt pin
   reg_write(CPUCTL_ADDR, CPUCTL_IE);
@@ -383,8 +411,8 @@ bool hcd_port_connect_status(uint8_t rhport) {
 void hcd_port_reset(uint8_t rhport) {
   (void) rhport;
   // Bus reset will also trigger CONDET IRQ, disable it
-  uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
-  reg_write(HIEN_ADDR, hien);
+  uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
+  hien_write(hien);
 
   reg_write(HCTL_ADDR, HCTL_BUSRST);
 }
@@ -396,7 +424,7 @@ void hcd_port_reset_end(uint8_t rhport) {
 
   // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
   reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
-  reg_write(HIEN_ADDR, DEFAULT_HIEN);
+  hien_write(DEFAULT_HIEN);
 }
 
 // Get port link speed
@@ -426,6 +454,10 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
   _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
 
+  if (ep_desc->bEndpointAddress == 0) {
+    _hcd_data.ep[ep_num][1].packet_size = tu_edpt_packet_size(ep_desc);
+  }
+
   return true;
 }
 
@@ -442,15 +474,18 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->total_len = buflen;
   ep->xferred_len = 0;
 
-  uint8_t hirq = peraddr_write(daddr);
+  peraddr_write(daddr);
 
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
   if ( ep_num == 0 ) {
     ep->data_toggle = 1;
     if ( buffer == NULL || buflen == 0 ) {
-      // ZLP for ACK stage
+      // ZLP for ACK stage, use HS
       hxfr |= HXFR_HS;
+      hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
+      hxfr_write(hxfr);
+      return true;
     }
   } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
     hxfr |= HXFR_ISO;
@@ -458,7 +493,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
 
   if ( 0 == ep_dir ) {
     // Page 12: Programming BULK-OUT Transfers
-    TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ);
+    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
 
     uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
     fifo_write(SNDFIFO_ADDR, buffer, xact_len);
@@ -516,7 +551,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
   uint8_t const hrsl = reg_read(HRSL_ADDR);
   uint8_t const result = hrsl & HRSL_RESULT_MASK;
-  uint8_t xfer_result;
+  xfer_result_t xfer_result;
 
   TU_LOG3("HRSL: %02X\r\n", hrsl);
   switch(result) {
@@ -537,18 +572,21 @@ static void handle_xfer_done(uint8_t rhport) {
       break;
   }
 
-  uint8_t ep_dir = 0;
   uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
   uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
 
-  hcd_ep_t * ep;
-
   if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
     // SETUP or OUT transfer
-    ep_dir = 0;
-    ep = &_hcd_data.ep[ep_num][ep_dir];
+    hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
+    uint8_t xact_len;
+    if (xfer_type & HXFR_SETUP) {
+      xact_len = 8;
+    } else if ( xfer_type & HXFR_HS ) {
+      xact_len = 0;
+    } else {
+      xact_len = _hcd_data.sndbc;
+    }
 
-    uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc;
     ep->xferred_len += xact_len;
 
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -558,10 +596,27 @@ static void handle_xfer_done(uint8_t rhport) {
     }
   } else {
     // IN transfer
-    ep_dir = 1;
-    ep = &_hcd_data.ep[ep_num][ep_dir];
-    uint8_t const xact_len = reg_read(RCVBC_ADDR);
-    ep->xferred_len += xact_len;
+    hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+    uint8_t xact_len;
+
+    if ( xfer_type & HXFR_HS ) {
+      xact_len = 0;
+    } else {
+      // RCVDAV_IRQ can trigger 2 times (dual buffered)
+      while ( _hcd_data.hirq & HIRQ_RCVDAV_IRQ ) {
+        uint8_t rcvbc = reg_read(RCVBC_ADDR);
+        xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
+        if ( xact_len ) {
+          fifo_read(ep->buf, xact_len);
+          ep->buf += xact_len;
+          ep->xferred_len += xact_len;
+        }
+
+        // ack RCVDVAV IRQ
+        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
+        _hcd_data.hirq = reg_read(HIRQ_ADDR);
+      }
+    }
 
     // short packet or all bytes transferred
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -572,13 +627,35 @@ static void handle_xfer_done(uint8_t rhport) {
   }
 }
 
+#if CFG_TUSB_DEBUG >= 3
+void print_hirq(uint8_t hirq) {
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_HXFRDN_IRQ) TU_LOG3(" HXFRDN");
+  if (hirq & HIRQ_FRAME_IRQ)  TU_LOG3(" FRAME");
+  if (hirq & HIRQ_CONDET_IRQ) TU_LOG3(" CONDET");
+  if (hirq & HIRQ_SUSDN_IRQ)  TU_LOG3(" SUSDN");
+  if (hirq & HIRQ_SNDBAV_IRQ) TU_LOG3(" SNDBAV");
+  if (hirq & HIRQ_RCVDAV_IRQ) TU_LOG3(" RCVDAV");
+  if (hirq & HIRQ_RWU_IRQ)    TU_LOG3(" RWU");
+  if (hirq & HIRQ_BUSEVENT_IRQ) TU_LOG3(" BUSEVENT");
+
+  TU_LOG3("\r\n");
+}
+
+#else
+  #define print_hirq(hirq)
+#endif
+
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport) {
   // not initialized, do nothing
   if ( !_hcd_data.inited ) return;
 
-  uint8_t hirq = reg_read(HIRQ_ADDR);
-  TU_LOG3_HEX(hirq);
+  uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
+  if (!hirq) return;
+
+  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
@@ -598,13 +675,8 @@ void hcd_int_handler(uint8_t rhport) {
     handle_xfer_done(rhport);
   }
 
-  if ( hirq & HIRQ_RCVDAV_IRQ ) {
-    TU_LOG3("RCVDAV\r\n");
-    TU_LOG3_INT(reg_read(RCVBC_ADDR));
-  }
-
-  // clear all interrupt execept SNDBAV_IRQ
-  hirq &= ~HIRQ_SNDBAV_IRQ;
+  // clear all interrupt except SNDBAV_IRQ and RCVDAV_IRQ must be clear after pulling data from FIFO
+  hirq &= ~ (HIRQ_SNDBAV_IRQ | HIRQ_RCVDAV_IRQ);
   if ( hirq ) {
     reg_write(HIRQ_ADDR, hirq);
   }
-- 
cgit v1.3.1


From 3ed5d6c3724cfa9699d403a76a00f1b04672e2b5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 24 Aug 2023 16:27:12 +0700
Subject: complete enumeration

---
 hw/bsp/nrf/family.c                       |  5 ++-
 src/portable/analog/max3421/hcd_max3421.c | 68 +++++++++++++++++++------------
 2 files changed, 47 insertions(+), 26 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 45a5166a7..368763b84 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -105,6 +105,10 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
+void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled);
+}
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
@@ -241,7 +245,6 @@ void board_init(void) {
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
   nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
-  nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true);
 #endif
 
 }
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 467d7410a..514cf34b7 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -166,6 +166,7 @@ enum {
 typedef struct {
   uint8_t xfer_type;
   uint8_t data_toggle;
+  uint8_t xfer_complete;
   uint16_t packet_size;
 
   uint16_t total_len;
@@ -244,7 +245,6 @@ static void reg_write(uint8_t reg, uint8_t data) {
 
   // HIRQ register since we are in full-duplex mode
   _hcd_data.hirq = rx_buf[0];
-  TU_LOG3_HEX(_hcd_data.hirq);
 }
 
 static uint8_t reg_read(uint8_t reg) {
@@ -473,6 +473,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
+  ep->xfer_complete = 0;
 
   peraddr_write(daddr);
 
@@ -595,34 +596,19 @@ static void handle_xfer_done(uint8_t rhport) {
       // more to transfer
     }
   } else {
-    // IN transfer
+    // IN transfer: fifo data is already received in RCVDAV IRQ
     hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
-    uint8_t xact_len;
 
     if ( xfer_type & HXFR_HS ) {
-      xact_len = 0;
-    } else {
-      // RCVDAV_IRQ can trigger 2 times (dual buffered)
-      while ( _hcd_data.hirq & HIRQ_RCVDAV_IRQ ) {
-        uint8_t rcvbc = reg_read(RCVBC_ADDR);
-        xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
-        if ( xact_len ) {
-          fifo_read(ep->buf, xact_len);
-          ep->buf += xact_len;
-          ep->xferred_len += xact_len;
-        }
-
-        // ack RCVDVAV IRQ
-        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
-        _hcd_data.hirq = reg_read(HIRQ_ADDR);
-      }
+      ep->xfer_complete = 1;
     }
 
     // short packet or all bytes transferred
-    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+    if ( ep->xfer_complete ) {
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
+      hxfr_write(_hcd_data.hxfr);
     }
   }
 }
@@ -655,7 +641,7 @@ void hcd_int_handler(uint8_t rhport) {
   uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
   if (!hirq) return;
 
-  print_hirq(hirq);
+//  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
@@ -671,12 +657,44 @@ void hcd_int_handler(uint8_t rhport) {
     }
   }
 
-  if (hirq & HIRQ_HXFRDN_IRQ) {
-    handle_xfer_done(rhport);
+  // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
+  // not call this handler again. So we need to loop until all IRQ are cleared
+  while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) {
+    if ( hirq & HIRQ_RCVDAV_IRQ ) {
+      uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+      hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+      uint8_t xact_len;
+
+      // RCVDAV_IRQ can trigger 2 times (dual buffered)
+      while ( hirq & HIRQ_RCVDAV_IRQ ) {
+        uint8_t rcvbc = reg_read(RCVBC_ADDR);
+        xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
+        if ( xact_len ) {
+          fifo_read(ep->buf, xact_len);
+          ep->buf += xact_len;
+          ep->xferred_len += xact_len;
+        }
+
+        // ack RCVDVAV IRQ
+        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
+        hirq = reg_read(HIRQ_ADDR);
+      }
+
+      if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+        ep->xfer_complete = 1;
+      }
+    }
+
+    if ( hirq & HIRQ_HXFRDN_IRQ ) {
+      reg_write(HIRQ_ADDR, HIRQ_HXFRDN_IRQ);
+      handle_xfer_done(rhport);
+    }
+
+    hirq = reg_read(HIRQ_ADDR);
   }
 
-  // clear all interrupt except SNDBAV_IRQ and RCVDAV_IRQ must be clear after pulling data from FIFO
-  hirq &= ~ (HIRQ_SNDBAV_IRQ | HIRQ_RCVDAV_IRQ);
+  // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
+  hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
     reg_write(HIRQ_ADDR, hirq);
   }
-- 
cgit v1.3.1


From 344932d27e1f65932ce922b639370ecc4fff2153 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 24 Aug 2023 16:27:32 +0700
Subject: add tuh_max3421e_int_api(), retry control if received NAK

---
 src/portable/analog/max3421/hcd_max3421.c | 60 ++++++++++++++++++++-----------
 1 file changed, 40 insertions(+), 20 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 514cf34b7..b4f75e392 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -28,6 +28,7 @@
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
+#include <stdatomic.h>
 #include "host/hcd.h"
 
 //--------------------------------------------------------------------+
@@ -164,11 +165,15 @@ enum {
 //--------------------------------------------------------------------+
 
 typedef struct {
-  uint8_t xfer_type;
-  uint8_t data_toggle;
-  uint8_t xfer_complete;
   uint16_t packet_size;
 
+  struct TU_ATTR_PACKED {
+    uint8_t is_iso        : 1;
+    uint8_t data_toggle   : 1;
+    uint8_t xfer_queued   : 1;
+    uint8_t xfer_complete : 1;
+  };
+
   uint16_t total_len;
   uint16_t xferred_len;
   uint8_t* buf;
@@ -176,6 +181,7 @@ typedef struct {
 
 typedef struct {
   bool inited;
+  atomic_bool busy; // busy transferring
 
   // cached register
   uint8_t sndbc;
@@ -198,8 +204,7 @@ static max2341_data_t _hcd_data;
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
-
-//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
+void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 
 //--------------------------------------------------------------------+
 //
@@ -348,6 +353,9 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
+  TU_LOG2_INT(sizeof(hcd_ep_t));
+  TU_LOG2_INT(sizeof(max2341_data_t));
+
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
   // full duplex, interrupt negative edge
@@ -382,12 +390,12 @@ bool hcd_init(uint8_t rhport) {
 
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport) {
-  (void) rhport;
+  tuh_max3421e_int_api(rhport, true);
 }
 
 // Disable USB interrupt
 void hcd_int_disable(uint8_t rhport) {
-  (void) rhport;
+  tuh_max3421e_int_api(rhport, false);
 }
 
 // Get frame number (1ms)
@@ -447,17 +455,20 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
   (void) rhport;
   (void) dev_addr;
-  (void) ep_desc;
 
   uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
   uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
 
-  _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
+  hcd_ep_t * ep = &_hcd_data.ep[ep_num][ep_dir];
+
+  ep->packet_size = tu_edpt_packet_size(ep_desc);
 
   if (ep_desc->bEndpointAddress == 0) {
-    _hcd_data.ep[ep_num][1].packet_size = tu_edpt_packet_size(ep_desc);
+    _hcd_data.ep[0][1].packet_size = ep->packet_size;
   }
 
+  ep->is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0;
+
   return true;
 }
 
@@ -474,11 +485,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->total_len = buflen;
   ep->xferred_len = 0;
   ep->xfer_complete = 0;
+  ep->xfer_queued = 1;
 
   peraddr_write(daddr);
 
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
+
   if ( ep_num == 0 ) {
     ep->data_toggle = 1;
     if ( buffer == NULL || buflen == 0 ) {
@@ -488,7 +501,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       hxfr_write(hxfr);
       return true;
     }
-  } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
+  } else if ( ep->is_iso ) {
     hxfr |= HXFR_ISO;
   }
 
@@ -551,11 +564,13 @@ static void handle_xfer_done(uint8_t rhport) {
   (void) rhport;
 
   uint8_t const hrsl = reg_read(HRSL_ADDR);
-  uint8_t const result = hrsl & HRSL_RESULT_MASK;
+  uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
+  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+
   xfer_result_t xfer_result;
 
-  TU_LOG3("HRSL: %02X\r\n", hrsl);
-  switch(result) {
+  //TU_LOG3("HRSL: %02X\r\n", hrsl);
+  switch(hresult) {
     case HRSL_SUCCESS:
       xfer_result = XFER_RESULT_SUCCESS;
       break;
@@ -568,21 +583,26 @@ static void handle_xfer_done(uint8_t rhport) {
       // occurred when initialized without any pending transfer. Skip for now
       return;
 
+    case HRSL_NAK:
+      // NAK on control, retry immediately
+      if (ep_num == 0) hxfr_write(_hcd_data.hxfr);
+      return;
+
     default:
       xfer_result = XFER_RESULT_FAILED;
       break;
   }
 
-  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
-  uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
+  uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
 
-  if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
+  if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) {
     // SETUP or OUT transfer
     hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
     uint8_t xact_len;
-    if (xfer_type & HXFR_SETUP) {
+
+    if ( hxfr_type & HXFR_SETUP) {
       xact_len = 8;
-    } else if ( xfer_type & HXFR_HS ) {
+    } else if ( hxfr_type & HXFR_HS ) {
       xact_len = 0;
     } else {
       xact_len = _hcd_data.sndbc;
@@ -599,7 +619,7 @@ static void handle_xfer_done(uint8_t rhport) {
     // IN transfer: fifo data is already received in RCVDAV IRQ
     hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
 
-    if ( xfer_type & HXFR_HS ) {
+    if ( hxfr_type & HXFR_HS ) {
       ep->xfer_complete = 1;
     }
 
-- 
cgit v1.3.1


From e6cf125e537125fc7303afc7d0703a3de6b8b334 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 24 Aug 2023 16:46:20 +0700
Subject: save data toggle, always retry NAK. work with msc device

---
 src/portable/analog/max3421/hcd_max3421.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index b4f75e392..9579409c5 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -492,7 +492,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
 
-  if ( ep_num == 0 ) {
+  if ( ep->is_iso ) {
+    hxfr |= HXFR_ISO;
+  } else if ( ep_num == 0 ) {
     ep->data_toggle = 1;
     if ( buffer == NULL || buflen == 0 ) {
       // ZLP for ACK stage, use HS
@@ -501,8 +503,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       hxfr_write(hxfr);
       return true;
     }
-  } else if ( ep->is_iso ) {
-    hxfr |= HXFR_ISO;
   }
 
   if ( 0 == ep_dir ) {
@@ -511,7 +511,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
 
     uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
     fifo_write(SNDFIFO_ADDR, buffer, xact_len);
-    reg_write(SNDBC_ADDR, xact_len);
+    sndbc_write(xact_len);
 
     hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
     hxfr |= HXFR_OUT_NIN;
@@ -585,7 +585,10 @@ static void handle_xfer_done(uint8_t rhport) {
 
     case HRSL_NAK:
       // NAK on control, retry immediately
-      if (ep_num == 0) hxfr_write(_hcd_data.hxfr);
+      //if (ep_num == 0)
+      {
+        hxfr_write(_hcd_data.hxfr);
+      }
       return;
 
     default:
@@ -609,8 +612,14 @@ static void handle_xfer_done(uint8_t rhport) {
     }
 
     ep->xferred_len += xact_len;
+    ep->buf += xact_len;
 
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+      if ( ep_num ) {
+        // save data toggle for non-control
+        ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+      }
+
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
@@ -625,6 +634,11 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
+      if ( ep_num ) {
+        // save data toggle for non-control
+        ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+      }
+
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
-- 
cgit v1.3.1


From f5ebc1700f4bde1cc166bf5f3d8eb69d8832722a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 12:12:44 +0700
Subject: add spi lock with interrupt enable/disable

---
 src/portable/analog/max3421/hcd_max3421.c | 176 +++++++++++++++---------------
 1 file changed, 91 insertions(+), 85 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 9579409c5..0144deca6 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -180,7 +180,6 @@ typedef struct {
 } hcd_ep_t;
 
 typedef struct {
-  bool inited;
   atomic_bool busy; // busy transferring
 
   // cached register
@@ -194,6 +193,8 @@ typedef struct {
   volatile uint16_t frame_count;
 
   hcd_ep_t ep[8][2];
+
+  OSAL_MUTEX_DEF(spi_mutex);
 } max2341_data_t;
 
 static max2341_data_t _hcd_data;
@@ -210,86 +211,106 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 //
 //--------------------------------------------------------------------+
 
-static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
-  uint8_t const rhport = 0;
+static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
+  // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
+  if (!in_isr) {
+    tuh_max3421e_int_api(rhport, false);
+  }
+
+  // assert CS
+  tuh_max3421_spi_cs_api(rhport, true);
+}
+
+static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
+  // de-assert CS
+  tuh_max3421_spi_cs_api(rhport, false);
+
+  // mutex unlock and re-enable interrupt
+  if (!in_isr) {
+    tuh_max3421e_int_api(rhport, true);
+  }
+}
+
+static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
   uint8_t hirq;
   reg |= CMDBYTE_WRITE;
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
 
   tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
   _hcd_data.hirq = hirq;
   tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
 
-  tuh_max3421_spi_cs_api(rhport, false);
+  max3421_spi_unlock(rhport, in_isr);
 
 }
 
-static void fifo_read(uint8_t * buffer, uint16_t len) {
-  uint8_t const rhport = 0;
+static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
   uint8_t hirq;
   uint8_t const reg = RCVVFIFO_ADDR;
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
 
   tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0);
   _hcd_data.hirq = hirq;
   tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
 
-  tuh_max3421_spi_cs_api(rhport, false);
+  max3421_spi_unlock(rhport, in_isr);
 }
 
-static void reg_write(uint8_t reg, uint8_t data) {
-  uint8_t const rhport = 0;
+static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
+
   tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(rhport, false);
+
+  max3421_spi_unlock(rhport, in_isr);
 
   // HIRQ register since we are in full-duplex mode
   _hcd_data.hirq = rx_buf[0];
 }
 
-static uint8_t reg_read(uint8_t reg) {
-  uint8_t const rhport = 0;
+static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
   uint8_t tx_buf[2] = {reg, 0};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
+
   bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(rhport, false);
+
+  max3421_spi_unlock(rhport, in_isr);
 
   _hcd_data.hirq = rx_buf[0];
   return ret ? rx_buf[1] : 0;
 }
 
-static inline void hien_write(uint8_t data) {
+static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hien = data;
-  reg_write(HIEN_ADDR, data);
+  reg_write(rhport, HIEN_ADDR, data, in_isr);
 }
 
-static inline void mode_write(uint8_t data) {
+static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.mode = data;
-  reg_write(MODE_ADDR, data);
+  reg_write(rhport, MODE_ADDR, data, in_isr);
 }
 
-static inline void peraddr_write(uint8_t data) {
+static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
   if ( _hcd_data.peraddr == data ) return; // no need to change address
 
   _hcd_data.peraddr = data;
-  reg_write(PERADDR_ADDR, data);
+  reg_write(rhport, PERADDR_ADDR, data, in_isr);
 }
 
-static inline void hxfr_write(uint8_t data) {
+static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hxfr = data;
-  reg_write(HXFR_ADDR, data);
+  reg_write(rhport, HXFR_ADDR, data, in_isr);
 }
 
-static inline void sndbc_write(uint8_t data) {
+static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.sndbc = data;
-  reg_write(SNDBC_ADDR, data);
+  reg_write(rhport, SNDBC_ADDR, data, in_isr);
 }
 
 
@@ -307,9 +328,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
 }
 
 tusb_speed_t handle_connect_irq(uint8_t rhport) {
-  (void) rhport;
-
-  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
 
   tusb_speed_t speed;
@@ -328,7 +347,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 
     default: {
       // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
-      uint8_t const mode = reg_read(MODE_ADDR);
+      uint8_t const mode = reg_read(rhport, MODE_ADDR, true);
       uint8_t const ls_bit = mode & MODE_LOWSPEED;
 
       if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
@@ -344,7 +363,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
     }
   }
 
-  mode_write(new_mode);
+  mode_write(rhport, new_mode, true);
   TU_LOG2_INT(speed);
   return speed;
 }
@@ -358,32 +377,32 @@ bool hcd_init(uint8_t rhport) {
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
+  hcd_int_disable(rhport);
+
   // full duplex, interrupt negative edge
-  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI);
+  reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
   // reset
-  reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
-  reg_write(USBCTL_ADDR, 0);
-  while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
+  reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
+  reg_write(rhport, USBCTL_ADDR, 0, false);
+  while( !(reg_read(rhport, USBIRQ_ADDR, false) & USBIRQ_OSCOK_IRQ) ) {
     // wait for oscillator to stabilize
   }
 
   // Mode: Host and DP/DM pull down
-  mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
+  mode_write(rhport, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST, false);
 
   // frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
-  reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST);
+  reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
 
   // clear all previously pending IRQ
-  reg_write(HIRQ_ADDR, 0xff);
-
-  _hcd_data.inited = true;
+  reg_write(rhport, HIRQ_ADDR, 0xff, false);
 
   // Enable IRQ
-  hien_write(DEFAULT_HIEN);
+  hien_write(rhport, DEFAULT_HIEN, false);
 
   // Enable Interrupt pin
-  reg_write(CPUCTL_ADDR, CPUCTL_IE);
+  reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
 
   return true;
 }
@@ -417,22 +436,20 @@ bool hcd_port_connect_status(uint8_t rhport) {
 // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
 // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport) {
-  (void) rhport;
   // Bus reset will also trigger CONDET IRQ, disable it
   uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
-  hien_write(hien);
+  hien_write(rhport, hien, false);
 
-  reg_write(HCTL_ADDR, HCTL_BUSRST);
+  reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false);
 }
 
 // Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport) {
-  (void) rhport;
-  reg_write(HCTL_ADDR, 0);
+  reg_write(rhport, HCTL_ADDR, 0, false);
 
   // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
-  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
-  hien_write(DEFAULT_HIEN);
+  reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false);
+  hien_write(rhport, DEFAULT_HIEN, false);
 }
 
 // Get port link speed
@@ -487,7 +504,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->xfer_complete = 0;
   ep->xfer_queued = 1;
 
-  peraddr_write(daddr);
+  peraddr_write(rhport, daddr, false);
 
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
@@ -500,7 +517,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       // ZLP for ACK stage, use HS
       hxfr |= HXFR_HS;
       hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
-      hxfr_write(hxfr);
+      hxfr_write(rhport, hxfr, false);
       return true;
     }
   }
@@ -510,8 +527,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
     TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
 
     uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
-    fifo_write(SNDFIFO_ADDR, buffer, xact_len);
-    sndbc_write(xact_len);
+    fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
+    sndbc_write(rhport, xact_len, false);
 
     hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
     hxfr |= HXFR_OUT_NIN;
@@ -520,8 +537,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
     hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
   }
 
-  reg_write(HCTL_ADDR, hctl);
-  hxfr_write(hxfr);
+  reg_write(rhport, HCTL_ADDR, hctl, false);
+  hxfr_write(rhport, hxfr, false);
 
   return true;
 }
@@ -544,9 +561,9 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->total_len  = 8;
   ep->xferred_len = 0;
 
-  peraddr_write(daddr);
-  fifo_write(SUDFIFO_ADDR, setup_packet, 8);
-  hxfr_write(HXFR_SETUP);
+  peraddr_write(rhport, daddr, false);
+  fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
+  hxfr_write(rhport, HXFR_SETUP, false);
 
   return true;
 }
@@ -561,9 +578,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 }
 
 static void handle_xfer_done(uint8_t rhport) {
-  (void) rhport;
-
-  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
   uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
 
@@ -587,7 +602,7 @@ static void handle_xfer_done(uint8_t rhport) {
       // NAK on control, retry immediately
       //if (ep_num == 0)
       {
-        hxfr_write(_hcd_data.hxfr);
+        hxfr_write(rhport, _hcd_data.hxfr, true);
       }
       return;
 
@@ -615,11 +630,8 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
-      if ( ep_num ) {
-        // save data toggle for non-control
-        ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
-      }
-
+      // save data toggle
+      ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
@@ -634,15 +646,12 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      if ( ep_num ) {
-        // save data toggle for non-control
-        ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
-      }
-
+      // save data toggle
+      ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
-      hxfr_write(_hcd_data.hxfr);
+      hxfr_write(rhport, _hcd_data.hxfr, true);
     }
   }
 }
@@ -669,10 +678,7 @@ void print_hirq(uint8_t hirq) {
 
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport) {
-  // not initialized, do nothing
-  if ( !_hcd_data.inited ) return;
-
-  uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
+  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
   if (!hirq) return;
 
 //  print_hirq(hirq);
@@ -701,17 +707,17 @@ void hcd_int_handler(uint8_t rhport) {
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
       while ( hirq & HIRQ_RCVDAV_IRQ ) {
-        uint8_t rcvbc = reg_read(RCVBC_ADDR);
+        uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true);
         xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
         if ( xact_len ) {
-          fifo_read(ep->buf, xact_len);
+          fifo_read(rhport, ep->buf, xact_len, true);
           ep->buf += xact_len;
           ep->xferred_len += xact_len;
         }
 
         // ack RCVDVAV IRQ
-        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
-        hirq = reg_read(HIRQ_ADDR);
+        reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true);
+        hirq = reg_read(rhport, HIRQ_ADDR, true);
       }
 
       if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -720,17 +726,17 @@ void hcd_int_handler(uint8_t rhport) {
     }
 
     if ( hirq & HIRQ_HXFRDN_IRQ ) {
-      reg_write(HIRQ_ADDR, HIRQ_HXFRDN_IRQ);
+      reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true);
       handle_xfer_done(rhport);
     }
 
-    hirq = reg_read(HIRQ_ADDR);
+    hirq = reg_read(rhport, HIRQ_ADDR, true);
   }
 
   // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
   hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
-    reg_write(HIRQ_ADDR, hirq);
+    reg_write(rhport, HIRQ_ADDR, hirq, true);
   }
 }
 
-- 
cgit v1.3.1


From 09ceaa6cf37d29e605495716fc2497ed5228a37f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 13:18:47 +0700
Subject: add osal mutex for spi

---
 src/portable/analog/max3421/hcd_max3421.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 0144deca6..09845ffe4 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -194,7 +194,10 @@ typedef struct {
 
   hcd_ep_t ep[8][2];
 
-  OSAL_MUTEX_DEF(spi_mutex);
+  OSAL_MUTEX_DEF(spi_mutexdef);
+#if OSAL_MUTEX_REQUIRED
+  osal_mutex_t spi_mutex;
+#endif
 } max2341_data_t;
 
 static max2341_data_t _hcd_data;
@@ -215,6 +218,7 @@ static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, false);
+    (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
   }
 
   // assert CS
@@ -228,6 +232,7 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
   // mutex unlock and re-enable interrupt
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, true);
+    (void) osal_mutex_unlock(_hcd_data.spi_mutex);
   }
 }
 
@@ -372,12 +377,16 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
+  hcd_int_disable(rhport);
+
   TU_LOG2_INT(sizeof(hcd_ep_t));
   TU_LOG2_INT(sizeof(max2341_data_t));
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
-  hcd_int_disable(rhport);
+#if OSAL_MUTEX_REQUIRED
+  _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
+#endif
 
   // full duplex, interrupt negative edge
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
-- 
cgit v1.3.1


From ecf2f910424b53fecc3ca82ae410f054518cc752 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 16:36:28 +0700
Subject: use endpoint pool for more flexible multiple devices support

---
 src/portable/analog/max3421/hcd_max3421.c | 178 ++++++++++++++++++++----------
 1 file changed, 121 insertions(+), 57 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 09845ffe4..b0325f240 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -165,22 +165,26 @@ enum {
 //--------------------------------------------------------------------+
 
 typedef struct {
-  uint16_t packet_size;
-
   struct TU_ATTR_PACKED {
+    uint8_t ep_dir        : 1;
     uint8_t is_iso        : 1;
     uint8_t data_toggle   : 1;
-    uint8_t xfer_queued   : 1;
+    uint8_t xfer_pending  : 1;
     uint8_t xfer_complete : 1;
   };
+  struct TU_ATTR_PACKED {
+    uint8_t daddr : 4;
+    uint8_t ep_num : 4;
+  };
 
+  uint16_t packet_size;
   uint16_t total_len;
   uint16_t xferred_len;
   uint8_t* buf;
-} hcd_ep_t;
+} max3421_ep_t;
 
 typedef struct {
-  atomic_bool busy; // busy transferring
+  atomic_flag busy; // busy transferring
 
   // cached register
   uint8_t sndbc;
@@ -192,15 +196,16 @@ typedef struct {
 
   volatile uint16_t frame_count;
 
-  hcd_ep_t ep[8][2];
+  max3421_ep_t ep0_addr0; // control endpoint for addr0
+  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL];
 
   OSAL_MUTEX_DEF(spi_mutexdef);
 #if OSAL_MUTEX_REQUIRED
   osal_mutex_t spi_mutex;
 #endif
-} max2341_data_t;
+} max3421_data_t;
 
-static max2341_data_t _hcd_data;
+static max3421_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
@@ -211,7 +216,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 
 //--------------------------------------------------------------------+
-//
+// SPI Helper
 //--------------------------------------------------------------------+
 
 static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
@@ -318,6 +323,44 @@ static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
   reg_write(rhport, SNDBC_ADDR, data, in_isr);
 }
 
+//--------------------------------------------------------------------+
+// Endpoint helper
+//--------------------------------------------------------------------+
+
+static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  for(size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    // for control endpoint, skip direction check
+    if ( daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0) ) {
+      return ep;
+    }
+  }
+
+  return NULL;
+}
+
+// daddr = 0 and ep_num = 0 means find a free (allocate) endpoint
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) {
+  return find_ep_not_addr0(0, 0, 0);
+}
+
+// free all endpoints belong to device address
+static void free_ep(uint8_t daddr) {
+  for (size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (ep->daddr == daddr) {
+      tu_memclr(ep, sizeof(max3421_ep_t));
+    }
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  if (daddr == 0 && ep_num == 0) {
+    return &_hcd_data.ep0_addr0;
+  }else{
+    return find_ep_not_addr0(daddr, ep_num, ep_dir);
+  }
+}
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -379,8 +422,8 @@ bool hcd_init(uint8_t rhport) {
 
   hcd_int_disable(rhport);
 
-  TU_LOG2_INT(sizeof(hcd_ep_t));
-  TU_LOG2_INT(sizeof(max2341_data_t));
+  TU_LOG2_INT(sizeof(max3421_ep_t));
+  TU_LOG2_INT(sizeof(max3421_data_t));
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
@@ -478,22 +521,29 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
 //--------------------------------------------------------------------+
 
 // Open an endpoint
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc) {
   (void) rhport;
-  (void) dev_addr;
+  (void) daddr;
 
   uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
   uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
 
-  hcd_ep_t * ep = &_hcd_data.ep[ep_num][ep_dir];
-
-  ep->packet_size = tu_edpt_packet_size(ep_desc);
+  max3421_ep_t * ep;
+  if (daddr == 0 && ep_num == 0) {
+    ep = &_hcd_data.ep0_addr0;
+  }else {
+    ep = allocate_ep();
+    TU_ASSERT(ep);
+    ep->daddr = daddr;
+    ep->ep_num = ep_num;
+    ep->ep_dir = ep_dir;
+  }
 
-  if (ep_desc->bEndpointAddress == 0) {
-    _hcd_data.ep[0][1].packet_size = ep->packet_size;
+  if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) {
+    ep->is_iso = 1;
   }
 
-  ep->is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0;
+  ep->packet_size = tu_edpt_packet_size(ep_desc);
 
   return true;
 }
@@ -505,49 +555,54 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   uint8_t const ep_num = tu_edpt_number(ep_addr);
   uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
-  hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir];
+  max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
+  TU_ASSERT(ep);
 
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
   ep->xfer_complete = 0;
-  ep->xfer_queued = 1;
-
-  peraddr_write(rhport, daddr, false);
-
-  uint8_t hctl = 0;
-  uint8_t hxfr = ep_num;
-
-  if ( ep->is_iso ) {
-    hxfr |= HXFR_ISO;
-  } else if ( ep_num == 0 ) {
-    ep->data_toggle = 1;
-    if ( buffer == NULL || buflen == 0 ) {
-      // ZLP for ACK stage, use HS
-      hxfr |= HXFR_HS;
-      hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
-      hxfr_write(rhport, hxfr, false);
-      return true;
+  ep->xfer_pending = 1;
+
+  // carry out transfer if not busy
+//  if ( atomic_flag_test_and_set(&_hcd_data.busy) )
+  {
+    peraddr_write(rhport, daddr, false);
+
+    uint8_t hctl = 0;
+    uint8_t hxfr = ep_num;
+
+    if ( ep->is_iso ) {
+      hxfr |= HXFR_ISO;
+    } else if ( ep_num == 0 ) {
+      ep->data_toggle = 1;
+      if ( buffer == NULL || buflen == 0 ) {
+        // ZLP for ACK stage, use HS
+        hxfr |= HXFR_HS;
+        hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
+        hxfr_write(rhport, hxfr, false);
+        return true;
+      }
     }
-  }
 
-  if ( 0 == ep_dir ) {
-    // Page 12: Programming BULK-OUT Transfers
-    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
+    if ( 0 == ep_dir ) {
+      // Page 12: Programming BULK-OUT Transfers
+      TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
 
-    uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
-    fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
-    sndbc_write(rhport, xact_len, false);
+      uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
+      fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
+      sndbc_write(rhport, xact_len, false);
 
-    hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-    hxfr |= HXFR_OUT_NIN;
-  } else {
-    // Page 13: Programming BULK-IN Transfers
-    hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
-  }
+      hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+      hxfr |= HXFR_OUT_NIN;
+    } else {
+      // Page 13: Programming BULK-IN Transfers
+      hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+    }
 
-  reg_write(rhport, HCTL_ADDR, hctl, false);
-  hxfr_write(rhport, hxfr, false);
+    reg_write(rhport, HCTL_ADDR, hctl, false);
+    hxfr_write(rhport, hxfr, false);
+  }
 
   return true;
 }
@@ -566,7 +621,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
   (void) rhport;
 
-  hcd_ep_t* ep = &_hcd_data.ep[0][0];
+  max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
   ep->total_len  = 8;
   ep->xferred_len = 0;
 
@@ -624,7 +679,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
   if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) {
     // SETUP or OUT transfer
-    hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
+    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 0);
     uint8_t xact_len;
 
     if ( hxfr_type & HXFR_SETUP) {
@@ -644,10 +699,15 @@ static void handle_xfer_done(uint8_t rhport) {
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
+      xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, true);
+      sndbc_write(rhport, xact_len, true);
+
+      hxfr_write(rhport, _hcd_data.hxfr, true);
     }
   } else {
     // IN transfer: fifo data is already received in RCVDAV IRQ
-    hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
 
     if ( hxfr_type & HXFR_HS ) {
       ep->xfer_complete = 1;
@@ -702,6 +762,10 @@ void hcd_int_handler(uint8_t rhport) {
     if (speed == TUSB_SPEED_INVALID) {
       hcd_event_device_remove(rhport, true);
     }else {
+      // FIXME multiple MAX3421 rootdevice address is not 1
+      uint8_t const daddr = 1;
+      free_ep(daddr);
+
       hcd_event_device_attach(rhport, true);
     }
   }
@@ -710,8 +774,8 @@ void hcd_int_handler(uint8_t rhport) {
   // not call this handler again. So we need to loop until all IRQ are cleared
   while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) {
     if ( hirq & HIRQ_RCVDAV_IRQ ) {
-      uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
-      hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+      uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+      max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
       uint8_t xact_len;
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
-- 
cgit v1.3.1


From ac00b9147298184ca0bd1eadac3a02e7e867085d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 17:26:57 +0700
Subject: add xact_out(), xact_in() to manage transfer

---
 src/portable/analog/max3421/hcd_max3421.c | 143 +++++++++++++++++++-----------
 1 file changed, 89 insertions(+), 54 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index b0325f240..00b36201c 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -331,7 +331,7 @@ static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep
   for(size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     // for control endpoint, skip direction check
-    if ( daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0) ) {
+    if (daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) {
       return ep;
     }
   }
@@ -362,6 +362,28 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr,
   }
 }
 
+//static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
+//  size_t idx = cur_ep - _hcd_data.ep;
+//
+//  // starting from next endpoint
+//  for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+//    max3421_ep_t* ep = &_hcd_data.ep[i];
+//    if (ep->xfer_pending) {
+//      return ep;
+//    }
+//  }
+//
+//  // wrap around including current endpoint
+//  for (size_t i = 0; i <= idx; i++) {
+//    max3421_ep_t* ep = &_hcd_data.ep[i];
+//    if (ep->xfer_pending) {
+//      return ep;
+//    }
+//  }
+//
+//  return NULL;
+//}
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
@@ -548,6 +570,37 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
   return true;
 }
 
+void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  // Page 12: Programming BULK-OUT Transfers
+  // TODO double buffered
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+  }
+
+  uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+  fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
+  sndbc_write(rhport, xact_len, in_isr);
+
+  uint8_t const hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
+  hxfr_write(rhport, hxfr, in_isr);
+}
+
+void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  // Page 13: Programming BULK-IN Transfers
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+  }
+
+  uint8_t const hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
+  hxfr_write(rhport, hxfr, in_isr);
+}
+
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   (void) rhport;
@@ -567,17 +620,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   // carry out transfer if not busy
 //  if ( atomic_flag_test_and_set(&_hcd_data.busy) )
   {
-    peraddr_write(rhport, daddr, false);
-
-    uint8_t hctl = 0;
     uint8_t hxfr = ep_num;
 
-    if ( ep->is_iso ) {
-      hxfr |= HXFR_ISO;
-    } else if ( ep_num == 0 ) {
+    if ( ep_num == 0 ) {
       ep->data_toggle = 1;
       if ( buffer == NULL || buflen == 0 ) {
         // ZLP for ACK stage, use HS
+        peraddr_write(rhport, daddr, false);
+
         hxfr |= HXFR_HS;
         hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
         hxfr_write(rhport, hxfr, false);
@@ -586,22 +636,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
     }
 
     if ( 0 == ep_dir ) {
-      // Page 12: Programming BULK-OUT Transfers
       TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
-
-      uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
-      fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
-      sndbc_write(rhport, xact_len, false);
-
-      hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-      hxfr |= HXFR_OUT_NIN;
+      xact_out(rhport, ep, true, false);
     } else {
-      // Page 13: Programming BULK-IN Transfers
-      hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+      xact_in(rhport, ep, true, false);
     }
-
-    reg_write(rhport, HCTL_ADDR, hctl, false);
-    hxfr_write(rhport, hxfr, false);
   }
 
   return true;
@@ -644,7 +683,12 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 static void handle_xfer_done(uint8_t rhport) {
   uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
-  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+
+  uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+  uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
+  uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
+
+  max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
 
   xfer_result_t xfer_result;
 
@@ -663,10 +707,11 @@ static void handle_xfer_done(uint8_t rhport) {
       return;
 
     case HRSL_NAK:
-      // NAK on control, retry immediately
-      //if (ep_num == 0)
-      {
+      if (ep_num == 0) {
+        // NAK on control, retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, true);
+      }else {
+        // NAK on non-control, find next pending to switch
       }
       return;
 
@@ -675,16 +720,28 @@ static void handle_xfer_done(uint8_t rhport) {
       break;
   }
 
-  uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
+  if (ep_dir) {
+    // IN transfer: fifo data is already received in RCVDAV IRQ
+    if ( hxfr_type & HXFR_HS ) {
+      ep->xfer_complete = 1;
+    }
 
-  if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) {
+    // short packet or all bytes transferred
+    if ( ep->xfer_complete ) {
+      // save data toggle
+      ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+      hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
+    }else {
+      // more to transfer
+      hxfr_write(rhport, _hcd_data.hxfr, true);
+    }
+  } else {
     // SETUP or OUT transfer
-    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 0);
     uint8_t xact_len;
 
-    if ( hxfr_type & HXFR_SETUP) {
+    if (hxfr_type & HXFR_SETUP) {
       xact_len = 8;
-    } else if ( hxfr_type & HXFR_HS ) {
+    } else if (hxfr_type & HXFR_HS) {
       xact_len = 0;
     } else {
       xact_len = _hcd_data.sndbc;
@@ -693,34 +750,12 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->xferred_len += xact_len;
     ep->buf += xact_len;
 
-    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+    if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
       // save data toggle
       ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
-    }else {
-      // more to transfer
-      xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, true);
-      sndbc_write(rhport, xact_len, true);
-
-      hxfr_write(rhport, _hcd_data.hxfr, true);
-    }
-  } else {
-    // IN transfer: fifo data is already received in RCVDAV IRQ
-    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
-
-    if ( hxfr_type & HXFR_HS ) {
-      ep->xfer_complete = 1;
-    }
-
-    // short packet or all bytes transferred
-    if ( ep->xfer_complete ) {
-      // save data toggle
-      ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
-      hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
-    }else {
-      // more to transfer
-      hxfr_write(rhport, _hcd_data.hxfr, true);
+    } else {
+      xact_out(rhport, ep, false, true);
     }
   }
 }
-- 
cgit v1.3.1


From cd7464a8847db5efa14f568bdf8746d898fc7eb4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 17:37:09 +0700
Subject: try next endpoint when received NAK

---
 src/portable/analog/max3421/hcd_max3421.c | 58 ++++++++++++++++++++-----------
 1 file changed, 37 insertions(+), 21 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 00b36201c..e546f99ce 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -362,27 +362,27 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr,
   }
 }
 
-//static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
-//  size_t idx = cur_ep - _hcd_data.ep;
-//
-//  // starting from next endpoint
-//  for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
-//    max3421_ep_t* ep = &_hcd_data.ep[i];
-//    if (ep->xfer_pending) {
-//      return ep;
-//    }
-//  }
-//
-//  // wrap around including current endpoint
-//  for (size_t i = 0; i <= idx; i++) {
-//    max3421_ep_t* ep = &_hcd_data.ep[i];
-//    if (ep->xfer_pending) {
-//      return ep;
-//    }
-//  }
-//
-//  return NULL;
-//}
+static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
+  size_t idx = cur_ep - _hcd_data.ep;
+
+  // starting from next endpoint
+  for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (ep->xfer_pending) {
+      return ep;
+    }
+  }
+
+  // wrap around including current endpoint
+  for (size_t i = 0; i <= idx; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (ep->xfer_pending) {
+      return ep;
+    }
+  }
+
+  return NULL;
+}
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -443,6 +443,7 @@ bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
   hcd_int_disable(rhport);
+  tuh_max3421_spi_cs_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
   TU_LOG2_INT(sizeof(max3421_data_t));
@@ -689,6 +690,7 @@ static void handle_xfer_done(uint8_t rhport) {
   uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
 
   max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
+  TU_ASSERT(ep, );
 
   xfer_result_t xfer_result;
 
@@ -712,6 +714,20 @@ static void handle_xfer_done(uint8_t rhport) {
         hxfr_write(rhport, _hcd_data.hxfr, true);
       }else {
         // NAK on non-control, find next pending to switch
+        max3421_ep_t *next_ep = find_next_pending_ep(ep);
+        TU_ASSERT(next_ep, );
+
+        if (ep == next_ep) {
+          // only one pending, retry immediately
+          hxfr_write(rhport, _hcd_data.hxfr, true);
+        }else {
+          // switch to next pending TODO could have issue with double buffered if not clear previously out data
+          if ( ep_dir ) {
+            xact_in(rhport, next_ep, true, true);
+          } else {
+            xact_out(rhport, next_ep, true, true);
+          }
+        }
       }
       return;
 
-- 
cgit v1.3.1


From 502b1bdda62f0f207d9a51daf134574e455f3aa2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 27 Aug 2023 23:45:34 +0700
Subject: more update to transaction

---
 examples/host/cdc_msc_hid/src/tusb_config.h       |  9 ++--
 examples/host/msc_file_explorer/src/tusb_config.h | 10 +++--
 src/common/tusb_mcu.h                             | 12 ++++++
 src/host/hcd.h                                    |  4 +-
 src/host/usbh.c                                   |  1 +
 src/portable/analog/max3421/hcd_max3421.c         | 51 +++++++++++++++--------
 6 files changed, 62 insertions(+), 25 deletions(-)

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index abb75f068..7d621d466 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -35,9 +35,12 @@
 //--------------------------------------------------------------------+
 
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+  #define CFG_TUH_RPI_PIO_USB   0
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
+  #define CFG_TUH_MAX3421      1
 #endif
 
 // RHPort number used for host can be defined by board.mk, default to port 0
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index 1e0d067bf..bb2fd4cf5 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -35,11 +35,15 @@
 //--------------------------------------------------------------------+
 
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+  #define CFG_TUH_RPI_PIO_USB   0
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_US
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
+  #define CFG_TUH_MAX3421      1
 #endif
 
+
 // RHPort number used for host can be defined by board.mk, default to port 0
 #ifndef BOARD_TUH_RHPORT
 #define BOARD_TUH_RHPORT      0
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 35f94efbc..21939df7c 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -385,6 +385,18 @@
   #define TUP_RHPORT_HIGHSPEED    1
 #endif
 
+
+//--------------------------------------------------------------------+
+// External USB controller
+//--------------------------------------------------------------------+
+
+#if defined(CFG_TUH_MAX3421) & CFG_TUH_MAX3421
+  #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
+    #define CFG_TUH_MAX3421_ENDPOINT_TOTAL  (8 + 4*(CFG_TUH_DEVICE_MAX-1))
+  #endif
+#endif
+
+
 //--------------------------------------------------------------------+
 // Default Values
 //--------------------------------------------------------------------+
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 1f01a1a2f..e25b20ea3 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -39,7 +39,7 @@
 // Configuration
 //--------------------------------------------------------------------+
 
-// Max number of endpoints per device
+// Max number of endpoints pair per device
 // TODO optimize memory usage
 #ifndef CFG_TUH_ENDPOINT_MAX
   #define CFG_TUH_ENDPOINT_MAX   16
@@ -167,7 +167,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 //--------------------------------------------------------------------+
 
 // Open an endpoint
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc);
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7a09f5b6e..12a7f5839 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -919,6 +919,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
   switch (event->event_id)
   {
 //    case HCD_EVENT_DEVICE_REMOVE:
+//      // FIXME device remove from a hub need an HCD API for hcd to free up endpoint
 //      // mark device as removing to prevent further xfer before the event is processed in usbh task
 //      break;
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index e546f99ce..574cca788 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -582,6 +582,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   }
 
   uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ, );
   fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
   sndbc_write(rhport, xact_len, in_isr);
 
@@ -602,6 +603,28 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   hxfr_write(rhport, hxfr, in_isr);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  if (ep->ep_dir) {
+    xact_in(rhport, ep, switch_ep, in_isr);
+  }else {
+    xact_out(rhport, ep, switch_ep, in_isr);
+  }
+}
+
+void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
+  (void) rhport;
+  (void) result;
+  ep->xfer_pending = 0;
+  ep->data_toggle = data_toggle;
+  //uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
+  //hcd_event_xfer_complete(rhport, ep_addr, ep->xferred_len, result, true);
+
+//  max3421_ep_t *next_ep = find_next_pending_ep(ep);
+//  if (next_ep) {
+//    xact_inout(rhport, next_ep, true, true);
+//  }
+}
+
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   (void) rhport;
@@ -612,6 +635,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
   TU_ASSERT(ep);
 
+  // control transfer can switch direction
+  ep->ep_dir = ep_dir;
+
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
@@ -636,12 +662,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       }
     }
 
-    if ( 0 == ep_dir ) {
-      TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
-      xact_out(rhport, ep, true, false);
-    } else {
-      xact_in(rhport, ep, true, false);
-    }
+    xact_inout(rhport, ep, true, false);
   }
 
   return true;
@@ -662,6 +683,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   (void) rhport;
 
   max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
+  ep->ep_dir = 0;
   ep->total_len  = 8;
   ep->xferred_len = 0;
 
@@ -715,18 +737,13 @@ static void handle_xfer_done(uint8_t rhport) {
       }else {
         // NAK on non-control, find next pending to switch
         max3421_ep_t *next_ep = find_next_pending_ep(ep);
-        TU_ASSERT(next_ep, );
 
         if (ep == next_ep) {
           // only one pending, retry immediately
           hxfr_write(rhport, _hcd_data.hxfr, true);
-        }else {
+        }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
-          if ( ep_dir ) {
-            xact_in(rhport, next_ep, true, true);
-          } else {
-            xact_out(rhport, next_ep, true, true);
-          }
+          xact_inout(rhport, next_ep, true, true);
         }
       }
       return;
@@ -744,8 +761,8 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      // save data toggle
-      ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+      uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle
+      xfer_complete_isr(rhport, ep, xfer_result, dt);
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
@@ -767,8 +784,8 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
-      // save data toggle
-      ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+      uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle
+      xfer_complete_isr(rhport, ep, xfer_result, dt);
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     } else {
       xact_out(rhport, ep, false, true);
-- 
cgit v1.3.1


From b31924e13edff0f29829056152348a9255e72169 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Aug 2023 12:41:44 +0700
Subject: - add xfer_complete_isr() - merge addr0 ep to pool - add control
 status to xact in/out - use atomic flag busy to ensure only 1 transfer is
 active at any time - execute pending transfer after one is complete (or clear
 busy flag) - change rtt mode to block if full

---
 hw/bsp/family_support.cmake               |   1 +
 src/portable/analog/max3421/hcd_max3421.c | 118 +++++++++++++++---------------
 2 files changed, 62 insertions(+), 57 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 7c89427c0..1cbcfb2a7 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -216,6 +216,7 @@ function(family_configure_common TARGET RTOS)
       if (NOT TARGET segger_rtt)
         add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
         target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
+        target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
       endif()
       target_link_libraries(${TARGET} PUBLIC segger_rtt)
     endif ()
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 574cca788..262dbca0f 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -195,9 +195,7 @@ typedef struct {
   uint8_t hxfr;
 
   volatile uint16_t frame_count;
-
-  max3421_ep_t ep0_addr0; // control endpoint for addr0
-  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL];
+  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
 
   OSAL_MUTEX_DEF(spi_mutexdef);
 #if OSAL_MUTEX_REQUIRED
@@ -328,7 +326,7 @@ static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
 //--------------------------------------------------------------------+
 
 static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
-  for(size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+  for(size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     // for control endpoint, skip direction check
     if (daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) {
@@ -344,9 +342,17 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) {
   return find_ep_not_addr0(0, 0, 0);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  if (daddr == 0 && ep_num == 0) {
+    return &_hcd_data.ep[0];
+  }else{
+    return find_ep_not_addr0(daddr, ep_num, ep_dir);
+  }
+}
+
 // free all endpoints belong to device address
 static void free_ep(uint8_t daddr) {
-  for (size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+  for (size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     if (ep->daddr == daddr) {
       tu_memclr(ep, sizeof(max3421_ep_t));
@@ -354,16 +360,8 @@ static void free_ep(uint8_t daddr) {
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
-  if (daddr == 0 && ep_num == 0) {
-    return &_hcd_data.ep0_addr0;
-  }else{
-    return find_ep_not_addr0(daddr, ep_num, ep_dir);
-  }
-}
-
 static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
-  size_t idx = cur_ep - _hcd_data.ep;
+  size_t const idx = cur_ep - _hcd_data.ep;
 
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
@@ -553,7 +551,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
 
   max3421_ep_t * ep;
   if (daddr == 0 && ep_num == 0) {
-    ep = &_hcd_data.ep0_addr0;
+    ep = &_hcd_data.ep[0];
   }else {
     ep = allocate_ep();
     TU_ASSERT(ep);
@@ -581,12 +579,20 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ, );
-  fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
-  sndbc_write(rhport, xact_len, in_isr);
+  uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
+
+  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
+    // Control ZLP status use HS
+    hxfr |= HXFR_HS;
+  } else {
+    uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
+    if (xact_len) {
+      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
+    }
+    sndbc_write(rhport, xact_len, in_isr);
+  }
 
-  uint8_t const hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -599,7 +605,12 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  uint8_t const hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
+  uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
+  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
+    // Control ZLP status use HS
+    hxfr |= HXFR_HS;
+  }
+
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -611,24 +622,8 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t
   }
 }
 
-void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
-  (void) rhport;
-  (void) result;
-  ep->xfer_pending = 0;
-  ep->data_toggle = data_toggle;
-  //uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
-  //hcd_event_xfer_complete(rhport, ep_addr, ep->xferred_len, result, true);
-
-//  max3421_ep_t *next_ep = find_next_pending_ep(ep);
-//  if (next_ep) {
-//    xact_inout(rhport, next_ep, true, true);
-//  }
-}
-
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
-  (void) rhport;
-
   uint8_t const ep_num = tu_edpt_number(ep_addr);
   uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
@@ -644,24 +639,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->xfer_complete = 0;
   ep->xfer_pending = 1;
 
-  // carry out transfer if not busy
-//  if ( atomic_flag_test_and_set(&_hcd_data.busy) )
-  {
-    uint8_t hxfr = ep_num;
-
-    if ( ep_num == 0 ) {
-      ep->data_toggle = 1;
-      if ( buffer == NULL || buflen == 0 ) {
-        // ZLP for ACK stage, use HS
-        peraddr_write(rhport, daddr, false);
-
-        hxfr |= HXFR_HS;
-        hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
-        hxfr_write(rhport, hxfr, false);
-        return true;
-      }
-    }
+  if ( ep_num == 0 ) {
+    ep->data_toggle = 1;
+  }
 
+  // carry out transfer if not busy
+  if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
     xact_inout(rhport, ep, true, false);
   }
 
@@ -683,6 +666,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   (void) rhport;
 
   max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
+  TU_ASSERT(ep);
+
   ep->ep_dir = 0;
   ep->total_len  = 8;
   ep->xferred_len = 0;
@@ -703,6 +688,26 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
+//--------------------------------------------------------------------+
+// Interrupt Handler
+//--------------------------------------------------------------------+
+
+static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
+  uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
+  ep->data_toggle = data_toggle;
+  ep->xfer_pending = 0;
+  hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true);
+
+  // Find next pending endpoint
+  max3421_ep_t *next_ep = find_next_pending_ep(ep);
+  if (next_ep) {
+    xact_inout(rhport, next_ep, true, true);
+  }else {
+    // no more pending
+    atomic_flag_clear(&_hcd_data.busy);
+  }
+}
+
 static void handle_xfer_done(uint8_t rhport) {
   uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
@@ -739,7 +744,7 @@ static void handle_xfer_done(uint8_t rhport) {
         max3421_ep_t *next_ep = find_next_pending_ep(ep);
 
         if (ep == next_ep) {
-          // only one pending, retry immediately
+          // this endpoint is only one pending, retry immediately
           hxfr_write(rhport, _hcd_data.hxfr, true);
         }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
@@ -763,7 +768,6 @@ static void handle_xfer_done(uint8_t rhport) {
     if ( ep->xfer_complete ) {
       uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle
       xfer_complete_isr(rhport, ep, xfer_result, dt);
-      hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
       hxfr_write(rhport, _hcd_data.hxfr, true);
@@ -786,8 +790,8 @@ static void handle_xfer_done(uint8_t rhport) {
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
       uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle
       xfer_complete_isr(rhport, ep, xfer_result, dt);
-      hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     } else {
+      // more to transfer
       xact_out(rhport, ep, false, true);
     }
   }
-- 
cgit v1.3.1


From 588b758717f3c22aa8046d61247b9967de8840b7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Aug 2023 17:34:22 +0700
Subject: rename OPT_MCU_KINETIS_K64 to OPT_MCU_KINETIS_K

---
 hw/bsp/board_mcu.h               | 2 +-
 src/common/tusb_mcu.h            | 2 +-
 src/portable/nxp/khci/dcd_khci.c | 6 +++---
 src/tusb_option.h                | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 3928435f0..b0f7891b4 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -47,7 +47,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
   #include "fsl_device_registers.h"
 
-#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64)
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 4a0c5acef..d983f8677 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -97,7 +97,7 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
-#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K64)
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
   #define TUP_USBIP_CHIPIDEA_FS
   #define TUP_USBIP_CHIPIDEA_FS_KINETIS
   #define TUP_DCD_ENDPOINT_MAX    16
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index d957338ad..2293d1b59 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -269,10 +269,10 @@ void dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
-#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K64)
+#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K)
   uint32_t clk_recover_irc_en;
   uint32_t clk_recover_ctrl;
-  
+
   clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN;
   clk_recover_ctrl   = KHCI->CLK_RECOVER_CTRL;
 
@@ -284,7 +284,7 @@ void dcd_init(uint8_t rhport)
 #else
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
-#endif  
+#endif
 
   tu_memclr(&_dcd, sizeof(_dcd));
   KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index bbaa2a53a..bf2667c4c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -121,7 +121,7 @@
 #define OPT_MCU_KINETIS_KL       1200 ///< NXP KL series
 #define OPT_MCU_KINETIS_K32L     1201 ///< NXP K32L series
 #define OPT_MCU_KINETIS_K32      1201 ///< Alias to K32L
-#define OPT_MCU_KINETIS_K64      1202 ///< NXP K64 series
+#define OPT_MCU_KINETIS_K        1202 ///< NXP K series
 
 #define OPT_MCU_MKL25ZXX         1200 ///< Alias to KL (obsolete)
 #define OPT_MCU_K32L2BXX         1201 ///< Alias to K32 (obsolete)
-- 
cgit v1.3.1


From 3740a3287ad5965df34639e90bfa890b36c0fd60 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Aug 2023 18:22:21 +0700
Subject: - correct tuh_max3421e_int_api() for nrf52 - hcd_int_disable/enable
 is software only to reduce interrupt lag

---
 hw/bsp/nrf/boards/pca10056/board.h        |  9 ++++
 hw/bsp/nrf/family.c                       | 20 ++++++-
 src/portable/analog/max3421/hcd_max3421.c | 86 +++++++++++++++++++++----------
 3 files changed, 87 insertions(+), 28 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index f4368f830..16d31addb 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -31,6 +31,8 @@
  extern "C" {
 #endif
 
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
 // LED
 #define LED_PIN               13
 #define LED_STATE_ON          0
@@ -43,6 +45,13 @@
 #define UART_RX_PIN           8
 #define UART_TX_PIN           6
 
+// SPI for USB host shield
+#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421E_MISO_PIN _PINNUM(1, 14)
+#define MAX3421E_CS_PIN   _PINNUM(1, 12)
+#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 368763b84..083efc235 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -107,7 +107,12 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
 //--------------------------------------------------------------------+
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
-  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled);
+
+  if (enabled) {
+    nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
+  }else {
+    nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN);
+  }
 }
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
@@ -217,6 +222,19 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+  // MAX3421 need 3.3v signal
+  if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+
+    NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
+
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+
+    NVIC_SystemReset();
+  }
+
   // manually manage CS
   nrf_gpio_cfg_output(MAX3421E_CS_PIN);
   tuh_max3421_spi_cs_api(0, false);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 262dbca0f..cb7911992 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -184,8 +184,6 @@ typedef struct {
 } max3421_ep_t;
 
 typedef struct {
-  atomic_flag busy; // busy transferring
-
   // cached register
   uint8_t sndbc;
   uint8_t hirq;
@@ -194,7 +192,10 @@ typedef struct {
   uint8_t peraddr;
   uint8_t hxfr;
 
+  atomic_flag busy; // busy transferring
+  volatile uint8_t intr_disable_count;
   volatile uint16_t frame_count;
+
   max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
 
   OSAL_MUTEX_DEF(spi_mutexdef);
@@ -220,8 +221,8 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
   if (!in_isr) {
-    tuh_max3421e_int_api(rhport, false);
     (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+    tuh_max3421e_int_api(rhport, false);
   }
 
   // assert CS
@@ -294,6 +295,12 @@ static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
   return ret ? rx_buf[1] : 0;
 }
 
+static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  reg_write(rhport, HIRQ_ADDR, data, in_isr);
+  // HIRQ write 1 is clear
+  _hcd_data.hirq &= ~data;
+}
+
 static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hien = data;
   reg_write(rhport, HIEN_ADDR, data, in_isr);
@@ -440,13 +447,14 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
-  hcd_int_disable(rhport);
+  tuh_max3421e_int_api(rhport, false);
   tuh_max3421_spi_cs_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
   TU_LOG2_INT(sizeof(max3421_data_t));
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
+  _hcd_data.peraddr = 0xff; // invalid
 
 #if OSAL_MUTEX_REQUIRED
   _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
@@ -469,11 +477,13 @@ bool hcd_init(uint8_t rhport) {
   reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
 
   // clear all previously pending IRQ
-  reg_write(rhport, HIRQ_ADDR, 0xff, false);
+  hirq_write(rhport, 0xff, false);
 
   // Enable IRQ
   hien_write(rhport, DEFAULT_HIEN, false);
 
+  tuh_max3421e_int_api(rhport, true);
+
   // Enable Interrupt pin
   reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
 
@@ -481,13 +491,21 @@ bool hcd_init(uint8_t rhport) {
 }
 
 // Enable USB interrupt
+// Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, true);
+  (void) rhport;
+  // tuh_max3421e_int_api(rhport, true);
+  if (_hcd_data.intr_disable_count) {
+    _hcd_data.intr_disable_count--;
+  }
 }
 
 // Disable USB interrupt
+// Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, false);
+  (void) rhport;
+  //tuh_max3421e_int_api(rhport, false);
+  _hcd_data.intr_disable_count++;
 }
 
 // Get frame number (1ms)
@@ -521,7 +539,7 @@ void hcd_port_reset_end(uint8_t rhport) {
   reg_write(rhport, HCTL_ADDR, 0, false);
 
   // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
-  reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false);
+  hirq_write(rhport, HIRQ_CONDET_IRQ, false);
   hien_write(rhport, DEFAULT_HIEN, false);
 }
 
@@ -572,19 +590,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
 void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 12: Programming BULK-OUT Transfers
   // TODO double buffered
-  if (switch_ep) {
-    peraddr_write(rhport, ep->daddr, in_isr);
-
-    uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-  }
 
   uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
-
   if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
     // Control ZLP status use HS
     hxfr |= HXFR_HS;
-  } else {
+  }
+
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    if ( 0 == (hxfr & HXFR_HS) ) {
+      uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+    }
+  }
+
+  if ( 0 == (hxfr & HXFR_HS) ) {
     uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
     TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
     if (xact_len) {
@@ -598,12 +620,6 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
 
 void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 13: Programming BULK-IN Transfers
-  if (switch_ep) {
-    peraddr_write(rhport, ep->daddr, in_isr);
-
-    uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
-    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-  }
 
   uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
   if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
@@ -611,6 +627,15 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     hxfr |= HXFR_HS;
   }
 
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    if ( 0 == (hxfr & HXFR_HS) ) {
+      uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+    }
+  }
+
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -721,7 +746,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
   xfer_result_t xfer_result;
 
-  //TU_LOG3("HRSL: %02X\r\n", hrsl);
+//  TU_LOG3("HRSL: %02X\r\n", hrsl);
   switch(hresult) {
     case HRSL_SUCCESS:
       xfer_result = XFER_RESULT_SUCCESS;
@@ -821,13 +846,20 @@ void print_hirq(uint8_t hirq) {
 void hcd_int_handler(uint8_t rhport) {
   uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
   if (!hirq) return;
-
 //  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
   }
 
+  // interrupt is disabled, only ack FRAME IRQ and skip the rest
+  if (_hcd_data.intr_disable_count) {
+    if (hirq & HIRQ_FRAME_IRQ) {
+      hirq_write(rhport, HIRQ_FRAME_IRQ, true);
+    }
+    return;
+  }
+
   if (hirq & HIRQ_CONDET_IRQ) {
     tusb_speed_t speed = handle_connect_irq(rhport);
 
@@ -861,7 +893,7 @@ void hcd_int_handler(uint8_t rhport) {
         }
 
         // ack RCVDVAV IRQ
-        reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true);
+        hirq_write(rhport, HIRQ_RCVDAV_IRQ, true);
         hirq = reg_read(rhport, HIRQ_ADDR, true);
       }
 
@@ -871,7 +903,7 @@ void hcd_int_handler(uint8_t rhport) {
     }
 
     if ( hirq & HIRQ_HXFRDN_IRQ ) {
-      reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true);
+      hirq_write(rhport, HIRQ_HXFRDN_IRQ, true);
       handle_xfer_done(rhport);
     }
 
@@ -881,7 +913,7 @@ void hcd_int_handler(uint8_t rhport) {
   // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
   hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
-    reg_write(rhport, HIRQ_ADDR, hirq, true);
+    hirq_write(rhport, hirq, true);
   }
 }
 
-- 
cgit v1.3.1


From 2a814a99af32bf084cbb730d97e3c9cb31a3fa85 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Aug 2023 20:27:37 +0700
Subject: - hcd_setup_send() also check for busy flag - xact_inout() to support
 send setup

---
 src/portable/analog/max3421/hcd_max3421.c | 71 +++++++++++++++++--------------
 1 file changed, 39 insertions(+), 32 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index cb7911992..461e02593 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -168,6 +168,7 @@ typedef struct {
   struct TU_ATTR_PACKED {
     uint8_t ep_dir        : 1;
     uint8_t is_iso        : 1;
+    uint8_t is_setup      : 1;
     uint8_t data_toggle   : 1;
     uint8_t xfer_pending  : 1;
     uint8_t xfer_complete : 1;
@@ -590,56 +591,55 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
 void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 12: Programming BULK-OUT Transfers
   // TODO double buffered
-
-  uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
-  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
-    // Control ZLP status use HS
-    hxfr |= HXFR_HS;
-  }
-
   if (switch_ep) {
     peraddr_write(rhport, ep->daddr, in_isr);
 
-    if ( 0 == (hxfr & HXFR_HS) ) {
-      uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-    }
+    uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  if ( 0 == (hxfr & HXFR_HS) ) {
-    uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
-    if (xact_len) {
-      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
-    }
-    sndbc_write(rhport, xact_len, in_isr);
+  uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
+  if (xact_len) {
+    fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
   }
+  sndbc_write(rhport, xact_len, in_isr);
 
+  uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
   hxfr_write(rhport, hxfr, in_isr);
 }
 
 void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 13: Programming BULK-IN Transfers
-
-  uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
-  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
-    // Control ZLP status use HS
-    hxfr |= HXFR_HS;
-  }
-
   if (switch_ep) {
     peraddr_write(rhport, ep->daddr, in_isr);
 
-    if ( 0 == (hxfr & HXFR_HS) ) {
-      uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
-      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-    }
+    uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
+  uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
   hxfr_write(rhport, hxfr, in_isr);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  if (ep->ep_num == 0 ) {
+    // setup
+    if (ep->is_setup) {
+      peraddr_write(rhport, ep->daddr, in_isr);
+      hxfr_write(rhport, HXFR_SETUP, in_isr);
+      return;
+    }
+
+    // status
+    if (ep->buf == NULL || ep->total_len == 0) {
+      uint8_t const hxfr = HXFR_HS | (ep->ep_dir ? 0 : HXFR_OUT_NIN);
+      peraddr_write(rhport, ep->daddr, in_isr);
+      hxfr_write(rhport, hxfr, in_isr);
+      return;
+    }
+  }
+
   if (ep->ep_dir) {
     xact_in(rhport, ep, switch_ep, in_isr);
   }else {
@@ -665,12 +665,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->xfer_pending = 1;
 
   if ( ep_num == 0 ) {
+    ep->is_setup = 0;
     ep->data_toggle = 1;
   }
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
     xact_inout(rhport, ep, true, false);
+  } else {
+    return true;
   }
 
   return true;
@@ -694,12 +697,16 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   TU_ASSERT(ep);
 
   ep->ep_dir = 0;
-  ep->total_len  = 8;
+  ep->total_len = 8;
   ep->xferred_len = 0;
+  ep->is_setup = 1;
 
-  peraddr_write(rhport, daddr, false);
   fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
-  hxfr_write(rhport, HXFR_SETUP, false);
+
+  // carry out transfer if not busy
+  if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
+    xact_inout(rhport, ep, true, false);
+  }
 
   return true;
 }
-- 
cgit v1.3.1


From 966584363546023d85f4d8b748b18ace63ea1c57 Mon Sep 17 00:00:00 2001
From: Alexander Mueller <alexander.mueller@littleblue.de>
Date: Tue, 29 Aug 2023 18:16:50 +0200
Subject: Fix the weak dcd_edpt0_status_complete for Keil Compiler

The Keil compiler seems to have different semantics and the defined function was never called.

The same is probably true for the other weak functions. I can change those too.
---
 src/device/dcd.h          |  2 +-
 src/device/usbd_control.c | 11 ++++++++++-
 2 files changed, 11 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 18a708347..b1984fda3 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -155,7 +155,7 @@ void dcd_sof_enable(uint8_t rhport, bool en);
 
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request);
 
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 76d062e40..a6081060e 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -135,6 +135,15 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
 // USBD API
 //--------------------------------------------------------------------+
 
+TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void)rhport;
+  (void)request;
+
+  // this is the default implementation that is called when no "real" implementation
+  // of the function exists
+}
+
 void usbd_control_reset(void);
 void usbd_control_set_request(tusb_control_request_t const *request);
 void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
@@ -173,7 +182,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     TU_ASSERT(0 == xferred_bytes);
 
     // invoke optional dcd hook if available
-    if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
+    dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
 
     if (_ctrl_xfer.complete_cb)
     {
-- 
cgit v1.3.1


From 1ab488eb06ef4cb8ad9c0cff91e6b0caf76f73c4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 30 Aug 2023 16:04:18 +0700
Subject: call xfer_complete_isr() when result is not successful (stalled or
 failed)

---
 hw/bsp/nrf/boards/pca10095/board.h        |  9 +++++++
 hw/bsp/nrf/family.c                       |  7 +++--
 hw/bsp/nrf/nrfx_config.h                  |  2 +-
 src/common/tusb_mcu.h                     |  2 +-
 src/portable/analog/max3421/hcd_max3421.c | 43 ++++++++++++++++++++++---------
 5 files changed, 47 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
index fd3c63d6a..b9d3a19dc 100644
--- a/hw/bsp/nrf/boards/pca10095/board.h
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -31,6 +31,8 @@
  extern "C" {
 #endif
 
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
 // LED
 #define LED_PIN               28
 #define LED_STATE_ON          0
@@ -43,6 +45,13 @@
 #define UART_RX_PIN           32
 #define UART_TX_PIN           33
 
+// SPI for USB host shield
+#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421E_MISO_PIN _PINNUM(1, 14)
+#define MAX3421E_CS_PIN   _PINNUM(1, 12)
+#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 083efc235..2b4260083 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -34,6 +34,7 @@
 #pragma GCC diagnostic ignored "-Wcast-align"
 #pragma GCC diagnostic ignored "-Wunused-parameter"
 #pragma GCC diagnostic ignored "-Wundef"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
 #endif
 
 #include "nrfx.h"
@@ -94,7 +95,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 
 //------------- Host using MAX2341E -------------//
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 
 void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
@@ -222,7 +223,8 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-  // MAX3421 need 3.3v signal
+  // MAX3421 need 3.3v signal (may not be needed)
+  #if defined(UICR_REGOUT0_VOUT_Msk) && 0
   if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
     NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
     while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -234,6 +236,7 @@ void board_init(void) {
 
     NVIC_SystemReset();
   }
+  #endif
 
   // manually manage CS
   nrf_gpio_cfg_output(MAX3421E_CS_PIN);
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
index e3d0ea91b..95ef33ce4 100644
--- a/hw/bsp/nrf/nrfx_config.h
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -11,7 +11,7 @@
 #define NRFX_UARTE0_ENABLED  1
 
 #define NRFX_SPIM_ENABLED    1
-#define NRFX_SPIM0_ENABLED   1
+#define NRFX_SPIM1_ENABLED   1 // use SPI1 since nrf5340 share uart with spi
 
 #define NRFX_PRS_ENABLED     0
 #define NRFX_USBREG_ENABLED  1
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 21939df7c..8807ff8aa 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -390,7 +390,7 @@
 // External USB controller
 //--------------------------------------------------------------------+
 
-#if defined(CFG_TUH_MAX3421) & CFG_TUH_MAX3421
+#if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
   #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
     #define CFG_TUH_MAX3421_ENDPOINT_TOTAL  (8 + 4*(CFG_TUH_DEVICE_MAX-1))
   #endif
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 461e02593..705bb5bfd 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -374,7 +374,8 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->xfer_pending) {
+    if (ep->xfer_pending && ep->packet_size) {
+//      TU_LOG3("next pending i = %u\n", i);
       return ep;
     }
   }
@@ -382,7 +383,8 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // wrap around including current endpoint
   for (size_t i = 0; i <= idx; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->xfer_pending) {
+    if (ep->xfer_pending && ep->packet_size) {
+//      TU_LOG3("next pending i = %u\n", i);
       return ep;
     }
   }
@@ -464,6 +466,10 @@ bool hcd_init(uint8_t rhport) {
   // full duplex, interrupt negative edge
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
+  // V1 is 0x01, V2 is 0x12, V3 is 0x13
+  // uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+  // TU_LOG2_HEX(revision);
+
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
   reg_write(rhport, USBCTL_ADDR, 0, false);
@@ -699,6 +705,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->ep_dir = 0;
   ep->total_len = 8;
   ep->xferred_len = 0;
+  ep->xfer_pending = 1;
   ep->is_setup = 1;
 
   fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
@@ -724,9 +731,16 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 // Interrupt Handler
 //--------------------------------------------------------------------+
 
-static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
+static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) {
   uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
-  ep->data_toggle = data_toggle;
+
+  // save data toggle
+  if (ep->ep_dir) {
+    ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+  }else {
+    ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+  }
+
   ep->xfer_pending = 0;
   hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true);
 
@@ -763,10 +777,6 @@ static void handle_xfer_done(uint8_t rhport) {
       xfer_result = XFER_RESULT_STALLED;
       break;
 
-    case HRSL_BAD_REQ:
-      // occurred when initialized without any pending transfer. Skip for now
-      return;
-
     case HRSL_NAK:
       if (ep_num == 0) {
         // NAK on control, retry immediately
@@ -781,15 +791,26 @@ static void handle_xfer_done(uint8_t rhport) {
         }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
           xact_inout(rhport, next_ep, true, true);
+        }else {
+          TU_ASSERT(false,);
         }
       }
       return;
 
+    case HRSL_BAD_REQ:
+      // occurred when initialized without any pending transfer. Skip for now
+      return;
+
     default:
       xfer_result = XFER_RESULT_FAILED;
       break;
   }
 
+  if (xfer_result != XFER_RESULT_SUCCESS) {
+    xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+    return;
+  }
+
   if (ep_dir) {
     // IN transfer: fifo data is already received in RCVDAV IRQ
     if ( hxfr_type & HXFR_HS ) {
@@ -798,8 +819,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle
-      xfer_complete_isr(rhport, ep, xfer_result, dt);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
     }else {
       // more to transfer
       hxfr_write(rhport, _hcd_data.hxfr, true);
@@ -820,8 +840,7 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
-      uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle
-      xfer_complete_isr(rhport, ep, xfer_result, dt);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
     } else {
       // more to transfer
       xact_out(rhport, ep, false, true);
-- 
cgit v1.3.1


From 41493426b38c8ce44b1f7720b907538bc5402f98 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 30 Aug 2023 16:21:43 +0700
Subject: use ep buf to keep setup packet, work well with hid device

---
 examples/host/msc_file_explorer/src/tusb_config.h | 2 +-
 src/portable/analog/max3421/hcd_max3421.c         | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index 28e130c0e..e6186ba46 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -37,7 +37,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
   #define CFG_TUH_RPI_PIO_USB   0
-  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_US
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
 //#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
 //  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
 //  #define CFG_TUH_MAX3421      1
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 705bb5bfd..d644390da 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -633,6 +633,7 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t
     // setup
     if (ep->is_setup) {
       peraddr_write(rhport, ep->daddr, in_isr);
+      fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr);
       hxfr_write(rhport, HXFR_SETUP, in_isr);
       return;
     }
@@ -703,12 +704,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   TU_ASSERT(ep);
 
   ep->ep_dir = 0;
+  ep->is_setup = 1;
+  ep->buf = (uint8_t*)(uintptr_t) setup_packet;
   ep->total_len = 8;
   ep->xferred_len = 0;
+  ep->xfer_complete = 0;
   ep->xfer_pending = 1;
-  ep->is_setup = 1;
-
-  fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
-- 
cgit v1.3.1


From 3b7d5aa0421f3d3a7ac199de0138dc40141fbddd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 31 Aug 2023 16:52:09 +0700
Subject: improve connection & disconnection detection. But there is still
 issue when CONDETIRQ occurs but we are disabled interrupt (for osal queue
 access).

---
 hw/bsp/board.c                            | 26 ++++------
 hw/bsp/nrf/family.c                       | 49 ++++++++----------
 src/host/usbh.c                           |  2 +-
 src/portable/analog/max3421/hcd_max3421.c | 85 ++++++++++++++-----------------
 4 files changed, 72 insertions(+), 90 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 417630a03..562792625 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -44,17 +44,16 @@
 
 // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
 #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM)
+
 #include "SEGGER_RTT.h"
 
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) {
   (void) fhdl;
-  SEGGER_RTT_Write(0, (const char*) buf, (int) count);
+  SEGGER_RTT_Write(0, (const char *) buf, (int) count);
   return count;
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) {
   (void) fhdl;
   int rd = (int) SEGGER_RTT_Read(0, buf, count);
   return (rd > 0) ? rd : -1;
@@ -67,8 +66,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 
 #include "board_mcu.h"
 
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
   (void) fhdl;
   uint8_t const* buf8 = (uint8_t const*) buf;
 
@@ -79,8 +77,7 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
   return (int) count;
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
   (void) fhdl;
   (void) buf;
   (void) count;
@@ -90,14 +87,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 #else
 
 // Default logging with on-board UART
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
   (void) fhdl;
   return board_uart_write(buf, (int) count);
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
   (void) fhdl;
   int rd = board_uart_read((uint8_t*) buf, (int) count);
   return (rd > 0) ? rd : -1;
@@ -105,8 +100,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 
 #endif
 
-int board_getchar(void)
-{
+int board_getchar(void) {
   char c;
-  return ( sys_read(0, &c, 1) > 0 ) ? (int) c : (-1);
+  return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
 }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 2b4260083..7358458ce 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -98,7 +98,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 
 void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
-  if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
+  if (!(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
 
   tuh_int_handler(1);
 }
@@ -111,7 +111,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
 
   if (enabled) {
     nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
-  }else {
+  } else {
     nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN);
   }
 }
@@ -121,7 +121,7 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
   (void) rhport;
 
   nrfx_spim_xfer_desc_t xfer = {
@@ -157,21 +157,21 @@ void board_init(void) {
   nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP);
 
   // 1ms tick timer
-  SysTick_Config(SystemCoreClock/1000);
+  SysTick_Config(SystemCoreClock / 1000);
 
   // UART
   nrfx_uarte_config_t uart_cfg = {
-    .pseltxd   = UART_TX_PIN,
-    .pselrxd   = UART_RX_PIN,
-    .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .pselrts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .p_context = NULL,
-    .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
-    .interrupt_priority = 7,
-    .hal_cfg = {
-      .hwfc      = NRF_UARTE_HWFC_DISABLED,
-      .parity    = NRF_UARTE_PARITY_EXCLUDED,
-    }
+      .pseltxd   = UART_TX_PIN,
+      .pselrxd   = UART_RX_PIN,
+      .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
+      .pselrts   = NRF_UARTE_PSEL_DISCONNECTED,
+      .p_context = NULL,
+      .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
+      .interrupt_priority = 7,
+      .hal_cfg = {
+          .hwfc      = NRF_UARTE_HWFC_DISABLED,
+          .parity    = NRF_UARTE_PARITY_EXCLUDED,
+      }
   };
 
   nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler);
@@ -211,11 +211,11 @@ void board_init(void) {
 
     // USB power may already be ready at this time -> no event generated
     // We need to invoke the handler based on the status initially
-    #ifdef NRF5340_XXAA
+#ifdef NRF5340_XXAA
     usb_reg = NRF_USBREGULATOR->USBREGSTATUS;
-    #else
+#else
     usb_reg = NRF_POWER->USBREGSTATUS;
-    #endif
+#endif
   }
 
   if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
@@ -308,8 +308,7 @@ uint32_t board_millis(void) {
 
 #ifdef SOFTDEVICE_PRESENT
 // process SOC event from SD
-uint32_t proc_soc(void)
-{
+uint32_t proc_soc(void) {
   uint32_t soc_evt;
   uint32_t err = sd_evt_get(&soc_evt);
 
@@ -326,18 +325,14 @@ uint32_t proc_soc(void)
   return err;
 }
 
-uint32_t proc_ble(void)
-{
+uint32_t proc_ble(void) {
   // do nothing with ble
   return NRF_ERROR_NOT_FOUND;
 }
 
-void SD_EVT_IRQHandler(void)
-{
+void SD_EVT_IRQHandler(void) {
   // process BLE and SOC until there is no more events
-  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) )
-  {
-
+  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) ) {
   }
 }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 12a7f5839..bacb3a719 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -852,7 +852,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
     ep_state->busy    = 0;
     ep_state->claimed = 0;
     TU_LOG1("Failed\r\n");
-    TU_BREAKPOINT();
+//    TU_BREAKPOINT();
     return false;
   }
 }
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index d644390da..56d3aea45 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -405,45 +405,46 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   return false;
 }
 
-tusb_speed_t handle_connect_irq(uint8_t rhport) {
+static void handle_connect_irq(uint8_t rhport) {
   uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
 
-  tusb_speed_t speed;
   uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+  TU_LOG2_HEX(jk);
 
   switch(jk) {
-    case 0x00:
-      // SEO is disconnected
-      speed = TUSB_SPEED_INVALID;
-      break;
-
-    case (HRSL_JSTATUS | HRSL_KSTATUS):
-      // SE1 is illegal
-      speed = TUSB_SPEED_INVALID;
+    case 0x00:                          // SEO is disconnected
+    case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
+      mode_write(rhport, new_mode, true);
+      hcd_event_device_remove(rhport, true);
       break;
 
     default: {
-      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
-      uint8_t const mode = reg_read(rhport, MODE_ADDR, true);
-      uint8_t const ls_bit = mode & MODE_LOWSPEED;
+      // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
+      if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
+        break;
+      }
 
-      if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
-        speed = TUSB_SPEED_LOW;
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      // However, since we are always in full speed mode, we can just check J-state
+      if (jk == HRSL_KSTATUS) {
         new_mode |= MODE_LOWSPEED;
-      } else {
-        speed =  TUSB_SPEED_FULL;
+        TU_LOG3("Low speed\n");
+      }else {
+        TU_LOG3("Full speed\n");
       }
+      new_mode |= MODE_SOFKAENAB;
+      mode_write(rhport, new_mode, true);
 
-      new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device
+      // FIXME multiple MAX3421 rootdevice address is not 1
+      uint8_t const daddr = 1;
+      free_ep(daddr);
+
+      hcd_event_device_attach(rhport, true);
 
       break;
     }
   }
-
-  mode_write(rhport, new_mode, true);
-  TU_LOG2_INT(speed);
-  return speed;
 }
 
 // Initialize controller to host mode
@@ -500,8 +501,9 @@ bool hcd_init(uint8_t rhport) {
 // Enable USB interrupt
 // Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
+//  tuh_max3421e_int_api(rhport, true);
+
   (void) rhport;
-  // tuh_max3421e_int_api(rhport, true);
   if (_hcd_data.intr_disable_count) {
     _hcd_data.intr_disable_count--;
   }
@@ -510,8 +512,8 @@ void hcd_int_enable (uint8_t rhport) {
 // Disable USB interrupt
 // Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  (void) rhport;
   //tuh_max3421e_int_api(rhport, false);
+  (void) rhport;
   _hcd_data.intr_disable_count++;
 }
 
@@ -534,20 +536,12 @@ bool hcd_port_connect_status(uint8_t rhport) {
 // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
 // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport) {
-  // Bus reset will also trigger CONDET IRQ, disable it
-  uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
-  hien_write(rhport, hien, false);
-
   reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false);
 }
 
 // Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport) {
   reg_write(rhport, HCTL_ADDR, 0, false);
-
-  // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
-  hirq_write(rhport, HIRQ_CONDET_IRQ, false);
-  hien_write(rhport, DEFAULT_HIEN, false);
 }
 
 // Get port link speed
@@ -660,7 +654,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
   max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
-  TU_ASSERT(ep);
+  TU_VERIFY(ep);
 
   // control transfer can switch direction
   ep->ep_dir = ep_dir;
@@ -767,8 +761,6 @@ static void handle_xfer_done(uint8_t rhport) {
   TU_ASSERT(ep, );
 
   xfer_result_t xfer_result;
-
-//  TU_LOG3("HRSL: %02X\r\n", hrsl);
   switch(hresult) {
     case HRSL_SUCCESS:
       xfer_result = XFER_RESULT_SUCCESS;
@@ -803,6 +795,7 @@ static void handle_xfer_done(uint8_t rhport) {
       return;
 
     default:
+      TU_LOG3("HRSL: %02X\r\n", hrsl);
       xfer_result = XFER_RESULT_FAILED;
       break;
   }
@@ -875,30 +868,30 @@ void hcd_int_handler(uint8_t rhport) {
   if (!hirq) return;
 //  print_hirq(hirq);
 
+//  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true);
+
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
   }
 
+  #if 1
   // interrupt is disabled, only ack FRAME IRQ and skip the rest
   if (_hcd_data.intr_disable_count) {
     if (hirq & HIRQ_FRAME_IRQ) {
       hirq_write(rhport, HIRQ_FRAME_IRQ, true);
     }
+
+    if ((hirq & HIRQ_CONDET_IRQ) && !(_hcd_data.mode & MODE_SOFKAENAB)) {
+      // connection when interrupt is disabled
+      TU_LOG3_INT(_hcd_data.intr_disable_count);
+      return;
+    }
     return;
   }
+  #endif
 
   if (hirq & HIRQ_CONDET_IRQ) {
-    tusb_speed_t speed = handle_connect_irq(rhport);
-
-    if (speed == TUSB_SPEED_INVALID) {
-      hcd_event_device_remove(rhport, true);
-    }else {
-      // FIXME multiple MAX3421 rootdevice address is not 1
-      uint8_t const daddr = 1;
-      free_ep(daddr);
-
-      hcd_event_device_attach(rhport, true);
-    }
+    handle_connect_irq(rhport);
   }
 
   // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
-- 
cgit v1.3.1


From ed0a233d4830baa8a767fcc20dcbfedbb09b7b41 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 31 Aug 2023 21:28:27 +0700
Subject: vastly improve attach/detach device, still have issue where thing is
 still hanged occasionally.

---
 src/portable/analog/max3421/hcd_max3421.c | 126 +++++++++++++++++-------------
 1 file changed, 70 insertions(+), 56 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 56d3aea45..c61389cb9 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -215,6 +215,9 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 
+static void handle_connect_irq(uint8_t rhport, bool in_isr);
+static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
+
 //--------------------------------------------------------------------+
 // SPI Helper
 //--------------------------------------------------------------------+
@@ -238,6 +241,14 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, true);
     (void) osal_mutex_unlock(_hcd_data.spi_mutex);
+
+    // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
+    // It would be ok if we are operating since SOF will re-trigger interrupt.
+    // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
+    if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
+      handle_connect_irq(rhport, false);
+      hirq_write(rhport, HIRQ_CONDET_IRQ, false);
+    }
   }
 }
 
@@ -405,48 +416,6 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   return false;
 }
 
-static void handle_connect_irq(uint8_t rhport) {
-  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
-  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
-
-  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
-  TU_LOG2_HEX(jk);
-
-  switch(jk) {
-    case 0x00:                          // SEO is disconnected
-    case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
-      mode_write(rhport, new_mode, true);
-      hcd_event_device_remove(rhport, true);
-      break;
-
-    default: {
-      // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
-      if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
-        break;
-      }
-
-      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
-      // However, since we are always in full speed mode, we can just check J-state
-      if (jk == HRSL_KSTATUS) {
-        new_mode |= MODE_LOWSPEED;
-        TU_LOG3("Low speed\n");
-      }else {
-        TU_LOG3("Full speed\n");
-      }
-      new_mode |= MODE_SOFKAENAB;
-      mode_write(rhport, new_mode, true);
-
-      // FIXME multiple MAX3421 rootdevice address is not 1
-      uint8_t const daddr = 1;
-      free_ep(daddr);
-
-      hcd_event_device_attach(rhport, true);
-
-      break;
-    }
-  }
-}
-
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
@@ -507,6 +476,14 @@ void hcd_int_enable (uint8_t rhport) {
   if (_hcd_data.intr_disable_count) {
     _hcd_data.intr_disable_count--;
   }
+
+  // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
+  // It would be ok if we are operating since SOF will re-trigger interrupt.
+  // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
+//  if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
+//    handle_connect_irq(rhport, false);
+//    hirq_write(rhport, HIRQ_CONDET_IRQ, false);
+//  }
 }
 
 // Disable USB interrupt
@@ -726,6 +703,54 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 // Interrupt Handler
 //--------------------------------------------------------------------+
 
+static void handle_connect_irq(uint8_t rhport, bool in_isr) {
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
+  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
+
+  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+  TU_LOG2_HEX(jk);
+
+  switch(jk) {
+    case 0x00:                          // SEO is disconnected
+    case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
+      mode_write(rhport, new_mode, in_isr);
+
+      // port reset anyway, this will help to stable bus signal for next connection
+      reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr);
+
+      hcd_event_device_remove(rhport, in_isr);
+
+      reg_write(rhport, HCTL_ADDR, 0, in_isr);
+      break;
+
+    default: {
+      // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
+      if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
+        break;
+      }
+
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      // However, since we are always in full speed mode, we can just check J-state
+      if (jk == HRSL_KSTATUS) {
+        new_mode |= MODE_LOWSPEED;
+        TU_LOG3("Low speed\n");
+      }else {
+        TU_LOG3("Full speed\n");
+      }
+      new_mode |= MODE_SOFKAENAB;
+      mode_write(rhport, new_mode, in_isr);
+
+      // FIXME multiple MAX3421 rootdevice address is not 1
+      uint8_t const daddr = 1;
+      free_ep(daddr);
+
+      hcd_event_device_attach(rhport, in_isr);
+
+      break;
+    }
+  }
+}
+
 static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) {
   uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
 
@@ -758,7 +783,7 @@ static void handle_xfer_done(uint8_t rhport) {
   uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
 
   max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
-  TU_ASSERT(ep, );
+  TU_VERIFY(ep, );
 
   xfer_result_t xfer_result;
   switch(hresult) {
@@ -857,7 +882,6 @@ void print_hirq(uint8_t hirq) {
 
   TU_LOG3("\r\n");
 }
-
 #else
   #define print_hirq(hirq)
 #endif
@@ -868,30 +892,20 @@ void hcd_int_handler(uint8_t rhport) {
   if (!hirq) return;
 //  print_hirq(hirq);
 
-//  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true);
-
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
   }
 
-  #if 1
-  // interrupt is disabled, only ack FRAME IRQ and skip the rest
+  // interrupt is disabled by usbh task: only ack FRAME IRQ and skip the rest
   if (_hcd_data.intr_disable_count) {
     if (hirq & HIRQ_FRAME_IRQ) {
       hirq_write(rhport, HIRQ_FRAME_IRQ, true);
     }
-
-    if ((hirq & HIRQ_CONDET_IRQ) && !(_hcd_data.mode & MODE_SOFKAENAB)) {
-      // connection when interrupt is disabled
-      TU_LOG3_INT(_hcd_data.intr_disable_count);
-      return;
-    }
     return;
   }
-  #endif
 
   if (hirq & HIRQ_CONDET_IRQ) {
-    handle_connect_irq(rhport);
+    handle_connect_irq(rhport, true);
   }
 
   // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
-- 
cgit v1.3.1


From 1dd9fa3f307e6f3a847619d587529ea17608c1a3 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Thu, 31 Aug 2023 20:24:56 +0200
Subject: code review: changed to TinyUSB log system

---
 src/class/net/ncm_device.c | 205 +++++++++++++++++++++------------------------
 1 file changed, 96 insertions(+), 109 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 1c6f888cd..d0832cf73 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -59,30 +59,11 @@
 #include "ncm.h"
 
 
-#if !defined(tu_static)  ||  ECLIPSE_GUI
+#if !defined(tu_static)  ||  defined(ECLIPSE_GUI)
     // TinyUSB <=0.15.0 does not know "tu_static"
     #define tu_static static
 #endif
 
-#if 0
-    #define DEBUG_OUT(...)  printf(__VA_ARGS__)
-    #define DEBUG_OUT_ENABLED
-#else
-    #define DEBUG_OUT(...)
-#endif
-
-#if 0
-    #define INFO_OUT(...)   printf(__VA_ARGS__)
-#else
-    #define INFO_OUT(...)
-#endif
-
-#if 1
-    #define ERROR_OUT(...)  printf(__VA_ARGS__)
-#else
-    #define ERROR_OUT(...)
-#endif
-
 // calculate alignment of xmit datagrams within an NTB
 #define XMIT_ALIGN_OFFSET(x)   ((CFG_TUD_NCM_ALIGNMENT - ((x) & (CFG_TUD_NCM_ALIGNMENT - 1))) & (CFG_TUD_NCM_ALIGNMENT - 1))
 
@@ -103,7 +84,7 @@ typedef struct {
     uint8_t     rhport;                            //!< storage of \a rhport because some callbacks are done without it
 
     // recv handling
-    recv_ntb_t  recv_ntb[RECV_NTB_N];              //!< actual recv NTBs
+    CFG_TUSB_MEM_ALIGN recv_ntb_t  recv_ntb[RECV_NTB_N];              //!< actual recv NTBs
     recv_ntb_t *recv_free_ntb[RECV_NTB_N];         //!< free list of recv NTBs
     recv_ntb_t *recv_ready_ntb[RECV_NTB_N];        //!< NTBs waiting for transmission to glue logic
     recv_ntb_t *recv_tinyusb_ntb;                  //!< buffer for the running transfer TinyUSB -> driver
@@ -111,7 +92,7 @@ typedef struct {
     uint16_t               recv_glue_ntb_datagram_ndx;        //!< index into \a recv_glue_ntb_datagram
 
     // xmit handling
-    xmit_ntb_t  xmit_ntb[XMIT_NTB_N];              //!< actual xmit NTBs
+    CFG_TUSB_MEM_ALIGN xmit_ntb_t  xmit_ntb[XMIT_NTB_N];              //!< actual xmit NTBs
     xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N];         //!< free list of xmit NTBs
     xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N];        //!< NTBs waiting for transmission to TinyUSB
     xmit_ntb_t *xmit_tinyusb_ntb;                  //!< buffer for the running transfer driver -> TinyUSB
@@ -159,7 +140,7 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par
 //      ==6 -> SystemView runs fine, iperf also
 //      >6  -> iperf starts to show errors
 //      -> 6 seems to be the best value.  Why?  Don't know, perhaps only on my system?
-//      switch \a INFO_OUT on to see interesting values for this.
+//      switch \a TU_LOG2 on to see interesting values for this.
 //
 //      iperf:    for MSS in 100 200 400 800 1200 1450 1500; do iperf -c 192.168.14.1 -e -i 1 -M $MSS -l 8192 -P 1; sleep 2; done
 //      sysview:  SYSTICKS_PER_SEC=35000, IDLE_US=1000, PRINT_MOD=1000
@@ -192,8 +173,8 @@ tu_static struct ncm_notify_t ncm_notify_speed_change = {
                 .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
                 .wLength  = 8,
         },
-        .downlink = 1000000,
-        .uplink   = 1000000,
+        .downlink = 12000000,
+        .uplink   = 12000000,
 };
 
 
@@ -204,28 +185,28 @@ static void notification_xmit(uint8_t rhport, bool force_next)
  * Notifications are transferred to the host once during connection setup.
  */
 {
-    DEBUG_OUT("notification_xmit(%d, %d) - %d %d\n", force_next, rhport, ncm_interface.notification_xmit_state, ncm_interface.notification_xmit_is_running);
+    TU_LOG3("notification_xmit(%d, %d) - %d %d\n", force_next, rhport, ncm_interface.notification_xmit_state, ncm_interface.notification_xmit_is_running);
 
     if ( !force_next  &&  ncm_interface.notification_xmit_is_running) {
         return;
     }
 
     if (ncm_interface.notification_xmit_state == NOTIFICATION_SPEED) {
-        DEBUG_OUT("  NOTIFICATION_SPEED\n");
+        TU_LOG3("  NOTIFICATION_SPEED\n");
         ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
         usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t*) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
         ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED;
         ncm_interface.notification_xmit_is_running = true;
     }
     else if (ncm_interface.notification_xmit_state == NOTIFICATION_CONNECTED) {
-        DEBUG_OUT("  NOTIFICATION_CONNECTED\n");
+        TU_LOG3("  NOTIFICATION_CONNECTED\n");
         ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
         usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t*) &ncm_notify_connected, sizeof(ncm_notify_connected));
         ncm_interface.notification_xmit_state = NOTIFICATION_DONE;
         ncm_interface.notification_xmit_is_running = true;
     }
     else {
-        DEBUG_OUT("  NOTIFICATION_FINISHED\n");
+        TU_LOG3("  NOTIFICATION_FINISHED\n");
     }
 }   // notification_xmit
 
@@ -241,7 +222,7 @@ static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb)
  * Put NTB into the transmitter free list.
  */
 {
-    DEBUG_OUT("xmit_put_ntb_into_free_list() - %p\n", ncm_interface.xmit_tinyusb_ntb);
+    TU_LOG3("xmit_put_ntb_into_free_list() - %p\n", ncm_interface.xmit_tinyusb_ntb);
 
     if (free_ntb == NULL) {
         // can happen due to ZLPs
@@ -254,7 +235,7 @@ static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb)
             return;
         }
     }
-    ERROR_OUT("(EE) xmit_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
+    TU_LOG1("(EE) xmit_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
 }   // xmit_put_ntb_into_free_list
 
 
@@ -264,7 +245,7 @@ static xmit_ntb_t *xmit_get_free_ntb(void)
  * Get an NTB from the free list
  */
 {
-    DEBUG_OUT("xmit_get_free_ntb()\n");
+    TU_LOG3("xmit_get_free_ntb()\n");
 
     for (int i = 0;  i < XMIT_NTB_N;  ++i) {
         if (ncm_interface.xmit_free_ntb[i] != NULL) {
@@ -283,7 +264,7 @@ static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb)
  * Put a filled NTB into the ready list
  */
 {
-    INFO_OUT("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
+    TU_LOG2("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
 
     for (int i = 0;  i < XMIT_NTB_N;  ++i) {
         if (ncm_interface.xmit_ready_ntb[i] == NULL) {
@@ -291,7 +272,7 @@ static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb)
             return;
         }
     }
-    ERROR_OUT("(EE) xmit_put_ntb_into_ready_list: ready list full\n");  // this should not happen
+    TU_LOG1("(EE) xmit_put_ntb_into_ready_list: ready list full\n");  // this should not happen
 }   // xmit_put_ntb_into_ready_list
 
 
@@ -308,13 +289,13 @@ static xmit_ntb_t *xmit_get_next_ready_ntb(void)
     memmove(ncm_interface.xmit_ready_ntb + 0, ncm_interface.xmit_ready_ntb + 1, sizeof(ncm_interface.xmit_ready_ntb) - sizeof(ncm_interface.xmit_ready_ntb[0]));
     ncm_interface.xmit_ready_ntb[XMIT_NTB_N - 1] = NULL;
 
-    DEBUG_OUT("recv_get_next_ready_ntb: %p\n", r);
+    TU_LOG3("recv_get_next_ready_ntb: %p\n", r);
     return r;
 }   // xmit_get_next_ready_ntb
 
 
 
-static bool xmit_insert_required_zlp(uint8_t rhport, uint16_t xferred_bytes)
+static bool xmit_insert_required_zlp(uint8_t rhport, uint32_t xferred_bytes)
 /**
  * Transmit a ZLP if required
  *
@@ -327,7 +308,7 @@ static bool xmit_insert_required_zlp(uint8_t rhport, uint16_t xferred_bytes)
  *    This must be called from netd_xfer_cb() so that ep_in is ready
  */
 {
-    DEBUG_OUT("xmit_insert_required_zlp(%d,%d)\n", rhport, xferred_bytes);
+    TU_LOG3("xmit_insert_required_zlp(%d,%d)\n", rhport, xferred_bytes);
 
     if (xferred_bytes == 0  ||  xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE != 0) {
         return false;
@@ -336,7 +317,7 @@ static bool xmit_insert_required_zlp(uint8_t rhport, uint16_t xferred_bytes)
     TU_ASSERT(ncm_interface.itf_data_alt == 1, false);
     TU_ASSERT( !usbd_edpt_busy(rhport, ncm_interface.ep_in), false);
 
-    INFO_OUT("xmit_insert_required_zlp! (%u)\n", (unsigned)xferred_bytes);
+    TU_LOG2("xmit_insert_required_zlp! (%u)\n", (unsigned)xferred_bytes);
 
     // start transmission of the ZLP
     usbd_edpt_xfer(rhport, ncm_interface.ep_in, NULL, 0);
@@ -351,18 +332,18 @@ static void xmit_start_if_possible(uint8_t rhport)
  * Start transmission if it there is a waiting packet and if can be done from interface side.
  */
 {
-    DEBUG_OUT("xmit_start_if_possible()\n");
+    TU_LOG3("xmit_start_if_possible()\n");
 
     if (ncm_interface.xmit_tinyusb_ntb != NULL) {
-        DEBUG_OUT("  !xmit_start_if_possible 1\n");
+        TU_LOG3("  !xmit_start_if_possible 1\n");
         return;
     }
     if (ncm_interface.itf_data_alt != 1) {
-        ERROR_OUT("(II) !xmit_start_if_possible 2\n");
+        TU_LOG1("(II) !xmit_start_if_possible 2\n");
         return;
     }
     if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
-        INFO_OUT("  !xmit_start_if_possible 3\n");
+        TU_LOG2("  !xmit_start_if_possible 3\n");
         return;
     }
 
@@ -379,16 +360,16 @@ static void xmit_start_if_possible(uint8_t rhport)
 #ifdef DEBUG_OUT_ENABLED
     {
         uint16_t len = ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength;
-        DEBUG_OUT(" %d\n", len);
+        TU_LOG3(" %d\n", len);
         for (int i = 0;  i < len;  ++i) {
-            DEBUG_OUT(" %02x", ncm_interface.xmit_tinyusb_ntb->data[i]);
+            TU_LOG3(" %02x", ncm_interface.xmit_tinyusb_ntb->data[i]);
         }
-        DEBUG_OUT("\n");
+        TU_LOG3("\n");
     }
 #endif
 
     if (ncm_interface.xmit_glue_ntb_datagram_ndx != 1) {
-        DEBUG_OUT(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength, ncm_interface.xmit_glue_ntb_datagram_ndx);
+        TU_LOG3(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength, ncm_interface.xmit_glue_ntb_datagram_ndx);
     }
 
     // Kick off an endpoint transfer
@@ -402,7 +383,7 @@ static bool xmit_requested_datagram_fits_into_current_ntb(uint16_t datagram_size
  * check if a new datagram fits into the current NTB
  */
 {
-    DEBUG_OUT("xmit_requested_datagram_fits_into_current_ntb(%d) - %p %p\n", datagram_size, ncm_interface.xmit_tinyusb_ntb, ncm_interface.xmit_glue_ntb);
+    TU_LOG3("xmit_requested_datagram_fits_into_current_ntb(%d) - %p %p\n", datagram_size, ncm_interface.xmit_tinyusb_ntb, ncm_interface.xmit_glue_ntb);
 
     if (ncm_interface.xmit_glue_ntb == NULL) {
         return false;
@@ -423,7 +404,7 @@ static bool xmit_setup_next_glue_ntb(void)
  * Setup an NTB for the glue logic
  */
 {
-    DEBUG_OUT("xmit_setup_next_glue_ntb - %p\n", ncm_interface.xmit_glue_ntb);
+    TU_LOG3("xmit_setup_next_glue_ntb - %p\n", ncm_interface.xmit_glue_ntb);
 
     if (ncm_interface.xmit_glue_ntb != NULL) {
         // put NTB into waiting list (the new datagram did not fit in)
@@ -432,7 +413,7 @@ static bool xmit_setup_next_glue_ntb(void)
 
     ncm_interface.xmit_glue_ntb = xmit_get_free_ntb();              // get next buffer (if any)
     if (ncm_interface.xmit_glue_ntb == NULL) {
-        DEBUG_OUT("  xmit_setup_next_glue_ntb - nothing free\n");   // should happen rarely
+        TU_LOG3("  xmit_setup_next_glue_ntb - nothing free\n");   // should happen rarely
         return false;
     }
 
@@ -469,7 +450,7 @@ static recv_ntb_t *recv_get_free_ntb(void)
  * Returned buffer (if any) has the size \a CFG_TUD_NCM_OUT_NTB_MAX_SIZE.
  */
 {
-    DEBUG_OUT("recv_get_free_ntb()\n");
+    TU_LOG3("recv_get_free_ntb()\n");
 
     for (int i = 0;  i < RECV_NTB_N;  ++i) {
         if (ncm_interface.recv_free_ntb[i] != NULL) {
@@ -495,7 +476,7 @@ static recv_ntb_t *recv_get_next_ready_ntb(void)
     memmove(ncm_interface.recv_ready_ntb + 0, ncm_interface.recv_ready_ntb + 1, sizeof(ncm_interface.recv_ready_ntb) - sizeof(ncm_interface.recv_ready_ntb[0]));
     ncm_interface.recv_ready_ntb[RECV_NTB_N - 1] = NULL;
 
-    DEBUG_OUT("recv_get_next_ready_ntb: %p\n", r);
+    TU_LOG3("recv_get_next_ready_ntb: %p\n", r);
     return r;
 }   // recv_get_next_ready_ntb
 
@@ -506,7 +487,7 @@ static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb)
  *
  */
 {
-    DEBUG_OUT("recv_put_ntb_into_free_list(%p)\n", free_ntb);
+    TU_LOG3("recv_put_ntb_into_free_list(%p)\n", free_ntb);
 
     for (int i = 0;  i < RECV_NTB_N;  ++i) {
         if (ncm_interface.recv_free_ntb[i] == NULL) {
@@ -514,7 +495,7 @@ static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb)
             return;
         }
     }
-    ERROR_OUT("(EE) recv_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
+    TU_LOG1("(EE) recv_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
 }   // recv_put_ntb_into_free_list
 
 
@@ -525,7 +506,7 @@ static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
  * put this buffer into the waiting list and free the receive logic.
  */
 {
-    DEBUG_OUT("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
+    TU_LOG3("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
 
     for (int i = 0;  i < RECV_NTB_N;  ++i) {
         if (ncm_interface.recv_ready_ntb[i] == NULL) {
@@ -533,7 +514,7 @@ static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
             return;
         }
     }
-    ERROR_OUT("(EE) recv_put_ntb_into_ready_list: ready list full\n");  // this should not happen
+    TU_LOG1("(EE) recv_put_ntb_into_ready_list: ready list full\n");  // this should not happen
 }   // recv_put_ntb_into_ready_list
 
 
@@ -544,7 +525,7 @@ static void recv_try_to_start_new_reception(uint8_t rhport)
  * Return value is actually not of interest.
  */
 {
-    DEBUG_OUT("recv_try_to_start_new_reception(%d)\n", rhport);
+    TU_LOG3("recv_try_to_start_new_reception(%d)\n", rhport);
 
     if (ncm_interface.itf_data_alt != 1) {
         return;
@@ -552,7 +533,7 @@ static void recv_try_to_start_new_reception(uint8_t rhport)
     if (ncm_interface.recv_tinyusb_ntb != NULL) {
         return;
     }
-    if (usbd_edpt_busy(ncm_interface.rhport, ncm_interface.ep_out)) {
+    if (usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
         return;
     }
 
@@ -562,8 +543,8 @@ static void recv_try_to_start_new_reception(uint8_t rhport)
     }
 
     // initiate transfer
-    DEBUG_OUT("  start reception\n");
-    bool r = usbd_edpt_xfer(0, ncm_interface.ep_out, ncm_interface.recv_tinyusb_ntb->data, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+    TU_LOG3("  start reception\n");
+    bool r = usbd_edpt_xfer(rhport, ncm_interface.ep_out, ncm_interface.recv_tinyusb_ntb->data, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
     if ( !r) {
         recv_put_ntb_into_free_list(ncm_interface.recv_tinyusb_ntb);
         ncm_interface.recv_tinyusb_ntb = NULL;
@@ -572,7 +553,7 @@ static void recv_try_to_start_new_reception(uint8_t rhport)
 
 
 
-static bool recv_validate_datagram(const recv_ntb_t *ntb, uint16_t len)
+static bool recv_validate_datagram(const recv_ntb_t *ntb, uint32_t len)
 /**
  * Validate incoming datagram.
  * \return true if valid
@@ -583,84 +564,86 @@ static bool recv_validate_datagram(const recv_ntb_t *ntb, uint16_t len)
 {
     const nth16_t *nth16 = &(ntb->nth);
 
-    DEBUG_OUT("recv_validate_datagram(%p)\n", ntb);
+    TU_LOG3("recv_validate_datagram(%p)\n", ntb);
 
     //
     // check header
     //
     if (nth16->wHeaderLength != sizeof(nth16_t))
     {
-        ERROR_OUT("(EE) ill nth16 length: %d\n", nth16->wHeaderLength);
+        TU_LOG1("(EE) ill nth16 length: %d\n", nth16->wHeaderLength);
         return false;
     }
     if (nth16->dwSignature != NTH16_SIGNATURE) {
-        ERROR_OUT("(EE) ill signature: 0x%08x\n", (unsigned)nth16->dwSignature);
+        TU_LOG1("(EE) ill signature: 0x%08x\n", (unsigned)nth16->dwSignature);
         return false;
     }
     if (len < sizeof(nth16_t) + sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
-        ERROR_OUT("(EE) ill min len: %d\n", len);
+        TU_LOG1("(EE) ill min len: %d\n", len);
         return false;
     }
     if (nth16->wBlockLength > len) {
-        ERROR_OUT("(EE) ill block length: %d > %d\n", nth16->wBlockLength, len);
+        TU_LOG1("(EE) ill block length: %d > %d\n", nth16->wBlockLength, len);
         return false;
     }
     if (nth16->wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        ERROR_OUT("(EE) ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+        TU_LOG1("(EE) ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
         return false;
     }
     if (nth16->wNdpIndex < sizeof(nth16)  ||  nth16->wNdpIndex > len - (sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t))) {
-        ERROR_OUT("(EE) ill position of first ndp: %d (%d)\n", nth16->wNdpIndex, len);
+        TU_LOG1("(EE) ill position of first ndp: %d (%d)\n", nth16->wNdpIndex, len);
         return false;
     }
 
     //
     // check (first) NDP(16)
     //
-    const ndp16_t *ndp16 = (ndp16_t *)(ntb->data + nth16->wNdpIndex);
+    const ndp16_t *ndp16 = (const ndp16_t *)(ntb->data + nth16->wNdpIndex);
 
     if (ndp16->wLength < sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
-        ERROR_OUT("(EE) ill ndp16 length: %d\n", ndp16->wLength);
+        TU_LOG1("(EE) ill ndp16 length: %d\n", ndp16->wLength);
         return false;
     }
     if (ndp16->dwSignature != NDP16_SIGNATURE_NCM0  &&  ndp16->dwSignature != NDP16_SIGNATURE_NCM1) {
-        ERROR_OUT("(EE) ill signature: 0x%08x\n", (unsigned)ndp16->dwSignature);
+        TU_LOG1("(EE) ill signature: 0x%08x\n", (unsigned)ndp16->dwSignature);
         return false;
     }
     if (ndp16->wNextNdpIndex != 0) {
-        ERROR_OUT("(EE) cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
+        TU_LOG1("(EE) cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
         return false;
     }
 
-    const ndp16_datagram_t *ndp16_datagram = (ndp16_datagram_t *)(ntb->data + nth16->wNdpIndex + sizeof(ndp16_t));
+    const ndp16_datagram_t *ndp16_datagram = (const ndp16_datagram_t *)(ntb->data + nth16->wNdpIndex + sizeof(ndp16_t));
     int ndx = 0;
-    int max_ndx = (ndp16->wLength - sizeof(ndp16_t)) / sizeof(ndp16_datagram_t);
+    uint16_t max_ndx = (uint16_t)((ndp16->wLength - sizeof(ndp16_t)) / sizeof(ndp16_datagram_t));
 
     if (max_ndx > 2) {
         // number of datagrams in NTB > 1
-        INFO_OUT("<< %d (%d)\n", max_ndx - 1, ntb->nth.wBlockLength);
+        TU_LOG2("<< %d (%d)\n", max_ndx - 1, ntb->nth.wBlockLength);
     }
     if (ndp16_datagram[max_ndx-1].wDatagramIndex != 0  ||  ndp16_datagram[max_ndx-1].wDatagramLength != 0) {
-        INFO_OUT("  max_ndx != 0\n");
+        TU_LOG2("  max_ndx != 0\n");
         return false;
     }
     while (ndp16_datagram[ndx].wDatagramIndex != 0  &&  ndp16_datagram[ndx].wDatagramLength != 0) {
-        DEBUG_OUT("  << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
+        TU_LOG3("  << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
         if (ndp16_datagram[ndx].wDatagramIndex > len) {
-            ERROR_OUT("(EE) ill start of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
+            TU_LOG1("(EE) ill start of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
             return false;
         }
         if (ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength > len) {
-            ERROR_OUT("(EE) ill end of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
+            TU_LOG1("(EE) ill end of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
             return false;
         }
         ++ndx;
     }
 
-    for (int i = 0;  i < len;  ++i) {
-        DEBUG_OUT(" %02x", ntb->data[i]);
+#if CFG_TUSB_DEBUG >= 3
+    for (uint32_t i = 0;  i < len;  ++i) {
+        TU_LOG3(" %02x", ntb->data[i]);
     }
-    DEBUG_OUT("\n");
+    TU_LOG3("\n");
+#endif
 
     // -> ntb contains a valid packet structure
     //    ok... I did not check for garbage within the datagram indices...
@@ -674,11 +657,11 @@ static void recv_transfer_datagram_to_glue_logic(void)
  * Transfer the next (pending) datagram to the glue logic and return receive buffer if empty.
  */
 {
-    DEBUG_OUT("recv_transfer_datagram_to_glue_logic()\n");
+    TU_LOG3("recv_transfer_datagram_to_glue_logic()\n");
 
     if (ncm_interface.recv_glue_ntb == NULL) {
         ncm_interface.recv_glue_ntb = recv_get_next_ready_ntb();
-        DEBUG_OUT("  new buffer for glue logic: %p\n", ncm_interface.recv_glue_ntb);
+        TU_LOG3("  new buffer for glue logic: %p\n", ncm_interface.recv_glue_ntb);
         ncm_interface.recv_glue_ntb_datagram_ndx = 0;
     }
 
@@ -688,21 +671,21 @@ static void recv_transfer_datagram_to_glue_logic(void)
                                                                     + sizeof(ndp16_t));
 
         if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex == 0) {
-            ERROR_OUT("(EE) SOMETHING WENT WRONG 1\n");
+            TU_LOG1("(EE) SOMETHING WENT WRONG 1\n");
         }
         else if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength == 0) {
-            ERROR_OUT("(EE) SOMETHING WENT WRONG 2\n");
+            TU_LOG1("(EE) SOMETHING WENT WRONG 2\n");
         }
         else {
             uint16_t datagramIndex  = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex;
             uint16_t datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength;
 
-            DEBUG_OUT("  recv[%d] - %d %d\n", ncm_interface.recv_glue_ntb_datagram_ndx, datagramIndex, datagramLength);
+            TU_LOG3("  recv[%d] - %d %d\n", ncm_interface.recv_glue_ntb_datagram_ndx, datagramIndex, datagramLength);
             if (tud_network_recv_cb(ncm_interface.recv_glue_ntb->data + datagramIndex, datagramLength)) {
                 //
                 // send datagram successfully to glue logic
                 //
-                DEBUG_OUT("    OK\n");
+                TU_LOG3("    OK\n");
                 datagramIndex  = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramIndex;
                 datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramLength;
 
@@ -734,7 +717,7 @@ bool tud_network_can_xmit(uint16_t size)
  * and transmission operation.
  */
 {
-    DEBUG_OUT("tud_network_can_xmit(%d)\n", size);
+    TU_LOG3("tud_network_can_xmit(%d)\n", size);
 
     TU_ASSERT(size <= CFG_TUD_NCM_OUT_NTB_MAX_SIZE - (sizeof(nth16_t) + sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)), false);
 
@@ -743,7 +726,7 @@ bool tud_network_can_xmit(uint16_t size)
         return true;
     }
     xmit_start_if_possible(ncm_interface.rhport);
-    ERROR_OUT("(II) tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
+    TU_LOG1("(II) tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
     return false;
 }   // tud_network_can_xmit
 
@@ -755,10 +738,10 @@ void tud_network_xmit(void *ref, uint16_t arg)
  * If currently no transmission is started, then initiate transmission.
  */
 {
-    DEBUG_OUT("tud_network_xmit(%p, %d)\n", ref, arg);
+    TU_LOG3("tud_network_xmit(%p, %d)\n", ref, arg);
 
     if (ncm_interface.xmit_glue_ntb == NULL) {
-        ERROR_OUT("(EE) tud_network_xmit: no buffer\n");             // must not happen (really)
+        TU_LOG1("(EE) tud_network_xmit: no buffer\n");             // must not happen (really)
         return;
     }
 
@@ -772,10 +755,10 @@ void tud_network_xmit(void *ref, uint16_t arg)
     ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramLength = size;
     ncm_interface.xmit_glue_ntb_datagram_ndx += 1;
 
-    ntb->nth.wBlockLength += size + XMIT_ALIGN_OFFSET(size);
+    ntb->nth.wBlockLength += (uint16_t)(size + XMIT_ALIGN_OFFSET(size));
 
     if (ntb->nth.wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        ERROR_OUT("(II) tud_network_xmit: buffer overflow\n");       // must not happen (really)
+        TU_LOG1("(II) tud_network_xmit: buffer overflow\n");       // must not happen (really)
         return;
     }
 
@@ -789,7 +772,7 @@ void tud_network_recv_renew(void)
  * Keep the receive logic busy and transfer pending packets to the glue logic.
  */
 {
-    DEBUG_OUT("tud_network_recv_renew()\n");
+    TU_LOG3("tud_network_recv_renew()\n");
 
     recv_transfer_datagram_to_glue_logic();
     recv_try_to_start_new_reception(ncm_interface.rhport);
@@ -802,7 +785,7 @@ void tud_network_recv_renew_r(uint8_t rhport)
  * Same as tud_network_recv_renew() but knows \a rhport
  */
 {
-    DEBUG_OUT("tud_network_recv_renew_r(%d)\n", rhport);
+    TU_LOG3("tud_network_recv_renew_r(%d)\n", rhport);
 
     ncm_interface.rhport = rhport;
     tud_network_recv_renew();
@@ -819,7 +802,7 @@ void netd_init(void)
  * Might be called several times.
  */
 {
-    DEBUG_OUT("netd_init()\n");
+    TU_LOG3("netd_init()\n");
 
     memset( &ncm_interface, 0, sizeof(ncm_interface));
 
@@ -839,7 +822,9 @@ void netd_reset(uint8_t rhport)
  * In this driver this is the same as netd_init()
  */
 {
-    DEBUG_OUT("netd_reset(%d)\n", rhport);
+    (void)rhport;
+
+    TU_LOG3("netd_reset(%d)\n", rhport);
 
     netd_init();
 }   // netd_reset
@@ -862,7 +847,7 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16
  * - USB interface is open
  */
 {
-    DEBUG_OUT("netd_open(%d,%p,%d)\n", rhport, itf_desc, max_len);
+    TU_LOG3("netd_open(%d,%p,%d)\n", rhport, itf_desc, max_len);
 
     TU_ASSERT(ncm_interface.ep_notif == 0, 0);           // assure that the interface is only opened once
 
@@ -915,7 +900,9 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
  * Handle TinyUSB requests to process transfer events.
  */
 {
-    DEBUG_OUT("netd_xfer_cb(%d,%d,%d,%u)\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
+    (void)result;
+
+    TU_LOG3("netd_xfer_cb(%d,%d,%d,%u)\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
 
     if (ep_addr == ncm_interface.ep_out) {
         //
@@ -924,10 +911,10 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
         // - if ready transfer datagrams to the glue logic for further processing
         // - if there is a free receive buffer, initiate reception
         //
-        DEBUG_OUT("  EP_OUT %d %d %d %u\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
+        TU_LOG3("  EP_OUT %d %d %d %u\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
         if ( !recv_validate_datagram( ncm_interface.recv_tinyusb_ntb, xferred_bytes)) {
             // verification failed: ignore NTB and return it to free
-            ERROR_OUT("(EE) VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
+            TU_LOG1("(EE) VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
         }
         else {
             // packet ok -> put it into ready list
@@ -943,7 +930,7 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
         // - insert ZLPs when necessary
         // - if there is another transmit NTB waiting, try to start transmission
         //
-        DEBUG_OUT("  EP_IN %d %u\n", ncm_interface.itf_data_alt, (unsigned)xferred_bytes);
+        TU_LOG3("  EP_IN %d %u\n", ncm_interface.itf_data_alt, (unsigned)xferred_bytes);
         xmit_put_ntb_into_free_list(ncm_interface.xmit_tinyusb_ntb);
         ncm_interface.xmit_tinyusb_ntb = NULL;
         if ( !xmit_insert_required_zlp(rhport, xferred_bytes)) {
@@ -954,7 +941,7 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
         //
         // next transfer on notification channel
         //
-        DEBUG_OUT("  EP_NOTIF\n");
+        TU_LOG3("  EP_NOTIF\n");
         notification_xmit(rhport, true);
     }
 
@@ -969,7 +956,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
  * At startup transmission of notification packets are done here.
  */
 {
-    DEBUG_OUT("netd_control_xfer_cb(%d, %d, %p)\n", rhport, stage, request);
+    TU_LOG3("netd_control_xfer_cb(%d, %d, %p)\n", rhport, stage, request);
 
     if (stage != CONTROL_STAGE_SETUP) {
         return true;
@@ -981,7 +968,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
                 case TUSB_REQ_GET_INTERFACE: {
                     TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
 
-                    DEBUG_OUT("  TUSB_REQ_GET_INTERFACE - %d\n", ncm_interface.itf_data_alt);
+                    TU_LOG3("  TUSB_REQ_GET_INTERFACE - %d\n", ncm_interface.itf_data_alt);
                     tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
                 }
                 break;
@@ -989,8 +976,8 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
                 case TUSB_REQ_SET_INTERFACE: {
                     TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex  &&  request->wValue < 2, false);
 
-                    ncm_interface.itf_data_alt = request->wValue;
-                    DEBUG_OUT("  TUSB_REQ_SET_INTERFACE - %d %d %d\n", ncm_interface.itf_data_alt, request->wIndex, ncm_interface.itf_num);
+                    ncm_interface.itf_data_alt = (uint8_t)request->wValue;
+                    TU_LOG3("  TUSB_REQ_SET_INTERFACE - %d %d %d\n", ncm_interface.itf_data_alt, request->wIndex, ncm_interface.itf_num);
 
                     if (ncm_interface.itf_data_alt == 1) {
                         tud_network_recv_renew_r(rhport);
@@ -1009,12 +996,12 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         case TUSB_REQ_TYPE_CLASS:
             TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
 
-            DEBUG_OUT("  TUSB_REQ_TYPE_CLASS: %d\n", request->bRequest);
+            TU_LOG3("  TUSB_REQ_TYPE_CLASS: %d\n", request->bRequest);
 
             if (request->bRequest == NCM_GET_NTB_PARAMETERS) {
                 // transfer NTB parameters to host.
                 // TODO can one assume, that tud_control_xfer() succeeds?
-                DEBUG_OUT("    NCM_GET_NTB_PARAMETERS\n");
+                TU_LOG3("    NCM_GET_NTB_PARAMETERS\n");
                 tud_control_xfer(rhport, request, (void*) (uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
             }
             break;
-- 
cgit v1.3.1


From 51ea467350f84b92439d0890a4b12bd55e2eff91 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Thu, 31 Aug 2023 20:34:12 +0200
Subject: removed debug comment

---
 src/class/net/ncm_device.c | 12 ------------
 1 file changed, 12 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index d0832cf73..9adb3df0d 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -134,18 +134,6 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par
         .wNtbOutMaxDatagrams     = 6                                     // 0=no limit
 };
 
-// Some confusing remarks about wNtbOutMaxDatagrams...
-//      ==1 -> SystemView packets/s goes up to 2000 and events are lost during startup
-//      ==0 -> SystemView runs fine, iperf shows in wireshark a lot of error
-//      ==6 -> SystemView runs fine, iperf also
-//      >6  -> iperf starts to show errors
-//      -> 6 seems to be the best value.  Why?  Don't know, perhaps only on my system?
-//      switch \a TU_LOG2 on to see interesting values for this.
-//
-//      iperf:    for MSS in 100 200 400 800 1200 1450 1500; do iperf -c 192.168.14.1 -e -i 1 -M $MSS -l 8192 -P 1; sleep 2; done
-//      sysview:  SYSTICKS_PER_SEC=35000, IDLE_US=1000, PRINT_MOD=1000
-//
-
 //-----------------------------------------------------------------------------
 //
 // everything about notifications
-- 
cgit v1.3.1


From 1b9108ea0dc237835e801d26cc7eef052acad987 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 6 Sep 2023 17:11:35 +0700
Subject: minor debug clean up

---
 src/common/tusb_common.h |  6 ++----
 src/common/tusb_debug.h  | 37 ++++++++++++++-----------------------
 src/device/usbd.c        |  2 +-
 src/device/usbd_pvt.h    | 15 ++++++---------
 src/host/usbh.c          |  6 ++----
 5 files changed, 25 insertions(+), 41 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index c303c6eaf..6fffed11c 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -122,13 +122,11 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, c
 
 
 //------------- Bytes -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) {
   return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) {
   return (uint16_t) ((((uint16_t) high) << 8) | low);
 }
 
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 36507041f..99176c02a 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -58,16 +58,14 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
   #define tu_printf    printf
 #endif
 
-static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
-{
+static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
   for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
 }
 
 // Log with Level
 #define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
 #define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
-#define TU_LOG_ARR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _ARR)(__VA_ARGS__)
-#define TU_LOG_PTR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _PTR)(__VA_ARGS__)
+#define TU_LOG_BUF(n, ...)    TU_XSTRCAT3(TU_LOG, n, _BUF)(__VA_ARGS__)
 #define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
 #define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
 #define TU_LOG_LOCATION()     tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
@@ -76,8 +74,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 // Log Level 1: Error
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
-#define TU_LOG1_ARR(_x, _n)   tu_print_arr((uint8_t const*)(_x), _n)
-#define TU_LOG1_PTR(_x)       tu_print_arr((uint8_t const*)(_x), sizeof(*(_x)))
+#define TU_LOG1_BUF(_x, _n)   tu_print_buf((uint8_t const*)(_x), _n)
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
 #define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
@@ -85,8 +82,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 #if CFG_TUSB_DEBUG >= 2
   #define TU_LOG2             TU_LOG1
   #define TU_LOG2_MEM         TU_LOG1_MEM
-  #define TU_LOG2_ARR         TU_LOG1_ARR
-  #define TU_LOG2_PTR         TU_LOG1_PTR
+  #define TU_LOG2_BUF         TU_LOG1_BUF
   #define TU_LOG2_INT         TU_LOG1_INT
   #define TU_LOG2_HEX         TU_LOG1_HEX
 #endif
@@ -95,30 +91,25 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 #if CFG_TUSB_DEBUG >= 3
   #define TU_LOG3             TU_LOG1
   #define TU_LOG3_MEM         TU_LOG1_MEM
-  #define TU_LOG3_ARR         TU_LOG1_ARR
-  #define TU_LOG3_PTR         TU_LOG1_PTR
+  #define TU_LOG3_BUF         TU_LOG1_BUF
   #define TU_LOG3_INT         TU_LOG1_INT
   #define TU_LOG3_HEX         TU_LOG1_HEX
 #endif
 
-typedef struct
-{
+typedef struct {
   uint32_t key;
   const char* data;
 } tu_lookup_entry_t;
 
-typedef struct
-{
+typedef struct {
   uint16_t count;
   tu_lookup_entry_t const* items;
 } tu_lookup_table_t;
 
-static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
-{
+static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) {
   tu_static char not_found[11];
 
-  for(uint16_t i=0; i<p_table->count; i++)
-  {
+  for(uint16_t i=0; i<p_table->count; i++) {
     if (p_table->items[i].key == key) return p_table->items[i].data;
   }
 
@@ -133,7 +124,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG
   #define TU_LOG(n, ...)
   #define TU_LOG_MEM(n, ...)
-  #define TU_LOG_PTR(n, ...)
+  #define TU_LOG_BUF(n, ...)
   #define TU_LOG_INT(n, ...)
   #define TU_LOG_HEX(n, ...)
   #define TU_LOG_LOCATION()
@@ -144,14 +135,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 
 #define TU_LOG0(...)
 #define TU_LOG0_MEM(...)
-#define TU_LOG0_PTR(...)
+#define TU_LOG0_BUF(...)
 #define TU_LOG0_INT(...)
 #define TU_LOG0_HEX(...)
 
 #ifndef TU_LOG1
   #define TU_LOG1(...)
   #define TU_LOG1_MEM(...)
-  #define TU_LOG1_PTR(...)
+  #define TU_LOG1_BUF(...)
   #define TU_LOG1_INT(...)
   #define TU_LOG1_HEX(...)
 #endif
@@ -159,7 +150,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG2
   #define TU_LOG2(...)
   #define TU_LOG2_MEM(...)
-  #define TU_LOG2_PTR(...)
+  #define TU_LOG2_BUF(...)
   #define TU_LOG2_INT(...)
   #define TU_LOG2_HEX(...)
 #endif
@@ -167,7 +158,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG3
   #define TU_LOG3(...)
   #define TU_LOG3_MEM(...)
-  #define TU_LOG3_PTR(...)
+  #define TU_LOG3_BUF(...)
   #define TU_LOG3_INT(...)
   #define TU_LOG3_HEX(...)
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index f0d9fba52..50941c46f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -506,7 +506,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
-        TU_LOG_PTR(CFG_TUD_LOG_LEVEL, &event.setup_received);
+        TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
         TU_LOG_USBD("\r\n");
 
         // Mark as connected after receiving 1st setup packet.
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 16585167f..153be7cee 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -23,8 +23,8 @@
  *
  * This file is part of the TinyUSB stack.
  */
-#ifndef USBD_PVT_H_
-#define USBD_PVT_H_
+#ifndef _TUSB_USBD_PVT_H_
+#define _TUSB_USBD_PVT_H_
 
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
@@ -44,8 +44,7 @@
 // Class Driver API
 //--------------------------------------------------------------------+
 
-typedef struct
-{
+typedef struct {
   #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   char const* name;
   #endif
@@ -111,8 +110,7 @@ bool usbd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endp
 
 // Check if endpoint is ready (not busy and not stalled)
 TU_ATTR_ALWAYS_INLINE static inline
-bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) {
   return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr);
 }
 
@@ -124,11 +122,10 @@ void usbd_sof_enable(uint8_t rhport, bool en);
  *------------------------------------------------------------------*/
 
 bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in);
-void usbd_defer_func( osal_task_func_t func, void* param, bool in_isr );
-
+void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr);
 
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* USBD_PVT_H_ */
+#endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index bacb3a719..e60e680c2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -583,7 +583,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
   TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
               (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
                   tu_str_std_request[xfer->setup->bRequest] : "Class Request");
-  TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup);
+  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8);
   TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb) {
@@ -660,10 +660,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
   if (XFER_RESULT_SUCCESS != result) {
     TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
-    #if CFG_TUSB_DEBUG == 1
-    TU_LOG1_PTR(request);
+    TU_LOG1_BUF(request, 8);
     TU_LOG1("\r\n");
-    #endif
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);
-- 
cgit v1.3.1


From 21ab40bab2e2fee28fa595f648a17944696c3d65 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 7 Sep 2023 12:38:18 +0700
Subject: - wrap up hcd max3421, work well with nrf52840 - also add
 usbh_defer_func()

---
 hw/bsp/nrf/family.c                       |  7 ++++--
 src/host/usbh.c                           | 26 ++++++++++++----------
 src/host/usbh_pvt.h                       | 10 ++++-----
 src/portable/analog/max3421/hcd_max3421.c | 36 ++-----------------------------
 4 files changed, 27 insertions(+), 52 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 7358458ce..39ce179e8 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -109,10 +109,12 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
+  // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
+  // when disabled
   if (enabled) {
-    nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
+    NVIC_EnableIRQ(GPIOTE_IRQn);
   } else {
-    nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN);
+    NVIC_DisableIRQ(GPIOTE_IRQn);
   }
 }
 
@@ -266,6 +268,7 @@ void board_init(void) {
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
   nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
+  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
 #endif
 
 }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e60e680c2..e332f35cc 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -753,29 +753,33 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
 // USBH API For Class Driver
 //--------------------------------------------------------------------+
 
-uint8_t usbh_get_rhport(uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+uint8_t usbh_get_rhport(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   return dev ? dev->rhport : _dev0.rhport;
 }
 
-uint8_t* usbh_get_enum_buf(void)
-{
+uint8_t *usbh_get_enum_buf(void) {
   return _usbh_ctrl_buf;
 }
 
-void usbh_int_set(bool enabled)
-{
+void usbh_int_set(bool enabled) {
   // TODO all host controller if multiple are used since they shared the same event queue
-  if (enabled)
-  {
+  if (enabled) {
     hcd_int_enable(_usbh_controller);
-  }else
-  {
+  } else {
     hcd_int_disable(_usbh_controller);
   }
 }
 
+void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
+  hcd_event_t event = { 0 };
+  event.event_id = USBH_EVENT_FUNC_CALL;
+  event.func_call.func = func;
+  event.func_call.param = param;
+
+  osal_queue_send(_usbh_q, &event, in_isr);
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 0b58a91bc..2b61a77db 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_USBH_CLASSDRIVER_H_
-#define _TUSB_USBH_CLASSDRIVER_H_
+#ifndef _TUSB_USBH_PVT_H_
+#define _TUSB_USBH_PVT_H_
 
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
@@ -76,6 +76,8 @@ uint8_t* usbh_get_enum_buf(void);
 
 void usbh_int_set(bool enabled);
 
+void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr);
+
 //--------------------------------------------------------------------+
 // USBH Endpoint API
 //--------------------------------------------------------------------+
@@ -85,12 +87,10 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 TU_ATTR_ALWAYS_INLINE
-static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) {
   return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0);
 }
 
-
 // Claim an endpoint before submitting a transfer.
 // If caller does not make any transfer, it must release endpoint for others.
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index c61389cb9..95cf5516e 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -194,7 +194,6 @@ typedef struct {
   uint8_t hxfr;
 
   atomic_flag busy; // busy transferring
-  volatile uint8_t intr_disable_count;
   volatile uint16_t frame_count;
 
   max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
@@ -241,14 +240,6 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, true);
     (void) osal_mutex_unlock(_hcd_data.spi_mutex);
-
-    // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
-    // It would be ok if we are operating since SOF will re-trigger interrupt.
-    // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
-    if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
-      handle_connect_irq(rhport, false);
-      hirq_write(rhport, HIRQ_CONDET_IRQ, false);
-    }
   }
 }
 
@@ -470,28 +461,13 @@ bool hcd_init(uint8_t rhport) {
 // Enable USB interrupt
 // Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
-//  tuh_max3421e_int_api(rhport, true);
-
-  (void) rhport;
-  if (_hcd_data.intr_disable_count) {
-    _hcd_data.intr_disable_count--;
-  }
-
-  // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
-  // It would be ok if we are operating since SOF will re-trigger interrupt.
-  // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
-//  if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
-//    handle_connect_irq(rhport, false);
-//    hirq_write(rhport, HIRQ_CONDET_IRQ, false);
-//  }
+  tuh_max3421e_int_api(rhport, true);
 }
 
 // Disable USB interrupt
 // Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  //tuh_max3421e_int_api(rhport, false);
-  (void) rhport;
-  _hcd_data.intr_disable_count++;
+  tuh_max3421e_int_api(rhport, false);
 }
 
 // Get frame number (1ms)
@@ -896,14 +872,6 @@ void hcd_int_handler(uint8_t rhport) {
     _hcd_data.frame_count++;
   }
 
-  // interrupt is disabled by usbh task: only ack FRAME IRQ and skip the rest
-  if (_hcd_data.intr_disable_count) {
-    if (hirq & HIRQ_FRAME_IRQ) {
-      hirq_write(rhport, HIRQ_FRAME_IRQ, true);
-    }
-    return;
-  }
-
   if (hirq & HIRQ_CONDET_IRQ) {
     handle_connect_irq(rhport, true);
   }
-- 
cgit v1.3.1


From f1d3663d24f04dbb68732f8287c516abd0b7ecfb Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Fri, 8 Sep 2023 07:01:13 +0200
Subject: minor changes to comments and debug output

---
 src/class/net/ncm_device.c | 24 +++++++++---------------
 1 file changed, 9 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 9adb3df0d..d803d6429 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -59,11 +59,6 @@
 #include "ncm.h"
 
 
-#if !defined(tu_static)  ||  defined(ECLIPSE_GUI)
-    // TinyUSB <=0.15.0 does not know "tu_static"
-    #define tu_static static
-#endif
-
 // calculate alignment of xmit datagrams within an NTB
 #define XMIT_ALIGN_OFFSET(x)   ((CFG_TUD_NCM_ALIGNMENT - ((x) & (CFG_TUD_NCM_ALIGNMENT - 1))) & (CFG_TUD_NCM_ALIGNMENT - 1))
 
@@ -84,7 +79,7 @@ typedef struct {
     uint8_t     rhport;                            //!< storage of \a rhport because some callbacks are done without it
 
     // recv handling
-    CFG_TUSB_MEM_ALIGN recv_ntb_t  recv_ntb[RECV_NTB_N];              //!< actual recv NTBs
+    CFG_TUSB_MEM_ALIGN recv_ntb_t  recv_ntb[RECV_NTB_N]; //!< actual recv NTBs
     recv_ntb_t *recv_free_ntb[RECV_NTB_N];         //!< free list of recv NTBs
     recv_ntb_t *recv_ready_ntb[RECV_NTB_N];        //!< NTBs waiting for transmission to glue logic
     recv_ntb_t *recv_tinyusb_ntb;                  //!< buffer for the running transfer TinyUSB -> driver
@@ -92,7 +87,7 @@ typedef struct {
     uint16_t               recv_glue_ntb_datagram_ndx;        //!< index into \a recv_glue_ntb_datagram
 
     // xmit handling
-    CFG_TUSB_MEM_ALIGN xmit_ntb_t  xmit_ntb[XMIT_NTB_N];              //!< actual xmit NTBs
+    CFG_TUSB_MEM_ALIGN xmit_ntb_t  xmit_ntb[XMIT_NTB_N]; //!< actual xmit NTBs
     xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N];         //!< free list of xmit NTBs
     xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N];        //!< NTBs waiting for transmission to TinyUSB
     xmit_ntb_t *xmit_tinyusb_ntb;                  //!< buffer for the running transfer driver -> TinyUSB
@@ -327,7 +322,7 @@ static void xmit_start_if_possible(uint8_t rhport)
         return;
     }
     if (ncm_interface.itf_data_alt != 1) {
-        TU_LOG1("(II) !xmit_start_if_possible 2\n");
+        TU_LOG1("(EE) !xmit_start_if_possible 2\n");
         return;
     }
     if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
@@ -472,7 +467,7 @@ static recv_ntb_t *recv_get_next_ready_ntb(void)
 
 static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb)
 /**
- *
+ * Put NTB into the receiver free list.
  */
 {
     TU_LOG3("recv_put_ntb_into_free_list(%p)\n", free_ntb);
@@ -490,8 +485,8 @@ static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb)
 
 static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
 /**
- * The \a ncm_interface.recv_tinyusb_ntb is filled,
- * put this buffer into the waiting list and free the receive logic.
+ * \a ready_ntb holds a validated NTB,
+ * put this buffer into the waiting list.
  */
 {
     TU_LOG3("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
@@ -510,7 +505,6 @@ static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
 static void recv_try_to_start_new_reception(uint8_t rhport)
 /**
  * If possible, start a new reception TinyUSB -> driver.
- * Return value is actually not of interest.
  */
 {
     TU_LOG3("recv_try_to_start_new_reception(%d)\n", rhport);
@@ -552,7 +546,7 @@ static bool recv_validate_datagram(const recv_ntb_t *ntb, uint32_t len)
 {
     const nth16_t *nth16 = &(ntb->nth);
 
-    TU_LOG3("recv_validate_datagram(%p)\n", ntb);
+    TU_LOG3("recv_validate_datagram(%p, %d)\n", ntb, (int)len);
 
     //
     // check header
@@ -714,7 +708,7 @@ bool tud_network_can_xmit(uint16_t size)
         return true;
     }
     xmit_start_if_possible(ncm_interface.rhport);
-    TU_LOG1("(II) tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
+    TU_LOG2("tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
     return false;
 }   // tud_network_can_xmit
 
@@ -746,7 +740,7 @@ void tud_network_xmit(void *ref, uint16_t arg)
     ntb->nth.wBlockLength += (uint16_t)(size + XMIT_ALIGN_OFFSET(size));
 
     if (ntb->nth.wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        TU_LOG1("(II) tud_network_xmit: buffer overflow\n");       // must not happen (really)
+        TU_LOG1("(EE) tud_network_xmit: buffer overflow\n");       // must not happen (really)
         return;
     }
 
-- 
cgit v1.3.1


From 7ce4cfa638a86bfabd7ce8147ea5468d69c1af21 Mon Sep 17 00:00:00 2001
From: maidnl <d.aimo@arduino.cc>
Date: Fri, 8 Sep 2023 10:12:03 +0200
Subject: renesas: added wait function for IN transaction

This fixes a problem found on MSD class where data read from from disks were sometimes partially overwritten by the status MSD message ("USBS...").
The function introduced wait for the hw fifo pipe to be empty, that prevent that new writing in the fife overwrite data which are not yet be transmitted by hw.
---
 src/portable/renesas/rusb2/dcd_rusb2.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 3ec1b70b5..68ef5890f 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -266,6 +266,13 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void
   tu_fifo_advance_write_pointer(f, count);
 }
 
+
+static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) {
+  TU_ASSERT(num);
+  while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {}
+}
+
+
 //--------------------------------------------------------------------+
 // Pipe Transfer
 //--------------------------------------------------------------------+
@@ -339,6 +346,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
   const unsigned rem  = pipe->remaining;
 
   if (!rem) {
+    wait_pipe_fifo_empty(rusb, num);
     pipe->buf = NULL;
     return true;
   }
-- 
cgit v1.3.1


From 228acbeac2642534753beffd866db2a7eab45e31 Mon Sep 17 00:00:00 2001
From: maidnl <d.aimo@arduino.cc>
Date: Fri, 8 Sep 2023 15:48:05 +0200
Subject: wait_pipe_fifo_empty() now returns bool (as expected using TU_ASSERT
 macro)

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 68ef5890f..24edc30e7 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -267,9 +267,10 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void
 }
 
 
-static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) {
+static bool wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) {
   TU_ASSERT(num);
   while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {}
+  return true;
 }
 
 
-- 
cgit v1.3.1


From c074488f75522c7c29dc7853aa2d8597b4858f89 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 9 Sep 2023 12:20:16 +0700
Subject: minor rename

---
 hw/bsp/nrf/boards/feather_nrf52840_express/board.h |  10 +-
 hw/bsp/nrf/boards/pca10056/board.h                 |  10 +-
 hw/bsp/nrf/boards/pca10095/board.h                 |  10 +-
 hw/bsp/nrf/family.c                                |  22 +--
 hw/bsp/samd51/boards/metro_m4_express/board.h      |  12 +-
 hw/bsp/samd51/family.c                             | 183 +++++++++++----------
 src/portable/analog/max3421/hcd_max3421.c          |  14 +-
 7 files changed, 131 insertions(+), 130 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index e6e7590ac..76100a14a 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -46,11 +46,11 @@
 #define UART_TX_PIN     25
 
 // SPI for USB host shield
-#define MAX3421E_SCK_PIN  14
-#define MAX3421E_MOSI_PIN 13
-#define MAX3421E_MISO_PIN 15
-#define MAX3421E_CS_PIN   27
-#define MAX3241E_INTR_PIN 26
+#define MAX3421_SCK_PIN  14
+#define MAX3421_MOSI_PIN 13
+#define MAX3421_MISO_PIN 15
+#define MAX3421_CS_PIN   27
+#define MAX3421_INTR_PIN 26
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index 16d31addb..9459e7911 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -46,11 +46,11 @@
 #define UART_TX_PIN           6
 
 // SPI for USB host shield
-#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
-#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
-#define MAX3421E_MISO_PIN _PINNUM(1, 14)
-#define MAX3421E_CS_PIN   _PINNUM(1, 12)
-#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+#define MAX3421_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421_MISO_PIN _PINNUM(1, 14)
+#define MAX3421_CS_PIN   _PINNUM(1, 12)
+#define MAX3421_INTR_PIN _PINNUM(1, 11)
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
index b9d3a19dc..ad3379bf6 100644
--- a/hw/bsp/nrf/boards/pca10095/board.h
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -46,11 +46,11 @@
 #define UART_TX_PIN           33
 
 // SPI for USB host shield
-#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
-#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
-#define MAX3421E_MISO_PIN _PINNUM(1, 14)
-#define MAX3421E_CS_PIN   _PINNUM(1, 12)
-#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+#define MAX3421_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421_MISO_PIN _PINNUM(1, 14)
+#define MAX3421_CS_PIN   _PINNUM(1, 12)
+#define MAX3421_INTR_PIN _PINNUM(1, 11)
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 47c765a96..6fcfd9476 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -97,8 +97,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 
-void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
-  if (!(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
+void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+  if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
 
   tuh_int_handler(1);
 }
@@ -207,14 +207,14 @@ void board_init(void) {
   #endif
 
   // manually manage CS
-  nrf_gpio_cfg_output(MAX3421E_CS_PIN);
-  nrf_gpio_pin_write(MAX3421E_CS_PIN, 1);
+  nrf_gpio_cfg_output(MAX3421_CS_PIN);
+  nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
 
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
-      .sck_pin        = MAX3421E_SCK_PIN,
-      .mosi_pin       = MAX3421E_MOSI_PIN,
-      .miso_pin       = MAX3421E_MISO_PIN,
+      .sck_pin        = MAX3421_SCK_PIN,
+      .mosi_pin       = MAX3421_MOSI_PIN,
+      .miso_pin       = MAX3421_MISO_PIN,
       .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
       .ss_active_high = false,
       .irq_priority   = 3,
@@ -233,8 +233,8 @@ void board_init(void) {
   nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
-  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
-  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
+  nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
+  nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
 #endif
 
 }
@@ -317,7 +317,7 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
 //--------------------------------------------------------------------+
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
-void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
   // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
@@ -331,7 +331,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
-  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
+  nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index 3441d03e9..fe2a867a4 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -44,12 +44,12 @@
 #define UART_RX_PIN           22
 
 // SPI for USB host shield
-#define MAX3421E_SERCOM   SERCOM2
-#define MAX3421E_SCK_PIN  13
-#define MAX3421E_MOSI_PIN 12
-#define MAX3421E_MISO_PIN 14
-#define MAX3421E_CS_PIN   18 // D10
-#define MAX3241E_INTR_PIN 20 // D9
+#define MAX3421_SERCOM   2  // SERCOM2
+#define MAX3421_SCK_PIN  13
+#define MAX3421_MOSI_PIN 12
+#define MAX3421_MISO_PIN 14
+#define MAX3421_CS_PIN   18 // D10
+#define MAX3421_INTR_PIN 20 // D9
 
 
 #ifdef __cplusplus
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 51cfd19ba..34dd93cef 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -73,58 +73,14 @@ void USB_3_Handler(void) {
 }
 
 //--------------------------------------------------------------------+
-//
+// Implementation
 //--------------------------------------------------------------------+
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-void max3421_init(void)
-{
-  //------------- SPI Init -------------//
-
-  // Enable the APB clock for SERCOM2
-  MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
-
-  // Configure GCLK for SERCOM2, initClockNVIC()
-  GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-  GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+static void max3421_init(void);
 
-  // Disable the SPI module
-  SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
-
-  // Reset the SPI module
-  SERCOM2->SPI.CTRLA.bit.SWRST = 1;
-  while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
+//#define
 
-  // Set up SPI in master mode, MSB first, SPI mode 0
-  uint8_t const mosi_pad = 0;
-  uint8_t const miso_pad = 2;
-  SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
-
-  SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
-  while( SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1 );
-
-  // Set the baud rate
-  uint32_t baudrate = 4000000u;
-  SERCOM2->SPI.BAUD.reg = (uint8_t)(SystemCoreClock / (2 * baudrate) - 1); // Replace 1000000 with your desired baud rate
-
-  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
-  // 2 function C: PIO_SERCOM
-  gpio_set_pin_direction(MAX3421E_SCK_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_pull_mode(MAX3421E_SCK_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421E_SCK_PIN, 2);
-
-  gpio_set_pin_direction(MAX3421E_MOSI_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_pull_mode(MAX3421E_MOSI_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421E_MOSI_PIN, 2);
-
-  gpio_set_pin_direction(MAX3421E_MISO_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(MAX3421E_MISO_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421E_MISO_PIN, 2);
-
-  // Enable the SPI module
-  SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
-  while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
-}
 #endif
 
 void board_init(void) {
@@ -180,46 +136,7 @@ void board_init(void) {
   gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-  // CS pin
-  gpio_set_pin_direction(MAX3421E_CS_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(MAX3421E_CS_PIN, 1);
-
-  // SPI
   max3421_init();
-
-  // INT pin with external interrupt
-  gpio_set_pin_direction(MAX3241E_INTR_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(MAX3241E_INTR_PIN, GPIO_PULL_UP);
-
-  // Enable the APB clock for EIC (External Interrupt Controller)
-  MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
-
-  // Configure GCLK for EIC
-  GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-
-  // Configure PA20 as an input
-  PORT->Group[0].DIRCLR.reg = PORT_PA20;
-  PORT->Group[0].PINCFG[20].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN;
-  PORT->Group[0].OUTSET.reg = PORT_PA20;  // Enable pull-up
-
-  // Configure PA20 to use EIC
-  PORT->Group[0].PMUX[10].bit.PMUXE = MUX_PA20A_EIC_EXTINT4;
-  PORT->Group[0].PINCFG[20].bit.PMUXEN = 1;
-
-  // Disable EIC
-  EIC->CTRLA.bit.ENABLE = 0;
-  while (EIC->SYNCBUSY.bit.ENABLE);
-
-  // Configure EXTINT4 (PA20) to trigger on falling edge
-  EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
-
-  // Enable EXTINT4
-  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
-
-  // Enable EIC
-  EIC->CTRLA.bit.ENABLE = 1;
-  while (EIC->SYNCBUSY.bit.ENABLE);
-
 #endif
 }
 
@@ -264,8 +181,91 @@ uint32_t board_millis(void) {
 //--------------------------------------------------------------------+
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
-void EIC_4_Handler(void)
-{
+static void max3421_init(void) {
+  // CS pin
+  gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
+  //------------- SPI Init -------------//
+
+  // Enable the APB clock for SERCOM2
+  MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+
+  // Configure GCLK for SERCOM2, initClockNVIC()
+  GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Disable the SPI module
+  SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
+
+  // Reset the SPI module
+  SERCOM2->SPI.CTRLA.bit.SWRST = 1;
+  while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
+
+  // Set up SPI in master mode, MSB first, SPI mode 0
+  uint8_t const mosi_pad = 0;
+  uint8_t const miso_pad = 2;
+  SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
+
+  SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+  while (SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1);
+
+  // Set the baud rate
+  uint32_t baudrate = 4000000u;
+  SERCOM2->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) -
+                                     1); // Replace 1000000 with your desired baud rate
+
+  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
+  // 2 function C: PIO_SERCOM
+  gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_SCK_PIN, 2);
+
+  gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MOSI_PIN, 2);
+
+  gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MISO_PIN, 2);
+
+  // Enable the SPI module
+  SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
+  while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
+
+  //------------- External Interrupt -------------//
+
+  // INT pin with external interrupt
+  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+
+  // Enable the APB clock for EIC (External Interrupt Controller)
+  MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+
+  // Configure GCLK for EIC
+  GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Configure PA20 as an input with function A (external interrupt)
+  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(MAX3421_INTR_PIN, 0);
+
+  // Disable EIC
+  EIC->CTRLA.bit.ENABLE = 0;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+
+  // Configure EXTINT4 (PA20) to trigger on falling edge
+  EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
+
+  // Enable EXTINT4
+  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
+
+  // Enable EIC
+  EIC->CTRLA.bit.ENABLE = 1;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+}
+
+void EIC_4_Handler(void) {
   // Clear the interrupt flag
   EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << 4);
 
@@ -273,7 +273,7 @@ void EIC_4_Handler(void)
   tuh_int_handler(1);
 }
 
-void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
   if (enabled) {
@@ -285,7 +285,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
-  gpio_set_pin_level(MAX3421E_CS_PIN, active ? 0 : 1);
+  gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
@@ -299,7 +299,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
     // Write data to be transmitted
     uint8_t data = 0x00;
     if (count < tx_len) {
-       data = tx_buf[count];
+      data = tx_buf[count];
     }
 
     SERCOM2->SPI.DATA.reg = (uint32_t) data;
@@ -322,6 +322,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 
   return true;
 }
+
 #endif
 
 #endif
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 95cf5516e..238b518a0 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -212,7 +212,7 @@ static max3421_data_t _hcd_data;
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
-void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
+void tuh_max3421_int_api(uint8_t rhport, bool enabled);
 
 static void handle_connect_irq(uint8_t rhport, bool in_isr);
 static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
@@ -225,7 +225,7 @@ static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
   if (!in_isr) {
     (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-    tuh_max3421e_int_api(rhport, false);
+    tuh_max3421_int_api(rhport, false);
   }
 
   // assert CS
@@ -238,7 +238,7 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
 
   // mutex unlock and re-enable interrupt
   if (!in_isr) {
-    tuh_max3421e_int_api(rhport, true);
+    tuh_max3421_int_api(rhport, true);
     (void) osal_mutex_unlock(_hcd_data.spi_mutex);
   }
 }
@@ -411,7 +411,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
-  tuh_max3421e_int_api(rhport, false);
+  tuh_max3421_int_api(rhport, false);
   tuh_max3421_spi_cs_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
@@ -450,7 +450,7 @@ bool hcd_init(uint8_t rhport) {
   // Enable IRQ
   hien_write(rhport, DEFAULT_HIEN, false);
 
-  tuh_max3421e_int_api(rhport, true);
+  tuh_max3421_int_api(rhport, true);
 
   // Enable Interrupt pin
   reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
@@ -461,13 +461,13 @@ bool hcd_init(uint8_t rhport) {
 // Enable USB interrupt
 // Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, true);
+  tuh_max3421_int_api(rhport, true);
 }
 
 // Disable USB interrupt
 // Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, false);
+  tuh_max3421_int_api(rhport, false);
 }
 
 // Get frame number (1ms)
-- 
cgit v1.3.1


From 11fba8433474a0653047823a25a749183a7d1ac2 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Wed, 13 Sep 2023 21:29:04 +0000
Subject: Error handling on transfer

---
 src/class/hid/hid_device.c | 25 +++++++++++++++++++++----
 src/class/hid/hid_device.h |  4 ++++
 2 files changed, 25 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 5637ea6b4..8bedb6395 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -381,8 +381,6 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
 
 bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
-  (void) result;
-
   uint8_t instance = 0;
   hidd_interface_t * p_hid = _hidd_itf;
 
@@ -394,6 +392,25 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   }
   TU_ASSERT(instance < CFG_TUD_HID);
 
+  // Check if there was a problem
+  if (XFER_RESULT_SUCCESS != result)
+  {
+    // Inform application about the issue
+    if (tud_hid_report_issue_cb)
+    {
+      tud_hid_report_issue_cb(instance, ep_addr, result, xferred_bytes);
+    }
+
+    // Allow a new transfer to be received if issue happened on an OUT endpoint
+    if (ep_addr == p_hid->ep_out)
+    {
+      // Prepare the OUT endpoint to be able to receive a new transfer
+      TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)));
+    }
+
+    return true;
+  }
+
   // Sent report successfully
   if (ep_addr == p_hid->ep_in)
   {
@@ -402,10 +419,10 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
       tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t) xferred_bytes);
     }
   }
-  // Received report
+  // Received report successfully
   else if (ep_addr == p_hid->ep_out)
   {
-    tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_INVALID, p_hid->epout_buf, (uint16_t) xferred_bytes);
+    tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_OUTPUT, p_hid->epout_buf, (uint16_t) xferred_bytes);
     TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)));
   }
 
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 17b24def1..056727378 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -118,6 +118,8 @@ TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
 // Note: For composite reports, report[0] is report ID
 TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
 
+// Invoked when a transfer wasn't successful
+TU_ATTR_WEAK void tud_hid_report_issue_cb(uint8_t instance, uint8_t ep_addr, xfer_result_t result, uint16_t xferred_bytes);
 
 //--------------------------------------------------------------------+
 // Inline Functions
@@ -411,6 +413,8 @@ uint16_t hidd_open            (uint8_t rhport, tusb_desc_interface_t const * itf
 bool     hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 bool     hidd_xfer_cb         (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
 
+void test(void);
+
 #ifdef __cplusplus
  }
 #endif
-- 
cgit v1.3.1


From 81e63ed6d865d43b634ed6bf2d3df3ae29135913 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Wed, 13 Sep 2023 22:03:44 +0000
Subject: Fixing warning

---
 src/class/hid/hid_device.c | 2 +-
 src/class/hid/hid_device.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 8bedb6395..564ad12f6 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -398,7 +398,7 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
     // Inform application about the issue
     if (tud_hid_report_issue_cb)
     {
-      tud_hid_report_issue_cb(instance, ep_addr, result, xferred_bytes);
+      tud_hid_report_issue_cb(instance, ep_addr, result, (uint16_t) xferred_bytes);
     }
 
     // Allow a new transfer to be received if issue happened on an OUT endpoint
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 056727378..a934753eb 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -119,7 +119,7 @@ TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
 TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
 
 // Invoked when a transfer wasn't successful
-TU_ATTR_WEAK void tud_hid_report_issue_cb(uint8_t instance, uint8_t ep_addr, xfer_result_t result, uint16_t xferred_bytes);
+TU_ATTR_WEAK void tud_hid_report_issue_cb(uint8_t instance, uint8_t ep_addr, xfer_result_t result, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Inline Functions
-- 
cgit v1.3.1


From 81cd9951080181234f20d81c831ca0595d499577 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 18 Sep 2023 22:15:31 +0700
Subject: add default CFG_TUH_MAX3421 = 0, default spi speed for samd21/samd51
 to 12Mhz

---
 hw/bsp/samd21/family.c                    |  3 ++-
 hw/bsp/samd51/family.c                    | 11 +++++++++--
 src/portable/analog/max3421/hcd_max3421.c |  2 +-
 src/tusb_option.h                         | 22 +++++++++++++---------
 4 files changed, 25 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index cfe66b8dc..395155548 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -269,7 +269,8 @@ uint32_t board_millis(void) {
 
 static void max3421_init(void) {
   //------------- SPI Init -------------//
-  uint32_t const baudrate = 4000000u;
+  // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
+  uint32_t const baudrate = 12000000u;
 
   // Enable the APB clock for SERCOM
   PM->APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID);
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 2cf00c7af..c1b914a02 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -183,7 +183,9 @@ uint32_t board_millis(void) {
 
 static void max3421_init(void) {
   //------------- SPI Init -------------//
-  uint32_t const baudrate = 4000000u;
+
+  // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
+  uint32_t const baudrate = 12000000u;
 
   struct {
     volatile uint32_t *mck_apb;
@@ -229,7 +231,12 @@ static void max3421_init(void) {
   while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
 
   // Set the baud rate
-  sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1);
+  uint8_t baud_reg = (uint8_t) (SystemCoreClock / (2 * baudrate));
+  if (baud_reg) {
+    baud_reg--;
+  }
+
+  sercom->SPI.BAUD.reg = baud_reg;
 
   // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
   gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 238b518a0..f3f76fd58 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -263,7 +263,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0);
+  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
   _hcd_data.hirq = hirq;
   tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c72117850..a41f5a07e 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -424,11 +424,11 @@
 //------------- CLASS -------------//
 
 #ifndef CFG_TUH_HUB
-#define CFG_TUH_HUB    0
+  #define CFG_TUH_HUB    0
 #endif
 
 #ifndef CFG_TUH_CDC
-#define CFG_TUH_CDC    0
+  #define CFG_TUH_CDC    0
 #endif
 
 #ifndef CFG_TUH_CDC_FTDI
@@ -442,34 +442,38 @@
 #endif
 
 #ifndef CFG_TUH_HID
-#define CFG_TUH_HID    0
+  #define CFG_TUH_HID    0
 #endif
 
 #ifndef CFG_TUH_MIDI
-#define CFG_TUH_MIDI   0
+  #define CFG_TUH_MIDI   0
 #endif
 
 #ifndef CFG_TUH_MSC
-#define CFG_TUH_MSC    0
+  #define CFG_TUH_MSC    0
 #endif
 
 #ifndef CFG_TUH_VENDOR
-#define CFG_TUH_VENDOR 0
+  #define CFG_TUH_VENDOR 0
 #endif
 
 #ifndef CFG_TUH_API_EDPT_XFER
-#define CFG_TUH_API_EDPT_XFER 0
+  #define CFG_TUH_API_EDPT_XFER 0
 #endif
 
 // Enable PIO-USB software host controller
 #ifndef CFG_TUH_RPI_PIO_USB
-#define CFG_TUH_RPI_PIO_USB 0
+  #define CFG_TUH_RPI_PIO_USB 0
 #endif
 
 #ifndef CFG_TUD_RPI_PIO_USB
-#define CFG_TUD_RPI_PIO_USB 0
+  #define CFG_TUD_RPI_PIO_USB 0
 #endif
 
+// MAX3421 Host controller option
+#ifndef CFG_TUH_MAX3421
+  #define CFG_TUH_MAX3421  0
+#endif
 
 //--------------------------------------------------------------------+
 // TypeC Options (Default)
-- 
cgit v1.3.1


From 9d0251f7a6751a0d998da4fad81a35a043608275 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 19 Sep 2023 15:42:52 +0200
Subject: Fix UAC interleaved copy.

---
 src/class/audio/audio_device.c | 113 +++++++++++++++++++----------------------
 1 file changed, 51 insertions(+), 62 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 1a7ce7870..0e4220f4f 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -631,68 +631,59 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 // Decoding according to 2.3.1.5 Audio Streams
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used)
+static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, uint8_t * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used)
 {
 
-  // This function is an optimized version of
-  //  while((uint8_t *)dst < dst_end)
-  //  {
-  //    memcpy(dst, src, nBytesToCopy);
-  //    dst = (uint8_t *)dst + nBytesToCopy;
-  //    src += nBytesToCopy * n_ff_used;
-  //  }
-
-  // Optimize for fast half word copies
-  typedef struct{
-    uint16_t val;
-  } __attribute((__packed__)) unaligned_uint16_t;
-
-  // Optimize for fast word copies
-  typedef struct{
-    uint32_t val;
-  } __attribute((__packed__)) unaligned_uint32_t;
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
 
   switch (nBytesToCopy)
   {
     case 1:
       while((uint8_t *)dst < dst_end)
       {
-        *(uint8_t *)dst++ = *src;
-        src += n_ff_used;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        src += 2 * (n_ff_used - 1);
       }
       break;
 
     case 2:
       while((uint8_t *)dst < dst_end)
       {
-        *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src;
-        dst += 2;
-        src += 2 * n_ff_used;
+        *(uint32_t*)dst = *(uint32_t*)src;
+        src += 4;
+        dst += 4;
+        src += 4 * (n_ff_used - 1);
       }
       break;
 
     case 3:
       while((uint8_t *)dst < dst_end)
       {
-        //        memcpy(dst, src, 3);
-        //        dst = (uint8_t *)dst + 3;
-        //        src += 3 * n_ff_used;
-
-        // TODO: Is there a faster way to copy 3 bytes?
-        *(uint8_t *)dst++ = *src++;
-        *(uint8_t *)dst++ = *src++;
-        *(uint8_t *)dst++ = *src++;
-
-        src += 3 * (n_ff_used - 1);
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        src += 6 * (n_ff_used - 1);
       }
       break;
 
     case 4:
       while((uint8_t *)dst < dst_end)
       {
-        *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
+        src += 4;
+        dst += 4;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
+        src += 4;
         dst += 4;
-        src += 4 * n_ff_used;
+        src += 8 * (n_ff_used - 1);
       }
       break;
   }
@@ -946,57 +937,55 @@ range [-1, +1)
 // Helper function
 static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used)
 {
-  // Optimize for fast half word copies
-  typedef struct{
-    uint16_t val;
-  } __attribute((__packed__)) unaligned_uint16_t;
-
-  // Optimize for fast word copies
-  typedef struct{
-    uint32_t val;
-  } __attribute((__packed__)) unaligned_uint32_t;
-
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
   switch (nBytesToCopy)
   {
     case 1:
       while(src < src_end)
       {
-        *dst = *src++;
-        dst += n_ff_used;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        dst += 2 * (n_ff_used - 1);
       }
       break;
 
     case 2:
       while(src < src_end)
       {
-        *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src;
-        src += 2;
-        dst += 2 * n_ff_used;
+        *(uint32_t*)dst = *(uint32_t*)src;
+        src += 4;
+        dst += 4;
+        dst += 4 * (n_ff_used - 1);
       }
       break;
 
     case 3:
       while(src < src_end)
       {
-        //        memcpy(dst, src, 3);
-        //        src = (uint8_t *)src + 3;
-        //        dst += 3 * n_ff_used;
-
-        // TODO: Is there a faster way to copy 3 bytes?
-        *dst++ = *src++;
-        *dst++ = *src++;
-        *dst++ = *src++;
-
-        dst += 3 * (n_ff_used - 1);
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        dst += 6 * (n_ff_used - 1);
       }
       break;
 
     case 4:
       while(src < src_end)
       {
-        *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
+        src += 4;
+        dst += 4;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
         src += 4;
-        dst += 4 * n_ff_used;
+        dst += 4;
+        dst += 8 * (n_ff_used - 1);
       }
       break;
   }
-- 
cgit v1.3.1


From 6be7f354c26e09a87d1b856b0e237ff82be5963f Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 19 Sep 2023 16:32:49 +0200
Subject: Fix cast-align.

---
 src/class/audio/audio_device.c | 196 +++++++++++++++++++----------------------
 1 file changed, 90 insertions(+), 106 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 0e4220f4f..46fd6dfa9 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -631,64 +631,55 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 // Decoding according to 2.3.1.5 Audio Streams
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, uint8_t * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used)
 {
-
   // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
-
-  switch (nBytesToCopy)
+  uint16_t * dst16 = dst;
+  uint16_t * src16 = src;
+  const uint16_t * dst_end16 = dst_end;
+  uint32_t * dst32 = dst;
+  uint32_t * src32 = src;
+  const uint32_t * dst_end32 = dst_end;
+
+  if (nBytesToCopy == 1)
   {
-    case 1:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        src += 2 * (n_ff_used - 1);
-      }
-      break;
-
-    case 2:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint32_t*)dst = *(uint32_t*)src;
-        src += 4;
-        dst += 4;
-        src += 4 * (n_ff_used - 1);
-      }
-      break;
-
-    case 3:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        src += 6 * (n_ff_used - 1);
-      }
-      break;
-
-    case 4:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        src += 8 * (n_ff_used - 1);
-      }
-      break;
+    while(dst16 < dst_end16)
+    {
+      *dst16++ = *src16++;
+      src16 += n_ff_used - 1;
+    }
+    return src16;
+  }
+  else if (nBytesToCopy == 2)
+  {
+    while(dst32 < dst_end32)
+    {
+      *dst32++ = *src32++;
+      src32 += n_ff_used - 1;
+    }
+    return src32;
+  }
+  else if (nBytesToCopy == 3)
+  {
+    while(dst16 < dst_end16)
+    {
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      src16 += 3 * (n_ff_used - 1);
+    }
+    return src16;
+  }
+  else // nBytesToCopy == 4
+  {
+    while(dst32 < dst_end32)
+    {
+      *dst32++ = *src32++;
+      *dst32++ = *src32++;
+      src32 += 2 * (n_ff_used - 1);
+    }
+    return src32;
   }
-
-  return src;
 }
 
 static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received)
@@ -935,62 +926,55 @@ range [-1, +1)
  * */
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, void * src, const void * src_end, void * dst, uint8_t const n_ff_used)
 {
   // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
-  switch (nBytesToCopy)
+  uint16_t * dst16 = dst;
+  uint16_t * src16 = src;
+  const uint16_t * src_end16 = src_end;
+  uint32_t * dst32 = dst;
+  uint32_t * src32 = src;
+  const uint32_t * src_end32 = src_end;
+
+  if (nBytesToCopy == 1)
   {
-    case 1:
-      while(src < src_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        dst += 2 * (n_ff_used - 1);
-      }
-      break;
-
-    case 2:
-      while(src < src_end)
-      {
-        *(uint32_t*)dst = *(uint32_t*)src;
-        src += 4;
-        dst += 4;
-        dst += 4 * (n_ff_used - 1);
-      }
-      break;
-
-    case 3:
-      while(src < src_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        dst += 6 * (n_ff_used - 1);
-      }
-      break;
-
-    case 4:
-      while(src < src_end)
-      {
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        dst += 8 * (n_ff_used - 1);
-      }
-      break;
+    while(src16 < src_end16)
+    {
+      *dst16++ = *src16++;
+      dst16 += n_ff_used - 1;
+    }
+    return dst16;
+  }
+  else if (nBytesToCopy == 2)
+  {
+    while(src32 < src_end32)
+    {
+      *dst32++ = *src32++;
+      dst32 += n_ff_used - 1;
+    }
+    return dst32;
+  }
+  else if (nBytesToCopy == 3)
+  {
+    while(src16 < src_end16)
+    {
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      dst16 += 3 * (n_ff_used - 1);
+    }
+    return dst16;
+  }
+  else // nBytesToCopy == 4
+  {
+    while(src32 < src_end32)
+    {
+      *dst32++ = *src32++;
+      *dst32++ = *src32++;
+      dst32 += 2 * (n_ff_used - 1);
+    }
+    return dst32;
   }
-
-  return dst;
 }
 
 static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audio)
-- 
cgit v1.3.1


From a7c136c03f0c4a057f8b49c10ed9cddcecf52879 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Sep 2023 16:53:11 +0700
Subject: adding host/cdc_msc_hid_freertos example

---
 .idea/cmake.xml                                    |  19 +--
 examples/device/cdc_msc_freertos/Makefile          |   2 +-
 examples/device/cdc_msc_freertos/src/main.c        |  70 ++++-----
 examples/host/bare_api/CMakeLists.txt              |   5 +
 examples/host/cdc_msc_hid/CMakeLists.txt           |   5 +
 examples/host/cdc_msc_hid_freertos/CMakeLists.txt  |  36 +++++
 .../host/cdc_msc_hid_freertos/src/CMakeLists.txt   |   4 +
 examples/host/cdc_msc_hid_freertos/src/main.c      | 170 +++++++++++++++++++++
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    | 133 ++++++++++++++++
 examples/host/hid_controller/CMakeLists.txt        |   5 +
 examples/host/msc_file_explorer/CMakeLists.txt     |   5 +
 examples/make.mk                                   |   3 -
 .../boards/adafruit_metro_esp32s2/board.h          |   8 +
 hw/bsp/espressif/boards/espressif_kaluga_1/board.h |   8 +
 .../boards/espressif_s2_devkitc/board.cmake        |   2 +
 .../espressif/boards/espressif_s2_devkitc/board.h  |  45 ++++++
 hw/bsp/espressif/boards/family.c                   | 130 +++++++++++++---
 .../components/tinyusb_src/CMakeLists.txt          |  79 ++++++----
 src/host/usbh.c                                    |   2 +-
 src/portable/analog/max3421/hcd_max3421.c          |   2 +-
 20 files changed, 622 insertions(+), 111 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid_freertos/CMakeLists.txt
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/main.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/tusb_config.h
 create mode 100644 hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
 create mode 100644 hw/bsp/espressif/boards/espressif_s2_devkitc/board.h

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 89ec1066c..747f0fb58 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,23 +2,24 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
+      <configuration PROFILE_NAME="esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_saola_1">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
-            <env name="ESPPORT" value="/dev/ttyUSB0" />
-            <env name="IDF_PATH" value="$PROJECT_DIR$/../esp-idf" />
-            <env name="PATH" value="$PROJECT_DIR$/../esp-idf/components/esptool_py/esptool:/home/hathach/code/esp-idf/components/espcoredump:/home/hathach/code/esp-idf/components/partition_table:/home/hathach/code/esp-idf/components/app_update:/home/hathach/.espressif/tools/xtensa-esp-elf-gdb/11.2_20220823/xtensa-esp-elf-gdb/bin:/home/hathach/.espressif/tools/riscv32-esp-elf-gdb/11.2_20220823/riscv32-esp-elf-gdb/bin:/home/hathach/.espressif/tools/xtensa-esp32-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s2-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s2-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s3-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s3-elf/bin:/home/hathach/.espressif/tools/riscv32-esp-elf/esp-2021r2-patch5-8.4.0/riscv32-esp-elf/bin:/home/hathach/.espressif/tools/esp32ulp-elf/2.35_20220830/esp32ulp-elf/bin:/home/hathach/.espressif/tools/openocd-esp32/v0.11.0-esp32-20221026/openocd-esp32/bin:/home/hathach/.espressif/python_env/idf4.4_py3.10_env/bin:/home/hathach/code/esp-idf/tools:/home/hathach/app/riscv-openocd-wch/src:/home/hathach/app/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi/bin:/home/hathach/.local/bin:/home/hathach/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/opt/SEGGER/JLink:/home/hathach/app/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/10.2.0-1.2.1/.content/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/openocd/*/.content/bin:/home/hathach/ti/msp430-gcc/bin:/home/hathach/ti/MSPFlasher_1.3.20:/home/hathach/ti/uniflash_7.0.0:/home/hathach/app/gcc_8.3.0.202102_gnurx-elf/bin:/home/hathach/app/RFP_CLI_Linux_V31101_x64/linux-x64:/home/hathach/app/fomu-toolchain-linux_x86_64-v1.5.5/bin:/home/hathach/app/nuclei_riscv_newlibc_prebuilt_linux64_2020.08/gcc/bin:/home/hathach/app/riscv32-embecosm-ubuntu2004-gcc11.1.0/bin:/home/hathach/app/cov-analysis-linux64-2019.03/bin:/opt/iarsystems/bxarm/arm/bin:/home/hathach/.local/bin" />
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
+      <configuration PROFILE_NAME="kaluga" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_kaluga_1 -DMAX3421_HOST=1 -DLOG=2">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="esp32s3" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
-            <env name="ESPPORT" value="/dev/ttyUSB0" />
-            <env name="IDF_PATH" value="$PROJECT_DIR$/../esp-idf" />
-            <env name="PATH" value="$PROJECT_DIR$/../esp-idf/components/esptool_py/esptool:/home/hathach/code/esp-idf/components/espcoredump:/home/hathach/code/esp-idf/components/partition_table:/home/hathach/code/esp-idf/components/app_update:/home/hathach/.espressif/tools/xtensa-esp-elf-gdb/11.2_20220823/xtensa-esp-elf-gdb/bin:/home/hathach/.espressif/tools/riscv32-esp-elf-gdb/11.2_20220823/riscv32-esp-elf-gdb/bin:/home/hathach/.espressif/tools/xtensa-esp32-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s2-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s2-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s3-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s3-elf/bin:/home/hathach/.espressif/tools/riscv32-esp-elf/esp-2021r2-patch5-8.4.0/riscv32-esp-elf/bin:/home/hathach/.espressif/tools/esp32ulp-elf/2.35_20220830/esp32ulp-elf/bin:/home/hathach/.espressif/tools/openocd-esp32/v0.11.0-esp32-20221026/openocd-esp32/bin:/home/hathach/.espressif/python_env/idf4.4_py3.10_env/bin:/home/hathach/code/esp-idf/tools:/home/hathach/app/riscv-openocd-wch/src:/home/hathach/app/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi/bin:/home/hathach/.local/bin:/home/hathach/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/opt/SEGGER/JLink:/home/hathach/app/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/10.2.0-1.2.1/.content/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/openocd/*/.content/bin:/home/hathach/ti/msp430-gcc/bin:/home/hathach/ti/MSPFlasher_1.3.20:/home/hathach/ti/uniflash_7.0.0:/home/hathach/app/gcc_8.3.0.202102_gnurx-elf/bin:/home/hathach/app/RFP_CLI_Linux_V31101_x64/linux-x64:/home/hathach/app/fomu-toolchain-linux_x86_64-v1.5.5/bin:/home/hathach/app/nuclei_riscv_newlibc_prebuilt_linux64_2020.08/gcc/bin:/home/hathach/app/riscv32-embecosm-ubuntu2004-gcc11.1.0/bin:/home/hathach/app/cov-analysis-linux64-2019.03/bin:/opt/iarsystems/bxarm/arm/bin:/home/hathach/.local/bin" />
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
@@ -53,7 +54,7 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
     </configurations>
   </component>
diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 0bee668b7..3ac62a79c 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -10,7 +10,7 @@ INC += \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_PORTABLE_SRC)
+	$(TOP)/$(FREERTOS_PORTABLE_SRC) \
 
 # Example source
 EXAMPLE_SOURCE = \
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0b115a595..1dadc4513 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -41,6 +41,7 @@
 
   #define USBD_STACK_SIZE     4096
 #else
+
   #include "FreeRTOS.h"
   #include "semphr.h"
   #include "queue.h"
@@ -54,7 +55,7 @@
 #define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
 
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
+// MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
 /* Blink pattern
@@ -62,7 +63,7 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -81,16 +82,15 @@ StaticTask_t cdc_taskdef;
 
 TimerHandle_t blinky_tm;
 
-void led_blinky_cb(TimerHandle_t xTimer);
-void usb_device_task(void* param);
-void cdc_task(void* params);
+static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_device_task(void *param);
+void cdc_task(void *params);
 
 //--------------------------------------------------------------------+
 // Main
 //--------------------------------------------------------------------+
 
-int main(void)
-{
+int main(void) {
   board_init();
 
 #if configSUPPORT_STATIC_ALLOCATION
@@ -104,8 +104,8 @@ int main(void)
   xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 #else
   blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
-  xTaskCreate( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
-  xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
 #endif
 
   xTimerStart(blinky_tm, 0);
@@ -119,16 +119,14 @@ int main(void)
 }
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-void app_main(void)
-{
+void app_main(void) {
   main();
 }
 #endif
 
 // USB Device Driver task
 // This top level thread process all usb events and invoke callbacks
-void usb_device_task(void* param)
-{
+static void usb_device_task(void *param) {
   (void) param;
 
   // init device stack on configured roothub port
@@ -141,8 +139,7 @@ void usb_device_task(void* param)
   }
 
   // RTOS forever loop
-  while (1)
-  {
+  while (1) {
     // put this thread to waiting state until there is new events
     tud_task();
 
@@ -156,35 +153,28 @@ void usb_device_task(void* param)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  if (tud_mounted())
-  {
+void tud_resume_cb(void) {
+  if (tud_mounted()) {
     xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
-  }
-  else
-  {
+  } else {
     xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
   }
 }
@@ -192,20 +182,17 @@ void tud_resume_cb(void)
 //--------------------------------------------------------------------+
 // USB CDC
 //--------------------------------------------------------------------+
-void cdc_task(void* params)
-{
+void cdc_task(void *params) {
   (void) params;
 
   // RTOS forever loop
-  while ( 1 )
-  {
+  while (1) {
     // connected() check for DTR bit
     // Most but not all terminal client set this when making connection
     // if ( tud_cdc_connected() )
     {
       // There are data available
-      while ( tud_cdc_available() )
-      {
+      while (tud_cdc_available()) {
         uint8_t buf[64];
 
         // read and echo back
@@ -228,32 +215,27 @@ void cdc_task(void* params)
 }
 
 // Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
   (void) itf;
   (void) rts;
 
   // TODO set some indicator
-  if ( dtr )
-  {
+  if (dtr) {
     // Terminal connected
-  }else
-  {
+  } else {
     // Terminal disconnected
   }
 }
 
 // Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
+void tud_cdc_rx_cb(uint8_t itf) {
   (void) itf;
 }
 
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinky_cb(TimerHandle_t xTimer)
-{
+static void led_blinky_cb(TimerHandle_t xTimer) {
   (void) xTimer;
   static bool led_state = false;
 
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 05398b079..76182d6fa 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index ad5751705..a7c372a34 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/host/cdc_msc_hid_freertos/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
new file mode 100644
index 000000000..2e95a18e0
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
@@ -0,0 +1,36 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} freertos)
diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
new file mode 100644
index 000000000..dd7ec8e58
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "hid_app.c" "main.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
new file mode 100644
index 000000000..e2ddd52eb
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -0,0 +1,170 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+
+  #define USBH_STACK_SIZE     4096
+#else
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+
+  // Increase stack size when debug log is enabled
+  #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+// static timer & task
+#if configSUPPORT_STATIC_ALLOCATION
+StaticTimer_t blinky_tmdef;
+
+StackType_t  usb_host_stack[USBH_STACK_SIZE];
+StaticTask_t usb_host_taskdef;
+
+//StackType_t  cdc_stack[CDC_STACK_SZIE];
+//StaticTask_t cdc_taskdef;
+#endif
+
+
+TimerHandle_t blinky_tm;
+
+static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_host_task(void* param);
+
+extern void cdc_app_task(void);
+extern void hid_app_task(void);
+
+/*------------- MAIN -------------*/
+int main(void) {
+  board_init();
+
+  printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n");
+
+#if configSUPPORT_STATIC_ALLOCATION
+  // soft timer for blinky
+  blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
+
+  // Create a task for tinyusb device stack
+  xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef);
+
+  // Create CDC task
+  //xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+#else
+  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate( usb_device_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+  //xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+#endif
+
+  xTimerStart(blinky_tm, 0);
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  vTaskStartScheduler();
+#endif
+
+  return 0;
+}
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+void app_main(void) {
+  main();
+}
+#endif
+
+// USB Host task
+// This top level thread process all usb events and invoke callbacks
+static void usb_host_task(void *param) {
+  (void) param;
+
+  // init host stack on configured roothub port
+  tuh_init(BOARD_TUH_RHPORT);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tuh_task();
+
+    // following code only run if tuh_task() process at least 1 event
+  }
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+void tuh_mount_cb(uint8_t dev_addr) {
+  // application set-up
+  printf("A device with address %d is mounted\r\n", dev_addr);
+}
+
+void tuh_umount_cb(uint8_t dev_addr) {
+  // application tear-down
+  printf("A device with address %d is unmounted \r\n", dev_addr);
+}
+
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+static void led_blinky_cb(TimerHandle_t xTimer) {
+  (void) xTimer;
+  static bool led_state = false;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
new file mode 100644
index 000000000..1bed9a9b3
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -0,0 +1,133 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+  #define CFG_TUH_RPI_PIO_USB   0
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 1 // number of supported hubs
+#define CFG_TUH_CDC                 1 // CDC ACM
+#define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_MSC                 1
+#define CFG_TUH_VENDOR              0
+
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
+
+//------------- HID -------------//
+#define CFG_TUH_HID_EPIN_BUFSIZE    64
+#define CFG_TUH_HID_EPOUT_BUFSIZE   64
+
+//------------- CDC -------------//
+
+// Set Line Control state on enumeration/mounted:
+// DTR ( bit 0), RTS (bit 1)
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+// bit rate = 115200, 1 stop bit, no parity, 8 bit data width
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 3fb630aaa..c1b500dd8 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 1868b632e..1a57c7466 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/make.mk b/examples/make.mk
index 8fe4a3486..448d7883d 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -26,9 +26,6 @@ ifeq '$(findstring ;,$(PATH))' ';'
 CMDEXE := 1
 
 # makefile shell commands should use syntax for DOS CMD, not unix sh
-# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
-# We can't just use sh, because while sh and/or bash shell may be available,
-# many Windows environments won't have utilities like realpath used below, so...
 # Force DOS command shell on Windows.
 SHELL := cmd.exe
 endif
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
index 2ec80ef47..44ff11aa0 100644
--- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
@@ -36,6 +36,14 @@
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
index 0acb9c439..613e6ae0c 100644
--- a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
@@ -37,6 +37,14 @@
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
new file mode 100644
index 000000000..e068efef9
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
@@ -0,0 +1,45 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Note: On the production version (v1.2) WS2812 is connected to GPIO 18,
+// however earlier revision v1.1 WS2812 is connected to GPIO 17
+#define NEOPIXEL_PIN          18
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 8f857fb71..250b7001e 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -45,16 +45,19 @@
 static led_strip_t *strip;
 #endif
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+#include "driver/spi_master.h"
+static void max3421_init(void);
+#endif
 
 static void configure_pins(usb_hal_context_t *usb);
 
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
+//--------------------------------------------------------------------+
+// Implementation
+//--------------------------------------------------------------------+
 
+// Initialize on-board peripherals : led, button, uart and USB
+void board_init(void) {
 #ifdef NEOPIXEL_PIN
   #ifdef NEOPIXEL_POWER_PIN
   gpio_reset_pin(NEOPIXEL_POWER_PIN);
@@ -79,23 +82,27 @@ void board_init(void)
   gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
   gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
 
+#if CFG_TUD_ENABLED
   // USB Controller Hal init
   periph_module_reset(PERIPH_USB_MODULE);
   periph_module_enable(PERIPH_USB_MODULE);
 
   usb_hal_context_t hal = {
-    .use_external_phy = false // use built-in PHY
+      .use_external_phy = false // use built-in PHY
   };
   usb_hal_init(&hal);
   configure_pins(&hal);
+#endif
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+  max3421_init();
+#endif
 }
 
-static void configure_pins(usb_hal_context_t *usb)
-{
+static void configure_pins(usb_hal_context_t *usb) {
   /* usb_periph_iopins currently configures USB_OTG as USB Device.
    * Introduce additional parameters in usb_hal_context_t when adding support
-   * for USB Host.
-   */
+   * for USB Host. */
   for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
     if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
       esp_rom_gpio_pad_select_gpio(iopin->pin);
@@ -115,6 +122,7 @@ static void configure_pins(usb_hal_context_t *usb)
       esp_rom_gpio_pad_unhold(iopin->pin);
     }
   }
+
   if (!usb->use_external_phy) {
     gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
     gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
@@ -122,8 +130,7 @@ static void configure_pins(usb_hal_context_t *usb)
 }
 
 // Turn LED on or off
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
 #ifdef NEOPIXEL_PIN
   strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
   strip->refresh(strip, 100);
@@ -132,21 +139,102 @@ void board_led_write(bool state)
 
 // Get the current state of button
 // a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
 }
 
 // Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
 // Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+static spi_device_handle_t max3421_spi;
+
+static void IRAM_ATTR max3421_isr_handler(void* arg)
+{
+  (void) arg;
+  //uint32_t gpio_num = (uint32_t) arg;
+  //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL);
+  tuh_int_handler(1);
+}
+
+static void max3421_init(void) {
+  // CS pin
+  gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT);
+  gpio_set_level(MAX3421_CS_PIN, 1);
+
+  // SPI
+  spi_bus_config_t buscfg={
+      .miso_io_num = MAX3421_MISO_PIN,
+      .mosi_io_num = MAX3421_MOSI_PIN,
+      .sclk_io_num = MAX3421_SCK_PIN,
+      .quadwp_io_num = -1,
+      .quadhd_io_num = -1,
+      .data4_io_num = -1,
+      .data5_io_num = -1,
+      .data6_io_num = -1,
+      .data7_io_num = -1,
+      .max_transfer_sz = 128
+  };
+  ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) );
+
+  spi_device_interface_config_t max3421_cfg = {
+      .command_bits = 8,
+      .mode = 0,
+      .clock_speed_hz = 4000000, // 26000000
+      .spics_io_num = -1, // manual control CS
+      .queue_size = 1
+  };
+  ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) );
+
+  // Interrupt pin
+//  gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
+//  gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
+//
+//  gpio_install_isr_service(ESP_INTR_FLAG_EDGE);
+//  gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
+}
+
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+  if (enabled) {
+    gpio_intr_enable(MAX3421_INTR_PIN);
+  } else {
+    gpio_intr_disable(MAX3421_INTR_PIN);
+  }
+}
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+  (void) rhport;
+
+  spi_transaction_t xact = {
+      .length = tx_len,
+      .rxlength = rx_len,
+      .tx_buffer = tx_buf,
+      .rx_buffer = rx_buf
+  };
+
+  ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact));
+  return true;
+}
+
+#endif
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index bf8e45be2..2a154a8ff 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -16,40 +16,57 @@ else()
   return()
 endif()
 
-list(APPEND compile_options
-    "-DCFG_TUSB_MCU=${tusb_mcu}"
-    "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-    #"-DCFG_TUSB_DEBUG=1"
-    )
+list(APPEND compile_definitions
+  CFG_TUSB_MCU=${tusb_mcu}
+  CFG_TUSB_OS=OPT_OS_FREERTOS
+  )
 
-idf_component_get_property(freertos_component_dir freertos COMPONENT_DIR)
+list(APPEND srcs
+  # common
+  ${tusb_src}/tusb.c
+  ${tusb_src}/common/tusb_fifo.c
+  # device
+  ${tusb_src}/device/usbd.c
+  ${tusb_src}/device/usbd_control.c
+  ${tusb_src}/class/audio/audio_device.c
+  ${tusb_src}/class/cdc/cdc_device.c
+  ${tusb_src}/class/dfu/dfu_device.c
+  ${tusb_src}/class/dfu/dfu_rt_device.c
+  ${tusb_src}/class/hid/hid_device.c
+  ${tusb_src}/class/midi/midi_device.c
+  ${tusb_src}/class/msc/msc_device.c
+  ${tusb_src}/class/net/ecm_rndis_device.c
+  ${tusb_src}/class/net/ncm_device.c
+  ${tusb_src}/class/usbtmc/usbtmc_device.c
+  ${tusb_src}/class/vendor/vendor_device.c
+  ${tusb_src}/class/video/video_device.c
+  ${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c
+  # host
+  ${tusb_src}/host/usbh.c
+  ${tusb_src}/host/hub.c
+  ${tusb_src}/class/cdc/cdc_host.c
+  ${tusb_src}/class/hid/hid_host.c
+  ${tusb_src}/class/msc/msc_host.c
+  ${tusb_src}/class/vendor/vendor_host.c
+  )
 
-list(APPEND includes_public
-    "${tusb_src}"
-    # The FreeRTOS API include convention in tinyusb is different from esp-idf
-    #"${freertos_component_dir}/include/freertos"
-    )
+# use max3421 as host controller
+if (MAX3421_HOST STREQUAL "1")
+  list(APPEND srcs ${tusb_src}/portable/analog/max3421/hcd_max3421.c)
+  list(APPEND compile_definitions CFG_TUH_MAX3421=1)
+endif ()
 
-list(APPEND srcs
-    "${tusb_src}/tusb.c"
-    "${tusb_src}/common/tusb_fifo.c"
-    "${tusb_src}/device/usbd.c"
-    "${tusb_src}/device/usbd_control.c"
-    "${tusb_src}/class/cdc/cdc_device.c"
-    "${tusb_src}/class/dfu/dfu_rt_device.c"
-    "${tusb_src}/class/hid/hid_device.c"
-    "${tusb_src}/class/midi/midi_device.c"
-    "${tusb_src}/class/msc/msc_device.c"
-    "${tusb_src}/class/net/ecm_rndis_device.c"
-    "${tusb_src}/class/net/ncm_device.c"
-    "${tusb_src}/class/usbtmc/usbtmc_device.c"
-    "${tusb_src}/class/vendor/vendor_device.c"
-    "${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c"
-    )
+if (DEFINED LOG)
+  list(APPEND compile_definitions CFG_TUSB_DEBUG=${LOG})
+  if (LOG STREQUAL "4")
+    # no inline for debug level 4
+    list(APPEND compile_definitions TU_ATTR_ALWAYS_INLINE=)
+  endif ()
+endif()
 
 idf_component_register(SRCS ${srcs}
-    INCLUDE_DIRS ${includes_public}
-    REQUIRES src
-    )
+  INCLUDE_DIRS ${tusb_src}
+  REQUIRES src
+  )
 
-target_compile_options(${COMPONENT_LIB} PUBLIC ${compile_options})
+target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e332f35cc..dc2831da3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -659,7 +659,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %u\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     TU_LOG1_BUF(request, 8);
     TU_LOG1("\r\n");
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index f3f76fd58..3f6747404 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -882,7 +882,7 @@ void hcd_int_handler(uint8_t rhport) {
     if ( hirq & HIRQ_RCVDAV_IRQ ) {
       uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
       max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
-      uint8_t xact_len;
+      uint8_t xact_len = 0;
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
       while ( hirq & HIRQ_RCVDAV_IRQ ) {
-- 
cgit v1.3.1


From f6ca86c3ddeaec18f52b15f1065a5c9eea210c00 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Sep 2023 19:09:36 +0700
Subject: tested cdc_msc_hid_freertos with samd51

add -Wno-error=format for espressif
wrap up cdc_msc_hid_freertos
---
 examples/host/cdc_msc_hid_freertos/Makefile        |  32 +++
 examples/host/cdc_msc_hid_freertos/only.txt        |  13 +
 .../host/cdc_msc_hid_freertos/src/CMakeLists.txt   |   4 +-
 examples/host/cdc_msc_hid_freertos/src/cdc_app.c   | 109 +++++++++
 .../host/cdc_msc_hid_freertos/src/freertos_hook.c  | 111 +++++++++
 examples/host/cdc_msc_hid_freertos/src/hid_app.c   | 263 +++++++++++++++++++++
 examples/host/cdc_msc_hid_freertos/src/main.c      |  22 +-
 examples/host/cdc_msc_hid_freertos/src/msc_app.c   |  67 ++++++
 hw/bsp/espressif/boards/CMakeLists.txt             |   2 +
 hw/bsp/espressif/boards/family.c                   |  39 +--
 .../components/tinyusb_src/CMakeLists.txt          |   1 +
 hw/bsp/nrf/family.c                                | 106 +++++----
 hw/bsp/samd21/family.c                             |   9 +-
 hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h      |   2 +-
 hw/bsp/samd51/family.c                             |   8 +-
 src/host/usbh.c                                    |   2 +-
 16 files changed, 703 insertions(+), 87 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid_freertos/Makefile
 create mode 100644 examples/host/cdc_msc_hid_freertos/only.txt
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/cdc_app.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/hid_app.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/msc_app.c

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile
new file mode 100644
index 000000000..67bb6da55
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/Makefile
@@ -0,0 +1,32 @@
+include ../../make.mk
+
+FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
+
+INC += \
+	src \
+	$(TOP)/hw \
+	$(TOP)/$(FREERTOS_SRC)/include \
+	$(TOP)/$(FREERTOS_PORTABLE_SRC) \
+
+# Example source
+EXAMPLE_SOURCE = \
+  src/cdc_app.c \
+  src/freertos_hook.c \
+  src/hid_app.c \
+  src/main.c \
+  src/msc_app.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# TinyUSB Host Stack source
+SRC_C += \
+	src/class/cdc/cdc_host.c \
+	src/class/hid/hid_host.c \
+	src/class/msc/msc_host.c \
+	src/host/hub.c \
+	src/host/usbh.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+
+include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt
new file mode 100644
index 000000000..3837ac8a2
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/only.txt
@@ -0,0 +1,13 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT1XXX
+mcu:MIMXRT10XX
+mcu:MIMXRT11XX
+mcu:RP2040
+mcu:MSP432E4
+mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
index dd7ec8e58..6f057c106 100644
--- a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
@@ -1,4 +1,6 @@
 # This file is for ESP-IDF only
-idf_component_register(SRCS "hid_app.c" "main.c"
+idf_component_register(SRCS "cdc_app.c" "hid_app.c" "main.c" "msc_app.c"
                     INCLUDE_DIRS "."
                     REQUIRES boards tinyusb_src)
+
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
new file mode 100644
index 000000000..fc2b1228d
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -0,0 +1,109 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+//------------- IMPLEMENTATION -------------//
+
+size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
+  size_t count = 0;
+  while (count < bufsize) {
+    int ch = board_getchar();
+    if (ch <= 0) break;
+
+    buf[count] = (uint8_t) ch;
+    count++;
+  }
+
+  return count;
+}
+
+void cdc_app_task(void* param) {
+  (void) param;
+
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  while (1) {
+    uint32_t count = get_console_inputs(buf, bufsize);
+    buf[count] = 0;
+
+    if (count) {
+      // loop over all mounted interfaces
+      for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+        if (tuh_cdc_mounted(idx)) {
+          // console --> cdc interfaces
+          tuh_cdc_write(idx, buf, count);
+          tuh_cdc_write_flush(idx);
+        }
+      }
+    }
+
+    taskYIELD();
+  }
+}
+
+// Invoked when received new data
+void tuh_cdc_rx_cb(uint8_t idx) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  // forward cdc interfaces -> console
+  uint32_t count = tuh_cdc_read(idx, buf, bufsize);
+  buf[count] = 0;
+
+  printf((char *) buf);
+}
+
+void tuh_cdc_mount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = { 0 };
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+  // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
+  // otherwise you need to call tuh_cdc_set_line_coding() first
+  cdc_line_coding_t line_coding = { 0 };
+  if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
+    printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
+  }
+#endif
+}
+
+void tuh_cdc_umount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = { 0 };
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
new file mode 100644
index 000000000..07d159fd5
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
@@ -0,0 +1,111 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "common/tusb_common.h"
+
+void vApplicationMallocFailedHook(void) {
+  taskDISABLE_INTERRUPTS();
+  TU_ASSERT(false,);
+}
+
+void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) {
+  (void) pxTask;
+  (void) pcTaskName;
+
+  taskDISABLE_INTERRUPTS();
+  TU_ASSERT(false,);
+}
+
+/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+ * used by the Idle task. */
+void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer,
+                                   uint32_t *pulIdleTaskStackSize) {
+  /* If the buffers to be provided to the Idle task are declared inside this
+   * function then they must be declared static - otherwise they will be allocated on
+   * the stack and so not exists after this function exits. */
+  static StaticTask_t xIdleTaskTCB;
+  static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE];
+
+  /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+    state will be stored. */
+  *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+  /* Pass out the array that will be used as the Idle task's stack. */
+  *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+  /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+  *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+
+/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer,
+                                    uint32_t *pulTimerTaskStackSize) {
+  /* If the buffers to be provided to the Timer task are declared inside this
+   * function then they must be declared static - otherwise they will be allocated on
+   * the stack and so not exists after this function exits. */
+  static StaticTask_t xTimerTaskTCB;
+  static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH];
+
+  /* Pass out a pointer to the StaticTask_t structure in which the Timer
+    task's state will be stored. */
+  *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+  /* Pass out the array that will be used as the Timer task's stack. */
+  *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+  /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
+  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+
+#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X
+#include "iodefine.h"
+void vApplicationSetupTimerInterrupt(void)
+{
+  /* Enable CMT0 */
+  SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
+  MSTP(CMT0)       = 0;
+  SYSTEM.PRCR.WORD = (0xA5u<<8);
+
+  CMT0.CMCNT      = 0;
+  CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
+  CMT0.CMCR.WORD  = TU_BIT(6) | 2;
+  IR(CMT0, CMI0)  = 0;
+  IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
+  IEN(CMT0, CMI0) = 1;
+  CMT.CMSTR0.BIT.STR0 = 1;
+}
+#endif
diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
new file mode 100644
index 000000000..a2df3b909
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
@@ -0,0 +1,263 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+// If your host terminal support ansi escape code such as TeraTerm
+// it can be use to simulate mouse cursor movement within terminal
+#define USE_ANSI_ESCAPE   0
+
+#define MAX_REPORT  4
+
+static uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII };
+
+// Each HID instance can has multiple reports
+static struct {
+  uint8_t report_count;
+  tuh_hid_report_info_t report_info[MAX_REPORT];
+} hid_info[CFG_TUH_HID];
+
+static void process_kbd_report(hid_keyboard_report_t const *report);
+static void process_mouse_report(hid_mouse_report_t const *report);
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len);
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device with hid interface is mounted
+// Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
+// can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *desc_report, uint16_t desc_len) {
+  printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
+
+  // Interface protocol (hid_interface_protocol_enum_t)
+  const char *protocol_str[] = { "None", "Keyboard", "Mouse" };
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+  printf("HID Interface Protocol = %s\r\n", protocol_str[itf_protocol]);
+
+  // By default host stack will use activate boot protocol on supported interface.
+  // Therefore for this simple example, we only need to parse generic report descriptor (with built-in parser)
+  if (itf_protocol == HID_ITF_PROTOCOL_NONE) {
+    hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT,
+                                                                      desc_report, desc_len);
+    printf("HID has %u reports \r\n", hid_info[instance].report_count);
+  }
+
+  // request to receive report
+  // tuh_hid_report_received_cb() will be invoked when report is available
+  if (!tuh_hid_receive_report(dev_addr, instance)) {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+// Invoked when device with hid interface is un-mounted
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) {
+  printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+}
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+  switch (itf_protocol) {
+    case HID_ITF_PROTOCOL_KEYBOARD:
+      TU_LOG2("HID receive boot keyboard report\r\n");
+      process_kbd_report((hid_keyboard_report_t const *) report);
+      break;
+
+    case HID_ITF_PROTOCOL_MOUSE:
+      TU_LOG2("HID receive boot mouse report\r\n");
+      process_mouse_report((hid_mouse_report_t const *) report);
+      break;
+
+    default:
+      // Generic report requires matching ReportID and contents with previous parsed report info
+      process_generic_report(dev_addr, instance, report, len);
+      break;
+  }
+
+  // continue to request to receive report
+  if (!tuh_hid_receive_report(dev_addr, instance)) {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+//--------------------------------------------------------------------+
+// Keyboard
+//--------------------------------------------------------------------+
+
+// look up new key in previous keys
+static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode) {
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i] == keycode) return true;
+  }
+
+  return false;
+}
+
+static void process_kbd_report(hid_keyboard_report_t const *report) {
+  static hid_keyboard_report_t prev_report = { 0, 0, { 0 } }; // previous report to check key released
+
+  //------------- example code ignore control (non-printable) key affects -------------//
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i]) {
+      if (find_key_in_report(&prev_report, report->keycode[i])) {
+        // exist in previous report means the current key is holding
+      } else {
+        // not existed in previous report means the current key is pressed
+        bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
+        uint8_t ch = keycode2ascii[report->keycode[i]][is_shift ? 1 : 0];
+        putchar(ch);
+        if (ch == '\r') putchar('\n'); // added new line for enter key
+
+        #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
+        fflush(stdout); // flush right away, else nanolib will wait for newline
+        #endif
+      }
+    }
+    // TODO example skips key released
+  }
+
+  prev_report = *report;
+}
+
+//--------------------------------------------------------------------+
+// Mouse
+//--------------------------------------------------------------------+
+
+void cursor_movement(int8_t x, int8_t y, int8_t wheel) {
+#if USE_ANSI_ESCAPE
+  // Move X using ansi escape
+  if ( x < 0) {
+    printf(ANSI_CURSOR_BACKWARD(%d), (-x)); // move left
+  }else if ( x > 0) {
+    printf(ANSI_CURSOR_FORWARD(%d), x); // move right
+  }
+
+  // Move Y using ansi escape
+  if ( y < 0) {
+    printf(ANSI_CURSOR_UP(%d), (-y)); // move up
+  }else if ( y > 0) {
+    printf(ANSI_CURSOR_DOWN(%d), y); // move down
+  }
+
+  // Scroll using ansi escape
+  if (wheel < 0) {
+    printf(ANSI_SCROLL_UP(%d), (-wheel)); // scroll up
+  }else if (wheel > 0) {
+    printf(ANSI_SCROLL_DOWN(%d), wheel); // scroll down
+  }
+
+  printf("\r\n");
+#else
+  printf("(%d %d %d)\r\n", x, y, wheel);
+#endif
+}
+
+static void process_mouse_report(hid_mouse_report_t const *report) {
+  static hid_mouse_report_t prev_report = { 0 };
+
+  //------------- button state  -------------//
+  uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
+  if (button_changed_mask & report->buttons) {
+    printf(" %c%c%c ",
+           report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-',
+           report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-',
+           report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-');
+  }
+
+  //------------- cursor movement -------------//
+  cursor_movement(report->x, report->y, report->wheel);
+}
+
+//--------------------------------------------------------------------+
+// Generic Report
+//--------------------------------------------------------------------+
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+  (void) dev_addr;
+
+  uint8_t const rpt_count = hid_info[instance].report_count;
+  tuh_hid_report_info_t *rpt_info_arr = hid_info[instance].report_info;
+  tuh_hid_report_info_t *rpt_info = NULL;
+
+  if (rpt_count == 1 && rpt_info_arr[0].report_id == 0) {
+    // Simple report without report ID as 1st byte
+    rpt_info = &rpt_info_arr[0];
+  } else {
+    // Composite report, 1st byte is report ID, data starts from 2nd byte
+    uint8_t const rpt_id = report[0];
+
+    // Find report id in the array
+    for (uint8_t i = 0; i < rpt_count; i++) {
+      if (rpt_id == rpt_info_arr[i].report_id) {
+        rpt_info = &rpt_info_arr[i];
+        break;
+      }
+    }
+
+    report++;
+    len--;
+  }
+
+  if (!rpt_info) {
+    printf("Couldn't find report info !\r\n");
+    return;
+  }
+
+  // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples:
+  // - Keyboard                     : Desktop, Keyboard
+  // - Mouse                        : Desktop, Mouse
+  // - Gamepad                      : Desktop, Gamepad
+  // - Consumer Control (Media Key) : Consumer, Consumer Control
+  // - System Control (Power key)   : Desktop, System Control
+  // - Generic (vendor)             : 0xFFxx, xx
+  if (rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP) {
+    switch (rpt_info->usage) {
+      case HID_USAGE_DESKTOP_KEYBOARD:
+        TU_LOG1("HID receive keyboard report\r\n");
+        // Assume keyboard follow boot report layout
+        process_kbd_report((hid_keyboard_report_t const *) report);
+        break;
+
+      case HID_USAGE_DESKTOP_MOUSE:
+        TU_LOG1("HID receive mouse report\r\n");
+        // Assume mouse follow boot report layout
+        process_mouse_report((hid_mouse_report_t const *) report);
+        break;
+
+      default:
+        break;
+    }
+  }
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index e2ddd52eb..d5574789f 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -51,6 +51,8 @@
   #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
+#define CDC_STACK_SZIE      (3*configMINIMAL_STACK_SIZE/2)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
@@ -72,18 +74,16 @@ StaticTimer_t blinky_tmdef;
 StackType_t  usb_host_stack[USBH_STACK_SIZE];
 StaticTask_t usb_host_taskdef;
 
-//StackType_t  cdc_stack[CDC_STACK_SZIE];
-//StaticTask_t cdc_taskdef;
+StackType_t  cdc_stack[CDC_STACK_SZIE];
+StaticTask_t cdc_taskdef;
 #endif
 
-
 TimerHandle_t blinky_tm;
 
 static void led_blinky_cb(TimerHandle_t xTimer);
 static void usb_host_task(void* param);
 
-extern void cdc_app_task(void);
-extern void hid_app_task(void);
+extern void cdc_app_task(void* param);
 
 /*------------- MAIN -------------*/
 int main(void) {
@@ -91,19 +91,15 @@ int main(void) {
 
   printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n");
 
+  // Create soft timer for blinky, task for tinyusb stack and CDC
 #if configSUPPORT_STATIC_ALLOCATION
-  // soft timer for blinky
   blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
-
-  // Create a task for tinyusb device stack
   xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef);
-
-  // Create CDC task
-  //xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  xTaskCreateStatic(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 #else
   blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
-  xTaskCreate( usb_device_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
-  //xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+  xTaskCreate(usb_host_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+  xTaskCreate(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
 #endif
 
   xTimerStart(blinky_tm, 0);
diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
new file mode 100644
index 000000000..a8d6fbfaa
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
@@ -0,0 +1,67 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+#if CFG_TUH_MSC
+
+static scsi_inquiry_resp_t inquiry_resp;
+
+bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
+  msc_cbw_t const *cbw = cb_data->cbw;
+  msc_csw_t const *csw = cb_data->csw;
+
+  if (csw->status != 0) {
+    printf("Inquiry failed\r\n");
+    return false;
+  }
+
+  // Print out Vendor ID, Product ID and Rev
+  printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
+
+  // Get capacity of device
+  uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
+  uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
+
+  printf("Disk Size: %lu MB\r\n", block_count / ((1024 * 1024) / block_size));
+  printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+
+  return true;
+}
+
+//------------- IMPLEMENTATION -------------//
+void tuh_msc_mount_cb(uint8_t dev_addr) {
+  printf("A MassStorage device is mounted\r\n");
+
+  uint8_t const lun = 0;
+  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
+}
+
+void tuh_msc_umount_cb(uint8_t dev_addr) {
+  (void) dev_addr;
+  printf("A MassStorage device is unmounted\r\n");
+}
+
+#endif
diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
index 325263c1d..8209e8747 100644
--- a/hw/bsp/espressif/boards/CMakeLists.txt
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -4,3 +4,5 @@ idf_component_register(SRCS family.c
                     INCLUDE_DIRS "." ${BOARD} ${hw_dir}
                     PRIV_REQUIRES "driver"
                     REQUIRES led_strip src tinyusb_src)
+
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 250b7001e..d96d86670 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -33,6 +33,7 @@
 #include "soc/usb_periph.h"
 
 #include "driver/rmt.h"
+#include "driver/uart.h"
 
 #if ESP_IDF_VERSION_MAJOR > 4
   #include "esp_private/periph_ctrl.h"
@@ -145,9 +146,7 @@ uint32_t board_button_read(void) {
 
 // Get characters from UART
 int board_uart_read(uint8_t *buf, int len) {
-  (void) buf;
-  (void) len;
-  return 0;
+  return uart_read_bytes(UART_NUM_0, buf, len, 0);
 }
 
 // Send characters to UART
@@ -157,6 +156,11 @@ int board_uart_write(void const *buf, int len) {
   return 0;
 }
 
+int board_getchar(void) {
+  char c;
+  return (uart_read_bytes(UART_NUM_0, &c, 1, 0) > 0) ? (int) c : (-1);
+}
+
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
@@ -164,12 +168,12 @@ int board_uart_write(void const *buf, int len) {
 
 static spi_device_handle_t max3421_spi;
 
-static void IRAM_ATTR max3421_isr_handler(void* arg)
-{
-  (void) arg;
-  //uint32_t gpio_num = (uint32_t) arg;
+static void IRAM_ATTR max3421_isr_handler(void* arg) {
+  (void) arg; // arg is gpio num
   //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL);
+  gpio_set_level(13, 1);
   tuh_int_handler(1);
+  gpio_set_level(13, 0);
 }
 
 static void max3421_init(void) {
@@ -188,12 +192,11 @@ static void max3421_init(void) {
       .data5_io_num = -1,
       .data6_io_num = -1,
       .data7_io_num = -1,
-      .max_transfer_sz = 128
+      .max_transfer_sz = 1024
   };
   ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) );
 
   spi_device_interface_config_t max3421_cfg = {
-      .command_bits = 8,
       .mode = 0,
       .clock_speed_hz = 4000000, // 26000000
       .spics_io_num = -1, // manual control CS
@@ -201,12 +204,16 @@ static void max3421_init(void) {
   };
   ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) );
 
+  // debug
+  gpio_set_direction(13, GPIO_MODE_OUTPUT);
+  gpio_set_level(13, 0);
+
   // Interrupt pin
-//  gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
-//  gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
-//
-//  gpio_install_isr_service(ESP_INTR_FLAG_EDGE);
-//  gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
+  gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
+  gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
+
+  gpio_install_isr_service(0);
+  gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
 }
 
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
@@ -227,8 +234,8 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
   (void) rhport;
 
   spi_transaction_t xact = {
-      .length = tx_len,
-      .rxlength = rx_len,
+      .length = tx_len << 3, // length in bits
+      .rxlength = rx_len << 3, // length in bits
       .tx_buffer = tx_buf,
       .rx_buffer = rx_buf
   };
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index 2a154a8ff..abe276910 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -70,3 +70,4 @@ idf_component_register(SRCS ${srcs}
   )
 
 target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 6fcfd9476..3620bc8cc 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -95,13 +95,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 
 //------------- Host using MAX2341E -------------//
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+static void max3421_init(void);
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
-
-void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
-  if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
-
-  tuh_int_handler(1);
-}
 #endif
 
 
@@ -191,50 +186,7 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-  // MAX3421 need 3.3v signal (may not be needed)
-  #if defined(UICR_REGOUT0_VOUT_Msk) && 0
-  if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
-    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
-
-    NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
-
-    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
-
-    NVIC_SystemReset();
-  }
-  #endif
-
-  // manually manage CS
-  nrf_gpio_cfg_output(MAX3421_CS_PIN);
-  nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
-
-  // USB host using max3421e usb controller via SPI
-  nrfx_spim_config_t cfg = {
-      .sck_pin        = MAX3421_SCK_PIN,
-      .mosi_pin       = MAX3421_MOSI_PIN,
-      .miso_pin       = MAX3421_MISO_PIN,
-      .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
-      .ss_active_high = false,
-      .irq_priority   = 3,
-      .orc            = 0xFF,
-      // default setting 4 Mhz, Mode 0, MSB first
-      .frequency      = NRF_SPIM_FREQ_4M,
-      .mode           = NRF_SPIM_MODE_0,
-      .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
-  };
-
-  // no handler --> blocking
-  nrfx_spim_init(&_spi, &cfg, NULL, NULL);
-
-  // max3421e interrupt pin
-  nrfx_gpiote_init(1);
-  nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
-  in_config.pull = NRF_GPIO_PIN_PULLUP;
-
-  nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
-  nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
+  max3421_init();
 #endif
 
 }
@@ -317,6 +269,60 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
 //--------------------------------------------------------------------+
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
+void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+  if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
+  tuh_int_handler(1);
+}
+
+static void max3421_init(void) {
+  // MAX3421 need 3.3v signal (may not be needed)
+//  #if defined(UICR_REGOUT0_VOUT_Msk)
+//  if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
+//    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+//    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+//
+//    NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
+//
+//    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+//    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+//
+//    NVIC_SystemReset();
+//  }
+//  #endif
+
+  // manually manage CS
+  nrf_gpio_cfg_output(MAX3421_CS_PIN);
+  nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
+
+  // USB host using max3421e usb controller via SPI
+  nrfx_spim_config_t cfg = {
+      .sck_pin        = MAX3421_SCK_PIN,
+      .mosi_pin       = MAX3421_MOSI_PIN,
+      .miso_pin       = MAX3421_MISO_PIN,
+      .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
+      .ss_active_high = false,
+      .irq_priority   = 3,
+      .orc            = 0xFF,
+      // default setting 4 Mhz, Mode 0, MSB first
+      .frequency      = NRF_SPIM_FREQ_4M,
+      .mode           = NRF_SPIM_MODE_0,
+      .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
+  };
+
+  // no handler --> blocking
+  nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+
+  // max3421e interrupt pin
+  nrfx_gpiote_init(1);
+  nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
+  in_config.pull = NRF_GPIO_PIN_PULLUP;
+
+  NVIC_SetPriority(GPIOTE_IRQn, 2);
+
+  nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
+  nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
+}
+
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 395155548..335039e2f 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -261,6 +261,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+#endif
 
 //--------------------------------------------------------------------+
 //
@@ -344,6 +345,11 @@ static void max3421_init(void) {
   EIC->CONFIG[0].reg &= ~(7 << sense_shift);
   EIC->CONFIG[0].reg |= 2 << sense_shift;
 
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(EIC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
   // Enable External Interrupt
   EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
@@ -413,6 +419,3 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 }
 
 #endif
-
-
-#endif
diff --git a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
index e3ee529cf..32db4ad95 100644
--- a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
@@ -59,7 +59,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*6*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index c1b914a02..7b9de35c9 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -175,6 +175,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+#endif
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
@@ -290,6 +291,11 @@ static void max3421_init(void) {
   *eic_config &= ~(7 << sense_shift);
   *eic_config |= 2 << sense_shift;
 
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(EIC_0_IRQn + MAX3421_INTR_EIC_ID, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
   // Enable External Interrupt
   EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
@@ -360,5 +366,3 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 }
 
 #endif
-
-#endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index dc2831da3..e332f35cc 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -659,7 +659,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %u\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     TU_LOG1_BUF(request, 8);
     TU_LOG1("\r\n");
 
-- 
cgit v1.3.1


From 1168e4e16343cc0a6d958899460f1b841624974f Mon Sep 17 00:00:00 2001
From: bac <ben.cowperthwaite@sonardyne.com>
Date: Tue, 26 Sep 2023 15:27:17 +0100
Subject: Added support for USB2 HS peripheral (with integrated HS PHY) on
 STM32U59x chips

---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index cb455bd90..aa77511fa 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -84,7 +84,17 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
   #include "stm32u5xx.h"
-  #define USB_OTG_FS_PERIPH_BASE       USB_OTG_FS_BASE
+  // NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY)
+  // USB_OTG_FS_BASE and OTG_FS_IRQn not defined
+  #if (! defined USB_OTG_FS)
+    #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE
+    #define EP_MAX_HS                 9
+    #define EP_FIFO_SIZE_HS           4096
+    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_HS_BASE
+    #define OTG_FS_IRQn               OTG_HS_IRQn
+  #else
+    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_FS_BASE
+  #endif
   #define EP_MAX_FS       6
   #define EP_FIFO_SIZE_FS 1280
 
-- 
cgit v1.3.1


From 2f6592de7f94851cfcca411242398c5da7b792de Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 11:30:18 +0700
Subject: update max3421 to have hcd_int_handler_ext()

---
 hw/bsp/espressif/boards/family.c          | 22 ++++++++++-
 src/host/hcd.h                            |  3 ++
 src/portable/analog/max3421/hcd_max3421.c | 62 ++++++++++++++++---------------
 3 files changed, 55 insertions(+), 32 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index d96d86670..a04e1e7c5 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -167,15 +167,30 @@ int board_getchar(void) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
 static spi_device_handle_t max3421_spi;
+SemaphoreHandle_t max3421_intr_sem;
 
 static void IRAM_ATTR max3421_isr_handler(void* arg) {
   (void) arg; // arg is gpio num
-  //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL);
   gpio_set_level(13, 1);
-  tuh_int_handler(1);
+
+  BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  xSemaphoreGiveFromISR(max3421_intr_sem, &xHigherPriorityTaskWoken);
+  if (xHigherPriorityTaskWoken) {
+    portYIELD_FROM_ISR();
+  }
+
   gpio_set_level(13, 0);
 }
 
+static void max3421_intr_task(void* param) {
+  (void) param;
+
+  while (1) {
+    xSemaphoreTake(max3421_intr_sem, portMAX_DELAY);
+    tuh_int_handler(BOARD_TUH_RHPORT);
+  }
+}
+
 static void max3421_init(void) {
   // CS pin
   gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT);
@@ -209,6 +224,9 @@ static void max3421_init(void) {
   gpio_set_level(13, 0);
 
   // Interrupt pin
+  max3421_intr_sem = xSemaphoreCreateBinary();
+  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-1, NULL);
+
   gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
   gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index e25b20ea3..a2d4da85d 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -133,6 +133,9 @@ bool hcd_init(uint8_t rhport);
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport);
 
+// Interrupt Hanndler (extended version)
+void hcd_int_handler_ext(uint8_t rhport, bool in_isr);
+
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport);
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 3f6747404..652a971ee 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -428,8 +428,8 @@ bool hcd_init(uint8_t rhport) {
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
   // V1 is 0x01, V2 is 0x12, V3 is 0x13
-  // uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
-  // TU_LOG2_HEX(revision);
+  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+  TU_LOG2_HEX(revision);
 
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
@@ -693,9 +693,7 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
 
       // port reset anyway, this will help to stable bus signal for next connection
       reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr);
-
       hcd_event_device_remove(rhport, in_isr);
-
       reg_write(rhport, HCTL_ADDR, 0, in_isr);
       break;
 
@@ -721,13 +719,12 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
       free_ep(daddr);
 
       hcd_event_device_attach(rhport, in_isr);
-
       break;
     }
   }
 }
 
-static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) {
+static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl, bool in_isr) {
   uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
 
   // save data toggle
@@ -738,20 +735,20 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
   }
 
   ep->xfer_pending = 0;
-  hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true);
+  hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, in_isr);
 
   // Find next pending endpoint
   max3421_ep_t *next_ep = find_next_pending_ep(ep);
   if (next_ep) {
-    xact_inout(rhport, next_ep, true, true);
+    xact_inout(rhport, next_ep, true, in_isr);
   }else {
     // no more pending
     atomic_flag_clear(&_hcd_data.busy);
   }
 }
 
-static void handle_xfer_done(uint8_t rhport) {
-  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
+static void handle_xfer_done(uint8_t rhport, bool in_isr) {
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
 
   uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
@@ -774,17 +771,17 @@ static void handle_xfer_done(uint8_t rhport) {
     case HRSL_NAK:
       if (ep_num == 0) {
         // NAK on control, retry immediately
-        hxfr_write(rhport, _hcd_data.hxfr, true);
+        hxfr_write(rhport, _hcd_data.hxfr, in_isr);
       }else {
         // NAK on non-control, find next pending to switch
         max3421_ep_t *next_ep = find_next_pending_ep(ep);
 
         if (ep == next_ep) {
           // this endpoint is only one pending, retry immediately
-          hxfr_write(rhport, _hcd_data.hxfr, true);
+          hxfr_write(rhport, _hcd_data.hxfr, in_isr);
         }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
-          xact_inout(rhport, next_ep, true, true);
+          xact_inout(rhport, next_ep, true, in_isr);
         }else {
           TU_ASSERT(false,);
         }
@@ -802,7 +799,7 @@ static void handle_xfer_done(uint8_t rhport) {
   }
 
   if (xfer_result != XFER_RESULT_SUCCESS) {
-    xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+    xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
     return;
   }
 
@@ -814,10 +811,10 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
     }else {
       // more to transfer
-      hxfr_write(rhport, _hcd_data.hxfr, true);
+      hxfr_write(rhport, _hcd_data.hxfr, in_isr);
     }
   } else {
     // SETUP or OUT transfer
@@ -835,10 +832,10 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
-      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
     } else {
       // more to transfer
-      xact_out(rhport, ep, false, true);
+      xact_out(rhport, ep, false, in_isr);
     }
   }
 }
@@ -862,9 +859,9 @@ void print_hirq(uint8_t hirq) {
   #define print_hirq(hirq)
 #endif
 
-// Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
-  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
+// Interrupt handler (extended)
+void hcd_int_handler_ext(uint8_t rhport, bool in_isr) {
+  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, in_isr) & _hcd_data.hien;
   if (!hirq) return;
 //  print_hirq(hirq);
 
@@ -873,7 +870,7 @@ void hcd_int_handler(uint8_t rhport) {
   }
 
   if (hirq & HIRQ_CONDET_IRQ) {
-    handle_connect_irq(rhport, true);
+    handle_connect_irq(rhport, in_isr);
   }
 
   // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
@@ -886,17 +883,17 @@ void hcd_int_handler(uint8_t rhport) {
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
       while ( hirq & HIRQ_RCVDAV_IRQ ) {
-        uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true);
+        uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
         xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
         if ( xact_len ) {
-          fifo_read(rhport, ep->buf, xact_len, true);
+          fifo_read(rhport, ep->buf, xact_len, in_isr);
           ep->buf += xact_len;
           ep->xferred_len += xact_len;
         }
 
         // ack RCVDVAV IRQ
-        hirq_write(rhport, HIRQ_RCVDAV_IRQ, true);
-        hirq = reg_read(rhport, HIRQ_ADDR, true);
+        hirq_write(rhport, HIRQ_RCVDAV_IRQ, in_isr);
+        hirq = reg_read(rhport, HIRQ_ADDR, in_isr);
       }
 
       if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -905,18 +902,23 @@ void hcd_int_handler(uint8_t rhport) {
     }
 
     if ( hirq & HIRQ_HXFRDN_IRQ ) {
-      hirq_write(rhport, HIRQ_HXFRDN_IRQ, true);
-      handle_xfer_done(rhport);
+      hirq_write(rhport, HIRQ_HXFRDN_IRQ, in_isr);
+      handle_xfer_done(rhport, in_isr);
     }
 
-    hirq = reg_read(rhport, HIRQ_ADDR, true);
+    hirq = reg_read(rhport, HIRQ_ADDR, in_isr);
   }
 
   // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
   hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
-    hirq_write(rhport, hirq, true);
+    hirq_write(rhport, hirq, in_isr);
   }
 }
 
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  hcd_int_handler_ext(rhport, true);
+}
+
 #endif
-- 
cgit v1.3.1


From 3b0ffd0f488671f1bafa4bcd9e22dd51f8bb6dee Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 15:51:03 +0700
Subject: change hcd_int_handler(rhport, in_isr) signature: add in_isr

change tuh_int_handler() to take in_isr as optional parameter (default =
true)
---
 examples/host/bare_api/only.txt                    |  1 +
 examples/host/cdc_msc_hid/only.txt                 |  1 +
 examples/host/hid_controller/only.txt              |  1 +
 examples/host/msc_file_explorer/only.txt           |  1 +
 hw/bsp/imxrt/family.c                              |  4 +-
 hw/bsp/kinetis_kl/family.c                         |  2 +-
 hw/bsp/kinetis_kl/family.cmake                     | 75 ++++++++++----------
 .../lpc17/boards/lpcxpresso1769/lpcxpresso1769.c   |  2 +-
 hw/bsp/lpc17/boards/mbed1768/mbed1768.c            |  2 +-
 hw/bsp/lpc18/family.c                              | 55 ++++++---------
 hw/bsp/lpc40/family.c                              |  2 +-
 hw/bsp/lpc43/family.c                              |  4 +-
 hw/bsp/msp432e4/family.c                           |  2 +-
 hw/bsp/ngx4330/ngx4330.c                           |  4 +-
 hw/bsp/nrf/family.c                                |  2 +-
 hw/bsp/ra/family.c                                 |  6 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c       |  2 +-
 hw/bsp/samd21/family.c                             |  2 +-
 hw/bsp/samd51/family.c                             |  2 +-
 hw/bsp/stm32g4/family.cmake                        | 81 +++++++++++-----------
 hw/bsp/tm4c123/family.c                            |  2 +-
 src/common/tusb_common.h                           |  2 -
 src/common/tusb_timeout.h                          | 80 ---------------------
 src/common/tusb_verify.h                           | 52 +++++---------
 src/host/hcd.h                                     |  2 +-
 src/host/usbh.h                                    | 11 ++-
 src/portable/analog/max3421/hcd_max3421.c          |  3 +-
 src/portable/ehci/ehci.c                           |  4 +-
 src/portable/mentor/musb/hcd_musb.c                |  4 +-
 src/portable/nxp/khci/hcd_khci.c                   |  7 +-
 src/portable/ohci/ohci.c                           |  5 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c       |  4 +-
 src/portable/renesas/rusb2/hcd_rusb2.c             |  5 +-
 src/portable/template/hcd_template.c               |  3 +-
 src/tusb.h                                         |  4 +-
 35 files changed, 172 insertions(+), 267 deletions(-)
 delete mode 100644 src/common/tusb_timeout.h

(limited to 'src')

diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index ec95a8b24..32d89f794 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -188,7 +188,7 @@ void USB_OTG1_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
@@ -199,7 +199,7 @@ void USB_OTG2_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+    tuh_int_handler(1, true);
   #endif
 }
 
diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c
index 3e9aa83a4..c436be3e6 100644
--- a/hw/bsp/kinetis_kl/family.c
+++ b/hw/bsp/kinetis_kl/family.c
@@ -39,7 +39,7 @@
 void USB0_IRQHandler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
index 793ef1783..4151979a0 100644
--- a/hw/bsp/kinetis_kl/family.cmake
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -22,48 +22,47 @@ set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      ${SDK_DIR}/drivers/gpio/fsl_gpio.c
-      ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c
-      ${SDK_DIR}/drivers/uart/fsl_uart.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-      ${SDK_DIR}/drivers/common
-      ${SDK_DIR}/drivers/gpio
-      ${SDK_DIR}/drivers/lpsci
-      ${SDK_DIR}/drivers/port
-      ${SDK_DIR}/drivers/smc
-      ${SDK_DIR}/drivers/uart
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c
+    ${SDK_DIR}/drivers/uart/fsl_uart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/gpio
+    ${SDK_DIR}/drivers/lpsci
+    ${SDK_DIR}/drivers/port
+    ${SDK_DIR}/drivers/smc
+    ${SDK_DIR}/drivers/uart
+    )
+  update_board(${BOARD_TARGET})
 
-    # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
 
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
       )
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
   endif ()
 endfunction()
 
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
index c7d655368..8c26b906f 100644
--- a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
@@ -37,7 +37,7 @@ void USB_IRQHandler(void)
   #endif
 
   #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
diff --git a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
index b2c92d640..613dcb570 100644
--- a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
+++ b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
@@ -151,7 +151,7 @@ void USB_IRQHandler(void)
   #endif
 
   #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index b11f4fe0e..e6abecb4b 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -43,25 +43,23 @@
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
   #if PORT_SUPPORT_DEVICE(0)
-    tud_int_handler(0);
+  tud_int_handler(0);
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 }
 
-void USB1_IRQHandler(void)
-{
+void USB1_IRQHandler(void) {
   #if PORT_SUPPORT_DEVICE(1)
-    tud_int_handler(1);
+  tud_int_handler(1);
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+  tuh_int_handler(1, true);
   #endif
 }
 
@@ -74,28 +72,26 @@ const uint32_t OscRateIn = 12000000;
 const uint32_t ExtRateIn = 0;
 
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
+  extern void (*const g_pfnVectors[])(void);
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+  *pSCB_VTOR = (unsigned int) g_pfnVectors;
 #endif
 
   board_lpc18_pinmux();
 
-  #ifdef TRACE_ETM
+#ifdef TRACE_ETM
   // Trace clock is limited to 60MHz, limit CPU clock to 120MHz
   Chip_SetupCoreClock(CLKIN_CRYSTAL, 120000000UL, true);
-  #else
+#else
   // CPU clock max to 180 Mhz
   Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
-  #endif
+#endif
 
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -135,27 +131,22 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // active low
   return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
   return Chip_UART_Read(UART_DEV, buf, len);
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
+int board_uart_write(void const *buf, int len) {
+  uint8_t const *buf8 = (uint8_t const *) buf;
+  for (int i = 0; i < len; i++) {
     while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
     Chip_UART_SendByte(UART_DEV, buf8[i]);
   }
@@ -165,13 +156,13 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c
index 526e3a080..d6c8ef32a 100644
--- a/hw/bsp/lpc40/family.c
+++ b/hw/bsp/lpc40/family.c
@@ -37,7 +37,7 @@ void USB_IRQHandler(void) {
   #endif
 
   #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 }
 
diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index d52c1a071..8be729f7d 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -213,7 +213,7 @@ void USB0_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
@@ -224,7 +224,7 @@ void USB1_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+    tuh_int_handler(1, true);
   #endif
 }
 
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 10f3ac736..d5ef7f930 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -34,7 +34,7 @@
 void USB0_IRQHandler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
index a767d5f29..bd84e449b 100644
--- a/hw/bsp/ngx4330/ngx4330.c
+++ b/hw/bsp/ngx4330/ngx4330.c
@@ -214,7 +214,7 @@ void USB0_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
@@ -225,7 +225,7 @@ void USB1_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+    tuh_int_handler(1, true);
   #endif
 }
 
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 6fcfd9476..fc755f512 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -100,7 +100,7 @@ static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
 
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
 }
 #endif
 
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 0aa58d86d..fdf4c8666 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -188,7 +188,7 @@ void usbfs_interrupt_handler(void) {
   R_BSP_IrqStatusClear(irq);
 
   #if PORT_SUPPORT_HOST(0)
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 
   #if PORT_SUPPORT_DEVICE(0)
@@ -201,7 +201,7 @@ void usbfs_resume_handler(void) {
   R_BSP_IrqStatusClear(irq);
 
   #if PORT_SUPPORT_HOST(0)
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 
   #if PORT_SUPPORT_DEVICE(0)
@@ -229,7 +229,7 @@ void usbhs_interrupt_handler(void) {
   R_BSP_IrqStatusClear(irq);
 
   #if PORT_SUPPORT_HOST(1)
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
   #endif
 
   #if PORT_SUPPORT_DEVICE(1)
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 513eca678..032dac810 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -177,7 +177,7 @@ void INT_Excep_SCI5_RXI5(void)
 void INT_Excep_USB0_USBI0(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index cfe66b8dc..0ea729055 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -356,7 +356,7 @@ void EIC_Handler(void) {
   EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
   // Call the TinyUSB interrupt handler
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
 }
 
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 2cf00c7af..268d60e48 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -296,7 +296,7 @@ void MAX3421_EIC_Handler(void) {
   EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
   // Call the TinyUSB interrupt handler
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
 }
 
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 675a96c74..f8cabcbe5 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -26,50 +26,47 @@ set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    # Startup & Linker script
-    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-    add_library(${BOARD_TARGET} STATIC
-      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-      ${CMSIS_5}/CMSIS/Core/Include
-      ${ST_CMSIS}/Include
-      ${ST_HAL_DRIVER}/Inc
-      )
-    target_compile_options(${BOARD_TARGET} PUBLIC
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
       )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
       )
-
-    update_board(${BOARD_TARGET})
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        -nostartfiles
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
   endif ()
 endfunction()
 
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index ad5ae505f..738bc3fa0 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -8,7 +8,7 @@
 void USB0_Handler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 
 #if CFG_TUD_ENABLED
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 6fffed11c..caeb5f2ef 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -75,8 +75,6 @@
 #include "tusb_types.h"
 #include "tusb_debug.h"
 
-#include "tusb_timeout.h" // TODO remove
-
 //--------------------------------------------------------------------+
 // Optional API implemented by application if needed
 // TODO move to a more ovious place/file
diff --git a/src/common/tusb_timeout.h b/src/common/tusb_timeout.h
deleted file mode 100644
index 533e67ab8..000000000
--- a/src/common/tusb_timeout.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup Group_Common Common Files
- *  \defgroup Group_TimeoutTimer timeout timer
- *  @{ */
-
-#ifndef _TUSB_TIMEOUT_H_
-#define _TUSB_TIMEOUT_H_
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-  uint32_t start;
-  uint32_t interval;
-}tu_timeout_t;
-
-#if 0
-
-extern uint32_t tusb_hal_millis(void);
-
-static inline void tu_timeout_set(tu_timeout_t* tt, uint32_t msec)
-{
-  tt->interval = msec;
-  tt->start    = tusb_hal_millis();
-}
-
-static inline bool tu_timeout_expired(tu_timeout_t* tt)
-{
-  return ( tusb_hal_millis() - tt->start ) >= tt->interval;
-}
-
-// For used with periodic event to prevent drift
-static inline void tu_timeout_reset(tu_timeout_t* tt)
-{
-  tt->start += tt->interval;
-}
-
-static inline void tu_timeout_restart(tu_timeout_t* tt)
-{
-  tt->start = tusb_hal_millis();
-}
-
-#endif
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_TIMEOUT_H_ */
-
-/** @} */
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 12355e8be..1b5f53dfc 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -56,12 +56,8 @@
  *   #define TU_VERIFY(cond)                  if(cond) return false;
  *   #define TU_VERIFY(cond,ret)              if(cond) return ret;
  *
- *   #define TU_VERIFY_HDLR(cond,handler)     if(cond) {handler; return false;}
- *   #define TU_VERIFY_HDLR(cond,ret,handler) if(cond) {handler; return ret;}
- *
  *   #define TU_ASSERT(cond)                  if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;}
  *   #define TU_ASSERT(cond,ret)              if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
- *
  *------------------------------------------------------------------*/
 
 #ifdef __cplusplus
@@ -97,40 +93,23 @@
   #define TU_BREAKPOINT() do {} while (0)
 #endif
 
-/*------------------------------------------------------------------*/
-/* Macro Generator
- *------------------------------------------------------------------*/
-
 // Helper to implement optional parameter for TU_VERIFY Macro family
 #define _GET_3RD_ARG(arg1, arg2, arg3, ...)        arg3
-#define _GET_4TH_ARG(arg1, arg2, arg3, arg4, ...)  arg4
-
-/*------------- Generator for TU_VERIFY and TU_VERIFY_HDLR -------------*/
-#define TU_VERIFY_DEFINE(_cond, _handler, _ret)  do            \
-{                                                              \
-  if ( !(_cond) ) { _handler; return _ret;  }                  \
-} while(0)
 
 /*------------------------------------------------------------------*/
 /* TU_VERIFY
  * - TU_VERIFY_1ARGS : return false if failed
  * - TU_VERIFY_2ARGS : return provided value if failed
  *------------------------------------------------------------------*/
-#define TU_VERIFY_1ARGS(_cond)                         TU_VERIFY_DEFINE(_cond, , false)
-#define TU_VERIFY_2ARGS(_cond, _ret)                   TU_VERIFY_DEFINE(_cond, , _ret)
+#define TU_VERIFY_DEFINE(_cond, _ret)    \
+  do {                                   \
+    if ( !(_cond) ) { return _ret; }     \
+  } while(0)
 
-#define TU_VERIFY(...)                   _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__)
+#define TU_VERIFY_1ARGS(_cond)         TU_VERIFY_DEFINE(_cond, false)
+#define TU_VERIFY_2ARGS(_cond, _ret)   TU_VERIFY_DEFINE(_cond, _ret)
 
-
-/*------------------------------------------------------------------*/
-/* TU_VERIFY WITH HANDLER
- * - TU_VERIFY_HDLR_2ARGS : execute handler, return false if failed
- * - TU_VERIFY_HDLR_3ARGS : execute handler, return provided error if failed
- *------------------------------------------------------------------*/
-#define TU_VERIFY_HDLR_2ARGS(_cond, _handler)           TU_VERIFY_DEFINE(_cond, _handler, false)
-#define TU_VERIFY_HDLR_3ARGS(_cond, _handler, _ret)     TU_VERIFY_DEFINE(_cond, _handler, _ret)
-
-#define TU_VERIFY_HDLR(...)              _GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
+#define TU_VERIFY(...)                 _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__)
 
 /*------------------------------------------------------------------*/
 /* ASSERT
@@ -138,19 +117,20 @@
  * - 1 arg : return false if failed
  * - 2 arg : return error if failed
  *------------------------------------------------------------------*/
-#define ASSERT_1ARGS(_cond)            TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), false)
-#define ASSERT_2ARGS(_cond, _ret)      TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), _ret)
+#define TU_ASSERT_DEFINE(_cond, _ret)                                 \
+  do {                                                                \
+    if ( !(_cond) ) { _MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \
+  } while(0)
+
+#define TU_ASSERT_1ARGS(_cond)         TU_ASSERT_DEFINE(_cond, false)
+#define TU_ASSERT_2ARGS(_cond, _ret)   TU_ASSERT_DEFINE(_cond, _ret)
 
 #ifndef TU_ASSERT
-#define TU_ASSERT(...)             _GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
+#define TU_ASSERT(...)                 _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__)
 #endif
 
-/*------------------------------------------------------------------*/
-/* ASSERT HDLR
- *------------------------------------------------------------------*/
-
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* TUSB_VERIFY_H_ */
+#endif
diff --git a/src/host/hcd.h b/src/host/hcd.h
index e25b20ea3..2bde289df 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -131,7 +131,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_AT
 bool hcd_init(uint8_t rhport);
 
 // Interrupt Handler
-void hcd_int_handler(uint8_t rhport);
+void hcd_int_handler(uint8_t rhport, bool in_isr);
 
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport);
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 684e8240e..770d70dfe 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -124,11 +124,16 @@ void tuh_task(void) {
 bool tuh_task_event_ready(void);
 
 #ifndef _TUSB_HCD_H_
-extern void hcd_int_handler(uint8_t rhport);
+extern void hcd_int_handler(uint8_t rhport, bool in_isr);
 #endif
 
-// Interrupt handler, name alias to HCD
-#define tuh_int_handler   hcd_int_handler
+// Interrupt handler alias to HCD with in_isr as optional parameter
+// - tuh_int_handler(rhport) --> hcd_int_handler(rhport, true)
+// - tuh_int_handler(rhport, in_isr) --> hcd_int_handler(rhport, in_isr)
+// Note: this is similar to TU_VERIFY(), _GET_3RD_ARG() is defined in tusb_verify.h
+#define _tuh_int_handler_1arg(_rhport)            hcd_int_handler(_rhport, true)
+#define _tuh_int_hanlder_2arg(_rhport, _in_isr)   hcd_int_handler(_rhport, _in_isr)
+#define tuh_int_handler(...)   _GET_3RD_ARG(__VA_ARGS__, _tuh_int_hanlder_2arg, _tuh_int_handler_1arg, _dummy)(__VA_ARGS__)
 
 // Check if roothub port is initialized and active as a host
 bool tuh_rhport_is_active(uint8_t rhport);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 238b518a0..d013d6179 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -863,7 +863,8 @@ void print_hirq(uint8_t hirq) {
 #endif
 
 // Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
   uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
   if (!hirq) return;
 //  print_hirq(hirq);
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index c93c33fc0..572b9826c 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -656,8 +656,8 @@ void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms)
 }
 
 //------------- Host Controller Driver's Interrupt Handler -------------//
-void hcd_int_handler(uint8_t rhport)
-{
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
   ehci_registers_t* regs = ehci_data.regs;
   uint32_t const int_status = regs->status;
 
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 02090df85..5312c2812 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -847,8 +847,10 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 /*-------------------------------------------------------------------
  * ISR
  *-------------------------------------------------------------------*/
-void hcd_int_handler(uint8_t rhport)
+void hcd_int_handler(uint8_t rhport, bool in_isr)
 {
+  (void) in_isr;
+
   uint_fast8_t is, txis, rxis;
 
   is   = USB0->IS;   /* read and clear interrupt status */
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 55327e02d..57684b259 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -447,6 +447,10 @@ void hcd_port_reset(uint8_t rhport)
   _hcd.need_reset = false;
 }
 
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;
@@ -583,8 +587,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 /*--------------------------------------------------------------------+
  * ISR
  *--------------------------------------------------------------------+*/
-void hcd_int_handler(uint8_t rhport)
+void hcd_int_handler(uint8_t rhport, bool in_isr)
 {
+  (void) in_isr;
   uint32_t is  = KHCI->ISTAT;
   uint32_t msk = KHCI->INTEN;
 
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 413e72037..f978b0965 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -667,8 +667,9 @@ static void done_queue_isr(uint8_t hostid)
   }
 }
 
-void hcd_int_handler(uint8_t hostid)
-{
+void hcd_int_handler(uint8_t hostid, bool in_isr) {
+  (void) in_isr;
+
   uint32_t const int_en     = OHCI_REG->interrupt_enable;
   uint32_t const int_status = OHCI_REG->interrupt_status & int_en;
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 21dc3f67d..4ed6d36bb 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -252,9 +252,9 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   }
 }
 
-void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
-{
+void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport, bool in_isr) {
   (void) rhport;
+  (void) in_isr;
   hcd_rp2040_irq();
 }
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 790cd6b32..bf95be707 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -771,8 +771,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 //--------------------------------------------------------------------+
 // ISR
 //--------------------------------------------------------------------+
-void hcd_int_handler(uint8_t rhport)
-{
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
+
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
   unsigned is0 = rusb->INTSTS0;
   unsigned is1 = rusb->INTSTS1;
diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c
index 3e3b91558..b073d6057 100644
--- a/src/portable/template/hcd_template.c
+++ b/src/portable/template/hcd_template.c
@@ -51,8 +51,9 @@ bool hcd_init(uint8_t rhport) {
 }
 
 // Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
   (void) rhport;
+  (void) in_isr;
 }
 
 // Enable USB interrupt
diff --git a/src/tusb.h b/src/tusb.h
index d6534ca28..c9d56d3c3 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -66,7 +66,7 @@
   #endif
 #else
   #ifndef tuh_int_handler
-  #define tuh_int_handler(_x)
+  #define tuh_int_handler(...)
   #endif
 #endif
 
@@ -123,7 +123,7 @@
   #endif
 #else
   #ifndef tud_int_handler
-  #define tud_int_handler(_x)
+  #define tud_int_handler(...)
   #endif
 #endif
 
-- 
cgit v1.3.1


From 277852afc1798f2acdb61917984e76b4bafa699e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Sep 2023 10:56:38 +0700
Subject: fix esp32 msc example

---
 examples/host/cdc_msc_hid_freertos/src/cdc_app.c |   8 +-
 examples/host/cdc_msc_hid_freertos/src/hid_app.c |   4 +
 examples/host/cdc_msc_hid_freertos/src/main.c    |  12 +-
 examples/host/cdc_msc_hid_freertos/src/msc_app.c |   8 +-
 src/class/msc/msc_host.c                         | 265 ++++++++++-------------
 src/class/msc/msc_host.h                         |   8 +-
 src/host/usbh.c                                  |  22 +-
 7 files changed, 151 insertions(+), 176 deletions(-)

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
index 943e534d8..91dcc2e1a 100644
--- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -31,9 +31,7 @@
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-
-//------------- IMPLEMENTATION -------------//
-
+// helper
 size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
   size_t count = 0;
   while (count < bufsize) {
@@ -47,6 +45,10 @@ size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
   return count;
 }
 
+void cdc_app_init(void) {
+  // nothing to do
+}
+
 void cdc_app_task(void* param) {
   (void) param;
 
diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
index a2df3b909..9ea5c1be0 100644
--- a/examples/host/cdc_msc_hid_freertos/src/hid_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
@@ -48,6 +48,10 @@ static void process_kbd_report(hid_keyboard_report_t const *report);
 static void process_mouse_report(hid_mouse_report_t const *report);
 static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len);
 
+void hid_app_init(void) {
+  // nothing to do
+}
+
 //--------------------------------------------------------------------+
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index 88e742ee2..b60be015b 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -82,10 +82,15 @@ StaticTask_t cdc_taskdef;
 TimerHandle_t blinky_tm;
 
 static void led_blinky_cb(TimerHandle_t xTimer);
-static void usb_host_task(void* param);
+extern void cdc_app_init(void);
+extern void hid_app_init(void);
+extern void msc_app_init(void);
 
+static void usb_host_task(void* param);
 extern void cdc_app_task(void* param);
 
+
+
 /*------------- MAIN -------------*/
 int main(void) {
   board_init();
@@ -131,6 +136,10 @@ static void usb_host_task(void *param) {
     board_init_after_tusb();
   }
 
+  cdc_app_init();
+  hid_app_init();
+  msc_app_init();
+
   // RTOS forever loop
   while (1) {
     // put this thread to waiting state until there is new events
@@ -154,7 +163,6 @@ void tuh_umount_cb(uint8_t dev_addr) {
   printf("A device with address %d is unmounted \r\n", dev_addr);
 }
 
-
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
index a8d6fbfaa..ee02ba917 100644
--- a/examples/host/cdc_msc_hid_freertos/src/msc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
@@ -25,10 +25,12 @@
 
 #include "tusb.h"
 
-#if CFG_TUH_MSC
-
 static scsi_inquiry_resp_t inquiry_resp;
 
+void msc_app_init(void) {
+  // nothing to do
+}
+
 bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
   msc_cbw_t const *cbw = cb_data->cbw;
   msc_csw_t const *csw = cb_data->csw;
@@ -63,5 +65,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr) {
   (void) dev_addr;
   printf("A MassStorage device is unmounted\r\n");
 }
-
-#endif
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index da264142c..39f2d9f1c 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -43,16 +43,14 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-enum
-{
+enum {
   MSC_STAGE_IDLE = 0,
   MSC_STAGE_CMD,
   MSC_STAGE_DATA,
   MSC_STAGE_STATUS,
 };
 
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
@@ -69,13 +67,13 @@ typedef struct
 
   //------------- SCSI -------------//
   uint8_t stage;
-  void*   buffer;
+  void* buffer;
   tuh_msc_complete_cb_t complete_cb;
   uintptr_t complete_arg;
 
   CFG_TUH_MEM_ALIGN msc_cbw_t cbw;
   CFG_TUH_MEM_ALIGN msc_csw_t csw;
-}msch_interface_t;
+} msch_interface_t;
 
 CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
 
@@ -86,40 +84,34 @@ static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
 
 // FIXME potential nul reference
 TU_ATTR_ALWAYS_INLINE
-static inline msch_interface_t* get_itf(uint8_t dev_addr)
-{
-  return &_msch_itf[dev_addr-1];
+static inline msch_interface_t* get_itf(uint8_t dev_addr) {
+  return &_msch_itf[dev_addr - 1];
 }
 
 //--------------------------------------------------------------------+
 // PUBLIC API
 //--------------------------------------------------------------------+
-uint8_t tuh_msc_get_maxlun(uint8_t dev_addr)
-{
+uint8_t tuh_msc_get_maxlun(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->max_lun;
 }
 
-uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun)
-{
+uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->capacity[lun].block_count;
 }
 
-uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun)
-{
+uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->capacity[lun].block_size;
 }
 
-bool tuh_msc_mounted(uint8_t dev_addr)
-{
+bool tuh_msc_mounted(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->mounted;
 }
 
-bool tuh_msc_ready(uint8_t dev_addr)
-{
+bool tuh_msc_ready(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out);
 }
@@ -127,20 +119,20 @@ bool tuh_msc_ready(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 // PUBLIC API: SCSI COMMAND
 //--------------------------------------------------------------------+
-static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun)
-{
+static inline void cbw_init(msc_cbw_t* cbw, uint8_t lun) {
   tu_memclr(cbw, sizeof(msc_cbw_t));
   cbw->signature = MSC_CBW_SIGNATURE;
   cbw->tag       = 0x54555342; // TUSB
   cbw->lun       = lun;
 }
 
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
-  msch_interface_t* p_msc = get_itf(dev_addr);
+bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data,
+                          tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
+  msch_interface_t* p_msc = get_itf(daddr);
   TU_VERIFY(p_msc->configured);
 
-  // TODO claim endpoint
+  // claim endpoint
+  TU_VERIFY(usbh_edpt_claim(daddr, p_msc->ep_out));
 
   p_msc->cbw = *cbw;
   p_msc->stage = MSC_STAGE_CMD;
@@ -148,15 +140,18 @@ bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tu
   p_msc->complete_cb = complete_cb;
   p_msc->complete_arg = arg;
 
-  TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)));
+  if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t))) {
+    usbh_edpt_release(daddr, p_msc->ep_out);
+    return false;
+  }
 
   return true;
 }
 
-bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
-   msch_interface_t* p_msc = get_itf(dev_addr);
-   TU_VERIFY(p_msc->configured);
+bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response,
+                           tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
+  msch_interface_t* p_msc = get_itf(dev_addr);
+  TU_VERIFY(p_msc->configured);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
@@ -169,8 +164,8 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r
   return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response,
+                     tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
@@ -181,18 +176,16 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons
   cbw.dir         = TUSB_DIR_IN_MASK;
   cbw.cmd_len     = sizeof(scsi_inquiry_t);
 
-  scsi_inquiry_t const cmd_inquiry =
-  {
-    .cmd_code     = SCSI_CMD_INQUIRY,
-    .alloc_length = sizeof(scsi_inquiry_resp_t)
+  scsi_inquiry_t const cmd_inquiry = {
+      .cmd_code     = SCSI_CMD_INQUIRY,
+      .alloc_length = sizeof(scsi_inquiry_resp_t)
   };
   memcpy(cbw.command, &cmd_inquiry, cbw.cmd_len);
 
   return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->configured);
 
@@ -200,16 +193,16 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
   cbw_init(&cbw, lun);
 
   cbw.total_bytes = 0;
-  cbw.dir         = TUSB_DIR_OUT;
-  cbw.cmd_len     = sizeof(scsi_test_unit_ready_t);
-  cbw.command[0]  = SCSI_CMD_TEST_UNIT_READY;
-  cbw.command[1]  = lun; // according to wiki TODO need verification
+  cbw.dir        = TUSB_DIR_OUT;
+  cbw.cmd_len    = sizeof(scsi_test_unit_ready_t);
+  cbw.command[0] = SCSI_CMD_TEST_UNIT_READY;
+  cbw.command[1] = lun; // according to wiki TODO need verification
 
   return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg);
 }
 
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void* response,
+                           tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
@@ -217,73 +210,64 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_ms
   cbw.dir         = TUSB_DIR_IN_MASK;
   cbw.cmd_len     = sizeof(scsi_request_sense_t);
 
-  scsi_request_sense_t const cmd_request_sense =
-  {
-    .cmd_code     = SCSI_CMD_REQUEST_SENSE,
-    .alloc_length = 18
+  scsi_request_sense_t const cmd_request_sense = {
+      .cmd_code     = SCSI_CMD_REQUEST_SENSE,
+      .alloc_length = 18
   };
-
   memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
 
   return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void* buffer, uint32_t lba, uint16_t block_count,
+                    tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
-  cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
-  cbw.dir         = TUSB_DIR_IN_MASK;
-  cbw.cmd_len     = sizeof(scsi_read10_t);
+  cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
+  cbw.dir = TUSB_DIR_IN_MASK;
+  cbw.cmd_len = sizeof(scsi_read10_t);
 
-  scsi_read10_t const cmd_read10 =
-  {
-    .cmd_code    = SCSI_CMD_READ_10,
-    .lba         = tu_htonl(lba),
-    .block_count = tu_htons(block_count)
+  scsi_read10_t const cmd_read10 = {
+      .cmd_code    = SCSI_CMD_READ_10,
+      .lba         = tu_htonl(lba),
+      .block_count = tu_htons(block_count)
   };
-
   memcpy(cbw.command, &cmd_read10, cbw.cmd_len);
 
   return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg);
 }
 
-bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const* buffer, uint32_t lba, uint16_t block_count,
+                     tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
-  cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
+  cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
   cbw.dir         = TUSB_DIR_OUT;
   cbw.cmd_len     = sizeof(scsi_write10_t);
 
-  scsi_write10_t const cmd_write10 =
-  {
-    .cmd_code    = SCSI_CMD_WRITE_10,
-    .lba         = tu_htonl(lba),
-    .block_count = tu_htons(block_count)
+  scsi_write10_t const cmd_write10 = {
+      .cmd_code    = SCSI_CMD_WRITE_10,
+      .lba         = tu_htonl(lba),
+      .block_count = tu_htons(block_count)
   };
-
   memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb, arg);
+  return tuh_msc_scsi_command(dev_addr, &cbw, (void*) (uintptr_t) buffer, complete_cb, arg);
 }
 
 #if 0
 // MSC interface Reset (not used now)
-bool tuh_msc_reset(uint8_t dev_addr)
-{
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
+bool tuh_msc_reset(uint8_t dev_addr) {
+  tusb_control_request_t const new_request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_OUT
@@ -300,79 +284,71 @@ bool tuh_msc_reset(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 // CLASS-USBH API
 //--------------------------------------------------------------------+
-void msch_init(void)
-{
+void msch_init(void) {
   tu_memclr(_msch_itf, sizeof(_msch_itf));
 }
 
-void msch_close(uint8_t dev_addr)
-{
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+void msch_close(uint8_t dev_addr) {
+  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,);
   msch_interface_t* p_msc = get_itf(dev_addr);
-  TU_VERIFY(p_msc->configured, );
+  TU_VERIFY(p_msc->configured,);
 
   TU_LOG_DRV("  MSCh close addr = %d\r\n", dev_addr);
 
   // invoke Application Callback
   if (p_msc->mounted) {
-    if(tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
+    if (tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
   }
 
   tu_memclr(p_msc, sizeof(msch_interface_t));
 }
 
-bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
+bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   msc_cbw_t const * cbw = &p_msc->cbw;
   msc_csw_t       * csw = &p_msc->csw;
 
-  switch (p_msc->stage)
-  {
+  switch (p_msc->stage) {
     case MSC_STAGE_CMD:
       // Must be Command Block
-      TU_ASSERT(ep_addr == p_msc->ep_out &&  event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
+      TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
 
-      if ( cbw->total_bytes && p_msc->buffer )
-      {
+      if (cbw->total_bytes && p_msc->buffer) {
         // Data stage if any
         p_msc->stage = MSC_STAGE_DATA;
-
         uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
         TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
-      }else
-      {
+      } else {
         // Status stage
         p_msc->stage = MSC_STAGE_STATUS;
         TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
       }
-    break;
+      break;
 
     case MSC_STAGE_DATA:
       // Status stage
       p_msc->stage = MSC_STAGE_STATUS;
       TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
-    break;
+      break;
 
     case MSC_STAGE_STATUS:
       // SCSI op is complete
       p_msc->stage = MSC_STAGE_IDLE;
 
-      if (p_msc->complete_cb)
-      {
-        tuh_msc_complete_data_t const cb_data =
-        {
-          .cbw = cbw,
-          .csw = csw,
-          .scsi_data = p_msc->buffer,
-          .user_arg = p_msc->complete_arg
+      if (p_msc->complete_cb) {
+        tuh_msc_complete_data_t const cb_data = {
+            .cbw = cbw,
+            .csw = csw,
+            .scsi_data = p_msc->buffer,
+            .user_arg = p_msc->complete_arg
         };
         p_msc->complete_cb(dev_addr, &cb_data);
       }
-    break;
+      break;
 
-    // unknown state
-    default: break;
+      // unknown state
+    default:
+      break;
   }
 
   return true;
@@ -381,39 +357,35 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 //--------------------------------------------------------------------+
 // MSC Enumeration
 //--------------------------------------------------------------------+
-
-static void config_get_maxlun_complete (tuh_xfer_t* xfer);
-static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data);
+static void config_get_maxlun_complete(tuh_xfer_t* xfer);
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 
-bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
-{
+bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) {
   (void) rhport;
   TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
-             MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
+             MSC_PROTOCOL_BOT == desc_itf->bInterfaceProtocol);
 
   // msc driver length is fixed
-  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
+  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) +
+                                       desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(drv_len <= max_len);
 
   msch_interface_t* p_msc = get_itf(dev_addr);
-  tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(desc_itf);
+  tusb_desc_endpoint_t const* ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(desc_itf);
 
-  for(uint32_t i=0; i<2; i++)
-  {
+  for (uint32_t i = 0; i < 2; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
     TU_ASSERT(tuh_edpt_open(dev_addr, ep_desc));
 
-    if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
-    {
+    if (TUSB_DIR_IN == tu_edpt_dir(ep_desc->bEndpointAddress)) {
       p_msc->ep_in = ep_desc->bEndpointAddress;
-    }else
-    {
+    } else {
       p_msc->ep_out = ep_desc->bEndpointAddress;
     }
 
-    ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(ep_desc);
+    ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(ep_desc);
   }
 
   p_msc->itf_num = desc_itf->bInterfaceNumber;
@@ -430,32 +402,31 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) {
   //------------- Get Max Lun -------------//
   TU_LOG_DRV("MSC Get Max Lun\r\n");
   tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = MSC_REQ_GET_MAX_LUN,
-    .wValue   = 0,
-    .wIndex   = itf_num,
-    .wLength  = 1
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
+      },
+      .bRequest = MSC_REQ_GET_MAX_LUN,
+      .wValue   = 0,
+      .wIndex   = itf_num,
+      .wLength  = 1
   };
 
   tuh_xfer_t xfer = {
-    .daddr       = dev_addr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = _msch_buffer,
-    .complete_cb = config_get_maxlun_complete,
-    .user_data    = 0
+      .daddr       = dev_addr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = _msch_buffer,
+      .complete_cb = config_get_maxlun_complete,
+      .user_data    = 0
   };
   TU_ASSERT(tuh_control_xfer(&xfer));
 
   return true;
 }
 
-static void config_get_maxlun_complete (tuh_xfer_t* xfer)
-{
+static void config_get_maxlun_complete(tuh_xfer_t* xfer) {
   uint8_t const daddr = xfer->daddr;
   msch_interface_t* p_msc = get_itf(daddr);
 
@@ -471,18 +442,16 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
 }
 
-static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
-{
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
   msc_cbw_t const* cbw = cb_data->cbw;
   msc_csw_t const* csw = cb_data->csw;
 
-  if (csw->status == 0)
-  {
+  if (csw->status == 0) {
     // Unit is ready, read its capacity
     TU_LOG_DRV("SCSI Read Capacity\r\n");
-    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0);
-  }else
-  {
+    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer),
+                          config_read_capacity_complete, 0);
+  } else {
     // Note: During enumeration, some device fails Test Unit Ready and require a few retries
     // with Request Sense to start working !!
     // TODO limit number of retries
@@ -493,8 +462,7 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d
   return true;
 }
 
-static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
-{
+static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
   msc_cbw_t const* cbw = cb_data->cbw;
   msc_csw_t const* csw = cb_data->csw;
 
@@ -503,8 +471,7 @@ static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_dat
   return true;
 }
 
-static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
-{
+static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
   msc_cbw_t const* cbw = cb_data->cbw;
   msc_csw_t const* csw = cb_data->csw;
 
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 6c0e5c9dd..9ca1b4703 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_MSC_HOST_H_
-#define _TUSB_MSC_HOST_H_
+#ifndef TUSB_MSC_HOST_H_
+#define TUSB_MSC_HOST_H_
 
 #include "msc.h"
 
@@ -73,7 +73,7 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun);
 // Perform a full SCSI command (cbw, data, csw) in non-blocking manner.
 // Complete callback is invoked when SCSI op is complete.
 // return true if success, false if there is already pending operation.
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
+bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Inquiry command
 // Complete callback is invoked when SCSI op is complete.
@@ -123,4 +123,4 @@ bool msch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, ui
  }
 #endif
 
-#endif /* _TUSB_MSC_HOST_H_ */
+#endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e332f35cc..8d75c9726 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -817,6 +817,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 }
 
 // Submit an transfer
+// TODO call usbh_edpt_release if failed
 bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
@@ -1713,19 +1714,16 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
   return true;
 }
 
-void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
-{
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
   usbh_device_t* dev = get_device(dev_addr);
 
-  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
-  {
+  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++) {
     // continue with next valid interface
     // IAD binding interface such as CDCs should return itf_num + 1 when complete
     // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
     usbh_class_driver_t const * driver = get_driver(drv_id);
-    if (driver)
-    {
+    if (driver) {
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
@@ -1733,23 +1731,19 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   }
 
   // all interface are configured
-  if (itf_num == CFG_TUH_INTERFACE_MAX)
-  {
+  if (itf_num == CFG_TUH_INTERFACE_MAX) {
     enum_full_complete();
 
-    if (is_hub_addr(dev_addr))
-    {
+    if (is_hub_addr(dev_addr)) {
       TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr);
-    }else
-    {
+    }else {
       // Invoke callback if available
       if (tuh_mount_cb) tuh_mount_cb(dev_addr);
     }
   }
 }
 
-static void enum_full_complete(void)
-{
+static void enum_full_complete(void) {
   // mark enumeration as complete
   _dev0.enumerating = 0;
 
-- 
cgit v1.3.1


From 6b8933cfe838b369c58d4fc9ced8aa5c9382a6d6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Sep 2023 12:55:59 +0700
Subject: fix build with new freertos host example

---
 examples/device/cdc_msc_freertos/Makefile          |   2 -
 examples/host/bare_api/Makefile                    |  10 -
 examples/host/cdc_msc_hid/Makefile                 |  10 -
 examples/host/cdc_msc_hid_freertos/Makefile        |  18 +-
 .../src/FreeRTOSConfig/FreeRTOSConfig.h            | 215 +++++++++++++++++++++
 examples/host/hid_controller/Makefile              |  10 -
 examples/host/msc_file_explorer/Makefile           |  10 -
 hw/bsp/lpc17/family.mk                             |   4 +-
 src/portable/analog/max3421/hcd_max3421.c          |   4 +-
 src/tinyusb.mk                                     |   7 +
 10 files changed, 237 insertions(+), 53 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h

(limited to 'src')

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 3ac62a79c..84c833fb5 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += lib/FreeRTOS-Kernel
-
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index 058307c40..161f8c774 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -10,14 +10,4 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 7c16b39d3..15b8a5b31 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -13,14 +13,4 @@ EXAMPLE_SOURCE = \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile
index 67bb6da55..a9670b4f2 100644
--- a/examples/host/cdc_msc_hid_freertos/Makefile
+++ b/examples/host/cdc_msc_hid_freertos/Makefile
@@ -5,6 +5,7 @@ FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
 
 INC += \
 	src \
+	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
 	$(TOP)/$(FREERTOS_PORTABLE_SRC) \
@@ -19,14 +20,15 @@ EXAMPLE_SOURCE = \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
+# FreeRTOS source, all files in port folder
 SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+	$(FREERTOS_SRC)/list.c \
+	$(FREERTOS_SRC)/queue.c \
+	$(FREERTOS_SRC)/tasks.c \
+	$(FREERTOS_SRC)/timers.c \
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
+
+SRC_S += \
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
 
 include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..a1fc8bb09
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,215 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+// Include MCU header
+#include "bsp/board_mcu.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+  #error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
+// TODO fix later
+// FIXME cause redundant-decls warnings
+#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
+  extern u32 SystemCoreClock;
+#else
+  extern uint32_t SystemCoreClock;
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU								        0
+#define configENABLE_FPU								        1
+#define configENABLE_TRUSTZONE					        0
+#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      0
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR					        INT_Excep_ICU_SWINT
+#define vTickISR								              INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				      (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			  1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
+
+#else
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+#if defined(__NVIC_PRIO_BITS)
+  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
+	#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+#elif defined(__ECLIC_INTCTLBITS)
+  // RISC-V Bumblebee core from nuclei
+  #define configPRIO_BITS       __ECLIC_INTCTLBITS
+
+#elif defined(__IASMARM__)
+  // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+  // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+  // IAR user must update this to correct value of the target MCU
+  #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+  #define configPRIO_BITS       2
+
+#else
+  #error "FreeRTOS configPRIO_BITS to be defined"
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index cda2977bc..e7f603f25 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -11,14 +11,4 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index 1fda72b18..8319d3c2b 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -24,14 +24,4 @@ SRC_C += \
 # suppress warning caused by fatfs
 CFLAGS += -Wno-error=cast-qual
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk
index abf6abe13..44b406d90 100644
--- a/hw/bsp/lpc17/family.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -22,6 +22,8 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
@@ -29,7 +31,7 @@ SRC_C += \
 	$(MCU_DIR)/src/iocon_17xx_40xx.c \
 	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
 	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c
+	$(MCU_DIR)/src/uart_17xx_40xx.c \
 
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 6613956de..77912a4c9 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -428,8 +428,8 @@ bool hcd_init(uint8_t rhport) {
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
   // V1 is 0x01, V2 is 0x12, V3 is 0x13
-  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
-  TU_LOG2_HEX(revision);
+//  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+//  TU_LOG2_HEX(revision);
 
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
diff --git a/src/tinyusb.mk b/src/tinyusb.mk
index 85052f90f..89ea0212c 100644
--- a/src/tinyusb.mk
+++ b/src/tinyusb.mk
@@ -17,3 +17,10 @@ TINYUSB_SRC_C += \
 	src/class/usbtmc/usbtmc_device.c \
 	src/class/video/video_device.c \
 	src/class/vendor/vendor_device.c \
+  src/host/usbh.c \
+  src/host/hub.c \
+  src/class/cdc/cdc_host.c \
+  src/class/hid/hid_host.c \
+  src/class/msc/msc_host.c \
+  src/class/vendor/vendor_host.c \
+  src/typec/usbc.c \
-- 
cgit v1.3.1


From 8348631bf538e2aa0a433ed6e7df9e42bb39bdd5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Sep 2023 16:15:31 +0700
Subject: improve esp32 ci, build esp32 with -DDMAX3421_HOST=1 for max3421
 testing revert change in hcd.h

---
 .github/workflows/build_esp.yml                    | 21 +-------
 .../espressif/boards/espressif_s3_devkitm/board.h  |  8 +++
 src/host/hcd.h                                     |  3 --
 tools/build_esp32.py                               | 63 ++++++++++++----------
 4 files changed, 45 insertions(+), 50 deletions(-)

(limited to 'src')

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 29585cb36..897616f09 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -29,12 +29,10 @@ jobs:
       fail-fast: false
       matrix:
         board:
-        # Alphabetical order
         # ESP32-S2
-        - 'espressif_saola_1'
+        - 'espressif_kaluga_1'
         # ESP32-S3
-        #- 'espressif_s3_devkitm'
-        # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy"
+        - 'espressif_s3_devkitm'
 
     steps:
     - name: Setup Python
@@ -48,20 +46,5 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
     - name: Build
       run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32.py ${{ matrix.board }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        # find -quit to only print linkermap of 1 board per example
-        for ex in `ls -d examples/device/*/`
-        do
-          find ${ex} -maxdepth 3 -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
-        done
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
index fe33b5c43..4b4151e72 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
@@ -36,6 +36,14 @@
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/host/hcd.h b/src/host/hcd.h
index edffb34cb..2bde289df 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -133,9 +133,6 @@ bool hcd_init(uint8_t rhport);
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport, bool in_isr);
 
-// Interrupt Hanndler (extended version)
-void hcd_int_handler_ext(uint8_t rhport, bool in_isr);
-
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport);
 
diff --git a/tools/build_esp32.py b/tools/build_esp32.py
index 00783bf58..1f73d3b22 100644
--- a/tools/build_esp32.py
+++ b/tools/build_esp32.py
@@ -17,8 +17,8 @@ exit_status = 0
 
 total_time = time.monotonic()
 
-build_format = '| {:23} | {:30} | {:18} | {:7} | {:6} | {:6} |'
-build_separator = '-' * 100
+build_format = '| {:30} | {:30} | {:18} | {:7} | {:6} | {:6} |'
+build_separator = '-' * 107
 
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
@@ -26,12 +26,9 @@ def filter_with_input(mylist):
         if len(input_args) > 0:
             mylist[:] = input_args
 
+
 # Build all examples if not specified
-all_examples = []
-for entry in os.scandir("examples/device"):
-    # Only includes example with CMakeLists.txt for esp32s, and skip board_test to speed up ci
-    if entry.is_dir() and os.path.exists(entry.path + "/sdkconfig.defaults") and entry.name != 'board_test':
-        all_examples.append(entry.name)
+all_examples = [entry.replace('examples/', '') for entry in glob.glob("examples/*/*_freertos")]
 filter_with_input(all_examples)
 all_examples.sort()
 
@@ -46,32 +43,41 @@ all_boards.sort()
 def build_board(example, board):
     global success_count, fail_count, skip_count, exit_status
     start_time = time.monotonic()
+
+    # Check if board is skipped
+    build_dir = f"cmake-build/cmake-build-{board}/{example}"
+
+    # Generate and build
+    r = subprocess.run(f"cmake examples/{example} -B {build_dir} -G \"Ninja\" -DBOARD={board} -DMAX3421_HOST=1",
+                       shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    if r.returncode == 0:
+        r = subprocess.run(f"cmake --build {build_dir}", shell=True, stdout=subprocess.PIPE,
+                           stderr=subprocess.STDOUT)
+    build_duration = time.monotonic() - start_time
     flash_size = "-"
     sram_size = "-"
 
-    # Check if board is skipped
-    if build_utils.skip_example(example, board):
-        success = SKIPPED
-        skip_count += 1
-        print(build_format.format(example, board, success, '-', flash_size, sram_size))
+    if r.returncode == 0:
+        success = SUCCEEDED
+        success_count += 1
+        #(flash_size, sram_size) = build_size(example, board)
     else:
-        subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        build_result = subprocess.run("make -j -C examples/device/{} BOARD={} all".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
-        if build_result.returncode == 0:
-            success = SUCCEEDED
-            success_count += 1
-            (flash_size, sram_size) = build_size(example, board)
-        else:
-            exit_status = build_result.returncode
-            success = FAILED
-            fail_count += 1
-
-        build_duration = time.monotonic() - start_time
-        print(build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size))
+        exit_status = r.returncode
+        success = FAILED
+        fail_count += 1
+
+    title = build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size)
+    if os.getenv('CI'):
+        # always print build output if in CI
+        print(f"::group::{title}")
+        print(r.stdout.decode("utf-8"))
+        print(f"::endgroup::")
+    else:
+        # print build output if failed
+        print(title)
+        if r.returncode != 0:
+            print(r.stdout.decode("utf-8"))
 
-        if build_result.returncode != 0:
-            print(build_result.stdout.decode("utf-8"))
 
 def build_size(example, board):
     #elf_file = 'examples/device/{}/_build/{}/{}-firmware.elf'.format(example, board, board)
@@ -82,6 +88,7 @@ def build_size(example, board):
     sram_size = int(size_list[1]) + int(size_list[2])
     return (flash_size, sram_size)
 
+
 print(build_separator)
 print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
 print(build_separator)
-- 
cgit v1.3.1


From 67e34267a68c81f62ff315ac990f07a60f4dc93c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 4 Oct 2023 18:00:32 +0700
Subject: change tuh_max3421_spi_xfer_api() signature

tested working with sam d21 and d51, not tested with nrf52, seem not
working with esp32
---
 hw/bsp/espressif/boards/family.c          | 39 +++++++++++++++++++------------
 hw/bsp/nrf/family.c                       | 20 ++++++++++------
 hw/bsp/samd21/family.c                    | 27 +++++++++++----------
 hw/bsp/samd51/family.c                    | 35 +++++++++++++++------------
 src/portable/analog/max3421/hcd_max3421.c | 27 ++++++++++++---------
 5 files changed, 88 insertions(+), 60 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index c6a592627..912ca5f35 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -38,7 +38,9 @@
 #if ESP_IDF_VERSION_MAJOR > 4
   #include "esp_private/periph_ctrl.h"
 #else
+
   #include "driver/periph_ctrl.h"
+
 #endif
 
 // Note; current code use UART0 can cause device to reset while monitoring
@@ -46,16 +48,21 @@
 #define UART_ID  UART_NUM_0
 
 #ifdef NEOPIXEL_PIN
+
 #include "led_strip.h"
-static led_strip_t *strip;
+
+static led_strip_t* strip;
 #endif
 
 #if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+
 #include "driver/spi_master.h"
+
 static void max3421_init(void);
+
 #endif
 
-static void configure_pins(usb_hal_context_t *usb);
+static void configure_pins(usb_hal_context_t* usb);
 
 //--------------------------------------------------------------------+
 // Implementation
@@ -115,11 +122,11 @@ void board_init(void) {
 #endif
 }
 
-static void configure_pins(usb_hal_context_t *usb) {
+static void configure_pins(usb_hal_context_t* usb) {
   /* usb_periph_iopins currently configures USB_OTG as USB Device.
    * Introduce additional parameters in usb_hal_context_t when adding support
    * for USB Host. */
-  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
+  for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
     if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
       esp_rom_gpio_pad_select_gpio(iopin->pin);
       if (iopin->is_output) {
@@ -160,7 +167,7 @@ uint32_t board_button_read(void) {
 }
 
 // Get characters from UART
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
 #if USE_UART
   return uart_read_bytes(UART_ID, buf, len, 0);
 #else
@@ -169,7 +176,7 @@ int board_uart_read(uint8_t *buf, int len) {
 }
 
 // Send characters to UART
-int board_uart_write(void const *buf, int len) {
+int board_uart_write(void const* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
@@ -216,7 +223,7 @@ static void max3421_init(void) {
   gpio_set_level(MAX3421_CS_PIN, 1);
 
   // SPI
-  spi_bus_config_t buscfg={
+  spi_bus_config_t buscfg = {
       .miso_io_num = MAX3421_MISO_PIN,
       .mosi_io_num = MAX3421_MOSI_PIN,
       .sclk_io_num = MAX3421_SCK_PIN,
@@ -228,7 +235,7 @@ static void max3421_init(void) {
       .data7_io_num = -1,
       .max_transfer_sz = 1024
   };
-  ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) );
+  ESP_ERROR_CHECK(spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
 
   spi_device_interface_config_t max3421_cfg = {
       .mode = 0,
@@ -236,7 +243,7 @@ static void max3421_init(void) {
       .spics_io_num = -1, // manual control CS
       .queue_size = 1
   };
-  ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) );
+  ESP_ERROR_CHECK(spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi));
 
   // debug
   gpio_set_direction(13, GPIO_MODE_OUTPUT);
@@ -244,7 +251,7 @@ static void max3421_init(void) {
 
   // Interrupt pin
   max3421_intr_sem = xSemaphoreCreateBinary();
-  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-2, NULL);
+  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES - 2, NULL);
 
   gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
   gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
@@ -267,18 +274,20 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
-  if (tx_len == 0) {
+  if (tx_buf == NULL) {
     // fifo read, transmit rx_buf as dummy
     tx_buf = rx_buf;
-    tx_len = rx_len;
   }
 
+  // length in bits
+  size_t const len_bits = xfer_bytes << 3;
+
   spi_transaction_t xact = {
-      .length = tx_len << 3, // length in bits
-      .rxlength = rx_len << 3, // length in bits
+      .length = len_bits,
+      .rxlength = rx_buf ? len_bits : 0,
       .tx_buffer = tx_buf,
       .rx_buffer = rx_buf
   };
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 631f53fcd..c431389f3 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -95,7 +95,9 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 
 //------------- Host using MAX2341E -------------//
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
 static void max3421_init(void);
+
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 #endif
 
@@ -203,15 +205,15 @@ uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
 //  return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
 }
 
-int board_uart_write(void const *buf, int len) {
-  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0;
+int board_uart_write(void const* buf, int len) {
+  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -323,6 +325,7 @@ static void max3421_init(void) {
   nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
 }
 
+// API to enable/disable MAX3421 INTR pin interrupt
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
@@ -335,22 +338,25 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   }
 }
 
+// API to control MAX3421 SPI CS
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
   nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
   nrfx_spim_xfer_desc_t xfer = {
       .p_tx_buffer = tx_buf,
-      .tx_length   = tx_len,
+      .tx_length   = tx_buf ? xfer_bytes : 0,
       .p_rx_buffer = rx_buf,
-      .rx_length   = rx_len,
+      .rx_length   = rx_buf ? xfer_bytes : 0,
   };
 
-  return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
+  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
 }
 
 #endif
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index b9365fc3f..ccb2c99b1 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -72,6 +72,7 @@ static void uart_init(void);
 #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
 
 static void max3421_init(void);
+
 #endif
 
 void board_init(void) {
@@ -237,13 +238,13 @@ int board_uart_write(void const * buf, int len)
 static void uart_init(void) {
 }
 
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
 }
 
-int board_uart_write(void const *buf, int len) {
+int board_uart_write(void const* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
@@ -261,6 +262,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
 //--------------------------------------------------------------------+
@@ -278,8 +280,8 @@ static void max3421_init(void) {
 
   // Configure GCLK for SERCOM
 //  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM4_CORE | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
-  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val+MAX3421_SERCOM_ID) |
-      GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val + MAX3421_SERCOM_ID) |
+                      GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
   while (GCLK->STATUS.bit.SYNCBUSY);
 
   Sercom* sercom = MAX3421_SERCOM;
@@ -293,7 +295,7 @@ static void max3421_init(void) {
 
   // Set up SPI in master mode, MSB first, SPI mode 0
   sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
-      SERCOM_SPI_CTRLA_MODE(3);
+                          SERCOM_SPI_CTRLA_MODE(3);
 
   sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
   while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
@@ -366,6 +368,7 @@ void EIC_Handler(void) {
   tuh_int_handler(1, true);
 }
 
+// API to enable/disable MAX3421 INTR pin interrupt
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
@@ -376,24 +379,26 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   }
 }
 
+// API to control MAX3421 SPI CS
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
   gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
   Sercom* sercom = MAX3421_SERCOM;
 
-  size_t count = 0;
-  while (count < tx_len || count < rx_len) {
+  for (size_t count = 0; count < xfer_bytes; count++) {
     // Wait for the transmit buffer to be empty
     while (!sercom->SPI.INTFLAG.bit.DRE);
 
     // Write data to be transmitted
     uint8_t data = 0x00;
-    if (count < tx_len) {
+    if (tx_buf) {
       data = tx_buf[count];
     }
 
@@ -404,11 +409,9 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 
     // Read received data
     data = (uint8_t) sercom->SPI.DATA.reg;
-    if (count < rx_len) {
+    if (rx_buf) {
       rx_buf[count] = data;
     }
-
-    count++;
   }
 
   // wait for bus idle and clear flags
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 4d43c7745..bca18e1a2 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -81,6 +81,7 @@ void USB_3_Handler(void) {
 #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler)
 
 static void max3421_init(void);
+
 #endif
 
 void board_init(void) {
@@ -153,13 +154,13 @@ uint32_t board_button_read(void) {
   return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
 }
 
-int board_uart_write(void const *buf, int len) {
+int board_uart_write(void const* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
@@ -175,6 +176,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
 //--------------------------------------------------------------------+
@@ -189,7 +191,7 @@ static void max3421_init(void) {
   uint32_t const baudrate = 12000000u;
 
   struct {
-    volatile uint32_t *mck_apb;
+    volatile uint32_t* mck_apb;
     uint32_t mask;
     uint8_t gclk_id_core;
     uint8_t gclk_id_slow;
@@ -214,8 +216,10 @@ static void max3421_init(void) {
   *sercom_clock[MAX3421_SERCOM_ID].mck_apb |= sercom_clock[MAX3421_SERCOM_ID].mask;
 
   // Configure GCLK for SERCOM
-  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg =
+      GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg =
+      GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
 
   // Disable the SPI module
   sercom->SPI.CTRLA.bit.ENABLE = 0;
@@ -226,7 +230,7 @@ static void max3421_init(void) {
 
   // Set up SPI in master mode, MSB first, SPI mode 0
   sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
-      SERCOM_SPI_CTRLA_MODE(3);
+                          SERCOM_SPI_CTRLA_MODE(3);
 
   sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
   while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
@@ -278,9 +282,9 @@ static void max3421_init(void) {
   while (EIC->SYNCBUSY.bit.ENABLE);
 
   // Configure EIC to trigger on falling edge
-  volatile uint32_t * eic_config;
+  volatile uint32_t* eic_config;
   uint8_t sense_shift;
-  if ( MAX3421_INTR_EIC_ID < 8 ) {
+  if (MAX3421_INTR_EIC_ID < 8) {
     eic_config = &EIC->CONFIG[0].reg;
     sense_shift = MAX3421_INTR_EIC_ID * 4;
   } else {
@@ -312,6 +316,7 @@ void MAX3421_EIC_Handler(void) {
   tuh_int_handler(1, true);
 }
 
+// API to enable/disable MAX3421 INTR pin interrupt
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
@@ -323,24 +328,26 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   }
 }
 
+// API to control MAX3421 SPI CS
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
   gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
   Sercom* sercom = MAX3421_SERCOM;
 
-  size_t count = 0;
-  while (count < tx_len || count < rx_len) {
+  for (size_t count = 0; count < xfer_bytes; count++) {
     // Wait for the transmit buffer to be empty
     while (!sercom->SPI.INTFLAG.bit.DRE);
 
     // Write data to be transmitted
     uint8_t data = 0x00;
-    if (count < tx_len) {
+    if (tx_buf) {
       data = tx_buf[count];
     }
 
@@ -351,11 +358,9 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 
     // Read received data
     data = (uint8_t) sercom->SPI.DATA.reg;
-    if (count < rx_len) {
+    if (rx_buf) {
       rx_buf[count] = data;
     }
-
-    count++;
   }
 
   // wait for bus idle and clear flags
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 77912a4c9..787c1e511 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -210,16 +210,21 @@ static max3421_data_t _hcd_data;
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
 
-void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
-void tuh_max3421_int_api(uint8_t rhport, bool enabled);
+// API to control MAX3421 SPI CS
+extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 
-static void handle_connect_irq(uint8_t rhport, bool in_isr);
-static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes);
+
+// API to enable/disable MAX3421 INTR pin interrupt
+extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
 
 //--------------------------------------------------------------------+
 // SPI Helper
 //--------------------------------------------------------------------+
+static void handle_connect_irq(uint8_t rhport, bool in_isr);
+static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
 
 static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
@@ -249,9 +254,9 @@ static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
   _hcd_data.hirq = hirq;
-  tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
+  tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
 
   max3421_spi_unlock(rhport, in_isr);
 
@@ -263,9 +268,9 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
   _hcd_data.hirq = hirq;
-  tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
+  tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
 
   max3421_spi_unlock(rhport, in_isr);
 }
@@ -276,7 +281,7 @@ static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
 
   max3421_spi_unlock(rhport, in_isr);
 
@@ -290,7 +295,7 @@ static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
 
   max3421_spi_lock(rhport, in_isr);
 
-  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
 
   max3421_spi_unlock(rhport, in_isr);
 
-- 
cgit v1.3.1


From ce627f431831e1fbaa3bb7bad35a489b8006b749 Mon Sep 17 00:00:00 2001
From: "denis.krasutski" <denis.krasutski>
Date: Fri, 6 Oct 2023 13:04:54 +0300
Subject: feat(ch32f20x): add support of ch32f20x

---
 .gitignore                                   |    1 +
 README.rst                                   |    2 +-
 docs/reference/dependencies.rst              |    1 +
 docs/reference/supported.rst                 |    5 +-
 hw/bsp/board_mcu.h                           |    3 +
 hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h  |   59 ++
 hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk |    7 +
 hw/bsp/ch32f20x/ch32f205.ld                  |  111 +++
 hw/bsp/ch32f20x/ch32f20x_conf.h              |   40 +
 hw/bsp/ch32f20x/ch32f20x_it.c                |   35 +
 hw/bsp/ch32f20x/ch32f20x_it.h                |   25 +
 hw/bsp/ch32f20x/core_cm3.h                   |   11 +
 hw/bsp/ch32f20x/debug_uart.c                 |  105 +++
 hw/bsp/ch32f20x/debug_uart.h                 |   31 +
 hw/bsp/ch32f20x/family.c                     |  141 ++++
 hw/bsp/ch32f20x/family.mk                    |   30 +
 hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s   |  493 +++++++++++
 hw/bsp/ch32f20x/system_ch32f20x.c            | 1122 ++++++++++++++++++++++++++
 hw/bsp/ch32f20x/system_ch32f20x.h            |   28 +
 hw/bsp/ch32v307/family.mk                    |    2 +-
 src/common/tusb_mcu.h                        |    4 +
 src/portable/wch/ch32_usbhs_reg.h            |  349 ++++++++
 src/portable/wch/ch32v307/ch32_usbhs_reg.h   |  345 --------
 src/portable/wch/ch32v307/dcd_usbhs.c        |  391 ---------
 src/portable/wch/dcd_ch32_usbhs.c            |  391 +++++++++
 src/tusb_option.h                            |    1 +
 tools/get_deps.py                            |    3 +
 tools/iar_template.ipcf                      |    4 +-
 28 files changed, 2999 insertions(+), 741 deletions(-)
 create mode 100644 hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h
 create mode 100644 hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk
 create mode 100644 hw/bsp/ch32f20x/ch32f205.ld
 create mode 100644 hw/bsp/ch32f20x/ch32f20x_conf.h
 create mode 100644 hw/bsp/ch32f20x/ch32f20x_it.c
 create mode 100644 hw/bsp/ch32f20x/ch32f20x_it.h
 create mode 100644 hw/bsp/ch32f20x/core_cm3.h
 create mode 100644 hw/bsp/ch32f20x/debug_uart.c
 create mode 100644 hw/bsp/ch32f20x/debug_uart.h
 create mode 100644 hw/bsp/ch32f20x/family.c
 create mode 100644 hw/bsp/ch32f20x/family.mk
 create mode 100644 hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s
 create mode 100644 hw/bsp/ch32f20x/system_ch32f20x.c
 create mode 100644 hw/bsp/ch32f20x/system_ch32f20x.h
 create mode 100644 src/portable/wch/ch32_usbhs_reg.h
 delete mode 100644 src/portable/wch/ch32v307/ch32_usbhs_reg.h
 delete mode 100644 src/portable/wch/ch32v307/dcd_usbhs.c
 create mode 100644 src/portable/wch/dcd_ch32_usbhs.c

(limited to 'src')

diff --git a/.gitignore b/.gitignore
index c665d6c73..e6ccec736 100644
--- a/.gitignore
+++ b/.gitignore
@@ -81,6 +81,7 @@ hw/mcu/st/stm32u5xx_hal_driver
 hw/mcu/st/stm32wbxx_hal_driver
 hw/mcu/ti
 hw/mcu/wch/ch32v307
+hw/mcu/wch/ch32f20x
 lib/CMSIS_5
 lib/FreeRTOS-Kernel
 lib/lwip
diff --git a/README.rst b/README.rst
index aef310b98..919596e67 100644
--- a/README.rst
+++ b/README.rst
@@ -60,7 +60,7 @@ The stack supports the following MCUs:
 - **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G0, G4, L0, L1, L4, L4+, WB
 - **TI:** MSP430, MSP432E4, TM4C123
 - **ValentyUSB:** eptri
-- **WCH:** CH32V307
+- **WCH:** CH32V307, CH32F20x
 
 Here is the list of `Supported Devices`_ that can be used with provided examples.
 
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
index 130527e2c..d532a3a1e 100644
--- a/docs/reference/dependencies.rst
+++ b/docs/reference/dependencies.rst
@@ -56,6 +56,7 @@ hw/mcu/st/stm32u5xx_hal_driver            https://github.com/STMicroelectronics/
 hw/mcu/st/stm32wbxx_hal_driver            https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git  2c5f06638be516c1b772f768456ba637f077bac8
 hw/mcu/ti                                 https://github.com/hathach/ti_driver.git                        143ed6cc20a7615d042b03b21e070197d473e6e5
 hw/mcu/wch/ch32v307                       https://github.com/openwch/ch32v307.git                         17761f5cf9dbbf2dcf665b7c04934188add20082
+hw/mcu/wch/ch32f20x                       https://github.com/openwch/ch32f20x.git                         77c4095087e5ed2c548ec9058e655d0b8757663b
 lib/CMSIS_5                               https://github.com/ARM-software/CMSIS_5.git                     20285262657d1b482d132d20d755c8c330d55c1f
 lib/FreeRTOS-Kernel                       https://github.com/FreeRTOS/FreeRTOS-Kernel.git                 def7d2df2b0506d3d249334974f51e427c17a41c
 lib/lwip                                  https://github.com/lwip-tcpip/lwip.git                          159e31b689577dbf69cf0683bbaffbd71fa5ee10
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index aed64782c..8843dd405 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -109,6 +109,8 @@ Supported MCUs
 | ValentyUSB   | eptri                 | ✔      | ✖    | ✖         | eptri             |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 | WCH          | CH32V307              | ✔      |      | ✔         | ch32v307          |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | CH32F20x              | ✔      |      | ✔         | ch32f205          |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 
 
@@ -415,4 +417,5 @@ Tomu
 WCH
 ---
 
-- `CH32V307V-R1-1v0 <https://lcsc.com/product-detail/Development-Boards-Kits_WCH-Jiangsu-Qin-Heng-CH32V307V-EVT-R1_C2943980.html>`
+-  `CH32V307V-R1-1v0 <https://lcsc.com/product-detail/Development-Boards-Kits_WCH-Jiangsu-Qin-Heng-CH32V307V-EVT-R1_C2943980.html>`__
+-  `CH32F205R-R0-1v0 <https://github.com/openwch/ch32f20x/blob/main/EVT/PUB/CH32F20x%20Evaluation%20Board%20Reference-EN.pdf>`__
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index e5d2bb608..4ce5c4139 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -161,6 +161,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_TM4C123
   #include "TM4C123.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X
+  #include "ch32f20x.h"
+
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   // no header needed
 
diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h
new file mode 100644
index 000000000..d5849bddb
--- /dev/null
+++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h
@@ -0,0 +1,59 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED: need to wire pin LED1 to PC0 in the P1 header
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_Pin_1
+#define LED_STATE_ON          0
+#define LED_CLOCK_EN()        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// Button: need to wire pin KEY to PC1 in the P1 header
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_Pin_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_CLOCK_EN()     RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// UART
+#define UART_DEV              USART2
+#define UART_DEV_IRQn         USART2_IRQn
+#define UART_DEV_IRQHandler   USART2_IRQHandler
+#define UART_DEV_GPIO_PORT    GPIOA
+#define UART_DEV_TX_PIN       GPIO_Pin_2
+#define UART_DEV_CLK_EN()     do {                                                      \
+                                RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);   \
+                                RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);  \
+                              } while(0)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk
new file mode 100644
index 000000000..f0e9bf30f
--- /dev/null
+++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.mk
@@ -0,0 +1,7 @@
+LD_FILE = $(FAMILY_PATH)/ch32f205.ld
+
+SRC_S += \
+	$(FAMILY_PATH)/startup_gcc_ch32f20x_d8c.s
+
+CFLAGS += \
+	-DCH32F20x_D8C
diff --git a/hw/bsp/ch32f20x/ch32f205.ld b/hw/bsp/ch32f20x/ch32f205.ld
new file mode 100644
index 000000000..7c8d04cc5
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f205.ld
@@ -0,0 +1,111 @@
+ENTRY(Reset_Handler)
+
+_Min_Heap_Size = 0x200;
+_Min_Stack_Size = 0x400;
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+SECTIONS
+{
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))
+    . = ALIGN(4);
+  } >FLASH
+
+  .text :
+  {
+    . = ALIGN(4);
+    _stext = .;
+    *(.text)
+    *(.text*)
+    *(.glue_7)
+    *(.glue_7t)
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+    _etext = .;
+  } >FLASH
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)
+    *(.rodata*)
+    . = ALIGN(4);
+  } >FLASH
+  .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+  _sidata = LOADADDR(.data);
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;
+    *(.data)
+    *(.data*)
+    . = ALIGN(4);
+    _edata = .;
+  } >RAM AT> FLASH
+  . = ALIGN(4);
+  .bss :
+  {
+    _sbss = .;
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    _ebss = .;
+    __bss_end__ = _ebss;
+  } >RAM
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    __HeapStart = .;
+    . = . + _Min_Heap_Size;
+    __HeapEnd = .;
+    __StackLimit = .;
+    . = . + _Min_Stack_Size;
+    __StackTop = .;
+    . = ALIGN(4);
+  } >RAM
+_estack = __StackTop;
+_sstack = __StackLimit;
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/ch32f20x/ch32f20x_conf.h b/hw/bsp/ch32f20x/ch32f20x_conf.h
new file mode 100644
index 000000000..f94da5dec
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_conf.h
@@ -0,0 +1,40 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32f20x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2021/08/08
+ * Description        : Library configuration file.
+ *********************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * Attention: This software (modified or not) and binary are used for
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
+ *******************************************************************************/
+#ifndef __CH32F20x_CONF_H
+#define __CH32F20x_CONF_H
+
+#include "ch32f20x_adc.h"
+#include "ch32f20x_bkp.h"
+#include "ch32f20x_can.h"
+#include "ch32f20x_crc.h"
+#include "ch32f20x_dac.h"
+#include "ch32f20x_dbgmcu.h"
+#include "ch32f20x_dma.h"
+#include "ch32f20x_exti.h"
+#include "ch32f20x_flash.h"
+#include "ch32f20x_fsmc.h"
+#include "ch32f20x_gpio.h"
+#include "ch32f20x_i2c.h"
+#include "ch32f20x_iwdg.h"
+#include "ch32f20x_pwr.h"
+#include "ch32f20x_rcc.h"
+#include "ch32f20x_rtc.h"
+#include "ch32f20x_sdio.h"
+#include "ch32f20x_spi.h"
+#include "ch32f20x_tim.h"
+#include "ch32f20x_usart.h"
+#include "ch32f20x_wwdg.h"
+#include "ch32f20x_it.h"
+#include "ch32f20x_misc.h"
+
+#endif /* __CH32F20x_CONF_H */
+
diff --git a/hw/bsp/ch32f20x/ch32f20x_it.c b/hw/bsp/ch32f20x/ch32f20x_it.c
new file mode 100644
index 000000000..94e28e380
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_it.c
@@ -0,0 +1,35 @@
+#include "ch32f20x_it.h"
+
+#include "ch32f20x.h"
+
+/* -------------------------------------------------------------------------- */
+
+void NMI_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void MemManage_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void BusFault_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void UsageFault_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
+
+void DebugMon_Handler(void) {
+
+}
+
+/* -------------------------------------------------------------------------- */
diff --git a/hw/bsp/ch32f20x/ch32f20x_it.h b/hw/bsp/ch32f20x/ch32f20x_it.h
new file mode 100644
index 000000000..34f3bbf96
--- /dev/null
+++ b/hw/bsp/ch32f20x/ch32f20x_it.h
@@ -0,0 +1,25 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32f20x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/08/08
+* Description        : This file contains the headers of the interrupt handlers.
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#ifndef __CH32F20xIT_H
+#define __CH32F20xIT_H
+
+#include "ch32f20x.h"
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void DebugMon_Handler(void);
+
+
+#endif /* __CH32F20xIT_H */
diff --git a/hw/bsp/ch32f20x/core_cm3.h b/hw/bsp/ch32f20x/core_cm3.h
new file mode 100644
index 000000000..c35a4eec3
--- /dev/null
+++ b/hw/bsp/ch32f20x/core_cm3.h
@@ -0,0 +1,11 @@
+/* There is core_cm3.h wrapper just to avoid warnings from CMSIS headers */
+/* if you want use original file add to make file:
+    INC += \
+        $(TOP)/$(CH32F20X_SDK_SRC)/CMSIS
+*/
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+
+#include <../../CMSIS/core_cm3.h>
+
+#pragma GCC diagnostic pop
diff --git a/hw/bsp/ch32f20x/debug_uart.c b/hw/bsp/ch32f20x/debug_uart.c
new file mode 100644
index 000000000..a595eb6f7
--- /dev/null
+++ b/hw/bsp/ch32f20x/debug_uart.c
@@ -0,0 +1,105 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#include <ch32f20x.h>
+
+#include "board.h"
+#include "debug_uart.h"
+
+#define UART_RINGBUFFER_SIZE_TX 64
+#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
+
+static char tx_buf[UART_RINGBUFFER_SIZE_TX];
+static unsigned int tx_produce = 0;
+static volatile unsigned int tx_consume = 0;
+
+void UART_DEV_IRQHandler(void)
+{
+  if(USART_GetITStatus(UART_DEV, USART_IT_TC) != RESET) {
+    USART_ClearITPendingBit(UART_DEV, USART_IT_TC);
+
+    if(tx_consume != tx_produce) {
+      USART_SendData(UART_DEV, tx_buf[tx_consume]);
+      tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
+    }
+  }
+}
+
+void uart_write(char c)
+{
+  unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
+
+  NVIC_DisableIRQ(UART_DEV_IRQn);
+  if((tx_consume != tx_produce) || (USART_GetFlagStatus(UART_DEV, USART_FLAG_TXE) == RESET)) {
+    tx_buf[tx_produce] = c;
+    tx_produce = tx_produce_next;
+  } else {
+    USART_SendData(UART_DEV, c);
+  }
+  NVIC_EnableIRQ(UART_DEV_IRQn);
+}
+
+void uart_sync(void)
+{
+  while(tx_consume != tx_produce) {
+    //Waiting for transfer complete
+  }
+}
+
+void usart_printf_init(uint32_t baudrate)
+{
+  tx_produce = 0;
+  tx_consume = 0;
+
+  UART_DEV_CLK_EN();
+
+  GPIO_InitTypeDef gpio_config = {
+    .GPIO_Pin = UART_DEV_TX_PIN,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+    .GPIO_Mode = GPIO_Mode_AF_PP,
+  };
+  GPIO_Init(UART_DEV_GPIO_PORT, &gpio_config);
+
+  USART_InitTypeDef uart_config = {
+    .USART_BaudRate = baudrate,
+    .USART_WordLength = USART_WordLength_8b,
+    .USART_StopBits = USART_StopBits_1,
+    .USART_Parity = USART_Parity_No,
+    .USART_HardwareFlowControl = USART_HardwareFlowControl_None,
+    .USART_Mode = USART_Mode_Tx,
+  };
+
+  USART_Init(UART_DEV, &uart_config);
+  USART_ITConfig(UART_DEV, USART_IT_TC, ENABLE);
+  USART_Cmd(UART_DEV, ENABLE);
+
+  NVIC_InitTypeDef nvic_config = {
+    .NVIC_IRQChannel = UART_DEV_IRQn,
+    .NVIC_IRQChannelPreemptionPriority = 1,
+    .NVIC_IRQChannelSubPriority = 3,
+    .NVIC_IRQChannelCmd = ENABLE,
+  };
+  NVIC_Init(&nvic_config);
+}
diff --git a/hw/bsp/ch32f20x/debug_uart.h b/hw/bsp/ch32f20x/debug_uart.h
new file mode 100644
index 000000000..10284cf6f
--- /dev/null
+++ b/hw/bsp/ch32f20x/debug_uart.h
@@ -0,0 +1,31 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+
+void uart_write(char c);
+void uart_sync(void);
+void usart_printf_init(uint32_t baudrate);
diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c
new file mode 100644
index 000000000..9717832d6
--- /dev/null
+++ b/hw/bsp/ch32f20x/family.c
@@ -0,0 +1,141 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Denis Krasutski
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stdio.h"
+#include "debug_uart.h"
+
+#include "ch32f20x.h"
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+void USBHS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void board_init(void) {
+
+  /* Disable interrupts during init */
+  __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USBHS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+	usart_printf_init(115200);
+
+  // USB HS Clock config
+  RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
+  RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
+  RCC_USBHSConfig(RCC_USBPLL_Div2);
+  RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
+  RCC_USBHSPHYPLLALIVEcmd(ENABLE);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
+
+  // LED
+  LED_CLOCK_EN();
+  GPIO_InitTypeDef led_pin_config = {
+    .GPIO_Pin = LED_PIN,
+    .GPIO_Mode = GPIO_Mode_Out_OD,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(LED_PORT, &led_pin_config);
+
+  // Button
+  BUTTON_CLOCK_EN();
+  GPIO_InitTypeDef button_pin_config = {
+    .GPIO_Pin = BUTTON_PIN,
+    .GPIO_Mode = GPIO_Mode_IPU,
+    .GPIO_Speed = GPIO_Speed_50MHz,
+  };
+  GPIO_Init(BUTTON_PORT, &button_pin_config);
+
+  /* Enable interrupts globally */
+  __enable_irq();
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+
+#endif
+
+void HardFault_Handler(void)
+{
+  __asm("BKPT #0\n");
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_WriteBit(LED_PORT, LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  int txsize = len;
+  while ( txsize-- )
+  {
+    uart_write(*(uint8_t const*) buf);
+    buf++;
+  }
+  return len;
+}
diff --git a/hw/bsp/ch32f20x/family.mk b/hw/bsp/ch32f20x/family.mk
new file mode 100644
index 000000000..c08451b9c
--- /dev/null
+++ b/hw/bsp/ch32f20x/family.mk
@@ -0,0 +1,30 @@
+# Submodules
+CH32F20X_SDK = hw/mcu/wch/ch32f20x
+DEPS_SUBMODULES += $(CH32F20X_SDK)
+
+# WCH-SDK paths
+CH32F20X_SDK_SRC = $(CH32F20X_SDK)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m3
+
+CFLAGS += \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32F20X \
+	-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+
+SRC_C += \
+	src/portable/wch/dcd_ch32_usbhs.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_gpio.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_misc.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_rcc.c \
+	$(CH32F20X_SDK_SRC)/StdPeriphDriver/src/ch32f20x_usart.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(CH32F20X_SDK_SRC)/StdPeriphDriver/inc
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
+
+flash: flash-stlink
diff --git a/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s
new file mode 100644
index 000000000..2ecac2ac1
--- /dev/null
+++ b/hw/bsp/ch32f20x/startup_gcc_ch32f20x_d8c.s
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file      startup_gcc_ch32f20x_d8c.s
+  * @author    Denis Krasutski
+  * @brief     CH32F205 Devices vector table
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+.syntax unified
+.cpu cortex-m3
+.thumb
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+
+.section  .text.Reset_Handler
+.weak  Reset_Handler
+.type  Reset_Handler, %function
+Reset_Handler:
+  /* set stack pointer */
+  ldr   sp, =_estack
+  /* Call the clock system initialization function.*/
+  bl  SystemInit
+  /* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+  /* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+  /* Call static constructors */
+  bl __libc_init_array
+  /* Call the application's entry point.*/
+  bl  main
+  bx  lr
+  .size  Reset_Handler, .-Reset_Handler
+
+.section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+  .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+/*******************************************************************************
+ External Interrupts
+*******************************************************************************/
+.word     WWDG_IRQHandler
+.word     PVD_IRQHandler
+.word     TAMPER_IRQHandler
+.word     RTC_IRQHandler
+.word     FLASH_IRQHandler
+.word     RCC_IRQHandler
+.word     EXTI0_IRQHandler
+.word     EXTI1_IRQHandler
+.word     EXTI2_IRQHandler
+.word     EXTI3_IRQHandler
+.word     EXTI4_IRQHandler
+.word     DMA1_Channel1_IRQHandler
+.word     DMA1_Channel2_IRQHandler
+.word     DMA1_Channel3_IRQHandler
+.word     DMA1_Channel4_IRQHandler
+.word     DMA1_Channel5_IRQHandler
+.word     DMA1_Channel6_IRQHandler
+.word     DMA1_Channel7_IRQHandler
+.word     ADC1_2_IRQHandler
+.word     USB_HP_CAN1_TX_IRQHandler
+.word     USB_LP_CAN1_RX0_IRQHandler
+.word     CAN1_RX1_IRQHandler
+.word     CAN1_SCE_IRQHandler
+.word     EXTI9_5_IRQHandler
+.word     TIM1_BRK_IRQHandler
+.word     TIM1_UP_IRQHandler
+.word     TIM1_TRG_COM_IRQHandler
+.word     TIM1_CC_IRQHandler
+.word     TIM2_IRQHandler
+.word     TIM3_IRQHandler
+.word     TIM4_IRQHandler
+.word     I2C1_EV_IRQHandler
+.word     I2C1_ER_IRQHandler
+.word     I2C2_EV_IRQHandler
+.word     I2C2_ER_IRQHandler
+.word     SPI1_IRQHandler
+.word     SPI2_IRQHandler
+.word     USART1_IRQHandler
+.word     USART2_IRQHandler
+.word     USART3_IRQHandler
+.word     EXTI15_10_IRQHandler
+.word     RTCAlarm_IRQHandler
+.word     0
+.word     TIM8_BRK_IRQHandler
+.word     TIM8_UP_IRQHandler
+.word     TIM8_TRG_COM_IRQHandler
+.word     TIM8_CC_IRQHandler
+.word     RNG_IRQHandler
+.word     FSMC_IRQHandler
+.word     SDIO_IRQHandler
+.word     TIM5_IRQHandler
+.word     SPI3_IRQHandler
+.word     UART4_IRQHandler
+.word     UART5_IRQHandler
+.word     TIM6_IRQHandler
+.word     TIM7_IRQHandler
+.word     DMA2_Channel1_IRQHandler
+.word     DMA2_Channel2_IRQHandler
+.word     DMA2_Channel3_IRQHandler
+.word     DMA2_Channel4_IRQHandler
+.word     DMA2_Channel5_IRQHandler
+.word     ETH_IRQHandler
+.word     ETH_WKUP_IRQHandler
+.word     CAN2_TX_IRQHandler
+.word     CAN2_RX0_IRQHandler
+.word     CAN2_RX1_IRQHandler
+.word     CAN2_SCE_IRQHandler
+.word     OTG_FS_IRQHandler
+.word     USBHSWakeup_IRQHandler
+.word     USBHS_IRQHandler
+.word     DVP_IRQHandler
+.word     UART6_IRQHandler
+.word     UART7_IRQHandler
+.word     UART8_IRQHandler
+.word     TIM9_BRK_IRQHandler
+.word     TIM9_UP_IRQHandler
+.word     TIM9_TRG_COM_IRQHandler
+.word     TIM9_CC_IRQHandler
+.word     TIM10_BRK_IRQHandler
+.word     TIM10_UP_IRQHandler
+.word     TIM10_TRG_COM_IRQHandler
+.word     TIM10_CC_IRQHandler
+.word     DMA2_Channel6_IRQHandler
+.word     DMA2_Channel7_IRQHandler
+.word     DMA2_Channel8_IRQHandler
+.word     DMA2_Channel9_IRQHandler
+.word     DMA2_Channel10_IRQHandler
+.word     DMA2_Channel11_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases
+*
+*******************************************************************************/
+.weak NMI_Handler
+.thumb_set NMI_Handler,Default_Handler
+
+.weak HardFault_Handler
+.thumb_set HardFault_Handler,Default_Handler
+
+.weak MemManage_Handler
+.thumb_set MemManage_Handler,Default_Handler
+
+.weak BusFault_Handler
+.thumb_set BusFault_Handler,Default_Handler
+
+.weak UsageFault_Handler
+.thumb_set UsageFault_Handler,Default_Handler
+
+.weak SVC_Handler
+.thumb_set SVC_Handler,Default_Handler
+
+.weak DebugMon_Handler
+.thumb_set DebugMon_Handler,Default_Handler
+
+.weak PendSV_Handler
+.thumb_set PendSV_Handler,Default_Handler
+
+.weak SysTick_Handler
+.thumb_set SysTick_Handler,Default_Handler
+
+.weak WWDG_IRQHandler
+.thumb_set WWDG_IRQHandler,Default_Handler
+
+.weak PVD_IRQHandler
+.thumb_set PVD_IRQHandler,Default_Handler
+
+.weak TAMPER_IRQHandler
+.thumb_set TAMPER_IRQHandler,Default_Handler
+
+.weak RTC_IRQHandler
+.thumb_set RTC_IRQHandler,Default_Handler
+
+.weak FLASH_IRQHandler
+.thumb_set FLASH_IRQHandler,Default_Handler
+
+.weak RCC_IRQHandler
+.thumb_set RCC_IRQHandler,Default_Handler
+
+.weak EXTI0_IRQHandler
+.thumb_set EXTI0_IRQHandler,Default_Handler
+
+.weak EXTI1_IRQHandler
+.thumb_set EXTI1_IRQHandler,Default_Handler
+
+.weak EXTI2_IRQHandler
+.thumb_set EXTI2_IRQHandler,Default_Handler
+
+.weak EXTI3_IRQHandler
+.thumb_set EXTI3_IRQHandler,Default_Handler
+
+.weak EXTI4_IRQHandler
+.thumb_set EXTI4_IRQHandler,Default_Handler
+
+.weak DMA1_Channel1_IRQHandler
+.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+.weak DMA1_Channel2_IRQHandler
+.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+.weak DMA1_Channel3_IRQHandler
+.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+.weak DMA1_Channel4_IRQHandler
+.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+.weak DMA1_Channel5_IRQHandler
+.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+.weak DMA1_Channel6_IRQHandler
+.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+.weak DMA1_Channel7_IRQHandler
+.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+.weak ADC1_2_IRQHandler
+.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+.weak USB_HP_CAN1_TX_IRQHandler
+.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+.weak USB_LP_CAN1_RX0_IRQHandler
+.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+.weak CAN1_RX1_IRQHandler
+.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+.weak CAN1_SCE_IRQHandler
+.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+.weak EXTI9_5_IRQHandler
+.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+.weak TIM1_BRK_IRQHandler
+.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+.weak TIM1_UP_IRQHandler
+.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+.weak TIM1_TRG_COM_IRQHandler
+.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM1_CC_IRQHandler
+.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+.weak TIM2_IRQHandler
+.thumb_set TIM2_IRQHandler,Default_Handler
+
+.weak TIM3_IRQHandler
+.thumb_set TIM3_IRQHandler,Default_Handler
+
+.weak TIM4_IRQHandler
+.thumb_set TIM4_IRQHandler,Default_Handler
+
+.weak I2C1_EV_IRQHandler
+.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+.weak I2C1_ER_IRQHandler
+.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+.weak I2C2_EV_IRQHandler
+.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+.weak I2C2_ER_IRQHandler
+.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+.weak SPI1_IRQHandler
+.thumb_set SPI1_IRQHandler,Default_Handler
+
+.weak SPI2_IRQHandler
+.thumb_set SPI2_IRQHandler,Default_Handler
+
+.weak USART1_IRQHandler
+.thumb_set USART1_IRQHandler,Default_Handler
+
+.weak USART2_IRQHandler
+.thumb_set USART2_IRQHandler,Default_Handler
+
+.weak USART3_IRQHandler
+.thumb_set USART3_IRQHandler,Default_Handler
+
+.weak EXTI15_10_IRQHandler
+.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+.weak RTCAlarm_IRQHandler
+.thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+.weak TIM8_BRK_IRQHandler
+.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+.weak TIM8_UP_IRQHandler
+.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+.weak TIM8_TRG_COM_IRQHandler
+.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM8_CC_IRQHandler
+.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+.weak RNG_IRQHandler
+.thumb_set RNG_IRQHandler,Default_Handler
+
+.weak FSMC_IRQHandler
+.thumb_set FSMC_IRQHandler,Default_Handler
+
+.weak SDIO_IRQHandler
+.thumb_set SDIO_IRQHandler,Default_Handler
+
+.weak TIM5_IRQHandler
+.thumb_set TIM5_IRQHandler,Default_Handler
+
+.weak SPI3_IRQHandler
+.thumb_set SPI3_IRQHandler,Default_Handler
+
+.weak UART4_IRQHandler
+.thumb_set UART4_IRQHandler,Default_Handler
+
+.weak UART5_IRQHandler
+.thumb_set UART5_IRQHandler,Default_Handler
+
+.weak TIM6_IRQHandler
+.thumb_set TIM6_IRQHandler,Default_Handler
+
+.weak TIM7_IRQHandler
+.thumb_set TIM7_IRQHandler,Default_Handler
+
+.weak DMA2_Channel1_IRQHandler
+.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+.weak DMA2_Channel2_IRQHandler
+.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+.weak DMA2_Channel3_IRQHandler
+.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+.weak DMA2_Channel4_IRQHandler
+.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+.weak DMA2_Channel5_IRQHandler
+.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+.weak ETH_IRQHandler
+.thumb_set ETH_IRQHandler,Default_Handler
+
+.weak ETH_WKUP_IRQHandler
+.thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+.weak CAN2_TX_IRQHandler
+.thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+.weak CAN2_RX0_IRQHandler
+.thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+.weak CAN2_RX1_IRQHandler
+.thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+.weak CAN2_SCE_IRQHandler
+.thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+.weak OTG_FS_IRQHandler
+.thumb_set OTG_FS_IRQHandler,Default_Handler
+
+.weak USBHSWakeup_IRQHandler
+.thumb_set USBHSWakeup_IRQHandler,Default_Handler
+
+.weak USBHS_IRQHandler
+.thumb_set USBHS_IRQHandler,Default_Handler
+
+.weak DVP_IRQHandler
+.thumb_set DVP_IRQHandler,Default_Handler
+
+.weak UART6_IRQHandler
+.thumb_set UART6_IRQHandler,Default_Handler
+
+.weak UART7_IRQHandler
+.thumb_set UART7_IRQHandler,Default_Handler
+
+.weak UART8_IRQHandler
+.thumb_set UART8_IRQHandler,Default_Handler
+
+.weak TIM9_BRK_IRQHandler
+.thumb_set TIM9_BRK_IRQHandler,Default_Handler
+
+.weak TIM9_UP_IRQHandler
+.thumb_set TIM9_UP_IRQHandler,Default_Handler
+
+.weak TIM9_TRG_COM_IRQHandler
+.thumb_set TIM9_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM9_CC_IRQHandler
+.thumb_set TIM9_CC_IRQHandler,Default_Handler
+
+.weak TIM10_BRK_IRQHandler
+.thumb_set TIM10_BRK_IRQHandler,Default_Handler
+
+.weak TIM10_UP_IRQHandler
+.thumb_set TIM10_UP_IRQHandler,Default_Handler
+
+.weak TIM10_TRG_COM_IRQHandler
+.thumb_set TIM10_TRG_COM_IRQHandler,Default_Handler
+
+.weak TIM10_CC_IRQHandler
+.thumb_set TIM10_CC_IRQHandler,Default_Handler
+
+.weak DMA2_Channel6_IRQHandler
+.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+.weak DMA2_Channel7_IRQHandler
+.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+.weak DMA2_Channel8_IRQHandler
+.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
+
+.weak DMA2_Channel9_IRQHandler
+.thumb_set DMA2_Channel9_IRQHandler,Default_Handler
+
+.weak DMA2_Channel10_IRQHandler
+.thumb_set DMA2_Channel10_IRQHandler,Default_Handler
+
+.weak DMA2_Channel11_IRQHandler
+.thumb_set DMA2_Channel11_IRQHandler,Default_Handler
diff --git a/hw/bsp/ch32f20x/system_ch32f20x.c b/hw/bsp/ch32f20x/system_ch32f20x.c
new file mode 100644
index 000000000..0a59b9287
--- /dev/null
+++ b/hw/bsp/ch32f20x/system_ch32f20x.c
@@ -0,0 +1,1122 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32f20x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/08/08
+* Description        : CH32F20x Device Peripheral Access Layer System Source File.
+*                      For CH32F208 HSE = 32Mhz
+*                      For others   HSE = 8Mhz
+*********************************************************************************
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* Attention: This software (modified or not) and binary are used for
+* microcontroller manufactured by Nanjing Qinheng Microelectronics.
+*******************************************************************************/
+#include "ch32f20x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_48MHz_HSE  48000000
+//#define SYSCLK_FREQ_56MHz_HSE  56000000
+//#define SYSCLK_FREQ_72MHz_HSE  72000000
+#define SYSCLK_FREQ_96MHz_HSE  96000000
+//#define SYSCLK_FREQ_120MHz_HSE  120000000
+//#define SYSCLK_FREQ_144MHz_HSE  144000000
+//#define SYSCLK_FREQ_HSI    HSI_VALUE
+//#define SYSCLK_FREQ_48MHz_HSI  48000000
+//#define SYSCLK_FREQ_56MHz_HSI  56000000
+//#define SYSCLK_FREQ_72MHz_HSI  72000000
+//#define SYSCLK_FREQ_96MHz_HSI  96000000
+//#define SYSCLK_FREQ_120MHz_HSI  120000000
+//#define SYSCLK_FREQ_144MHz_HSI  144000000
+
+
+/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */
+/* #define VECT_TAB_SRAM */
+
+/* Vector Table base offset field This value must be a multiple of 0x200 */
+#define VECT_TAB_OFFSET  0x0
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;              /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSE;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz_HSI
+uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz_HSI;        /* System Clock Frequency (Core Clock) */
+#else
+uint32_t SystemCoreClock         = HSI_VALUE;                    /* System Clock Frequency (Core Clock) */
+
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* system_private_function_proto_types */
+static void SetSysClock( void );
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSE
+static void SetSysClockTo48_HSE( void );
+#elif defined SYSCLK_FREQ_56MHz_HSE
+static void SetSysClockTo56_HSE( void );
+#elif defined SYSCLK_FREQ_72MHz_HSE
+static void SetSysClockTo72_HSE( void );
+#elif defined SYSCLK_FREQ_96MHz_HSE
+static void SetSysClockTo96_HSE( void );
+#elif defined SYSCLK_FREQ_120MHz_HSE
+static void SetSysClockTo120_HSE( void );
+#elif defined SYSCLK_FREQ_144MHz_HSE
+static void SetSysClockTo144_HSE( void );
+#elif defined SYSCLK_FREQ_48MHz_HSI
+static void SetSysClockTo48_HSI( void );
+#elif defined SYSCLK_FREQ_56MHz_HSI
+static void SetSysClockTo56_HSI( void );
+#elif defined SYSCLK_FREQ_72MHz_HSI
+static void SetSysClockTo72_HSI( void );
+#elif defined SYSCLK_FREQ_96MHz_HSI
+static void SetSysClockTo96_HSI( void );
+#elif defined SYSCLK_FREQ_120MHz_HSI
+static void SetSysClockTo120_HSI( void );
+#elif defined SYSCLK_FREQ_144MHz_HSI
+static void SetSysClockTo144_HSI( void );
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit( void )
+{
+    RCC->CTLR |= ( uint32_t )0x00000001;
+
+#ifdef CH32F20x_D8C
+    RCC->CFGR0 &= ( uint32_t )0xF8FF0000;
+#else
+    RCC->CFGR0 &= ( uint32_t )0xF0FF0000;
+#endif
+
+    RCC->CTLR &= ( uint32_t )0xFEF6FFFF;
+    RCC->CTLR &= ( uint32_t )0xFFFBFFFF;
+    RCC->CFGR0 &= ( uint32_t )0xFF80FFFF;
+#ifdef CH32F20x_D8C
+    RCC->CTLR &= ( uint32_t )0xEBFFFFFF;
+    RCC->INTR = 0x00FF0000;
+    RCC->CFGR2 = 0x00000000;
+#else
+    RCC->INTR = 0x009F0000;
+#endif
+
+    SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate( void )
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+	  uint8_t Pll_6_5 = 0;
+
+#if defined (CH32F20x_D8C)
+   	uint8_t Pll2mull = 0;
+
+#endif
+
+    tmp = RCC->CFGR0 & RCC_SWS;
+
+    switch( tmp )
+    {
+        case 0x00:
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04:
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08:
+            pllmull = RCC->CFGR0 & RCC_PLLMULL;
+            pllsource = RCC->CFGR0 & RCC_PLLSRC;
+            pllmull = ( pllmull >> 18 ) + 2;
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+            if( pllmull == 17 )
+            {
+                pllmull = 18;
+            }
+#else
+            if( pllmull == 2 )
+            {
+                pllmull = 18;
+            }
+            if( pllmull == 15 )
+            {
+                pllmull = 13;  /* *6.5 */
+                Pll_6_5 = 1;
+            }
+            if( pllmull == 16 )
+            {
+                pllmull = 15;
+            }
+            if( pllmull == 17 )
+            {
+                pllmull = 16;
+            }
+#endif
+
+            if( pllsource == 0x00 )
+            {
+								if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) SystemCoreClock = HSI_VALUE * pllmull;
+								else SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+            }
+            else
+            {
+#if defined (CH32F20x_D8C)
+	          if(RCC->CFGR2 & (1<<16)){ /* PLL2 */
+              SystemCoreClock = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1);  /* PREDIV2 */
+
+              Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8);
+
+              if(Pll2mull == 0) SystemCoreClock = (SystemCoreClock * 5)>>1;
+              else if(Pll2mull == 1) SystemCoreClock = (SystemCoreClock * 25)>>1;
+              else if(Pll2mull == 15) SystemCoreClock = SystemCoreClock * 20;
+              else  SystemCoreClock = SystemCoreClock * (Pll2mull + 2);
+
+              SystemCoreClock = SystemCoreClock/((RCC->CFGR2 & 0xF) + 1);  /* PREDIV1 */
+          }
+          else{/* HSE */
+              SystemCoreClock = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1);  /* PREDIV1 */
+          }
+
+          SystemCoreClock = SystemCoreClock * pllmull;
+#else
+
+#if defined (CH32F20x_D8W)
+								if((RCC->CFGR0 & (3<<22)) == (3<<22))
+								{
+									SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
+								}
+								else
+#endif
+                if( ( RCC->CFGR0 & RCC_PLLXTPRE ) != ( uint32_t )RESET )
+                {
+#ifdef CH32F20x_D8W
+                    SystemCoreClock = ( ( HSE_VALUE >> 2 ) >> 1 ) * pllmull;
+#else
+                    SystemCoreClock = ( HSE_VALUE >> 1 ) * pllmull;
+#endif
+                }
+                else
+                {
+#ifdef CH32F20x_D8W
+                    SystemCoreClock = ( HSE_VALUE >> 2 ) * pllmull;
+#else
+                    SystemCoreClock = HSE_VALUE * pllmull;
+#endif
+
+                }
+#endif
+            }
+
+            if( Pll_6_5 == 1 ) SystemCoreClock = ( SystemCoreClock / 2 );
+
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+
+    tmp = AHBPrescTable[( ( RCC->CFGR0 & RCC_HPRE ) >> 4 )];
+    SystemCoreClock >>= tmp;
+}
+
+
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock( void )
+{
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_48MHz_HSE
+    SetSysClockTo48_HSE();
+#elif defined SYSCLK_FREQ_56MHz_HSE
+    SetSysClockTo56_HSE();
+#elif defined SYSCLK_FREQ_72MHz_HSE
+    SetSysClockTo72_HSE();
+#elif defined SYSCLK_FREQ_96MHz_HSE
+    SetSysClockTo96_HSE();
+#elif defined SYSCLK_FREQ_120MHz_HSE
+    SetSysClockTo120_HSE();
+#elif defined SYSCLK_FREQ_144MHz_HSE
+    SetSysClockTo144_HSE();
+#elif defined SYSCLK_FREQ_48MHz_HSI
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_FREQ_56MHz_HSI
+    SetSysClockTo56_HSI();
+#elif defined SYSCLK_FREQ_72MHz_HSI
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_FREQ_96MHz_HSI
+    SetSysClockTo96_HSI();
+#elif defined SYSCLK_FREQ_120MHz_HSI
+    SetSysClockTo120_HSI();
+#elif defined SYSCLK_FREQ_144MHz_HSI
+    SetSysClockTo144_HSI();
+
+#endif
+
+    /* If none of the define above is enabled, the HSI is used as System clock
+     * source (default after reset)
+    */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV1;
+
+         /* Select HSE as system clock source
+          *   CH32F20x_D6 (HSE=8Mhz)
+          *   CH32F20x_D8 (HSE=8Mhz)
+          *   CH32F20x_D8W (HSE=32Mhz)
+          */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_HSE;
+
+        /* Wait till HSE is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x04 )
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSE
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSE
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSE
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+         /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz)
+          *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8Mhz)
+          *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz(HSE=32Mhz)
+          */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+                                    RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSE
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+                                    RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSE
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+#if defined (CH32F20x_D8W)
+		RCC->CFGR0 |= (uint32_t)(3<<22);
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
+#else
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+#endif
+
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+     /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz)
+      *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8Mhz)
+      *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz(HSE=32Mhz)
+      */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+
+#elif defined SYSCLK_FREQ_144MHz_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSE
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSE( void )
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ( ( uint32_t )RCC_HSEON );
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    }
+    while( ( HSEStatus == 0 ) && ( StartUpCounter != HSE_STARTUP_TIMEOUT ) );
+
+    if( ( RCC->CTLR & RCC_HSERDY ) != RESET )
+    {
+        HSEStatus = ( uint32_t )0x01;
+    }
+    else
+    {
+        HSEStatus = ( uint32_t )0x00;
+    }
+
+    if( HSEStatus == ( uint32_t )0x01 )
+    {
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+        /*  CH32F20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz)
+         *  CH32F20x_D8-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8Mhz)
+         *  CH32F20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz(HSE=32Mhz)
+         */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE |
+                                    RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18 );
+#else
+        RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN );
+#endif
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+        RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+        * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_48MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo48_HSI
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+#elif defined SYSCLK_FREQ_56MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo56_HSI
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+#elif defined SYSCLK_FREQ_72MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo72_HSI
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo96_HSI
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo120_HSI
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120_HSI(void)
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15_EXTEN );
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz_HSI
+
+/*********************************************************************
+ * @fn      SetSysClockTo144_HSI
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144_HSI( void )
+{
+		EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+		/* HCLK = SYSCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_HPRE_DIV1;
+		/* PCLK2 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE2_DIV1;
+		/* PCLK1 = HCLK */
+		RCC->CFGR0 |= ( uint32_t )RCC_PPRE1_DIV2;
+
+		/*  PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL ) );
+
+#if defined (CH32F20x_D6) || defined (CH32F20x_D8) || defined (CH32F20x_D8W)
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18 );
+#else
+		RCC->CFGR0 |= ( uint32_t )( RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18_EXTEN );
+#endif
+
+		/* Enable PLL */
+		RCC->CTLR |= RCC_PLLON;
+		/* Wait till PLL is ready */
+		while( ( RCC->CTLR & RCC_PLLRDY ) == 0 )
+		{
+		}
+		/* Select PLL as system clock source */
+		RCC->CFGR0 &= ( uint32_t )( ( uint32_t )~( RCC_SW ) );
+		RCC->CFGR0 |= ( uint32_t )RCC_SW_PLL;
+		/* Wait till PLL is used as system clock source */
+		while( ( RCC->CFGR0 & ( uint32_t )RCC_SWS ) != ( uint32_t )0x08 )
+		{
+		}
+}
+
+
+#endif
diff --git a/hw/bsp/ch32f20x/system_ch32f20x.h b/hw/bsp/ch32f20x/system_ch32f20x.h
new file mode 100644
index 000000000..734c80a5a
--- /dev/null
+++ b/hw/bsp/ch32f20x/system_ch32f20x.h
@@ -0,0 +1,28 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32f20x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/08/08
+* Description        : CH32F20x Device Peripheral Access Layer System Header File.
+*******************************************************************************/
+#ifndef __SYSTEM_CH32F20x_H
+#define __SYSTEM_CH32F20x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32F20x_SYSTEM_H */
+
+
+
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 4b06cf429..45f0317ee 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -29,7 +29,7 @@ CFLAGS += \
 	-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
 
 SRC_C += \
-	src/portable/wch/ch32v307/dcd_usbhs.c \
+	src/portable/wch/dcd_ch32_usbhs.c \
 	$(CH32V307_SDK_SRC)/Core/core_riscv.c \
 	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \
 	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 8807ff8aa..a72976ae9 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -383,6 +383,10 @@
 #elif TU_CHECK_MCU(OPT_MCU_CH32V307)
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_RHPORT_HIGHSPEED    1
+
+#elif TU_CHECK_MCU(OPT_MCU_CH32F20X)
+  #define TUP_DCD_ENDPOINT_MAX    16
+  #define TUP_RHPORT_HIGHSPEED    1
 #endif
 
 
diff --git a/src/portable/wch/ch32_usbhs_reg.h b/src/portable/wch/ch32_usbhs_reg.h
new file mode 100644
index 000000000..9b956231f
--- /dev/null
+++ b/src/portable/wch/ch32_usbhs_reg.h
@@ -0,0 +1,349 @@
+#ifndef _USB_CH32_USBHS_REG_H
+#define _USB_CH32_USBHS_REG_H
+
+#if (CFG_TUSB_MCU == OPT_MCU_CH32V307)
+#include <ch32v30x.h>
+#elif (CFG_TUSB_MCU == OPT_MCU_CH32F20X)
+#include <ch32f20x.h>
+#endif
+
+/******************* GLOBAL ******************/
+
+// USB CONTROL
+#define USBHS_CONTROL_OFFSET 0x00
+#define USBHS_DMA_EN         (1 << 0)
+#define USBHS_ALL_CLR        (1 << 1)
+#define USBHS_FORCE_RST      (1 << 2)
+#define USBHS_INT_BUSY_EN    (1 << 3)
+#define USBHS_DEV_PU_EN      (1 << 4)
+#define USBHS_SPEED_MASK     (3 << 5)
+#define USBHS_FULL_SPEED     (0 << 5)
+#define USBHS_HIGH_SPEED     (1 << 5)
+#define USBHS_LOW_SPEED      (2 << 5)
+#define USBHS_HOST_MODE      (1 << 7)
+
+// USB_INT_EN
+#define USBHS_INT_EN_OFFSET 0x02
+#define USBHS_BUS_RST_EN    (1 << 0)
+#define USBHS_DETECT_EN     (1 << 0)
+#define USBHS_TRANSFER_EN   (1 << 1)
+#define USBHS_SUSPEND_EN    (1 << 2)
+#define USBHS_SOF_ACT_EN    (1 << 3)
+#define USBHS_FIFO_OV_EN    (1 << 4)
+#define USBHS_SETUP_ACT_EN  (1 << 5)
+#define USBHS_ISO_ACT_EN    (1 << 6)
+#define USBHS_DEV_NAK_EN    (1 << 7)
+
+// USB DEV AD
+#define USBHS_DEV_AD_OFFSET 0x03
+// USB FRAME_NO
+#define USBHS_FRAME_NO_OFFSET 0x04
+// USB SUSPEND
+#define USBHS_SUSPEND_OFFSET    0x06
+#define USBHS_DEV_REMOTE_WAKEUP (1 << 2)
+#define USBHS_LINESTATE_MASK    (2 << 4) /* Read Only */
+
+// RESERVED0
+
+// USB SPEED TYPE
+#define USBHS_SPEED_TYPE_OFFSET 0x08
+#define USBSPEED_MASK           (0x03)
+
+// USB_MIS_ST
+#define USBHS_MIS_ST_OFFSET 0x09
+#define USBHS_SPLIT_CAN     (1 << 0)
+#define USBHS_ATTACH        (1 << 1)
+#define USBHS_SUSPEND       (1 << 2)
+#define USBHS_BUS_RESET     (1 << 3)
+#define USBHS_R_FIFO_RDY    (1 << 4)
+#define USBHS_SIE_FREE      (1 << 5)
+#define USBHS_SOF_ACT       (1 << 6)
+#define USBHS_SOF_PRES      (1 << 7)
+
+// INT_FLAG
+#define USBHS_INT_FLAG_OFFSET 0x0A
+#define USBHS_BUS_RST_FLAG    (1 << 0)
+#define USBHS_DETECT_FLAG     (1 << 0)
+#define USBHS_TRANSFER_FLAG   (1 << 1)
+#define USBHS_SUSPEND_FLAG    (1 << 2)
+#define USBHS_HST_SOF_FLAG    (1 << 3)
+#define USBHS_FIFO_OV_FLAG    (1 << 4)
+#define USBHS_SETUP_FLAG      (1 << 5)
+#define USBHS_ISO_ACT_FLAG    (1 << 6)
+
+// INT_ST
+#define USBHS_INT_ST_OFFSET  0x0B
+#define USBHS_DEV_UIS_IS_NAK (1 << 7)
+#define USBHS_DEV_UIS_TOG_OK (1 << 6)
+#define MASK_UIS_TOKEN       (3 << 4)
+#define MASK_UIS_ENDP        (0x0F)
+#define MASK_UIS_H_RES       (0x0F)
+
+#define USBHS_TOGGLE_OK (0x40)
+#define USBHS_HOST_RES  (0x0f)
+
+//USB_RX_LEN
+#define USBHS_RX_LEN_OFFSET 0x0C
+/******************* DEVICE ******************/
+
+//UEP_CONFIG
+#define USBHS_UEP_CONFIG_OFFSET 0x10
+#define USBHS_EP0_T_EN          (1 << 0)
+#define USBHS_EP0_R_EN          (1 << 16)
+
+#define USBHS_EP1_T_EN (1 << 1)
+#define USBHS_EP1_R_EN (1 << 17)
+
+#define USBHS_EP2_T_EN (1 << 2)
+#define USBHS_EP2_R_EN (1 << 18)
+
+#define USBHS_EP3_T_EN (1 << 3)
+#define USBHS_EP3_R_EN (1 << 19)
+
+#define USBHS_EP4_T_EN (1 << 4)
+#define USBHS_EP4_R_EN (1 << 20)
+
+#define USBHS_EP5_T_EN (1 << 5)
+#define USBHS_EP5_R_EN (1 << 21)
+
+#define USBHS_EP6_T_EN (1 << 6)
+#define USBHS_EP6_R_EN (1 << 22)
+
+#define USBHS_EP7_T_EN (1 << 7)
+#define USBHS_EP7_R_EN (1 << 23)
+
+#define USBHS_EP8_T_EN (1 << 8)
+#define USBHS_EP8_R_EN (1 << 24)
+
+#define USBHS_EP9_T_EN (1 << 9)
+#define USBHS_EP9_R_EN (1 << 25)
+
+#define USBHS_EP10_T_EN (1 << 10)
+#define USBHS_EP10_R_EN (1 << 26)
+
+#define USBHS_EP11_T_EN (1 << 11)
+#define USBHS_EP11_R_EN (1 << 27)
+
+#define USBHS_EP12_T_EN (1 << 12)
+#define USBHS_EP12_R_EN (1 << 28)
+
+#define USBHS_EP13_T_EN (1 << 13)
+#define USBHS_EP13_R_EN (1 << 29)
+
+#define USBHS_EP14_T_EN (1 << 14)
+#define USBHS_EP14_R_EN (1 << 30)
+
+#define USBHS_EP15_T_EN (1 << 15)
+#define USBHS_EP15_R_EN (1 << 31)
+
+//UEP_TYPE
+#define USBHS_UEP_TYPE_OFFSET 0x14
+#define USBHS_EP0_T_TYP       (1 << 0)
+#define USBHS_EP0_R_TYP       (1 << 16)
+
+#define USBHS_EP1_T_TYP (1 << 1)
+#define USBHS_EP1_R_TYP (1 << 17)
+
+#define USBHS_EP2_T_TYP (1 << 2)
+#define USBHS_EP2_R_TYP (1 << 18)
+
+#define USBHS_EP3_T_TYP (1 << 3)
+#define USBHS_EP3_R_TYP (1 << 19)
+
+#define USBHS_EP4_T_TYP (1 << 4)
+#define USBHS_EP4_R_TYP (1 << 20)
+
+#define USBHS_EP5_T_TYP (1 << 5)
+#define USBHS_EP5_R_TYP (1 << 21)
+
+#define USBHS_EP6_T_TYP (1 << 6)
+#define USBHS_EP6_R_TYP (1 << 22)
+
+#define USBHS_EP7_T_TYP (1 << 7)
+#define USBHS_EP7_R_TYP (1 << 23)
+
+#define USBHS_EP8_T_TYP (1 << 8)
+#define USBHS_EP8_R_TYP (1 << 24)
+
+#define USBHS_EP9_T_TYP (1 << 8)
+#define USBHS_EP9_R_TYP (1 << 25)
+
+#define USBHS_EP10_T_TYP (1 << 10)
+#define USBHS_EP10_R_TYP (1 << 26)
+
+#define USBHS_EP11_T_TYP (1 << 11)
+#define USBHS_EP11_R_TYP (1 << 27)
+
+#define USBHS_EP12_T_TYP (1 << 12)
+#define USBHS_EP12_R_TYP (1 << 28)
+
+#define USBHS_EP13_T_TYP (1 << 13)
+#define USBHS_EP13_R_TYP (1 << 29)
+
+#define USBHS_EP14_T_TYP (1 << 14)
+#define USBHS_EP14_R_TYP (1 << 30)
+
+#define USBHS_EP15_T_TYP (1 << 15)
+#define USBHS_EP15_R_TYP (1 << 31)
+
+/* BUF_MOD UEP1~15 */
+#define USBHS_BUF_MOD_OFFSET  0x18
+#define USBHS_EP0_BUF_MOD     (1 << 0)
+#define USBHS_EP0_ISO_BUF_MOD (1 << 16)
+
+#define USBHS_EP1_BUF_MOD     (1 << 1)
+#define USBHS_EP1_ISO_BUF_MOD (1 << 17)
+
+#define USBHS_EP2_BUF_MOD     (1 << 2)
+#define USBHS_EP2_ISO_BUF_MOD (1 << 18)
+
+#define USBHS_EP3_BUF_MOD     (1 << 3)
+#define USBHS_EP3_ISO_BUF_MOD (1 << 19)
+
+#define USBHS_EP4_BUF_MOD     (1 << 4)
+#define USBHS_EP4_ISO_BUF_MOD (1 << 20)
+
+#define USBHS_EP5_BUF_MOD     (1 << 5)
+#define USBHS_EP5_ISO_BUF_MOD (1 << 21)
+
+#define USBHS_EP6_BUF_MOD     (1 << 6)
+#define USBHS_EP6_ISO_BUF_MOD (1 << 22)
+
+#define USBHS_EP7_BUF_MOD     (1 << 7)
+#define USBHS_EP7_ISO_BUF_MOD (1 << 23)
+
+#define USBHS_EP8_BUF_MOD     (1 << 8)
+#define USBHS_EP8_ISO_BUF_MOD (1 << 24)
+
+#define USBHS_EP9_BUF_MOD     (1 << 9)
+#define USBHS_EP9_ISO_BUF_MOD (1 << 25)
+
+#define USBHS_EP10_BUF_MOD     (1 << 10)
+#define USBHS_EP10_ISO_BUF_MOD (1 << 26)
+
+#define USBHS_EP11_BUF_MOD     (1 << 11)
+#define USBHS_EP11_ISO_BUF_MOD (1 << 27)
+
+#define USBHS_EP12_BUF_MOD     (1 << 12)
+#define USBHS_EP12_ISO_BUF_MOD (1 << 28)
+
+#define USBHS_EP13_BUF_MOD     (1 << 13)
+#define USBHS_EP13_ISO_BUF_MOD (1 << 29)
+
+#define USBHS_EP14_BUF_MOD     (1 << 14)
+#define USBHS_EP14_ISO_BUF_MOD (1 << 30)
+
+#define USBHS_EP15_BUF_MOD     (1 << 15)
+#define USBHS_EP15_ISO_BUF_MOD (1 << 31)
+//USBHS_EPn_T_EN  USBHS_EPn_R_EN  USBHS_EPn_BUF_MOD  Description: Arrange from low to high with UEPn_DMA as the starting address
+//      0               0               x            The endpoint is disabled and the UEPn_*_DMA buffers are not used.
+//      1               0               0            The first address of the receive (OUT) buffer is UEPn_RX_DMA
+//      1               0               1            RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA
+//      0               1               0            The first address of the transmit (IN) buffer is UEPn_TX_DMA.
+//      0               1               1            RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA
+
+/* USB0_DMA */
+#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address
+
+/* USBX_RX_DMA */
+#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_T_LEN_OFFSET(n)   (0xD8 + 4 * (n)) // endpoint x DMA buffer address
+#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address
+#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address
+
+// UEPn_T_LEN
+#define USBHS_EP_T_LEN_MASK (0x7FF)
+
+//UEPn_TX_CTRL
+#define USBHS_EP_T_RES_MASK  (3 << 0)
+#define USBHS_EP_T_RES_ACK   (0 << 0)
+#define USBHS_EP_T_RES_NYET  (1 << 0)
+#define USBHS_EP_T_RES_NAK   (2 << 0)
+#define USBHS_EP_T_RES_STALL (3 << 0)
+
+#define USBHS_EP_T_TOG_MASK (3 << 3)
+#define USBHS_EP_T_TOG_0    (0 << 3)
+#define USBHS_EP_T_TOG_1    (1 << 3)
+#define USBHS_EP_T_TOG_2    (2 << 3)
+#define USBHS_EP_T_TOG_M    (3 << 3)
+
+#define USBHS_EP_T_AUTOTOG (1 << 5)
+
+//UEPn_RX_CTRL
+#define USBHS_EP_R_RES_MASK  (3 << 0)
+#define USBHS_EP_R_RES_ACK   (0 << 0)
+#define USBHS_EP_R_RES_NYET  (1 << 0)
+#define USBHS_EP_R_RES_NAK   (2 << 0)
+#define USBHS_EP_R_RES_STALL (3 << 0)
+
+#define USBHS_EP_R_TOG_MASK (3 << 3)
+#define USBHS_EP_R_TOG_0    (0 << 3)
+#define USBHS_EP_R_TOG_1    (1 << 3)
+#define USBHS_EP_R_TOG_2    (2 << 3)
+#define USBHS_EP_R_TOG_M    (3 << 3)
+
+#define USBHS_EP_R_AUTOTOG (1 << 5)
+
+#define USBHS_TOG_MATCH (1 << 6)
+
+/******************* HOST ******************/
+// USB HOST_CTRL
+#define USBHS_SEND_BUS_RESET   (1 << 0)
+#define USBHS_SEND_BUS_SUSPEND (1 << 1)
+#define USBHS_SEND_BUS_RESUME  (1 << 2)
+#define USBHS_REMOTE_WAKE      (1 << 3)
+#define USBHS_PHY_SUSPENDM     (1 << 4)
+#define USBHS_UH_SOFT_FREE     (1 << 6)
+#define USBHS_SEND_SOF_EN      (1 << 7)
+
+//UH_CONFIG
+#define USBHS_HOST_TX_EN (1 << 3)
+#define USBHS_HOST_RX_EN (1 << 18)
+
+// HOST_EP_TYPE
+#define USBHS_ENDP_TX_ISO (1 << 3)
+#define USBHS_ENDP_RX_ISO (1 << (16 + 2))
+
+// R32_UH_EP_PID
+#define USBHS_HOST_MASK_TOKEN (0x0f)
+#define USBHS_HOST_MASK_ENDP  (0x0f << 4)
+
+//R8_UH_RX_CTRL
+#define USBHS_EP_R_RES_MASK  (3 << 0)
+#define USBHS_EP_R_RES_ACK   (0 << 0)
+#define USBHS_EP_R_RES_NYET  (1 << 0)
+#define USBHS_EP_R_RES_NAK   (2 << 0)
+#define USBHS_EP_R_RES_STALL (3 << 0)
+
+#define USBHS_UH_R_RES_NO   (1 << 2)
+#define USBHS_UH_R_TOG_1    (1 << 3)
+#define USBHS_UH_R_TOG_2    (2 << 3)
+#define USBHS_UH_R_TOG_3    (3 << 3)
+#define USBHS_UH_R_TOG_AUTO (1 << 5)
+#define USBHS_UH_R_DATA_NO  (1 << 6)
+//R8_UH_TX_CTRL
+#define USBHS_UH_T_RES_MASK  (3 << 0)
+#define USBHS_UH_T_RES_ACK   (0 << 0)
+#define USBHS_UH_T_RES_NYET  (1 << 0)
+#define USBHS_UH_T_RES_NAK   (2 << 0)
+#define USBHS_UH_T_RES_STALL (3 << 0)
+
+#define USBHS_UH_T_RES_NO   (1 << 2)
+#define USBHS_UH_T_TOG_1    (1 << 3)
+#define USBHS_UH_T_TOG_2    (2 << 3)
+#define USBHS_UH_T_TOG_3    (3 << 3)
+#define USBHS_UH_T_TOG_AUTO (1 << 5)
+#define USBHS_UH_T_DATA_NO  (1 << 6)
+
+// 00: OUT, 01:SOF, 10:IN, 11:SETUP
+#define PID_OUT   0
+#define PID_SOF   1
+#define PID_IN    2
+#define PID_SETUP 3
+
+#endif
diff --git a/src/portable/wch/ch32v307/ch32_usbhs_reg.h b/src/portable/wch/ch32v307/ch32_usbhs_reg.h
deleted file mode 100644
index 5a2c1fbc9..000000000
--- a/src/portable/wch/ch32v307/ch32_usbhs_reg.h
+++ /dev/null
@@ -1,345 +0,0 @@
-#ifndef _USB_CH32_USBHS_REG_H
-#define _USB_CH32_USBHS_REG_H
-
-#include <ch32v30x.h>
-
-/******************* GLOBAL ******************/
-
-// USB CONTROL
-#define USBHS_CONTROL_OFFSET 0x00
-#define USBHS_DMA_EN         (1 << 0)
-#define USBHS_ALL_CLR        (1 << 1)
-#define USBHS_FORCE_RST      (1 << 2)
-#define USBHS_INT_BUSY_EN    (1 << 3)
-#define USBHS_DEV_PU_EN      (1 << 4)
-#define USBHS_SPEED_MASK     (3 << 5)
-#define USBHS_FULL_SPEED     (0 << 5)
-#define USBHS_HIGH_SPEED     (1 << 5)
-#define USBHS_LOW_SPEED      (2 << 5)
-#define USBHS_HOST_MODE      (1 << 7)
-
-// USB_INT_EN
-#define USBHS_INT_EN_OFFSET 0x02
-#define USBHS_BUS_RST_EN    (1 << 0)
-#define USBHS_DETECT_EN     (1 << 0)
-#define USBHS_TRANSFER_EN   (1 << 1)
-#define USBHS_SUSPEND_EN    (1 << 2)
-#define USBHS_SOF_ACT_EN    (1 << 3)
-#define USBHS_FIFO_OV_EN    (1 << 4)
-#define USBHS_SETUP_ACT_EN  (1 << 5)
-#define USBHS_ISO_ACT_EN    (1 << 6)
-#define USBHS_DEV_NAK_EN    (1 << 7)
-
-// USB DEV AD
-#define USBHS_DEV_AD_OFFSET 0x03
-// USB FRAME_NO
-#define USBHS_FRAME_NO_OFFSET 0x04
-// USB SUSPEND
-#define USBHS_SUSPEND_OFFSET    0x06
-#define USBHS_DEV_REMOTE_WAKEUP (1 << 2)
-#define USBHS_LINESTATE_MASK    (2 << 4) /* Read Only */
-
-// RESERVED0
-
-// USB SPEED TYPE
-#define USBHS_SPEED_TYPE_OFFSET 0x08
-#define USBSPEED_MASK           (0x03)
-
-// USB_MIS_ST
-#define USBHS_MIS_ST_OFFSET 0x09
-#define USBHS_SPLIT_CAN     (1 << 0)
-#define USBHS_ATTACH        (1 << 1)
-#define USBHS_SUSPEND       (1 << 2)
-#define USBHS_BUS_RESET     (1 << 3)
-#define USBHS_R_FIFO_RDY    (1 << 4)
-#define USBHS_SIE_FREE      (1 << 5)
-#define USBHS_SOF_ACT       (1 << 6)
-#define USBHS_SOF_PRES      (1 << 7)
-
-// INT_FLAG
-#define USBHS_INT_FLAG_OFFSET 0x0A
-#define USBHS_BUS_RST_FLAG    (1 << 0)
-#define USBHS_DETECT_FLAG     (1 << 0)
-#define USBHS_TRANSFER_FLAG   (1 << 1)
-#define USBHS_SUSPEND_FLAG    (1 << 2)
-#define USBHS_HST_SOF_FLAG    (1 << 3)
-#define USBHS_FIFO_OV_FLAG    (1 << 4)
-#define USBHS_SETUP_FLAG      (1 << 5)
-#define USBHS_ISO_ACT_FLAG    (1 << 6)
-
-// INT_ST
-#define USBHS_INT_ST_OFFSET  0x0B
-#define USBHS_DEV_UIS_IS_NAK (1 << 7)
-#define USBHS_DEV_UIS_TOG_OK (1 << 6)
-#define MASK_UIS_TOKEN       (3 << 4)
-#define MASK_UIS_ENDP        (0x0F)
-#define MASK_UIS_H_RES       (0x0F)
-
-#define USBHS_TOGGLE_OK (0x40)
-#define USBHS_HOST_RES  (0x0f)
-
-//USB_RX_LEN
-#define USBHS_RX_LEN_OFFSET 0x0C
-/******************* DEVICE ******************/
-
-//UEP_CONFIG
-#define USBHS_UEP_CONFIG_OFFSET 0x10
-#define USBHS_EP0_T_EN          (1 << 0)
-#define USBHS_EP0_R_EN          (1 << 16)
-
-#define USBHS_EP1_T_EN (1 << 1)
-#define USBHS_EP1_R_EN (1 << 17)
-
-#define USBHS_EP2_T_EN (1 << 2)
-#define USBHS_EP2_R_EN (1 << 18)
-
-#define USBHS_EP3_T_EN (1 << 3)
-#define USBHS_EP3_R_EN (1 << 19)
-
-#define USBHS_EP4_T_EN (1 << 4)
-#define USBHS_EP4_R_EN (1 << 20)
-
-#define USBHS_EP5_T_EN (1 << 5)
-#define USBHS_EP5_R_EN (1 << 21)
-
-#define USBHS_EP6_T_EN (1 << 6)
-#define USBHS_EP6_R_EN (1 << 22)
-
-#define USBHS_EP7_T_EN (1 << 7)
-#define USBHS_EP7_R_EN (1 << 23)
-
-#define USBHS_EP8_T_EN (1 << 8)
-#define USBHS_EP8_R_EN (1 << 24)
-
-#define USBHS_EP9_T_EN (1 << 9)
-#define USBHS_EP9_R_EN (1 << 25)
-
-#define USBHS_EP10_T_EN (1 << 10)
-#define USBHS_EP10_R_EN (1 << 26)
-
-#define USBHS_EP11_T_EN (1 << 11)
-#define USBHS_EP11_R_EN (1 << 27)
-
-#define USBHS_EP12_T_EN (1 << 12)
-#define USBHS_EP12_R_EN (1 << 28)
-
-#define USBHS_EP13_T_EN (1 << 13)
-#define USBHS_EP13_R_EN (1 << 29)
-
-#define USBHS_EP14_T_EN (1 << 14)
-#define USBHS_EP14_R_EN (1 << 30)
-
-#define USBHS_EP15_T_EN (1 << 15)
-#define USBHS_EP15_R_EN (1 << 31)
-
-//UEP_TYPE
-#define USBHS_UEP_TYPE_OFFSET 0x14
-#define USBHS_EP0_T_TYP       (1 << 0)
-#define USBHS_EP0_R_TYP       (1 << 16)
-
-#define USBHS_EP1_T_TYP (1 << 1)
-#define USBHS_EP1_R_TYP (1 << 17)
-
-#define USBHS_EP2_T_TYP (1 << 2)
-#define USBHS_EP2_R_TYP (1 << 18)
-
-#define USBHS_EP3_T_TYP (1 << 3)
-#define USBHS_EP3_R_TYP (1 << 19)
-
-#define USBHS_EP4_T_TYP (1 << 4)
-#define USBHS_EP4_R_TYP (1 << 20)
-
-#define USBHS_EP5_T_TYP (1 << 5)
-#define USBHS_EP5_R_TYP (1 << 21)
-
-#define USBHS_EP6_T_TYP (1 << 6)
-#define USBHS_EP6_R_TYP (1 << 22)
-
-#define USBHS_EP7_T_TYP (1 << 7)
-#define USBHS_EP7_R_TYP (1 << 23)
-
-#define USBHS_EP8_T_TYP (1 << 8)
-#define USBHS_EP8_R_TYP (1 << 24)
-
-#define USBHS_EP9_T_TYP (1 << 8)
-#define USBHS_EP9_R_TYP (1 << 25)
-
-#define USBHS_EP10_T_TYP (1 << 10)
-#define USBHS_EP10_R_TYP (1 << 26)
-
-#define USBHS_EP11_T_TYP (1 << 11)
-#define USBHS_EP11_R_TYP (1 << 27)
-
-#define USBHS_EP12_T_TYP (1 << 12)
-#define USBHS_EP12_R_TYP (1 << 28)
-
-#define USBHS_EP13_T_TYP (1 << 13)
-#define USBHS_EP13_R_TYP (1 << 29)
-
-#define USBHS_EP14_T_TYP (1 << 14)
-#define USBHS_EP14_R_TYP (1 << 30)
-
-#define USBHS_EP15_T_TYP (1 << 15)
-#define USBHS_EP15_R_TYP (1 << 31)
-
-/* BUF_MOD UEP1~15 */
-#define USBHS_BUF_MOD_OFFSET  0x18
-#define USBHS_EP0_BUF_MOD     (1 << 0)
-#define USBHS_EP0_ISO_BUF_MOD (1 << 16)
-
-#define USBHS_EP1_BUF_MOD     (1 << 1)
-#define USBHS_EP1_ISO_BUF_MOD (1 << 17)
-
-#define USBHS_EP2_BUF_MOD     (1 << 2)
-#define USBHS_EP2_ISO_BUF_MOD (1 << 18)
-
-#define USBHS_EP3_BUF_MOD     (1 << 3)
-#define USBHS_EP3_ISO_BUF_MOD (1 << 19)
-
-#define USBHS_EP4_BUF_MOD     (1 << 4)
-#define USBHS_EP4_ISO_BUF_MOD (1 << 20)
-
-#define USBHS_EP5_BUF_MOD     (1 << 5)
-#define USBHS_EP5_ISO_BUF_MOD (1 << 21)
-
-#define USBHS_EP6_BUF_MOD     (1 << 6)
-#define USBHS_EP6_ISO_BUF_MOD (1 << 22)
-
-#define USBHS_EP7_BUF_MOD     (1 << 7)
-#define USBHS_EP7_ISO_BUF_MOD (1 << 23)
-
-#define USBHS_EP8_BUF_MOD     (1 << 8)
-#define USBHS_EP8_ISO_BUF_MOD (1 << 24)
-
-#define USBHS_EP9_BUF_MOD     (1 << 9)
-#define USBHS_EP9_ISO_BUF_MOD (1 << 25)
-
-#define USBHS_EP10_BUF_MOD     (1 << 10)
-#define USBHS_EP10_ISO_BUF_MOD (1 << 26)
-
-#define USBHS_EP11_BUF_MOD     (1 << 11)
-#define USBHS_EP11_ISO_BUF_MOD (1 << 27)
-
-#define USBHS_EP12_BUF_MOD     (1 << 12)
-#define USBHS_EP12_ISO_BUF_MOD (1 << 28)
-
-#define USBHS_EP13_BUF_MOD     (1 << 13)
-#define USBHS_EP13_ISO_BUF_MOD (1 << 29)
-
-#define USBHS_EP14_BUF_MOD     (1 << 14)
-#define USBHS_EP14_ISO_BUF_MOD (1 << 30)
-
-#define USBHS_EP15_BUF_MOD     (1 << 15)
-#define USBHS_EP15_ISO_BUF_MOD (1 << 31)
-//USBHS_EPn_T_EN  USBHS_EPn_R_EN  USBHS_EPn_BUF_MOD  Description: Arrange from low to high with UEPn_DMA as the starting address
-//      0               0               x            The endpoint is disabled and the UEPn_*_DMA buffers are not used.
-//      1               0               0            The first address of the receive (OUT) buffer is UEPn_RX_DMA
-//      1               0               1            RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA
-//      0               1               0            The first address of the transmit (IN) buffer is UEPn_TX_DMA.
-//      0               1               1            RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA
-
-/* USB0_DMA */
-#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address
-
-/* USBX_RX_DMA */
-#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address
-
-#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address
-
-#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address
-
-#define USBHS_UEPx_T_LEN_OFFSET(n)   (0xD8 + 4 * (n)) // endpoint x DMA buffer address
-#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address
-#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address
-
-// UEPn_T_LEN
-#define USBHS_EP_T_LEN_MASK (0x7FF)
-
-//UEPn_TX_CTRL
-#define USBHS_EP_T_RES_MASK  (3 << 0)
-#define USBHS_EP_T_RES_ACK   (0 << 0)
-#define USBHS_EP_T_RES_NYET  (1 << 0)
-#define USBHS_EP_T_RES_NAK   (2 << 0)
-#define USBHS_EP_T_RES_STALL (3 << 0)
-
-#define USBHS_EP_T_TOG_MASK (3 << 3)
-#define USBHS_EP_T_TOG_0    (0 << 3)
-#define USBHS_EP_T_TOG_1    (1 << 3)
-#define USBHS_EP_T_TOG_2    (2 << 3)
-#define USBHS_EP_T_TOG_M    (3 << 3)
-
-#define USBHS_EP_T_AUTOTOG (1 << 5)
-
-//UEPn_RX_CTRL
-#define USBHS_EP_R_RES_MASK  (3 << 0)
-#define USBHS_EP_R_RES_ACK   (0 << 0)
-#define USBHS_EP_R_RES_NYET  (1 << 0)
-#define USBHS_EP_R_RES_NAK   (2 << 0)
-#define USBHS_EP_R_RES_STALL (3 << 0)
-
-#define USBHS_EP_R_TOG_MASK (3 << 3)
-#define USBHS_EP_R_TOG_0    (0 << 3)
-#define USBHS_EP_R_TOG_1    (1 << 3)
-#define USBHS_EP_R_TOG_2    (2 << 3)
-#define USBHS_EP_R_TOG_M    (3 << 3)
-
-#define USBHS_EP_R_AUTOTOG (1 << 5)
-
-#define USBHS_TOG_MATCH (1 << 6)
-
-/******************* HOST ******************/
-// USB HOST_CTRL
-#define USBHS_SEND_BUS_RESET   (1 << 0)
-#define USBHS_SEND_BUS_SUSPEND (1 << 1)
-#define USBHS_SEND_BUS_RESUME  (1 << 2)
-#define USBHS_REMOTE_WAKE      (1 << 3)
-#define USBHS_PHY_SUSPENDM     (1 << 4)
-#define USBHS_UH_SOFT_FREE     (1 << 6)
-#define USBHS_SEND_SOF_EN      (1 << 7)
-
-//UH_CONFIG
-#define USBHS_HOST_TX_EN (1 << 3)
-#define USBHS_HOST_RX_EN (1 << 18)
-
-// HOST_EP_TYPE
-#define USBHS_ENDP_TX_ISO (1 << 3)
-#define USBHS_ENDP_RX_ISO (1 << (16 + 2))
-
-// R32_UH_EP_PID
-#define USBHS_HOST_MASK_TOKEN (0x0f)
-#define USBHS_HOST_MASK_ENDP  (0x0f << 4)
-
-//R8_UH_RX_CTRL
-#define USBHS_EP_R_RES_MASK  (3 << 0)
-#define USBHS_EP_R_RES_ACK   (0 << 0)
-#define USBHS_EP_R_RES_NYET  (1 << 0)
-#define USBHS_EP_R_RES_NAK   (2 << 0)
-#define USBHS_EP_R_RES_STALL (3 << 0)
-
-#define USBHS_UH_R_RES_NO   (1 << 2)
-#define USBHS_UH_R_TOG_1    (1 << 3)
-#define USBHS_UH_R_TOG_2    (2 << 3)
-#define USBHS_UH_R_TOG_3    (3 << 3)
-#define USBHS_UH_R_TOG_AUTO (1 << 5)
-#define USBHS_UH_R_DATA_NO  (1 << 6)
-//R8_UH_TX_CTRL
-#define USBHS_UH_T_RES_MASK  (3 << 0)
-#define USBHS_UH_T_RES_ACK   (0 << 0)
-#define USBHS_UH_T_RES_NYET  (1 << 0)
-#define USBHS_UH_T_RES_NAK   (2 << 0)
-#define USBHS_UH_T_RES_STALL (3 << 0)
-
-#define USBHS_UH_T_RES_NO   (1 << 2)
-#define USBHS_UH_T_TOG_1    (1 << 3)
-#define USBHS_UH_T_TOG_2    (2 << 3)
-#define USBHS_UH_T_TOG_3    (3 << 3)
-#define USBHS_UH_T_TOG_AUTO (1 << 5)
-#define USBHS_UH_T_DATA_NO  (1 << 6)
-
-// 00: OUT, 01:SOF, 10:IN, 11:SETUP
-#define PID_OUT   0
-#define PID_SOF   1
-#define PID_IN    2
-#define PID_SETUP 3
-
-#endif
diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c
deleted file mode 100644
index 3ad011cff..000000000
--- a/src/portable/wch/ch32v307/dcd_usbhs.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2022 Greg Davill
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307)
-#include "device/dcd.h"
-
-#include "ch32_usbhs_reg.h"
-#include "core_riscv.h"
-
-// Max number of bi-directional endpoints including EP0
-#define EP_MAX 16
-
-typedef struct {
-    uint8_t *buffer;
-    // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
-    uint16_t total_len;
-    uint16_t queued_len;
-    uint16_t max_size;
-    bool short_packet;
-} xfer_ctl_t;
-
-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
-static xfer_ctl_t xfer_status[EP_MAX][2];
-
-#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2)
-#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4)
-#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4)
-#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2)
-
-#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1))
-#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
-
-/* Endpoint Buffer */
-TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64];  // ep0(64)
-
-volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01;
-
-void dcd_init(uint8_t rhport) {
-    (void)rhport;
-
-    memset(&xfer_status, 0, sizeof(xfer_status));
-
-    USBHSD->HOST_CTRL = 0x00;
-    USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
-
-    USBHSD->CONTROL = 0;
-
-#if TUD_OPT_HIGH_SPEED
-    USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
-#else
-    #error OPT_MODE_FULL_SPEED not currently supported on CH32V307
-    USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
-#endif
-
-    USBHSD->INT_EN = 0;
-    USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN;
-
-    /* ALL endpoint enable */
-    USBHSD->ENDP_CONFIG = 0xffffffff;
-
-    USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
-    USBHSD->ENDP_TYPE = 0x00;
-    USBHSD->BUF_MODE = 0x00;
-
-    USBHSD->UEP0_MAX_LEN = 64;
-
-    USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD;
-
-    USBHSD->UEP0_TX_LEN = 0;
-    USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK;
-    USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
-
-    for (int ep = 1; ep < EP_MAX; ep++) {
-        EP_TX_LEN(ep) = 0;
-        EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
-        EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
-
-        EP_RX_MAX_LEN(ep) = 512;
-    }
-
-    USBHSD->DEV_AD = 0;
-    USBHSD->CONTROL |= USBHS_DEV_PU_EN;
-}
-
-void dcd_int_enable(uint8_t rhport) {
-    (void)rhport;
-
-    NVIC_EnableIRQ(USBHS_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport) {
-    (void)rhport;
-
-    NVIC_DisableIRQ(USBHS_IRQn);
-}
-
-void dcd_edpt_close_all(uint8_t rhport) {
-    (void)rhport;
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
-    (void)dev_addr;
-
-    // Response with zlp status
-    dcd_edpt_xfer(rhport, 0x80, NULL, 0);
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-}
-
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
-    (void)rhport;
-
-    if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
-        request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-        request->bRequest == TUSB_REQ_SET_ADDRESS) {
-        USBHSD->DEV_AD = (uint8_t)request->wValue;
-    }
-
-    EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK;
-    EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK;
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) {
-    (void)rhport;
-
-    uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-    uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
-    TU_ASSERT(epnum < EP_MAX);
-
-    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
-    xfer->max_size = tu_edpt_packet_size(desc_edpt);
-
-    if (epnum != 0) {
-        if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) {
-            EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK;
-        } else {
-            EP_TX_LEN(epnum) = 0;
-            EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
-        }
-    }
-
-    return true;
-}
-
-int usbd_ep_close(const uint8_t ep) {
-    (void)ep;
-
-    return 0;
-}
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
-    (void)rhport;
-
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    uint8_t const dir = tu_edpt_dir(ep_addr);
-
-    if (epnum == 0) {
-        if (dir == TUSB_DIR_OUT) {
-            USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL;
-        } else {
-            USBHSD->UEP0_TX_LEN = 0;
-            USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL;
-        }
-    } else {
-        if (dir == TUSB_DIR_OUT) {
-            EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL;
-
-        } else {
-            EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL;
-        }
-    }
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
-    (void)rhport;
-
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    uint8_t const dir = tu_edpt_dir(ep_addr);
-
-    if (epnum == 0) {
-        if (dir == TUSB_DIR_OUT) {
-            USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
-        } else {
-        }
-    } else {
-        if (dir == TUSB_DIR_OUT) {
-            EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK;
-
-        } else {
-            EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK;
-        }
-    }
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
-    (void)rhport;
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    uint8_t const dir = tu_edpt_dir(ep_addr);
-
-    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
-    xfer->buffer = buffer;
-    // xfer->ff           = NULL; // TODO support dcd_edpt_xfer_fifo API
-    xfer->total_len = total_bytes;
-    xfer->queued_len = 0;
-    xfer->short_packet = false;
-
-    // uint16_t num_packets = (total_bytes / xfer->max_size);
-    uint16_t short_packet_size = total_bytes % (xfer->max_size + 1);
-
-    // Zero-size packet is special case.
-    if (short_packet_size == 0 || (total_bytes == 0)) {
-        xfer->short_packet = true;
-    }
-
-    if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
-        if (!total_bytes) {
-            xfer->short_packet = true;
-            if (epnum == 0) {
-                USBHSD->UEP0_TX_LEN = 0;
-                USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
-                USBHS_Dev_Endp0_Tog ^= 1;
-            } else {
-                EP_TX_LEN(epnum) = 0;
-                EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
-            }
-        } else {
-            if (epnum == 0) {
-                xfer->queued_len += short_packet_size;
-                memcpy(&EP0_DatabufHD[0], buffer, short_packet_size);
-
-                USBHSD->UEP0_TX_LEN = short_packet_size;
-                USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
-                USBHS_Dev_Endp0_Tog ^= 1;
-            } else {
-                xfer->queued_len += short_packet_size;
-
-                EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
-                USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
-                EP_TX_LEN(epnum) = short_packet_size;
-                EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
-            }
-        }
-    } else { /* TUSB_DIR_OUT */
-        if (epnum == 0) {
-            uint32_t read_count = USBHSD->RX_LEN;
-            read_count = TU_MIN(read_count, total_bytes);
-
-            if ((total_bytes == 8)) {
-                read_count = 8;
-                memcpy(buffer, &EP0_DatabufHD[0], 8);
-            } else {
-                memcpy(buffer, &EP0_DatabufHD[0], read_count);
-            }
-        } else {
-            EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer;
-            USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum);
-        }
-
-        // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes);
-    }
-    return true;
-}
-
-
-static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) {
-    // xfer->queued_len = xfer->total_len - remaining;
-
-    uint16_t remaining = xfer->total_len - xfer->queued_len;
-    uint16_t to_recv_size;
-
-    if (remaining <= xfer->max_size) {
-        // Avoid buffer overflow.
-        to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
-    } else {
-        // Room for full packet, choose recv_size based on what the microcontroller
-        // claims.
-        to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
-    }
-
-    if (to_recv_size) {
-    }
-
-    xfer->queued_len += xfer_size;
-
-    // Per USB spec, a short OUT packet (including length 0) is always
-    // indicative of the end of a transfer (at least for ctl, bulk, int).
-    xfer->short_packet = (xfer_size < xfer->max_size);
-}
-
-void dcd_int_handler(uint8_t rhport) {
-    (void)rhport;
-
-    uint32_t end_num, rx_token;
-    uint8_t intflag = 0;
-
-    intflag = USBHSD->INT_FG;
-
-    if (intflag & USBHS_TRANSFER_FLAG) {
-
-        end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP;
-        rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03;
-
-        uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0);
-
-        xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp));
-
-        if (rx_token == PID_OUT) {
-            uint16_t rx_len = USBHSD->RX_LEN;
-
-            receive_packet(xfer, rx_len);
-
-            if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
-                xfer->short_packet = false;
-
-                dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-            }
-
-            if (end_num == 0) {
-                USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
-            }
-
-        } else if (rx_token == PID_IN) {
-            if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
-                xfer->short_packet = false;
-                xfer->total_len = 0;
-                dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-
-                EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK;
-
-                if (end_num == 0) {
-                }
-            } else {
-                dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len);
-            }
-        }
-
-        USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */
-    } else if (intflag & USBHS_SETUP_FLAG) {
-        USBHS_Dev_Endp0_Tog = 1;
-        dcd_event_setup_received(0, EP0_DatabufHD, true);
-
-        USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
-    } else if (intflag & USBHS_DETECT_FLAG) {
-        USBHS_Dev_Endp0_Tog = 1;
-
-        xfer_status[0][TUSB_DIR_OUT].max_size = 64;
-        xfer_status[0][TUSB_DIR_IN].max_size = 64;
-
-        dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
-
-        USBHSD->DEV_AD = 0;
-        USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
-
-        USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */
-    } else if (intflag & USBHS_SUSPEND_FLAG) {
-        dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND };
-        dcd_event_handler(&event, true);
-
-        USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
-    }
-}
-
-#endif
diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c
new file mode 100644
index 000000000..1f1c0b876
--- /dev/null
+++ b/src/portable/wch/dcd_ch32_usbhs.c
@@ -0,0 +1,391 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && ((CFG_TUSB_MCU == OPT_MCU_CH32V307) || (CFG_TUSB_MCU == OPT_MCU_CH32F20X))
+#include "device/dcd.h"
+
+#include "ch32_usbhs_reg.h"
+
+
+// Max number of bi-directional endpoints including EP0
+#define EP_MAX 16
+
+typedef struct {
+    uint8_t *buffer;
+    // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
+    uint16_t total_len;
+    uint16_t queued_len;
+    uint16_t max_size;
+    bool short_packet;
+} xfer_ctl_t;
+
+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+static xfer_ctl_t xfer_status[EP_MAX][2];
+
+#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2)
+#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4)
+#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4)
+#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2)
+
+#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1))
+#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
+
+/* Endpoint Buffer */
+TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64];  // ep0(64)
+
+volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01;
+
+void dcd_init(uint8_t rhport) {
+    (void)rhport;
+
+    memset(&xfer_status, 0, sizeof(xfer_status));
+
+    USBHSD->HOST_CTRL = 0x00;
+    USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
+
+    USBHSD->CONTROL = 0;
+
+#if TUD_OPT_HIGH_SPEED
+    USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
+#else
+    #error OPT_MODE_FULL_SPEED not currently supported on CH32
+    USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
+#endif
+
+    USBHSD->INT_EN = 0;
+    USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN;
+
+    /* ALL endpoint enable */
+    USBHSD->ENDP_CONFIG = 0xffffffff;
+
+    USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
+    USBHSD->ENDP_TYPE = 0x00;
+    USBHSD->BUF_MODE = 0x00;
+
+    USBHSD->UEP0_MAX_LEN = 64;
+
+    USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD;
+
+    USBHSD->UEP0_TX_LEN = 0;
+    USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK;
+    USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
+
+    for (int ep = 1; ep < EP_MAX; ep++) {
+        EP_TX_LEN(ep) = 0;
+        EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
+        EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+
+        EP_RX_MAX_LEN(ep) = 512;
+    }
+
+    USBHSD->DEV_AD = 0;
+    USBHSD->CONTROL |= USBHS_DEV_PU_EN;
+}
+
+void dcd_int_enable(uint8_t rhport) {
+    (void)rhport;
+
+    NVIC_EnableIRQ(USBHS_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+    (void)rhport;
+
+    NVIC_DisableIRQ(USBHS_IRQn);
+}
+
+void dcd_edpt_close_all(uint8_t rhport) {
+    (void)rhport;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+    (void)dev_addr;
+
+    // Response with zlp status
+    dcd_edpt_xfer(rhport, 0x80, NULL, 0);
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
+    (void)rhport;
+
+    if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+        request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+        request->bRequest == TUSB_REQ_SET_ADDRESS) {
+        USBHSD->DEV_AD = (uint8_t)request->wValue;
+    }
+
+    EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK;
+    EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) {
+    (void)rhport;
+
+    uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
+    uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
+
+    TU_ASSERT(epnum < EP_MAX);
+
+    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+    xfer->max_size = tu_edpt_packet_size(desc_edpt);
+
+    if (epnum != 0) {
+        if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) {
+            EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK;
+        } else {
+            EP_TX_LEN(epnum) = 0;
+            EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+        }
+    }
+
+    return true;
+}
+
+int usbd_ep_close(const uint8_t ep) {
+    (void)ep;
+
+    return 0;
+}
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+    (void)rhport;
+
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    if (epnum == 0) {
+        if (dir == TUSB_DIR_OUT) {
+            USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL;
+        } else {
+            USBHSD->UEP0_TX_LEN = 0;
+            USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL;
+        }
+    } else {
+        if (dir == TUSB_DIR_OUT) {
+            EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL;
+
+        } else {
+            EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL;
+        }
+    }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+    (void)rhport;
+
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    if (epnum == 0) {
+        if (dir == TUSB_DIR_OUT) {
+            USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
+        } else {
+        }
+    } else {
+        if (dir == TUSB_DIR_OUT) {
+            EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK;
+
+        } else {
+            EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK;
+        }
+    }
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
+    (void)rhport;
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+    xfer->buffer = buffer;
+    // xfer->ff           = NULL; // TODO support dcd_edpt_xfer_fifo API
+    xfer->total_len = total_bytes;
+    xfer->queued_len = 0;
+    xfer->short_packet = false;
+
+    // uint16_t num_packets = (total_bytes / xfer->max_size);
+    uint16_t short_packet_size = total_bytes % (xfer->max_size + 1);
+
+    // Zero-size packet is special case.
+    if (short_packet_size == 0 || (total_bytes == 0)) {
+        xfer->short_packet = true;
+    }
+
+    if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
+        if (!total_bytes) {
+            xfer->short_packet = true;
+            if (epnum == 0) {
+                USBHSD->UEP0_TX_LEN = 0;
+                USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
+                USBHS_Dev_Endp0_Tog ^= 1;
+            } else {
+                EP_TX_LEN(epnum) = 0;
+                EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
+            }
+        } else {
+            if (epnum == 0) {
+                xfer->queued_len += short_packet_size;
+                memcpy(&EP0_DatabufHD[0], buffer, short_packet_size);
+
+                USBHSD->UEP0_TX_LEN = short_packet_size;
+                USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
+                USBHS_Dev_Endp0_Tog ^= 1;
+            } else {
+                xfer->queued_len += short_packet_size;
+
+                EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
+                USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
+                EP_TX_LEN(epnum) = short_packet_size;
+                EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
+            }
+        }
+    } else { /* TUSB_DIR_OUT */
+        if (epnum == 0) {
+            uint32_t read_count = USBHSD->RX_LEN;
+            read_count = TU_MIN(read_count, total_bytes);
+
+            if ((total_bytes == 8)) {
+                read_count = 8;
+                memcpy(buffer, &EP0_DatabufHD[0], 8);
+            } else {
+                memcpy(buffer, &EP0_DatabufHD[0], read_count);
+            }
+        } else {
+            EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer;
+            USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum);
+        }
+
+        // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes);
+    }
+    return true;
+}
+
+
+static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) {
+    // xfer->queued_len = xfer->total_len - remaining;
+
+    uint16_t remaining = xfer->total_len - xfer->queued_len;
+    uint16_t to_recv_size;
+
+    if (remaining <= xfer->max_size) {
+        // Avoid buffer overflow.
+        to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
+    } else {
+        // Room for full packet, choose recv_size based on what the microcontroller
+        // claims.
+        to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
+    }
+
+    if (to_recv_size) {
+    }
+
+    xfer->queued_len += xfer_size;
+
+    // Per USB spec, a short OUT packet (including length 0) is always
+    // indicative of the end of a transfer (at least for ctl, bulk, int).
+    xfer->short_packet = (xfer_size < xfer->max_size);
+}
+
+void dcd_int_handler(uint8_t rhport) {
+    (void)rhport;
+
+    uint32_t end_num, rx_token;
+    uint8_t intflag = 0;
+
+    intflag = USBHSD->INT_FG;
+
+    if (intflag & USBHS_TRANSFER_FLAG) {
+
+        end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP;
+        rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03;
+
+        uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0);
+
+        xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp));
+
+        if (rx_token == PID_OUT) {
+            uint16_t rx_len = USBHSD->RX_LEN;
+
+            receive_packet(xfer, rx_len);
+
+            if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
+                xfer->short_packet = false;
+
+                dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+            }
+
+            if (end_num == 0) {
+                USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
+            }
+
+        } else if (rx_token == PID_IN) {
+            if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
+                xfer->short_packet = false;
+                xfer->total_len = 0;
+                dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+
+                EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK;
+
+                if (end_num == 0) {
+                }
+            } else {
+                dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len);
+            }
+        }
+
+        USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */
+    } else if (intflag & USBHS_SETUP_FLAG) {
+        USBHS_Dev_Endp0_Tog = 1;
+        dcd_event_setup_received(0, EP0_DatabufHD, true);
+
+        USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
+    } else if (intflag & USBHS_DETECT_FLAG) {
+        USBHS_Dev_Endp0_Tog = 1;
+
+        xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+        xfer_status[0][TUSB_DIR_IN].max_size = 64;
+
+        dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
+
+        USBHSD->DEV_AD = 0;
+        USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
+
+        USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */
+    } else if (intflag & USBHS_SUSPEND_FLAG) {
+        dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND };
+        dcd_event_handler(&event, true);
+
+        USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
+    }
+}
+
+#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a41f5a07e..f4b1a1dd4 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -169,6 +169,7 @@
 
 // WCH
 #define OPT_MCU_CH32V307         2200 ///< WCH CH32V307
+#define OPT_MCU_CH32F20X         2210 ///< WCH CH32F20x
 
 
 // NXP LPC MCX
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 1fac291a3..af3043e4e 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -164,6 +164,9 @@ deps_optional = {
     'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git',
                             '17761f5cf9dbbf2dcf665b7c04934188add20082',
                             'ch32v307'],
+    'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git',
+                            '77c4095087e5ed2c548ec9058e655d0b8757663b',
+                            'ch32f20x'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
                     'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index 4919fe7b4..c3683c3d7 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -164,8 +164,8 @@
         <group name="src/portable/valentyusb/eptri">
             <path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
         </group>
-        <group name="src/portable/wch/ch32v307">
-            <path>$TUSB_DIR$/src/portable/wch/ch32v307/dcd_usbhs.c</path>
+        <group name="src/portable/wch">
+            <path>$TUSB_DIR$/src/portable/wch/dcd_ch32_usbhs.c</path>
         </group>
         <group name="src/typec">
             <path>$TUSB_DIR$/src/typec/usbc.c</path>
-- 
cgit v1.3.1


From 8b2cb63da88c0f790fee8d514971153569993b05 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 10 Oct 2023 18:22:20 +0200
Subject: Fix naming nBytesPerSample.

---
 src/class/audio/audio_device.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 46fd6dfa9..5d3772a9d 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -631,9 +631,9 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 // Decoding according to 2.3.1.5 Audio Streams
 
 // Helper function
-static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesPerSample, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used)
 {
-  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2)
   uint16_t * dst16 = dst;
   uint16_t * src16 = src;
   const uint16_t * dst_end16 = dst_end;
@@ -641,7 +641,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
   uint32_t * src32 = src;
   const uint32_t * dst_end32 = dst_end;
 
-  if (nBytesToCopy == 1)
+  if (nBytesPerSample == 1)
   {
     while(dst16 < dst_end16)
     {
@@ -650,7 +650,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
     }
     return src16;
   }
-  else if (nBytesToCopy == 2)
+  else if (nBytesPerSample == 2)
   {
     while(dst32 < dst_end32)
     {
@@ -659,7 +659,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
     }
     return src32;
   }
-  else if (nBytesToCopy == 3)
+  else if (nBytesPerSample == 3)
   {
     while(dst16 < dst_end16)
     {
@@ -670,7 +670,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
     }
     return src16;
   }
-  else // nBytesToCopy == 4
+  else // nBytesPerSample == 4
   {
     while(dst32 < dst_end32)
     {
@@ -926,9 +926,9 @@ range [-1, +1)
  * */
 
 // Helper function
-static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, void * src, const void * src_end, void * dst, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesPerSample, void * src, const void * src_end, void * dst, uint8_t const n_ff_used)
 {
-  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2)
   uint16_t * dst16 = dst;
   uint16_t * src16 = src;
   const uint16_t * src_end16 = src_end;
@@ -936,7 +936,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
   uint32_t * src32 = src;
   const uint32_t * src_end32 = src_end;
 
-  if (nBytesToCopy == 1)
+  if (nBytesPerSample == 1)
   {
     while(src16 < src_end16)
     {
@@ -945,7 +945,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
     }
     return dst16;
   }
-  else if (nBytesToCopy == 2)
+  else if (nBytesPerSample == 2)
   {
     while(src32 < src_end32)
     {
@@ -954,7 +954,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
     }
     return dst32;
   }
-  else if (nBytesToCopy == 3)
+  else if (nBytesPerSample == 3)
   {
     while(src16 < src_end16)
     {
@@ -965,7 +965,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
     }
     return dst16;
   }
-  else // nBytesToCopy == 4
+  else // nBytesPerSample == 4
   {
     while(src32 < src_end32)
     {
-- 
cgit v1.3.1


From 656e1e416aa9dbd7ba4c18e777f7294a101f0667 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 09:46:01 +0200
Subject: Add flow control for IN transfer.

---
 examples/device/audio_4_channel_mic/src/main.c     |  30 ++++-
 .../audio_4_channel_mic/src/plot_audio_samples.py  |   7 +-
 .../device/audio_4_channel_mic/src/tusb_config.h   |  15 ++-
 src/class/audio/audio_device.c                     | 140 ++++++++++++++++++---
 src/class/audio/audio_device.h                     |  16 +++
 5 files changed, 187 insertions(+), 21 deletions(-)

(limited to 'src')

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 4bcbdb692..52e6d71f7 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -69,8 +69,13 @@ uint8_t clkValid;
 audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
 audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
 
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
 // Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
 uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2];   // Ensure half word aligned
+#else
+// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_EP_SZ_IN];   // Ensure half word aligned
+#endif
 
 void led_blinking_task(void);
 void audio_task(void);
@@ -97,6 +102,7 @@ int main(void)
   sampleFreqRng.subrange[0].bRes = 0;
 
   // Generate dummy data
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
   uint16_t * p_buff = i2s_dummy_buffer[0];
   uint16_t dataVal = 1;
   for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
@@ -116,6 +122,23 @@ int main(void)
     float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
     *p_buff++ = (uint16_t)(sinf(t) * 25) + 200;
   }
+#else
+  uint16_t * p_buff = i2s_dummy_buffer;
+  uint16_t dataVal = 1;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal++;
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170;
+    // CH4 sinus wave
+    float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = (uint16_t)(sinf(t) * 25) + 200;
+  }
+#endif
 
   while (1)
   {
@@ -384,6 +407,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         {
           case AUDIO_CS_REQ_CUR:
             TU_LOG2("    Get Sample Freq.\r\n");
+            // Set sample rate for flow control
+            tud_audio_set_tx_flow_control(sampFreq);
             return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
 
           case AUDIO_CS_REQ_RANGE:
@@ -429,12 +454,15 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   //    tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
   // }
 
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
   // Write I2S buffer into FIFO
   for (uint8_t cnt=0; cnt < 2; cnt++)
   {
     tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
   }
-
+#else
+  tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
+#endif
   return true;
 }
 
diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
index a3a2b2fd4..d17a908b6 100644
--- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
+++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
@@ -10,11 +10,11 @@ if __name__ == '__main__':
     # print(sd.query_devices())
 
     fs = 48000  		# Sample rate
-    duration = 20e-3   # Duration of recording
+    duration = 1   # Duration of recording
 
     if platform.system() == 'Windows':
         # WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows)
-        device = 'Microphone (MicNode_4_Ch), Windows WDM-KS'
+        device = 'Microphone (MicNode_4_Ch), Windows WASAPI'
     elif platform.system() == 'Darwin':
         device = 'MicNode_4_Ch'
     else:
@@ -28,8 +28,7 @@ if __name__ == '__main__':
 
     time = np.arange(0, duration, 1 / fs)  # time vector
     # strip starting zero
-    myrecording = myrecording[100:]
-    time = time[100:]
+
     plt.plot(time, myrecording)
     plt.xlabel('Time [s]')
     plt.ylabel('Amplitude')
diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 291ac4f79..d1e19c5a1 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -114,14 +114,25 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX    2         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_ENABLE_ENCODING                 0
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          CFG_TUD_AUDIO_EP_SZ_IN
 
-#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
 #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
 #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+
+#else
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             4 * CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN
+
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 5d3772a9d..9299440c9 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -364,14 +364,21 @@ typedef struct
 #endif
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  uint32_t sample_rate_tx;
+  uint16_t packet_sz_tx[3];
+  uint8_t bclock_id_tx;
+  uint8_t interval_tx;
+#endif
+
   // Encoding parameters - parameters are set when alternate AS interface is set by host
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL)
   audio_format_type_t format_type_tx;
   uint8_t n_channels_tx;
+  uint8_t n_bytes_per_sampe_tx;
 
 #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
   audio_data_format_type_I_t format_type_I_tx;
-  uint8_t n_bytes_per_sampe_tx;
   uint8_t n_channels_per_ff_tx;
   uint8_t n_ff_used_tx;
 #endif
@@ -444,7 +451,7 @@ static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id);
 static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id);
 static uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio);
 
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
 static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * p_desc, uint8_t const * p_desc_end, uint8_t const as_itf);
 
 static inline uint8_t tu_desc_subtype(void const* desc)
@@ -453,6 +460,10 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size);
+#endif
+
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq);
 #endif
@@ -821,6 +832,57 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1
 
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+
+bool tud_audio_n_set_tx_flow_control(uint8_t func_id, uint32_t sample_rate)
+{
+  TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
+  audiod_function_t* audio = &_audiod_fct[func_id];
+
+  TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
+  TU_VERIFY(audio->n_channels_tx);
+  TU_VERIFY(audio->n_bytes_per_sampe_tx);
+  TU_VERIFY(audio->interval_tx);
+
+  if (sample_rate == 0)
+  {
+    audio->packet_sz_tx[0] = 0;
+    audio->packet_sz_tx[1] = 0;
+    audio->packet_sz_tx[2] = 0;
+    return false;
+  }
+
+  const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
+
+  const uint32_t sample_normimal = sample_rate * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+  const uint32_t sample_reminder = sample_rate * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+
+  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+
+  TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
+
+  // Frmt20.pdf 2.3.1.1 USB Packets
+  if (sample_reminder)
+  {
+    // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots
+    audio->packet_sz_tx[0] = packet_sz_tx_norm;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
+  } else
+  {
+    // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav)
+    // (medium VFP) and INT(nav)+1 (large VFP).
+    audio->packet_sz_tx[0] = packet_sz_tx_min;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
+  }
+
+  return true;
+}
+
+#endif
 
 // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission.
 // If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write.
@@ -886,9 +948,16 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
 
 #else
   // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule
-
+#if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  uint16_t tgt_packet_sz;
+  // packet_sz_tx is based on total packet size, here we want size for each support buffer.
+  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, &tgt_packet_sz))
+    n_bytes_tx = tgt_packet_sz;
+  else
+    n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);
+#else
   n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);      // Limit up to max packet size, more can not be done for ISO
-
+#endif
 #if USE_LINEAR_BUFFER_TX
   tu_fifo_read_n(&audio->ep_in_ff, audio->lin_buf_in, n_bytes_tx);
   TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, n_bytes_tx));
@@ -987,7 +1056,6 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
 
   // Determine amount of samples
   uint8_t const n_ff_used               = audio->n_ff_used_tx;
-  uint16_t const nBytesToCopy           = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
   uint16_t const capPerFF               = audio->ep_in_sz / n_ff_used;                                        // Sample capacity per FIFO in bytes
   uint16_t nBytesPerFFToSend            = tu_fifo_count(&audio->tx_supp_ff[0]);
   uint8_t cnt_ff;
@@ -1001,14 +1069,24 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
     }
   }
 
-  // Check if there is enough
+#if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  uint16_t tgt_packet_sz;
+  // packet_sz_tx is based on total packet size, here we want size for each support buffer.
+  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, nBytesPerFFToSend * n_ff_used, audio->tx_supp_ff[0].depth * n_ff_used, &tgt_packet_sz))
+    nBytesPerFFToSend = tgt_packet_sz / n_ff_used;
+#endif
+
+  // Check if there is enough data
   if (nBytesPerFFToSend == 0)    return 0;
 
   // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT!
   nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, capPerFF);
 
+#if !CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
   // Round to full number of samples (flooring)
-  nBytesPerFFToSend = (nBytesPerFFToSend / nBytesToCopy) * nBytesToCopy;
+  uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
+  nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize;
+#endif
 
   // Encode
   uint8_t * dst;
@@ -1489,6 +1567,9 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   #if CFG_TUD_AUDIO_ENABLE_EP_IN
                 ep_in = desc_ep->bEndpointAddress;
                 ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
+    #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+                _audiod_fct[i].interval_tx = desc_ep->bInterval;
+    #endif
   #endif
               } else
               {
@@ -1607,6 +1688,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
     audio->ep_in = 0;                           // Necessary?
 
+  #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+    audio->packet_sz_tx[0] = 0;
+    audio->packet_sz_tx[1] = 0;
+    audio->packet_sz_tx[2] = 0;
+  #endif
   }
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN
 
@@ -1657,7 +1743,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     // Find correct interface
     if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt)
     {
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
+#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
       uint8_t const * p_desc_parse_for_params = p_desc;
 #endif
       // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary
@@ -1686,12 +1772,13 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             audio->ep_in_sz = tu_edpt_packet_size(desc_ep);
 
             // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters
-  #if CFG_TUD_AUDIO_ENABLE_ENCODING
+  #if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
             audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf);
 
             // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
-    #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-            const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx);
+    #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+            const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx))
+               * (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx));
             for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
             {
               tu_fifo_config(&audio->tx_supp_ff[cnt], audio->tx_supp_ff[cnt].buffer, active_fifo_depth, 1, true);
@@ -2404,7 +2491,7 @@ static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id)
   return false;
 }
 
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
 // p_desc points to the AS interface of alternate setting zero
 // itf is the interface number of the corresponding interface - we check if the interface belongs to EP in or EP out to see if it is a TX or RX parameter
 // Currently, only AS interfaces with an EP (in or out) are supposed to be parsed for!
@@ -2455,7 +2542,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
     }
 
     // Look for a Type I Format Type Descriptor(2.3.1.6 - Audio Formats)
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
     if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_FORMAT_TYPE && ((audio_desc_type_I_format_t const * )p_desc)->bFormatType == AUDIO_FORMAT_TYPE_I)
     {
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -2491,6 +2578,31 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size)
+{
+  TU_VERIFY(norminal_size[1]);
+
+  // This flow control method need a FIFO size of 4*Navg
+  TU_VERIFY(norminal_size[1] <= fifo_size * 4);
+
+  if (data_size < norminal_size[0])
+    *packet_size = 0;
+  else
+  {
+    uint16_t slot_size = norminal_size[2] - norminal_size[1];
+    if (data_size < fifo_size / 2 - slot_size)
+      *packet_size = norminal_size[0];
+    else if (data_size > fifo_size / 2 + slot_size)
+      *packet_size = norminal_size[2];
+    else
+      *packet_size = norminal_size[1];
+  }
+
+  return true;
+}
+#endif
+
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 7c88b99fc..4cb3ca84c 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -181,6 +181,11 @@
 #endif
 #endif
 
+// (For TYPE-I format only) Flow control is necessary to allow IN ep send correct amount of data, unless it's a virtual device where data is perfectly synchronized to USB clock.
+#ifndef CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL  1
+#endif
+
 // Enable/disable feedback EP (required for asynchronous RX applications)
 #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                    0                             // Feedback - 0 or 1
@@ -392,6 +397,10 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_i
 uint16_t    tud_audio_int_ctr_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+bool tud_audio_n_set_tx_flow_control       (uint8_t func_id, uint32_t sample_rate);
+#endif
+
 //--------------------------------------------------------------------+
 // Application API (Interface0)
 //--------------------------------------------------------------------+
@@ -670,6 +679,13 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+static inline bool tud_audio_set_tx_flow_control(uint32_t sample_rate)
+{
+  return tud_audio_n_set_tx_flow_control(0, sample_rate);
+}
+#endif
+
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 static inline bool tud_audio_fb_set(uint32_t feedback)
-- 
cgit v1.3.1


From 0a1d6cf4d028bce2248da01b8cc13aa4673e61b5 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 13:06:55 +0200
Subject: Read sample rate directly from control transfer to eliminate
 callback.

---
 examples/device/audio_4_channel_mic/src/main.c |   5 +-
 src/class/audio/audio_device.c                 | 301 ++++++++++++++-----------
 src/class/audio/audio_device.h                 |  10 -
 3 files changed, 173 insertions(+), 143 deletions(-)

(limited to 'src')

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 52e6d71f7..9c37315c8 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -407,9 +407,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         {
           case AUDIO_CS_REQ_CUR:
             TU_LOG2("    Get Sample Freq.\r\n");
-            // Set sample rate for flow control
-            tud_audio_set_tx_flow_control(sampFreq);
-            return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+            // Buffered control transfer is needed for IN flow control to work
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
 
           case AUDIO_CS_REQ_RANGE:
             TU_LOG2("    Get Sample Freq. range\r\n");
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9299440c9..e246281be 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -461,7 +461,8 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size);
+static bool audiod_calc_tx_packet_sz(audiod_function_t* audio);
+static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_size);
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
@@ -832,58 +833,6 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1
 
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-
-bool tud_audio_n_set_tx_flow_control(uint8_t func_id, uint32_t sample_rate)
-{
-  TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
-  audiod_function_t* audio = &_audiod_fct[func_id];
-
-  TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
-  TU_VERIFY(audio->n_channels_tx);
-  TU_VERIFY(audio->n_bytes_per_sampe_tx);
-  TU_VERIFY(audio->interval_tx);
-
-  if (sample_rate == 0)
-  {
-    audio->packet_sz_tx[0] = 0;
-    audio->packet_sz_tx[1] = 0;
-    audio->packet_sz_tx[2] = 0;
-    return false;
-  }
-
-  const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
-
-  const uint32_t sample_normimal = sample_rate * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
-  const uint32_t sample_reminder = sample_rate * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
-
-  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-
-  TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
-
-  // Frmt20.pdf 2.3.1.1 USB Packets
-  if (sample_reminder)
-  {
-    // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots
-    audio->packet_sz_tx[0] = packet_sz_tx_norm;
-    audio->packet_sz_tx[1] = packet_sz_tx_norm;
-    audio->packet_sz_tx[2] = packet_sz_tx_max;
-  } else
-  {
-    // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav)
-    // (medium VFP) and INT(nav)+1 (large VFP).
-    audio->packet_sz_tx[0] = packet_sz_tx_min;
-    audio->packet_sz_tx[1] = packet_sz_tx_norm;
-    audio->packet_sz_tx[2] = packet_sz_tx_max;
-  }
-
-  return true;
-}
-
-#endif
-
 // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission.
 // If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write.
 
@@ -949,12 +898,8 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
 #else
   // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule
 #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-  uint16_t tgt_packet_sz;
   // packet_sz_tx is based on total packet size, here we want size for each support buffer.
-  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, &tgt_packet_sz))
-    n_bytes_tx = tgt_packet_sz;
-  else
-    n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);
+  n_bytes_tx = audiod_tx_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, audio->ep_in_sz);
 #else
   n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);      // Limit up to max packet size, more can not be done for ISO
 #endif
@@ -1056,7 +1001,6 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
 
   // Determine amount of samples
   uint8_t const n_ff_used               = audio->n_ff_used_tx;
-  uint16_t const capPerFF               = audio->ep_in_sz / n_ff_used;                                        // Sample capacity per FIFO in bytes
   uint16_t nBytesPerFFToSend            = tu_fifo_count(&audio->tx_supp_ff[0]);
   uint8_t cnt_ff;
 
@@ -1070,19 +1014,18 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
   }
 
 #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-  uint16_t tgt_packet_sz;
+  const uint16_t norm_packet_sz_tx[3] = {audio->packet_sz_tx[0] / n_ff_used,
+                                         audio->packet_sz_tx[1] / n_ff_used,
+                                         audio->packet_sz_tx[2] / n_ff_used};
   // packet_sz_tx is based on total packet size, here we want size for each support buffer.
-  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, nBytesPerFFToSend * n_ff_used, audio->tx_supp_ff[0].depth * n_ff_used, &tgt_packet_sz))
-    nBytesPerFFToSend = tgt_packet_sz / n_ff_used;
-#endif
-
+  nBytesPerFFToSend = audiod_tx_packet_size(norm_packet_sz_tx, nBytesPerFFToSend, audio->tx_supp_ff[0].depth, audio->ep_in_sz / n_ff_used);
+  // Check if there is enough data
+  if (nBytesPerFFToSend == 0)    return 0;
+#else
   // Check if there is enough data
   if (nBytesPerFFToSend == 0)    return 0;
-
   // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT!
-  nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, capPerFF);
-
-#if !CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, audio->ep_in_sz / n_ff_used);
   // Round to full number of samples (flooring)
   uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
   nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize;
@@ -1349,7 +1292,7 @@ void audiod_init(void)
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
 
     // Set encoding parameters for Type_I formats
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
     switch (i)
     {
 #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
@@ -1529,85 +1472,115 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       }
 
 #if USE_ISO_EP_ALLOCATION
+      {
   #if CFG_TUD_AUDIO_ENABLE_EP_IN
-      uint8_t  ep_in = 0;
-      uint16_t ep_in_size = 0;
+        uint8_t  ep_in = 0;
+        uint16_t ep_in_size = 0;
   #endif
 
   #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-      uint8_t  ep_out = 0;
-      uint16_t ep_out_size = 0;
+        uint8_t  ep_out = 0;
+        uint16_t ep_out_size = 0;
   #endif
 
   #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-      uint8_t ep_fb = 0;
+        uint8_t ep_fb = 0;
   #endif
-
-      uint8_t const *p_desc = _audiod_fct[i].p_desc;
-      uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
-      while (p_desc < p_desc_end)
-      {
-        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        while (p_desc < p_desc_end)
         {
-          tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-          if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
           {
-  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-            // Explicit feedback EP
-            if (desc_ep->bmAttributes.usage == 1)
+            tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
             {
-              ep_fb = desc_ep->bEndpointAddress;
-            }
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+              // Explicit feedback EP
+              if (desc_ep->bmAttributes.usage == 1)
+              {
+                ep_fb = desc_ep->bEndpointAddress;
+              }
   #endif
-            // Data EP
-            if (desc_ep->bmAttributes.usage == 0)
-            {
-              if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+              // Data EP
+              if (desc_ep->bmAttributes.usage == 0)
               {
+                if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+                {
   #if CFG_TUD_AUDIO_ENABLE_EP_IN
-                ep_in = desc_ep->bEndpointAddress;
-                ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
-    #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-                _audiod_fct[i].interval_tx = desc_ep->bInterval;
-    #endif
+                  ep_in = desc_ep->bEndpointAddress;
+                  ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
   #endif
-              } else
-              {
+                } else
+                {
   #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-                ep_out = desc_ep->bEndpointAddress;
-                ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
+                  ep_out = desc_ep->bEndpointAddress;
+                  ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
   #endif
+                }
               }
-            }
 
+            }
           }
+
+          p_desc = tu_desc_next(p_desc);
         }
-        p_desc = tu_desc_next(p_desc);
-      }
 
   #if CFG_TUD_AUDIO_ENABLE_EP_IN
-      if (ep_in)
-      {
-        usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size);
-      }
+        if (ep_in)
+        {
+          usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size);
+        }
   #endif
 
   #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (ep_out)
-      {
-        usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size);
-      }
+        if (ep_out)
+        {
+          usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size);
+        }
   #endif
 
   #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-      if (ep_fb)
-      {
-        usbd_edpt_iso_alloc(rhport, ep_fb, 4);
-      }
+        if (ep_fb)
+        {
+          usbd_edpt_iso_alloc(rhport, ep_fb, 4);
+        }
   #endif
-
+      }
 #endif // USE_ISO_EP_ALLOCATION
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+      {
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        while (p_desc < p_desc_end)
+        {
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+          {
+            tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+            {
+              if (desc_ep->bmAttributes.usage == 0)
+              {
+                if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+                {
+                  _audiod_fct[i].interval_tx = desc_ep->bInterval;
+                }
+              }
+            }
+          } else
+          if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL)
+          {
+            if(tu_unaligned_read16(p_desc + 4) == AUDIO_TERM_TYPE_USB_STREAMING)
+            {
+               _audiod_fct[i].bclock_id_tx = p_desc[8];
+            }
+          }
+          p_desc = tu_desc_next(p_desc);
+        }
+      }
+#endif // CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+
       break;
     }
   }
@@ -1910,6 +1883,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   if (disable) usbd_sof_enable(rhport, false);
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  audiod_calc_tx_packet_sz(audio);
+#endif
+
   tud_control_status(rhport, p_request);
 
   return true;
@@ -2352,6 +2329,19 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
   // Copy into buffer
   TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, _audiod_fct[func_id].ctrl_buf_sz, data, (size_t)len));
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  // Find data for sampling_frequency_control
+  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
+  {
+    uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+    uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+    if (_audiod_fct[func_id].bclock_id_tx == entityID && ctrlSel == AUDIO_CS_CTRL_SAM_FREQ && p_request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(_audiod_fct[func_id].ctrl_buf);
+    }
+  }
+#endif
+
   // Schedule transmit
   return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len);
 }
@@ -2579,28 +2569,79 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size)
+
+static bool audiod_calc_tx_packet_sz(audiod_function_t* audio)
 {
-  TU_VERIFY(norminal_size[1]);
+  TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
+  TU_VERIFY(audio->n_channels_tx);
+  TU_VERIFY(audio->n_bytes_per_sampe_tx);
+  TU_VERIFY(audio->interval_tx);
+  TU_VERIFY(audio->sample_rate_tx);
 
-  // This flow control method need a FIFO size of 4*Navg
-  TU_VERIFY(norminal_size[1] <= fifo_size * 4);
+  const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
 
-  if (data_size < norminal_size[0])
-    *packet_size = 0;
-  else
+  const uint32_t sample_normimal = audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+  const uint32_t sample_reminder = audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+
+  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+
+  // Endpoint size must larger than packet size
+  TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
+
+  // Frmt20.pdf 2.3.1.1 USB Packets
+  if (sample_reminder)
   {
-    uint16_t slot_size = norminal_size[2] - norminal_size[1];
-    if (data_size < fifo_size / 2 - slot_size)
-      *packet_size = norminal_size[0];
-    else if (data_size > fifo_size / 2 + slot_size)
-      *packet_size = norminal_size[2];
-    else
-      *packet_size = norminal_size[1];
+    // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots
+    audio->packet_sz_tx[0] = packet_sz_tx_norm;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
+  } else
+  {
+    // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav)
+    // (medium VFP) and INT(nav)+1 (large VFP).
+    audio->packet_sz_tx[0] = packet_sz_tx_min;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
   }
 
   return true;
 }
+
+static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_depth)
+{
+  // Flow control need a FIFO size of at least 4*Navg
+  if(norminal_size[1] && norminal_size[1] <= fifo_depth * 4)
+  {
+    uint16_t packet_size;
+    uint16_t slot_size = norminal_size[2] - norminal_size[1];
+    if (data_count < fifo_depth / 2 - slot_size)
+    {
+      if (data_count < norminal_size[0])
+      {
+        // If you get here frequently, then your I2S clock deviation is too big !
+        packet_size = 0;
+      } else
+      {
+        packet_size = norminal_size[0];
+      }
+    }
+    else if (data_count > fifo_depth / 2 + slot_size)
+    {
+      packet_size = norminal_size[2];
+    } else
+    {
+      packet_size = norminal_size[1];
+    }
+    // Normally this cap is not necessary
+    return tu_min16(packet_size, max_depth);
+  } else
+  {
+    return tu_min16(data_count, max_depth);
+  }
+}
+
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 4cb3ca84c..ef3e12a06 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -397,9 +397,6 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_i
 uint16_t    tud_audio_int_ctr_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-bool tud_audio_n_set_tx_flow_control       (uint8_t func_id, uint32_t sample_rate);
-#endif
 
 //--------------------------------------------------------------------+
 // Application API (Interface0)
@@ -679,13 +676,6 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-static inline bool tud_audio_set_tx_flow_control(uint32_t sample_rate)
-{
-  return tud_audio_n_set_tx_flow_control(0, sample_rate);
-}
-#endif
-
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 static inline bool tud_audio_fb_set(uint32_t feedback)
-- 
cgit v1.3.1


From d83a2107883c8a6224ab99f248a59b216a8d2a82 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 15:18:05 +0200
Subject: Add blackout time.

---
 src/class/audio/audio_device.c | 30 ++++++++++++++++++++++--------
 1 file changed, 22 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index e246281be..d32ed56b2 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2614,25 +2614,39 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da
   // Flow control need a FIFO size of at least 4*Navg
   if(norminal_size[1] && norminal_size[1] <= fifo_depth * 4)
   {
+    // Use blackout to prioritize normal size packet
+    static int ctrl_blackout = 0;
     uint16_t packet_size;
     uint16_t slot_size = norminal_size[2] - norminal_size[1];
-    if (data_count < fifo_depth / 2 - slot_size)
+    if (data_count < norminal_size[0])
     {
-      if (data_count < norminal_size[0])
-      {
         // If you get here frequently, then your I2S clock deviation is too big !
         packet_size = 0;
+    } else
+    if (data_count < fifo_depth / 2 - slot_size && !ctrl_blackout)
+    {
+      packet_size = norminal_size[0];
+      ctrl_blackout = 10;
+    } else
+    if (data_count > fifo_depth / 2 + slot_size && !ctrl_blackout)
+    {
+      packet_size = norminal_size[2];
+      if(norminal_size[0] == norminal_size[1])
+      {
+        // nav = INT(nav) + 1
+        ctrl_blackout = 2;
       } else
       {
-        packet_size = norminal_size[0];
+        // nav = INT(nav)
+        ctrl_blackout = 10;
       }
-    }
-    else if (data_count > fifo_depth / 2 + slot_size)
-    {
-      packet_size = norminal_size[2];
     } else
     {
       packet_size = norminal_size[1];
+      if (ctrl_blackout)
+      {
+        ctrl_blackout--;
+      }
     }
     // Normally this cap is not necessary
     return tu_min16(packet_size, max_depth);
-- 
cgit v1.3.1


From e9d894fe6620d623bc393698a971d08d43516e01 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 15:23:05 +0200
Subject: Fix compile.

---
 .../device/audio_4_channel_mic/src/tusb_config.h   |  5 +++--
 src/class/audio/audio_device.c                     | 26 +++++++++++-----------
 2 files changed, 16 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index d1e19c5a1..f86b63528 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -115,7 +115,8 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 
-#define CFG_TUD_AUDIO_ENABLE_ENCODING                 0
+#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL              1
 
 #if CFG_TUD_AUDIO_ENABLE_ENCODING
 
@@ -129,7 +130,7 @@ extern "C" {
 
 #else
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             4 * CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN
 
 #endif
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index d32ed56b2..220771aec 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -217,7 +217,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 // Software encoding/decoding support FIFOs
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
   #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -225,7 +225,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -233,7 +233,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -243,7 +243,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
   #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -251,7 +251,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -259,7 +259,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -2519,7 +2519,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
       }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
       if (as_itf == audio->ep_out_as_intf_num)
       {
         audio->n_channels_rx = ((audio_desc_cs_as_interface_t const * )p_desc)->bNrChannels;
@@ -2552,7 +2552,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
       }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
       if (as_itf == audio->ep_out_as_intf_num)
       {
         audio->n_bytes_per_sampe_rx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
@@ -2580,12 +2580,12 @@ static bool audiod_calc_tx_packet_sz(audiod_function_t* audio)
 
   const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
 
-  const uint32_t sample_normimal = audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
-  const uint32_t sample_reminder = audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+  const uint16_t sample_normimal = (uint16_t)(audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
+  const uint16_t sample_reminder = (uint16_t)(audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
 
-  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_min = (uint16_t)((sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
+  const uint16_t packet_sz_tx_norm = (uint16_t)(sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
+  const uint16_t packet_sz_tx_max = (uint16_t)((sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
 
   // Endpoint size must larger than packet size
   TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
-- 
cgit v1.3.1


From ade8a19aefa91e4aba0bbb0ddeafbcd041c6a4c3 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 21:21:52 +0200
Subject: Put sw_buf in USB section only if necessary.

---
 src/class/audio/audio_device.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 220771aec..9712afde9 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -110,24 +110,36 @@
 #error Maximum number of audio functions restricted to three!
 #endif
 
+// Put sw_buf in USB section only if necessary
+#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING
+#define IN_SW_BUF_MEM_SECTION
+#else
+#define IN_SW_BUF_MEM_SECTION CFG_TUD_MEM_SECTION
+#endif
+#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING
+#define OUT_SW_BUF_MEM_SECTION
+#else
+#define OUT_SW_BUF_MEM_SECTION CFG_TUD_MEM_SECTION
+#endif
+
 // EP IN software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
   #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
+    IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO
     #endif
   #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
+    IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO
     #endif
   #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
+    IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO
     #endif
@@ -154,21 +166,21 @@
 // EP OUT software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
   #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+    OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO
     #endif
   #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
+    OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO
     #endif
   #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
+    OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO
     #endif
-- 
cgit v1.3.1


From f88a5bb03b2504df272d2cd285b17e66f11dfc64 Mon Sep 17 00:00:00 2001
From: Shawn Hoffman <godisgovernment@gmail.com>
Date: Tue, 17 Oct 2023 19:26:11 -0700
Subject: hid_device: use separate buffer for SET_REPORT instead of epout

---
 src/class/hid/hid_device.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 2d46d760f..c939c0117 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -52,6 +52,7 @@ typedef struct
 
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE];
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t set_report_buf[CFG_TUD_HID_EP_BUFSIZE];
 
   // TODO save hid descriptor since host can specifically request this after enumeration
   // Note: HID descriptor may be not available from application after enumeration
@@ -307,15 +308,15 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
       case  HID_REQ_CONTROL_SET_REPORT:
         if ( stage == CONTROL_STAGE_SETUP )
         {
-          TU_VERIFY(request->wLength <= sizeof(p_hid->epout_buf));
-          tud_control_xfer(rhport, request, p_hid->epout_buf, request->wLength);
+          TU_VERIFY(request->wLength <= sizeof(p_hid->set_report_buf));
+          tud_control_xfer(rhport, request, p_hid->set_report_buf, request->wLength);
         }
         else if ( stage == CONTROL_STAGE_ACK )
         {
           uint8_t const report_type = tu_u16_high(request->wValue);
           uint8_t const report_id   = tu_u16_low(request->wValue);
 
-          uint8_t const* report_buf = p_hid->epout_buf;
+          uint8_t const* report_buf = p_hid->set_report_buf;
           uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
 
           // If host request a specific Report ID, extract report ID in buffer before invoking callback
-- 
cgit v1.3.1


From 27a2c8cba4dc7c56509bb3d9b6415a6fe8f638ac Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 18 Oct 2023 18:43:07 +0700
Subject: adding nulceo stm32u5a5, fix clock configure issue

dwc2 core stuck at reset
---
 hw/bsp/stm32u5/boards/stm32u575eval/board.h        |  15 +-
 hw/bsp/stm32u5/boards/stm32u575nucleo/board.h      |  15 +-
 .../boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld | 167 ++++++++++
 hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake  |   2 +-
 hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h      |  57 ++--
 hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk     |   2 +-
 .../stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc     | 352 +++++++++++++++++++++
 hw/bsp/stm32u5/family.c                            |  53 +++-
 src/common/tusb_mcu.h                              |  13 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h            |  10 +-
 src/tusb_option.h                                  |   6 +-
 tools/get_deps.py                                  |  21 +-
 12 files changed, 643 insertions(+), 70 deletions(-)
 create mode 100644 hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld
 create mode 100644 hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc

(limited to 'src')

diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
index 5562b95a8..bd91502af 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
@@ -55,12 +55,10 @@ extern "C"
 // RCC Clock
 //--------------------------------------------------------------------+
 
-static inline void board_clock_init(void)
-{
-
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
 
   /* Enable Power Clock*/
   __HAL_RCC_PWR_CLK_ENABLE();
@@ -94,7 +92,8 @@ static inline void board_clock_init(void)
 
   /** Initializes the CPU, AHB and APB buses clocks
    */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
@@ -104,6 +103,8 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
+static void SystemPower_Config(void) {
+}
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
index 54a6d4cd7..6d244d418 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
@@ -54,12 +54,10 @@ extern "C"
 // RCC Clock
 //--------------------------------------------------------------------+
 
-static inline void board_clock_init(void)
-{
-
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
 
   /* Enable Power Clock */
   __HAL_RCC_PWR_CLK_ENABLE();
@@ -93,7 +91,8 @@ static inline void board_clock_init(void)
 
   /** Initializes the CPU, AHB and APB buses clocks
    */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.ClockType =
+      RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
@@ -103,6 +102,8 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
+static void SystemPower_Config(void) {
+}
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld
new file mode 100644
index 000000000..8aa68a6a6
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/STM32U5A5ZJTXQ_FLASH.ld
@@ -0,0 +1,167 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U5A5xJ Device from STM32U5 series
+**                      4096Kbytes FLASH
+**                      2512Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2023 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM   (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K
+  SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K
+  FLASH (rx)  : ORIGIN = 0x08000000, LENGTH = 4096K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
index eea16213b..24d4ef95a 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
@@ -1,7 +1,7 @@
 set(MCU_VARIANT stm32u5a5xx)
 set(JLINK_DEVICE stm32u5a5zj)
 
-set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32U5A5ZJTXQ_FLASH.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
index 54a6d4cd7..37b008727 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
@@ -54,46 +54,44 @@ extern "C"
 // RCC Clock
 //--------------------------------------------------------------------+
 
-static inline void board_clock_init(void)
-{
-
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+static void SystemClock_Config(void) {
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
 
-  /* Enable Power Clock */
   __HAL_RCC_PWR_CLK_ENABLE();
+  HAL_PWREx_EnableVddA();
 
   /** Configure the main internal regulator output voltage
-   */
-  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+  */
+  if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+    Error_Handler();
+  }
 
   /** Initializes the CPU, AHB and APB buses clocks
   */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
   RCC_OscInitStruct.PLL.PLLM = 1;
-  RCC_OscInitStruct.PLL.PLLN = 10;
-  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLN = 20;
+  RCC_OscInitStruct.PLL.PLLP = 8;
   RCC_OscInitStruct.PLL.PLLQ = 2;
-  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLR = 2;
   RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
   RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
-  PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
-
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+    Error_Handler();
+  }
 
   /** Initializes the CPU, AHB and APB buses clocks
-   */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+                                | RCC_CLOCKTYPE_PCLK3;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
@@ -103,6 +101,19 @@ static inline void board_clock_init(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
+static void SystemPower_Config(void) {
+  HAL_PWREx_EnableVddIO2();
+
+  /*
+   * Switch to SMPS regulator instead of LDO
+   */
+  if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) {
+    Error_Handler();
+  }
+/* USER CODE BEGIN PWR */
+/* USER CODE END PWR */
+}
+
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
index 48a4206a6..13025efa6 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
@@ -2,7 +2,7 @@ CFLAGS += \
   -DSTM32U5A5xx \
 
 # All source paths should be relative to the top level.
-LD_FILE = ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U5A9xx_FLASH.ld
+LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s
 
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc
new file mode 100644
index 000000000..289734040
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/cubemx/stm32u5a5nucleo.ioc
@@ -0,0 +1,352 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_2
+ADC1.IPParameters=Rank-1\#ChannelRegularConversion,master,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,MonitoredBy-1\#ChannelRegularConversion,NbrOfConversionFlag
+ADC1.MonitoredBy-1\#ChannelRegularConversion=__NULL
+ADC1.NbrOfConversionFlag=1
+ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.Rank-1\#ChannelRegularConversion=1
+ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_5CYCLE
+ADC1.master=1
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+CORTEX_M33_NS.userName=CORTEX_M33
+File.Version=6
+GPDMA1.DIRECTION_GPDMACH0=DMA_MEMORY_TO_PERIPH
+GPDMA1.DIRECTION_GPDMACH3=DMA_MEMORY_TO_PERIPH
+GPDMA1.IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0=__NULL
+GPDMA1.IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3=__NULL
+GPDMA1.IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5=__NULL
+GPDMA1.IPParameters=IPHANDLE_GPDMACH5-SIMPLEREQUEST_GPDMACH5,REQUEST_GPDMACH5,IPHANDLE_GPDMACH3-SIMPLEREQUEST_GPDMACH3,REQUEST_GPDMACH3,DIRECTION_GPDMACH3,IPHANDLE_GPDMACH0-SIMPLEREQUEST_GPDMACH0,REQUEST_GPDMACH0,DIRECTION_GPDMACH0,SRCINC_GPDMACH0
+GPDMA1.REQUEST_GPDMACH0=GPDMA1_REQUEST_USART1_TX
+GPDMA1.REQUEST_GPDMACH3=GPDMA1_REQUEST_UCPD1_TX
+GPDMA1.REQUEST_GPDMACH5=GPDMA1_REQUEST_UCPD1_RX
+GPDMA1.SRCINC_GPDMACH0=DMA_SINC_INCREMENTED
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+MMTAppReg1.MEMORYMAP.AP=RW_priv_only
+MMTAppReg1.MEMORYMAP.AppRegionName=RAM
+MMTAppReg1.MEMORYMAP.ContextName=CortexM33
+MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M33
+MMTAppReg1.MEMORYMAP.DefaultDataRegion=true
+MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,AP
+MMTAppReg1.MEMORYMAP.Name=RAM
+MMTAppReg1.MEMORYMAP.Size=2555904
+MMTAppReg1.MEMORYMAP.StartAddress=0x20000000
+MMTAppReg2.MEMORYMAP.AppRegionName=RAM Reserved Alias Region
+MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M33
+MMTAppReg2.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ReservedRegion,Name
+MMTAppReg2.MEMORYMAP.Name=RAM Reserved Alias Region
+MMTAppReg2.MEMORYMAP.ReservedRegion=true
+MMTAppReg2.MEMORYMAP.Size=2555904
+MMTAppReg2.MEMORYMAP.StartAddress=0x0A000000
+MMTAppReg3.MEMORYMAP.AP=RO_priv_only
+MMTAppReg3.MEMORYMAP.AppRegionName=FLASH
+MMTAppReg3.MEMORYMAP.Cacheability=WTRA
+MMTAppReg3.MEMORYMAP.ContextName=CortexM33
+MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M33
+MMTAppReg3.MEMORYMAP.DefaultCodeRegion=true
+MMTAppReg3.MEMORYMAP.DefaultDataRegion=false
+MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion
+MMTAppReg3.MEMORYMAP.MemType=ROM
+MMTAppReg3.MEMORYMAP.Name=FLASH
+MMTAppReg3.MEMORYMAP.Size=4194304
+MMTAppReg3.MEMORYMAP.StartAddress=0x08000000
+MMTAppRegionsCount=3
+MMTConfigApplied=false
+Mcu.CPN=STM32U5A5ZJT6Q
+Mcu.ContextProject=TrustZoneDisabled
+Mcu.Family=STM32U5
+Mcu.IP0=ADC1
+Mcu.IP1=CORTEX_M33_NS
+Mcu.IP10=UCPD1
+Mcu.IP11=USART1
+Mcu.IP12=USBPD
+Mcu.IP13=USBX
+Mcu.IP14=USB_OTG_HS
+Mcu.IP2=GPDMA1
+Mcu.IP3=ICACHE
+Mcu.IP4=MEMORYMAP
+Mcu.IP5=NVIC
+Mcu.IP6=PWR
+Mcu.IP7=RCC
+Mcu.IP8=SYS
+Mcu.IP9=THREADX
+Mcu.IPNb=15
+Mcu.Name=STM32U5A5ZJTxQ
+Mcu.Package=LQFP144
+Mcu.Pin0=PH0-OSC_IN (PH0)
+Mcu.Pin1=PH1-OSC_OUT (PH1)
+Mcu.Pin10=VP_GPDMA1_VS_GPDMACH0
+Mcu.Pin11=VP_GPDMA1_VS_GPDMACH3
+Mcu.Pin12=VP_GPDMA1_VS_GPDMACH5
+Mcu.Pin13=VP_ICACHE_VS_ICACHE
+Mcu.Pin14=VP_PWR_VS_DBSignals
+Mcu.Pin15=VP_PWR_VS_SECSignals
+Mcu.Pin16=VP_PWR_VS_LPOM
+Mcu.Pin17=VP_SYS_VS_tim6
+Mcu.Pin18=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault
+Mcu.Pin19=VP_USBPD_VS_USBPD1
+Mcu.Pin2=PC1
+Mcu.Pin20=VP_USBPD_VS_PD3TYPEC
+Mcu.Pin21=VP_USBPD_VS_usbpd_tim2
+Mcu.Pin22=VP_USBPD_VS_usbpd_usb_cohabitation
+Mcu.Pin23=VP_USBX_Core_System
+Mcu.Pin24=VP_USBX_UX Device CoreStack_HS
+Mcu.Pin25=VP_USBX_UX Device Controller_HS
+Mcu.Pin26=VP_USBX_UX Device CDC ACM Class_HS
+Mcu.Pin27=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.Pin3=PB15
+Mcu.Pin4=PG2
+Mcu.Pin5=PA9
+Mcu.Pin6=PA10
+Mcu.Pin7=PA11
+Mcu.Pin8=PA12
+Mcu.Pin9=PA15 (JTDI)
+Mcu.PinsNb=28
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32U5A5ZJTxQ
+MxCube.Version=6.9.2
+MxDb.Version=DB.6.0.92
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.GPDMA1_Channel0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.GPDMA1_Channel3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.GPDMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true\:true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+NVIC.OTG_HS_IRQn=true\:7\:0\:true\:false\:true\:false\:true\:true\:true
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
+NVIC.SavedPendsvIrqHandlerGenerated=true
+NVIC.SavedSvcallIrqHandlerGenerated=true
+NVIC.SavedSystickIrqHandlerGenerated=true
+NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:false\:false\:false\:true\:false
+NVIC.TIM6_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true
+NVIC.TimeBase=TIM6_IRQn
+NVIC.TimeBaseIP=TIM6
+NVIC.UCPD1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:false\:true
+NVIC.USART1_IRQn=true\:6\:0\:true\:false\:true\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+PA10.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA10.GPIO_PuPd=GPIO_PULLUP
+PA10.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA11.GPIOParameters=GPIO_Speed
+PA11.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA11.Mode=Internal_Phy_Device
+PA11.Signal=USB_OTG_HS_DM
+PA12.GPIOParameters=GPIO_Speed
+PA12.GPIO_Speed=GPIO_SPEED_FREQ_LOW
+PA12.Mode=Internal_Phy_Device
+PA12.Signal=USB_OTG_HS_DP
+PA15\ (JTDI).Mode=Sink_AllSignals
+PA15\ (JTDI).Signal=UCPD1_CC1
+PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd
+PA9.GPIO_PuPd=GPIO_PULLUP
+PA9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB15.Mode=Sink_AllSignals
+PB15.Signal=UCPD1_CC2
+PC1.Mode=IN2-Single-Ended
+PC1.Signal=ADC1_IN2
+PG2.GPIOParameters=GPIO_Label
+PG2.GPIO_Label=LED_RED
+PG2.Locked=true
+PG2.Signal=GPIO_Output
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PWR.IPParameters=PowerMode
+PWR.PowerMode=PWR_SMPS_SUPPLY
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32U5A5ZJTxQ
+ProjectManager.Example=Ux_Device_CDC_ACM
+ProjectManager.ExampleSource=MxCubeFw
+ProjectManager.FirmwarePackage=STM32Cube FW_U5 V1.3.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LPBAM.generateCode=
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=stm32u5a5nucleo.ioc
+ProjectManager.ProjectName=stm32u5a5nucleo
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_ICACHE_Init-ICACHE-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-false,6-MX_UCPD1_Init-UCPD1-false-LL-true,7-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-true-HAL-false,8-MX_USBPD_Init-USBPD-false-HAL-false,9-MX_USBX_Init-USBX-false-HAL-false,10-MX_ADC1_Init-ADC1-false-HAL-true,11-MX_MEMORYMAP_Init-MEMORYMAP-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
+RCC.ADCFreq_Value=16000000
+RCC.ADF1Freq_Value=160000000
+RCC.AHBFreq_Value=160000000
+RCC.APB1Freq_Value=160000000
+RCC.APB1TimFreq_Value=160000000
+RCC.APB2Freq_Value=160000000
+RCC.APB2TimFreq_Value=160000000
+RCC.APB3Freq_Value=160000000
+RCC.CK48Freq_Value=48000000
+RCC.CRSFreq_Value=48000000
+RCC.CortexFreq_Value=160000000
+RCC.DACCLockSelectionVirtual=RCC_DAC1CLKSOURCE_LSI
+RCC.DACFreq_Value=32000
+RCC.EPOD_VALUE=16000000
+RCC.FCLKCortexFreq_Value=160000000
+RCC.FDCANFreq_Value=160000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=160000000
+RCC.HSE_VALUE=16000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=160000000
+RCC.I2C2Freq_Value=160000000
+RCC.I2C3Freq_Value=160000000
+RCC.I2C4Freq_Value=160000000
+RCC.I2C5Freq_Value=160000000
+RCC.I2C6Freq_Value=160000000
+RCC.IPParameters=ADCFreq_Value,ADF1Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CK48Freq_Value,CRSFreq_Value,CortexFreq_Value,DACCLockSelectionVirtual,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2C5Freq_Value,I2C6Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIDIV_VALUE,LSI_VALUE,MCO1PinFreq_Value,MDF1Freq_Value,MSIClockRange,MSI_VALUE,OCTOSPIMFreq_Value,PLL1P,PLL2FRACN,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3FRACN,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAESFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBPHYCLockSelection,USBPHYFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value
+RCC.LPTIM2Freq_Value=160000000
+RCC.LPUART1Freq_Value=160000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSIDIV_VALUE=32000
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=160000000
+RCC.MDF1Freq_Value=160000000
+RCC.MSIClockRange=RCC_MSIRANGE_0
+RCC.MSI_VALUE=48000000
+RCC.OCTOSPIMFreq_Value=160000000
+RCC.PLL1P=8
+RCC.PLL2FRACN=0
+RCC.PLL2PoutputFreq_Value=3096000000
+RCC.PLL2QoutputFreq_Value=3096000000
+RCC.PLL2RoutputFreq_Value=3096000000
+RCC.PLL3FRACN=0
+RCC.PLL3PoutputFreq_Value=3096000000
+RCC.PLL3QoutputFreq_Value=3096000000
+RCC.PLL3RoutputFreq_Value=3096000000
+RCC.PLLFRACN=0
+RCC.PLLN=20
+RCC.PLLPoutputFreq_Value=40000000
+RCC.PLLQoutputFreq_Value=160000000
+RCC.PLLRCLKFreq_Value=160000000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.RNGFreq_Value=48000000
+RCC.SAESFreq_Value=48000000
+RCC.SAI1Freq_Value=3096000000
+RCC.SAI2Freq_Value=3096000000
+RCC.SDMMCFreq_Value=40000000
+RCC.SPI1Freq_Value=160000000
+RCC.SPI2Freq_Value=160000000
+RCC.SPI3Freq_Value=160000000
+RCC.SYSCLKFreq_VALUE=160000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=160000000
+RCC.UART5Freq_Value=160000000
+RCC.USART1Freq_Value=160000000
+RCC.USART2Freq_Value=160000000
+RCC.USART3Freq_Value=160000000
+RCC.USART6Freq_Value=160000000
+RCC.USBPHYCLockSelection=RCC_USBPHYCLKSOURCE_HSE
+RCC.USBPHYFreq_Value=16000000
+RCC.VCOInput2Freq_Value=48000000
+RCC.VCOInput3Freq_Value=48000000
+RCC.VCOInputFreq_Value=16000000
+RCC.VCOOutputFreq_Value=320000000
+RCC.VCOPLL2OutputFreq_Value=6192000000
+RCC.VCOPLL3OutputFreq_Value=6192000000
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+USBX.BSP.number=1
+USBX.Core_System=1
+USBX.IPParameters=Core_System,UX_Device_CoreStack,UX_Device_Controller,UX_DEVICE_CDC_ACM,USBD_CDCACM_EPIN_ADDR,USBD_CDCACM_EPOUT_HS_MPS,USBD_CDCACM_EPIN_HS_MPS,UX_DEVICE_APP_MEM_POOL_SIZE,USBD_PRODUCT_STRING,UX_SLAVE_REQUEST_DATA_MAX_LENGTH,USBX_DEVICE_SYS_SIZE,USBD_PID,USBD_SERIAL_NUMBER,UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH,USBD_CDCACM_EPINCMD_ADDR,MAX_POWER_IN_MILLI_AMPER
+USBX.MAX_POWER_IN_MILLI_AMPER=0
+USBX.USBD_CDCACM_EPINCMD_ADDR=2
+USBX.USBD_CDCACM_EPIN_ADDR=1
+USBX.USBD_CDCACM_EPIN_HS_MPS=512
+USBX.USBD_CDCACM_EPOUT_HS_MPS=512
+USBX.USBD_PID=22336
+USBX.USBD_PRODUCT_STRING=STM32 Virtual ComPort
+USBX.USBD_SERIAL_NUMBER=CDC_ACM001
+USBX.USBX_DEVICE_SYS_SIZE=4*1024
+USBX.UX_DEVICE_APP_MEM_POOL_SIZE=8192
+USBX.UX_DEVICE_CDC_ACM=1
+USBX.UX_Device_Controller=1
+USBX.UX_Device_CoreStack=1
+USBX.UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH=256
+USBX.UX_SLAVE_REQUEST_DATA_MAX_LENGTH=512
+USBX0.BSP.STBoard=false
+USBX0.BSP.api=Unknown
+USBX0.BSP.component=
+USBX0.BSP.condition=
+USBX0.BSP.instance=USB_OTG_HS
+USBX0.BSP.ip=USB_OTG_HS
+USBX0.BSP.mode=Device_Only
+USBX0.BSP.name=USBDevice
+USBX0.BSP.semaphore=
+USBX0.BSP.solution=USB_OTG_HS
+USB_OTG_HS.IPParameters=VirtualMode
+USB_OTG_HS.VirtualMode=Device_HS
+VP_GPDMA1_VS_GPDMACH0.Mode=SIMPLEREQUEST_GPDMACH0
+VP_GPDMA1_VS_GPDMACH0.Signal=GPDMA1_VS_GPDMACH0
+VP_GPDMA1_VS_GPDMACH3.Mode=SIMPLEREQUEST_GPDMACH3
+VP_GPDMA1_VS_GPDMACH3.Signal=GPDMA1_VS_GPDMACH3
+VP_GPDMA1_VS_GPDMACH5.Mode=SIMPLEREQUEST_GPDMACH5
+VP_GPDMA1_VS_GPDMACH5.Signal=GPDMA1_VS_GPDMACH5
+VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache
+VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE
+VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
+VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
+VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
+VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
+VP_PWR_VS_LPOM.Mode=PowerOptimisation
+VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM
+VP_PWR_VS_SECSignals.Mode=Security/Privilege
+VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
+VP_SYS_VS_tim6.Mode=TIM6
+VP_SYS_VS_tim6.Signal=SYS_VS_tim6
+VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Mode=Core_Default
+VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Signal=THREADX_VS_RTOSJjThreadXJjCoreJjDefault
+VP_USBPD_VS_PD3TYPEC.Mode=PD3_TypeC
+VP_USBPD_VS_PD3TYPEC.Signal=USBPD_VS_PD3TYPEC
+VP_USBPD_VS_USBPD1.Mode=USBPD_P0
+VP_USBPD_VS_USBPD1.Signal=USBPD_VS_USBPD1
+VP_USBPD_VS_usbpd_tim2.Mode=TIM2
+VP_USBPD_VS_usbpd_tim2.Signal=USBPD_VS_usbpd_tim2
+VP_USBPD_VS_usbpd_usb_cohabitation.Mode=Enable USB Support
+VP_USBPD_VS_usbpd_usb_cohabitation.Signal=USBPD_VS_usbpd_usb_cohabitation
+VP_USBX_Core_System.Mode=Core_System
+VP_USBX_Core_System.Signal=USBX_Core_System
+VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Mode=UX_Device_class_CDC_ACM_HS
+VP_USBX_UX\ Device\ CDC\ ACM\ Class_HS.Signal=USBX_UX Device CDC ACM Class_HS
+VP_USBX_UX\ Device\ Controller_HS.Mode=UX_Device_Controller_HS
+VP_USBX_UX\ Device\ Controller_HS.Signal=USBX_UX Device Controller_HS
+VP_USBX_UX\ Device\ CoreStack_HS.Mode=UX_Device_CoreStack_HS
+VP_USBX_UX\ Device\ CoreStack_HS.Signal=USBX_UX Device CoreStack_HS
+board=NUCLEO-U5A5ZJ-Q
+boardIOC=true
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index ab4194623..16a86cbbb 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -37,6 +37,9 @@
 #pragma GCC diagnostic pop
 #endif
 
+static void Error_Handler(void) {
+}
+
 #include "bsp/board_api.h"
 #include "board.h"
 
@@ -47,6 +50,10 @@ void OTG_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
+void OTG_HS_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -54,8 +61,9 @@ void OTG_FS_IRQHandler(void) {
 UART_HandleTypeDef UartHandle;
 
 void board_init(void) {
-
-  board_clock_init();
+  // Init clock, implemented in board.h
+  SystemClock_Config();
+  SystemPower_Config();
 
   // Enable All GPIOs clocks
   __HAL_RCC_GPIOA_CLK_ENABLE();
@@ -75,9 +83,6 @@ void board_init(void) {
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   GPIO_InitTypeDef GPIO_InitStruct;
@@ -135,7 +140,13 @@ void board_init(void) {
   GPIO_InitStruct.Alternate = GPIO_AF10_USB;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
-#if defined(OTG_FS_VBUS_SENSE) && OTG_FS_VBUS_SENSE
+#ifdef USB_OTG_FS
+  #if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+
+  #if defined(OTG_FS_VBUS_SENSE) && OTG_FS_VBUS_SENSE
   // Configure VBUS Pin OTG_FS_VBUS_SENSE
   GPIO_InitStruct.Pin = GPIO_PIN_9;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
@@ -144,20 +155,44 @@ void board_init(void) {
 
   // Enable VBUS sense (B device) via pin PA9
   USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
+  #else
   // Disable VBUS sense (B device) via pin PA9
   USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
   // B-peripheral session valid override enable
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
+  #endif // vbus sense
 
   /* Enable USB power on Pwrctrl CR2 register */
   HAL_PWREx_EnableVddUSB();
 
-  /* USB_OTG_FS clock enable */
+  /* USB clock enable */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+#else
+  // STM59x/Ax/Fx/Gx only have 1 USB HS port
+
+  #if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+
+
+  // Disable VBUS sense (B device)
+  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  // B-peripheral session valid override enable
+  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+
+  /* Enable USB power on Pwrctrl CR2 register */
+  HAL_PWREx_EnableVddUSB();
+
+  /* USB clock enable */
+  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+#endif // USB_OTG_FS
+
+
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 8807ff8aa..1797f0bc4 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -217,9 +217,7 @@
 
   // TypeC controller
   #define TUP_USBIP_TYPEC_STM32
-
   #define TUP_DCD_ENDPOINT_MAX    8
-
   #define TUP_TYPEC_RHPORTS_NUM 1
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G0)
@@ -261,14 +259,21 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32U5)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
-  #define TUP_DCD_ENDPOINT_MAX    6
+
+  // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
+  #if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
+      defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
+    #define TUP_DCD_ENDPOINT_MAX  9
+    #define TUP_RHPORT_HIGHSPEED  1
+  #else
+    #define TUP_DCD_ENDPOINT_MAX  6
+  #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L5)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
-
 //--------------------------------------------------------------------+
 // Sony
 //--------------------------------------------------------------------+
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index aa77511fa..a97a10223 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -86,18 +86,16 @@
   #include "stm32u5xx.h"
   // NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY)
   // USB_OTG_FS_BASE and OTG_FS_IRQn not defined
-  #if (! defined USB_OTG_FS)
+  #if !defined(USB_OTG_FS)
     #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE
     #define EP_MAX_HS                 9
     #define EP_FIFO_SIZE_HS           4096
-    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_HS_BASE
-    #define OTG_FS_IRQn               OTG_HS_IRQn
+    //#define OTG_FS_IRQn               OTG_HS_IRQn
   #else
     #define USB_OTG_FS_PERIPH_BASE    USB_OTG_FS_BASE
+    #define EP_MAX_FS       6
+    #define EP_FIFO_SIZE_FS 1280
   #endif
-  #define EP_MAX_FS       6
-  #define EP_FIFO_SIZE_FS 1280
-
 #else
   #error "Unsupported MCUs"
 #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a41f5a07e..a29eb8a3a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -174,10 +174,10 @@
 // NXP LPC MCX
 #define OPT_MCU_MCXN9            2300  ///< NXP MCX N9 Series
 
-// Helper to check if configured MCU is one of listed
+// Check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
-#define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)
-#define TU_CHECK_MCU(...)   (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
+#define _TU_CHECK_MCU(_m)    (CFG_TUSB_MCU == _m)
+#define TU_CHECK_MCU(...)    (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
 
 //--------------------------------------------------------------------+
 // Supported OS
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 9fdefac9d..8f93ca61f 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -181,6 +181,10 @@ deps_all = {**deps_mandatory, **deps_optional}
 TOP = Path(__file__).parent.parent.resolve()
 
 
+def run_cmd(cmd):
+    return subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+
+
 def get_a_dep(d):
     if d not in deps_all.keys():
         print('{} is not found in dependency list')
@@ -189,25 +193,24 @@ def get_a_dep(d):
     commit = deps_all[d][1]
     families = deps_all[d][2]
 
-    print('cloning {} with {}'.format(d, url))
+    print(f'cloning {d} with {url}')
 
     p = Path(TOP / d)
-    git_cmd = "git -C {}".format(p)
+    git_cmd = f"git -C {p}"
 
     # Init git deps if not existed
     if not p.exists():
         p.mkdir(parents=True)
-        subprocess.run("{} init".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        run_cmd(f"git -C {p} init")
+        run_cmd(f"git -C {p} remote add origin {url}")
 
     # Check if commit is already fetched
-    result = subprocess.run("{} rev-parse HEAD".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    result = run_cmd(f"git -C {p} rev-parse HEAD")
     head = result.stdout.decode("utf-8").splitlines()[0]
-
+    run_cmd(f"git -C {p} reset --hard")
     if commit != head:
-        subprocess.run("{} reset --hard".format(git_cmd, commit), shell=True)
-        subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True)
-        subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        run_cmd(f"git -C {p} fetch --depth 1 origin {commit}")
+        run_cmd(f"git -C {p} checkout FETCH_HEAD")
 
     return 0
 
-- 
cgit v1.3.1


From d3fa3cdf487be5929240bc23f9d109c5e3e947bc Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 18 Oct 2023 17:05:35 +0200
Subject: Adjsut blackout time.

---
 examples/device/audio_4_channel_mic/src/tusb_config.h | 4 ++--
 src/class/audio/audio_device.c                        | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index f86b63528..cf44918e2 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -126,12 +126,12 @@ extern "C" {
 #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
 #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Minimum 4*EP size is needed for flow control
 
 #else
 
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN    // Minimum 4*EP size is needed for flow control
 
 #endif
 
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9712afde9..9af999992 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2645,11 +2645,11 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da
       packet_size = norminal_size[2];
       if(norminal_size[0] == norminal_size[1])
       {
-        // nav = INT(nav) + 1
-        ctrl_blackout = 2;
+        // nav > INT(nav), eg. 44.1k, 88.2k
+        ctrl_blackout = 0;
       } else
       {
-        // nav = INT(nav)
+        // nav = INT(nav), eg. 48k, 96k
         ctrl_blackout = 10;
       }
     } else
-- 
cgit v1.3.1


From 2d802e03e9a86ff3306398f1db59b8218f625c7f Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 24 Oct 2023 22:14:24 +0200
Subject: Update audio_4_channel_mic example for HS device.

---
 examples/device/audio_4_channel_mic/src/main.c     | 30 ++++++++++++----------
 .../device/audio_4_channel_mic/src/tusb_config.h   |  4 +--
 src/device/usbd.h                                  |  6 ++---
 3 files changed, 22 insertions(+), 18 deletions(-)

(limited to 'src')

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 9c37315c8..1de4f9dac 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -71,10 +71,10 @@ audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range stat
 
 #if CFG_TUD_AUDIO_ENABLE_ENCODING
 // Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
-uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2];   // Ensure half word aligned
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
 #else
 // Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
-uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_EP_SZ_IN];   // Ensure half word aligned
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000];
 #endif
 
 void led_blinking_task(void);
@@ -185,8 +185,21 @@ void tud_resume_cb(void)
 
 void audio_task(void)
 {
-  // Yet to be filled - e.g. put meas data into TX FIFOs etc.
-  // asm("nop");
+  // Yet to be filled - e.g. read audio from I2S buffer.
+  // Here we simulate a I2S receive callback every 1ms.
+  static uint32_t start_ms = 0;
+  uint32_t curr_ms = board_millis();
+  if ( start_ms == curr_ms ) return; // not enough time
+  start_ms = curr_ms;
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+  // Write I2S buffer into FIFO
+  for (uint8_t cnt=0; cnt < 2; cnt++)
+  {
+    tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
+  }
+#else
+  tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -453,15 +466,6 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   //    tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
   // }
 
-#if CFG_TUD_AUDIO_ENABLE_ENCODING
-  // Write I2S buffer into FIFO
-  for (uint8_t cnt=0; cnt < 2; cnt++)
-  {
-    tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
-  }
-#else
-  tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
-#endif
   return true;
 }
 
diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index cf44918e2..46484f847 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -126,12 +126,12 @@ extern "C" {
 #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
 #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Minimum 4*EP size is needed for flow control
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device
 
 #else
 
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN    // Minimum 4*EP size is needed for flow control
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
 
 #endif
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 782f538fd..93a2033c4 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -465,7 +465,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -514,7 +514,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -562,7 +562,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
-- 
cgit v1.3.1


From 9cba9a753b2d8a8c06f1dacc5c16d656397f5d79 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Oct 2023 17:40:53 +0700
Subject: update s3 devkitm with max3421 pin following metro s3, check max3421
 version to make sure it is valid

---
 .idea/cmake.xml                                      | 2 +-
 hw/bsp/espressif/boards/espressif_s3_devkitm/board.h | 6 +++---
 src/portable/analog/max3421/hcd_max3421.c            | 5 +++--
 3 files changed, 7 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 88e0e27ad..9f17c805c 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -16,7 +16,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="esp32s3" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm">
+      <configuration PROFILE_NAME="espressif_s3_devkitm" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm -DMAX3421_HOST=1 -DLOG=2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
index 4b4151e72..a319fbc61 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
@@ -38,9 +38,9 @@
 
 // SPI for USB host shield
 #define MAX3421_SPI_HOST  SPI2_HOST
-#define MAX3421_SCK_PIN  36
-#define MAX3421_MOSI_PIN 35
-#define MAX3421_MISO_PIN 37
+#define MAX3421_SCK_PIN  39
+#define MAX3421_MOSI_PIN 42
+#define MAX3421_MISO_PIN 21
 #define MAX3421_CS_PIN   15
 #define MAX3421_INTR_PIN 14
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 787c1e511..4665c1b06 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -433,8 +433,9 @@ bool hcd_init(uint8_t rhport) {
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
   // V1 is 0x01, V2 is 0x12, V3 is 0x13
-//  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
-//  TU_LOG2_HEX(revision);
+  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+  TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
+  TU_LOG2_HEX(revision);
 
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
-- 
cgit v1.3.1


From a4c542a7b4e753997864b129a4d5fd5b9b77f4e3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Oct 2023 22:21:58 +0700
Subject: addd dwc2_info.py/md update stm32u5a5 board clock & power configure,
 able to get passed otg clock reset

---
 hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h |  12 ++
 hw/bsp/stm32u5/family.c                       |  11 +-
 src/portable/synopsys/dwc2/dwc2_info.md       |  54 +++++++++
 src/portable/synopsys/dwc2/dwc2_info.py       | 158 ++++++++++++++++++++++++++
 src/portable/synopsys/dwc2/dwc2_stm32.h       |  95 ++++++++--------
 src/portable/synopsys/dwc2/dwc2_type.h        |   1 +
 6 files changed, 278 insertions(+), 53 deletions(-)
 create mode 100644 src/portable/synopsys/dwc2/dwc2_info.md
 create mode 100644 src/portable/synopsys/dwc2/dwc2_info.py

(limited to 'src')

diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
index 37b008727..c4eb94dd8 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
@@ -99,6 +99,18 @@ static void SystemClock_Config(void) {
   RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  // USB Clock
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHY;
+  PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+    Error_Handler();
+  }
+
+  /** Set the OTG PHY reference clock selection
+  */
+  HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
 }
 
 static void SystemPower_Config(void) {
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 16a86cbbb..3fbc50d93 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -177,7 +177,6 @@ void board_init(void) {
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   #endif
 
-
   // Disable VBUS sense (B device)
   USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
@@ -185,11 +184,17 @@ void board_init(void) {
   USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
   USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 
+  /* USB clock enable */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_USBPHYC_CLK_ENABLE();
+
   /* Enable USB power on Pwrctrl CR2 register */
   HAL_PWREx_EnableVddUSB();
+  HAL_PWREx_EnableUSBHSTranceiverSupply();
 
-  /* USB clock enable */
-  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+  /*Configuring the SYSCFG registers OTG_HS PHY*/
+  HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
 #endif // USB_OTG_FS
 
 
diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
new file mode 100644
index 000000000..2d8ab067f
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -0,0 +1,54 @@
+|                             | BCM2711 (Pi4)   | EFM32GG FullSpeed   | ESP32-S2   | STM32F407 Fullspeed   | STM32F407 Highspeed   | STM32F411 Fullspeed   | STM32F412 Fullspeed   | STM32F723 Fullspeed   | STM32F723 HighSpeed   | STM32F767 Fullspeed   | STM32H743 Highspeed   | STM32L476 Fullspeed   | STM32U5A5 Highspeed   | GD32VF103 Fullspeed   | XMC4500    |
+|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
+| guid                        | 0x2708A000      | 0x00000000          | 0x00000000 | 0x00001200            | 0x00001100            | 0x00001200            | 0x00002000            | 0x00003000            | 0x00003100            | 0x00002000            | 0x00002300            | 0x00002000            | 0x00005000            | 0x00001000            | 0x00AEC000 |
+| gsnpsid                     | 0x4F54280A      | 0x4F54330A          | 0x4F54400A | 0x4F54281A            | 0x4F54281A            | 0x4F54281A            | 0x4F54320A            | 0x4F54330A            | 0x4F54330A            | 0x4F54320A            | 0x4F54330A            | 0x4F54310A            | 0x4F54411A            | 0x00000000            | 0x4F54292A |
+| ghwcfg1                     | 0x00000000      | 0x00000000          | 0x00000000 | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000 |
+| ghwcfg2                     | 0x228DDD50      | 0x228F5910          | 0x224DD930 | 0x229DCD20            | 0x229ED590            | 0x229DCD20            | 0x229ED520            | 0x229ED520            | 0x229FE1D0            | 0x229ED520            | 0x229FE190            | 0x229ED520            | 0x228FE052            | 0x00000000            | 0x228F5930 |
+| - op_mode                   | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 2                     | 0                     | 0          |
+| - arch                      | 2               | 2                   | 2          | 0                     | 2                     | 0                     | 0                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2          |
+| - point2point               | 0               | 0                   | 1          | 1                     | 0                     | 1                     | 1                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0                     | 1          |
+| - hs_phy_type               | 1               | 0                   | 0          | 0                     | 2                     | 0                     | 0                     | 0                     | 3                     | 0                     | 2                     | 0                     | 1                     | 0                     | 0          |
+| - fs_phy_type               | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - num_dev_ep                | 7               | 6                   | 6          | 3                     | 5                     | 3                     | 5                     | 5                     | 8                     | 5                     | 8                     | 5                     | 8                     | 0                     | 6          |
+| - num_host_ch               | 7               | 13                  | 7          | 7                     | 11                    | 7                     | 11                    | 11                    | 15                    | 11                    | 15                    | 11                    | 15                    | 0                     | 13         |
+| - period_channel_support    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - enable_dynamic_fifo       | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - mul_cpu_int               | 0               | 0                   | 0          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
+| - reserved21                | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - nperiod_tx_q_depth        | 2               | 2                   | 1          | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 0                     | 2          |
+| - host_period_tx_q_depth    | 2               | 2                   | 2          | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 0                     | 2          |
+| - dev_token_q_depth         | 8               | 8                   | 8          | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 0                     | 8          |
+| - otg_enable_ic_usb         | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| ghwcfg3                     | 0x0FF000E8      | 0x01F204E8          | 0x00C804B5 | 0x020001E8            | 0x03F403E8            | 0x020001E8            | 0x0200D1E8            | 0x0200D1E8            | 0x03EED2E8            | 0x0200D1E8            | 0x03B8D2E8            | 0x0200D1E8            | 0x03B882E8            | 0x00000000            | 0x027A01E5 |
+| - xfer_size_width           | 8               | 8                   | 5          | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 0                     | 5          |
+| - packet_size_width         | 6               | 6                   | 3          | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 0                     | 6          |
+| - otg_enable                | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - i2c_enable                | 0               | 0                   | 0          | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0                     | 1          |
+| - vendor_ctrl_itf           | 0               | 0                   | 0          | 0                     | 1                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0          |
+| - optional_feature_removed  | 0               | 1                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - synch_reset               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - otg_adp_support           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
+| - otg_enable_hsic           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - battery_charger_support   | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
+| - lpm_mode                  | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0          |
+| - total_fifo_size           | 4080            | 498                 | 200        | 512                   | 1012                  | 512                   | 512                   | 512                   | 1006                  | 512                   | 952                   | 512                   | 952                   | 0                     | 634        |
+| ghwcfg4                     | 0x1FF00020      | 0x1BF08030          | 0xD3F0A030 | 0x0FF08030            | 0x17F00030            | 0x0FF08030            | 0x17F08030            | 0x17F08030            | 0x23F00030            | 0x17F08030            | 0xE3F00030            | 0x17F08030            | 0xE2103E30            | 0x00000000            | 0xDBF08030 |
+| - num_dev_period_in_ep      | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - power_optimized           | 0               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - ahb_freq_min              | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - hibernation               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - reserved7                 | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 4                     | 0                     | 0          |
+| - service_interval_mode     | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - ipg_isoc_en               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - acg_enable                | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - reserved13                | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - utmi_phy_data_width       | 0               | 2                   | 2          | 2                     | 0                     | 2                     | 2                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 0                     | 2          |
+| - dev_ctrl_ep_num           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - iddg_filter_enabled       | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - vbus_valid_filter_enabled | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - a_valid_filter_enabled    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - b_valid_filter_enabled    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - dedicated_fifos           | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - num_dev_in_eps            | 15              | 13                  | 9          | 7                     | 11                    | 7                     | 11                    | 11                    | 1                     | 11                    | 1                     | 11                    | 1                     | 0                     | 13         |
+| - dma_desc_enable           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0          |
+| - dma_dynamic               | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1          |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
new file mode 100644
index 000000000..0af6c4c77
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -0,0 +1,158 @@
+import click
+import ctypes
+import pandas as pd
+
+# hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4']
+dwc2_reg_value = {
+    'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020],
+    'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030],
+    'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030],
+    'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
+    'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
+    'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
+    'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+    'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+    'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
+    'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+    'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores
+    'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+    'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30],
+    'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0],
+    'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030]
+}
+
+# Combine dwc2_info with dwc2_reg_list
+# dwc2_info = {
+#     'BCM2711 (Pi4)': {
+#         'guid': 0x2708A000,
+#         'gsnpsid': 0x4F54280A,
+#         'ghwcfg1': 0,
+#         'ghwcfg2': 0x228DDD50,
+#         'ghwcfg3': 0xFF000E8,
+#         'ghwcfg4': 0x1FF00020
+#     },
+dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()}
+
+class GHWCFG2(ctypes.LittleEndianStructure):
+    _fields_ = [
+        ("op_mode", ctypes.c_uint32, 3),
+        ("arch", ctypes.c_uint32, 2),
+        ("point2point", ctypes.c_uint32, 1),
+        ("hs_phy_type", ctypes.c_uint32, 2),
+        ("fs_phy_type", ctypes.c_uint32, 2),
+        ("num_dev_ep", ctypes.c_uint32, 4),
+        ("num_host_ch", ctypes.c_uint32, 4),
+        ("period_channel_support", ctypes.c_uint32, 1),
+        ("enable_dynamic_fifo", ctypes.c_uint32, 1),
+        ("mul_cpu_int", ctypes.c_uint32, 1),
+        ("reserved21", ctypes.c_uint32, 1),
+        ("nperiod_tx_q_depth", ctypes.c_uint32, 2),
+        ("host_period_tx_q_depth", ctypes.c_uint32, 2),
+        ("dev_token_q_depth", ctypes.c_uint32, 5),
+        ("otg_enable_ic_usb", ctypes.c_uint32, 1)
+    ]
+
+
+class GHWCFG3(ctypes.LittleEndianStructure):
+    _fields_ = [
+        ("xfer_size_width", ctypes.c_uint32, 4),
+        ("packet_size_width", ctypes.c_uint32, 3),
+        ("otg_enable", ctypes.c_uint32, 1),
+        ("i2c_enable", ctypes.c_uint32, 1),
+        ("vendor_ctrl_itf", ctypes.c_uint32, 1),
+        ("optional_feature_removed", ctypes.c_uint32, 1),
+        ("synch_reset", ctypes.c_uint32, 1),
+        ("otg_adp_support", ctypes.c_uint32, 1),
+        ("otg_enable_hsic", ctypes.c_uint32, 1),
+        ("battery_charger_support", ctypes.c_uint32, 1),
+        ("lpm_mode", ctypes.c_uint32, 1),
+        ("total_fifo_size", ctypes.c_uint32, 16)
+    ]
+
+
+class GHWCFG4(ctypes.LittleEndianStructure):
+    _fields_ = [
+        ("num_dev_period_in_ep", ctypes.c_uint32, 4),
+        ("power_optimized", ctypes.c_uint32, 1),
+        ("ahb_freq_min", ctypes.c_uint32, 1),
+        ("hibernation", ctypes.c_uint32, 1),
+        ("reserved7", ctypes.c_uint32, 3),
+        ("service_interval_mode", ctypes.c_uint32, 1),
+        ("ipg_isoc_en", ctypes.c_uint32, 1),
+        ("acg_enable", ctypes.c_uint32, 1),
+        ("reserved13", ctypes.c_uint32, 1),
+        ("utmi_phy_data_width", ctypes.c_uint32, 2),
+        ("dev_ctrl_ep_num", ctypes.c_uint32, 4),
+        ("iddg_filter_enabled", ctypes.c_uint32, 1),
+        ("vbus_valid_filter_enabled", ctypes.c_uint32, 1),
+        ("a_valid_filter_enabled", ctypes.c_uint32, 1),
+        ("b_valid_filter_enabled", ctypes.c_uint32, 1),
+        ("dedicated_fifos", ctypes.c_uint32, 1),
+        ("num_dev_in_eps", ctypes.c_uint32, 4),
+        ("dma_desc_enable", ctypes.c_uint32, 1),
+        ("dma_dynamic", ctypes.c_uint32, 1)
+    ]
+
+
+@click.group()
+def cli():
+    pass
+
+
+@cli.command()
+@click.argument('mcus', nargs=-1)
+@click.option('-a', '--all', is_flag=True, help='Print all bit-field values')
+def info(mcus, all):
+    """Print DWC2 register values for given MCU(s)"""
+    if len(mcus) == 0:
+        mcus = dwc2_info
+
+    for mcu in mcus:
+        for entry in dwc2_info:
+            if mcu.lower() in entry.lower():
+                print(f"## {entry}")
+                for r_name, r_value in dwc2_info[entry].items():
+                    print(f"{r_name} = 0x{r_value:08X}")
+                    # Print bit-field values
+                    if all and r_name.upper() in globals():
+                        class_name = globals()[r_name.upper()]
+                        ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
+                        for field_name, field_type, _ in class_name._fields_:
+                            print(f"  {field_name} = {getattr(ghwcfg, field_name)}")
+
+
+@cli.command()
+def render_md():
+    """Render dwc2_info to Markdown table"""
+    # Create an empty list to hold the dictionaries
+    dwc2_info_list = []
+
+    #Iterate over the dwc2_info dictionary and extract fields
+    for device, reg_values in dwc2_info.items():
+        entry_dict = {"Device": device}
+        for r_name, r_value in reg_values.items():
+            entry_dict[r_name] = f"0x{r_value:08X}"
+            # Print bit-field values
+            if r_name.upper() in globals():
+                class_name = globals()[r_name.upper()]
+                ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
+                for field_name, field_type, _ in class_name._fields_:
+                    entry_dict[f' - {field_name}'] = getattr(ghwcfg, field_name)
+
+        dwc2_info_list.append(entry_dict)
+
+    # Create a Pandas DataFrame from the list of dictionaries
+    df = pd.DataFrame(dwc2_info_list).set_index('Device')
+
+    # Transpose the DataFrame to switch rows and columns
+    df = df.T
+    #print(df)
+
+    # Write the Markdown table to a file
+    with open('dwc2_info.md', 'w') as md_file:
+        md_file.write(df.to_markdown())
+
+
+if __name__ == '__main__':
+    cli()
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index a97a10223..57df4e941 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -28,7 +28,7 @@
 #define _DWC2_STM32_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 // EP_MAX       : Max number of bi-directional endpoints including EP0
@@ -84,17 +84,15 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
   #include "stm32u5xx.h"
-  // NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY)
-  // USB_OTG_FS_BASE and OTG_FS_IRQn not defined
-  #if !defined(USB_OTG_FS)
+  // U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
+  #ifdef USB_OTG_FS
+    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_FS_BASE
+    #define EP_MAX_FS                 6
+    #define EP_FIFO_SIZE_FS           1280
+  #else
     #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE
     #define EP_MAX_HS                 9
     #define EP_FIFO_SIZE_HS           4096
-    //#define OTG_FS_IRQn               OTG_HS_IRQn
-  #else
-    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_FS_BASE
-    #define EP_MAX_FS       6
-    #define EP_FIFO_SIZE_FS 1280
   #endif
 #else
   #error "Unsupported MCUs"
@@ -109,15 +107,14 @@
 
 // On STM32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
-static const dwc2_controller_t _dwc2_controller[] =
-{
-#ifdef USB_OTG_FS_PERIPH_BASE
-  { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
-#endif
-
-#ifdef USB_OTG_HS_PERIPH_BASE
-  { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
-#endif
+static const dwc2_controller_t _dwc2_controller[] = {
+    #ifdef USB_OTG_FS_PERIPH_BASE
+    { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
+    #endif
+
+    #ifdef USB_OTG_HS_PERIPH_BASE
+    { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
+    #endif
 };
 
 //--------------------------------------------------------------------+
@@ -128,40 +125,33 @@ static const dwc2_controller_t _dwc2_controller[] =
 // extern uint32_t SystemCoreClock;
 
 TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
+static inline void dwc2_dcd_int_enable(uint8_t rhport) {
+  NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_disable (uint8_t rhport)
-{
-  NVIC_DisableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
+static inline void dwc2_dcd_int_disable(uint8_t rhport) {
+  NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_remote_wakeup_delay(void)
-{
+static inline void dwc2_remote_wakeup_delay(void) {
   // try to delay for 1 ms
   uint32_t count = SystemCoreClock / 1000;
-  while ( count-- ) __NOP();
+  while (count--) __NOP();
 }
 
 // MCU specific PHY init, called BEFORE core reset
-static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
-  if ( hs_phy_type == HS_PHY_TYPE_NONE )
-  {
+static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
+  if (hs_phy_type == HS_PHY_TYPE_NONE) {
     // Enable on-chip FS PHY
     dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
-  }else
-  {
-    // Disable FS PHY
+  } else {
+    // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
     dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
 
     // Enable on-chip HS PHY
-    if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI)
-    {
+    if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
 #ifdef USB_HS_PHYC
       // Enable UTMI HS PHY
       dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
@@ -200,34 +190,39 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 }
 
 // MCU specific PHY update, it is called AFTER init() and core reset
-static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
-{
+static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   // used to set turnaround time for fullspeed, nothing to do in highspeed mode
-  if ( hs_phy_type == HS_PHY_TYPE_NONE )
-  {
+  if (hs_phy_type == HS_PHY_TYPE_NONE) {
     // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
     uint32_t turnaround;
 
-    if ( SystemCoreClock >= 32000000u )
+    if (SystemCoreClock >= 32000000u) {
       turnaround = 0x6u;
-    else if ( SystemCoreClock >= 27500000u )
+    } else if (SystemCoreClock >= 27500000u) {
       turnaround = 0x7u;
-    else if ( SystemCoreClock >= 24000000u )
+    } else if (SystemCoreClock >= 24000000u) {
       turnaround = 0x8u;
-    else if ( SystemCoreClock >= 21800000u )
+    } else if (SystemCoreClock >= 21800000u) {
       turnaround = 0x9u;
-    else if ( SystemCoreClock >= 20000000u )
+    }
+    else if (SystemCoreClock >= 20000000u) {
       turnaround = 0xAu;
-    else if ( SystemCoreClock >= 18500000u )
+    }
+    else if (SystemCoreClock >= 18500000u) {
       turnaround = 0xBu;
-    else if ( SystemCoreClock >= 17200000u )
+    }
+    else if (SystemCoreClock >= 17200000u) {
       turnaround = 0xCu;
-    else if ( SystemCoreClock >= 16000000u )
+    }
+    else if (SystemCoreClock >= 16000000u) {
       turnaround = 0xDu;
-    else if ( SystemCoreClock >= 15000000u )
+    }
+    else if (SystemCoreClock >= 15000000u) {
       turnaround = 0xEu;
-    else
+    }
+    else {
       turnaround = 0xFu;
+    }
 
     dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
   }
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 3fc979337..6516882da 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -43,6 +43,7 @@ typedef struct
 #define DWC2_CORE_REV_3_00a   0x4f54300a
 #define DWC2_CORE_REV_3_10a   0x4f54310a
 #define DWC2_CORE_REV_4_00a   0x4f54400a
+#define DWC2_CORE_REV_4_11a   0x4f54411a
 #define DWC2_CORE_REV_4_20a   0x4f54420a
 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
-- 
cgit v1.3.1


From 305ef5d48a083f2052351a8a325310168c420c0e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Oct 2023 22:22:27 +0700
Subject: minor space format dwc2 driver

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 648 +++++++++++++---------------------
 1 file changed, 237 insertions(+), 411 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c6132a1f5..7b50a7d54 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -82,8 +82,8 @@
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 
 typedef struct {
-  uint8_t * buffer;
-  tu_fifo_t * ff;
+  uint8_t* buffer;
+  tu_fifo_t* ff;
   uint16_t total_len;
   uint16_t max_size;
   uint8_t interval;
@@ -93,30 +93,27 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
 
 // EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
+static uint16_t ep0_pending[2];               // Index determines direction as tusb_dir_t type
 
 // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
-static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
-static bool     _out_ep_closed;                   // Flag to check if RX FIFO size needs an update (reduce its size)
+static uint16_t _allocated_fifo_words_tx;     // TX FIFO size in words (IN EPs)
+static bool _out_ep_closed;                   // Flag to check if RX FIFO size needs an update (reduce its size)
 
 // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
 static bool _sof_en;
 
 // Calculate the RX FIFO size according to recommendations from reference manual
-static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count)
-{
-  return 15 + 2*(max_ep_size/4) + 2*ep_count;
+static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
+  return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
 }
 
-static void update_grxfsiz(uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+static void update_grxfsiz(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < ep_count; epnum++)
-  {
+  for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
     max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
   }
 
@@ -125,9 +122,8 @@ static void update_grxfsiz(uint8_t rhport)
 }
 
 // Start of Bus Reset
-static void bus_reset(uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+static void bus_reset(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   tu_memclr(xfer_status, sizeof(xfer_status));
@@ -139,15 +135,14 @@ static void bus_reset(uint8_t rhport)
   dwc2->dcfg &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
-  for ( uint8_t n = 0; n < ep_count; n++ )
-  {
+  for (uint8_t n = 0; n < ep_count; n++) {
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
   // 2. Set up interrupt mask
   dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
-  dwc2->doepmsk  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-  dwc2->diepmsk  = DIEPMSK_TOM   | DIEPMSK_XFRCM;
+  dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+  dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -206,36 +201,34 @@ static void bus_reset(uint8_t rhport)
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx);
+  dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
   xfer_status[0][TUSB_DIR_OUT].max_size = 64;
-  xfer_status[0][TUSB_DIR_IN ].max_size = 64;
+  xfer_status[0][TUSB_DIR_IN].max_size = 64;
 
   dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
   dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
-static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
-{
+static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets,
+                                  uint16_t total_bytes) {
   (void) rhport;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   // EP0 is limited to one packet each xfer
   // We use multiple transaction of xfer->max_size length to get a whole transfer done
-  if ( epnum == 0 )
-  {
-    xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, dir);
+  if (epnum == 0) {
+    xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
     total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
     ep0_pending[dir] -= total_bytes;
   }
 
   // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
-  if ( dir == TUSB_DIR_IN )
-  {
+  if (dir == TUSB_DIR_IN) {
     dwc2_epin_t* epin = dwc2->epin;
 
     // A full IN transfer (multiple packets, possibly) triggers XFRC.
@@ -245,20 +238,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
 
     // For ISO endpoint set correct odd/even bit for next frame.
-    if ( (epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
-    {
+    if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
       epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if ( total_bytes != 0 )
-    {
+    if (total_bytes != 0) {
       dwc2->diepempmsk |= (1 << epnum);
     }
-  }
-  else
-  {
+  } else {
     dwc2_epout_t* epout = dwc2->epout;
 
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
@@ -267,9 +256,8 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
                              ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
 
     epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
-    if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
-         XFER_CTL_BASE(epnum, dir)->interval == 1 )
-    {
+    if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
+        XFER_CTL_BASE(epnum, dir)->interval == 1) {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
       epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
@@ -281,93 +269,35 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 /* Controller API
  *------------------------------------------------------------------*/
 #if CFG_TUSB_DEBUG >= DWC2_DEBUG
-void print_dwc2_info(dwc2_regs_t * dwc2)
-{
-  dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm;
-  dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
-  dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
 
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
-//  TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->guid);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1);
-
-  // HW configure 2
-  TU_LOG(DWC2_DEBUG, "\r\n");
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg2);
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->op_mode                );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->arch                   );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->point2point            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->hs_phy_type            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->fs_phy_type            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_dev_ep             );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_host_ch            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->period_channel_support );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->enable_dynamic_fifo    );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->mul_cpu_int            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->nperiod_tx_q_depth     );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->host_period_tx_q_depth );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->dev_token_q_depth      );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->otg_enable_ic_usb      );
-
-  // HW configure 3
-  TU_LOG(DWC2_DEBUG, "\r\n");
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg3);
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->xfer_size_width          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->packet_size_width        );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->i2c_enable               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->vendor_ctrl_itf          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->optional_feature_removed );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->synch_reset              );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_adp_support          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable_hsic          );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->battery_charger_support  );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->lpm_mode                 );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->total_fifo_size          );
-
-  // HW configure 4
-  TU_LOG(DWC2_DEBUG, "\r\n");
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg4);
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_period_in_ep      );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->power_optimized           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ahb_freq_min              );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->hibernation               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->service_interval_mode     );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ipg_isoc_en               );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->acg_enable                );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->utmi_phy_data_width       );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dev_ctrl_ep_num           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->iddg_filter_enabled       );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->vbus_valid_filter_enabled );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->a_valid_filter_enabled    );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->b_valid_filter_enabled    );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dedicated_fifos           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_in_eps            );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_desc_enable           );
-  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_dynamic               );
+void print_dwc2_info(dwc2_regs_t* dwc2) {
+  // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+  // use dwc2_info.py/md for bit-field value and comparison with other ports
+  volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
+  TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
+  for (size_t i = 0; i < 5; i++) {
+    TU_LOG(DWC2_DEBUG, "0x%08lX, ", p[i]);
+  }
+  TU_LOG(DWC2_DEBUG, "0x%08lX\r\n", p[5]);
 }
+
 #endif
 
-static void reset_core(dwc2_regs_t * dwc2)
-{
+static void reset_core(dwc2_regs_t* dwc2) {
   // reset core
   dwc2->grstctl |= GRSTCTL_CSRST;
 
   // wait for reset bit is cleared
   // TODO version 4.20a should wait for RESET DONE mask
-  while (dwc2->grstctl & GRSTCTL_CSRST) { }
+  while (dwc2->grstctl & GRSTCTL_CSRST) {}
 
   // wait for AHB master IDLE
-  while ( !(dwc2->grstctl & GRSTCTL_AHBIDL) ) { }
+  while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {}
 
   // wait for device mode ?
 }
 
-static bool phy_hs_supported(dwc2_regs_t * dwc2)
-{
+static bool phy_hs_supported(dwc2_regs_t* dwc2) {
   // note: esp32 incorrect report its hs_phy_type as utmi
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   return false;
@@ -376,8 +306,7 @@ static bool phy_hs_supported(dwc2_regs_t * dwc2)
 #endif
 }
 
-static void phy_fs_init(dwc2_regs_t * dwc2)
-{
+static void phy_fs_init(dwc2_regs_t* dwc2) {
   TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n");
 
   // Select FS PHY
@@ -401,15 +330,13 @@ static void phy_fs_init(dwc2_regs_t * dwc2)
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
 }
 
-static void phy_hs_init(dwc2_regs_t * dwc2)
-{
+static void phy_hs_init(dwc2_regs_t* dwc2) {
   uint32_t gusbcfg = dwc2->gusbcfg;
 
   // De-select FS PHY
   gusbcfg &= ~GUSBCFG_PHYSEL;
 
-  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI)
-  {
+  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
     TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
 
     // Select ULPI
@@ -423,8 +350,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
 
     // Disable FS/LS ULPI
     gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
-  }else
-  {
+  } else {
     TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n");
 
     // Select UTMI+ with 8-bit interface
@@ -465,8 +391,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   dwc2->dcfg = dcfg;
 }
 
-static bool check_dwc2(dwc2_regs_t * dwc2)
-{
+static bool check_dwc2(dwc2_regs_t* dwc2) {
 #if CFG_TUSB_DEBUG >= DWC2_DEBUG
   print_dwc2_info(dwc2);
 #endif
@@ -481,41 +406,35 @@ static bool check_dwc2(dwc2_regs_t * dwc2)
   return true;
 }
 
-void dcd_init (uint8_t rhport)
-{
+void dcd_init(uint8_t rhport) {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   // Check Synopsys ID register, failed if controller clock/power is not enabled
-  TU_VERIFY(check_dwc2(dwc2), );
-
+  if (!check_dwc2(dwc2)) return;
   dcd_disconnect(rhport);
 
   // max number of endpoints & total_fifo_size are:
   // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size
 
-  if( phy_hs_supported(dwc2) )
-  {
-    // Highspeed
-    phy_hs_init(dwc2);
-  }else
-  {
-    // core does not support highspeed or hs-phy is not present
-    phy_fs_init(dwc2);
+  if (phy_hs_supported(dwc2)) {
+    phy_hs_init(dwc2); // Highspeed
+  } else {
+    phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present
   }
 
   // Restart PHY clock
   dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
 
-	/* Set HS/FS Timeout Calibration to 7 (max available value).
-	 * The number of PHY clocks that the application programs in
-	 * this field is added to the high/full speed interpacket timeout
-	 * duration in the core to account for any additional delays
-	 * introduced by the PHY. This can be required, because the delay
-	 * introduced by the PHY in generating the linestate condition
-	 * can vary from one PHY to another.
-	 */
+  /* Set HS/FS Timeout Calibration to 7 (max available value).
+   * The number of PHY clocks that the application programs in
+   * this field is added to the high/full speed interpacket timeout
+   * duration in the core to account for any additional delays
+   * introduced by the PHY. This can be required, because the delay
+   * introduced by the PHY in generating the linestate condition
+   * can vary from one PHY to another.
+   */
   dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
 
   // Force device mode
@@ -537,7 +456,7 @@ void dcd_init (uint8_t rhport)
   // Required as part of core initialization.
   // TODO: How should mode mismatch be handled? It will cause
   // the core to stop working/require reset.
-  dwc2->gintmsk = GINTMSK_OTGINT   | GINTMSK_MMISM  | GINTMSK_RXFLVLM  |
+  dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_MMISM | GINTMSK_RXFLVLM |
                   GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
 
   // Enable global interrupt
@@ -554,30 +473,26 @@ void dcd_init (uint8_t rhport)
   dcd_connect(rhport);
 }
 
-void dcd_int_enable (uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   dwc2_dcd_int_enable(rhport);
 }
 
-void dcd_int_disable (uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   dwc2_dcd_int_disable(rhport);
 }
 
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
 
   // Response with status after changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
-void dcd_remote_wakeup(uint8_t rhport)
-{
+void dcd_remote_wakeup(uint8_t rhport) {
   (void) rhport;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   // set remote wakeup
   dwc2->dctl |= DCTL_RWUSIG;
@@ -592,35 +507,29 @@ void dcd_remote_wakeup(uint8_t rhport)
   dwc2->dctl &= ~DCTL_RWUSIG;
 }
 
-void dcd_connect(uint8_t rhport)
-{
+void dcd_connect(uint8_t rhport) {
   (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   dwc2->dctl &= ~DCTL_SDIS;
 }
 
-void dcd_disconnect(uint8_t rhport)
-{
+void dcd_disconnect(uint8_t rhport) {
   (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   dwc2->dctl |= DCTL_SDIS;
 }
 
 // Be advised: audio, video and possibly other iso-ep classes use dcd_sof_enable() to enable/disable its corresponding ISR on purpose!
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   _sof_en = en;
 
-  if (en)
-  {
+  if (en) {
     dwc2->gintsts = GINTSTS_SOF;
     dwc2->gintmsk |= GINTMSK_SOFM;
-  }
-  else
-  {
+  } else {
     dwc2->gintmsk &= ~GINTMSK_SOFM;
   }
 }
@@ -629,33 +538,30 @@ void dcd_sof_enable(uint8_t rhport, bool en)
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
 
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
   (void) rhport;
 
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
   TU_ASSERT(epnum < ep_count);
 
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
   xfer->interval = desc_edpt->bInterval;
 
   uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4);
 
-  if(dir == TUSB_DIR_OUT)
-  {
+  if (dir == TUSB_DIR_OUT) {
     // Calculate required size of RX FIFO
-    uint16_t const sz = calc_grxfsiz(4*fifo_size, ep_count);
+    uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
 
     // If size_rx needs to be extended check if possible and if so enlarge it
-    if (dwc2->grxfsiz < sz)
-    {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size/4);
+    if (dwc2->grxfsiz < sz) {
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
 
       // Enlarge RX FIFO
       dwc2->grxfsiz = sz;
@@ -667,9 +573,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
                                   (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
     dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
-  }
-  else
-  {
+  } else {
     // "USB Data FIFOs" section in reference manual
     // Peripheral FIFO architecture
     //
@@ -692,15 +596,17 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
     // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size/4);
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
 
     _allocated_fifo_words_tx += fifo_size;
 
-    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size*4, _dwc2_controller[rhport].ep_fifo_size-_allocated_fifo_words_tx*4);
+    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size * 4,
+           _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx);
+    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
+                               (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
 
     dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
                                  (epnum << DIEPCTL_TXFNUM_Pos) |
@@ -715,16 +621,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 }
 
 // Close all non-control endpoints, cancel all pending transfers if any.
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+void dcd_edpt_close_all(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   // Disable non-control interrupt
   dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
-  for(uint8_t n = 1; n < ep_count; n++)
-  {
+  for (uint8_t n = 1; n < ep_count; n++) {
     // disable OUT endpoint
     dwc2->epout[n].doepctl = 0;
     xfer_status[n][TUSB_DIR_OUT].max_size = 0;
@@ -738,31 +642,27 @@ void dcd_edpt_close_all (uint8_t rhport)
   _allocated_fifo_words_tx = 16;
 }
 
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = buffer;
-  xfer->ff          = NULL;
-  xfer->total_len   = total_bytes;
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer = buffer;
+  xfer->ff = NULL;
+  xfer->total_len = total_bytes;
 
   // EP0 can only handle one packet
-  if(epnum == 0)
-  {
+  if (epnum == 0) {
     ep0_pending[dir] = total_bytes;
 
     // Schedule the first transaction for EP0 transfer
     edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
-  }
-  else
-  {
+  } else {
     uint16_t num_packets = (total_bytes / xfer->max_size);
     uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
     // Zero-size packet is special case.
-    if ( (short_packet_size > 0) || (total_bytes == 0) ) num_packets++;
+    if ((short_packet_size > 0) || (total_bytes == 0)) num_packets++;
 
     // Schedule packets to be sent within interrupt
     edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
@@ -775,24 +675,23 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 // bytes should be written and second to keep the return value free to give back a boolean
 // success message. If total_bytes is too big, the FIFO will copy only what is available
 // into the USB buffer!
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) {
   // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
   TU_ASSERT(ff->item_size == 1);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = NULL;
-  xfer->ff          = ff;
-  xfer->total_len   = total_bytes;
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer = NULL;
+  xfer->ff = ff;
+  xfer->total_len = total_bytes;
 
   uint16_t num_packets = (total_bytes / xfer->max_size);
   uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
   // Zero-size packet is special case.
-  if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++;
+  if (short_packet_size > 0 || (total_bytes == 0)) num_packets++;
 
   // Schedule packets to be sent within interrupt
   edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
@@ -800,62 +699,52 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   return true;
 }
 
-static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
-{
+static void dcd_edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
   (void) rhport;
 
-  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if ( dir == TUSB_DIR_IN )
-  {
+  if (dir == TUSB_DIR_IN) {
     dwc2_epin_t* epin = dwc2->epin;
 
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA) )
-    {
+    if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) {
       epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
-    }
-    else
-    {
+    } else {
       // Stop transmitting packets and NAK IN xfers.
       epin[epnum].diepctl |= DIEPCTL_SNAK;
-      while ( (epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {}
+      while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {}
 
       // Disable the endpoint.
       epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
-      while ( (epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {}
+      while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {}
 
       epin[epnum].diepint = DIEPINT_EPDISD;
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
     dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
-    while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
-  }
-  else
-  {
+    while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {}
+  } else {
     dwc2_epout_t* epout = dwc2->epout;
 
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA) )
-    {
+    if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) {
       epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
-    }
-    else
-    {
+    } else {
       // Asserting GONAK is required to STALL an OUT endpoint.
       // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
       // anyway, and it can't be cleared by user code. If this while loop never
       // finishes, we have bigger problems than just the stack.
       dwc2->dctl |= DCTL_SGONAK;
-      while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
+      while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
 
       // Ditto here- disable the endpoint.
       epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
-      while ( (epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {}
+      while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {}
 
       epout[epnum].doepint = DOEPINT_EPDISD;
 
@@ -868,55 +757,46 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
 /**
  * Close an endpoint.
  */
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   dcd_edpt_disable(rhport, ep_addr, false);
 
   // Update max_size
   xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
 
-  if (dir == TUSB_DIR_IN)
-  {
+  if (dir == TUSB_DIR_IN) {
     uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
     uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
 
     // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx,);
+    TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
-  }
-  else
-  {
+  } else {
     _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
   }
 }
 
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   dcd_edpt_disable(rhport, ep_addr, true);
 }
 
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // Clear stall and reset data toggle
-  if ( dir == TUSB_DIR_IN )
-  {
+  if (dir == TUSB_DIR_IN) {
     dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL;
     dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
-  }
-  else
-  {
+  } else {
     dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL;
     dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
   }
@@ -925,70 +805,63 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 /*------------------------------------------------------------------*/
 
 // Read a single data packet from receive FIFO
-static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
-{
+static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
   (void) rhport;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile const uint32_t * rx_fifo = dwc2->fifo[0];
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  volatile const uint32_t* rx_fifo = dwc2->fifo[0];
 
   // Reading full available 32 bit words from fifo
   uint16_t full_words = len >> 2;
-  while(full_words--)
-  {
+  while (full_words--) {
     tu_unaligned_write32(dst, *rx_fifo);
     dst += 4;
   }
 
   // Read the remaining 1-3 bytes from fifo
   uint8_t const bytes_rem = len & 0x03;
-  if ( bytes_rem != 0 )
-  {
+  if (bytes_rem != 0) {
     uint32_t const tmp = *rx_fifo;
     dst[0] = tu_u32_byte0(tmp);
-    if ( bytes_rem > 1 ) dst[1] = tu_u32_byte1(tmp);
-    if ( bytes_rem > 2 ) dst[2] = tu_u32_byte2(tmp);
+    if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
+    if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
   }
 }
 
 // Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const * src, uint16_t len)
-{
+static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
   (void) rhport;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile uint32_t * tx_fifo = dwc2->fifo[fifo_num];
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
 
   // Pushing full available 32 bit words to fifo
   uint16_t full_words = len >> 2;
-  while(full_words--)
-  {
+  while (full_words--) {
     *tx_fifo = tu_unaligned_read32(src);
     src += 4;
   }
 
   // Write the remaining 1-3 bytes into fifo
   uint8_t const bytes_rem = len & 0x03;
-  if ( bytes_rem )
-  {
+  if (bytes_rem) {
     uint32_t tmp_word = src[0];
-    if ( bytes_rem > 1 ) tmp_word |= (src[1] << 8);
-    if ( bytes_rem > 2 ) tmp_word |= (src[2] << 16);
+    if (bytes_rem > 1) tmp_word |= (src[1] << 8);
+    if (bytes_rem > 2) tmp_word |= (src[2] << 16);
 
     *tx_fifo = tmp_word;
   }
 }
 
-static void handle_rxflvl_irq(uint8_t rhport)
-{
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile uint32_t const * rx_fifo = dwc2->fifo[0];
+static void handle_rxflvl_irq(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  volatile uint32_t const* rx_fifo = dwc2->fifo[0];
 
   // Pop control word off FIFO
   uint32_t const ctl_word = dwc2->grxstsp;
-  uint8_t  const pktsts   = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos;
-  uint8_t  const epnum    = (ctl_word & GRXSTSP_EPNUM_Msk  ) >> GRXSTSP_EPNUM_Pos;
-  uint16_t const bcnt     = (ctl_word & GRXSTSP_BCNT_Msk   ) >> GRXSTSP_BCNT_Pos;
+  uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
+  uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
+  uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
 
   dwc2_epout_t* epout = &dwc2->epout[epnum];
 
@@ -1003,10 +876,10 @@ static void handle_rxflvl_irq(uint8_t rhport)
 //  TU_LOG(DWC2_DEBUG, "  daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint);
 //#endif
 
-  switch ( pktsts )
-  {
+  switch (pktsts) {
     // Global OUT NAK: do nothing
-    case GRXSTS_PKTSTS_GLOBALOUTNAK: break;
+    case GRXSTS_PKTSTS_GLOBALOUTNAK:
+      break;
 
     case GRXSTS_PKTSTS_SETUPRX:
       // Setup packet received
@@ -1015,26 +888,22 @@ static void handle_rxflvl_irq(uint8_t rhport)
       // only the last one is valid.
       _setup_packet[0] = (*rx_fifo);
       _setup_packet[1] = (*rx_fifo);
-    break;
+      break;
 
     case GRXSTS_PKTSTS_SETUPDONE:
       // Setup packet done (Interrupt)
       epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
-    break;
+      break;
 
-    case GRXSTS_PKTSTS_OUTRX:
-    {
+    case GRXSTS_PKTSTS_OUTRX: {
       // Out packet received
-      xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+      xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
       // Read packet off RxFIFO
-      if ( xfer->ff )
-      {
+      if (xfer->ff) {
         // Ring buffer
         tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
-      }
-      else
-      {
+      } else {
         // Linear buffer
         read_fifo_packet(rhport, xfer->buffer, bcnt);
 
@@ -1043,73 +912,64 @@ static void handle_rxflvl_irq(uint8_t rhport)
       }
 
       // Truncate transfer length in case of short packet
-      if ( bcnt < xfer->max_size )
-      {
+      if (bcnt < xfer->max_size) {
         xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
-        if ( epnum == 0 )
-        {
+        if (epnum == 0) {
           xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
           ep0_pending[TUSB_DIR_OUT] = 0;
         }
       }
     }
-    break;
+      break;
 
-    // Out packet done (Interrupt)
+      // Out packet done (Interrupt)
     case GRXSTS_PKTSTS_OUTDONE:
-        // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a
-        // May (or not) be 3.10a specific feature/bug or depending on MCU configuration
-        // XFRC complete is additionally generated when
-        // - setup packet is received
-        // - complete the data stage of control write is complete
-        if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
-        {
-          uint32_t doepint = epout->doepint;
-
-          if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR))
-          {
-            // skip this "no-data" transfer complete event
-            // Note: STPKTRX will be clear later by setup received handler
-            uint32_t clear_flags = DOEPINT_XFRC;
-
-            if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR;
-
-            epout->doepint = clear_flags;
-
-            // TU_LOG(DWC2_DEBUG, "  FIX extra transfer complete on setup/data compete\r\n");
-          }
+      // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a
+      // May (or not) be 3.10a specific feature/bug or depending on MCU configuration
+      // XFRC complete is additionally generated when
+      // - setup packet is received
+      // - complete the data stage of control write is complete
+      if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
+        uint32_t doepint = epout->doepint;
+
+        if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) {
+          // skip this "no-data" transfer complete event
+          // Note: STPKTRX will be clear later by setup received handler
+          uint32_t clear_flags = DOEPINT_XFRC;
+
+          if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR;
+
+          epout->doepint = clear_flags;
+
+          // TU_LOG(DWC2_DEBUG, "  FIX extra transfer complete on setup/data compete\r\n");
         }
-    break;
+      }
+      break;
 
     default:    // Invalid
       TU_BREAKPOINT();
-    break;
+      break;
   }
 }
 
-static void handle_epout_irq (uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+static void handle_epout_irq(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < ep_count; n++ )
-  {
-    if ( dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n) )
-    {
+  for (uint8_t n = 0; n < ep_count; n++) {
+    if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) {
       dwc2_epout_t* epout = &dwc2->epout[n];
 
       uint32_t const doepint = epout->doepint;
 
       // SETUP packet Setup Phase done.
-      if ( doepint & DOEPINT_STUP )
-      {
+      if (doepint & DOEPINT_STUP) {
         uint32_t clear_flag = DOEPINT_STUP;
 
         // STPKTRX is only available for version from 3_00a
-        if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
-        {
+        if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
           clear_flag |= DOEPINT_STPKTRX;
         }
 
@@ -1118,20 +978,16 @@ static void handle_epout_irq (uint8_t rhport)
       }
 
       // OUT XFER complete
-      if ( epout->doepint & DOEPINT_XFRC )
-      {
+      if (epout->doepint & DOEPINT_XFRC) {
         epout->doepint = DOEPINT_XFRC;
 
-        xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+        xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
         // EP0 can only handle one packet
-        if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
-        {
+        if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
           // Schedule another packet to be received.
           edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
-        }
-        else
-        {
+        } else {
           dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
         }
       }
@@ -1139,40 +995,32 @@ static void handle_epout_irq (uint8_t rhport)
   }
 }
 
-static void handle_epin_irq (uint8_t rhport)
-{
-  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+static void handle_epin_irq(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-  dwc2_epin_t* epin      = dwc2->epin;
+  dwc2_epin_t* epin = dwc2->epin;
 
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < ep_count; n++ )
-  {
-    if ( dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n) )
-    {
+  for (uint8_t n = 0; n < ep_count; n++) {
+    if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) {
       // IN XFER complete (entire xfer).
-      xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
+      xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
 
-      if ( epin[n].diepint & DIEPINT_XFRC )
-      {
+      if (epin[n].diepint & DIEPINT_XFRC) {
         epin[n].diepint = DIEPINT_XFRC;
 
         // EP0 can only handle one packet
-        if ( (n == 0) && ep0_pending[TUSB_DIR_IN] )
-        {
+        if ((n == 0) && ep0_pending[TUSB_DIR_IN]) {
           // Schedule another packet to be transmitted.
           edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
-        }
-        else
-        {
+        } else {
           dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
         }
       }
 
       // XFER FIFO empty
-      if ( (epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
-      {
+      if ((epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) {
         // diepint's TXFE bit is read-only, software cannot clear it.
         // It will only be cleared by hardware when written bytes is more than
         // - 64 bytes or
@@ -1181,8 +1029,7 @@ static void handle_epin_irq (uint8_t rhport)
         uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
 
         // Process every single packet (only whole packets can be written to fifo)
-        for ( uint16_t i = 0; i < remaining_packets; i++ )
-        {
+        for (uint16_t i = 0; i < remaining_packets; i++) {
           uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
 
           // Packet can not be larger than ep max size
@@ -1190,16 +1037,13 @@ static void handle_epin_irq (uint8_t rhport)
 
           // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
           // EP has to be checked if the buffer can take another WHOLE packet
-          if ( packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break;
+          if (packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
 
           // Push packet to Tx-FIFO
-          if ( xfer->ff )
-          {
-            volatile uint32_t *tx_fifo = dwc2->fifo[n];
+          if (xfer->ff) {
+            volatile uint32_t* tx_fifo = dwc2->fifo[n];
             tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
-          }
-          else
-          {
+          } else {
             write_fifo_packet(rhport, n, xfer->buffer, packet_size);
 
             // Increment pointer to xfer data
@@ -1208,8 +1052,7 @@ static void handle_epin_irq (uint8_t rhport)
         }
 
         // Turn off TXFE if all bytes are written.
-        if ( ((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 )
-        {
+        if (((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) {
           dwc2->diepempmsk &= ~(1 << n);
         }
       }
@@ -1217,55 +1060,49 @@ static void handle_epin_irq (uint8_t rhport)
   }
 }
 
-void dcd_int_handler(uint8_t rhport)
-{
-  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+void dcd_int_handler(uint8_t rhport) {
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   uint32_t const int_mask = dwc2->gintmsk;
   uint32_t const int_status = dwc2->gintsts & int_mask;
 
-  if(int_status & GINTSTS_USBRST)
-  {
+  if (int_status & GINTSTS_USBRST) {
     // USBRST is start of reset.
     dwc2->gintsts = GINTSTS_USBRST;
     bus_reset(rhport);
   }
 
-  if(int_status & GINTSTS_ENUMDNE)
-  {
+  if (int_status & GINTSTS_ENUMDNE) {
     // ENUMDNE is the end of reset where speed of the link is detected
 
     dwc2->gintsts = GINTSTS_ENUMDNE;
 
     tusb_speed_t speed;
-    switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos)
-    {
+    switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) {
       case DSTS_ENUMSPD_HS:
         speed = TUSB_SPEED_HIGH;
-      break;
+        break;
 
       case DSTS_ENUMSPD_LS:
         speed = TUSB_SPEED_LOW;
-      break;
+        break;
 
       case DSTS_ENUMSPD_FS_HSPHY:
       case DSTS_ENUMSPD_FS:
       default:
         speed = TUSB_SPEED_FULL;
-      break;
+        break;
     }
 
     dcd_event_bus_reset(rhport, speed, true);
   }
 
-  if(int_status & GINTSTS_USBSUSP)
-  {
+  if (int_status & GINTSTS_USBSUSP) {
     dwc2->gintsts = GINTSTS_USBSUSP;
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
-  if(int_status & GINTSTS_WKUINT)
-  {
+  if (int_status & GINTSTS_WKUINT) {
     dwc2->gintsts = GINTSTS_WKUINT;
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
@@ -1273,30 +1110,24 @@ void dcd_int_handler(uint8_t rhport)
   // TODO check GINTSTS_DISCINT for disconnect detection
   // if(int_status & GINTSTS_DISCINT)
 
-  if(int_status & GINTSTS_OTGINT)
-  {
+  if (int_status & GINTSTS_OTGINT) {
     // OTG INT bit is read-only
     uint32_t const otg_int = dwc2->gotgint;
 
-    if (otg_int & GOTGINT_SEDET)
-    {
+    if (otg_int & GOTGINT_SEDET) {
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
 
     dwc2->gotgint = otg_int;
   }
 
-  if(int_status & GINTSTS_SOF)
-  {
+  if (int_status & GINTSTS_SOF) {
     dwc2->gotgint = GINTSTS_SOF;
 
-    if (_sof_en)
-    {
+    if (_sof_en) {
       uint32_t frame = (dwc2->dsts & (DSTS_FNSOF)) >> 8;
       dcd_event_sof(rhport, frame, true);
-    }
-    else
-    {
+    } else {
       // Disable SOF interrupt if SOF was not explicitly enabled. SOF was used for remote wakeup detection
       dwc2->gintmsk &= ~GINTMSK_SOFM;
     }
@@ -1305,22 +1136,19 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   // RxFIFO non-empty interrupt handling.
-  if(int_status & GINTSTS_RXFLVL)
-  {
+  if (int_status & GINTSTS_RXFLVL) {
     // RXFLVL bit is read-only
 
     // Mask out RXFLVL while reading data from FIFO
     dwc2->gintmsk &= ~GINTMSK_RXFLVLM;
 
     // Loop until all available packets were handled
-    do
-    {
+    do {
       handle_rxflvl_irq(rhport);
-    } while(dwc2->gotgint & GINTSTS_RXFLVL);
+    } while (dwc2->gotgint & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
-    if (_out_ep_closed)
-    {
+    if (_out_ep_closed) {
       update_grxfsiz(rhport);
 
       // Disable flag
@@ -1331,15 +1159,13 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   // OUT endpoint interrupt handling.
-  if(int_status & GINTSTS_OEPINT)
-  {
+  if (int_status & GINTSTS_OEPINT) {
     // OEPINT is read-only, clear using DOEPINTn
     handle_epout_irq(rhport);
   }
 
   // IN endpoint interrupt handling.
-  if(int_status & GINTSTS_IEPINT)
-  {
+  if (int_status & GINTSTS_IEPINT) {
     // IEPINT bit read-only, clear using DIEPINTn
     handle_epin_irq(rhport);
   }
-- 
cgit v1.3.1


From 9f0223dccd9992f936054bae3c6256280af7f26a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Oct 2023 10:58:15 +0700
Subject: minor clean up

---
 hw/bsp/stm32f7/family.c                |    2 +-
 src/portable/synopsys/dwc2/dwc2_type.h | 1790 ++++++++++++++++----------------
 2 files changed, 911 insertions(+), 881 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index b504c435a..18cee073d 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -199,7 +199,7 @@ void board_init(void) {
   __HAL_RCC_OTGPHYC_CLK_ENABLE();
 
   #else
-  // MUC with external ULPI PHY
+  // MCU with external ULPI PHY
 
   /* ULPI CLK */
   GPIO_InitStruct.Pin = GPIO_PIN_5;
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 6516882da..c15771237 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -32,7 +32,7 @@ typedef struct
   uint32_t  ep_fifo_size;
 }dwc2_controller_t;
 
-/* DWC OTG HW Release versions */
+// DWC OTG HW Release versions
 #define DWC2_CORE_REV_2_71a   0x4f54271a
 #define DWC2_CORE_REV_2_72a   0x4f54272a
 #define DWC2_CORE_REV_2_80a   0x4f54280a
@@ -49,7 +49,7 @@ typedef struct
 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
 #define DWC2_CORE_REV_MASK    0x0000ffff
 
-/* DWC OTG HW Core ID */
+// DWC OTG HW Core ID
 #define DWC2_OTG_ID           0x4f540000
 #define DWC2_FS_IOT_ID        0x55310000
 #define DWC2_HS_IOT_ID        0x55320000
@@ -58,13 +58,13 @@ typedef struct
 // HS PHY
 typedef struct
 {
-  volatile uint32_t HS_PHYC_PLL;         // This register is used to control the PLL of the HS PHY.                       000h */
-  volatile uint32_t Reserved04;          // Reserved                                                                      004h */
-  volatile uint32_t Reserved08;          // Reserved                                                                      008h */
-  volatile uint32_t HS_PHYC_TUNE;        // This register is used to control the tuning interface of the High Speed PHY.  00Ch */
-  volatile uint32_t Reserved10;          // Reserved                                                                      010h */
-  volatile uint32_t Reserved14;          // Reserved                                                                      014h */
-  volatile uint32_t HS_PHYC_LDO;         // This register is used to control the regulator (LDO).                         018h */
+  volatile uint32_t HS_PHYC_PLL;         // 000h This register is used to control the PLL of the HS PHY.
+  volatile uint32_t Reserved04;          // 004h Reserved
+  volatile uint32_t Reserved08;          // 008h Reserved
+  volatile uint32_t HS_PHYC_TUNE;        // 00Ch This register is used to control the tuning interface of the High Speed PHY.
+  volatile uint32_t Reserved10;          // 010h Reserved
+  volatile uint32_t Reserved14;          // 014h Reserved
+  volatile uint32_t HS_PHYC_LDO;         // 018h This register is used to control the regulator (LDO).
 } HS_PHYC_GlobalTypeDef;
 #endif
 
@@ -299,103 +299,103 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 /********************  Bit definition for GOTGCTL register  ********************/
 #define GOTGCTL_SRQSCS_Pos               (0U)
-#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos)            // 0x00000001 */
-#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk                       // Session request success */
+#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos)            // 0x00000001
+#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk                       // Session request success
 #define GOTGCTL_SRQ_Pos                  (1U)
-#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos)               // 0x00000002 */
-#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk                          // Session request */
+#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos)               // 0x00000002
+#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk                          // Session request
 #define GOTGCTL_VBVALOEN_Pos             (2U)
-#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos)          // 0x00000004 */
-#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk                     // VBUS valid override enable */
+#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos)          // 0x00000004
+#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk                     // VBUS valid override enable
 #define GOTGCTL_VBVALOVAL_Pos            (3U)
-#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos)         // 0x00000008 */
-#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk                    // VBUS valid override value */
+#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos)         // 0x00000008
+#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk                    // VBUS valid override value
 #define GOTGCTL_AVALOEN_Pos              (4U)
-#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos)           // 0x00000010 */
-#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk                      // A-peripheral session valid override enable */
+#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos)           // 0x00000010
+#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk                      // A-peripheral session valid override enable
 #define GOTGCTL_AVALOVAL_Pos             (5U)
-#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos)          // 0x00000020 */
-#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk                     // A-peripheral session valid override value */
+#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos)          // 0x00000020
+#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk                     // A-peripheral session valid override value
 #define GOTGCTL_BVALOEN_Pos              (6U)
-#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos)           // 0x00000040 */
-#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk                      // B-peripheral session valid override enable */
+#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos)           // 0x00000040
+#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk                      // B-peripheral session valid override enable
 #define GOTGCTL_BVALOVAL_Pos             (7U)
-#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos)          // 0x00000080 */
-#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk                     // B-peripheral session valid override value  */
+#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos)          // 0x00000080
+#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk                     // B-peripheral session valid override value
 #define GOTGCTL_HNGSCS_Pos               (8U)
-#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos)            // 0x00000100 */
-#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk                       // Host set HNP enable */
+#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos)            // 0x00000100
+#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk                       // Host set HNP enable
 #define GOTGCTL_HNPRQ_Pos                (9U)
-#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos)             // 0x00000200 */
-#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk                        // HNP request */
+#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos)             // 0x00000200
+#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk                        // HNP request
 #define GOTGCTL_HSHNPEN_Pos              (10U)
-#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos)           // 0x00000400 */
-#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk                      // Host set HNP enable */
+#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos)           // 0x00000400
+#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk                      // Host set HNP enable
 #define GOTGCTL_DHNPEN_Pos               (11U)
-#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos)            // 0x00000800 */
-#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk                       // Device HNP enabled */
+#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos)            // 0x00000800
+#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk                       // Device HNP enabled
 #define GOTGCTL_EHEN_Pos                 (12U)
-#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos)              // 0x00001000 */
-#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk                         // Embedded host enable */
+#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos)              // 0x00001000
+#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk                         // Embedded host enable
 #define GOTGCTL_CIDSTS_Pos               (16U)
-#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos)            // 0x00010000 */
-#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk                       // Connector ID status */
+#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos)            // 0x00010000
+#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk                       // Connector ID status
 #define GOTGCTL_DBCT_Pos                 (17U)
-#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos)              // 0x00020000 */
-#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk                         // Long/short debounce time */
+#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos)              // 0x00020000
+#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk                         // Long/short debounce time
 #define GOTGCTL_ASVLD_Pos                (18U)
-#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos)             // 0x00040000 */
-#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk                        // A-session valid  */
+#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos)             // 0x00040000
+#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk                        // A-session valid
 #define GOTGCTL_BSESVLD_Pos              (19U)
-#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos)           // 0x00080000 */
-#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk                      // B-session valid */
+#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos)           // 0x00080000
+#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk                      // B-session valid
 #define GOTGCTL_OTGVER_Pos               (20U)
-#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos)            // 0x00100000 */
-#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk                       // OTG version  */
+#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos)            // 0x00100000
+#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk                       // OTG version
 
 /********************  Bit definition for HCFG register  ********************/
 #define HCFG_FSLSPCS_Pos                 (0U)
-#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos)              // 0x00000003 */
-#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk                         // FS/LS PHY clock select  */
-#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos)              // 0x00000001 */
-#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos)              // 0x00000002 */
+#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos)              // 0x00000003
+#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk                         // FS/LS PHY clock select
+#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos)              // 0x00000001
+#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos)              // 0x00000002
 #define HCFG_FSLSS_Pos                   (2U)
-#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                // 0x00000004 */
-#define HCFG_FSLSS                       HCFG_FSLSS_Msk                           // FS- and LS-only support */
+#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                // 0x00000004
+#define HCFG_FSLSS                       HCFG_FSLSS_Msk                           // FS- and LS-only support
 
 /********************  Bit definition for PCGCR register  ********************/
 #define PCGCR_STPPCLK_Pos                (0U)
-#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             // 0x00000001 */
-#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk                        // Stop PHY clock */
+#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             // 0x00000001
+#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk                        // Stop PHY clock
 #define PCGCR_GATEHCLK_Pos               (1U)
-#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos)            // 0x00000002 */
-#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk                       // Gate HCLK */
+#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos)            // 0x00000002
+#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk                       // Gate HCLK
 #define PCGCR_PHYSUSP_Pos                (4U)
-#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos)             // 0x00000010 */
-#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk                        // PHY suspended */
+#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos)             // 0x00000010
+#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk                        // PHY suspended
 
 /********************  Bit definition for GOTGINT register  ********************/
 #define GOTGINT_SEDET_Pos                (2U)
-#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos)             // 0x00000004 */
-#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk                        // Session end detected                   */
+#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos)             // 0x00000004
+#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk                        // Session end detected
 #define GOTGINT_SRSSCHG_Pos              (8U)
-#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos)           // 0x00000100 */
-#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk                      // Session request success status change  */
+#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos)           // 0x00000100
+#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk                      // Session request success status change
 #define GOTGINT_HNSSCHG_Pos              (9U)
-#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos)           // 0x00000200 */
-#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk                      // Host negotiation success status change */
+#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos)           // 0x00000200
+#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk                      // Host negotiation success status change
 #define GOTGINT_HNGDET_Pos               (17U)
-#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos)            // 0x00020000 */
-#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk                       // Host negotiation detected              */
+#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos)            // 0x00020000
+#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk                       // Host negotiation detected
 #define GOTGINT_ADTOCHG_Pos              (18U)
-#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos)           // 0x00040000 */
-#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk                      // A-device timeout change                */
+#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos)           // 0x00040000
+#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk                      // A-device timeout change
 #define GOTGINT_DBCDNE_Pos               (19U)
-#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos)            // 0x00080000 */
-#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk                       // Debounce done                          */
+#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos)            // 0x00080000
+#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk                       // Debounce done
 #define GOTGINT_IDCHNG_Pos               (20U)
-#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            // 0x00100000 */
-#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       // Change in ID pin input value           */
+#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            // 0x00100000
+#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       // Change in ID pin input value
 
 /********************  Bit definition for DCFG register  ********************/
 #define DCFG_DSPD_Pos                    (0U)
@@ -406,92 +406,92 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DCFG_DSPD_FS                     3    // Fullspeed on FS PHY
 
 #define DCFG_NZLSOHSK_Pos                (2U)
-#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004 */
-#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake */
+#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004
+#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake
 
 #define DCFG_DAD_Pos                     (4U)
-#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0 */
-#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address */
-#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010 */
-#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020 */
-#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040 */
-#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080 */
-#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100 */
-#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200 */
-#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400 */
+#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0
+#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address
+#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010
+#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020
+#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040
+#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080
+#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100
+#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200
+#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400
 
 #define DCFG_PFIVL_Pos                   (11U)
-#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800 */
-#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval */
-#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
-#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
+#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800
+#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval
+#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800
+#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000
 
 #define DCFG_XCVRDLY_Pos                 (14U)
-#define DCFG_XCVRDLY_Msk                 (0x1UL << DCFG_XCVRDLY_Pos)             /*!< 0x00004000 */
+#define DCFG_XCVRDLY_Msk                 (0x1UL << DCFG_XCVRDLY_Pos)             // 0x00004000
 #define DCFG_XCVRDLY                     DCFG_XCVRDLY_Msk                        // Enables delay between xcvr_sel and txvalid during device chirp
 
 #define DCFG_PERSCHIVL_Pos               (24U)
-#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
-#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */
-#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000 */
-#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000 */
+#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000
+#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval
+#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000
+#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000
 
 /********************  Bit definition for DCTL register  ********************/
 #define DCTL_RWUSIG_Pos                  (0U)
-#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               // 0x00000001 */
-#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk                          // Remote wakeup signaling */
+#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               // 0x00000001
+#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk                          // Remote wakeup signaling
 #define DCTL_SDIS_Pos                    (1U)
-#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos)                 // 0x00000002 */
-#define DCTL_SDIS                        DCTL_SDIS_Msk                            // Soft disconnect         */
+#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos)                 // 0x00000002
+#define DCTL_SDIS                        DCTL_SDIS_Msk                            // Soft disconnect
 #define DCTL_GINSTS_Pos                  (2U)
-#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos)               // 0x00000004 */
-#define DCTL_GINSTS                      DCTL_GINSTS_Msk                          // Global IN NAK status    */
+#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos)               // 0x00000004
+#define DCTL_GINSTS                      DCTL_GINSTS_Msk                          // Global IN NAK status
 #define DCTL_GONSTS_Pos                  (3U)
-#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos)               // 0x00000008 */
-#define DCTL_GONSTS                      DCTL_GONSTS_Msk                          // Global OUT NAK status   */
+#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos)               // 0x00000008
+#define DCTL_GONSTS                      DCTL_GONSTS_Msk                          // Global OUT NAK status
 
 #define DCTL_TCTL_Pos                    (4U)
-#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos)                 // 0x00000070 */
-#define DCTL_TCTL                        DCTL_TCTL_Msk                            // Test control */
-#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos)                 // 0x00000010 */
-#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos)                 // 0x00000020 */
-#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos)                 // 0x00000040 */
+#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos)                 // 0x00000070
+#define DCTL_TCTL                        DCTL_TCTL_Msk                            // Test control
+#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos)                 // 0x00000010
+#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos)                 // 0x00000020
+#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos)                 // 0x00000040
 #define DCTL_SGINAK_Pos                  (7U)
-#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos)               // 0x00000080 */
-#define DCTL_SGINAK                      DCTL_SGINAK_Msk                          // Set global IN NAK         */
+#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos)               // 0x00000080
+#define DCTL_SGINAK                      DCTL_SGINAK_Msk                          // Set global IN NAK
 #define DCTL_CGINAK_Pos                  (8U)
-#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos)               // 0x00000100 */
-#define DCTL_CGINAK                      DCTL_CGINAK_Msk                          // Clear global IN NAK       */
+#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos)               // 0x00000100
+#define DCTL_CGINAK                      DCTL_CGINAK_Msk                          // Clear global IN NAK
 #define DCTL_SGONAK_Pos                  (9U)
-#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos)               // 0x00000200 */
-#define DCTL_SGONAK                      DCTL_SGONAK_Msk                          // Set global OUT NAK        */
+#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos)               // 0x00000200
+#define DCTL_SGONAK                      DCTL_SGONAK_Msk                          // Set global OUT NAK
 #define DCTL_CGONAK_Pos                  (10U)
-#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos)               // 0x00000400 */
-#define DCTL_CGONAK                      DCTL_CGONAK_Msk                          // Clear global OUT NAK      */
+#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos)               // 0x00000400
+#define DCTL_CGONAK                      DCTL_CGONAK_Msk                          // Clear global OUT NAK
 #define DCTL_POPRGDNE_Pos                (11U)
-#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos)             // 0x00000800 */
-#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk                        // Power-on programming done */
+#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos)             // 0x00000800
+#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk                        // Power-on programming done
 
 /********************  Bit definition for HFIR register  ********************/
 #define HFIR_FRIVL_Pos                   (0U)
-#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos)             // 0x0000FFFF */
-#define HFIR_FRIVL                       HFIR_FRIVL_Msk                           // Frame interval */
+#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos)             // 0x0000FFFF
+#define HFIR_FRIVL                       HFIR_FRIVL_Msk                           // Frame interval
 
 /********************  Bit definition for HFNUM register  ********************/
 #define HFNUM_FRNUM_Pos                  (0U)
-#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos)            // 0x0000FFFF */
-#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk                          // Frame number         */
+#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos)            // 0x0000FFFF
+#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk                          // Frame number
 #define HFNUM_FTREM_Pos                  (16U)
-#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos)            // 0xFFFF0000 */
-#define HFNUM_FTREM                      HFNUM_FTREM_Msk                          // Frame time remaining */
+#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos)            // 0xFFFF0000
+#define HFNUM_FTREM                      HFNUM_FTREM_Msk                          // Frame time remaining
 
 /********************  Bit definition for DSTS register  ********************/
 #define DSTS_SUSPSTS_Pos                 (0U)
-#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              // 0x00000001 */
-#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         // Suspend status   */
+#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              // 0x00000001
+#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         // Suspend status
 #define DSTS_ENUMSPD_Pos                 (1U)
-#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              // 0x00000006 */
-#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         // Enumerated speed */
+#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              // 0x00000006
+#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         // Enumerated speed
 #define DSTS_ENUMSPD_HS                  0    // Highspeed
 #define DSTS_ENUMSPD_FS_HSPHY            1    // Fullspeed on HS PHY
 #define DSTS_ENUMSPD_LS                  2    // Lowspeed
@@ -499,427 +499,427 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 
 #define DSTS_EERR_Pos                    (3U)
-#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 // 0x00000008 */
-#define DSTS_EERR                        DSTS_EERR_Msk                            // Erratic error     */
+#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 // 0x00000008
+#define DSTS_EERR                        DSTS_EERR_Msk                            // Erratic error
 #define DSTS_FNSOF_Pos                   (8U)
-#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos)             // 0x003FFF00 */
-#define DSTS_FNSOF                       DSTS_FNSOF_Msk                           // Frame number of the received SOF */
+#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos)             // 0x003FFF00
+#define DSTS_FNSOF                       DSTS_FNSOF_Msk                           // Frame number of the received SOF
 
 /********************  Bit definition for GAHBCFG register  ********************/
 #define GAHBCFG_GINT_Pos                 (0U)
-#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos)              // 0x00000001 */
-#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk                         // Global interrupt mask */
+#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos)              // 0x00000001
+#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk                         // Global interrupt mask
 #define GAHBCFG_HBSTLEN_Pos              (1U)
-#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos)           // 0x0000001E */
-#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk                      // Burst length/type */
-#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos)           // Single */
-#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos)           // INCR */
-#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos)           // INCR4 */
-#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos)           // INCR8 */
-#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos)           // INCR16 */
+#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos)           // 0x0000001E
+#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk                      // Burst length/type
+#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos)           // Single
+#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos)           // INCR
+#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos)           // INCR4
+#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos)           // INCR8
+#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos)           // INCR16
 #define GAHBCFG_DMAEN_Pos                (5U)
-#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos)             // 0x00000020 */
-#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk                        // DMA enable */
+#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos)             // 0x00000020
+#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk                        // DMA enable
 #define GAHBCFG_TXFELVL_Pos              (7U)
-#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos)           // 0x00000080 */
-#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk                      // TxFIFO empty level */
+#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos)           // 0x00000080
+#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk                      // TxFIFO empty level
 #define GAHBCFG_PTXFELVL_Pos             (8U)
-#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100 */
-#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level */
+#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100
+#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level
 
 #define GSNPSID_ID_MASK                 TU_GENMASK(31, 16)
 
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
-#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007 */
-#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        // FS timeout calibration */
+#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007
+#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        // FS timeout calibration
 #define GUSBCFG_PHYIF16_Pos              (3U)
-#define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)             // 0x00000008 */
-#define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                        // PHY Interface (PHYIf) */
+#define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)           // 0x00000008
+#define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                      // PHY Interface (PHYIf)
 #define GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
-#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     // 0x00000010 */
-#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
+#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     // 0x00000010
+#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                // ULPI or UTMI+ Select (ULPI_UTMI_Sel)
 #define GUSBCFG_PHYSEL_Pos               (6U)
-#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
-#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040
+#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
 #define GUSBCFG_DDRSEL                   TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
 #define GUSBCFG_SRPCAP_Pos               (8U)
-#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
-#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
+#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100
+#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable
 #define GUSBCFG_HNPCAP_Pos               (9U)
-#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos)            // 0x00000200 */
-#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk                       // HNP-capable */
+#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos)            // 0x00000200
+#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk                       // HNP-capable
 #define GUSBCFG_TRDT_Pos                 (10U)
-#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              // 0x00003C00 */
-#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         // USB turnaround time */
+#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              // 0x00003C00
+#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         // USB turnaround time
 #define GUSBCFG_PHYLPCS_Pos              (15U)
-#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           // 0x00008000 */
-#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      // PHY Low-power clock select */
+#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           // 0x00008000
+#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      // PHY Low-power clock select
 #define GUSBCFG_ULPIFSLS_Pos             (17U)
-#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos)          // 0x00020000 */
-#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk                     // ULPI FS/LS select               */
+#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos)          // 0x00020000
+#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk                     // ULPI FS/LS select
 #define GUSBCFG_ULPIAR_Pos               (18U)
-#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos)            // 0x00040000 */
-#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk                       // ULPI Auto-resume                */
+#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos)            // 0x00040000
+#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk                       // ULPI Auto-resume
 #define GUSBCFG_ULPICSM_Pos              (19U)
-#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos)           // 0x00080000 */
-#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk                      // ULPI Clock SuspendM             */
+#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos)           // 0x00080000
+#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk                      // ULPI Clock SuspendM
 #define GUSBCFG_ULPIEVBUSD_Pos           (20U)
-#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos)        // 0x00100000 */
-#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk                   // ULPI External VBUS Drive        */
+#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos)        // 0x00100000
+#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk                   // ULPI External VBUS Drive
 #define GUSBCFG_ULPIEVBUSI_Pos           (21U)
-#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos)        // 0x00200000 */
-#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk                   // ULPI external VBUS indicator    */
+#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos)        // 0x00200000
+#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk                   // ULPI external VBUS indicator
 #define GUSBCFG_TSDPS_Pos                (22U)
-#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos)             // 0x00400000 */
-#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk                        // TermSel DLine pulsing selection */
+#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos)             // 0x00400000
+#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk                        // TermSel DLine pulsing selection
 #define GUSBCFG_PCCI_Pos                 (23U)
-#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos)              // 0x00800000 */
-#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk                         // Indicator complement            */
+#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos)              // 0x00800000
+#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk                         // Indicator complement
 #define GUSBCFG_PTCI_Pos                 (24U)
-#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos)              // 0x01000000 */
-#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk                         // Indicator pass through          */
+#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos)              // 0x01000000
+#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk                         // Indicator pass through
 #define GUSBCFG_ULPIIPD_Pos              (25U)
-#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos)           // 0x02000000 */
-#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk                      // ULPI interface protect disable  */
+#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos)           // 0x02000000
+#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk                      // ULPI interface protect disable
 #define GUSBCFG_FHMOD_Pos                (29U)
-#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos)             // 0x20000000 */
-#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk                        // Forced host mode                */
+#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos)             // 0x20000000
+#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk                        // Forced host mode
 #define GUSBCFG_FDMOD_Pos                (30U)
-#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos)             // 0x40000000 */
-#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk                        // Forced peripheral mode          */
+#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos)             // 0x40000000
+#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk                        // Forced peripheral mode
 #define GUSBCFG_CTXPKT_Pos               (31U)
-#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos)            // 0x80000000 */
-#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk                       // Corrupt Tx packet               */
+#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos)            // 0x80000000
+#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk                       // Corrupt Tx packet
 
 /********************  Bit definition for GRSTCTL register  ********************/
 #define GRSTCTL_CSRST_Pos                (0U)
-#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos)             // 0x00000001 */
-#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk                        // Core soft reset          */
+#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos)             // 0x00000001
+#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk                        // Core soft reset
 #define GRSTCTL_HSRST_Pos                (1U)
-#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos)             // 0x00000002 */
-#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk                        // HCLK soft reset          */
+#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos)             // 0x00000002
+#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk                        // HCLK soft reset
 #define GRSTCTL_FCRST_Pos                (2U)
-#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos)             // 0x00000004 */
-#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk                        // Host frame counter reset */
+#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos)             // 0x00000004
+#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk                        // Host frame counter reset
 #define GRSTCTL_RXFFLSH_Pos              (4U)
-#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos)           // 0x00000010 */
-#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk                      // RxFIFO flush             */
+#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos)           // 0x00000010
+#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk                      // RxFIFO flush
 #define GRSTCTL_TXFFLSH_Pos              (5U)
-#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos)           // 0x00000020 */
-#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk                      // TxFIFO flush             */
+#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos)           // 0x00000020
+#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk                      // TxFIFO flush
 #define GRSTCTL_TXFNUM_Pos               (6U)
-#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos)           // 0x000007C0 */
-#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk                       // TxFIFO number */
-#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos)           // 0x00000040 */
-#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos)           // 0x00000080 */
-#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100 */
-#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200 */
-#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400 */
+#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos)           // 0x000007C0
+#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk                       // TxFIFO number
+#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos)           // 0x00000040
+#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos)           // 0x00000080
+#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100
+#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200
+#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400
 #define GRSTCTL_CSFTRST_DONE_Pos       (29)
 #define GRSTCTL_CSFTRST_DONE           (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
 #define GRSTCTL_DMAREQ_Pos               (30U)
-#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000 */
-#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal */
+#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000
+#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal
 #define GRSTCTL_AHBIDL_Pos               (31U)
-#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos)            // 0x80000000 */
-#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk                       // AHB master idle */
+#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos)            // 0x80000000
+#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk                       // AHB master idle
 
 /********************  Bit definition for DIEPMSK register  ********************/
 #define DIEPMSK_XFRCM_Pos                (0U)
-#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos)             // 0x00000001 */
-#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask                 */
+#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos)             // 0x00000001
+#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask
 #define DIEPMSK_EPDM_Pos                 (1U)
-#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos)              // 0x00000002 */
-#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask                  */
+#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos)              // 0x00000002
+#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask
 #define DIEPMSK_TOM_Pos                  (3U)
-#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos)               // 0x00000008 */
-#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk                          // Timeout condition mask (nonisochronous endpoints) */
+#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos)               // 0x00000008
+#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk                          // Timeout condition mask (nonisochronous endpoints)
 #define DIEPMSK_ITTXFEMSK_Pos            (4U)
-#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos)         // 0x00000010 */
-#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk                    // IN token received when TxFIFO empty mask          */
+#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos)         // 0x00000010
+#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk                    // IN token received when TxFIFO empty mask
 #define DIEPMSK_INEPNMM_Pos              (5U)
-#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos)           // 0x00000020 */
-#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk                      // IN token received with EP mismatch mask           */
+#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos)           // 0x00000020
+#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk                      // IN token received with EP mismatch mask
 #define DIEPMSK_INEPNEM_Pos              (6U)
-#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos)           // 0x00000040 */
-#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk                      // IN endpoint NAK effective mask                    */
+#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos)           // 0x00000040
+#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk                      // IN endpoint NAK effective mask
 #define DIEPMSK_TXFURM_Pos               (8U)
-#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos)            // 0x00000100 */
-#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk                       // FIFO underrun mask                                */
+#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos)            // 0x00000100
+#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk                       // FIFO underrun mask
 #define DIEPMSK_BIM_Pos                  (9U)
-#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos)               // 0x00000200 */
-#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk                          // BNA interrupt mask                                */
+#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos)               // 0x00000200
+#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk                          // BNA interrupt mask
 
 /********************  Bit definition for HPTXSTS register  ********************/
 #define HPTXSTS_PTXFSAVL_Pos             (0U)
-#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos)       // 0x0000FFFF */
-#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk                     // Periodic transmit data FIFO space available     */
+#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos)       // 0x0000FFFF
+#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk                     // Periodic transmit data FIFO space available
 #define HPTXSTS_PTXQSAV_Pos              (16U)
-#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos)          // 0x00FF0000 */
-#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk                      // Periodic transmit request queue space available */
-#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos)          // 0x00010000 */
-#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos)          // 0x00020000 */
-#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos)          // 0x00040000 */
-#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos)          // 0x00080000 */
-#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos)          // 0x00100000 */
-#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos)          // 0x00200000 */
-#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos)          // 0x00400000 */
-#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos)          // 0x00800000 */
+#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos)          // 0x00FF0000
+#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk                      // Periodic transmit request queue space available
+#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos)          // 0x00010000
+#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos)          // 0x00020000
+#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos)          // 0x00040000
+#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos)          // 0x00080000
+#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos)          // 0x00100000
+#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos)          // 0x00200000
+#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos)          // 0x00400000
+#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos)          // 0x00800000
 
 #define HPTXSTS_PTXQTOP_Pos              (24U)
-#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos)          // 0xFF000000 */
-#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk                      // Top of the periodic transmit request queue */
-#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos)          // 0x01000000 */
-#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos)          // 0x02000000 */
-#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos)          // 0x04000000 */
-#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos)          // 0x08000000 */
-#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos)          // 0x10000000 */
-#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos)          // 0x20000000 */
-#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos)          // 0x40000000 */
-#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos)          // 0x80000000 */
+#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos)          // 0xFF000000
+#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk                      // Top of the periodic transmit request queue
+#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos)          // 0x01000000
+#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos)          // 0x02000000
+#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos)          // 0x04000000
+#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos)          // 0x08000000
+#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos)          // 0x10000000
+#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos)          // 0x20000000
+#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos)          // 0x40000000
+#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos)          // 0x80000000
 
 /********************  Bit definition for HAINT register  ********************/
 #define HAINT_HAINT_Pos                  (0U)
-#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos)            // 0x0000FFFF */
-#define HAINT_HAINT                      HAINT_HAINT_Msk                          // Channel interrupts */
+#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos)            // 0x0000FFFF
+#define HAINT_HAINT                      HAINT_HAINT_Msk                          // Channel interrupts
 
 /********************  Bit definition for DOEPMSK register  ********************/
 #define DOEPMSK_XFRCM_Pos                (0U)
-#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos)             // 0x00000001 */
-#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask */
+#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos)             // 0x00000001
+#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask
 #define DOEPMSK_EPDM_Pos                 (1U)
-#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos)              // 0x00000002 */
-#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask               */
+#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos)              // 0x00000002
+#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask
 #define DOEPMSK_AHBERRM_Pos              (2U)
-#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos)           // 0x00000004 */
-#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk                      // OUT transaction AHB Error interrupt mask    */
+#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos)           // 0x00000004
+#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk                      // OUT transaction AHB Error interrupt mask
 #define DOEPMSK_STUPM_Pos                (3U)
-#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos)             // 0x00000008 */
-#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk                        // SETUP phase done mask                          */
+#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos)             // 0x00000008
+#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk                        // SETUP phase done mask
 #define DOEPMSK_OTEPDM_Pos               (4U)
-#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos)            // 0x00000010 */
-#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk                       // OUT token received when endpoint disabled mask */
+#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos)            // 0x00000010
+#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk                       // OUT token received when endpoint disabled mask
 #define DOEPMSK_OTEPSPRM_Pos             (5U)
-#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos)          // 0x00000020 */
-#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk                     // Status Phase Received mask                     */
+#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos)          // 0x00000020
+#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk                     // Status Phase Received mask
 #define DOEPMSK_B2BSTUP_Pos              (6U)
-#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos)           // 0x00000040 */
-#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk                      // Back-to-back SETUP packets received mask       */
+#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos)           // 0x00000040
+#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk                      // Back-to-back SETUP packets received mask
 #define DOEPMSK_OPEM_Pos                 (8U)
-#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos)              // 0x00000100 */
-#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk                         // OUT packet error mask                          */
+#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos)              // 0x00000100
+#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk                         // OUT packet error mask
 #define DOEPMSK_BOIM_Pos                 (9U)
-#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos)              // 0x00000200 */
-#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk                         // BNA interrupt mask                             */
+#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos)              // 0x00000200
+#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk                         // BNA interrupt mask
 #define DOEPMSK_BERRM_Pos                (12U)
-#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos)             // 0x00001000 */
-#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk                        // Babble error interrupt mask                   */
+#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos)             // 0x00001000
+#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk                        // Babble error interrupt mask
 #define DOEPMSK_NAKM_Pos                 (13U)
-#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos)              // 0x00002000 */
-#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk                         // OUT Packet NAK interrupt mask                  */
+#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos)              // 0x00002000
+#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk                         // OUT Packet NAK interrupt mask
 #define DOEPMSK_NYETM_Pos                (14U)
-#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos)             // 0x00004000 */
-#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk                        // NYET interrupt mask                           */
+#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos)             // 0x00004000
+#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk                        // NYET interrupt mask
 
 /********************  Bit definition for GINTSTS register  ********************/
 #define GINTSTS_CMOD_Pos                 (0U)
-#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos)              // 0x00000001 */
-#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk                         // Current mode of operation                      */
+#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos)              // 0x00000001
+#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk                         // Current mode of operation
 #define GINTSTS_MMIS_Pos                 (1U)
-#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos)              // 0x00000002 */
-#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk                         // Mode mismatch interrupt                        */
+#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos)              // 0x00000002
+#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk                         // Mode mismatch interrupt
 #define GINTSTS_OTGINT_Pos               (2U)
-#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos)            // 0x00000004 */
-#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk                       // OTG interrupt                                  */
+#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos)            // 0x00000004
+#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk                       // OTG interrupt
 #define GINTSTS_SOF_Pos                  (3U)
-#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos)               // 0x00000008 */
-#define GINTSTS_SOF                      GINTSTS_SOF_Msk                          // Start of frame                                 */
+#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos)               // 0x00000008
+#define GINTSTS_SOF                      GINTSTS_SOF_Msk                          // Start of frame
 #define GINTSTS_RXFLVL_Pos               (4U)
-#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos)            // 0x00000010 */
-#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk                       // RxFIFO nonempty                                */
+#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos)            // 0x00000010
+#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk                       // RxFIFO nonempty
 #define GINTSTS_NPTXFE_Pos               (5U)
-#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos)            // 0x00000020 */
-#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk                       // Nonperiodic TxFIFO empty                       */
+#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos)            // 0x00000020
+#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk                       // Nonperiodic TxFIFO empty
 #define GINTSTS_GINAKEFF_Pos             (6U)
-#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos)          // 0x00000040 */
-#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk                     // Global IN nonperiodic NAK effective            */
+#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos)          // 0x00000040
+#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk                     // Global IN nonperiodic NAK effective
 #define GINTSTS_BOUTNAKEFF_Pos           (7U)
-#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos)        // 0x00000080 */
-#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk                   // Global OUT NAK effective                       */
+#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos)        // 0x00000080
+#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk                   // Global OUT NAK effective
 #define GINTSTS_ESUSP_Pos                (10U)
-#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos)             // 0x00000400 */
-#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk                        // Early suspend                                  */
+#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos)             // 0x00000400
+#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk                        // Early suspend
 #define GINTSTS_USBSUSP_Pos              (11U)
-#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos)           // 0x00000800 */
-#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk                      // USB suspend                                    */
+#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos)           // 0x00000800
+#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk                      // USB suspend
 #define GINTSTS_USBRST_Pos               (12U)
-#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos)            // 0x00001000 */
-#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk                       // USB reset                                      */
+#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos)            // 0x00001000
+#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk                       // USB reset
 #define GINTSTS_ENUMDNE_Pos              (13U)
-#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos)           // 0x00002000 */
-#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk                      // Enumeration done                               */
+#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos)           // 0x00002000
+#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk                      // Enumeration done
 #define GINTSTS_ISOODRP_Pos              (14U)
-#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos)           // 0x00004000 */
-#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk                      // Isochronous OUT packet dropped interrupt       */
+#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos)           // 0x00004000
+#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk                      // Isochronous OUT packet dropped interrupt
 #define GINTSTS_EOPF_Pos                 (15U)
-#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos)              // 0x00008000 */
-#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk                         // End of periodic frame interrupt                */
+#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos)              // 0x00008000
+#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk                         // End of periodic frame interrupt
 #define GINTSTS_IEPINT_Pos               (18U)
-#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos)            // 0x00040000 */
-#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk                       // IN endpoint interrupt                          */
+#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos)            // 0x00040000
+#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk                       // IN endpoint interrupt
 #define GINTSTS_OEPINT_Pos               (19U)
-#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos)            // 0x00080000 */
-#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk                       // OUT endpoint interrupt                         */
+#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos)            // 0x00080000
+#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk                       // OUT endpoint interrupt
 #define GINTSTS_IISOIXFR_Pos             (20U)
-#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos)          // 0x00100000 */
-#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk                     // Incomplete isochronous IN transfer             */
+#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos)          // 0x00100000
+#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk                     // Incomplete isochronous IN transfer
 #define GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
-#define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000 */
-#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk            // Incomplete periodic transfer                   */
+#define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000
+#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk            // Incomplete periodic transfer
 #define GINTSTS_DATAFSUSP_Pos            (22U)
-#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos)         // 0x00400000 */
-#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk                    // Data fetch suspended                           */
+#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos)         // 0x00400000
+#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk                    // Data fetch suspended
 #define GINTSTS_RSTDET_Pos               (23U)
-#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos)            // 0x00800000 */
-#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk                       // Reset detected interrupt                       */
+#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos)            // 0x00800000
+#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk                       // Reset detected interrupt
 #define GINTSTS_HPRTINT_Pos              (24U)
-#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos)           // 0x01000000 */
-#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk                      // Host port interrupt                            */
+#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos)           // 0x01000000
+#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk                      // Host port interrupt
 #define GINTSTS_HCINT_Pos                (25U)
-#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos)             // 0x02000000 */
-#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk                        // Host channels interrupt                        */
+#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos)             // 0x02000000
+#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk                        // Host channels interrupt
 #define GINTSTS_PTXFE_Pos                (26U)
-#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos)             // 0x04000000 */
-#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk                        // Periodic TxFIFO empty                          */
+#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos)             // 0x04000000
+#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk                        // Periodic TxFIFO empty
 #define GINTSTS_LPMINT_Pos               (27U)
-#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos)            // 0x08000000 */
-#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk                       // LPM interrupt                                  */
+#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos)            // 0x08000000
+#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk                       // LPM interrupt
 #define GINTSTS_CIDSCHG_Pos              (28U)
-#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos)           // 0x10000000 */
-#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk                      // Connector ID status change                     */
+#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos)           // 0x10000000
+#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk                      // Connector ID status change
 #define GINTSTS_DISCINT_Pos              (29U)
-#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos)           // 0x20000000 */
-#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk                      // Disconnect detected interrupt                  */
+#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos)           // 0x20000000
+#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk                      // Disconnect detected interrupt
 #define GINTSTS_SRQINT_Pos               (30U)
-#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos)            // 0x40000000 */
-#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk                       // Session request/new session detected interrupt */
+#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos)            // 0x40000000
+#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk                       // Session request/new session detected interrupt
 #define GINTSTS_WKUINT_Pos               (31U)
-#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos)            // 0x80000000 */
-#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk                       // Resume/remote wakeup detected interrupt        */
+#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos)            // 0x80000000
+#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk                       // Resume/remote wakeup detected interrupt
 
 /********************  Bit definition for GINTMSK register  ********************/
 #define GINTMSK_MMISM_Pos                (1U)
-#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos)             // 0x00000002 */
-#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk                        // Mode mismatch interrupt mask                        */
+#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos)             // 0x00000002
+#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk                        // Mode mismatch interrupt mask
 #define GINTMSK_OTGINT_Pos               (2U)
-#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos)            // 0x00000004 */
-#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk                       // OTG interrupt mask                                  */
+#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos)            // 0x00000004
+#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk                       // OTG interrupt mask
 #define GINTMSK_SOFM_Pos                 (3U)
-#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos)              // 0x00000008 */
-#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk                         // Start of frame mask                                 */
+#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos)              // 0x00000008
+#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk                         // Start of frame mask
 #define GINTMSK_RXFLVLM_Pos              (4U)
-#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos)           // 0x00000010 */
-#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk                      // Receive FIFO nonempty mask                          */
+#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos)           // 0x00000010
+#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk                      // Receive FIFO nonempty mask
 #define GINTMSK_NPTXFEM_Pos              (5U)
-#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos)           // 0x00000020 */
-#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk                      // Nonperiodic TxFIFO empty mask                       */
+#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos)           // 0x00000020
+#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk                      // Nonperiodic TxFIFO empty mask
 #define GINTMSK_GINAKEFFM_Pos            (6U)
-#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos)         // 0x00000040 */
-#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk                    // Global nonperiodic IN NAK effective mask            */
+#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos)         // 0x00000040
+#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk                    // Global nonperiodic IN NAK effective mask
 #define GINTMSK_GONAKEFFM_Pos            (7U)
-#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos)         // 0x00000080 */
-#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk                    // Global OUT NAK effective mask                       */
+#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos)         // 0x00000080
+#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk                    // Global OUT NAK effective mask
 #define GINTMSK_ESUSPM_Pos               (10U)
-#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos)            // 0x00000400 */
-#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk                       // Early suspend mask                                  */
+#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos)            // 0x00000400
+#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk                       // Early suspend mask
 #define GINTMSK_USBSUSPM_Pos             (11U)
-#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos)          // 0x00000800 */
-#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk                     // USB suspend mask                                    */
+#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos)          // 0x00000800
+#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk                     // USB suspend mask
 #define GINTMSK_USBRST_Pos               (12U)
-#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos)            // 0x00001000 */
-#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk                       // USB reset mask                                      */
+#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos)            // 0x00001000
+#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk                       // USB reset mask
 #define GINTMSK_ENUMDNEM_Pos             (13U)
-#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos)          // 0x00002000 */
-#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk                     // Enumeration done mask                               */
+#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos)          // 0x00002000
+#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk                     // Enumeration done mask
 #define GINTMSK_ISOODRPM_Pos             (14U)
-#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos)          // 0x00004000 */
-#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk                     // Isochronous OUT packet dropped interrupt mask       */
+#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos)          // 0x00004000
+#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk                     // Isochronous OUT packet dropped interrupt mask
 #define GINTMSK_EOPFM_Pos                (15U)
-#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos)             // 0x00008000 */
-#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk                        // End of periodic frame interrupt mask                */
+#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos)             // 0x00008000
+#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk                        // End of periodic frame interrupt mask
 #define GINTMSK_EPMISM_Pos               (17U)
-#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos)            // 0x00020000 */
-#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk                       // Endpoint mismatch interrupt mask                    */
+#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos)            // 0x00020000
+#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk                       // Endpoint mismatch interrupt mask
 #define GINTMSK_IEPINT_Pos               (18U)
-#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos)            // 0x00040000 */
-#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk                       // IN endpoints interrupt mask                         */
+#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos)            // 0x00040000
+#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk                       // IN endpoints interrupt mask
 #define GINTMSK_OEPINT_Pos               (19U)
-#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos)            // 0x00080000 */
-#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk                       // OUT endpoints interrupt mask                        */
+#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos)            // 0x00080000
+#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk                       // OUT endpoints interrupt mask
 #define GINTMSK_IISOIXFRM_Pos            (20U)
-#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos)         // 0x00100000 */
-#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk                    // Incomplete isochronous IN transfer mask             */
+#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos)         // 0x00100000
+#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk                    // Incomplete isochronous IN transfer mask
 #define GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
-#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos)   // 0x00200000 */
-#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk              // Incomplete periodic transfer mask                   */
+#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos)   // 0x00200000
+#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk              // Incomplete periodic transfer mask
 #define GINTMSK_FSUSPM_Pos               (22U)
-#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos)            // 0x00400000 */
-#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk                       // Data fetch suspended mask                           */
+#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos)            // 0x00400000
+#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk                       // Data fetch suspended mask
 #define GINTMSK_RSTDEM_Pos               (23U)
-#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos)            // 0x00800000 */
-#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk                       // Reset detected interrupt mask                       */
+#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos)            // 0x00800000
+#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk                       // Reset detected interrupt mask
 #define GINTMSK_PRTIM_Pos                (24U)
-#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos)             // 0x01000000 */
-#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk                        // Host port interrupt mask                            */
+#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos)             // 0x01000000
+#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk                        // Host port interrupt mask
 #define GINTMSK_HCIM_Pos                 (25U)
-#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos)              // 0x02000000 */
-#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk                         // Host channels interrupt mask                        */
+#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos)              // 0x02000000
+#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk                         // Host channels interrupt mask
 #define GINTMSK_PTXFEM_Pos               (26U)
-#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos)            // 0x04000000 */
-#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk                       // Periodic TxFIFO empty mask                          */
+#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos)            // 0x04000000
+#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk                       // Periodic TxFIFO empty mask
 #define GINTMSK_LPMINTM_Pos              (27U)
-#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos)           // 0x08000000 */
-#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk                      // LPM interrupt Mask                                  */
+#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos)           // 0x08000000
+#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk                      // LPM interrupt Mask
 #define GINTMSK_CIDSCHGM_Pos             (28U)
-#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos)          // 0x10000000 */
-#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk                     // Connector ID status change mask                     */
+#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos)          // 0x10000000
+#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk                     // Connector ID status change mask
 #define GINTMSK_DISCINT_Pos              (29U)
-#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos)           // 0x20000000 */
-#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk                      // Disconnect detected interrupt mask                  */
+#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos)           // 0x20000000
+#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk                      // Disconnect detected interrupt mask
 #define GINTMSK_SRQIM_Pos                (30U)
-#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos)             // 0x40000000 */
-#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk                        // Session request/new session detected interrupt mask */
+#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos)             // 0x40000000
+#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk                        // Session request/new session detected interrupt mask
 #define GINTMSK_WUIM_Pos                 (31U)
-#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos)              // 0x80000000 */
-#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk                         // Resume/remote wakeup detected interrupt mask        */
+#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos)              // 0x80000000
+#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk                         // Resume/remote wakeup detected interrupt mask
 
 /********************  Bit definition for DAINT register  ********************/
 #define DAINT_IEPINT_Pos                 (0U)
-#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos)           // 0x0000FFFF */
-#define DAINT_IEPINT                     DAINT_IEPINT_Msk                         // IN endpoint interrupt bits  */
+#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos)           // 0x0000FFFF
+#define DAINT_IEPINT                     DAINT_IEPINT_Msk                         // IN endpoint interrupt bits
 #define DAINT_OEPINT_Pos                 (16U)
-#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos)           // 0xFFFF0000 */
-#define DAINT_OEPINT                     DAINT_OEPINT_Msk                         // OUT endpoint interrupt bits */
+#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos)           // 0xFFFF0000
+#define DAINT_OEPINT                     DAINT_OEPINT_Msk                         // OUT endpoint interrupt bits
 
 /********************  Bit definition for HAINTMSK register  ********************/
 #define HAINTMSK_HAINTM_Pos              (0U)
-#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos)        // 0x0000FFFF */
-#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk                      // Channel interrupt mask */
+#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos)        // 0x0000FFFF
+#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk                      // Channel interrupt mask
 
 /********************  Bit definition for GRXSTSP register  ********************/
 #define GRXSTSP_EPNUM_Pos                (0U)
-#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos)             // 0x0000000F */
-#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk                        // IN EP interrupt mask bits  */
+#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos)             // 0x0000000F
+#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk                        // IN EP interrupt mask bits
 #define GRXSTSP_BCNT_Pos                 (4U)
-#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos)            // 0x00007FF0 */
-#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk                         // OUT EP interrupt mask bits */
+#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos)            // 0x00007FF0
+#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk                         // OUT EP interrupt mask bits
 #define GRXSTSP_DPID_Pos                 (15U)
-#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos)              // 0x00018000 */
-#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk                         // OUT EP interrupt mask bits */
+#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos)              // 0x00018000
+#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk                         // OUT EP interrupt mask bits
 #define GRXSTSP_PKTSTS_Pos               (17U)
-#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            // 0x001E0000 */
-#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       // OUT EP interrupt mask bits */
+#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            // 0x001E0000
+#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       // OUT EP interrupt mask bits
 
 #define GRXSTS_PKTSTS_GLOBALOUTNAK       1
 #define GRXSTS_PKTSTS_OUTRX              2
@@ -934,773 +934,803 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 /********************  Bit definition for DAINTMSK register  ********************/
 #define DAINTMSK_IEPM_Pos                (0U)
-#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          // 0x0000FFFF */
-#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk                        // IN EP interrupt mask bits */
+#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          // 0x0000FFFF
+#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk                        // IN EP interrupt mask bits
 #define DAINTMSK_OEPM_Pos                (16U)
-#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000 */
-#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits */
+#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000
+#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits
 
 #if 0
 /********************  Bit definition for OTG register  ********************/
 #define CHNUM_Pos                        (0U)
-#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     // 0x0000000F */
-#define CHNUM                            CHNUM_Msk                                // Channel number */
-#define CHNUM_0                          (0x1UL << CHNUM_Pos)                     // 0x00000001 */
-#define CHNUM_1                          (0x2UL << CHNUM_Pos)                     // 0x00000002 */
-#define CHNUM_2                          (0x4UL << CHNUM_Pos)                     // 0x00000004 */
-#define CHNUM_3                          (0x8UL << CHNUM_Pos)                     // 0x00000008 */
+#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     // 0x0000000F
+#define CHNUM                            CHNUM_Msk                                // Channel number
+#define CHNUM_0                          (0x1UL << CHNUM_Pos)                     // 0x00000001
+#define CHNUM_1                          (0x2UL << CHNUM_Pos)                     // 0x00000002
+#define CHNUM_2                          (0x4UL << CHNUM_Pos)                     // 0x00000004
+#define CHNUM_3                          (0x8UL << CHNUM_Pos)                     // 0x00000008
 #define BCNT_Pos                         (4U)
-#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)                    // 0x00007FF0 */
-#define BCNT                             BCNT_Msk                                 // Byte count */
+#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)                    // 0x00007FF0
+#define BCNT                             BCNT_Msk                                 // Byte count
 
 #define DPID_Pos                         (15U)
-#define DPID_Msk                         (0x3UL << DPID_Pos)                      // 0x00018000 */
-#define DPID                             DPID_Msk                                 // Data PID */
-#define DPID_0                           (0x1UL << DPID_Pos)                      // 0x00008000 */
-#define DPID_1                           (0x2UL << DPID_Pos)                      // 0x00010000 */
+#define DPID_Msk                         (0x3UL << DPID_Pos)                      // 0x00018000
+#define DPID                             DPID_Msk                                 // Data PID
+#define DPID_0                           (0x1UL << DPID_Pos)                      // 0x00008000
+#define DPID_1                           (0x2UL << DPID_Pos)                      // 0x00010000
 
 #define PKTSTS_Pos                       (17U)
-#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)                    // 0x001E0000 */
-#define PKTSTS                           PKTSTS_Msk                               // Packet status */
-#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)                    // 0x00020000 */
-#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)                    // 0x00040000 */
-#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)                    // 0x00080000 */
-#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)                    // 0x00100000 */
+#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)                    // 0x001E0000
+#define PKTSTS                           PKTSTS_Msk                               // Packet status
+#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)                    // 0x00020000
+#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)                    // 0x00040000
+#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)                    // 0x00080000
+#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)                    // 0x00100000
 
 #define EPNUM_Pos                        (0U)
-#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)                     // 0x0000000F */
-#define EPNUM                            EPNUM_Msk                                // Endpoint number */
-#define EPNUM_0                          (0x1UL << EPNUM_Pos)                     // 0x00000001 */
-#define EPNUM_1                          (0x2UL << EPNUM_Pos)                     // 0x00000002 */
-#define EPNUM_2                          (0x4UL << EPNUM_Pos)                     // 0x00000004 */
-#define EPNUM_3                          (0x8UL << EPNUM_Pos)                     // 0x00000008 */
+#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)                     // 0x0000000F
+#define EPNUM                            EPNUM_Msk                                // Endpoint number
+#define EPNUM_0                          (0x1UL << EPNUM_Pos)                     // 0x00000001
+#define EPNUM_1                          (0x2UL << EPNUM_Pos)                     // 0x00000002
+#define EPNUM_2                          (0x4UL << EPNUM_Pos)                     // 0x00000004
+#define EPNUM_3                          (0x8UL << EPNUM_Pos)                     // 0x00000008
 
 #define FRMNUM_Pos                       (21U)
-#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)                    // 0x01E00000 */
-#define FRMNUM                           FRMNUM_Msk                               // Frame number */
-#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)                    // 0x00200000 */
-#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    // 0x00400000 */
-#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    // 0x00800000 */
-#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    // 0x01000000 */
+#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)                    // 0x01E00000
+#define FRMNUM                           FRMNUM_Msk                               // Frame number
+#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)                    // 0x00200000
+#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    // 0x00400000
+#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    // 0x00800000
+#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    // 0x01000000
 #endif
 
 /********************  Bit definition for GRXFSIZ register  ********************/
 #define GRXFSIZ_RXFD_Pos                 (0U)
-#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos)           // 0x0000FFFF */
-#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk                         // RxFIFO depth */
+#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos)           // 0x0000FFFF
+#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk                         // RxFIFO depth
 
 /********************  Bit definition for DVBUSDIS register  ********************/
 #define DVBUSDIS_VBUSDT_Pos              (0U)
-#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos)        // 0x0000FFFF */
-#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      // Device VBUS discharge time */
+#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos)        // 0x0000FFFF
+#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      // Device VBUS discharge time
 
 /********************  Bit definition for OTG register  ********************/
 #define GNPTXFSIZ_NPTXFSA_Pos            (0U)
-#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos)                // 0x0000FFFF */
-#define GNPTXFSIZ_NPTXFSA                GNPTXFSIZ_NPTXFSA_Msk                    // Nonperiodic transmit RAM start address */
+#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos)                // 0x0000FFFF
+#define GNPTXFSIZ_NPTXFSA                GNPTXFSIZ_NPTXFSA_Msk                    // Nonperiodic transmit RAM start address
 #define GNPTXFSIZ_NPTXFD_Pos             (16U)
-#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos)                 // 0xFFFF0000 */
-#define GNPTXFSIZ_NPTXFD                 GNPTXFSIZ_NPTXFD_Msk                     // Nonperiodic TxFIFO depth               */
+#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos)                 // 0xFFFF0000
+#define GNPTXFSIZ_NPTXFD                 GNPTXFSIZ_NPTXFD_Msk                     // Nonperiodic TxFIFO depth
 #define DIEPTXF0_TX0FSA_Pos              (0U)
-#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << DIEPTXF0_TX0FSA_Pos)                 // 0x0000FFFF */
-#define DIEPTXF0_TX0FSA                  DIEPTXF0_TX0FSA_Msk                      // Endpoint 0 transmit RAM start address  */
+#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << DIEPTXF0_TX0FSA_Pos)                 // 0x0000FFFF
+#define DIEPTXF0_TX0FSA                  DIEPTXF0_TX0FSA_Msk                      // Endpoint 0 transmit RAM start address
 #define DIEPTXF0_TX0FD_Pos               (16U)
-#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << DIEPTXF0_TX0FD_Pos)                  // 0xFFFF0000 */
-#define DIEPTXF0_TX0FD                   DIEPTXF0_TX0FD_Msk                       // Endpoint 0 TxFIFO depth                */
+#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << DIEPTXF0_TX0FD_Pos)                  // 0xFFFF0000
+#define DIEPTXF0_TX0FD                   DIEPTXF0_TX0FD_Msk                       // Endpoint 0 TxFIFO depth
 
 /********************  Bit definition for DVBUSPULSE register  ********************/
 #define DVBUSPULSE_DVBUSP_Pos            (0U)
-#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos)       // 0x00000FFF */
-#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk                    // Device VBUS pulsing time */
+#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos)       // 0x00000FFF
+#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk                    // Device VBUS pulsing time
 
 /********************  Bit definition for GNPTXSTS register  ********************/
 #define GNPTXSTS_NPTXFSAV_Pos            (0U)
-#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos)      // 0x0000FFFF */
-#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk                    // Nonperiodic TxFIFO space available */
+#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos)      // 0x0000FFFF
+#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk                    // Nonperiodic TxFIFO space available
 
 #define GNPTXSTS_NPTQXSAV_Pos            (16U)
-#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00FF0000 */
-#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk                    // Nonperiodic transmit request queue space available */
-#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00010000 */
-#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00020000 */
-#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00040000 */
-#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00080000 */
-#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00100000 */
-#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00200000 */
-#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00400000 */
-#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00800000 */
+#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00FF0000
+#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk                    // Nonperiodic transmit request queue space available
+#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00010000
+#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00020000
+#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00040000
+#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00080000
+#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00100000
+#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00200000
+#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00400000
+#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00800000
 
 #define GNPTXSTS_NPTXQTOP_Pos            (24U)
-#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos)        // 0x7F000000 */
-#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk                    // Top of the nonperiodic transmit request queue */
-#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x01000000 */
-#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x02000000 */
-#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x04000000 */
-#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x08000000 */
-#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x10000000 */
-#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x20000000 */
-#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x40000000 */
+#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos)        // 0x7F000000
+#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk                    // Top of the nonperiodic transmit request queue
+#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x01000000
+#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x02000000
+#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x04000000
+#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x08000000
+#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x10000000
+#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x20000000
+#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x40000000
 
 /********************  Bit definition for DTHRCTL register  ********************/
 #define DTHRCTL_NONISOTHREN_Pos          (0U)
-#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos)       // 0x00000001 */
-#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk                  // Nonisochronous IN endpoints threshold enable */
+#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos)       // 0x00000001
+#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk                  // Nonisochronous IN endpoints threshold enable
 #define DTHRCTL_ISOTHREN_Pos             (1U)
-#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos)          // 0x00000002 */
-#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk                     // ISO IN endpoint threshold enable */
+#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos)          // 0x00000002
+#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk                     // ISO IN endpoint threshold enable
 
 #define DTHRCTL_TXTHRLEN_Pos             (2U)
-#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos)        // 0x000007FC */
-#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk                     // Transmit threshold length */
-#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000004 */
-#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000008 */
-#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000010 */
-#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000020 */
-#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000040 */
-#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000080 */
-#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000100 */
-#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000200 */
-#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000400 */
+#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos)        // 0x000007FC
+#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk                     // Transmit threshold length
+#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000004
+#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000008
+#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000010
+#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000020
+#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000040
+#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000080
+#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000100
+#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000200
+#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000400
 #define DTHRCTL_RXTHREN_Pos              (16U)
-#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos)           // 0x00010000 */
-#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk                      // Receive threshold enable */
+#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos)           // 0x00010000
+#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk                      // Receive threshold enable
 
 #define DTHRCTL_RXTHRLEN_Pos             (17U)
-#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos)        // 0x03FE0000 */
-#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk                     // Receive threshold length */
-#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00020000 */
-#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00040000 */
-#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00080000 */
-#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00100000 */
-#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00200000 */
-#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00400000 */
-#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00800000 */
-#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos)        // 0x01000000 */
-#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos)        // 0x02000000 */
+#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos)        // 0x03FE0000
+#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk                     // Receive threshold length
+#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00020000
+#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00040000
+#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00080000
+#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00100000
+#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00200000
+#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00400000
+#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00800000
+#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos)        // 0x01000000
+#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos)        // 0x02000000
 #define DTHRCTL_ARPEN_Pos                (27U)
-#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos)             // 0x08000000 */
-#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk                        // Arbiter parking enable */
+#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos)             // 0x08000000
+#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk                        // Arbiter parking enable
 
 /********************  Bit definition for DIEPEMPMSK register  ********************/
 #define DIEPEMPMSK_INEPTXFEM_Pos         (0U)
-#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos)   // 0x0000FFFF */
-#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk                 // IN EP Tx FIFO empty interrupt mask bits */
+#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos)   // 0x0000FFFF
+#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk                 // IN EP Tx FIFO empty interrupt mask bits
 
 /********************  Bit definition for DEACHINT register  ********************/
 #define DEACHINT_IEP1INT_Pos             (1U)
-#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos)          // 0x00000002 */
-#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk                     // IN endpoint 1interrupt bit   */
+#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos)          // 0x00000002
+#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk                     // IN endpoint 1interrupt bit
 #define DEACHINT_OEP1INT_Pos             (17U)
-#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos)          // 0x00020000 */
-#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     // OUT endpoint 1 interrupt bit */
+#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos)          // 0x00020000
+#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     // OUT endpoint 1 interrupt bit
 
 /********************  Bit definition for GCCFG register  ********************/
 #define STM32_GCCFG_DCDET_Pos            (0U)
-#define STM32_GCCFG_DCDET_Msk            (0x1UL << STM32_GCCFG_DCDET_Pos)         // 0x00000001 */
-#define STM32_GCCFG_DCDET                STM32_GCCFG_DCDET_Msk                    // Data contact detection (DCD) status */
+#define STM32_GCCFG_DCDET_Msk            (0x1UL << STM32_GCCFG_DCDET_Pos)         // 0x00000001
+#define STM32_GCCFG_DCDET                STM32_GCCFG_DCDET_Msk                    // Data contact detection (DCD) status
+
 #define STM32_GCCFG_PDET_Pos             (1U)
-#define STM32_GCCFG_PDET_Msk             (0x1UL << STM32_GCCFG_PDET_Pos)          // 0x00000002 */
-#define STM32_GCCFG_PDET                 STM32_GCCFG_PDET_Msk                     // Primary detection (PD) status */
+#define STM32_GCCFG_PDET_Msk             (0x1UL << STM32_GCCFG_PDET_Pos)          // 0x00000002
+#define STM32_GCCFG_PDET                 STM32_GCCFG_PDET_Msk                     // Primary detection (PD) status
+
 #define STM32_GCCFG_SDET_Pos             (2U)
-#define STM32_GCCFG_SDET_Msk             (0x1UL << STM32_GCCFG_SDET_Pos)          // 0x00000004 */
-#define STM32_GCCFG_SDET                 STM32_GCCFG_SDET_Msk                     // Secondary detection (SD) status */
+#define STM32_GCCFG_SDET_Msk             (0x1UL << STM32_GCCFG_SDET_Pos)          // 0x00000004
+#define STM32_GCCFG_SDET                 STM32_GCCFG_SDET_Msk                     // Secondary detection (SD) status
+
 #define STM32_GCCFG_PS2DET_Pos           (3U)
-#define STM32_GCCFG_PS2DET_Msk           (0x1UL << STM32_GCCFG_PS2DET_Pos)        // 0x00000008 */
-#define STM32_GCCFG_PS2DET               STM32_GCCFG_PS2DET_Msk                   // DM pull-up detection status */
+#define STM32_GCCFG_PS2DET_Msk           (0x1UL << STM32_GCCFG_PS2DET_Pos)        // 0x00000008
+#define STM32_GCCFG_PS2DET               STM32_GCCFG_PS2DET_Msk                   // DM pull-up detection status
+
 #define STM32_GCCFG_PWRDWN_Pos           (16U)
-#define STM32_GCCFG_PWRDWN_Msk           (0x1UL << STM32_GCCFG_PWRDWN_Pos)        // 0x00010000 */
-#define STM32_GCCFG_PWRDWN               STM32_GCCFG_PWRDWN_Msk                   // Power down */
+#define STM32_GCCFG_PWRDWN_Msk           (0x1UL << STM32_GCCFG_PWRDWN_Pos)        // 0x00010000
+#define STM32_GCCFG_PWRDWN               STM32_GCCFG_PWRDWN_Msk                   // Power down
+
 #define STM32_GCCFG_BCDEN_Pos            (17U)
-#define STM32_GCCFG_BCDEN_Msk            (0x1UL << STM32_GCCFG_BCDEN_Pos)         // 0x00020000 */
-#define STM32_GCCFG_BCDEN                STM32_GCCFG_BCDEN_Msk                    // Battery charging detector (BCD) enable */
+#define STM32_GCCFG_BCDEN_Msk            (0x1UL << STM32_GCCFG_BCDEN_Pos)         // 0x00020000
+#define STM32_GCCFG_BCDEN                STM32_GCCFG_BCDEN_Msk                    // Battery charging detector (BCD) enable
+
 #define STM32_GCCFG_DCDEN_Pos            (18U)
-#define STM32_GCCFG_DCDEN_Msk            (0x1UL << STM32_GCCFG_DCDEN_Pos)         // 0x00040000 */
+#define STM32_GCCFG_DCDEN_Msk            (0x1UL << STM32_GCCFG_DCDEN_Pos)         // 0x00040000
 #define STM32_GCCFG_DCDEN                STM32_GCCFG_DCDEN_Msk                    // Data contact detection (DCD) mode enable*/
+
 #define STM32_GCCFG_PDEN_Pos             (19U)
-#define STM32_GCCFG_PDEN_Msk             (0x1UL << STM32_GCCFG_PDEN_Pos)          // 0x00080000 */
+#define STM32_GCCFG_PDEN_Msk             (0x1UL << STM32_GCCFG_PDEN_Pos)          // 0x00080000
 #define STM32_GCCFG_PDEN                 STM32_GCCFG_PDEN_Msk                     // Primary detection (PD) mode enable*/
+
 #define STM32_GCCFG_SDEN_Pos             (20U)
-#define STM32_GCCFG_SDEN_Msk             (0x1UL << STM32_GCCFG_SDEN_Pos)          // 0x00100000 */
-#define STM32_GCCFG_SDEN                 STM32_GCCFG_SDEN_Msk                     // Secondary detection (SD) mode enable */
+#define STM32_GCCFG_SDEN_Msk             (0x1UL << STM32_GCCFG_SDEN_Pos)          // 0x00100000
+#define STM32_GCCFG_SDEN                 STM32_GCCFG_SDEN_Msk                     // Secondary detection (SD) mode enable
+
 #define STM32_GCCFG_VBDEN_Pos            (21U)
-#define STM32_GCCFG_VBDEN_Msk            (0x1UL << STM32_GCCFG_VBDEN_Pos)         // 0x00200000 */
-#define STM32_GCCFG_VBDEN                STM32_GCCFG_VBDEN_Msk                    // VBUS mode enable */
+#define STM32_GCCFG_VBDEN_Msk            (0x1UL << STM32_GCCFG_VBDEN_Pos)         // 0x00200000
+#define STM32_GCCFG_VBDEN                STM32_GCCFG_VBDEN_Msk                    // VBUS mode enable
+
 #define STM32_GCCFG_OTGIDEN_Pos          (22U)
-#define STM32_GCCFG_OTGIDEN_Msk          (0x1UL << STM32_GCCFG_OTGIDEN_Pos)       // 0x00400000 */
-#define STM32_GCCFG_OTGIDEN              STM32_GCCFG_OTGIDEN_Msk                  // OTG Id enable */
+#define STM32_GCCFG_OTGIDEN_Msk          (0x1UL << STM32_GCCFG_OTGIDEN_Pos)       // 0x00400000
+#define STM32_GCCFG_OTGIDEN              STM32_GCCFG_OTGIDEN_Msk                  // OTG Id enable
+
 #define STM32_GCCFG_PHYHSEN_Pos          (23U)
-#define STM32_GCCFG_PHYHSEN_Msk          (0x1UL << STM32_GCCFG_PHYHSEN_Pos)       // 0x00800000 */
-#define STM32_GCCFG_PHYHSEN              STM32_GCCFG_PHYHSEN_Msk                  // HS PHY enable */
+#define STM32_GCCFG_PHYHSEN_Msk          (0x1UL << STM32_GCCFG_PHYHSEN_Pos)       // 0x00800000
+#define STM32_GCCFG_PHYHSEN              STM32_GCCFG_PHYHSEN_Msk                  // HS PHY enable
+
+// TODO stm32u5a5 SDEN is 22nd bit, conflict with 20th bit above
+//#define STM32_GCCFG_SDEN_Pos                   (22U)
+//#define STM32_GCCFG_SDEN_Msk                   (0x1U << STM32_GCCFG_SDEN_Pos)             // 0x00400000
+//#define STM32_GCCFG_SDEN                       STM32_GCCFG_SDEN_Msk                       // Secondary detection (PD) mode enable
+
+// TODO stm32u5a5 VBVALOVA is 23rd bit, conflict with PHYHSEN bit above
+#define STM32_GCCFG_VBVALOVAL_Pos              (23U)
+#define STM32_GCCFG_VBVALOVAL_Msk              (0x1U << STM32_GCCFG_VBVALOVAL_Pos)        // 0x00800000
+#define STM32_GCCFG_VBVALOVAL                  STM32_GCCFG_VBVALOVAL_Msk                  // Value of VBUSVLDEXT0 femtoPHY input
+
+#define STM32_GCCFG_VBVALEXTOEN_Pos            (24U)
+#define STM32_GCCFG_VBVALEXTOEN_Msk            (0x1U << STM32_GCCFG_VBVALEXTOEN_Pos)      // 0x01000000
+#define STM32_GCCFG_VBVALEXTOEN                STM32_GCCFG_VBVALEXTOEN_Msk                // Enables of VBUSVLDEXT0 femtoPHY input override
+
+#define STM32_GCCFG_PULLDOWNEN_Pos             (25U)
+#define STM32_GCCFG_PULLDOWNEN_Msk             (0x1U << STM32_GCCFG_PULLDOWNEN_Pos)       // 0x02000000
+#define STM32_GCCFG_PULLDOWNEN                 STM32_GCCFG_PULLDOWNEN_Msk                 // Enables of femtoPHY pulldown resistors, used when ID PAD is disabled
+
 
 /********************  Bit definition for DEACHINTMSK register  ********************/
 #define DEACHINTMSK_IEP1INTM_Pos         (1U)
-#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos)      // 0x00000002 */
-#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk                 // IN Endpoint 1 interrupt mask bit  */
+#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos)      // 0x00000002
+#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk                 // IN Endpoint 1 interrupt mask bit
 #define DEACHINTMSK_OEP1INTM_Pos         (17U)
-#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos)      // 0x00020000 */
-#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk                 // OUT Endpoint 1 interrupt mask bit */
+#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos)      // 0x00020000
+#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk                 // OUT Endpoint 1 interrupt mask bit
 
 /********************  Bit definition for CID register  ********************/
 #define CID_PRODUCT_ID_Pos               (0U)
-#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos)     // 0xFFFFFFFF */
-#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk                       // Product ID field */
+#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos)     // 0xFFFFFFFF
+#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk                       // Product ID field
 
 /********************  Bit definition for GLPMCFG register  ********************/
 #define GLPMCFG_LPMEN_Pos                (0U)
-#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos)             // 0x00000001 */
-#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk                        // LPM support enable                                     */
+#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos)             // 0x00000001
+#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk                        // LPM support enable
 #define GLPMCFG_LPMACK_Pos               (1U)
-#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos)            // 0x00000002 */
-#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk                       // LPM Token acknowledge enable                           */
+#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos)            // 0x00000002
+#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk                       // LPM Token acknowledge enable
 #define GLPMCFG_BESL_Pos                 (2U)
-#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos)              // 0x0000003C */
-#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk                         // BESL value received with last ACKed LPM Token          */
+#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos)              // 0x0000003C
+#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk                         // BESL value received with last ACKed LPM Token
 #define GLPMCFG_REMWAKE_Pos              (6U)
-#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos)           // 0x00000040 */
-#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk                      // bRemoteWake value received with last ACKed LPM Token   */
+#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos)           // 0x00000040
+#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk                      // bRemoteWake value received with last ACKed LPM Token
 #define GLPMCFG_L1SSEN_Pos               (7U)
-#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos)            // 0x00000080 */
-#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk                       // L1 shallow sleep enable                                */
+#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos)            // 0x00000080
+#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk                       // L1 shallow sleep enable
 #define GLPMCFG_BESLTHRS_Pos             (8U)
-#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos)          // 0x00000F00 */
-#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk                     // BESL threshold                                         */
+#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos)          // 0x00000F00
+#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk                     // BESL threshold
 #define GLPMCFG_L1DSEN_Pos               (12U)
-#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos)            // 0x00001000 */
-#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk                       // L1 deep sleep enable                                   */
+#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos)            // 0x00001000
+#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk                       // L1 deep sleep enable
 #define GLPMCFG_LPMRSP_Pos               (13U)
-#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos)            // 0x00006000 */
-#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk                       // LPM response                                           */
+#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos)            // 0x00006000
+#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk                       // LPM response
 #define GLPMCFG_SLPSTS_Pos               (15U)
-#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos)            // 0x00008000 */
-#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk                       // Port sleep status                                      */
+#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos)            // 0x00008000
+#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk                       // Port sleep status
 #define GLPMCFG_L1RSMOK_Pos              (16U)
-#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos)           // 0x00010000 */
-#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk                      // Sleep State Resume OK                                  */
+#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos)           // 0x00010000
+#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk                      // Sleep State Resume OK
 #define GLPMCFG_LPMCHIDX_Pos             (17U)
-#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos)          // 0x001E0000 */
-#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk                     // LPM Channel Index                                      */
+#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos)          // 0x001E0000
+#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk                     // LPM Channel Index
 #define GLPMCFG_LPMRCNT_Pos              (21U)
-#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos)           // 0x00E00000 */
-#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk                      // LPM retry count                                        */
+#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos)           // 0x00E00000
+#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk                      // LPM retry count
 #define GLPMCFG_SNDLPM_Pos               (24U)
-#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos)            // 0x01000000 */
-#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk                       // Send LPM transaction                                   */
+#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos)            // 0x01000000
+#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk                       // Send LPM transaction
 #define GLPMCFG_LPMRCNTSTS_Pos           (25U)
-#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos)        // 0x0E000000 */
-#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk                   // LPM retry count status                                 */
+#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos)        // 0x0E000000
+#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk                   // LPM retry count status
 #define GLPMCFG_ENBESL_Pos               (28U)
-#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos)            // 0x10000000 */
-#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk                       // Enable best effort service latency                     */
+#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos)            // 0x10000000
+#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk                       // Enable best effort service latency
 
 /********************  Bit definition for DIEPEACHMSK1 register  ********************/
 #define DIEPEACHMSK1_XFRCM_Pos           (0U)
-#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos)        // 0x00000001 */
-#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask                 */
+#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos)        // 0x00000001
+#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask
 #define DIEPEACHMSK1_EPDM_Pos            (1U)
-#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos)         // 0x00000002 */
-#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask                  */
+#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos)         // 0x00000002
+#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask
 #define DIEPEACHMSK1_TOM_Pos             (3U)
-#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos)          // 0x00000008 */
-#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk                     // Timeout condition mask (nonisochronous endpoints) */
+#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos)          // 0x00000008
+#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk                     // Timeout condition mask (nonisochronous endpoints)
 #define DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010 */
-#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask          */
+#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010
+#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask
 #define DIEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos)      // 0x00000020 */
-#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask           */
+#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos)      // 0x00000020
+#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask
 #define DIEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos)      // 0x00000040 */
-#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask                    */
+#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos)      // 0x00000040
+#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask
 #define DIEPEACHMSK1_TXFURM_Pos          (8U)
-#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos)       // 0x00000100 */
-#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk                  // FIFO underrun mask                                */
+#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos)       // 0x00000100
+#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk                  // FIFO underrun mask
 #define DIEPEACHMSK1_BIM_Pos             (9U)
-#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos)          // 0x00000200 */
-#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk                     // BNA interrupt mask                                */
+#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos)          // 0x00000200
+#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk                     // BNA interrupt mask
 #define DIEPEACHMSK1_NAKM_Pos            (13U)
-#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos)         // 0x00002000 */
-#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask                                */
+#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos)         // 0x00002000
+#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask
 
 /********************  Bit definition for HPRT register  ********************/
 #define HPRT_PCSTS_Pos                   (0U)
-#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos)                // 0x00000001 */
-#define HPRT_PCSTS                       HPRT_PCSTS_Msk                           // Port connect status        */
+#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos)                // 0x00000001
+#define HPRT_PCSTS                       HPRT_PCSTS_Msk                           // Port connect status
 #define HPRT_PCDET_Pos                   (1U)
-#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos)                // 0x00000002 */
-#define HPRT_PCDET                       HPRT_PCDET_Msk                           // Port connect detected      */
+#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos)                // 0x00000002
+#define HPRT_PCDET                       HPRT_PCDET_Msk                           // Port connect detected
 #define HPRT_PENA_Pos                    (2U)
-#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos)                 // 0x00000004 */
-#define HPRT_PENA                        HPRT_PENA_Msk                            // Port enable                */
+#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos)                 // 0x00000004
+#define HPRT_PENA                        HPRT_PENA_Msk                            // Port enable
 #define HPRT_PENCHNG_Pos                 (3U)
-#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos)              // 0x00000008 */
-#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk                         // Port enable/disable change */
+#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos)              // 0x00000008
+#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk                         // Port enable/disable change
 #define HPRT_POCA_Pos                    (4U)
-#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos)                 // 0x00000010 */
-#define HPRT_POCA                        HPRT_POCA_Msk                            // Port overcurrent active    */
+#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos)                 // 0x00000010
+#define HPRT_POCA                        HPRT_POCA_Msk                            // Port overcurrent active
 #define HPRT_POCCHNG_Pos                 (5U)
-#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos)              // 0x00000020 */
-#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk                         // Port overcurrent change    */
+#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos)              // 0x00000020
+#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk                         // Port overcurrent change
 #define HPRT_PRES_Pos                    (6U)
-#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos)                 // 0x00000040 */
-#define HPRT_PRES                        HPRT_PRES_Msk                            // Port resume                */
+#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos)                 // 0x00000040
+#define HPRT_PRES                        HPRT_PRES_Msk                            // Port resume
 #define HPRT_PSUSP_Pos                   (7U)
-#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos)                // 0x00000080 */
-#define HPRT_PSUSP                       HPRT_PSUSP_Msk                           // Port suspend               */
+#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos)                // 0x00000080
+#define HPRT_PSUSP                       HPRT_PSUSP_Msk                           // Port suspend
 #define HPRT_PRST_Pos                    (8U)
-#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos)                 // 0x00000100 */
-#define HPRT_PRST                        HPRT_PRST_Msk                            // Port reset                 */
+#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos)                 // 0x00000100
+#define HPRT_PRST                        HPRT_PRST_Msk                            // Port reset
 
 #define HPRT_PLSTS_Pos                   (10U)
-#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos)                // 0x00000C00 */
-#define HPRT_PLSTS                       HPRT_PLSTS_Msk                           // Port line status           */
-#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos)                // 0x00000400 */
-#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos)                // 0x00000800 */
+#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos)                // 0x00000C00
+#define HPRT_PLSTS                       HPRT_PLSTS_Msk                           // Port line status
+#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos)                // 0x00000400
+#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos)                // 0x00000800
 #define HPRT_PPWR_Pos                    (12U)
-#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos)                 // 0x00001000 */
-#define HPRT_PPWR                        HPRT_PPWR_Msk                            // Port power                 */
+#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos)                 // 0x00001000
+#define HPRT_PPWR                        HPRT_PPWR_Msk                            // Port power
 
 #define HPRT_PTCTL_Pos                   (13U)
-#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos)                // 0x0001E000 */
-#define HPRT_PTCTL                       HPRT_PTCTL_Msk                           // Port test control          */
-#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos)                // 0x00002000 */
-#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos)                // 0x00004000 */
-#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos)                // 0x00008000 */
-#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos)                // 0x00010000 */
+#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos)                // 0x0001E000
+#define HPRT_PTCTL                       HPRT_PTCTL_Msk                           // Port test control
+#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos)                // 0x00002000
+#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos)                // 0x00004000
+#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos)                // 0x00008000
+#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos)                // 0x00010000
 
 #define HPRT_PSPD_Pos                    (17U)
-#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos)                 // 0x00060000 */
-#define HPRT_PSPD                        HPRT_PSPD_Msk                            // Port speed                 */
-#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos)                 // 0x00020000 */
-#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos)                 // 0x00040000 */
+#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos)                 // 0x00060000
+#define HPRT_PSPD                        HPRT_PSPD_Msk                            // Port speed
+#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos)                 // 0x00020000
+#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos)                 // 0x00040000
 
 /********************  Bit definition for DOEPEACHMSK1 register  ********************/
 #define DOEPEACHMSK1_XFRCM_Pos           (0U)
-#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos)        // 0x00000001 */
-#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask         */
+#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos)        // 0x00000001
+#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask
 #define DOEPEACHMSK1_EPDM_Pos            (1U)
-#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos)         // 0x00000002 */
-#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask          */
+#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos)         // 0x00000002
+#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask
 #define DOEPEACHMSK1_TOM_Pos             (3U)
-#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos)          // 0x00000008 */
-#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk                     // Timeout condition mask                    */
+#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos)          // 0x00000008
+#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk                     // Timeout condition mask
 #define DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010 */
-#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask  */
+#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010
+#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask
 #define DOEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos)      // 0x00000020 */
-#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask   */
+#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos)      // 0x00000020
+#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask
 #define DOEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos)      // 0x00000040 */
-#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask            */
+#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos)      // 0x00000040
+#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask
 #define DOEPEACHMSK1_TXFURM_Pos          (8U)
-#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos)       // 0x00000100 */
-#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk                  // OUT packet error mask                     */
+#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos)       // 0x00000100
+#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk                  // OUT packet error mask
 #define DOEPEACHMSK1_BIM_Pos             (9U)
-#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos)          // 0x00000200 */
-#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk                     // BNA interrupt mask                        */
+#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos)          // 0x00000200
+#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk                     // BNA interrupt mask
 #define DOEPEACHMSK1_BERRM_Pos           (12U)
-#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos)        // 0x00001000 */
-#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk                   // Bubble error interrupt mask               */
+#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos)        // 0x00001000
+#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk                   // Bubble error interrupt mask
 #define DOEPEACHMSK1_NAKM_Pos            (13U)
-#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos)         // 0x00002000 */
-#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask                        */
+#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos)         // 0x00002000
+#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask
 #define DOEPEACHMSK1_NYETM_Pos           (14U)
-#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos)        // 0x00004000 */
-#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk                   // NYET interrupt mask                       */
+#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos)        // 0x00004000
+#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk                   // NYET interrupt mask
 
 /********************  Bit definition for HPTXFSIZ register  ********************/
 #define HPTXFSIZ_PTXSA_Pos               (0U)
-#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos)         // 0x0000FFFF */
-#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk                       // Host periodic TxFIFO start address            */
+#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos)         // 0x0000FFFF
+#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk                       // Host periodic TxFIFO start address
 #define HPTXFSIZ_PTXFD_Pos               (16U)
-#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos)         // 0xFFFF0000 */
-#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       // Host periodic TxFIFO depth                    */
+#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos)         // 0xFFFF0000
+#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       // Host periodic TxFIFO depth
 
 /********************  Bit definition for DIEPCTL register  ********************/
 #define DIEPCTL_MPSIZ_Pos                (0U)
-#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           // 0x000007FF */
-#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        // Maximum packet size              */
+#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           // 0x000007FF
+#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        // Maximum packet size
 #define DIEPCTL_USBAEP_Pos               (15U)
-#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos)            // 0x00008000 */
-#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk                       // USB active endpoint              */
+#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos)            // 0x00008000
+#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk                       // USB active endpoint
 #define DIEPCTL_EONUM_DPID_Pos           (16U)
-#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos)        // 0x00010000 */
-#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk                   // Even/odd frame                   */
+#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos)        // 0x00010000
+#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk                   // Even/odd frame
 #define DIEPCTL_NAKSTS_Pos               (17U)
-#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos)            // 0x00020000 */
-#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk                       // NAK status                       */
+#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos)            // 0x00020000
+#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk                       // NAK status
 
 #define DIEPCTL_EPTYP_Pos                (18U)
-#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos)             // 0x000C0000 */
-#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk                        // Endpoint type                    */
-#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos)             // 0x00040000 */
-#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos)             // 0x00080000 */
+#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos)             // 0x000C0000
+#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk                        // Endpoint type
+#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos)             // 0x00040000
+#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos)             // 0x00080000
 #define DIEPCTL_STALL_Pos                (21U)
-#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos)             // 0x00200000 */
-#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk                        // STALL handshake                  */
+#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos)             // 0x00200000
+#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk                        // STALL handshake
 
 #define DIEPCTL_TXFNUM_Pos               (22U)
-#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos)            // 0x03C00000 */
-#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk                       // TxFIFO number                    */
-#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos)            // 0x00400000 */
-#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos)            // 0x00800000 */
-#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos)            // 0x01000000 */
-#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos)            // 0x02000000 */
+#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos)            // 0x03C00000
+#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk                       // TxFIFO number
+#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos)            // 0x00400000
+#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos)            // 0x00800000
+#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos)            // 0x01000000
+#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos)            // 0x02000000
 #define DIEPCTL_CNAK_Pos                 (26U)
-#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos)              // 0x04000000 */
-#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk                         // Clear NAK                        */
+#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos)              // 0x04000000
+#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk                         // Clear NAK
 #define DIEPCTL_SNAK_Pos                 (27U)
-#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos)              // 0x08000000 */
-#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk                         // Set NAK */
+#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos)              // 0x08000000
+#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk                         // Set NAK
 #define DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000 */
-#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID                    */
+#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000
+#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID
 #define DIEPCTL_SODDFRM_Pos              (29U)
-#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos)           // 0x20000000 */
-#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk                      // Set odd frame                    */
+#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos)           // 0x20000000
+#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk                      // Set odd frame
 #define DIEPCTL_EPDIS_Pos                (30U)
-#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos)             // 0x40000000 */
-#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk                        // Endpoint disable                 */
+#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos)             // 0x40000000
+#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk                        // Endpoint disable
 #define DIEPCTL_EPENA_Pos                (31U)
-#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos)             // 0x80000000 */
-#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk                        // Endpoint enable                  */
+#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos)             // 0x80000000
+#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk                        // Endpoint enable
 
 /********************  Bit definition for HCCHAR register  ********************/
 #define HCCHAR_MPSIZ_Pos                 (0U)
-#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos)            // 0x000007FF */
-#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk                         // Maximum packet size */
+#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos)            // 0x000007FF
+#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk                         // Maximum packet size
 
 #define HCCHAR_EPNUM_Pos                 (11U)
-#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos)              // 0x00007800 */
-#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk                         // Endpoint number */
-#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos)              // 0x00000800 */
-#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos)              // 0x00001000 */
-#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos)              // 0x00002000 */
-#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos)              // 0x00004000 */
+#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos)              // 0x00007800
+#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk                         // Endpoint number
+#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos)              // 0x00000800
+#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos)              // 0x00001000
+#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos)              // 0x00002000
+#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos)              // 0x00004000
 #define HCCHAR_EPDIR_Pos                 (15U)
-#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos)              // 0x00008000 */
-#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk                         // Endpoint direction */
+#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos)              // 0x00008000
+#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk                         // Endpoint direction
 #define HCCHAR_LSDEV_Pos                 (17U)
-#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos)              // 0x00020000 */
-#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk                         // Low-speed device */
+#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos)              // 0x00020000
+#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk                         // Low-speed device
 
 #define HCCHAR_EPTYP_Pos                 (18U)
-#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos)              // 0x000C0000 */
-#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk                         // Endpoint type */
-#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos)              // 0x00040000 */
-#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos)              // 0x00080000 */
+#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos)              // 0x000C0000
+#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk                         // Endpoint type
+#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos)              // 0x00040000
+#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos)              // 0x00080000
 
 #define HCCHAR_MC_Pos                    (20U)
-#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos)                 // 0x00300000 */
-#define HCCHAR_MC                        HCCHAR_MC_Msk                            // Multi Count (MC) / Error Count (EC) */
-#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos)                 // 0x00100000 */
-#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos)                 // 0x00200000 */
+#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos)                 // 0x00300000
+#define HCCHAR_MC                        HCCHAR_MC_Msk                            // Multi Count (MC) / Error Count (EC)
+#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos)                 // 0x00100000
+#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos)                 // 0x00200000
 
 #define HCCHAR_DAD_Pos                   (22U)
-#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos)               // 0x1FC00000 */
-#define HCCHAR_DAD                       HCCHAR_DAD_Msk                           // Device address */
-#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos)               // 0x00400000 */
-#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos)               // 0x00800000 */
-#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos)               // 0x01000000 */
-#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos)               // 0x02000000 */
-#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos)               // 0x04000000 */
-#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos)               // 0x08000000 */
-#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos)               // 0x10000000 */
+#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos)               // 0x1FC00000
+#define HCCHAR_DAD                       HCCHAR_DAD_Msk                           // Device address
+#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos)               // 0x00400000
+#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos)               // 0x00800000
+#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos)               // 0x01000000
+#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos)               // 0x02000000
+#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos)               // 0x04000000
+#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos)               // 0x08000000
+#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos)               // 0x10000000
 #define HCCHAR_ODDFRM_Pos                (29U)
-#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos)             // 0x20000000 */
-#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk                        // Odd frame */
+#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos)             // 0x20000000
+#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk                        // Odd frame
 #define HCCHAR_CHDIS_Pos                 (30U)
-#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos)              // 0x40000000 */
-#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk                         // Channel disable */
+#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos)              // 0x40000000
+#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk                         // Channel disable
 #define HCCHAR_CHENA_Pos                 (31U)
-#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos)              // 0x80000000 */
-#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk                         // Channel enable */
+#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos)              // 0x80000000
+#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk                         // Channel enable
 
 /********************  Bit definition for HCSPLT register  ********************/
 
 #define HCSPLT_PRTADDR_Pos               (0U)
-#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos)           // 0x0000007F */
-#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk                       // Port address */
-#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos)           // 0x00000001 */
-#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos)           // 0x00000002 */
-#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos)           // 0x00000004 */
-#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos)           // 0x00000008 */
-#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos)           // 0x00000010 */
-#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos)           // 0x00000020 */
-#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos)           // 0x00000040 */
+#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos)           // 0x0000007F
+#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk                       // Port address
+#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos)           // 0x00000001
+#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos)           // 0x00000002
+#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos)           // 0x00000004
+#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos)           // 0x00000008
+#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos)           // 0x00000010
+#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos)           // 0x00000020
+#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos)           // 0x00000040
 
 #define HCSPLT_HUBADDR_Pos               (7U)
-#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos)           // 0x00003F80 */
-#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk                       // Hub address */
-#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos)           // 0x00000080 */
-#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos)           // 0x00000100 */
-#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos)           // 0x00000200 */
-#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos)           // 0x00000400 */
-#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos)           // 0x00000800 */
-#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos)           // 0x00001000 */
-#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos)           // 0x00002000 */
+#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos)           // 0x00003F80
+#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk                       // Hub address
+#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos)           // 0x00000080
+#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos)           // 0x00000100
+#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos)           // 0x00000200
+#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos)           // 0x00000400
+#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos)           // 0x00000800
+#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos)           // 0x00001000
+#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos)           // 0x00002000
 
 #define HCSPLT_XACTPOS_Pos               (14U)
-#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos)            // 0x0000C000 */
-#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk                       // XACTPOS */
-#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos)            // 0x00004000 */
-#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos)            // 0x00008000 */
+#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos)            // 0x0000C000
+#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk                       // XACTPOS
+#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos)            // 0x00004000
+#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos)            // 0x00008000
 #define HCSPLT_COMPLSPLT_Pos             (16U)
-#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos)          // 0x00010000 */
-#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk                     // Do complete split */
+#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos)          // 0x00010000
+#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk                     // Do complete split
 #define HCSPLT_SPLITEN_Pos               (31U)
-#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos)            // 0x80000000 */
-#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk                       // Split enable */
+#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos)            // 0x80000000
+#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk                       // Split enable
 
 /********************  Bit definition for HCINT register  ********************/
 #define HCINT_XFRC_Pos                   (0U)
-#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos)                // 0x00000001 */
-#define HCINT_XFRC                       HCINT_XFRC_Msk                           // Transfer completed */
+#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos)                // 0x00000001
+#define HCINT_XFRC                       HCINT_XFRC_Msk                           // Transfer completed
 #define HCINT_CHH_Pos                    (1U)
-#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos)                 // 0x00000002 */
-#define HCINT_CHH                        HCINT_CHH_Msk                            // Channel halted */
+#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos)                 // 0x00000002
+#define HCINT_CHH                        HCINT_CHH_Msk                            // Channel halted
 #define HCINT_AHBERR_Pos                 (2U)
-#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos)              // 0x00000004 */
-#define HCINT_AHBERR                     HCINT_AHBERR_Msk                         // AHB error */
+#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos)              // 0x00000004
+#define HCINT_AHBERR                     HCINT_AHBERR_Msk                         // AHB error
 #define HCINT_STALL_Pos                  (3U)
-#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos)               // 0x00000008 */
-#define HCINT_STALL                      HCINT_STALL_Msk                          // STALL response received interrupt */
+#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos)               // 0x00000008
+#define HCINT_STALL                      HCINT_STALL_Msk                          // STALL response received interrupt
 #define HCINT_NAK_Pos                    (4U)
-#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos)                 // 0x00000010 */
-#define HCINT_NAK                        HCINT_NAK_Msk                            // NAK response received interrupt */
+#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos)                 // 0x00000010
+#define HCINT_NAK                        HCINT_NAK_Msk                            // NAK response received interrupt
 #define HCINT_ACK_Pos                    (5U)
-#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos)                 // 0x00000020 */
-#define HCINT_ACK                        HCINT_ACK_Msk                            // ACK response received/transmitted interrupt */
+#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos)                 // 0x00000020
+#define HCINT_ACK                        HCINT_ACK_Msk                            // ACK response received/transmitted interrupt
 #define HCINT_NYET_Pos                   (6U)
-#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos)                // 0x00000040 */
-#define HCINT_NYET                       HCINT_NYET_Msk                           // Response received interrupt */
+#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos)                // 0x00000040
+#define HCINT_NYET                       HCINT_NYET_Msk                           // Response received interrupt
 #define HCINT_TXERR_Pos                  (7U)
-#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos)               // 0x00000080 */
-#define HCINT_TXERR                      HCINT_TXERR_Msk                          // Transaction error */
+#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos)               // 0x00000080
+#define HCINT_TXERR                      HCINT_TXERR_Msk                          // Transaction error
 #define HCINT_BBERR_Pos                  (8U)
-#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos)               // 0x00000100 */
-#define HCINT_BBERR                      HCINT_BBERR_Msk                          // Babble error */
+#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos)               // 0x00000100
+#define HCINT_BBERR                      HCINT_BBERR_Msk                          // Babble error
 #define HCINT_FRMOR_Pos                  (9U)
-#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos)               // 0x00000200 */
-#define HCINT_FRMOR                      HCINT_FRMOR_Msk                          // Frame overrun */
+#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos)               // 0x00000200
+#define HCINT_FRMOR                      HCINT_FRMOR_Msk                          // Frame overrun
 #define HCINT_DTERR_Pos                  (10U)
-#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos)               // 0x00000400 */
-#define HCINT_DTERR                      HCINT_DTERR_Msk                          // Data toggle error */
+#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos)               // 0x00000400
+#define HCINT_DTERR                      HCINT_DTERR_Msk                          // Data toggle error
 
 /********************  Bit definition for DIEPINT register  ********************/
 #define DIEPINT_XFRC_Pos                 (0U)
-#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos)              // 0x00000001 */
-#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk                         // Transfer completed interrupt */
+#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos)              // 0x00000001
+#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk                         // Transfer completed interrupt
 #define DIEPINT_EPDISD_Pos               (1U)
-#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos)            // 0x00000002 */
-#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk                       // Endpoint disabled interrupt */
+#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos)            // 0x00000002
+#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk                       // Endpoint disabled interrupt
 #define DIEPINT_AHBERR_Pos               (2U)
-#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos)            // 0x00000004 */
-#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an IN transaction */
+#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos)            // 0x00000004
+#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an IN transaction
 #define DIEPINT_TOC_Pos                  (3U)
-#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos)               // 0x00000008 */
-#define DIEPINT_TOC                      DIEPINT_TOC_Msk                          // Timeout condition */
+#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos)               // 0x00000008
+#define DIEPINT_TOC                      DIEPINT_TOC_Msk                          // Timeout condition
 #define DIEPINT_ITTXFE_Pos               (4U)
-#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos)            // 0x00000010 */
-#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk                       // IN token received when TxFIFO is empty */
+#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos)            // 0x00000010
+#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk                       // IN token received when TxFIFO is empty
 #define DIEPINT_INEPNM_Pos               (5U)
-#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos)            // 0x00000020 */
-#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk                       // IN token received with EP mismatch */
+#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos)            // 0x00000020
+#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk                       // IN token received with EP mismatch
 #define DIEPINT_INEPNE_Pos               (6U)
-#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos)            // 0x00000040 */
-#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk                       // IN endpoint NAK effective */
+#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos)            // 0x00000040
+#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk                       // IN endpoint NAK effective
 #define DIEPINT_TXFE_Pos                 (7U)
-#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos)              // 0x00000080 */
-#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk                         // Transmit FIFO empty */
+#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos)              // 0x00000080
+#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk                         // Transmit FIFO empty
 #define DIEPINT_TXFIFOUDRN_Pos           (8U)
-#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos)        // 0x00000100 */
-#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk                   // Transmit Fifo Underrun */
+#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos)        // 0x00000100
+#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk                   // Transmit Fifo Underrun
 #define DIEPINT_BNA_Pos                  (9U)
-#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos)               // 0x00000200 */
-#define DIEPINT_BNA                      DIEPINT_BNA_Msk                          // Buffer not available interrupt */
+#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos)               // 0x00000200
+#define DIEPINT_BNA                      DIEPINT_BNA_Msk                          // Buffer not available interrupt
 #define DIEPINT_PKTDRPSTS_Pos            (11U)
-#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos)         // 0x00000800 */
-#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk                    // Packet dropped status */
+#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos)         // 0x00000800
+#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk                    // Packet dropped status
 #define DIEPINT_BERR_Pos                 (12U)
-#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos)              // 0x00001000 */
-#define DIEPINT_BERR                     DIEPINT_BERR_Msk                         // Babble error interrupt */
+#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos)              // 0x00001000
+#define DIEPINT_BERR                     DIEPINT_BERR_Msk                         // Babble error interrupt
 #define DIEPINT_NAK_Pos                  (13U)
-#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos)               // 0x00002000 */
-#define DIEPINT_NAK                      DIEPINT_NAK_Msk                          // NAK interrupt */
+#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos)               // 0x00002000
+#define DIEPINT_NAK                      DIEPINT_NAK_Msk                          // NAK interrupt
 
 /********************  Bit definition for HCINTMSK register  ********************/
 #define HCINTMSK_XFRCM_Pos               (0U)
-#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos)            // 0x00000001 */
-#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk                       // Transfer completed mask */
+#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos)            // 0x00000001
+#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk                       // Transfer completed mask
 #define HCINTMSK_CHHM_Pos                (1U)
-#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos)             // 0x00000002 */
-#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk                        // Channel halted mask */
+#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos)             // 0x00000002
+#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk                        // Channel halted mask
 #define HCINTMSK_AHBERR_Pos              (2U)
-#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos)           // 0x00000004 */
-#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk                      // AHB error */
+#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos)           // 0x00000004
+#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk                      // AHB error
 #define HCINTMSK_STALLM_Pos              (3U)
-#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos)           // 0x00000008 */
-#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk                      // STALL response received interrupt mask */
+#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos)           // 0x00000008
+#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk                      // STALL response received interrupt mask
 #define HCINTMSK_NAKM_Pos                (4U)
-#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos)             // 0x00000010 */
-#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk                        // NAK response received interrupt mask */
+#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos)             // 0x00000010
+#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk                        // NAK response received interrupt mask
 #define HCINTMSK_ACKM_Pos                (5U)
-#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos)             // 0x00000020 */
-#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk                        // ACK response received/transmitted interrupt mask */
+#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos)             // 0x00000020
+#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk                        // ACK response received/transmitted interrupt mask
 #define HCINTMSK_NYET_Pos                (6U)
-#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos)             // 0x00000040 */
-#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk                        // response received interrupt mask */
+#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos)             // 0x00000040
+#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk                        // response received interrupt mask
 #define HCINTMSK_TXERRM_Pos              (7U)
-#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos)           // 0x00000080 */
-#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk                      // Transaction error mask */
+#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos)           // 0x00000080
+#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk                      // Transaction error mask
 #define HCINTMSK_BBERRM_Pos              (8U)
-#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos)           // 0x00000100 */
-#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk                      // Babble error mask */
+#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos)           // 0x00000100
+#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk                      // Babble error mask
 #define HCINTMSK_FRMORM_Pos              (9U)
-#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos)           // 0x00000200 */
-#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk                      // Frame overrun mask */
+#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos)           // 0x00000200
+#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk                      // Frame overrun mask
 #define HCINTMSK_DTERRM_Pos              (10U)
-#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos)           // 0x00000400 */
-#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk                      // Data toggle error mask */
+#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos)           // 0x00000400
+#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk                      // Data toggle error mask
 
 /********************  Bit definition for DIEPTSIZ register  ********************/
 
 #define DIEPTSIZ_XFRSIZ_Pos              (0U)
-#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF */
-#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk                      // Transfer size */
+#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF
+#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk                      // Transfer size
 #define DIEPTSIZ_PKTCNT_Pos              (19U)
-#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos)         // 0x1FF80000 */
-#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk                      // Packet count */
+#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos)         // 0x1FF80000
+#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk                      // Packet count
 #define DIEPTSIZ_MULCNT_Pos              (29U)
-#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos)           // 0x60000000 */
-#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk                      // Packet count */
+#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos)           // 0x60000000
+#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk                      // Packet count
                                                                                   /********************  Bit definition for HCTSIZ register  ********************/
 #define HCTSIZ_XFRSIZ_Pos                (0U)
-#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos)         // 0x0007FFFF */
-#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk                        // Transfer size */
+#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos)         // 0x0007FFFF
+#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk                        // Transfer size
 #define HCTSIZ_PKTCNT_Pos                (19U)
-#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos)           // 0x1FF80000 */
-#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk                        // Packet count */
+#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos)           // 0x1FF80000
+#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk                        // Packet count
 #define HCTSIZ_DOPING_Pos                (31U)
-#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos)             // 0x80000000 */
-#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk                        // Do PING */
+#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos)             // 0x80000000
+#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk                        // Do PING
 #define HCTSIZ_DPID_Pos                  (29U)
-#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos)               // 0x60000000 */
-#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk                          // Data PID */
-#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos)               // 0x20000000 */
-#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos)               // 0x40000000 */
+#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos)               // 0x60000000
+#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk                          // Data PID
+#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos)               // 0x20000000
+#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos)               // 0x40000000
 
 /********************  Bit definition for DIEPDMA register  ********************/
 #define DIEPDMA_DMAADDR_Pos              (0U)
-#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos)    // 0xFFFFFFFF */
-#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk                      // DMA address */
+#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos)    // 0xFFFFFFFF
+#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk                      // DMA address
 
 /********************  Bit definition for HCDMA register  ********************/
 #define HCDMA_DMAADDR_Pos                (0U)
-#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos)      // 0xFFFFFFFF */
-#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk                        // DMA address */
+#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos)      // 0xFFFFFFFF
+#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk                        // DMA address
 
                                                                                   /********************  Bit definition for DTXFSTS register  ********************/
 #define DTXFSTS_INEPTFSAV_Pos            (0U)
-#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos)      // 0x0000FFFF */
-#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk                    // IN endpoint TxFIFO space available */
+#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos)      // 0x0000FFFF
+#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk                    // IN endpoint TxFIFO space available
 
                                                                                   /********************  Bit definition for DIEPTXF register  ********************/
 #define DIEPTXF_INEPTXSA_Pos             (0U)
-#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos)       // 0x0000FFFF */
-#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk                     // IN endpoint FIFOx transmit RAM start address */
+#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos)       // 0x0000FFFF
+#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk                     // IN endpoint FIFOx transmit RAM start address
 #define DIEPTXF_INEPTXFD_Pos             (16U)
-#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos)       // 0xFFFF0000 */
-#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk                     // IN endpoint TxFIFO depth */
+#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos)       // 0xFFFF0000
+#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk                     // IN endpoint TxFIFO depth
 
 /********************  Bit definition for DOEPCTL register  ********************/
 #define DOEPCTL_MPSIZ_Pos                (0U)
-#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           // 0x000007FF */
-#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        // Maximum packet size */          //Bit 1 */
+#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           // 0x000007FF
+#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        // Maximum packet size          //Bit 1
 #define DOEPCTL_USBAEP_Pos               (15U)
-#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos)            // 0x00008000 */
-#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk                       // USB active endpoint */
+#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos)            // 0x00008000
+#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk                       // USB active endpoint
 #define DOEPCTL_NAKSTS_Pos               (17U)
-#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos)            // 0x00020000 */
-#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk                       // NAK status */
+#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos)            // 0x00020000
+#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk                       // NAK status
 #define DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000 */
-#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID */
+#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000
+#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID
 #define DOEPCTL_SODDFRM_Pos              (29U)
-#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos)           // 0x20000000 */
-#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk                      // Set odd frame */
+#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos)           // 0x20000000
+#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk                      // Set odd frame
 #define DOEPCTL_EPTYP_Pos                (18U)
-#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos)             // 0x000C0000 */
-#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk                        // Endpoint type */
-#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos)             // 0x00040000 */
-#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos)             // 0x00080000 */
+#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos)             // 0x000C0000
+#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk                        // Endpoint type
+#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos)             // 0x00040000
+#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos)             // 0x00080000
 #define DOEPCTL_SNPM_Pos                 (20U)
-#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos)              // 0x00100000 */
-#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk                         // Snoop mode */
+#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos)              // 0x00100000
+#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk                         // Snoop mode
 #define DOEPCTL_STALL_Pos                (21U)
-#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos)             // 0x00200000 */
-#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk                        // STALL handshake */
+#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos)             // 0x00200000
+#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk                        // STALL handshake
 #define DOEPCTL_CNAK_Pos                 (26U)
-#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos)              // 0x04000000 */
-#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk                         // Clear NAK */
+#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos)              // 0x04000000
+#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk                         // Clear NAK
 #define DOEPCTL_SNAK_Pos                 (27U)
-#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos)              // 0x08000000 */
-#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk                         // Set NAK */
+#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos)              // 0x08000000
+#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk                         // Set NAK
 #define DOEPCTL_EPDIS_Pos                (30U)
-#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos)             // 0x40000000 */
-#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk                        // Endpoint disable */
+#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos)             // 0x40000000
+#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk                        // Endpoint disable
 #define DOEPCTL_EPENA_Pos                (31U)
-#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos)             // 0x80000000 */
-#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk                        // Endpoint enable */
+#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos)             // 0x80000000
+#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk                        // Endpoint enable
 
 /********************  Bit definition for DOEPINT register  ********************/
 #define DOEPINT_XFRC_Pos                 (0U)
-#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos)              // 0x00000001 */
-#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk                         // Transfer completed interrupt */
+#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos)              // 0x00000001
+#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk                         // Transfer completed interrupt
 #define DOEPINT_EPDISD_Pos               (1U)
-#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos)            // 0x00000002 */
-#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk                       // Endpoint disabled interrupt */
+#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos)            // 0x00000002
+#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk                       // Endpoint disabled interrupt
 #define DOEPINT_AHBERR_Pos               (2U)
-#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos)            // 0x00000004 */
-#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an OUT transaction */
+#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos)            // 0x00000004
+#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an OUT transaction
 #define DOEPINT_STUP_Pos                 (3U)
-#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos)              // 0x00000008 */
-#define DOEPINT_STUP                     DOEPINT_STUP_Msk                         // SETUP phase done */
+#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos)              // 0x00000008
+#define DOEPINT_STUP                     DOEPINT_STUP_Msk                         // SETUP phase done
 #define DOEPINT_OTEPDIS_Pos              (4U)
-#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos)           // 0x00000010 */
-#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk                      // OUT token received when endpoint disabled */
+#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos)           // 0x00000010
+#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk                      // OUT token received when endpoint disabled
 #define DOEPINT_OTEPSPR_Pos              (5U)
-#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos)           // 0x00000020 */
-#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk                      // Status Phase Received For Control Write */
+#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos)           // 0x00000020
+#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk                      // Status Phase Received For Control Write
 #define DOEPINT_B2BSTUP_Pos              (6U)
-#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos)           // 0x00000040 */
-#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk                      // Back-to-back SETUP packets received */
+#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos)           // 0x00000040
+#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk                      // Back-to-back SETUP packets received
 #define DOEPINT_OUTPKTERR_Pos            (8U)
-#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos)         // 0x00000100 */
-#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk                    // OUT packet error */
+#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos)         // 0x00000100
+#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk                    // OUT packet error
 #define DOEPINT_NAK_Pos                  (13U)
-#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos)               // 0x00002000 */
-#define DOEPINT_NAK                      DOEPINT_NAK_Msk                          // NAK Packet is transmitted by the device */
+#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos)               // 0x00002000
+#define DOEPINT_NAK                      DOEPINT_NAK_Msk                          // NAK Packet is transmitted by the device
 #define DOEPINT_NYET_Pos                 (14U)
-#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos)              // 0x00004000 */
-#define DOEPINT_NYET                     DOEPINT_NYET_Msk                         // NYET interrupt */
+#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos)              // 0x00004000
+#define DOEPINT_NYET                     DOEPINT_NYET_Msk                         // NYET interrupt
 #define DOEPINT_STPKTRX_Pos              (15U)
-#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos)           // 0x00008000 */
-#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk                      // Setup Packet Received */
+#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos)           // 0x00008000
+#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk                      // Setup Packet Received
 
 /********************  Bit definition for DOEPTSIZ register  ********************/
 #define DOEPTSIZ_XFRSIZ_Pos              (0U)
-#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF */
-#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk                      // Transfer size */
+#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF
+#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk                      // Transfer size
 #define DOEPTSIZ_PKTCNT_Pos              (19U)
-#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos)         // 0x1FF80000 */
-#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk                      // Packet count */
+#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos)         // 0x1FF80000
+#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk                      // Packet count
 
 #define DOEPTSIZ_STUPCNT_Pos             (29U)
-#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos)          // 0x60000000 */
-#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk                     // SETUP packet count */
-#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          // 0x20000000 */
-#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          // 0x40000000 */
+#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos)          // 0x60000000
+#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk                     // SETUP packet count
+#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          // 0x20000000
+#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          // 0x40000000
 
 /********************  Bit definition for PCGCTL register  ********************/
 #define PCGCTL_IF_DEV_MODE              TU_BIT(31)
-- 
cgit v1.3.1


From db3ff4b3527b9b81d381ecc21a74e76e81b2a8e9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Oct 2023 11:26:31 +0700
Subject: usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL set

---
 hw/bsp/family_support.cmake                       |  2 +-
 hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake |  1 +
 hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h     |  6 +++--
 hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk    |  1 +
 hw/bsp/stm32u5/family.c                           | 28 +++++++++++------------
 src/portable/synopsys/dwc2/dcd_dwc2.c             |  3 ++-
 src/portable/synopsys/dwc2/dwc2_stm32.h           | 25 +++++++++++---------
 7 files changed, 37 insertions(+), 29 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 9c625b58e..eec42160e 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -217,7 +217,7 @@ function(family_configure_common TARGET RTOS)
       if (NOT TARGET segger_rtt)
         add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
         target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
-        target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
+        #target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
       endif()
       target_link_libraries(${TARGET} PUBLIC segger_rtt)
     endif ()
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
index 24d4ef95a..230c3b722 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.cmake
@@ -6,5 +6,6 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32U5A5ZJTXQ_FLASH.ld)
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     STM32U5A5xx
+    HSE_VALUE=16000000UL
     )
 endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
index c4eb94dd8..1cc61d6bb 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h
@@ -38,8 +38,8 @@ extern "C"
 #define LED_STATE_ON 1
 
 // BUTTON
-#define BUTTON_PORT GPIOA
-#define BUTTON_PIN GPIO_PIN_0
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
 #define BUTTON_STATE_ACTIVE 1
 
 // UART Enable for STLink VCOM
@@ -101,6 +101,8 @@ static void SystemClock_Config(void) {
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 
   // USB Clock
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHY;
   PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
index 13025efa6..e759cec24 100644
--- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk
@@ -1,5 +1,6 @@
 CFLAGS += \
   -DSTM32U5A5xx \
+  -DHSE_VALUE=16000000UL \
 
 # All source paths should be relative to the top level.
 LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 3fbc50d93..94294b25d 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -124,7 +124,7 @@ void board_init(void) {
 
   HAL_UART_Init(&UartHandle);
 
-  /* Configure USB FS GPIOs */
+  /* Configure USB GPIOs */
   /* Configure DM DP Pins */
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -153,6 +153,12 @@ void board_init(void) {
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+  /* Enable USB power on Pwrctrl CR2 register */
+  HAL_PWREx_EnableVddUSB();
+
+  /* USB clock enable */
+  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
   // Enable VBUS sense (B device) via pin PA9
   USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
   #else
@@ -164,11 +170,6 @@ void board_init(void) {
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
   #endif // vbus sense
 
-  /* Enable USB power on Pwrctrl CR2 register */
-  HAL_PWREx_EnableVddUSB();
-
-  /* USB clock enable */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 #else
   // STM59x/Ax/Fx/Gx only have 1 USB HS port
 
@@ -177,15 +178,7 @@ void board_init(void) {
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   #endif
 
-  // Disable VBUS sense (B device)
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-
   /* USB clock enable */
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
   __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
   __HAL_RCC_USBPHYC_CLK_ENABLE();
 
@@ -195,6 +188,13 @@ void board_init(void) {
 
   /*Configuring the SYSCFG registers OTG_HS PHY*/
   HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
+
+  // Disable VBUS sense (B device)
+  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  // B-peripheral session valid override enable
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
 #endif // USB_OTG_FS
 
 
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 7b50a7d54..5c5450ac2 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -1074,7 +1074,6 @@ void dcd_int_handler(uint8_t rhport) {
 
   if (int_status & GINTSTS_ENUMDNE) {
     // ENUMDNE is the end of reset where speed of the link is detected
-
     dwc2->gintsts = GINTSTS_ENUMDNE;
 
     tusb_speed_t speed;
@@ -1094,6 +1093,8 @@ void dcd_int_handler(uint8_t rhport) {
         break;
     }
 
+    // TODO must update GUSBCFG_TRDT according to link speed
+
     dcd_event_bus_reset(rhport, speed, true);
   }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 57df4e941..2070c3943 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _DWC2_STM32_H_
-#define _DWC2_STM32_H_
+#ifndef DWC2_STM32_H_
+#define DWC2_STM32_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -124,35 +124,36 @@ static const dwc2_controller_t _dwc2_controller[] = {
 // SystemCoreClock is already included by family header
 // extern uint32_t SystemCoreClock;
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_enable(uint8_t rhport) {
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
   NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_dcd_int_disable(uint8_t rhport) {
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
   NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline void dwc2_remote_wakeup_delay(void) {
+TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
   // try to delay for 1 ms
   uint32_t count = SystemCoreClock / 1000;
   while (count--) __NOP();
 }
 
 // MCU specific PHY init, called BEFORE core reset
+// - dwc2 3.30a (H5) use USB_HS_PHYC
+// - dwc2 4.11a (U5) use femtoPHY
 static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   if (hs_phy_type == HS_PHY_TYPE_NONE) {
     // Enable on-chip FS PHY
     dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
   } else {
+#if CFG_TUSB_MCU != OPT_MCU_STM32U5
     // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
     dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+#endif
 
     // Enable on-chip HS PHY
     if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
-#ifdef USB_HS_PHYC
+      #ifdef USB_HS_PHYC
       // Enable UTMI HS PHY
       dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
 
@@ -184,7 +185,9 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
 
       // Enable PLL internal PHY
       USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-#endif
+      #else
+
+      #endif
     }
   }
 }
@@ -232,4 +235,4 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
 }
 #endif
 
-#endif /* _DWC2_STM32_H_ */
+#endif
-- 
cgit v1.3.1


From 214a4afa6aafe9daac6c1c304eb305b44e8cf86d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Oct 2023 11:53:40 +0700
Subject: dwc2 flush tx,rx fifo in dcd_init()

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 5c5450ac2..ac93632be 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -447,6 +447,14 @@ void dcd_init(uint8_t rhport) {
   // (non zero-length packet), send STALL back and discard.
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
+  // flush all TX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
+  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+
+  // flush RX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_RXFFLSH;
+  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+
   // Clear all interrupts
   uint32_t int_mask = dwc2->gintsts;
   dwc2->gintsts |= int_mask;
-- 
cgit v1.3.1


From 06c9d9a79a4426ece73052edca885f890b997fc4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Nov 2023 16:36:28 +0700
Subject: remove legacy driver st/synopsys

---
 src/portable/st/synopsys/dcd_synopsys.c    | 1240 -----------------------
 src/portable/st/synopsys/synopsys_common.h | 1465 ----------------------------
 2 files changed, 2705 deletions(-)
 delete mode 100644 src/portable/st/synopsys/dcd_synopsys.c
 delete mode 100644 src/portable/st/synopsys/synopsys_common.h

(limited to 'src')

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
deleted file mode 100644
index 2fc3adb4f..000000000
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ /dev/null
@@ -1,1240 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Copyright (c) 2020 Jan Duempelmann
- * Copyright (c) 2020 Reinhard Panhuber
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#define USE_SOF     0
-
-#if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
-    defined (STM32F107xB) || defined (STM32F107xC)
-#define STM32F1_SYNOPSYS
-#endif
-
-#if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
-    defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
-    defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define STM32L4_SYNOPSYS
-#endif
-
-#if CFG_TUD_ENABLED &&                                          \
-    ( (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \
-       CFG_TUSB_MCU == OPT_MCU_STM32F2                               || \
-       CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
-       CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
-       CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)  || \
-       CFG_TUSB_MCU == OPT_MCU_GD32VF103 )                           \
-    )
-
-// EP_MAX       : Max number of bi-directional endpoints including EP0
-// EP_FIFO_SIZE : Size of dedicated USB SRAM
-#if CFG_TUSB_MCU == OPT_MCU_STM32F1
-#include "stm32f1xx.h"
-#define EP_MAX_FS       4
-#define EP_FIFO_SIZE_FS 1280
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F2
-#include "stm32f2xx.h"
-#define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
-#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
-#include "stm32f4xx.h"
-#define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
-#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
-#define EP_MAX_HS       USB_OTG_HS_MAX_IN_ENDPOINTS
-#define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
-#include "stm32h7xx.h"
-#define EP_MAX_FS       9
-#define EP_FIFO_SIZE_FS 4096
-#define EP_MAX_HS       9
-#define EP_FIFO_SIZE_HS 4096
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
-#include "stm32f7xx.h"
-#define EP_MAX_FS       6
-#define EP_FIFO_SIZE_FS 1280
-#define EP_MAX_HS       9
-#define EP_FIFO_SIZE_HS 4096
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
-#include "stm32l4xx.h"
-#define EP_MAX_FS       6
-#define EP_FIFO_SIZE_FS 1280
-
-#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
-#include "synopsys_common.h"
-
-// for remote wakeup delay
-#define __NOP()   __asm volatile ("nop")
-
-// These numbers are the same for the whole GD32VF103 family.
-#define OTG_FS_IRQn     86
-#define EP_MAX_FS       4
-#define EP_FIFO_SIZE_FS 1280
-
-// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
-// Interrupt Controller by Nuclei. It is nearly API compatible to the
-// NVIC used by ARM MCUs.
-#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
-
-#define NVIC_EnableIRQ __eclic_enable_interrupt
-#define NVIC_DisableIRQ __eclic_disable_interrupt
-
-static inline void __eclic_enable_interrupt (uint32_t irq) {
-  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
-}
-
-static inline void __eclic_disable_interrupt (uint32_t irq){
-  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
-}
-
-#else
-#error "Unsupported MCUs"
-#endif
-
-#include "device/dcd.h"
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
-#if TUD_OPT_RHPORT == 0
-#define EP_MAX            EP_MAX_FS
-#define EP_FIFO_SIZE      EP_FIFO_SIZE_FS
-#define RHPORT_REGS_BASE  USB_OTG_FS_PERIPH_BASE
-#define RHPORT_IRQn       OTG_FS_IRQn
-
-#else
-#define EP_MAX            EP_MAX_HS
-#define EP_FIFO_SIZE      EP_FIFO_SIZE_HS
-#define RHPORT_REGS_BASE  USB_OTG_HS_PERIPH_BASE
-#define RHPORT_IRQn       OTG_HS_IRQn
-
-#endif
-
-#define GLOBAL_BASE(_port)     ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
-#define DEVICE_BASE(_port)     (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)
-#define OUT_EP_BASE(_port)     (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE)
-#define IN_EP_BASE(_port)      (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE)
-#define FIFO_BASE(_port, _x)   ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
-
-enum
-{
-  DCD_HIGH_SPEED        = 0, // Highspeed mode
-  DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY)
-  DCD_FULL_SPEED        = 3, // Full speed with internal PHY
-};
-
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
-
-typedef struct {
-  uint8_t * buffer;
-  tu_fifo_t * ff;
-  uint16_t total_len;
-  uint16_t max_size;
-  uint8_t interval;
-} xfer_ctl_t;
-
-typedef volatile uint32_t * usb_fifo_t;
-
-xfer_ctl_t xfer_status[EP_MAX][2];
-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
-
-// EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
-
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
-static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
-static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
-
-// Calculate the RX FIFO size according to recommendations from reference manual
-static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
-{
-  return 15 + 2*(ep_size/4) + 2*EP_MAX;
-}
-
-static void update_grxfsiz(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  // Determine largest EP size for RX FIFO
-  uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
-  {
-    max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
-  }
-
-  // Update size of RX FIFO
-  usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
-}
-
-// Setup the control endpoint 0.
-static void bus_reset(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  tu_memclr(xfer_status, sizeof(xfer_status));
-  _out_ep_closed = false;
-
-  // clear device address
-  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
-
-  // 1. NAK for all OUT endpoints
-  for(uint8_t n = 0; n < EP_MAX; n++) {
-    out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
-  }
-
-  // 2. Un-mask interrupt bits
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-  dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
-  dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
-
-  // "USB Data FIFOs" section in reference manual
-  // Peripheral FIFO architecture
-  //
-  // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
-  // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
-  // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
-  // configuration done below.
-  //
-  // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
-  // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
-  // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
-  // opened when the host sends an additional command: setInterface. At this point in time
-  // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
-  // an additional memory
-  //
-  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-  // | IN FIFO 0   |
-  // --------------- (320 or 1024) - 16
-  // | IN FIFO 1   |
-  // --------------- (320 or 1024) - 16 - x
-  // |   . . . .   |
-  // --------------- (320 or 1024) - 16 - x - y - ... - z
-  // | IN FIFO MAX |
-  // ---------------
-  // |    FREE     |
-  // --------------- GRXFSIZ
-  // | OUT FIFO    |
-  // | ( Shared )  |
-  // --------------- 0
-  //
-  // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
-  // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
-  //
-  // - All EP OUT shared a unique OUT FIFO which uses
-  //   - 13 for setup packets + control words (up to 3 setup packets).
-  //   - 1 for global NAK (not required/used here).
-  //   - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4) + 1"
-  //   - 2 for each used OUT endpoint
-  //
-  //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
-  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x EP_MAX = 47  + 2 x EP_MAX
-  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
-  //
-  //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
-  //   of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
-  //
-  //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
-  //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
-  //   overwrite this.
-
-  usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
-
-  _allocated_fifo_words_tx = 16;
-
-  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
-
-  // Fixed control EP0 size to 64 bytes
-  in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
-  xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
-
-  out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
-
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
-}
-
-// Set turn-around timeout according to link speed
-extern uint32_t SystemCoreClock;
-static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
-{
-  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
-  if ( speed == TUSB_SPEED_HIGH )
-  {
-    // Use fixed 0x09 for Highspeed
-    usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
-  }
-  else
-  {
-    // Turnaround timeout depends on the MCU clock
-    uint32_t turnaround;
-
-    if ( SystemCoreClock >= 32000000U )
-      turnaround = 0x6U;
-    else if ( SystemCoreClock >= 27500000U )
-      turnaround = 0x7U;
-    else if ( SystemCoreClock >= 24000000U )
-      turnaround = 0x8U;
-    else if ( SystemCoreClock >= 21800000U )
-      turnaround = 0x9U;
-    else if ( SystemCoreClock >= 20000000U )
-      turnaround = 0xAU;
-    else if ( SystemCoreClock >= 18500000U )
-      turnaround = 0xBU;
-    else if ( SystemCoreClock >= 17200000U )
-      turnaround = 0xCU;
-    else if ( SystemCoreClock >= 16000000U )
-      turnaround = 0xDU;
-    else if ( SystemCoreClock >= 15000000U )
-      turnaround = 0xEU;
-    else
-      turnaround = 0xFU;
-
-    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos);
-  }
-}
-
-static tusb_speed_t get_speed(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
-  return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
-}
-
-static void set_speed(uint8_t rhport, tusb_speed_t speed)
-{
-  uint32_t bitvalue;
-
-  if ( rhport == 1 )
-  {
-    bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
-  }
-  else
-  {
-    bitvalue = DCD_FULL_SPEED;
-  }
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // Clear and set speed bits
-  dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
-  dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
-}
-
-#if defined(USB_HS_PHYC)
-static bool USB_HS_PHYCInit(void)
-{
-  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
-
-  // Enable LDO: Note STM32F72/3xx Reference Manual rev 3 June 2018 incorrectly defined this bit as Disabled !!
-  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
-
-  // Wait until LDO ready
-  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
-
-  uint32_t phyc_pll = 0;
-
-  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
-  switch ( HSE_VALUE )
-  {
-    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
-    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
-    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
-    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
-    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
-    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
-    default:
-      TU_ASSERT(0);
-  }
-  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
-
-  // Control the tuning interface of the High Speed PHY
-  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
-  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
-
-  // Enable PLL internal PHY
-  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-
-  // Original ST code has 2 ms delay for PLL stabilization.
-  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
-
-  return true;
-}
-#endif
-
-static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
-{
-  (void) rhport;
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  // EP0 is limited to one packet each xfer
-  // We use multiple transaction of xfer->max_size length to get a whole transfer done
-  if(epnum == 0) {
-    xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir);
-    total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
-    ep0_pending[dir] -= total_bytes;
-  }
-
-  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
-  if(dir == TUSB_DIR_IN) {
-    // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk);
-
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
-    // For ISO endpoint set correct odd/even bit for next frame.
-    if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk);
-    }
-    // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if(total_bytes != 0) {
-      dev->DIEPEMPMSK |= (1 << epnum);
-    }
-  } else {
-    // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ);
-    out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk);
-
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
-    if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk);
-    }
-  }
-}
-
-/*------------------------------------------------------------------*/
-/* Controller API
- *------------------------------------------------------------------*/
-void dcd_init (uint8_t rhport)
-{
-  // Programming model begins in the last section of the chapter on the USB
-  // peripheral in each Reference Manual.
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  // No HNP/SRP (no OTG support), program timeout later.
-  if ( rhport == 1 )
-  {
-    // On selected MCUs HS port1 can be used with external PHY via ULPI interface
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
-    // deactivate internal PHY
-    usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
-
-    // Init The UTMI Interface
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-
-    // Select default internal VBUS Indicator and Drive for ULPI
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-#else
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-#endif
-
-#if defined(USB_HS_PHYC)
-    // Highspeed with embedded UTMI PHYC
-
-    // Select UTMI Interface
-    usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
-    usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
-
-    // Enables control of a High Speed USB PHY
-    USB_HS_PHYCInit();
-#endif
-  } else
-  {
-    // Enable internal PHY
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-  }
-
-  // Reset core after selecting PHY
-  // Wait AHB IDLE, reset then wait until it is cleared
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
-  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
-
-  // Restart PHY clock
-  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
-
-  // Clear all interrupts
-  usb_otg->GINTSTS |= usb_otg->GINTSTS;
-
-  // Required as part of core initialization.
-  // TODO: How should mode mismatch be handled? It will cause
-  // the core to stop working/require reset.
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // If USB host misbehaves during status portion of control xfer
-  // (non zero-length packet), send STALL back and discard.
-  dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
-
-  set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
-
-  // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
-
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
-      USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM     |
-      USB_OTG_GINTMSK_RXFLVLM  | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
-
-  // Enable global interrupt
-  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
-
-  dcd_connect(rhport);
-}
-
-void dcd_int_enable (uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(RHPORT_IRQn);
-}
-
-void dcd_int_disable (uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(RHPORT_IRQn);
-}
-
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
-
-  // Response with status after changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-}
-
-static void remote_wakeup_delay(void)
-{
-  // try to delay for 1 ms
-  uint32_t count = SystemCoreClock / 1000;
-  while ( count-- )
-  {
-    __NOP();
-  }
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // set remote wakeup
-  dev->DCTL |= USB_OTG_DCTL_RWUSIG;
-
-  // enable SOF to detect bus resume
-  usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
-
-  // Per specs: remote wakeup signal bit must be clear within 1-15ms
-  remote_wakeup_delay();
-
-  dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCTL &= ~USB_OTG_DCTL_SDIS;
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCTL |= USB_OTG_DCTL_SDIS;
-}
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
-}
-
-/*------------------------------------------------------------------*/
-/* DCD Endpoint port
- *------------------------------------------------------------------*/
-
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
-  TU_ASSERT(epnum < EP_MAX);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = tu_edpt_packet_size(desc_edpt);
-  xfer->interval = desc_edpt->bInterval;
-
-  uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word
-
-  if(dir == TUSB_DIR_OUT)
-  {
-    // Calculate required size of RX FIFO
-    uint16_t const sz = calc_rx_ff_size(4*fifo_size);
-
-    // If size_rx needs to be extended check if possible and if so enlarge it
-    if (usb_otg->GRXFSIZ < sz)
-    {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
-
-      // Enlarge RX FIFO
-      usb_otg->GRXFSIZ = sz;
-    }
-
-    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
-
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
-  }
-  else
-  {
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO 0   |
-    // --------------- (320 or 1024) - 16
-    // | IN FIFO 1   |
-    // --------------- (320 or 1024) - 16 - x
-    // |   . . . .   |
-    // --------------- (320 or 1024) - 16 - x - y - ... - z
-    // | IN FIFO MAX |
-    // ---------------
-    // |    FREE     |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // In FIFO is allocated by following rules:
-    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
-    // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
-
-    _allocated_fifo_words_tx += fifo_size;
-
-    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
-
-    // DIEPTXF starts at FIFO #1.
-    // Both TXFD and TXSA are in unit of 32-bit words.
-    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
-
-    in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
-        (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
-
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
-  }
-
-  return true;
-}
-
-// Close all non-control endpoints, cancel all pending transfers if any.
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  (void) rhport;
-
-//  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  // Disable non-control interrupt
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-
-  for(uint8_t n = 1; n < EP_MAX; n++)
-  {
-    // disable OUT endpoint
-    out_ep[n].DOEPCTL = 0;
-    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
-
-    // disable IN endpoint
-    in_ep[n].DIEPCTL = 0;
-    xfer_status[n][TUSB_DIR_IN].max_size = 0;
-  }
-
-  // reset allocated fifo IN
-  _allocated_fifo_words_tx = 16;
-}
-
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = buffer;
-  xfer->ff          = NULL;
-  xfer->total_len   = total_bytes;
-
-  // EP0 can only handle one packet
-  if(epnum == 0) {
-    ep0_pending[dir] = total_bytes;
-    // Schedule the first transaction for EP0 transfer
-    edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
-    return true;
-  }
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) {
-    num_packets++;
-  }
-
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
-
-  return true;
-}
-
-// The number of bytes has to be given explicitly to allow more flexible control of how many
-// bytes should be written and second to keep the return value free to give back a boolean
-// success message. If total_bytes is too big, the FIFO will copy only what is available
-// into the USB buffer!
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
-  TU_ASSERT(ff->item_size == 1);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = NULL;
-  xfer->ff          = ff;
-  xfer->total_len   = total_bytes;
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) num_packets++;
-
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
-
-  return true;
-}
-
-static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  if(dir == TUSB_DIR_IN) {
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0);
-    } else {
-      // Stop transmitting packets and NAK IN xfers.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
-
-      // Disable the endpoint.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0);
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
-      in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
-    }
-
-    // Flush the FIFO, and wait until we have confirmed it cleared.
-    usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos);
-    usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
-    while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
-  } else {
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
-      out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0;
-    } else {
-      // Asserting GONAK is required to STALL an OUT endpoint.
-      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
-      // anyway, and it can't be cleared by user code. If this while loop never
-      // finishes, we have bigger problems than just the stack.
-      dev->DCTL |= USB_OTG_DCTL_SGONAK;
-      while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
-
-      // Ditto here- disable the endpoint.
-      out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0);
-      while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
-      out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
-
-      // Allow other OUT endpoints to keep receiving.
-      dev->DCTL |= USB_OTG_DCTL_CGONAK;
-    }
-  }
-}
-
-/**
- * Close an endpoint.
- */
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_edpt_disable(rhport, ep_addr, false);
-
-  // Update max_size
-  xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
-
-  if (dir == TUSB_DIR_IN)
-  {
-    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
-    // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
-    _allocated_fifo_words_tx -= fifo_size;
-  }
-  else
-  {
-    _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
-  }
-}
-
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  dcd_edpt_disable(rhport, ep_addr, true);
-}
-
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  // Clear stall and reset data toggle
-  if(dir == TUSB_DIR_IN) {
-    in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-  } else {
-    out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-  }
-}
-
-/*------------------------------------------------------------------*/
-
-// Read a single data packet from receive FIFO
-static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
-{
-  (void) rhport;
-
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
-
-  // Reading full available 32 bit words from fifo
-  uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++) {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    dst[1] = (tmp & 0x0000FF00) >> 8;
-    dst[2] = (tmp & 0x00FF0000) >> 16;
-    dst[3] = (tmp & 0xFF000000) >> 24;
-    dst += 4;
-  }
-
-  // Read the remaining 1-3 bytes from fifo
-  uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem != 0) {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    if(bytes_rem > 1) {
-      dst[1] = (tmp & 0x0000FF00) >> 8;
-    }
-    if(bytes_rem > 2) {
-      dst[2] = (tmp & 0x00FF0000) >> 16;
-    }
-  }
-}
-
-// Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len)
-{
-  (void) rhport;
-
-  usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num);
-
-  // Pushing full available 32 bit words to fifo
-  uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++){
-    *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
-    src += 4;
-  }
-
-  // Write the remaining 1-3 bytes into fifo
-  uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem){
-    uint32_t tmp_word = 0;
-    tmp_word |= src[0];
-    if(bytes_rem > 1){
-      tmp_word |= src[1] << 8;
-    }
-    if(bytes_rem > 2){
-      tmp_word |= src[2] << 16;
-    }
-    *tx_fifo = tmp_word;
-  }
-}
-
-static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ep) {
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
-
-  // Pop control word off FIFO
-  uint32_t ctl_word = usb_otg->GRXSTSP;
-  uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
-  uint8_t epnum = (ctl_word &  USB_OTG_GRXSTSP_EPNUM_Msk) >>  USB_OTG_GRXSTSP_EPNUM_Pos;
-  uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
-
-  switch(pktsts) {
-    case 0x01: // Global OUT NAK (Interrupt)
-      break;
-
-    case 0x02: // Out packet recvd
-    {
-      xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-
-      // Read packet off RxFIFO
-      if (xfer->ff)
-      {
-        // Ring buffer
-        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
-      }
-      else
-      {
-        // Linear buffer
-        read_fifo_packet(rhport, xfer->buffer, bcnt);
-
-        // Increment pointer to xfer data
-        xfer->buffer += bcnt;
-      }
-
-      // Truncate transfer length in case of short packet
-      if(bcnt < xfer->max_size) {
-        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
-        if(epnum == 0) {
-          xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
-          ep0_pending[TUSB_DIR_OUT] = 0;
-        }
-      }
-    }
-    break;
-
-    case 0x03: // Out packet done (Interrupt)
-      break;
-
-    case 0x04: // Setup packet done (Interrupt)
-      out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
-      break;
-
-    case 0x06: // Setup packet recvd
-      // We can receive up to three setup packets in succession, but
-      // only the last one is valid.
-      _setup_packet[0] = (* rx_fifo);
-      _setup_packet[1] = (* rx_fifo);
-      break;
-
-    default: // Invalid
-      TU_BREAKPOINT();
-      break;
-  }
-}
-
-static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
-  // DAINT for a given EP clears when DOEPINTx is cleared.
-  // OEPINT will be cleared when DAINT's out bits are cleared.
-  for(uint8_t n = 0; n < EP_MAX; n++) {
-    xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
-    if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
-      // SETUP packet Setup Phase done.
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
-        out_ep[n].DOEPINT =  USB_OTG_DOEPINT_STUP;
-        dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
-      }
-
-      // OUT XFER complete
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
-        out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
-
-        // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
-          // Schedule another packet to be received.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
-        } else {
-          dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-      }
-    }
-  }
-}
-
-static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
-  // DAINT for a given EP clears when DIEPINTx is cleared.
-  // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < EP_MAX; n++ )
-  {
-    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
-
-    if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
-    {
-      // IN XFER complete (entire xfer).
-      if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
-      {
-        in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
-
-        // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
-          // Schedule another packet to be transmitted.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
-        } else {
-          dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-      }
-
-      // XFER FIFO empty
-      if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
-      {
-        // DIEPINT's TXFE bit is read-only, software cannot clear it.
-        // It will only be cleared by hardware when written bytes is more than
-        // - 64 bytes or
-        // - Half of TX FIFO size (configured by DIEPTXF)
-
-        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
-
-        // Process every single packet (only whole packets can be written to fifo)
-        for(uint16_t i = 0; i < remaining_packets; i++)
-        {
-          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
-
-          // Packet can not be larger than ep max size
-          uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
-
-          // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
-          // EP has to be checked if the buffer can take another WHOLE packet
-          if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break;
-
-          // Push packet to Tx-FIFO
-          if (xfer->ff)
-          {
-            usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
-            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
-          }
-          else
-          {
-            write_fifo_packet(rhport, n, xfer->buffer, packet_size);
-
-            // Increment pointer to xfer data
-            xfer->buffer += packet_size;
-          }
-        }
-
-        // Turn off TXFE if all bytes are written.
-        if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
-        {
-          dev->DIEPEMPMSK &= ~(1 << n);
-        }
-      }
-    }
-  }
-}
-
-void dcd_int_handler(uint8_t rhport)
-{
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
-
-  if(int_status & USB_OTG_GINTSTS_USBRST)
-  {
-    // USBRST is start of reset.
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
-    bus_reset(rhport);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_ENUMDNE)
-  {
-    // ENUMDNE is the end of reset where speed of the link is detected
-
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
-
-    tusb_speed_t const speed = get_speed(rhport);
-
-    set_turnaround(usb_otg, speed);
-    dcd_event_bus_reset(rhport, speed, true);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_USBSUSP)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
-    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_WKUINT)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT;
-    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-  }
-
-  // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
-  // if(int_status & USB_OTG_GINTSTS_DISCINT)
-
-  if(int_status & USB_OTG_GINTSTS_OTGINT)
-  {
-    // OTG INT bit is read-only
-    uint32_t const otg_int = usb_otg->GOTGINT;
-
-    if (otg_int & USB_OTG_GOTGINT_SEDET)
-    {
-      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-    }
-
-    usb_otg->GOTGINT = otg_int;
-  }
-
-  if(int_status & USB_OTG_GINTSTS_SOF)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
-
-    // Disable SOF interrupt since currently only used for remote wakeup detection
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
-
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-
-  // RxFIFO non-empty interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_RXFLVL)
-  {
-    // RXFLVL bit is read-only
-
-    // Mask out RXFLVL while reading data from FIFO
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
-
-    // Loop until all available packets were handled
-    do
-    {
-      handle_rxflvl_ints(rhport, out_ep);
-    } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
-
-    // Manage RX FIFO size
-    if (_out_ep_closed)
-    {
-      update_grxfsiz(rhport);
-
-      // Disable flag
-      _out_ep_closed = false;
-    }
-
-    usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
-  }
-
-  // OUT endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_OEPINT)
-  {
-    // OEPINT is read-only
-    handle_epout_ints(rhport, dev, out_ep);
-  }
-
-  // IN endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_IEPINT)
-  {
-    // IEPINT bit read-only
-    handle_epin_ints(rhport, dev, in_ep);
-  }
-
-  //  // Check for Incomplete isochronous IN transfer
-  //  if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
-  //    printf("      IISOIXFR!\r\n");
-  ////    TU_LOG2("      IISOIXFR!\r\n");
-  //  }
-}
-
-#endif
diff --git a/src/portable/st/synopsys/synopsys_common.h b/src/portable/st/synopsys/synopsys_common.h
deleted file mode 100644
index ce3195b23..000000000
--- a/src/portable/st/synopsys/synopsys_common.h
+++ /dev/null
@@ -1,1465 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    synopsys_common.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device USB OTG peripheral Header File.
-  *          This file contains the USB OTG peripheral register's definitions, bits
-  *          definitions and memory mapping for STM32F1xx devices.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for the USB OTG peripheral
-  *           - The Peripheral's registers declarations and bits definition
-  *           - Macros to access the peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-#include "stdint.h"
-
-#pragma once
-
-#ifdef __cplusplus
-  #define   __I   volatile
-#else
-  #define   __I   volatile const
-#endif
-#define     __O   volatile
-#define     __IO  volatile
-#define     __IM  volatile const
-#define     __OM  volatile
-#define     __IOM volatile
-
-/**
-  * @brief __USB_OTG_Core_register
-  */
-
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register       Address offset: 000h */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                Address offset: 004h */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register           Address offset: 008h */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register           Address offset: 00Ch */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                       Address offset: 010h */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                   Address offset: 014h */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register              Address offset: 018h */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register               Address offset: 01Ch */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register         Address offset: 020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                 Address offset: 024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register  Address offset: 028h */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg        Address offset: 02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved 030h*/
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                Address offset: 038h */
-  __IO uint32_t CID;                  /*!< User ID Register                           Address offset: 03Ch */
-  uint32_t  Reserved40[48];           /*!< Reserved 040h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg             Address offset: 100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
-} USB_OTG_GlobalTypeDef;
-
-/**
-  * @brief __device_Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t DCFG;                 /*!< dev Configuration Register                 Address offset: 800h*/
-  __IO uint32_t DCTL;                 /*!< dev Control Register                       Address offset: 804h*/
-  __IO uint32_t DSTS;                 /*!< dev Status Register (RO)                   Address offset: 808h*/
-  uint32_t Reserved0C;                /*!< Reserved 80Ch*/
-  __IO uint32_t DIEPMSK;              /*!< dev IN Endpoint Mask                       Address offset: 810h*/
-  __IO uint32_t DOEPMSK;              /*!< dev OUT Endpoint Mask                      Address offset: 814h*/
-  __IO uint32_t DAINT;                /*!< dev All Endpoints Itr Reg                  Address offset: 818h*/
-  __IO uint32_t DAINTMSK;             /*!< dev All Endpoints Itr Mask                 Address offset: 81Ch*/
-  uint32_t  Reserved20;               /*!< Reserved 820h*/
-  uint32_t Reserved9;                 /*!< Reserved 824h*/
-  __IO uint32_t DVBUSDIS;             /*!< dev VBUS discharge Register                Address offset: 828h*/
-  __IO uint32_t DVBUSPULSE;           /*!< dev VBUS Pulse Register                    Address offset: 82Ch*/
-  __IO uint32_t DTHRCTL;              /*!< dev thr                                    Address offset: 830h*/
-  __IO uint32_t DIEPEMPMSK;           /*!< dev empty msk                              Address offset: 834h*/
-  __IO uint32_t DEACHINT;             /*!< dedicated EP interrupt                     Address offset: 838h*/
-  __IO uint32_t DEACHMSK;             /*!< dedicated EP msk                           Address offset: 83Ch*/
-  uint32_t Reserved40;                /*!< dedicated EP mask                          Address offset: 840h*/
-  __IO uint32_t DINEP1MSK;            /*!< dedicated EP mask                          Address offset: 844h*/
-  uint32_t  Reserved44[15];           /*!< Reserved 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK;           /*!< dedicated EP msk                           Address offset: 884h*/
-} USB_OTG_DeviceTypeDef;
-
-/**
-  * @brief __IN_Endpoint-Specific_Register
-  */
-
-typedef struct
-{
-  __IO uint32_t DIEPCTL;              /*!< dev IN Endpoint Control Reg                900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;                /*!< Reserved                                   900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT;              /*!< dev IN Endpoint Itr Reg                    900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;                /*!< Reserved                                   900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ;             /*!< IN Endpoint Txfer Size                     900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA;              /*!< IN Endpoint DMA Address Reg                900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;              /*!< IN Endpoint Tx FIFO Status Reg             900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;                /*!< Reserved                                   900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-} USB_OTG_INEndpointTypeDef;
-
-/**
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t DOEPCTL;              /*!< dev OUT Endpoint Control Reg               B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;                /*!< Reserved                                   B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;              /*!< dev OUT Endpoint Itr Reg                   B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;                /*!< Reserved                                   B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;             /*!< dev OUT Endpoint Txfer Size                B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;              /*!< dev OUT Endpoint DMA Address               B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];             /*!< Reserved                                   B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-} USB_OTG_OUTEndpointTypeDef;
-
-/**
-  * @brief __Host_Mode_Register_Structures
-  */
-
-typedef struct
-{
-  __IO uint32_t HCFG;                 /*!< Host Configuration Register    400h*/
-  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;               /*!< Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask 418h*/
-} USB_OTG_HostTypeDef;
-
-/**
-  * @brief __Host_Channel_Specific_Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-} USB_OTG_HostChannelTypeDef;
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
-
-#define USB_OTG_GLOBAL_BASE                  0x00000000UL
-#define USB_OTG_DEVICE_BASE                  0x00000800UL
-#define USB_OTG_IN_ENDPOINT_BASE             0x00000900UL
-#define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00UL
-#define USB_OTG_EP_REG_SIZE                  0x00000020UL
-#define USB_OTG_HOST_BASE                    0x00000400UL
-#define USB_OTG_HOST_PORT_BASE               0x00000440UL
-#define USB_OTG_HOST_CHANNEL_BASE            0x00000500UL
-#define USB_OTG_HOST_CHANNEL_SIZE            0x00000020UL
-#define USB_OTG_PCGCCTL_BASE                 0x00000E00UL
-#define USB_OTG_FIFO_BASE                    0x00001000UL
-#define USB_OTG_FIFO_SIZE                    0x00001000UL
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 USB_OTG                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)
-#define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)
-#define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
-#define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)
-#define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)
-#define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)
-#define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)
-#define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
-#define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)
-#define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
-#define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)
-#define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)
-#define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)
-#define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)
-#define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
-#define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCFG_FSLSS_Pos                  (2U)
-#define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD_Pos                   (0U)
-#define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
-#define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)
-#define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD_Pos                    (4U)
-#define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCFG_DAD_1                      (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCFG_DAD_2                      (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCFG_DAD_3                      (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCFG_DAD_4                      (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
-
-#define USB_OTG_DCFG_PFIVL_Pos                  (11U)
-#define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
-
-#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)
-#define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
-#define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)
-#define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)
-#define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)
-#define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET_Pos               (2U)
-#define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
-#define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)
-#define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)
-#define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)
-#define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)
-#define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)
-#define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)
-#define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS_Pos                   (1U)
-#define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS_Pos                 (2U)
-#define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS_Pos                 (3U)
-#define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
-#define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL_Pos                   (4U)
-#define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
-#define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCTL_SGINAK_Pos                 (7U)
-#define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK_Pos                 (8U)
-#define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK_Pos                 (9U)
-#define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK_Pos                 (10U)
-#define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
-#define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)
-#define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL_Pos                  (0U)
-#define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)
-#define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM_Pos                 (16U)
-#define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)
-#define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)
-#define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
-#define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
-#define USB_OTG_DSTS_EERR_Pos                   (3U)
-#define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
-#define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF_Pos                  (8U)
-#define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
-#define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT_Pos                (0U)
-#define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
-#define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)
-#define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
-#define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
-#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
-#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
-#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
-#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)
-#define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)
-#define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
-#define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)
-#define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
-#define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)
-#define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
-#define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
-#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)
-#define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
-#define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)
-#define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
-#define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)
-#define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
-#define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)
-#define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
-#define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
-#define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
-#define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
-#define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
-#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)
-#define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)
-#define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
-#define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)
-#define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
-#define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)
-#define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
-#define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)
-#define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
-#define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)
-#define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
-#define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)
-#define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
-#define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)
-#define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
-#define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)
-#define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
-#define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)
-#define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
-#define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)
-#define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)
-#define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
-#define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)
-#define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
-#define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)
-#define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
-#define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)
-#define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
-#define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)
-#define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
-#define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
-
-
-#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)
-#define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
-#define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)
-#define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
-#define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)
-#define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
-#define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)
-#define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)
-#define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)
-#define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)
-#define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)
-#define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)
-#define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)
-#define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)
-#define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)
-#define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)
-#define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT_Pos                 (0U)
-#define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)
-#define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)
-#define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
-#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
-#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)
-#define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)
-#define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
-#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)
-#define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)
-#define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)
-#define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
-#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
-#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
-#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
-#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
-#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
-#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD_Pos                (0U)
-#define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
-#define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS_Pos                (1U)
-#define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)
-#define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF_Pos                 (3U)
-#define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)
-#define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)
-#define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)
-#define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)
-#define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)
-#define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST_Pos              (12U)
-#define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)
-#define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)
-#define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF_Pos                (15U)
-#define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)
-#define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)
-#define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)
-#define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)
-#define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)
-#define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT_Pos               (25U)
-#define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)
-#define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)
-#define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)
-#define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)
-#define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)
-#define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM_Pos               (1U)
-#define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)
-#define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM_Pos                (3U)
-#define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)
-#define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)
-#define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)
-#define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)
-#define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)
-#define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)
-#define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST_Pos              (12U)
-#define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)
-#define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)
-#define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)
-#define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)
-#define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
-#define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)
-#define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)
-#define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)
-#define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)
-#define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)
-#define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM_Pos                (25U)
-#define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)
-#define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)
-#define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)
-#define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)
-#define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM_Pos                (31U)
-#define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT_Pos                (0U)
-#define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT_Pos                (16U)
-#define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)
-#define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)
-#define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
-#define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)
-#define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
-#define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID_Pos                (15U)
-#define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
-#define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)
-#define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
-#define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)
-#define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)
-#define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)
-#define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)
-#define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA_Pos                     (0U)
-#define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD_Pos                      (16U)
-#define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA_Pos                      (0U)
-#define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD_Pos                       (16U)
-#define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)
-#define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
-#define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1             (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2             (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3             (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4             (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5             (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1             (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2             (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3             (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4             (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5             (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)
-#define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
-#define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)
-#define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
-#define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)
-#define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
-#define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)
-#define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
-#define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)
-#define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
-#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)
-#define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
-#define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)
-#define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)
-#define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)
-#define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
-#define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
-#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)
-#define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)
-#define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)
-#define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)
-#define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)
-#define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)
-#define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)
-#define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)
-#define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS_Pos                  (0U)
-#define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET_Pos                  (1U)
-#define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
-#define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA_Pos                   (2U)
-#define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
-#define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG_Pos                (3U)
-#define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
-#define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA_Pos                   (4U)
-#define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
-#define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG_Pos                (5U)
-#define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
-#define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES_Pos                   (6U)
-#define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
-#define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP_Pos                  (7U)
-#define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
-#define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
-#define USB_OTG_HPRT_PRST_Pos                   (8U)
-#define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
-#define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS_Pos                  (10U)
-#define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
-#define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
-#define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_HPRT_PPWR_Pos                   (12U)
-#define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL_Pos                  (13U)
-#define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
-#define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
-#define USB_OTG_HPRT_PTCTL_1                    (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
-#define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
-#define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
-
-#define USB_OTG_HPRT_PSPD_Pos                   (17U)
-#define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
-#define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)
-#define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)
-#define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)
-#define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)
-#define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)
-#define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)
-#define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)
-#define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)
-#define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)
-#define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)
-#define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)
-#define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
-#define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)
-#define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)
-#define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DIEPCTL_STALL_Pos               (21U)
-#define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)
-#define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
-#define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
-#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)
-#define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)
-#define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)
-#define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)
-#define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)
-#define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)
-#define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)
-#define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
-#define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
-#define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)
-#define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)
-#define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)
-#define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
-
-#define USB_OTG_HCCHAR_MC_Pos                   (20U)
-#define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
-#define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
-#define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
-
-#define USB_OTG_HCCHAR_DAD_Pos                  (22U)
-#define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
-#define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
-#define USB_OTG_HCCHAR_DAD_1                    (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
-#define USB_OTG_HCCHAR_DAD_2                    (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
-#define USB_OTG_HCCHAR_DAD_3                    (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
-#define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
-#define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
-#define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
-#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)
-#define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)
-#define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA_Pos                (31U)
-#define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)
-#define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
-#define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCSPLT_PRTADDR_1                (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCSPLT_PRTADDR_2                (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCSPLT_PRTADDR_3                (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCSPLT_PRTADDR_4                (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
-
-#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)
-#define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
-#define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCSPLT_HUBADDR_1                (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCSPLT_HUBADDR_2                (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCSPLT_HUBADDR_3                (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCSPLT_HUBADDR_4                (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
-
-#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)
-#define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
-#define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)
-#define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
-#define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)
-#define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC_Pos                  (0U)
-#define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH_Pos                   (1U)
-#define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR_Pos                (2U)
-#define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
-#define USB_OTG_HCINT_STALL_Pos                 (3U)
-#define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK_Pos                   (4U)
-#define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK_Pos                   (5U)
-#define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET_Pos                  (6U)
-#define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR_Pos                 (7U)
-#define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR_Pos                 (8U)
-#define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR_Pos                 (9U)
-#define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR_Pos                 (10U)
-#define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC_Pos                (0U)
-#define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)
-#define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
-#define USB_OTG_DIEPINT_TOC_Pos                 (3U)
-#define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)
-#define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
-#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
-#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)
-#define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE_Pos                (7U)
-#define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
-#define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA_Pos                 (9U)
-#define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)
-#define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR_Pos                (12U)
-#define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
-#define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK_Pos                 (13U)
-#define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)
-#define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)
-#define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)
-#define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)
-#define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)
-#define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)
-#define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET_Pos               (6U)
-#define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)
-#define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)
-#define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)
-#define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)
-#define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)
-#define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)
-#define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)
-#define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)
-#define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)
-#define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)
-#define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
-#define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)
-#define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)
-#define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)
-#define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)
-#define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)
-#define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)
-#define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)
-#define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)
-#define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)
-#define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)
-#define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)
-#define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
-#define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL_Pos               (21U)
-#define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)
-#define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)
-#define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)
-#define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)
-#define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC_Pos                (0U)
-#define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)
-#define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
-#define USB_OTG_DOEPINT_STUP_Pos                (3U)
-#define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)
-#define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
-#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)
-#define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
-#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
-#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
-#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
-#define USB_OTG_DOEPINT_NYET_Pos                (14U)
-#define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
-#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
-#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)
-#define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)
-#define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)
-#define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)
-#define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)
-#define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
-
-/* Legacy define */
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_CHNUM_Pos                       (0U)
-#define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
-#define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
-#define USB_OTG_BCNT_Pos                        (4U)
-#define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
-#define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
-
-#define USB_OTG_DPID_Pos                        (15U)
-#define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
-#define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
-#define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
-#define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
-
-#define USB_OTG_PKTSTS_Pos                      (17U)
-#define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
-#define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
-#define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
-#define USB_OTG_PKTSTS_1                        (0x2UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00040000 */
-#define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
-#define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
-
-#define USB_OTG_EPNUM_Pos                       (0U)
-#define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_EPNUM_1                         (0x2UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
-
-#define USB_OTG_FRMNUM_Pos                      (21U)
-#define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
-#define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
-#define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
-#define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
-#define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
-#define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-- 
cgit v1.3.1


From 46106c6ef41e7a0c3cec261c32a2f183f05a65ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 Nov 2023 15:22:02 +0700
Subject: skip tuh_max3421_spi_cs_api() in hcd_init()

only call tuh_max3421_spi_cs_api() in SPI start/end transfer since
Arduino port use this to call begin/endTransaction()
---
 src/portable/analog/max3421/hcd_max3421.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 4665c1b06..65f87f7c6 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -417,7 +417,6 @@ bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
   tuh_max3421_int_api(rhport, false);
-  tuh_max3421_spi_cs_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
   TU_LOG2_INT(sizeof(max3421_data_t));
-- 
cgit v1.3.1


From 4b9320e40ea65ca023925d0a644b116b7066e06f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Nov 2023 22:22:13 +0700
Subject: fix race condition when dev0 is removed while enumerating

---
 src/host/usbh.c                                | 70 +++++++++++++-------------
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 16 +++---
 2 files changed, 44 insertions(+), 42 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 8d75c9726..fb4fbe3cb 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -55,16 +55,12 @@ typedef struct
   uint8_t rhport;
   uint8_t hub_addr;
   uint8_t hub_port;
-  uint8_t speed;
-
-  // enumeration is in progress, done when all interfaces are configured
-  volatile uint8_t enumerating;
 
-//  struct TU_ATTR_PACKED {
-//    uint8_t          speed       : 4; // packed speed to save footprint
-//    volatile uint8_t enumerating : 1;
-//    uint8_t TU_RESERVED : 3;
-//  };
+  struct TU_ATTR_PACKED {
+             uint8_t speed       : 4; // packed speed to save footprint
+    volatile uint8_t enumerating : 1; // enumeration is in progress, false if not connected or all interfaces are configured
+    uint8_t TU_RESERVED : 3;
+  };
 } usbh_dev0_t;
 
 typedef struct {
@@ -431,8 +427,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
     switch (event.event_id)
     {
       case HCD_EVENT_DEVICE_ATTACH:
-        // due to the shared _usbh_ctrl_buf, we must complete enumerating
-        // one device before enumerating another one.
+        // due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one.
+        // TODO better to have an separated queue for newly attached devices
         if ( _dev0.enumerating ) {
           TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
 
@@ -556,11 +552,13 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
   // EP0 with setup packet
   TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
 
-  // pre-check to help reducing mutex lock
-  TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-
+  // Check if device is still connected (enumerating for dev0)
   uint8_t const daddr = xfer->daddr;
+  if ( daddr == 0 && !_dev0.enumerating) return false;
+  if ( daddr != 0 && get_device(daddr)->connected == 0) return false;
 
+  // pre-check to help reducing mutex lock
+  TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
   (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
@@ -917,19 +915,23 @@ void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
   }
 }
 
-TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
-{
-  switch (event->event_id)
-  {
-//    case HCD_EVENT_DEVICE_REMOVE:
-//      // FIXME device remove from a hub need an HCD API for hcd to free up endpoint
-//      // mark device as removing to prevent further xfer before the event is processed in usbh task
-//      break;
+TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) {
+  switch (event->event_id) {
+    case HCD_EVENT_DEVICE_REMOVE:
+      // FIXME device remove from a hub need an HCD API for hcd to free up endpoint
+      // mark device as removing to prevent further xfer before the event is processed in usbh task
 
-    default:
-      osal_queue_send(_usbh_q, event, in_isr);
-    break;
+      // Check if dev0 is removed
+      if ((event->rhport == _dev0.rhport) && (event->connection.hub_addr == _dev0.hub_addr) &&
+          (event->connection.hub_port == _dev0.hub_port)) {
+        _dev0.enumerating = 0;
+      }
+      break;
+
+    default: break;
   }
+
+  osal_queue_send(_usbh_q, event, in_isr);
 }
 
 //--------------------------------------------------------------------+
@@ -1294,8 +1296,7 @@ static bool _parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configu
 static void enum_full_complete(void);
 
 // process device enumeration
-static void process_enumeration(tuh_xfer_t* xfer)
-{
+static void process_enumeration(tuh_xfer_t* xfer) {
   // Retry a few times with transfers in enumeration since device can be unstable when starting up
   enum {
     ATTEMPT_COUNT_MAX = 3,
@@ -1303,19 +1304,20 @@ static void process_enumeration(tuh_xfer_t* xfer)
   };
   static uint8_t failed_count = 0;
 
-  if (XFER_RESULT_SUCCESS != xfer->result)
-  {
+  if (XFER_RESULT_SUCCESS != xfer->result) {
     // retry if not reaching max attempt
-    if ( failed_count < ATTEMPT_COUNT_MAX )
-    {
+    bool retry = _dev0.enumerating && (failed_count < ATTEMPT_COUNT_MAX);
+    if ( retry ) {
       failed_count++;
       osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit
       TU_LOG1("Enumeration attempt %u\r\n", failed_count);
-      TU_ASSERT(tuh_control_xfer(xfer), );
-    }else
-    {
+      retry = tuh_control_xfer(xfer);
+    }
+
+    if (!retry) {
       enum_full_complete();
     }
+
     return;
   }
   failed_count = 0;
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 93bc1bf43..f4de3c51d 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -182,14 +182,6 @@ void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) {
   root_port_t *rport = PIO_USB_ROOT_PORT(root_id);
   uint32_t const ints = rport->ints;
 
-  if ( ints & PIO_USB_INTS_CONNECT_BITS ) {
-    hcd_event_device_attach(tu_rhport, true);
-  }
-
-  if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) {
-    hcd_event_device_remove(tu_rhport, true);
-  }
-
   if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete);
   }
@@ -202,6 +194,14 @@ void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) {
     handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error);
   }
 
+  if ( ints & PIO_USB_INTS_CONNECT_BITS ) {
+    hcd_event_device_attach(tu_rhport, true);
+  }
+
+  if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) {
+    hcd_event_device_remove(tu_rhport, true);
+  }
+
   // clear all
   rport->ints &= ~ints;
 }
-- 
cgit v1.3.1


From 9377fd6901dd9c7b5361a9ce5c01a99cc6761750 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Nov 2023 22:34:49 +0700
Subject: fix -Werror=null-dereference warning

---
 src/host/usbh.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index fb4fbe3cb..d8fff9905 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -554,8 +554,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
 
   // Check if device is still connected (enumerating for dev0)
   uint8_t const daddr = xfer->daddr;
-  if ( daddr == 0 && !_dev0.enumerating) return false;
-  if ( daddr != 0 && get_device(daddr)->connected == 0) return false;
+  if ( daddr == 0 ) {
+    if (!_dev0.enumerating) return false;
+  } else {
+    usbh_device_t const* dev = get_device(daddr);
+    if (dev && dev->connected == 0) return false;
+  }
 
   // pre-check to help reducing mutex lock
   TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-- 
cgit v1.3.1


From 8bac68db84ccbf4f9fbd0d6075b6a1b0253c081a Mon Sep 17 00:00:00 2001
From: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
Date: Wed, 11 Oct 2023 10:15:52 +0200
Subject: Add historical EP compatibility to bth class

---
 src/class/bth/bth_device.c | 2 +-
 src/class/bth/bth_device.h | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index c5c74d26a..be36e8c11 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -204,7 +204,7 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
         request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE)
     {
       // HCI command packet addressing for single function Primary Controllers
-      TU_VERIFY(request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0);
+      TU_VERIFY((CFG_TUD_BTH_HISTORICAL_COMPAT && request->bRequest == 0xe0) || (request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0));
     }
     else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
     {
diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h
index 921bd7a1a..c23e74bfb 100755
--- a/src/class/bth/bth_device.h
+++ b/src/class/bth/bth_device.h
@@ -39,6 +39,13 @@
 #ifndef CFG_TUD_BTH_DATA_EPSIZE
 #define CFG_TUD_BTH_DATA_EPSIZE      64
 #endif
+#ifndef CFG_TUD_BTH_HISTORICAL_COMPAT
+#define CFG_TUD_BTH_HISTORICAL_COMPAT 0
+#endif
+#ifndef CFG_TUD_BTH_ISO_ALT_COUNT
+// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.1
+#error You must tell the driver the number of ISO endpoints to use
+#endif
 
 typedef struct TU_ATTR_PACKED
 {
-- 
cgit v1.3.1


From b5b34e73d6cbce1a1d85999ef92712fb98a73a84 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 19 Nov 2023 16:10:16 +0100
Subject: Add dwc2 info of F429.

---
 src/portable/synopsys/dwc2/dwc2_info.md | 108 ++++++++++++++++----------------
 src/portable/synopsys/dwc2/dwc2_info.py |   2 +
 2 files changed, 56 insertions(+), 54 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
index 2d8ab067f..f298f6656 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.md
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -1,54 +1,54 @@
-|                             | BCM2711 (Pi4)   | EFM32GG FullSpeed   | ESP32-S2   | STM32F407 Fullspeed   | STM32F407 Highspeed   | STM32F411 Fullspeed   | STM32F412 Fullspeed   | STM32F723 Fullspeed   | STM32F723 HighSpeed   | STM32F767 Fullspeed   | STM32H743 Highspeed   | STM32L476 Fullspeed   | STM32U5A5 Highspeed   | GD32VF103 Fullspeed   | XMC4500    |
-|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
-| guid                        | 0x2708A000      | 0x00000000          | 0x00000000 | 0x00001200            | 0x00001100            | 0x00001200            | 0x00002000            | 0x00003000            | 0x00003100            | 0x00002000            | 0x00002300            | 0x00002000            | 0x00005000            | 0x00001000            | 0x00AEC000 |
-| gsnpsid                     | 0x4F54280A      | 0x4F54330A          | 0x4F54400A | 0x4F54281A            | 0x4F54281A            | 0x4F54281A            | 0x4F54320A            | 0x4F54330A            | 0x4F54330A            | 0x4F54320A            | 0x4F54330A            | 0x4F54310A            | 0x4F54411A            | 0x00000000            | 0x4F54292A |
-| ghwcfg1                     | 0x00000000      | 0x00000000          | 0x00000000 | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000 |
-| ghwcfg2                     | 0x228DDD50      | 0x228F5910          | 0x224DD930 | 0x229DCD20            | 0x229ED590            | 0x229DCD20            | 0x229ED520            | 0x229ED520            | 0x229FE1D0            | 0x229ED520            | 0x229FE190            | 0x229ED520            | 0x228FE052            | 0x00000000            | 0x228F5930 |
-| - op_mode                   | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 2                     | 0                     | 0          |
-| - arch                      | 2               | 2                   | 2          | 0                     | 2                     | 0                     | 0                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2          |
-| - point2point               | 0               | 0                   | 1          | 1                     | 0                     | 1                     | 1                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0                     | 1          |
-| - hs_phy_type               | 1               | 0                   | 0          | 0                     | 2                     | 0                     | 0                     | 0                     | 3                     | 0                     | 2                     | 0                     | 1                     | 0                     | 0          |
-| - fs_phy_type               | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
-| - num_dev_ep                | 7               | 6                   | 6          | 3                     | 5                     | 3                     | 5                     | 5                     | 8                     | 5                     | 8                     | 5                     | 8                     | 0                     | 6          |
-| - num_host_ch               | 7               | 13                  | 7          | 7                     | 11                    | 7                     | 11                    | 11                    | 15                    | 11                    | 15                    | 11                    | 15                    | 0                     | 13         |
-| - period_channel_support    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
-| - enable_dynamic_fifo       | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
-| - mul_cpu_int               | 0               | 0                   | 0          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
-| - reserved21                | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| - nperiod_tx_q_depth        | 2               | 2                   | 1          | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 0                     | 2          |
-| - host_period_tx_q_depth    | 2               | 2                   | 2          | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 0                     | 2          |
-| - dev_token_q_depth         | 8               | 8                   | 8          | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 0                     | 8          |
-| - otg_enable_ic_usb         | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| ghwcfg3                     | 0x0FF000E8      | 0x01F204E8          | 0x00C804B5 | 0x020001E8            | 0x03F403E8            | 0x020001E8            | 0x0200D1E8            | 0x0200D1E8            | 0x03EED2E8            | 0x0200D1E8            | 0x03B8D2E8            | 0x0200D1E8            | 0x03B882E8            | 0x00000000            | 0x027A01E5 |
-| - xfer_size_width           | 8               | 8                   | 5          | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 0                     | 5          |
-| - packet_size_width         | 6               | 6                   | 3          | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 0                     | 6          |
-| - otg_enable                | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
-| - i2c_enable                | 0               | 0                   | 0          | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0                     | 1          |
-| - vendor_ctrl_itf           | 0               | 0                   | 0          | 0                     | 1                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0          |
-| - optional_feature_removed  | 0               | 1                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| - synch_reset               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| - otg_adp_support           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
-| - otg_enable_hsic           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| - battery_charger_support   | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
-| - lpm_mode                  | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0          |
-| - total_fifo_size           | 4080            | 498                 | 200        | 512                   | 1012                  | 512                   | 512                   | 512                   | 1006                  | 512                   | 952                   | 512                   | 952                   | 0                     | 634        |
-| ghwcfg4                     | 0x1FF00020      | 0x1BF08030          | 0xD3F0A030 | 0x0FF08030            | 0x17F00030            | 0x0FF08030            | 0x17F08030            | 0x17F08030            | 0x23F00030            | 0x17F08030            | 0xE3F00030            | 0x17F08030            | 0xE2103E30            | 0x00000000            | 0xDBF08030 |
-| - num_dev_period_in_ep      | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| - power_optimized           | 0               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
-| - ahb_freq_min              | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
-| - hibernation               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| - reserved7                 | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 4                     | 0                     | 0          |
-| - service_interval_mode     | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
-| - ipg_isoc_en               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
-| - acg_enable                | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
-| - reserved13                | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
-| - utmi_phy_data_width       | 0               | 2                   | 2          | 2                     | 0                     | 2                     | 2                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 0                     | 2          |
-| - dev_ctrl_ep_num           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
-| - iddg_filter_enabled       | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
-| - vbus_valid_filter_enabled | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
-| - a_valid_filter_enabled    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
-| - b_valid_filter_enabled    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
-| - dedicated_fifos           | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
-| - num_dev_in_eps            | 15              | 13                  | 9          | 7                     | 11                    | 7                     | 11                    | 11                    | 1                     | 11                    | 1                     | 11                    | 1                     | 0                     | 13         |
-| - dma_desc_enable           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0          |
-| - dma_dynamic               | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1          |
+|                             | BCM2711 (Pi4)   | EFM32GG FullSpeed   | ESP32-S2   | STM32F407 Fullspeed   | STM32F407 Highspeed   | STM32F411 Fullspeed   | STM32F412 Fullspeed   | STM32F429 Fullspeed   | STM32F429 Highspeed   | STM32F723 Fullspeed   | STM32F723 HighSpeed   | STM32F767 Fullspeed   | STM32H743 Highspeed   | STM32L476 Fullspeed   | STM32U5A5 Highspeed   | GD32VF103 Fullspeed   | XMC4500    |
+|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
+| guid                        | 0x2708A000      | 0x00000000          | 0x00000000 | 0x00001200            | 0x00001100            | 0x00001200            | 0x00002000            | 0x00001200            | 0x00001100            | 0x00003000            | 0x00003100            | 0x00002000            | 0x00002300            | 0x00002000            | 0x00005000            | 0x00001000            | 0x00AEC000 |
+| gsnpsid                     | 0x4F54280A      | 0x4F54330A          | 0x4F54400A | 0x4F54281A            | 0x4F54281A            | 0x4F54281A            | 0x4F54320A            | 0x4F54281A            | 0x4F54281A            | 0x4F54330A            | 0x4F54330A            | 0x4F54320A            | 0x4F54330A            | 0x4F54310A            | 0x4F54411A            | 0x00000000            | 0x4F54292A |
+| ghwcfg1                     | 0x00000000      | 0x00000000          | 0x00000000 | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000 |
+| ghwcfg2                     | 0x228DDD50      | 0x228F5910          | 0x224DD930 | 0x229DCD20            | 0x229ED590            | 0x229DCD20            | 0x229ED520            | 0x229DCD20            | 0x229ED590            | 0x229ED520            | 0x229FE1D0            | 0x229ED520            | 0x229FE190            | 0x229ED520            | 0x228FE052            | 0x00000000            | 0x228F5930 |
+| - op_mode                   | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 2                     | 0                     | 0          |
+| - arch                      | 2               | 2                   | 2          | 0                     | 2                     | 0                     | 0                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2          |
+| - point2point               | 0               | 0                   | 1          | 1                     | 0                     | 1                     | 1                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0                     | 1          |
+| - hs_phy_type               | 1               | 0                   | 0          | 0                     | 2                     | 0                     | 0                     | 0                     | 2                     | 0                     | 3                     | 0                     | 2                     | 0                     | 1                     | 0                     | 0          |
+| - fs_phy_type               | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - num_dev_ep                | 7               | 6                   | 6          | 3                     | 5                     | 3                     | 5                     | 3                     | 5                     | 5                     | 8                     | 5                     | 8                     | 5                     | 8                     | 0                     | 6          |
+| - num_host_ch               | 7               | 13                  | 7          | 7                     | 11                    | 7                     | 11                    | 7                     | 11                    | 11                    | 15                    | 11                    | 15                    | 11                    | 15                    | 0                     | 13         |
+| - period_channel_support    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - enable_dynamic_fifo       | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - mul_cpu_int               | 0               | 0                   | 0          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
+| - reserved21                | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - nperiod_tx_q_depth        | 2               | 2                   | 1          | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 0                     | 2          |
+| - host_period_tx_q_depth    | 2               | 2                   | 2          | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 2                     | 0                     | 2          |
+| - dev_token_q_depth         | 8               | 8                   | 8          | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 0                     | 8          |
+| - otg_enable_ic_usb         | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| ghwcfg3                     | 0x0FF000E8      | 0x01F204E8          | 0x00C804B5 | 0x020001E8            | 0x03F403E8            | 0x020001E8            | 0x0200D1E8            | 0x020001E8            | 0x03F403E8            | 0x0200D1E8            | 0x03EED2E8            | 0x0200D1E8            | 0x03B8D2E8            | 0x0200D1E8            | 0x03B882E8            | 0x00000000            | 0x027A01E5 |
+| - xfer_size_width           | 8               | 8                   | 5          | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 8                     | 0                     | 5          |
+| - packet_size_width         | 6               | 6                   | 3          | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 6                     | 0                     | 6          |
+| - otg_enable                | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - i2c_enable                | 0               | 0                   | 0          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0                     | 1          |
+| - vendor_ctrl_itf           | 0               | 0                   | 0          | 0                     | 1                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0          |
+| - optional_feature_removed  | 0               | 1                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - synch_reset               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - otg_adp_support           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
+| - otg_enable_hsic           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - battery_charger_support   | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 0          |
+| - lpm_mode                  | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 1                     | 0                     | 0                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0          |
+| - total_fifo_size           | 4080            | 498                 | 200        | 512                   | 1012                  | 512                   | 512                   | 512                   | 1012                  | 512                   | 1006                  | 512                   | 952                   | 512                   | 952                   | 0                     | 634        |
+| ghwcfg4                     | 0x1FF00020      | 0x1BF08030          | 0xD3F0A030 | 0x0FF08030            | 0x17F00030            | 0x0FF08030            | 0x17F08030            | 0x0FF08030            | 0x17F00030            | 0x17F08030            | 0x23F00030            | 0x17F08030            | 0xE3F00030            | 0x17F08030            | 0xE2103E30            | 0x00000000            | 0xDBF08030 |
+| - num_dev_period_in_ep      | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - power_optimized           | 0               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - ahb_freq_min              | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - hibernation               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - reserved7                 | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 4                     | 0                     | 0          |
+| - service_interval_mode     | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - ipg_isoc_en               | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - acg_enable                | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - reserved13                | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 0          |
+| - utmi_phy_data_width       | 0               | 2                   | 2          | 2                     | 0                     | 2                     | 2                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 2                     | 0                     | 0                     | 2          |
+| - dev_ctrl_ep_num           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0          |
+| - iddg_filter_enabled       | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 1          |
+| - vbus_valid_filter_enabled | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - a_valid_filter_enabled    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - b_valid_filter_enabled    | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - dedicated_fifos           | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
+| - num_dev_in_eps            | 15              | 13                  | 9          | 7                     | 11                    | 7                     | 11                    | 7                     | 11                    | 11                    | 1                     | 11                    | 1                     | 11                    | 1                     | 0                     | 13         |
+| - dma_desc_enable           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0          |
+| - dma_dynamic               | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1          |
\ No newline at end of file
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
index 0af6c4c77..4bcdb4fe5 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.py
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -12,6 +12,8 @@ dwc2_reg_value = {
     'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
     'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
     'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
+    'STM32F429 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030],
+    'STM32F429 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030],
     'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
     'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030],
     'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030],
-- 
cgit v1.3.1


From 8af470e06d032d1b9731d817741318883c0b8fa0 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 19 Nov 2023 16:19:11 +0100
Subject: Fix CI

---
 src/portable/synopsys/dwc2/dwc2_info.md | 2 +-
 src/portable/synopsys/dwc2/dwc2_info.py | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
index f298f6656..d093502b0 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.md
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -51,4 +51,4 @@
 | - dedicated_fifos           | 1               | 1                   | 1          | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 1                     | 0                     | 0                     | 1          |
 | - num_dev_in_eps            | 15              | 13                  | 9          | 7                     | 11                    | 7                     | 11                    | 7                     | 11                    | 11                    | 1                     | 11                    | 1                     | 11                    | 1                     | 0                     | 13         |
 | - dma_desc_enable           | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1                     | 0                     | 0          |
-| - dma_dynamic               | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1          |
\ No newline at end of file
+| - dma_dynamic               | 0               | 0                   | 1          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 1                     | 0                     | 1                     | 0                     | 1          |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
index 4bcdb4fe5..03c095655 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.py
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -154,6 +154,7 @@ def render_md():
     # Write the Markdown table to a file
     with open('dwc2_info.md', 'w') as md_file:
         md_file.write(df.to_markdown())
+        md_file.write('\n')
 
 
 if __name__ == '__main__':
-- 
cgit v1.3.1


From 1f71625a32a77d5fe243f71f9e8be03c9bbc41d1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 20 Nov 2023 21:31:06 +0700
Subject: add tuh_max3421_reg_read(), tuh_max3421_reg_read() for application
 usage

added max3241 for feather m4 and tested
---
 hw/bsp/samd51/boards/feather_m4_express/board.h | 17 ++++++
 hw/bsp/samd51/family.c                          | 28 +++++++--
 src/portable/analog/max3421/hcd_max3421.c       | 78 +++++++++++++++----------
 3 files changed, 86 insertions(+), 37 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.h b/hw/bsp/samd51/boards/feather_m4_express/board.h
index 4629643fd..474163c06 100644
--- a/hw/bsp/samd51/boards/feather_m4_express/board.h
+++ b/hw/bsp/samd51/boards/feather_m4_express/board.h
@@ -31,6 +31,8 @@
  extern "C" {
 #endif
 
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
 // LED
 #define LED_PIN               23
 #define LED_STATE_ON          1
@@ -43,6 +45,21 @@
 #define UART_TX_PIN           (32 + 17)
 #define UART_RX_PIN           (32 + 16)
 
+// SPI for USB host shield
+#define MAX3421_SERCOM_ID       1  // SERCOM2
+#define MAX3421_SERCOM_FUNCTION 2  // function C
+
+#define MAX3421_SCK_PIN         _PINNUM(0, 17)
+#define MAX3421_MOSI_PIN        _PINNUM(1, 23)
+#define MAX3421_MISO_PIN        _PINNUM(1, 22)
+#define MAX3421_TX_PAD          2 // MOSI = PAD_3, SCK = PAD_1
+#define MAX3421_RX_PAD          2 // MISO = PAD_2
+
+#define MAX3421_CS_PIN          21 // D11
+
+#define MAX3421_INTR_PIN        20 // D10
+#define MAX3421_INTR_EIC_ID     4  // EIC4
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index bca18e1a2..2a2aee982 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -76,12 +76,18 @@ void USB_3_Handler(void) {
 // Implementation
 //--------------------------------------------------------------------+
 
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+
+// API to read MAX3421's register. Implemented by TinyUSB
+extern uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
+
+// API to write MAX3421's register. Implemented by TinyUSB
+extern bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
+
 #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
 #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler)
 
 static void max3421_init(void);
-
 #endif
 
 void board_init(void) {
@@ -136,11 +142,23 @@ void board_init(void) {
   gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
   gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
 
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
   max3421_init();
 #endif
 }
 
+void board_init_after_tusb(void) {
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+  // FeatherWing MAX3421E use MAX3421E's GPIO0 for VBUS enable
+  enum {
+    IOPINS1_ADDR  = 20u << 3, // 0xA0
+  };
+
+  uint8_t rhport = 1;
+  tuh_max3421_reg_write(rhport, IOPINS1_ADDR, 0x01, false);
+#endif
+}
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
@@ -182,7 +200,7 @@ uint32_t board_millis(void) {
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
 
 static void max3421_init(void) {
   //------------- SPI Init -------------//
@@ -262,7 +280,7 @@ static void max3421_init(void) {
 
   // Enable the SPI module
   sercom->SPI.CTRLA.bit.ENABLE = 1;
-  while (sercom->SPI.SYNCBUSY.bit.ENABLE);
+  while (sercom->SPI.SYNCBUSY.bit.ENABLE) {}
 
   //------------- External Interrupt -------------//
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 65f87f7c6..2abd74d51 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -54,6 +54,12 @@ enum {
   CPUCTL_ADDR   = 16u << 3, // 0x80
   PINCTL_ADDR   = 17u << 3, // 0x88
   REVISION_ADDR = 18u << 3, // 0x90
+  // 19 is not used
+  IOPINS1_ADDR  = 20u << 3, // 0xA0
+  IOPINS2_ADDR  = 21u << 3, // 0xA8
+  GPINIRQ_ADDR  = 22u << 3, // 0xB0
+  GPINIEN_ADDR  = 23u << 3, // 0xB8
+  GPINPOL_ADDR  = 24u << 3, // 0xC0
   HIRQ_ADDR     = 25u << 3, // 0xC8
   HIEN_ADDR     = 26u << 3, // 0xD0
   MODE_ADDR     = 27u << 3, // 0xD8
@@ -207,7 +213,9 @@ typedef struct {
 static max3421_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
-// API: SPI transfer with MAX3421E, must be implemented by application
+// API: SPI transfer with MAX3421E
+// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application
+// - reg_read(), reg_write(): is implemented by this driver, can be used by application
 //--------------------------------------------------------------------+
 
 // API to control MAX3421 SPI CS
@@ -220,11 +228,18 @@ extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint
 // API to enable/disable MAX3421 INTR pin interrupt
 extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
 
+// API to read MAX3421's register. Implemented by TinyUSB
+uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr);
+
+// API to write MAX3421's register. Implemented by TinyUSB
+bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr);
+
 //--------------------------------------------------------------------+
-// SPI Helper
+// SPI Commands and Helper
 //--------------------------------------------------------------------+
-static void handle_connect_irq(uint8_t rhport, bool in_isr);
-static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
+
+#define reg_read  tuh_max3421_reg_read
+#define reg_write tuh_max3421_reg_write
 
 static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
@@ -248,61 +263,60 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
   }
 }
 
-static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
-  uint8_t hirq;
-  reg |= CMDBYTE_WRITE;
+uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
+  uint8_t tx_buf[2] = {reg, 0};
+  uint8_t rx_buf[2] = {0, 0};
 
   max3421_spi_lock(rhport, in_isr);
-
-  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
-  _hcd_data.hirq = hirq;
-  tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
-
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
   max3421_spi_unlock(rhport, in_isr);
 
+  _hcd_data.hirq = rx_buf[0];
+  return ret ? rx_buf[1] : 0;
 }
 
-static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
-  uint8_t hirq;
-  uint8_t const reg = RCVVFIFO_ADDR;
+bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
+  uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
+  uint8_t rx_buf[2] = {0, 0};
 
   max3421_spi_lock(rhport, in_isr);
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
+  max3421_spi_unlock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
-  _hcd_data.hirq = hirq;
-  tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
+  // HIRQ register since we are in full-duplex mode
+  _hcd_data.hirq = rx_buf[0];
 
-  max3421_spi_unlock(rhport, in_isr);
+  return ret;
 }
 
-static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
-  uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
-  uint8_t rx_buf[2] = {0, 0};
+static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
+  uint8_t hirq;
+  reg |= CMDBYTE_WRITE;
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
 
   max3421_spi_unlock(rhport, in_isr);
 
-  // HIRQ register since we are in full-duplex mode
-  _hcd_data.hirq = rx_buf[0];
 }
 
-static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
-  uint8_t tx_buf[2] = {reg, 0};
-  uint8_t rx_buf[2] = {0, 0};
+static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
+  uint8_t hirq;
+  uint8_t const reg = RCVVFIFO_ADDR;
 
   max3421_spi_lock(rhport, in_isr);
 
-  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
 
   max3421_spi_unlock(rhport, in_isr);
-
-  _hcd_data.hirq = rx_buf[0];
-  return ret ? rx_buf[1] : 0;
 }
 
+//------------- register write helper -------------//
 static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
   reg_write(rhport, HIRQ_ADDR, data, in_isr);
   // HIRQ write 1 is clear
-- 
cgit v1.3.1


From aedc92f2d31af6209b00e8a5d7abbfec02ed979b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Nov 2023 11:25:55 +0700
Subject: fix typo in cdc line coding enum

---
 examples/host/cdc_msc_hid/src/tusb_config.h          |  2 +-
 examples/host/cdc_msc_hid_freertos/src/tusb_config.h |  2 +-
 src/class/cdc/cdc.h                                  | 20 +++++++++++---------
 src/class/cdc/cdc_host.h                             |  2 +-
 4 files changed, 14 insertions(+), 12 deletions(-)

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index c8e9138e3..a53000a11 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -118,7 +118,7 @@
 
 // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
 // bit rate = 115200, 1 stop bit, no parity, 8 bit data width
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
 
 
 #ifdef __cplusplus
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index 1bed9a9b3..ba23301ed 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -123,7 +123,7 @@
 
 // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
 // bit rate = 115200, 1 stop bit, no parity, 8 bit data width
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
 
 
 #ifdef __cplusplus
diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 4658e43af..deec32ae4 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -182,21 +182,23 @@ typedef enum
   CDC_REQUEST_MDLM_SEMANTIC_MODEL                          = 0x60,
 }cdc_management_request_t;
 
-enum
-{
+enum {
   CDC_CONTROL_LINE_STATE_DTR = 0x01,
   CDC_CONTROL_LINE_STATE_RTS = 0x02,
 };
 
-enum
-{
-  CDC_LINE_CONDING_STOP_BITS_1   = 0, // 1   bit
-  CDC_LINE_CONDING_STOP_BITS_1_5 = 1, // 1.5 bits
-  CDC_LINE_CONDING_STOP_BITS_2   = 2, // 2   bits
+enum {
+  CDC_LINE_CODING_STOP_BITS_1   = 0, // 1   bit
+  CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits
+  CDC_LINE_CODING_STOP_BITS_2   = 2, // 2   bits
 };
 
-enum
-{
+// TODO Backward compatible for typos. Maybe removed in the future release
+#define CDC_LINE_CONDING_STOP_BITS_1   CDC_LINE_CODING_STOP_BITS_1
+#define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5
+#define CDC_LINE_CONDING_STOP_BITS_2   CDC_LINE_CODING_STOP_BITS_2
+
+enum {
   CDC_LINE_CODING_PARITY_NONE  = 0,
   CDC_LINE_CODING_PARITY_ODD   = 1,
   CDC_LINE_CODING_PARITY_EVEN  = 2,
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 19552f1ee..9e5edd94e 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -44,7 +44,7 @@
 
 // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
 //#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
 //#endif
 
 // RX FIFO size
-- 
cgit v1.3.1


From 025ffa200c5508c23e76316045792af4f7728da5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Nov 2023 17:36:52 +0700
Subject: add spec version to dwc2 info

---
 src/portable/synopsys/dwc2/dwc2_info.md  |   1 +
 src/portable/synopsys/dwc2/dwc2_info.py  |  14 +-
 src/portable/synopsys/dwc2/hwcfg_list.md | 777 -------------------------------
 3 files changed, 12 insertions(+), 780 deletions(-)
 delete mode 100644 src/portable/synopsys/dwc2/hwcfg_list.md

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md
index d093502b0..8690a0755 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.md
+++ b/src/portable/synopsys/dwc2/dwc2_info.md
@@ -2,6 +2,7 @@
 |:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------|
 | guid                        | 0x2708A000      | 0x00000000          | 0x00000000 | 0x00001200            | 0x00001100            | 0x00001200            | 0x00002000            | 0x00001200            | 0x00001100            | 0x00003000            | 0x00003100            | 0x00002000            | 0x00002300            | 0x00002000            | 0x00005000            | 0x00001000            | 0x00AEC000 |
 | gsnpsid                     | 0x4F54280A      | 0x4F54330A          | 0x4F54400A | 0x4F54281A            | 0x4F54281A            | 0x4F54281A            | 0x4F54320A            | 0x4F54281A            | 0x4F54281A            | 0x4F54330A            | 0x4F54330A            | 0x4F54320A            | 0x4F54330A            | 0x4F54310A            | 0x4F54411A            | 0x00000000            | 0x4F54292A |
+| - specs version             | 2.80a           | 3.30a               | 4.00a      | 2.81a                 | 2.81a                 | 2.81a                 | 3.20a                 | 2.81a                 | 2.81a                 | 3.30a                 | 3.30a                 | 3.20a                 | 3.30a                 | 3.10a                 | 4.11a                 | 0.00W                 | 2.92a      |
 | ghwcfg1                     | 0x00000000      | 0x00000000          | 0x00000000 | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000            | 0x00000000 |
 | ghwcfg2                     | 0x228DDD50      | 0x228F5910          | 0x224DD930 | 0x229DCD20            | 0x229ED590            | 0x229DCD20            | 0x229ED520            | 0x229DCD20            | 0x229ED590            | 0x229ED520            | 0x229FE1D0            | 0x229ED520            | 0x229FE190            | 0x229ED520            | 0x228FE052            | 0x00000000            | 0x228F5930 |
 | - op_mode                   | 0               | 0                   | 0          | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 0                     | 2                     | 0                     | 0          |
diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py
index 03c095655..55bec3d23 100644
--- a/src/portable/synopsys/dwc2/dwc2_info.py
+++ b/src/portable/synopsys/dwc2/dwc2_info.py
@@ -36,6 +36,7 @@ dwc2_reg_value = {
 #     },
 dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()}
 
+
 class GHWCFG2(ctypes.LittleEndianStructure):
     _fields_ = [
         ("op_mode", ctypes.c_uint32, 3),
@@ -130,13 +131,20 @@ def render_md():
     # Create an empty list to hold the dictionaries
     dwc2_info_list = []
 
-    #Iterate over the dwc2_info dictionary and extract fields
+    # Iterate over the dwc2_info dictionary and extract fields
     for device, reg_values in dwc2_info.items():
         entry_dict = {"Device": device}
         for r_name, r_value in reg_values.items():
             entry_dict[r_name] = f"0x{r_value:08X}"
-            # Print bit-field values
-            if r_name.upper() in globals():
+
+            if r_name == 'gsnpsid':
+                # Get dwc2 specs version
+                major = ((r_value >> 8) >> 4) & 0x0F
+                minor = (r_value >> 4) & 0xFF
+                patch = chr((r_value & 0x0F) + ord('a') - 0xA)
+                entry_dict[f' - specs version'] = f"{major:X}.{minor:02X}{patch}"
+            elif r_name.upper() in globals():
+                # Get bit-field values which exist as ctypes structures
                 class_name = globals()[r_name.upper()]
                 ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little'))
                 for field_name, field_type, _ in class_name._fields_:
diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md
deleted file mode 100644
index b5590da00..000000000
--- a/src/portable/synopsys/dwc2/hwcfg_list.md
+++ /dev/null
@@ -1,777 +0,0 @@
-# DWC2 Hardware Configuration Registers
-
-## Broadcom BCM2711 (Pi4)
-
-dwc2->guid = 2708A000
-dwc2->gsnpsid = 4F54280A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 228DDD50
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 1
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 7
-hw_cfg2->num_host_ch = 7
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = FF000E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 4080
-
-dwc2->ghwcfg4 = 1FF00020
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 0
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 15
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## EFM32GG FS
-
-dwc2->guid = 0
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 228F5910
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 6
-hw_cfg2->num_host_ch = 13
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 1F204E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 1
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 498
-
-dwc2->ghwcfg4 = 1BF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 13
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## ESP32-S2 Fullspeed
-
-dwc2->guid = 0
-dwc2->gsnpsid = 4F54400A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 224DD930
-hw_cfg2->op_mode = 2
-hw_cfg2->arch = 3
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 1
-hw_cfg2->fs_phy_type = 2
-hw_cfg2->num_dev_ep = 6
-hw_cfg2->num_host_ch = 9
-hw_cfg2->period_channel_support = 0
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 1
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 22
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = C804B5
-hw_cfg3->xfer_size_width = 10
-hw_cfg3->packet_size_width = 5
-hw_cfg3->otg_enable = 0
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 1
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 23130
-
-dwc2->ghwcfg4 = D3F0A030
-hw_cfg4->num_dev_period_in_ep = 10
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 0
-hw_cfg4->hibernation = 1
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 1
-hw_cfg4->acg_enable = 1
-hw_cfg4->utmi_phy_data_width = 1
-hw_cfg4->dev_ctrl_ep_num = 10
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 0
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 0
-hw_cfg4->dedicated_fifos = 0
-hw_cfg4->num_dev_in_eps = 13
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 1
-
-## STM32F407 and STM32F207
-
-STM32F407 and STM32F207 are exactly the same
-
-### STM32F407 Fullspeed
-
-dwc2->guid = 1200
-dwc2->gsnpsid = 4F54281A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229DCD20
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 3
-hw_cfg2->num_host_ch = 7
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 20001E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = FF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 7
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-### STM32F407 Highspeed
-
-dwc2->guid = 1100
-dwc2->gsnpsid = 4F54281A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED590
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 2
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 3F403E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 1012
-
-dwc2->ghwcfg4 = 17F00030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F411 Fullspeed
-
-dwc2->guid = 1200
-dwc2->gsnpsid = 4F54281A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229DCD20
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 3
-hw_cfg2->num_host_ch = 7
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 20001E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = FF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 7
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F412 FS
-
-dwc2->guid = 2000
-dwc2->gsnpsid = 4F54320A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F723
-
-### STM32F723 HighSpeed
-
-dwc2->guid = 3100
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229FE1D0
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 3
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 8
-hw_cfg2->num_host_ch = 15
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 3EED2E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 1006
-
-dwc2->ghwcfg4 = 23F00030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 1
-hw_cfg4->dma_desc_enable = 1
-hw_cfg4->dma_dynamic = 0
-
-### STM32F723 Fullspeed
-
-dwc2->guid = 3000
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32F767 FS
-
-dwc2->guid = 2000
-dwc2->gsnpsid = 4F54320A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## STM32H743 (both cores HS)
-
-dwc2->guid = 2300
-dwc2->gsnpsid = 4F54330A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229FE190
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 2
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 8
-hw_cfg2->num_host_ch = 15
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 3B8D2E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 1
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 952
-
-dwc2->ghwcfg4 = E3F00030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 1
-hw_cfg4->dma_desc_enable = 1
-hw_cfg4->dma_dynamic = 1
-
-## STM32L476 FS
-
-dwc2->guid = 2000
-dwc2->gsnpsid = 4F54310A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 229ED520
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 5
-hw_cfg2->num_host_ch = 11
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 1
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 200D1E8
-hw_cfg3->xfer_size_width = 8
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 1
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 1
-hw_cfg3->lpm_mode = 1
-hw_cfg3->total_fifo_size = 512
-
-dwc2->ghwcfg4 = 17F08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 11
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## GD32VF103 Fullspeed
-
-dwc2->guid = 1000
-dwc2->gsnpsid = 0
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 0
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 0
-hw_cfg2->point2point = 0
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 0
-hw_cfg2->num_dev_ep = 0
-hw_cfg2->num_host_ch = 0
-hw_cfg2->period_channel_support = 0
-hw_cfg2->enable_dynamic_fifo = 0
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 0
-hw_cfg2->host_period_tx_q_depth = 0
-hw_cfg2->dev_token_q_depth = 0
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 0
-hw_cfg3->xfer_size_width = 0
-hw_cfg3->packet_size_width = 0
-hw_cfg3->otg_enable = 0
-hw_cfg3->i2c_enable = 0
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 0
-
-dwc2->ghwcfg4 = 0
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 0
-hw_cfg4->ahb_freq_min = 0
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 0
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 0
-hw_cfg4->vbus_valid_filter_enabled = 0
-hw_cfg4->a_valid_filter_enabled = 0
-hw_cfg4->b_valid_filter_enabled = 0
-hw_cfg4->dedicated_fifos = 0
-hw_cfg4->num_dev_in_eps = 0
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 0
-
-## XMC4500
-
-dwc2->guid = AEC000
-dwc2->gsnpsid = 4F54292A
-dwc2->ghwcfg1 = 0
-
-dwc2->ghwcfg2 = 228F5930
-hw_cfg2->op_mode = 0
-hw_cfg2->arch = 2
-hw_cfg2->point2point = 1
-hw_cfg2->hs_phy_type = 0
-hw_cfg2->fs_phy_type = 1
-hw_cfg2->num_dev_ep = 6
-hw_cfg2->num_host_ch = 13
-hw_cfg2->period_channel_support = 1
-hw_cfg2->enable_dynamic_fifo = 1
-hw_cfg2->mul_cpu_int = 0
-hw_cfg2->nperiod_tx_q_depth = 2
-hw_cfg2->host_period_tx_q_depth = 2
-hw_cfg2->dev_token_q_depth = 8
-hw_cfg2->otg_enable_ic_usb = 0
-
-dwc2->ghwcfg3 = 27A01E5
-hw_cfg3->xfer_size_width = 5
-hw_cfg3->packet_size_width = 6
-hw_cfg3->otg_enable = 1
-hw_cfg3->i2c_enable = 1
-hw_cfg3->vendor_ctrl_itf = 0
-hw_cfg3->optional_feature_removed = 0
-hw_cfg3->synch_reset = 0
-hw_cfg3->otg_adp_support = 0
-hw_cfg3->otg_enable_hsic = 0
-hw_cfg3->battery_charger_support = 0
-hw_cfg3->lpm_mode = 0
-hw_cfg3->total_fifo_size = 634
-
-dwc2->ghwcfg4 = DBF08030
-hw_cfg4->num_dev_period_in_ep = 0
-hw_cfg4->power_optimized = 1
-hw_cfg4->ahb_freq_min = 1
-hw_cfg4->hibernation = 0
-hw_cfg4->service_interval_mode = 0
-hw_cfg4->ipg_isoc_en = 0
-hw_cfg4->acg_enable = 0
-hw_cfg4->utmi_phy_data_width = 2
-hw_cfg4->dev_ctrl_ep_num = 0
-hw_cfg4->iddg_filter_enabled = 1
-hw_cfg4->vbus_valid_filter_enabled = 1
-hw_cfg4->a_valid_filter_enabled = 1
-hw_cfg4->b_valid_filter_enabled = 1
-hw_cfg4->dedicated_fifos = 1
-hw_cfg4->num_dev_in_eps = 13
-hw_cfg4->dma_desc_enable = 0
-hw_cfg4->dma_dynamic = 1
-- 
cgit v1.3.1


From 01f22a9e25c9581c1a38559737a7ca7d1fc22c15 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Nov 2023 22:50:10 +0700
Subject: fix h7 running on fullspeed phy has issue with WFI if not disable
 ULPI clock

---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 2070c3943..dd78ccd06 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -145,6 +145,22 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   if (hs_phy_type == HS_PHY_TYPE_NONE) {
     // Enable on-chip FS PHY
     dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+
+    // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
+    // H7 running on full-speed phy need to disable ULPI clock in sleep mode.
+    // Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS.
+    // Note: there may be other family that is affected by this, but only H7 is tested so far
+    #if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN)
+    if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) {
+      RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN;
+    }
+    #endif
+
+    #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB1OTGHSULPILPEN)
+    if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) {
+      RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN;
+    }
+    #endif
   } else {
 #if CFG_TUSB_MCU != OPT_MCU_STM32U5
     // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
-- 
cgit v1.3.1


From 68894398af9e8a096c700b7a4e8c127e53a2d6bc Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@redyak.com.au>
Date: Wed, 1 Nov 2023 15:45:44 +1100
Subject: Add optional hooks for DCD and HCD events

These are intended to allow bare metal platforms with one-shot scheduling
capabilities to schedule the TinyUSB task handlers whenever they know there is
work for them to do.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
---
 src/device/usbd.c | 15 +++++++++++----
 src/host/usbh.c   |  2 ++
 src/tusb_option.h | 12 ++++++++++++
 3 files changed, 25 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 50941c46f..2b6d07a96 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1079,6 +1079,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 //--------------------------------------------------------------------+
 TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
 {
+  bool send = false;
   switch (event->event_id)
   {
     case DCD_EVENT_UNPLUGGED:
@@ -1086,7 +1087,7 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       _usbd_dev.addressed  = 0;
       _usbd_dev.cfg_num    = 0;
       _usbd_dev.suspended  = 0;
-      osal_queue_send(_usbd_q, event, in_isr);
+      send = true;
     break;
 
     case DCD_EVENT_SUSPEND:
@@ -1097,7 +1098,7 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       if ( _usbd_dev.connected )
       {
         _usbd_dev.suspended = 1;
-        osal_queue_send(_usbd_q, event, in_isr);
+        send = true;
       }
     break;
 
@@ -1106,7 +1107,7 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       if ( _usbd_dev.connected )
       {
         _usbd_dev.suspended = 0;
-        osal_queue_send(_usbd_q, event, in_isr);
+        send = true;
       }
     break;
 
@@ -1129,15 +1130,21 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
 
         dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME };
         osal_queue_send(_usbd_q, &event_resume, in_isr);
+        CFG_TUD_EVENT_HOOK(&event_resume, in_isr);
       }
 
       // skip osal queue for SOF in usbd task
     break;
 
     default:
-      osal_queue_send(_usbd_q, event, in_isr);
+      send = true;
     break;
   }
+
+  if (send) {
+      osal_queue_send(_usbd_q, event, in_isr);
+      CFG_TUD_EVENT_HOOK(event, in_isr);
+  }
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index d8fff9905..2fdc8216d 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -780,6 +780,7 @@ void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
   event.func_call.param = param;
 
   osal_queue_send(_usbh_q, &event, in_isr);
+  CFG_TUH_EVENT_HOOK(event, in_isr);
 }
 
 //--------------------------------------------------------------------+
@@ -936,6 +937,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
   }
 
   osal_queue_send(_usbh_q, event, in_isr);
+  CFG_TUH_EVENT_HOOK(event, in_isr);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a29eb8a3a..aedc02dbc 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -485,6 +485,18 @@
 #define tuc_int_handler(_p)
 #endif
 
+//--------------------------------------------------------------------+
+// Optional event hook functions for platform integration (defaults)
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUD_EVENT_HOOK
+#define CFG_TUD_EVENT_HOOK(EVENT, IN_ISR)
+#endif
+
+#ifndef CFG_TUH_EVENT_HOOK
+#define CFG_TUH_EVENT_HOOK(EVENT, IN_ISR)
+#endif
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------
-- 
cgit v1.3.1


From 54356a719e3968702d86346ec6305679ebd9dd0f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 23 Nov 2023 17:53:17 +0700
Subject: minor-update

---
 hw/bsp/board.c                      | 20 ++++++++----
 hw/bsp/family_support.cmake         |  5 +--
 hw/bsp/nrf/family.cmake             |  4 +--
 hw/bsp/nrf/family.mk                |  3 ++
 hw/bsp/stm32h7/family.cmake         |  4 +--
 src/osal/osal_none.h                | 64 ++++++++++++++-----------------------
 tools/cmake/toolchain/arm_gcc.cmake |  2 +-
 7 files changed, 47 insertions(+), 55 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 562792625..23b4b6628 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -44,13 +44,12 @@
 
 // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
 #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM)
-
 #include "SEGGER_RTT.h"
 
-TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) {
+TU_ATTR_USED int sys_write(int fhdl, const char *buf, size_t count) {
   (void) fhdl;
   SEGGER_RTT_Write(0, (const char *) buf, (int) count);
-  return count;
+  return (int) count;
 }
 
 TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) {
@@ -63,10 +62,9 @@ TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) {
 
 #elif defined(LOGGER_SWO)
 // Logging with SWO for ARM Cortex
-
 #include "board_mcu.h"
 
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
+TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) {
   (void) fhdl;
   uint8_t const* buf8 = (uint8_t const*) buf;
 
@@ -87,7 +85,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
 #else
 
 // Default logging with on-board UART
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
+TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) {
   (void) fhdl;
   return board_uart_write(buf, (int) count);
 }
@@ -100,6 +98,16 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
 
 #endif
 
+//TU_ATTR_USED int _close(int fhdl) {
+//  (void) fhdl;
+//  return 0;
+//}
+
+//TU_ATTR_USED int _fstat(int file, struct stat *st) {
+//  memset(st, 0, sizeof(*st));
+//  st->st_mode = S_IFCHR;
+//}
+
 int board_getchar(void) {
   char c;
   return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index eec42160e..930237fea 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -201,6 +201,9 @@ function(family_configure_common TARGET RTOS)
   # Generate linker map file
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     target_link_options(${TARGET} PUBLIC "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map")
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+      target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
+    endif ()
   endif()
 
   # ETM Trace option
@@ -289,13 +292,11 @@ function(family_configure_device_example TARGET RTOS)
   family_configure_example(${TARGET} ${RTOS})
 endfunction()
 
-
 # Configure host example with RTOS
 function(family_configure_host_example TARGET RTOS)
   family_configure_example(${TARGET} ${RTOS})
 endfunction()
 
-
 # Configure host + device example with RTOS
 function(family_configure_dual_usb_example TARGET RTOS)
   family_configure_example(${TARGET} ${RTOS})
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 99d9ac6dd..8cee2b433 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -84,9 +84,7 @@ function(add_board_target BOARD_TARGET)
         # linker file
         "LINKER:--script=${LD_FILE_GNU}"
         -L${NRFX_DIR}/mdk
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
+        --specs=nosys.specs --specs=nano.specs
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
       target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index df22477df..29802dc37 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -12,6 +12,9 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_NRF5X \
   -DCONFIG_GPIO_AS_PINRESET
 
+#CFLAGS += -nostdlib
+#CFLAGS += -D__START=main
+
 # suppress warning caused by vendor mcu driver
 CFLAGS += \
   -Wno-error=undef \
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index c08857a50..2d6ec76c8 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -66,9 +66,7 @@ function(add_board_target BOARD_TARGET)
       target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--script=${LD_FILE_GNU}"
         -nostartfiles
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
+        --specs=nosys.specs --specs=nano.specs
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
       target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 76e77c25d..a07d39828 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -24,11 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_NONE_H_
-#define _TUSB_OSAL_NONE_H_
+#ifndef TUSB_OSAL_NONE_H_
+#define TUSB_OSAL_NONE_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
@@ -43,39 +43,34 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec);
 //--------------------------------------------------------------------+
 // Binary Semaphore API
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   volatile uint16_t count;
-}osal_semaphore_def_t;
+} osal_semaphore_def_t;
 
 typedef osal_semaphore_def_t* osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
   semdef->count = 0;
   return semdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   (void) in_isr;
   sem_hdl->count++;
   return true;
 }
 
 // TODO blocking for now
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   (void) msec;
 
-  while (sem_hdl->count == 0) { }
+  while (sem_hdl->count == 0) {}
   sem_hdl->count--;
 
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
   sem_hdl->count = 0;
 }
 
@@ -90,19 +85,16 @@ typedef osal_semaphore_t osal_mutex_t;
 // Note: multiple cores MCUs usually do provide IPC API for mutex
 // or we can use std atomic function
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   mdef->count = 1;
   return mdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return osal_semaphore_post(mutex_hdl, false);
 }
 
@@ -119,11 +111,10 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 //--------------------------------------------------------------------+
 #include "common/tusb_fifo.h"
 
-typedef struct
-{
-  void (*interrupt_set)(bool);
+typedef struct {
+  void (* interrupt_set)(bool);
   tu_fifo_t ff;
-}osal_queue_def_t;
+} osal_queue_def_t;
 
 typedef osal_queue_def_t* osal_queue_t;
 
@@ -136,27 +127,23 @@ typedef osal_queue_def_t* osal_queue_t;
   }
 
 // lock queue by disable USB interrupt
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl) {
   // disable dcd/hcd interrupt
   qhdl->interrupt_set(false);
 }
 
 // unlock queue
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl) {
   // enable dcd/hcd interrupt
   qhdl->interrupt_set(true);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   tu_fifo_clear(&qdef->ff);
   return (osal_queue_t) qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   (void) msec; // not used, always behave as msec = 0
 
   _osal_q_lock(qhdl);
@@ -166,8 +153,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) {
   if (!in_isr) {
     _osal_q_lock(qhdl);
   }
@@ -179,19 +165,17 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
   }
 
   TU_ASSERT(success);
-
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   // Skip queue lock/unlock since this function is primarily called
   // with interrupt disabled before going into low power mode
   return tu_fifo_empty(&qhdl->ff);
 }
 
 #ifdef __cplusplus
- }
+}
 #endif
 
-#endif /* _TUSB_OSAL_NONE_H_ */
+#endif
diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake
index cefa9d2ce..7680d75ab 100644
--- a/tools/cmake/toolchain/arm_gcc.cmake
+++ b/tools/cmake/toolchain/arm_gcc.cmake
@@ -29,7 +29,7 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS
   -fno-strict-aliasing
   )
 
-set(TOOLCHAIN_EXE_LINKER_FLAGS
+list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
   -Wl,--print-memory-usage
   -Wl,--gc-sections
   -Wl,--cref
-- 
cgit v1.3.1


From 6e5c7f43906bac8ab47642e56c153297b83f3679 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Nov 2023 16:08:06 +0700
Subject: rename to CFG_TUD_BTH_HISTORICAL_COMPATIBLE, move
 CFG_TUD_BTH_ISO_ALT_COUNT to tusb_option.h and mandatory for BTH driver

---
 src/class/bth/bth_device.c |  4 +++-
 src/class/bth/bth_device.h | 12 ++++++------
 src/device/usbd.h          |  4 ----
 src/tusb_option.h          | 13 +++++++++----
 4 files changed, 18 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index be36e8c11..f145e2ead 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -204,7 +204,9 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
         request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE)
     {
       // HCI command packet addressing for single function Primary Controllers
-      TU_VERIFY((CFG_TUD_BTH_HISTORICAL_COMPAT && request->bRequest == 0xe0) || (request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0));
+      // also compatible with historical mode if enabled
+      TU_VERIFY((request->bRequest == 0 && request->wValue == 0 && request->wIndex == 0) ||
+                (CFG_TUD_BTH_HISTORICAL_COMPATIBLE && request->bRequest == 0xe0));
     }
     else if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
     {
diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h
index c23e74bfb..e782c532b 100755
--- a/src/class/bth/bth_device.h
+++ b/src/class/bth/bth_device.h
@@ -36,15 +36,15 @@
 #ifndef CFG_TUD_BTH_EVENT_EPSIZE
 #define CFG_TUD_BTH_EVENT_EPSIZE     16
 #endif
+
 #ifndef CFG_TUD_BTH_DATA_EPSIZE
 #define CFG_TUD_BTH_DATA_EPSIZE      64
 #endif
-#ifndef CFG_TUD_BTH_HISTORICAL_COMPAT
-#define CFG_TUD_BTH_HISTORICAL_COMPAT 0
-#endif
-#ifndef CFG_TUD_BTH_ISO_ALT_COUNT
-// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.1
-#error You must tell the driver the number of ISO endpoints to use
+
+// Allow BTH class to work in historically compatibility mode where the bRequest is always 0xe0.
+// See Bluetooth Core v5.3, Vol. 4, Part B, Section 2.2
+#ifndef CFG_TUD_BTH_HISTORICAL_COMPATIBLE
+#define CFG_TUD_BTH_HISTORICAL_COMPATIBLE 0
 #endif
 
 typedef struct TU_ATTR_PACKED
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 93a2033c4..e14e3d6de 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -771,10 +771,6 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 #define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER  0x01
 #define TUD_BT_PROTOCOL_AMP_CONTROLLER      0x02
 
-#ifndef CFG_TUD_BTH_ISO_ALT_COUNT
-#define CFG_TUD_BTH_ISO_ALT_COUNT 0
-#endif
-
 // Length of template descriptor: 38 bytes + number of ISO alternatives * 23
 #define TUD_BTH_DESC_LEN (8 + 9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7))
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index b8509a069..7920fbf35 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -342,6 +342,15 @@
   #define CFG_TUD_INTERFACE_MAX   16
 #endif
 
+//------------- Device Class Driver -------------//
+#ifndef CFG_TUD_BTH
+  #define CFG_TUD_BTH             0
+#endif
+
+#if CFG_TUD_BTH && !defined(CFG_TUD_BTH_ISO_ALT_COUNT)
+#error CFG_TUD_BTH_ISO_ALT_COUNT must be defined to tell Bluetooth driver the number of ISO endpoints to use
+#endif
+
 #ifndef CFG_TUD_CDC
   #define CFG_TUD_CDC             0
 #endif
@@ -382,10 +391,6 @@
   #define CFG_TUD_DFU             0
 #endif
 
-#ifndef CFG_TUD_BTH
-  #define CFG_TUD_BTH             0
-#endif
-
 #ifndef CFG_TUD_ECM_RNDIS
   #ifdef CFG_TUD_NET
     #warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS"
-- 
cgit v1.3.1


From 188fbd8ed9b5e0f5cc3ddb5e89f7afd421fc7c06 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Nov 2023 18:21:24 +0700
Subject: add optional event hook callback tud_event_hook_cb() and
 tuh_event_hook_cb()

---
 src/device/usbd.c | 83 +++++++++++++++++++++++--------------------------------
 src/device/usbd.h |  3 ++
 src/host/usbh.c   | 18 ++++++------
 src/host/usbh.h   |  5 +++-
 src/tusb_option.h | 12 --------
 5 files changed, 52 insertions(+), 69 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 2b6d07a96..59466b42e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -242,22 +242,17 @@ tu_static uint8_t _app_driver_count = 0;
 
 // virtually joins built-in and application drivers together.
 // Application is positioned first to allow overwriting built-in ones.
-static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
-{
+TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8_t drvid) {
   usbd_class_driver_t const * driver = NULL;
-
   if ( drvid < _app_driver_count ) {
     // Application drivers
     driver = &_app_driver[drvid];
   } else if ( drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0 ){
     driver = &_usbd_driver[drvid - _app_driver_count];
   }
-
   return driver;
 }
 
-
-
 //--------------------------------------------------------------------+
 // DCD Event
 //--------------------------------------------------------------------+
@@ -278,6 +273,11 @@ tu_static osal_queue_t _usbd_q;
   #define _usbd_mutex   NULL
 #endif
 
+TU_ATTR_ALWAYS_INLINE static inline bool queue_event(dcd_event_t const * event, bool in_isr) {
+  bool ret = osal_queue_send(_usbd_q, event, in_isr);
+  if (tud_event_hook_cb) tud_event_hook_cb(event->rhport, event->event_id, in_isr);
+  return ret;
+}
 
 //--------------------------------------------------------------------+
 // Prototypes
@@ -374,8 +374,7 @@ bool tud_connect(void)
 //--------------------------------------------------------------------+
 // USBD Task
 //--------------------------------------------------------------------+
-bool tud_inited(void)
-{
+bool tud_inited(void) {
   return _usbd_rhport != RHPORT_INVALID;
 }
 
@@ -1077,73 +1076,64 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 //--------------------------------------------------------------------+
 // DCD Event Handler
 //--------------------------------------------------------------------+
-TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
-{
+TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) {
   bool send = false;
-  switch (event->event_id)
-  {
+  switch (event->event_id) {
     case DCD_EVENT_UNPLUGGED:
-      _usbd_dev.connected  = 0;
-      _usbd_dev.addressed  = 0;
-      _usbd_dev.cfg_num    = 0;
-      _usbd_dev.suspended  = 0;
+      _usbd_dev.connected = 0;
+      _usbd_dev.addressed = 0;
+      _usbd_dev.cfg_num = 0;
+      _usbd_dev.suspended = 0;
       send = true;
-    break;
+      break;
 
     case DCD_EVENT_SUSPEND:
       // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
       // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ).
       // In addition, some MCUs such as SAMD or boards that haven no VBUS detection cannot distinguish
       // suspended vs disconnected. We will skip handling SUSPEND/RESUME event if not currently connected
-      if ( _usbd_dev.connected )
-      {
+      if (_usbd_dev.connected) {
         _usbd_dev.suspended = 1;
         send = true;
       }
-    break;
+      break;
 
     case DCD_EVENT_RESUME:
       // skip event if not connected (especially required for SAMD)
-      if ( _usbd_dev.connected )
-      {
+      if (_usbd_dev.connected) {
         _usbd_dev.suspended = 0;
         send = true;
       }
-    break;
+      break;
 
     case DCD_EVENT_SOF:
-      // SOF driver handler in ISR context
-      for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
-      {
-        usbd_class_driver_t const * driver = get_driver(i);
-        if (driver && driver->sof)
-        {
-          driver->sof(event->rhport, event->sof.frame_count);
-        }
-      }
-
       // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
       // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
-      if ( _usbd_dev.suspended )
-      {
+      if (_usbd_dev.suspended) {
         _usbd_dev.suspended = 0;
 
-        dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME };
-        osal_queue_send(_usbd_q, &event_resume, in_isr);
-        CFG_TUD_EVENT_HOOK(&event_resume, in_isr);
+        dcd_event_t const event_resume = {.rhport = event->rhport, .event_id = DCD_EVENT_RESUME};
+        queue_event(&event_resume, in_isr);
+      }
+
+      // SOF driver handler in ISR context
+      for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+        usbd_class_driver_t const* driver = get_driver(i);
+        if (driver && driver->sof) {
+          driver->sof(event->rhport, event->sof.frame_count);
+        }
       }
 
       // skip osal queue for SOF in usbd task
-    break;
+      break;
 
     default:
       send = true;
-    break;
+      break;
   }
 
   if (send) {
-      osal_queue_send(_usbd_q, event, in_isr);
-      CFG_TUD_EVENT_HOOK(event, in_isr);
+    queue_event(event, in_isr);
   }
 }
 
@@ -1187,18 +1177,15 @@ bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count
 }
 
 // Helper to defer an isr function
-void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
-{
-  dcd_event_t event =
-  {
+void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr) {
+  dcd_event_t event = {
       .rhport   = 0,
       .event_id = USBD_EVENT_FUNC_CALL,
   };
-
   event.func_call.func  = func;
   event.func_call.param = param;
 
-  dcd_event_handler(&event, in_isr);
+  queue_event(&event, in_isr);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 93a2033c4..1e2f31b06 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -146,6 +146,9 @@ TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en);
 // Invoked when usb bus is resumed
 TU_ATTR_WEAK void tud_resume_cb(void);
 
+// Invoked when there is a new usb event, which need to be processed by tud_task()/tud_task_ext()
+TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
+
 // Invoked when received control request with VENDOR TYPE
 TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 2fdc8216d..bbda99ea2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -247,9 +247,7 @@ CFG_TUH_MEM_SECTION struct
 
 //------------- Helper Function -------------//
 
-TU_ATTR_ALWAYS_INLINE
-static inline usbh_device_t* get_device(uint8_t dev_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) {
   TU_VERIFY(dev_addr > 0 && dev_addr <= TOTAL_DEVICES, NULL);
   return &_usbh_devices[dev_addr-1];
 }
@@ -268,6 +266,12 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec) {
 }
 #endif
 
+TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) {
+  bool ret = osal_queue_send(_usbh_q, event, in_isr);
+  if (tuh_event_hook_cb) tuh_event_hook_cb(event->rhport, event->event_id, in_isr);
+  return ret;
+}
+
 //--------------------------------------------------------------------+
 // Device API
 //--------------------------------------------------------------------+
@@ -433,7 +437,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
           TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
 
           bool is_empty = osal_queue_empty(_usbh_q);
-          osal_queue_send(_usbh_q, &event, in_isr);
+          queue_event(&event, in_isr);
 
           if (is_empty) {
             // Exit if this is the only event in the queue, otherwise we may loop forever
@@ -779,8 +783,7 @@ void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
   event.func_call.func = func;
   event.func_call.param = param;
 
-  osal_queue_send(_usbh_q, &event, in_isr);
-  CFG_TUH_EVENT_HOOK(event, in_isr);
+  queue_event(&event, in_isr);
 }
 
 //--------------------------------------------------------------------+
@@ -936,8 +939,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
     default: break;
   }
 
-  osal_queue_send(_usbh_q, event, in_isr);
-  CFG_TUH_EVENT_HOOK(event, in_isr);
+  queue_event(event, in_isr);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 770d70dfe..7591c7672 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -90,9 +90,12 @@ TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
 // Invoked when a device failed to mount during enumeration process
 // TU_ATTR_WEAK void tuh_mount_failed_cb (uint8_t daddr);
 
-/// Invoked when a device is unmounted (detached)
+// Invoked when a device is unmounted (detached)
 TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 
+// Invoked when there is a new usb event, which need to be processed by tuh_task()/tuh_task_ext()
+TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
+
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cf774a41c..b8509a069 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -486,18 +486,6 @@
 #define tuc_int_handler(_p)
 #endif
 
-//--------------------------------------------------------------------+
-// Optional event hook functions for platform integration (defaults)
-//--------------------------------------------------------------------+
-
-#ifndef CFG_TUD_EVENT_HOOK
-#define CFG_TUD_EVENT_HOOK(EVENT, IN_ISR)
-#endif
-
-#ifndef CFG_TUH_EVENT_HOOK
-#define CFG_TUH_EVENT_HOOK(EVENT, IN_ISR)
-#endif
-
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------
-- 
cgit v1.3.1


From 2fed722b0004e64667df526043f3bfcb131d3ee3 Mon Sep 17 00:00:00 2001
From: Xudong Zheng <7pkvm5aw@slicealias.com>
Date: Sun, 27 Aug 2023 15:21:15 -0400
Subject: add tuh_hid_set_default_protocol() to set default USB host HID
 protocol

---
 src/class/hid/hid_host.c | 11 +++++++++--
 src/class/hid/hid_host.h |  5 +++++
 2 files changed, 14 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index a3551c85a..80312676a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -211,6 +211,13 @@ static void set_protocol_complete(tuh_xfer_t* xfer)
   }
 }
 
+CFG_TUH_MEM_SECTION
+tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
+
+void tuh_hid_set_default_protocol(uint8_t protocol) {
+  _hidh_default_protocol = protocol;
+}
+
 static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol);
@@ -521,7 +528,7 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_
   p_hid->report_desc_len  = tu_unaligned_read16(&desc_hid->wReportLength);
 
   // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config
-  p_hid->protocol_mode = HID_PROTOCOL_BOOT;
+  p_hid->protocol_mode = _hidh_default_protocol;
   if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass )
   {
     p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
@@ -591,7 +598,7 @@ static void process_set_config(tuh_xfer_t* xfer)
     break;
 
     case CONFIG_SET_PROTOCOL:
-      _hidh_set_protocol(daddr, p_hid->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
+      _hidh_set_protocol(daddr, p_hid->itf_num, _hidh_default_protocol, process_set_config, CONFIG_GET_REPORT_DESC);
     break;
 
     case CONFIG_GET_REPORT_DESC:
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 08ad421d2..3c59e301d 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -97,6 +97,11 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr,
 //       Application can use set_protocol() to switch back to Report protocol.
 uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx);
 
+// Device by default is initialized in Boot protocol for simplicity. Application
+// can use this to modify the default protocol before calling tuh_init(), or use
+// set_protocol() to change the protocol after initialization.
+void tuh_hid_set_default_protocol(uint8_t protocol);
+
 // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
 // This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE)
 bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol);
-- 
cgit v1.3.1


From f469250fa34929b1890500b1d7abfb2a7bb7dcc5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Nov 2023 18:35:00 +0700
Subject: minor update

---
 src/class/hid/hid_host.c | 5 ++---
 src/class/hid/hid_host.h | 5 ++---
 2 files changed, 4 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 80312676a..db52b503f 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -67,6 +67,8 @@ typedef struct
 CFG_TUH_MEM_SECTION
 tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID];
 
+tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
+
 //--------------------------------------------------------------------+
 // Helper
 //--------------------------------------------------------------------+
@@ -211,9 +213,6 @@ static void set_protocol_complete(tuh_xfer_t* xfer)
   }
 }
 
-CFG_TUH_MEM_SECTION
-tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
-
 void tuh_hid_set_default_protocol(uint8_t protocol) {
   _hidh_default_protocol = protocol;
 }
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 3c59e301d..238b7c627 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -97,9 +97,8 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr,
 //       Application can use set_protocol() to switch back to Report protocol.
 uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx);
 
-// Device by default is initialized in Boot protocol for simplicity. Application
-// can use this to modify the default protocol before calling tuh_init(), or use
-// set_protocol() to change the protocol after initialization.
+// Device by default is enumerated in Boot protocol for simplicity. Application
+// can use this to modify the default protocol for next enumeration.
 void tuh_hid_set_default_protocol(uint8_t protocol);
 
 // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
-- 
cgit v1.3.1


From 426f791e7af6c8d53c828ecab37848ac833965ea Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Nov 2023 11:38:20 +0700
Subject: minor doc

---
 docs/reference/supported.rst |  2 +-
 src/device/dcd.h             | 30 +++++++++++-------------------
 2 files changed, 12 insertions(+), 20 deletions(-)

(limited to 'src')

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 983640dd3..c9fc4a882 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -41,7 +41,7 @@ Supported MCUs
 |              |     | dsPIC33         | ✔      |      |           | pic               | ci_fs variant|
 |              |     +-----------------+--------+------+-----------+-------------------+--------------+
 |              |     | 32mz            | ✔      |      |           | pic32mz           | musb variant |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
 | Mind Montion | mm32                  | ✔      |      | ✖         | mm32f327x_otg     | ci_fs variant|
 +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
 | NordicSemi   | nRF52833, nRF52840    | ✔      | ✖    | ✖         | nrf5x             |              |
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 18a708347..8c6813cf7 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -47,8 +47,7 @@
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 
-typedef enum
-{
+typedef enum {
   DCD_EVENT_INVALID = 0,
   DCD_EVENT_BUS_RESET,
   DCD_EVENT_UNPLUGGED,
@@ -65,13 +64,11 @@ typedef enum
   DCD_EVENT_COUNT
 } dcd_eventid_t;
 
-typedef struct TU_ATTR_ALIGNED(4)
-{
+typedef struct TU_ATTR_ALIGNED(4) {
   uint8_t rhport;
   uint8_t event_id;
 
-  union
-  {
+  union {
     // BUS RESET
     struct {
       tusb_speed_t speed;
@@ -123,7 +120,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
 //--------------------------------------------------------------------+
 
 // Initialize controller to device mode
-void dcd_init       (uint8_t rhport);
+void dcd_init(uint8_t rhport);
 
 // Interrupt Handler
 void dcd_int_handler(uint8_t rhport);
@@ -184,11 +181,11 @@ void dcd_edpt_stall           (uint8_t rhport, uint8_t ep_addr);
 void dcd_edpt_clear_stall     (uint8_t rhport, uint8_t ep_addr);
 
 // Allocate packet buffer used by ISO endpoints
-// Some MCU need manual packet buffer allocation, we allocation largest size to avoid clustering
+// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering
 TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
 
 // Configure and enable an ISO endpoint according to descriptor
-TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc);
+TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
 
 //--------------------------------------------------------------------+
 // Event API (implemented by stack)
@@ -198,23 +195,20 @@ TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t co
 extern void dcd_event_handler(dcd_event_t const * event, bool in_isr);
 
 // helper to send bus signal event
-TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) {
   dcd_event_t event = { .rhport = rhport, .event_id = eid };
   dcd_event_handler(&event, in_isr);
 }
 
 // helper to send bus reset event
-TU_ATTR_ALWAYS_INLINE static inline  void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline  void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) {
   dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
   event.bus_reset.speed = speed;
   dcd_event_handler(&event, in_isr);
 }
 
 // helper to send setup received
-TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) {
   dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
   memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t));
 
@@ -222,8 +216,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport
 }
 
 // helper to send transfer complete event
-TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) {
   dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE };
 
   event.xfer_complete.ep_addr = ep_addr;
@@ -233,8 +226,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport
   dcd_event_handler(&event, in_isr);
 }
 
-static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) {
   dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF };
   event.sof.frame_count = frame_count;
   dcd_event_handler(&event, in_isr);
-- 
cgit v1.3.1


From 031be18e26933850d63c91659832b9987efecf24 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Nov 2023 16:36:12 +0700
Subject: update release version

---
 library.json          |  2 +-
 repository.yml        |  3 ++-
 src/tusb_option.h     |  2 +-
 tools/make_release.py | 21 +++++++++++++++------
 4 files changed, 19 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/library.json b/library.json
index d637b528d..3cdd5990f 100644
--- a/library.json
+++ b/library.json
@@ -1,6 +1,6 @@
 {
     "name": "TinyUSB",
-    "version": "0.15.0",
+    "version": "0.16.0",
     "description": "TinyUSB is an open-source cross-platform USB Host/Device stack for embedded system, designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events are deferred then handled in the non-ISR task function.",
     "keywords": "usb, host, device",
     "repository":
diff --git a/repository.yml b/repository.yml
index 702753a90..28666d2d4 100644
--- a/repository.yml
+++ b/repository.yml
@@ -13,5 +13,6 @@ repo.versions:
     "0.13.0": "0.13.0"
     "0.14.0": "0.14.0"
     "0.15.0": "0.15.0"
-    "0-latest": "0.15.0"
+    "0.16.0": "0.16.0"
+    "0-latest": "0.16.0"
     "0-dev": "0.0.0"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 7920fbf35..6758933d8 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -30,7 +30,7 @@
 #include "common/tusb_compiler.h"
 
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     15
+#define TUSB_VERSION_MINOR     16
 #define TUSB_VERSION_REVISION  0
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 
diff --git a/tools/make_release.py b/tools/make_release.py
index 7481e8864..256ca8f21 100644
--- a/tools/make_release.py
+++ b/tools/make_release.py
@@ -1,6 +1,6 @@
 import re
 
-version = '0.15.0'
+version = '0.16.0'
 
 print('version {}'.format(version))
 ver_id = version.split('.')
@@ -9,13 +9,11 @@ ver_id = version.split('.')
 # src/tusb_option.h
 ###################
 f_option_h = 'src/tusb_option.h'
-
 with open(f_option_h) as f:
     fdata = f.read()
-
-fdata = re.sub(r'(#define TUSB_VERSION_MAJOR *) \d+', r"\1 {}".format(ver_id[0]), fdata)
-fdata = re.sub(r'(#define TUSB_VERSION_MINOR *) \d+', r"\1 {}".format(ver_id[1]), fdata)
-fdata = re.sub(r'(#define TUSB_VERSION_REVISION *) \d+', r"\1 {}".format(ver_id[2]), fdata)
+    fdata = re.sub(r'(#define TUSB_VERSION_MAJOR *) \d+', r"\1 {}".format(ver_id[0]), fdata)
+    fdata = re.sub(r'(#define TUSB_VERSION_MINOR *) \d+', r"\1 {}".format(ver_id[1]), fdata)
+    fdata = re.sub(r'(#define TUSB_VERSION_REVISION *) \d+', r"\1 {}".format(ver_id[2]), fdata)
 
 # Write the file out again
 with open(f_option_h, 'w') as f:
@@ -33,6 +31,17 @@ if fdata.find(version) < 0:
     with open(f_repository_yml, 'w') as f:
         f.write(fdata)
 
+###################
+# library.json
+###################
+f_library_json = 'library.json'
+with open(f_library_json) as f:
+    fdata = f.read()
+    fdata = re.sub(r'( {4}"version":) "\d+\.\d+\.\d+"', rf'\1 "{version}"', fdata)
+
+with open(f_library_json, 'w') as f:
+    f.write(fdata)
+
 ###################
 # docs/info/changelog.rst
 ###################
-- 
cgit v1.3.1


From 7e1fe2ff83e1089a1e75e4fdc03af4b0aa6048ea Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Fri, 24 Nov 2023 22:02:58 +0100
Subject: made log line end consistent \r\n

---
 examples/device/cdc_uac2/src/main.c       | 2 +-
 src/portable/analog/max3421/hcd_max3421.c | 8 ++++----
 src/portable/ehci/ehci.c                  | 4 ++--
 src/portable/mentor/musb/dcd_musb.c       | 4 ++--
 4 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c
index 7afa96c1a..25b2cd9a5 100644
--- a/examples/device/cdc_uac2/src/main.c
+++ b/examples/device/cdc_uac2/src/main.c
@@ -60,7 +60,7 @@ int main(void)
     led_blinking_task();
 
 #if (CFG_TUSB_MCU == OPT_MCU_RP2040)
-    // printf("Hello, world!\n");
+    // printf("Hello, world!\r\n");
 #endif
   }
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 65f87f7c6..d7ce5a92f 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -382,7 +382,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     if (ep->xfer_pending && ep->packet_size) {
-//      TU_LOG3("next pending i = %u\n", i);
+//      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
   }
@@ -391,7 +391,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   for (size_t i = 0; i <= idx; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     if (ep->xfer_pending && ep->packet_size) {
-//      TU_LOG3("next pending i = %u\n", i);
+//      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
   }
@@ -712,9 +712,9 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
       // However, since we are always in full speed mode, we can just check J-state
       if (jk == HRSL_KSTATUS) {
         new_mode |= MODE_LOWSPEED;
-        TU_LOG3("Low speed\n");
+        TU_LOG3("Low speed\r\n");
       }else {
-        TU_LOG3("Full speed\n");
+        TU_LOG3("Full speed\r\n");
       }
       new_mode |= MODE_SOFKAENAB;
       mode_write(rhport, new_mode, in_isr);
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 572b9826c..e145cbb1b 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -581,7 +581,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
         // clear halted bit if not caused by STALL to allow more transfer
         xfer_result = XFER_RESULT_FAILED;
         qtd_overlay->halted = false;
-        TU_LOG3("  QHD xfer err count: %d\n", qtd_overlay->err_count);
+        TU_LOG3("  QHD xfer err count: %d\r\n", qtd_overlay->err_count);
         // TU_BREAKPOINT(); // TODO skip unplugged device
       }else {
         // no error bits are set, endpoint is halted due to STALL
@@ -664,7 +664,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
   if (int_status & EHCI_INT_MASK_HC_HALTED) {
     // something seriously wrong, maybe forget to flush/invalidate cache
     TU_BREAKPOINT();
-    TU_LOG1("  HC halted\n");
+    TU_LOG1("  HC halted\r\n");
     return;
   }
 
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 3c0114e41..a817c5d6e 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -158,9 +158,9 @@ static inline unsigned free_block_size(free_block_t const *blk)
 #if 0
 static inline void print_block_list(free_block_t const *blk, unsigned num)
 {
-  TU_LOG1("*************\n");
+  TU_LOG1("*************\r\n");
   for (unsigned i = 0; i < num; ++i) {
-    TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
+    TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end);
     ++blk;
   }
 }
-- 
cgit v1.3.1


From b8881a3a141530a1d383d8869881e773b8a07d80 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Fri, 24 Nov 2023 22:34:28 +0100
Subject: fixed compile errors due to untreated CFG_TUH_LOG_LEVEL

---
 src/common/tusb_debug.h | 2 +-
 src/host/usbh.c         | 8 ++++----
 src/host/usbh_pvt.h     | 2 +-
 src/tusb.c              | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 99176c02a..bd388d910 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -43,7 +43,7 @@
 #if CFG_TUSB_DEBUG
 
 // Enum to String for debugging purposes
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
 extern char const* const tu_str_speed[];
 extern char const* const tu_str_std_request[];
 extern char const* const tu_str_xfer_result[];
diff --git a/src/host/usbh.c b/src/host/usbh.c
index d8fff9905..78c8abfbd 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -113,7 +113,7 @@ typedef struct {
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
   #define DRIVER_NAME(_name)    .name = _name,
 #else
   #define DRIVER_NAME(_name)
@@ -1233,7 +1233,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
       if (is_hub_addr(daddr)) {
-        TU_LOG(CFG_TUH_LOG_LEVEL, "  is a HUB device %u\r\n", daddr);
+        TU_LOG_USBH("  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
         // TODO a better to unroll recursrive is using array of removing_hubs and mark it here
@@ -1708,7 +1708,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
 
       if ( drv_id == TOTAL_DRIVER_COUNT - 1 )
       {
-        TU_LOG(CFG_TUH_LOG_LEVEL, "[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+        TU_LOG_USBH("[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
                dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
       }
     }
@@ -1741,7 +1741,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
     enum_full_complete();
 
     if (is_hub_addr(dev_addr)) {
-      TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr);
+      TU_LOG_USBH("HUB address = %u is mounted\r\n", dev_addr);
     }else {
       // Invoke callback if available
       if (tuh_mount_cb) tuh_mount_cb(dev_addr);
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 2b61a77db..3363ab9eb 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -51,7 +51,7 @@ enum {
 //--------------------------------------------------------------------+
 
 typedef struct {
-  #if CFG_TUSB_DEBUG >= 2
+  #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
   char const* name;
   #endif
 
diff --git a/src/tusb.c b/src/tusb.c
index 7b0a669a0..e0c1066d4 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -419,7 +419,7 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize
 #if CFG_TUSB_DEBUG
 #include <ctype.h>
 
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
 
 char const* const tu_str_speed[] = { "Full", "Low", "High" };
 char const* const tu_str_std_request[] =
-- 
cgit v1.3.1


From c4e04d3db4f8f33e906afbae4739d64e53fa9987 Mon Sep 17 00:00:00 2001
From: Oliver Larsson <larsson.e.oliver@gmail.com>
Date: Sun, 29 Oct 2023 16:53:10 +0100
Subject: Add configuration option CFG_TUH_CDC_CP210X_PID_LIST to tusb_option.h

---
 src/class/cdc/cdc_host.c      | 2 +-
 src/class/cdc/serial/cp210x.h | 2 --
 src/tusb_option.h             | 6 ++++++
 3 files changed, 7 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 53e15710e..a6af9b84d 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -109,7 +109,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 #if CFG_TUH_CDC_CP210X
 #include "serial/cp210x.h"
 
-static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST };
+static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST };
 enum {
   CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
 };
diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h
index b01417092..2c749f522 100644
--- a/src/class/cdc/serial/cp210x.h
+++ b/src/class/cdc/serial/cp210x.h
@@ -29,8 +29,6 @@
 // https://www.silabs.com/documents/public/application-notes/AN571.pdf
 
 #define TU_CP210X_VID 0x10C4
-#define TU_CP210X_PID_LIST \
-  0xEA60, 0xEA70
 
 /* Config request codes */
 #define CP210X_IFC_ENABLE      0x00
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a41f5a07e..3d290ae66 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -441,6 +441,12 @@
   #define CFG_TUH_CDC_CP210X 0
 #endif
 
+#ifndef CFG_TUH_CDC_CP210X_PID_LIST
+  // List of product IDs that can use the CP210X CDC driver
+  #define CFG_TUH_CDC_CP210X_PID_LIST \
+    0xEA60, 0xEA70
+#endif
+
 #ifndef CFG_TUH_HID
   #define CFG_TUH_HID    0
 #endif
-- 
cgit v1.3.1


From efde252ed0a577536f409db980f46db844a23b2b Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Fri, 8 Dec 2023 16:59:52 +0100
Subject: improved CFG_TUSB_DEBUG handling due to compile errors

---
 src/common/tusb_debug.h | 2 +-
 src/tusb.c              | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index bd388d910..0f4dc93f3 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -43,7 +43,7 @@
 #if CFG_TUSB_DEBUG
 
 // Enum to String for debugging purposes
-#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 extern char const* const tu_str_speed[];
 extern char const* const tu_str_std_request[];
 extern char const* const tu_str_xfer_result[];
diff --git a/src/tusb.c b/src/tusb.c
index e0c1066d4..7943ea5ef 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -419,7 +419,7 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize
 #if CFG_TUSB_DEBUG
 #include <ctype.h>
 
-#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
+#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 
 char const* const tu_str_speed[] = { "Full", "Low", "High" };
 char const* const tu_str_std_request[] =
-- 
cgit v1.3.1


From ac418f4d25400c12864b242f94215664dc5d9229 Mon Sep 17 00:00:00 2001
From: Angel Molina <angelmolinu@gmail.com>
Date: Sat, 9 Dec 2023 23:13:53 +0100
Subject: Fix strict-overflow warning when compiling with gcc >= 12

---
 src/class/audio/audio_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9af999992..731c39b54 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1565,7 +1565,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       {
         uint8_t const *p_desc = _audiod_fct[i].p_desc;
         uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
-        while (p_desc < p_desc_end)
+        while (p_desc_end - p_desc > 0)
         {
           if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
           {
-- 
cgit v1.3.1


From 506617d4b39ba9118a24477a4be6db9733e2e2f1 Mon Sep 17 00:00:00 2001
From: Ángel Molina Núñez <angmolin@ucm.es>
Date: Sun, 10 Dec 2023 17:04:46 +0100
Subject: Add comment to explain why the condition changes

---
 src/class/audio/audio_device.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 731c39b54..d438d0715 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1565,6 +1565,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       {
         uint8_t const *p_desc = _audiod_fct[i].p_desc;
         uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
         while (p_desc_end - p_desc > 0)
         {
           if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
-- 
cgit v1.3.1


From 9a7e23379ccd4fe572af824c09d6113401412522 Mon Sep 17 00:00:00 2001
From: Oliver Larsson <larsson.e.oliver@gmail.com>
Date: Mon, 11 Dec 2023 09:36:10 +0100
Subject: Add configuration option CFG_TUH_CDC_FTDI_PID_LIST to tusb_option.h

---
 src/class/cdc/cdc_host.c        | 2 +-
 src/class/cdc/serial/ftdi_sio.h | 5 +----
 src/tusb_option.h               | 6 ++++++
 3 files changed, 8 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index a6af9b84d..a6dfb45ae 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -90,7 +90,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 #if CFG_TUH_CDC_FTDI
 #include "serial/ftdi_sio.h"
 
-static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST };
+static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST };
 enum {
   FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
 };
diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h
index 6916e4031..0825f0719 100644
--- a/src/class/cdc/serial/ftdi_sio.h
+++ b/src/class/cdc/serial/ftdi_sio.h
@@ -25,11 +25,8 @@
 #ifndef TUSB_FTDI_SIO_H
 #define TUSB_FTDI_SIO_H
 
-// VID/PID for matching FTDI devices
+// VID for matching FTDI devices
 #define TU_FTDI_VID 0x0403
-#define TU_FTDI_PID_LIST \
-  0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, \
-  0xcd18
 
 // Commands
 #define FTDI_SIO_RESET             	0    /* Reset the port */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 900784388..7597392d6 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -442,6 +442,12 @@
   #define CFG_TUH_CDC_FTDI 0
 #endif
 
+#ifndef CFG_TUH_CDC_FTDI_PID_LIST
+  // List of product IDs that can use the FTDI CDC driver
+  #define CFG_TUH_CDC_FTDI_PID_LIST \
+    0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, 0xCD18
+#endif
+
 #ifndef CFG_TUH_CDC_CP210X
   // CP210X is not part of CDC class, only to re-use CDC driver API
   #define CFG_TUH_CDC_CP210X 0
-- 
cgit v1.3.1


From 93c40b6966db53ce70f4bea6b8a72bf2986ac180 Mon Sep 17 00:00:00 2001
From: henneboi <william.hennebois@st.com>
Date: Fri, 8 Dec 2023 13:34:42 +0100
Subject: Add Support stm32h5 for stm32h573i based on stm32_fsdev G0
 implementation Tested on Windows with IAR and gcc toolchain ( via cubeide)
 Tested only with audio examples, but sould be ok for other examples Cmake
 pacthed : but not tested Linux build : not tested Added a temporary
 workaround in make file to support H5 HAL repo ( ARMCC_VERSION=0)

---
 hw/bsp/board_mcu.h                                 |  11 +-
 hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h     | 165 ++++++++++
 .../boards/stm32h573i-dk/STM32H573I-DK_FLASH.ld    | 187 +++++++++++
 hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake    |  10 +
 hw/bsp/stm32h5/boards/stm32h573i-dk/board.h        | 125 ++++++++
 hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk       |  13 +
 hw/bsp/stm32h5/family.c                            | 206 ++++++++++++
 hw/bsp/stm32h5/family.cmake                        | 116 +++++++
 hw/bsp/stm32h5/family.mk                           |  57 ++++
 hw/bsp/stm32h5/stm32h5xx_hal_conf.h                | 355 +++++++++++++++++++++
 src/common/tusb_mcu.h                              |   6 +
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c      |  11 +-
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h        |  29 ++
 src/tusb_option.h                                  |   1 +
 tools/get_deps.py                                  |   9 +-
 15 files changed, 1295 insertions(+), 6 deletions(-)
 create mode 100644 hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/STM32H573I-DK_FLASH.ld
 create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake
 create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/board.h
 create mode 100644 hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk
 create mode 100644 hw/bsp/stm32h5/family.c
 create mode 100644 hw/bsp/stm32h5/family.cmake
 create mode 100644 hw/bsp/stm32h5/family.mk
 create mode 100644 hw/bsp/stm32h5/stm32h5xx_hal_conf.h

(limited to 'src')

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 4ce5c4139..d40f33bbe 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -40,8 +40,8 @@
 
 // Include order follows OPT_MCU_ number
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \
-      TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX)  || \
-      TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
+  TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX)  || \
+  TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
   #include "chip.h"
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
@@ -54,8 +54,8 @@
   #include "nrf.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
-      CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
-      CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
+  CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
+  CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
   #include "sam.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_SAMG
@@ -83,6 +83,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G4
   #include "stm32g4xx.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+  #include "stm32h5xx.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H7
   #include "stm32h7xx.h"
 
diff --git a/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..52dfa095f
--- /dev/null
+++ b/hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32g0xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+#define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+#define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY       ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY  2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY               ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY          ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/STM32H573I-DK_FLASH.ld b/hw/bsp/stm32h5/boards/stm32h573i-dk/STM32H573I-DK_FLASH.ld
new file mode 100644
index 000000000..c66464bd6
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/STM32H573I-DK_FLASH.ld
@@ -0,0 +1,187 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: STM32CubeMX
+**
+**  Abstract    : Linker script for stm32h573i-dk series
+**                640Kbytes FLASH and 2048Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 640K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake
new file mode 100644
index 000000000..82d4474af
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32h573i-dk)
+set(JLINK_DEVICE stm32h573i-dk)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32H573I-DK_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H573xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h
new file mode 100644
index 000000000..01834f151
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h
@@ -0,0 +1,125 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2034, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOI
+#define LED_PIN               GPIO_PIN_9
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART1
+#define UART_CLK_EN           __USART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF7_USART1
+
+#define UART_TX_PIN           GPIO_PIN_9
+#define UART_RX_PIN           GPIO_PIN_10
+
+
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+// Clock configure for STM32stm32h573i-dk
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  Freq 250MHZ */
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 100;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 10;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+  // Configure CRS clock source
+  __HAL_RCC_CRS_CLK_ENABLE();
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+
+  /* Select HSI48 as USB clock source */
+  RCC_PeriphCLKInitTypeDef usb_clk = {0 };
+  usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&usb_clk);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+
+  SystemCoreClockUpdate();
+
+
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk
new file mode 100644
index 000000000..66b299886
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.mk
@@ -0,0 +1,13 @@
+CFLAGS += \
+	-DSTM32H573xx
+
+# GCC
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h573xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32H573I-DK_FLASH.ld
+
+# IAR
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h573xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h573xx_flash.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h573i-dk
diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c
new file mode 100644
index 000000000..d035b791c
--- /dev/null
+++ b/hw/bsp/stm32h5/family.c
@@ -0,0 +1,206 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32h5xx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_DRD_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void)
+{
+  HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS
+  board_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+
+  //__HAL_RCC_SYSCFG_CLK_ENABLE();
+  //__HAL_RCC_PWR_CLK_ENABLE();
+
+  UART_CLK_EN();
+
+  #if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+  #elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_DRD_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  #ifdef UART_DEV
+  // UART
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef)
+  {
+    .Instance        = UART_DEV,
+    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+    .Init.WordLength = UART_WORDLENGTH_8B,
+    .Init.StopBits   = UART_STOPBITS_1,
+    .Init.Parity     = UART_PARITY_NONE,
+    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+    .Init.Mode       = UART_MODE_TX_RX,
+    .Init.OverSampling = UART_OVERSAMPLING_16,
+    .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT
+  };
+  HAL_UART_Init(&UartHandle);
+  #endif
+
+  // USB Pins TODO double check USB clock and pin setup
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+
+  /* Enable VDDUSB */
+  HAL_PWREx_EnableVddUSB();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+size_t board_get_unique_id(uint8_t id[], size_t max_len)
+{
+  (void) max_len;
+  volatile uint32_t *stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t *id32 = (uint32_t *)(uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  #ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t *)(uintptr_t) buf, len, 0xffff);
+  return len;
+  #else
+  (void) buf;
+  (void) len;
+  (void) UartHandle;
+  return 0;
+  #endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void)
+{
+  system_ticks++;
+  HAL_IncTick();
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+
+#endif
+
+void HardFault_Handler(void)
+{
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake
new file mode 100644
index 000000000..8edee1887
--- /dev/null
+++ b/hw/bsp/stm32h5/family.cmake
@@ -0,0 +1,116 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY h5)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32H5 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32H5 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  #family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32h5/family.mk b/hw/bsp/stm32h5/family.mk
new file mode 100644
index 000000000..e04e08d80
--- /dev/null
+++ b/hw/bsp/stm32h5/family.mk
@@ -0,0 +1,57 @@
+ST_FAMILY = h5
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32H5 
+  
+# workaround to fix a build issue due to a wrong define check in hal, this define must be removed as soon as the repo is fixed   
+CFLAGS += \
+  -D__ARMCC_VERSION=0
+
+# GCC Flags
+CFLAGS_GCC += \
+  -flto \
+  -nostdlib -nostartfiles \
+  -Wno-unused-parameter \
+  -Wno-cast-align
+
+# suppress warning caused by vendor mcu driver
+CFLAGS_GCC += -Wno-error=cast-align
+
+#LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
+# -----------------
+# Sources & Include
+# -----------------
+
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32h5/stm32h5xx_hal_conf.h b/hw/bsp/stm32h5/stm32h5xx_hal_conf.h
new file mode 100644
index 000000000..d017bb06b
--- /dev/null
+++ b/hw/bsp/stm32h5/stm32h5xx_hal_conf.h
@@ -0,0 +1,355 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h5xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018-2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32h5xx_HAL_CONF_H
+#define STM32h5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_EXTI_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_I2C_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS    0u
+#define USE_HAL_CEC_REGISTER_CALLBACKS    0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS   0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS   0u
+#define USE_HAL_DAC_REGISTER_CALLBACKS    0u
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS  0u
+#define USE_HAL_HCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS    0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS   0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS  0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS    0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS    0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS  0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS    0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS    0u
+#define USE_HAL_UART_REGISTER_CALLBACKS   0u
+#define USE_HAL_USART_REGISTER_CALLBACKS  0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS   0u
+
+
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Core Speed oscillator (CSI) default value.
+  *        This value is the default CSI range value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+#define CSI_VALUE              4000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE              64000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+#define HSI48_VALUE             48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                                  The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  32000UL    /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+
+#if !defined  (LSI_STARTUP_TIME)
+#define LSI_STARTUP_TIME          130UL      /*!< Time out for LSI start up, in ms */
+#endif /* LSI_STARTUP_TIME */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  32768UL    /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000UL     /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SPI/SAI peripheral
+  *        This value is used by the SPI/SAI HAL module to compute the SPI/SAI clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000UL /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ############################################ System Configuration ################################################ */
+
+/**
+  * @brief This is the HAL system configuration section
+  */
+
+#define  VDD_VALUE                  3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY          (15UL)  /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                   0U
+#define  PREFETCH_ENABLE            0U               /*!< Enable prefetch */
+
+
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME     1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include modules header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32h5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32h5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32h5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32h5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32h5xx_hal_adc.h"
+#include "stm32h5xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32h5xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32h5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32h5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32h5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32h5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32h5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32h5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32h5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32h5xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32h5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32h5xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32h5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32h5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32h5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32h5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32h5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32h5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32h5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32h5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32h5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32h5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32h5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32h5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32h5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for functions parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32h5xx_HAL_CONF_H */
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 6fab190ea..9c4083031 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -210,6 +210,12 @@
 
   #define TUP_DCD_ENDPOINT_MAX    9
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32H5)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+          
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
   // Device controller
   #define TUP_USBIP_FSDEV
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 14cabaf8d..b0a00b7ee 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -242,7 +242,7 @@ void dcd_init (uint8_t rhport)
   }
   USB->CNTR = 0; // Enable USB
 
-#ifndef STM32G0 // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
+#if !defined(STM32G0) && !defined(STM32H5)  // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
   USB->BTABLE = DCD_STM32_BTABLE_BASE;
 #endif
   USB->ISTR = 0; // Clear pending interrupts
@@ -357,6 +357,11 @@ void dcd_int_enable (uint8_t rhport)
   #else
     NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
   #endif
+    
+    
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+    NVIC_EnableIRQ(USB_DRD_FS_IRQn);
+    
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_EnableIRQ(USB_HP_IRQn);
@@ -414,6 +419,10 @@ void dcd_int_disable(uint8_t rhport)
   #else
     NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
   #endif
+    
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+    NVIC_DisableIRQ(USB_DRD_FS_IRQn);
+    
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_DisableIRQ(USB_HP_IRQn);
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index e6649de5a..0db426e50 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -110,6 +110,35 @@
   #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
   #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+  #include "stm32h5xx.h"
+  #define PMA_32BIT_ACCESS
+  #define PMA_LENGTH (2048u)
+  #undef USB_PMAADDR
+  #define USB_PMAADDR USB_DRD_PMAADDR
+  #define USB_TypeDef USB_DRD_TypeDef
+  #define EP0R CHEP0R
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB USB_DRD_FS
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+  
+        
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   #include "stm32wbxx.h"
   #define PMA_LENGTH (1024u)
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 7597392d6..699691b53 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -86,6 +86,7 @@
 #define OPT_MCU_STM32WB           312 ///< ST WB
 #define OPT_MCU_STM32U5           313 ///< ST U5
 #define OPT_MCU_STM32L5           314 ///< ST L5
+#define OPT_MCU_STM32H5           315 ///< ST H5
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 79c272c07..cda4fc8da 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -95,6 +95,10 @@ deps_optional = {
     'hw/mcu/st/cmsis_device_h7': ['https://github.com/STMicroelectronics/cmsis_device_h7.git',
                                   '60dc2c913203dc8629dc233d4384dcc41c91e77f',
                                   'stm32h7'],
+    'hw/mcu/st/cmsis_device_h5': ['https://github.com/STMicroelectronics/cmsis_device_h5.git',
+                                  '62b2cb0fbfe10c5791ee469bbde7b397c2fea8f5',
+                                  'stm32h5'],
+								  
     'hw/mcu/st/cmsis_device_l0': ['https://github.com/STMicroelectronics/cmsis_device_l0.git',
                                   '06748ca1f93827befdb8b794402320d94d02004f',
                                   'stm32l0'],
@@ -140,6 +144,9 @@ deps_optional = {
     'hw/mcu/st/stm32h7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git',
                                        'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04',
                                        'stm32h7'],
+    'hw/mcu/st/stm32h5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git',
+                                       '2cf77de584196d619cec1b4586c3b9e2820a254e',
+                                       'stm32h5'],
     'hw/mcu/st/stm32l0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git',
                                        'fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b',
                                        'stm32l0'],
@@ -170,7 +177,7 @@ deps_optional = {
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
                     'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
-                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 '
+                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5'
                     'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
                          'e73e04ca63495672d955f9268e003cffe168fcd8',
-- 
cgit v1.3.1


From 19d7d62e804dbf26f9d193d72710574abcd6fa95 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 13 Dec 2023 18:54:00 +0700
Subject: try to add samd51 to hil pool using doublereset (rpi gpio) and bossac

---
 .github/workflows/cmake_arm.yml | 10 +++++++++-
 hw/bsp/samd21/family.cmake      |  3 ++-
 hw/bsp/samd51/family.c          | 14 ++++++++++++++
 hw/bsp/samd51/family.cmake      |  4 +++-
 src/device/usbd_pvt.h           |  5 -----
 src/host/usbh_pvt.h             |  5 -----
 src/tusb_option.h               | 10 ++++++++++
 test/hil/hil_pi4.json           |  9 +++++++++
 test/hil/hil_test.py            | 39 +++++++++++++++++++++++++++++++++++++--
 9 files changed, 84 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index f760ca3ca..46dc7a93b 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -102,6 +102,13 @@ jobs:
         path: |
           cmake-build/cmake-build-feather_nrf52840_express/*/*/*.elf
 
+    - name: Upload Artifacts for Hardware Testing (samd51)
+      if: matrix.family == 'samd51' && github.repository_owner == 'hathach'
+      uses: actions/upload-artifact@v3
+      with:
+        name: itsybitsy_m4
+        path: |
+          cmake-build/cmake-build-itsybitsy_m4/*/*/*.bin
 
   # ---------------------------------------
   # Hardware in the loop (HIL)
@@ -116,8 +123,9 @@ jobs:
       fail-fast: false
       matrix:
         board:
-          - 'raspberry_pi_pico'
           - 'feather_nrf52840_express'
+          - 'itsybitsy_m4'
+          - 'raspberry_pi_pico'
     steps:
       - name: Clean workspace
         run: |
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
index 44aad6ecb..a79a25b54 100644
--- a/hw/bsp/samd21/family.cmake
+++ b/hw/bsp/samd21/family.cmake
@@ -10,7 +10,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS SAMD21 CACHE INTERNAL "")
-
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -f target/at91samdXX.cfg")
 
 #------------------------------------
 # BOARD_TARGET
@@ -102,4 +102,5 @@ function(family_configure_example TARGET RTOS)
 
   # Flashing
   family_flash_jlink(${TARGET})
+  #family_flash_openocd(${TARGET} ${OPENOCD_OPTION})
 endfunction()
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 009a0d290..170c88191 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -157,6 +157,20 @@ uint32_t board_button_read(void) {
   return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+
+  uint32_t did_addr[4] = {0x008061FC, 0x00806010, 0x00806014, 0x00806018};
+
+  for (int i = 0; i < 4; i++) {
+    uint32_t did = *((uint32_t const*) did_addr[i]);
+    did = TU_BSWAP32(did); // swap endian to match samd51 uf2 bootloader
+    memcpy(id + i * 4, &did, 4);
+  }
+
+  return 16;
+}
+
 int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd51/family.cmake
index 7591f3b1b..4d91bf1a6 100644
--- a/hw/bsp/samd51/family.cmake
+++ b/hw/bsp/samd51/family.cmake
@@ -10,7 +10,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS SAMD51 CACHE INTERNAL "")
-
+set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -c \"transport select swd\" -c \"set CHIPNAME samd51\" -f target/atsame5x.cfg")
 
 #------------------------------------
 # BOARD_TARGET
@@ -100,5 +100,7 @@ function(family_configure_example TARGET RTOS)
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
+  family_add_bin_hex(${TARGET})
   family_flash_jlink(${TARGET})
+  #family_flash_openocd(${TARGET} ${OPENOCD_OPTION})
 endfunction()
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 153be7cee..9039bc9d6 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -33,11 +33,6 @@
  extern "C" {
 #endif
 
-// Level where CFG_TUSB_DEBUG must be at least for USBD is logged
-#ifndef CFG_TUD_LOG_LEVEL
-#define CFG_TUD_LOG_LEVEL   2
-#endif
-
 #define TU_LOG_USBD(...)   TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 3363ab9eb..4a97a1c18 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -35,11 +35,6 @@
  extern "C" {
 #endif
 
-// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
-#ifndef CFG_TUH_LOG_LEVEL
-  #define CFG_TUH_LOG_LEVEL   2
-#endif
-
 #define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
 
 enum {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 7597392d6..4d2aa137c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -299,6 +299,16 @@
   #define CFG_TUSB_DEBUG 0
 #endif
 
+// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
+#ifndef CFG_TUH_LOG_LEVEL
+  #define CFG_TUH_LOG_LEVEL   2
+#endif
+
+// Level where CFG_TUSB_DEBUG must be at least for USBD is logged
+#ifndef CFG_TUD_LOG_LEVEL
+  #define CFG_TUD_LOG_LEVEL   2
+#endif
+
 // Memory section for placing buffer used for usb transferring. If MEM_SECTION is different for
 // host and device use: CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION instead
 #ifndef CFG_TUSB_MEM_SECTION
diff --git a/test/hil/hil_pi4.json b/test/hil/hil_pi4.json
index 560c3964e..17d9ff1fa 100644
--- a/test/hil/hil_pi4.json
+++ b/test/hil/hil_pi4.json
@@ -23,6 +23,15 @@
             "flasher": "jlink",
             "flasher_sn": "000682804350",
             "flasher_args": "-device nrf52840_xxaa"
+        },
+        {
+            "name": "itsybitsy_m4",
+            "uid": "D784B28C5338533335202020FF044726",
+            "flasher": "bossac",
+            "flashser_vendor": "Adafruit Industries",
+            "flasher_product": "ItsyBitsy M4 Express",
+            "flasher_reset_pin": "2",
+            "flasher_args": "--offset 0x4000"
         }
     ]
 }
diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py
index 8f8a3aa65..f9611b96e 100644
--- a/test/hil/hil_test.py
+++ b/test/hil/hil_test.py
@@ -34,6 +34,10 @@ import subprocess
 import json
 import glob
 
+# for RPI double reset: install sudo apt install python3-gpiozero or sudo pip install gpiozero
+from gpiozero import LED
+
+
 ENUM_TIMEOUT = 10
 
 
@@ -41,6 +45,8 @@ ENUM_TIMEOUT = 10
 def get_serial_dev(id, vendor_str, product_str, ifnum):
     if vendor_str and product_str:
         # known vendor and product
+        vendor_str = vendor_str.replace(' ', '_')
+        product_str = product_str.replace(' ', '_')
         return f'/dev/serial/by-id/usb-{vendor_str}_{product_str}_{id}-if{ifnum:02d}'
     else:
         # just use id: mostly for cp210x/ftdi flasher
@@ -115,7 +121,7 @@ def flash_jlink(board, firmware):
 
 def flash_openocd(board, firmware):
     ret = subprocess.run(
-        f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware}" -c "reset init" -c "resume" -c "exit"',
+        f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware} reset exit"',
         shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
     return ret
 
@@ -133,6 +139,35 @@ def flash_esptool(board, firmware):
     return ret
 
 
+def doublereset_with_rpi_gpio(board):
+    # Off = 0 = Reset
+    led = LED(board["flasher_reset_pin"])
+
+    led.off()
+    time.sleep(0.1)
+    led.on()
+    time.sleep(0.1)
+    led.off()
+    time.sleep(0.1)
+    led.on()
+
+def flash_bossac(board, firmware):
+    # double reset to enter bootloader
+    doublereset_with_rpi_gpio(board)
+
+    port = get_serial_dev(board["uid"], board["flashser_vendor"], board["flasher_product"], 0)
+    timeout = ENUM_TIMEOUT
+    while timeout:
+        if os.path.exists(port):
+            time.sleep(0.5)
+            break
+        else:
+            time.sleep(0.5)
+            timeout = timeout - 0.5
+    ret = subprocess.run(f'bossac --port {port} {board["flasher_args"]} -U -i -R -e -w {firmware}', shell=True, stdout=subprocess.PIPE,
+                         stderr=subprocess.STDOUT)
+    return ret
+
 # -------------------------------------------------------------
 # Tests
 # -------------------------------------------------------------
@@ -305,7 +340,7 @@ def main(config_file, board):
 
         for test in test_list:
             fw_list = [
-                # cmake: esp32 use .bin file
+                # cmake: esp32 & samd51 use .bin file
                 f'cmake-build/cmake-build-{item["name"]}/device/{test}/{test}.elf',
                 f'cmake-build/cmake-build-{item["name"]}/device/{test}/{test}.bin',
                 # make
-- 
cgit v1.3.1


From f3d713ac7336913a68326eae5a7e146ec2cd22c3 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 12 Dec 2023 22:35:05 +0100
Subject: Fix CI & typo.

---
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h        | 2 +-
 hw/bsp/stm32h5/boards/stm32h573i-dk/board.h          | 2 +-
 hw/bsp/stm32h5/family.mk                             | 4 ++--
 src/common/tusb_mcu.h                                | 1 -
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 7 ++-----
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 4 ++--
 tools/get_deps.py                                    | 1 -
 7 files changed, 8 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
index ae0820529..9ebaf73f0 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -2,7 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
- * Copyright (c) 2034, HiFiPhile
+ * Copyright (c) 2023, HiFiPhile
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
diff --git a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h
index 01834f151..a8808e32b 100644
--- a/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h
+++ b/hw/bsp/stm32h5/boards/stm32h573i-dk/board.h
@@ -2,7 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
- * Copyright (c) 2034, HiFiPhile
+ * Copyright (c) 2023, HiFiPhile
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
diff --git a/hw/bsp/stm32h5/family.mk b/hw/bsp/stm32h5/family.mk
index e04e08d80..2fd95ecec 100644
--- a/hw/bsp/stm32h5/family.mk
+++ b/hw/bsp/stm32h5/family.mk
@@ -11,9 +11,9 @@ CPU_CORE ?= cortex-m33
 # Compiler Flags
 # --------------
 CFLAGS += \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32H5 
+  -DCFG_TUSB_MCU=OPT_MCU_STM32H5
   
-# workaround to fix a build issue due to a wrong define check in hal, this define must be removed as soon as the repo is fixed   
+# workaround to fix a build issue due to a wrong define check in hal, this define must be removed as soon as the repo is fixed
 CFLAGS += \
   -D__ARMCC_VERSION=0
 
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 9c4083031..e589c4c86 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -214,7 +214,6 @@
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
-          
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
   // Device controller
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index b0a00b7ee..21cd3da26 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -357,11 +357,9 @@ void dcd_int_enable (uint8_t rhport)
   #else
     NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
   #endif
-    
-    
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
     NVIC_EnableIRQ(USB_DRD_FS_IRQn);
-    
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_EnableIRQ(USB_HP_IRQn);
@@ -419,10 +417,9 @@ void dcd_int_disable(uint8_t rhport)
   #else
     NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
   #endif
-    
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
     NVIC_DisableIRQ(USB_DRD_FS_IRQn);
-    
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_DisableIRQ(USB_HP_IRQn);
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 0db426e50..b71e4f498 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -137,8 +137,8 @@
   #define USB_EPADDR_FIELD USB_CHEP_ADDR
   #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
   #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
-  
-        
+
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   #include "stm32wbxx.h"
   #define PMA_LENGTH (1024u)
diff --git a/tools/get_deps.py b/tools/get_deps.py
index cda4fc8da..38ff81412 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -98,7 +98,6 @@ deps_optional = {
     'hw/mcu/st/cmsis_device_h5': ['https://github.com/STMicroelectronics/cmsis_device_h5.git',
                                   '62b2cb0fbfe10c5791ee469bbde7b397c2fea8f5',
                                   'stm32h5'],
-								  
     'hw/mcu/st/cmsis_device_l0': ['https://github.com/STMicroelectronics/cmsis_device_l0.git',
                                   '06748ca1f93827befdb8b794402320d94d02004f',
                                   'stm32l0'],
-- 
cgit v1.3.1


From 7f84fe9bdad2b3d7e2fc48b7dedb8bbdf305bf57 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 21 Dec 2023 08:48:59 +0100
Subject: dcd_nrf5x: Fix dcd_edpt_open for iso endpoint

When ISO endpoint handling was introduced two lines that
clear stall and data toggle bit were left unchanged and they
were effective for ISO enadpoint as well.
This is incorrect behavior since EPSTALL and DTOGGLE registers
have only 3 bits for address.
Leaving code that clears toggle bit results in endpoint 0 toggle bit
being reset when iso endpoint (8) is opened.

Now code that clears stall and toggle bit is applied to non-iso endpoint only
as it was done before iso handling was introduced.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index acc967bb3..4e702aed4 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -340,6 +340,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum);
       NRF_USBD->EPINEN  |= TU_BIT(epnum);
     }
+    // clear stall and reset DataToggle
+    NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
+    NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
   }
   else
   {
@@ -375,10 +378,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     }
   }
 
-  // clear stall and reset DataToggle
-  NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
-  NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
-
   __ISB(); __DSB();
 
   return true;
-- 
cgit v1.3.1


From a39be99a58847318e67d06db17c24e481d318f08 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 26 Dec 2023 12:24:54 +0100
Subject: improved hex debug print, improved USBH debug prints, added pid/vid
 debug print

---
 src/common/tusb_debug.h |  2 +-
 src/host/usbh.c         | 29 ++++++++++++++++-------------
 src/host/usbh_pvt.h     |  6 +++++-
 3 files changed, 22 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 0f4dc93f3..8db1606ae 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -76,7 +76,7 @@ static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_BUF(_x, _n)   tu_print_buf((uint8_t const*)(_x), _n)
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = 0x%lX\r\n", (unsigned long) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4d30d9f81..ee7424ed9 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -291,6 +291,9 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) {
   *vid = dev->vid;
   *pid = dev->pid;
 
+  TU_LOG_HEX_USBH(*vid);
+  TU_LOG_HEX_USBH(*pid);
+
   return true;
 }
 
@@ -340,12 +343,12 @@ bool tuh_init(uint8_t controller_id) {
   if ( tuh_inited() ) return true;
 
   TU_LOG_USBH("USBH init on controller %u\r\n", controller_id);
-  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(usbh_device_t));
-  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(hcd_event_t));
-  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(_ctrl_xfer));
-  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tuh_xfer_t));
-  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_fifo_t));
-  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_edpt_stream_t));
+  TU_LOG_INT_USBH(sizeof(usbh_device_t));
+  TU_LOG_INT_USBH(sizeof(hcd_event_t));
+  TU_LOG_INT_USBH(sizeof(_ctrl_xfer));
+  TU_LOG_INT_USBH(sizeof(tuh_xfer_t));
+  TU_LOG_INT_USBH(sizeof(tu_fifo_t));
+  TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -589,7 +592,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
   TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
               (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
                   tu_str_std_request[xfer->setup->bRequest] : "Class Request");
-  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8);
+  TU_LOG_BUF_USBH(xfer->setup, 8);
   TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb) {
@@ -665,9 +668,9 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
-    TU_LOG1_BUF(request, 8);
-    TU_LOG1("\r\n");
+    TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG_BUF_USBH(request, 8);
+    TU_LOG_USBH("\r\n");
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);
@@ -685,7 +688,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
       case CONTROL_STAGE_DATA:
         if (request->wLength) {
           TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
+          TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
         _ctrl_xfer.actual_len = (uint16_t) xferred_bytes;
@@ -860,7 +863,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
     // HCD error, mark endpoint as ready to allow next transfer
     ep_state->busy    = 0;
     ep_state->claimed = 0;
-    TU_LOG1("Failed\r\n");
+    TU_LOG_USBH("Failed\r\n");
 //    TU_BREAKPOINT();
     return false;
   }
@@ -1318,7 +1321,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     if ( retry ) {
       failed_count++;
       osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit
-      TU_LOG1("Enumeration attempt %u\r\n", failed_count);
+      TU_LOG_USBH("Enumeration attempt %u\r\n", failed_count);
       retry = tuh_control_xfer(xfer);
     }
 
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 4a97a1c18..4ed2a72b5 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -35,7 +35,11 @@
  extern "C" {
 #endif
 
-#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_USBH(...)      TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_MEM_USBH(...)  TU_LOG_MEM(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_BUF_USBH(...)  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_INT_USBH(...)  TU_LOG_INT(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_HEX_USBH(...)  TU_LOG_HEX(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
 
 enum {
   USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
-- 
cgit v1.3.1


From 551e47a464f55e1e36e2812e79902f4ef2955a17 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Dec 2023 22:50:01 +0700
Subject: allow rp2040 to use max3421e as host controller

- fix warnings build hcd max3421 with rp2040
- add tinyusb_host_max3421 target for rp2040 cmake, -DMAX3421_HOST=1
will enable this
- add max3421 driver implementation for rp2040 family
- update tusb_config for host to allow easy enable host selection for
rp2040 (default/pio-usb/max3421)
---
 .idea/cmake.xml                                    |  15 +--
 examples/host/bare_api/src/tusb_config.h           |  64 +++++-----
 examples/host/cdc_msc_hid/src/tusb_config.h        |  64 +++++-----
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    |  64 +++++-----
 examples/host/hid_controller/src/tusb_config.h     |  64 +++++-----
 examples/host/msc_file_explorer/src/tusb_config.h  |  65 +++++-----
 hw/bsp/rp2040/board.h                              |  11 ++
 hw/bsp/rp2040/family.c                             | 140 +++++++++++++++------
 hw/bsp/rp2040/family.cmake                         |  22 +++-
 src/portable/analog/max3421/hcd_max3421.c          |  36 +++---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c       |   2 +-
 11 files changed, 341 insertions(+), 206 deletions(-)

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index d12e44789..d3917c1f7 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,16 +2,17 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
-      <configuration PROFILE_NAME="feather_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_feather_rp2040" />
-      <configuration PROFILE_NAME="metro esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_metro_esp32s2 -DMAX3421_HOST=1 -DLOG=2">
+      <configuration PROFILE_NAME="pico" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
+      <configuration PROFILE_NAME="feather_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_feather_rp2040 -DLOG=2 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_metro_rp2040 -DLOG=2 -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="feather esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_feather_esp32s2 -DMAX3421_HOST=1 -DLOG=2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_saola_1">
+      <configuration PROFILE_NAME="metro esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_metro_esp32s2 -DMAX3421_HOST=1 -DLOG=2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
@@ -25,7 +26,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="espressif_s3_devkitm" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm -DMAX3421_HOST=1 -DLOG=2">
+      <configuration PROFILE_NAME="feather esp32s3" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_feather_esp32s3 -DMAX3421_HOST=1 -DLOG=2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
@@ -39,10 +40,10 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="feather_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
-      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="feather_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index ede9618d3..05ffbdf75 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -30,28 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-#if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#endif
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -67,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -85,11 +59,43 @@
 #endif
 
 #ifndef CFG_TUH_MEM_ALIGN
-#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_RPI_PIO_USB   1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index a53000a11..61abb85eb 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -30,28 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-#if CFG_TUSB_MCU == OPT_MCU_RP2040
-  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-  #define CFG_TUH_RPI_PIO_USB   0
-  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#endif
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -67,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -85,11 +59,43 @@
 #endif
 
 #ifndef CFG_TUH_MEM_ALIGN
-#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_RPI_PIO_USB   1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index ba23301ed..c661f47be 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -30,28 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-#if CFG_TUSB_MCU == OPT_MCU_RP2040
-  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-  #define CFG_TUH_RPI_PIO_USB   0
-  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#endif
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -72,12 +52,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -90,11 +64,43 @@
 #endif
 
 #ifndef CFG_TUH_MEM_ALIGN
-#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_RPI_PIO_USB   1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index d37fc02d2..8ddaddda7 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -30,28 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
- #if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#endif
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -67,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -85,11 +59,43 @@
 #endif
 
 #ifndef CFG_TUH_MEM_ALIGN
-#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_RPI_PIO_USB   1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index b4ccd8223..1703761a4 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -30,29 +30,8 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// Board Specific Configuration
-//--------------------------------------------------------------------+
-
-#if CFG_TUSB_MCU == OPT_MCU_RP2040
-  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-  #define CFG_TUH_RPI_PIO_USB   0
-  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#endif
-
-
-// RHPort number used for host can be defined by board.mk, default to port 0
-#ifndef BOARD_TUH_RHPORT
-#define BOARD_TUH_RHPORT      0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUH_MAX_SPEED
-#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
@@ -68,12 +47,6 @@
 #define CFG_TUSB_DEBUG        0
 #endif
 
-// Enable Host stack
-#define CFG_TUH_ENABLED       1
-
-// Default is max speed that hardware controller could support with on-chip PHY
-#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -86,11 +59,43 @@
 #endif
 
 #ifndef CFG_TUH_MEM_ALIGN
-#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#define CFG_TUH_MEM_ALIGN     __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// Host Configuration
+//--------------------------------------------------------------------
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
+  // #define CFG_TUH_RPI_PIO_USB   1 // use max3421 as host controller
+
+  // host roothub port is 1 if using either pio-usb or max3421
+  #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
+    #define BOARD_TUH_RHPORT      1
+  #endif
+#endif
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+//------------------------- Board Specific --------------------------
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 //--------------------------------------------------------------------
-// CONFIGURATION
+// Driver Configuration
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index 063c9580e..3849894ce 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -74,6 +74,17 @@
 #define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1
 #endif
 
+//--------------------------------------------------------------------
+// USB Host MAX3421E
+//--------------------------------------------------------------------
+
+#define MAX3421_SPI      PICO_DEFAULT_SPI_INSTANCE
+#define MAX3421_SCK_PIN  PICO_DEFAULT_SPI_SCK_PIN
+#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN
+#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN
+#define MAX3421_CS_PIN   10
+#define MAX3421_INTR_PIN 9
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 5ac104688..cffb632f3 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -37,10 +37,19 @@
 #include "bsp/board_api.h"
 #include "board.h"
 
+#ifdef UART_DEV
+static uart_inst_t *uart_inst;
+#endif
+
 #if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
 #include "pio_usb.h"
 #endif
 
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+#include "hardware/spi.h"
+static void max3421_init(void);
+#endif
+
 #ifdef BUTTON_BOOTSEL
 // This example blinks the Picoboard LED when the BOOTSEL button is pressed.
 //
@@ -53,73 +62,66 @@
 // This doesn't work if others are trying to access flash at the same time,
 // e.g. XIP streamer, or the other core.
 bool __no_inline_not_in_flash_func(get_bootsel_button)(void) {
-    const uint CS_PIN_INDEX = 1;
+  const uint CS_PIN_INDEX = 1;
 
-    // Must disable interrupts, as interrupt handlers may be in flash, and we
-    // are about to temporarily disable flash access!
-    uint32_t flags = save_and_disable_interrupts();
+  // Must disable interrupts, as interrupt handlers may be in flash, and we
+  // are about to temporarily disable flash access!
+  uint32_t flags = save_and_disable_interrupts();
 
-    // Set chip select to Hi-Z
-    hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
-                    GPIO_OVERRIDE_LOW << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
-                    IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
+  // Set chip select to Hi-Z
+  hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
+                  GPIO_OVERRIDE_LOW << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
+                  IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
 
-    // Note we can't call into any sleep functions in flash right now
-    for (volatile int i = 0; i < 1000; ++i);
+  // Note we can't call into any sleep functions in flash right now
+  for (volatile int i = 0; i < 1000; ++i);
 
-    // The HI GPIO registers in SIO can observe and control the 6 QSPI pins.
-    // Note the button pulls the pin *low* when pressed.
-    bool button_state = (sio_hw->gpio_hi_in & (1u << CS_PIN_INDEX));
+  // The HI GPIO registers in SIO can observe and control the 6 QSPI pins.
+  // Note the button pulls the pin *low* when pressed.
+  bool button_state = (sio_hw->gpio_hi_in & (1u << CS_PIN_INDEX));
 
-    // Need to restore the state of chip select, else we are going to have a
-    // bad time when we return to code in flash!
-    hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
-                    GPIO_OVERRIDE_NORMAL << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
-                    IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
+  // Need to restore the state of chip select, else we are going to have a
+  // bad time when we return to code in flash!
+  hw_write_masked(&ioqspi_hw->io[CS_PIN_INDEX].ctrl,
+                  GPIO_OVERRIDE_NORMAL << IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB,
+                  IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS);
 
-    restore_interrupts(flags);
+  restore_interrupts(flags);
 
-    return button_state;
+  return button_state;
 }
 #endif
 
 //------------- Segger RTT retarget -------------//
 #if defined(LOGGER_RTT)
-
 // Logging with RTT
 // - If RTT Control Block is not found by 'Auto Detection` try to use 'Search Range` with '0x20000000 0x10000'
 // - SWD speed is rather slow around 1000Khz
-
 #include "pico/stdio/driver.h"
 #include "SEGGER_RTT.h"
 
-static void stdio_rtt_write (const char *buf, int length)
-{
+static void stdio_rtt_write (const char *buf, int length) {
   SEGGER_RTT_Write(0, buf, (unsigned) length);
 }
 
-static int stdio_rtt_read (char *buf, int len)
-{
+static int stdio_rtt_read (char *buf, int len) {
   return (int) SEGGER_RTT_Read(0, buf, (unsigned) len);
 }
 
-static stdio_driver_t stdio_rtt =
-{
+static stdio_driver_t stdio_rtt = {
   .out_chars = stdio_rtt_write,
   .out_flush = NULL,
   .in_chars = stdio_rtt_read
 };
 
-void stdio_rtt_init(void)
-{
+void stdio_rtt_init(void) {
   stdio_set_driver_enabled(&stdio_rtt, true);
 }
-
 #endif
 
-#ifdef UART_DEV
-static uart_inst_t *uart_inst;
-#endif
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 
 void board_init(void)
 {
@@ -165,7 +167,9 @@ void board_init(void)
 #endif
 
 #if CFG_TUH_ENABLED
-  // set portfunc to host !!!
+  #if CFG_TUH_MAX3421
+  max3421_init();
+  #endif
 #endif
 
 #if !CFG_TUD_ENABLED && !CFG_TUH_ENABLED
@@ -242,3 +246,69 @@ int board_getchar(void) {
 // rp2040 implementation will install appropriate handler when initializing
 // tinyusb. There is no need to forward IRQ from application
 //--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+void max3421_int_handler(uint gpio, uint32_t event_mask) {
+  if (!(gpio == MAX3421_INTR_PIN && event_mask & GPIO_IRQ_EDGE_FALL)) return;
+  tuh_int_handler(BOARD_TUH_RHPORT, true);
+}
+
+static void max3421_init(void) {
+  // CS pin
+  gpio_init(MAX3421_CS_PIN);
+  gpio_set_dir(MAX3421_CS_PIN, GPIO_OUT);
+  gpio_put(MAX3421_CS_PIN, true);
+
+  // Interrupt pin
+  gpio_init(MAX3421_INTR_PIN);
+  gpio_set_dir(MAX3421_INTR_PIN, GPIO_IN);
+  gpio_pull_up(MAX3421_INTR_PIN);
+  gpio_set_irq_enabled_with_callback(MAX3421_INTR_PIN, GPIO_IRQ_EDGE_FALL, true, max3421_int_handler);
+
+  // SPI init
+  spi_init(MAX3421_SPI, 4*1000000ul);
+  gpio_set_function(MAX3421_SCK_PIN, GPIO_FUNC_SPI);
+  gpio_set_function(MAX3421_MOSI_PIN, GPIO_FUNC_SPI);
+  gpio_set_function(MAX3421_MISO_PIN, GPIO_FUNC_SPI);
+  spi_set_format(MAX3421_SPI, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
+}
+
+//// API to enable/disable MAX3421 INTR pin interrupt
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+  irq_set_enabled(IO_IRQ_BANK0, enabled);
+}
+
+// API to control MAX3421 SPI CS
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_put(MAX3421_CS_PIN, !active);
+}
+
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
+  (void) rhport;
+
+  if (tx_buf == NULL && rx_buf == NULL) {
+    return false;
+  }
+
+  int ret;
+
+  if (tx_buf == NULL) {
+    ret = spi_read_blocking(MAX3421_SPI, 0, rx_buf, xfer_bytes);
+  }else if (rx_buf == NULL) {
+    ret = spi_write_blocking(MAX3421_SPI, tx_buf, xfer_bytes);
+  }else {
+    ret = spi_write_read_blocking(spi0, tx_buf, rx_buf, xfer_bytes);
+  }
+
+  return ret == (int) xfer_bytes;
+}
+
+#endif
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 77d8029d9..ec40806fd 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -103,6 +103,20 @@ target_compile_definitions(tinyusb_host_base INTERFACE
 		RP2040_USB_HOST_MODE=1
 )
 
+#------------------------------------
+# Host MAX3421
+#------------------------------------
+add_library(tinyusb_host_max3421 INTERFACE)
+target_sources(tinyusb_host_max3421 INTERFACE
+	${TOP}/src/portable/analog/max3421/hcd_max3421.c
+	)
+target_compile_definitions(tinyusb_host_max3421 INTERFACE
+	CFG_TUH_MAX3421=1
+	)
+target_link_libraries(tinyusb_host_max3421 INTERFACE
+	hardware_spi
+	)
+
 #------------------------------------
 # BSP & Additions
 #------------------------------------
@@ -126,7 +140,7 @@ target_compile_definitions(tinyusb_additions INTERFACE
 if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
 	target_compile_definitions(tinyusb_additions INTERFACE
 			LOGGER_RTT
-			SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
+			#SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
 	)
 
 	target_sources(tinyusb_additions INTERFACE
@@ -186,6 +200,7 @@ function(family_add_pico_pio_usb TARGET)
 	target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
 endfunction()
 
+
 # since Pico-PIO_USB compiler support may lag, and change from version to version, add a function that pico-sdk/pico-examples
 # can check (if present) in case the user has updated their TinyUSB
 function(is_compiler_supported_by_pico_pio_usb OUTVAR)
@@ -209,6 +224,11 @@ function(family_configure_host_example TARGET RTOS)
 			family_add_pico_pio_usb(${PROJECT})
 		endif()
 	endif()
+
+	# for max3421 host
+	if (MAX3421_HOST STREQUAL "1")
+		target_link_libraries(${TARGET} PUBLIC tinyusb_host_max3421)
+	endif()
 endfunction()
 
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 051b7eaa8..cc4799dd6 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -171,6 +171,8 @@ enum {
 //--------------------------------------------------------------------+
 
 typedef struct {
+  uint8_t daddr;
+
   struct TU_ATTR_PACKED {
     uint8_t ep_dir        : 1;
     uint8_t is_iso        : 1;
@@ -179,17 +181,19 @@ typedef struct {
     uint8_t xfer_pending  : 1;
     uint8_t xfer_complete : 1;
   };
+
   struct TU_ATTR_PACKED {
-    uint8_t daddr : 4;
     uint8_t ep_num : 4;
+    uint16_t packet_size : 12;
   };
 
-  uint16_t packet_size;
   uint16_t total_len;
   uint16_t xferred_len;
   uint8_t* buf;
 } max3421_ep_t;
 
+TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct");
+
 typedef struct {
   // cached register
   uint8_t sndbc;
@@ -320,7 +324,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
 static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
   reg_write(rhport, HIRQ_ADDR, data, in_isr);
   // HIRQ write 1 is clear
-  _hcd_data.hirq &= ~data;
+  _hcd_data.hirq &= (uint8_t) ~data;
 }
 
 static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
@@ -390,7 +394,7 @@ static void free_ep(uint8_t daddr) {
 }
 
 static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
-  size_t const idx = cur_ep - _hcd_data.ep;
+  size_t const idx = (size_t) (cur_ep - _hcd_data.ep);
 
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
@@ -537,8 +541,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
   (void) rhport;
   (void) daddr;
 
-  uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
-  uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
+  uint8_t const ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
+  tusb_dir_t const ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
 
   max3421_ep_t * ep;
   if (daddr == 0 && ep_num == 0) {
@@ -547,15 +551,15 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
     ep = allocate_ep();
     TU_ASSERT(ep);
     ep->daddr = daddr;
-    ep->ep_num = ep_num;
-    ep->ep_dir = ep_dir;
+    ep->ep_num = (uint8_t) (ep_num & 0x0f);
+    ep->ep_dir = (ep_dir == TUSB_DIR_IN) ? 1 : 0;
   }
 
   if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) {
     ep->is_iso = 1;
   }
 
-  ep->packet_size = tu_edpt_packet_size(ep_desc);
+  ep->packet_size = (uint16_t) (tu_edpt_packet_size(ep_desc) & 0x7ff);
 
   return true;
 }
@@ -577,7 +581,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   }
   sndbc_write(rhport, xact_len, in_isr);
 
-  uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
+  uint8_t const hxfr = (uint8_t ) (ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0));
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -590,7 +594,7 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
+  uint8_t const hxfr = (uint8_t) (ep->ep_num | (ep->is_iso ? HXFR_ISO : 0));
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -623,13 +627,13 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   uint8_t const ep_num = tu_edpt_number(ep_addr);
-  uint8_t const ep_dir = tu_edpt_dir(ep_addr);
+  uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
 
   max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
   TU_VERIFY(ep);
 
   // control transfer can switch direction
-  ep->ep_dir = ep_dir;
+  ep->ep_dir = ep_dir ? 1u : 0u;
 
   ep->buf = buffer;
   ep->total_len = buflen;
@@ -748,9 +752,9 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
 
   // save data toggle
   if (ep->ep_dir) {
-    ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+    ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1u : 0u;
   }else {
-    ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+    ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1u : 0u;
   }
 
   ep->xfer_pending = 0;
@@ -929,7 +933,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
   }
 
   // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
-  hirq &= ~HIRQ_SNDBAV_IRQ;
+  hirq &= (uint8_t) ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
     hirq_write(rhport, hirq, in_isr);
   }
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 4ed6d36bb..08aef9314 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB && !CFG_TUH_MAX3421
 
 #include "pico.h"
 #include "rp2040_usb.h"
-- 
cgit v1.3.1


From c2bbcc9f60a2b7293fad4e24468d3f045fde28ee Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 26 Dec 2023 20:14:03 +0100
Subject: initial support of CH34x CDC device

---
 examples/host/cdc_msc_hid/src/tusb_config.h        |   1 +
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    |   1 +
 src/class/cdc/cdc_host.c                           | 466 ++++++++++++++++++++-
 src/class/cdc/serial/ch34x.h                       | 113 +++++
 src/tusb_option.h                                  |  17 +
 5 files changed, 595 insertions(+), 3 deletions(-)
 create mode 100644 src/class/cdc/serial/ch34x.h

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 61abb85eb..76d59c316 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -105,6 +105,7 @@
 #define CFG_TUH_CDC                 1 // CDC ACM
 #define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index c661f47be..bb7c3388d 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -110,6 +110,7 @@
 #define CFG_TUH_CDC                 1 // CDC ACM
 #define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index a6dfb45ae..9b5186e0c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 Heiko Kuester (CH34x support)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -69,7 +70,16 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-
+  #if CFG_TUH_CDC_CH34X
+  struct {
+    uint32_t  baud_rate;
+    uint8_t   mcr;
+    uint8_t   msr;
+    uint8_t   lcr;
+    uint32_t  quirks;
+    uint8_t   version;
+  } ch34x;
+  #endif
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -121,6 +131,23 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
+//------------- CH34x prototypes -------------//
+#if CFG_TUH_CDC_CH34X
+#include "serial/ch34x.h"
+
+static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
+enum {
+  CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] )
+};
+
+static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
+static void ch34x_process_config ( tuh_xfer_t* xfer );
+
+static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
+#endif
+
+
 enum {
   SERIAL_DRIVER_ACM = 0,
 
@@ -131,6 +158,10 @@ enum {
 #if CFG_TUH_CDC_CP210X
   SERIAL_DRIVER_CP210X,
 #endif
+
+#if CFG_TUH_CDC_CH34X
+  SERIAL_DRIVER_CH34X,
+#endif
 };
 
 typedef struct {
@@ -159,6 +190,13 @@ static const cdch_serial_driver_t serial_drivers[] = {
     .set_baudrate           = cp210x_set_baudrate
   },
   #endif
+
+  #if CFG_TUH_CDC_CH34X
+  { .process_set_config     = ch34x_process_config,
+    .set_control_line_state = ch34x_set_modem_ctrl,
+    .set_baudrate           = ch34x_set_baudrate
+  },
+#endif
 };
 
 enum {
@@ -426,6 +464,12 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
         break;
       #endif
 
+      #if CFG_TUH_CDC_CH34X
+      case SERIAL_DRIVER_CH34X:
+        TU_ASSERT(false, ); // see special ch34x_control_complete function
+        break;
+      #endif
+
       default: break;
     }
   }
@@ -641,7 +685,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
   {
     return acm_open(daddr, itf_desc, max_len);
   }
-  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
+  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
   else if ( 0xff == itf_desc->bInterfaceClass )
   {
     uint16_t vid, pid;
@@ -666,8 +710,16 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
       }
     }
     #endif
+
+    #if CFG_TUH_CDC_CH34X
+    for (size_t i = 0; i < CH34X_VID_PID_COUNT; i++) {
+      if ( ch34x_vids_pids[i][0] == vid && ch34x_vids_pids[i][1] == pid ) {
+        return ch34x_open(daddr, itf_desc, max_len);
+      }
+    }
+    #endif
   }
-  #endif
+  #endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
 
   return false;
 }
@@ -1176,4 +1228,412 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 #endif
 
+//--------------------------------------------------------------------+
+// CH34x
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_CDC_CH34X
+
+enum {
+  CONFIG_CH34X_STEP1 = 0,
+  CONFIG_CH34X_STEP2,
+  CONFIG_CH34X_STEP3,
+  CONFIG_CH34X_STEP4,
+  CONFIG_CH34X_STEP5,
+  CONFIG_CH34X_STEP6,
+  CONFIG_CH34X_STEP7,
+  CONFIG_CH34X_STEP8,
+  CONFIG_CH34X_COMPLETE
+};
+
+static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len )
+{
+  // CH34x Interface includes 1 vendor interface + 3 bulk endpoints
+  TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
+  TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
+
+  cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc );
+  TU_VERIFY ( p_cdc );
+
+  TU_LOG_DRV ( "CH34x opened\r\n" );
+  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc );
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair ( p_cdc, desc_ep );
+}
+
+static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  tusb_control_request_t const request_setup = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_VENDOR,
+          .direction = direction
+      },
+      .bRequest = request,
+      .wValue   = tu_htole16 ( value ),
+      .wIndex   = tu_htole16 ( index ),
+      .wLength  = tu_htole16 ( length )
+  };
+
+  // use usbh enum buf since application variable does not live long enough
+  uint8_t* enum_buf = NULL;
+
+  if ( buffer && length > 0 ) {
+    enum_buf = usbh_get_enum_buf();
+    tu_memcpy_s ( enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length );
+  }
+
+  tuh_xfer_t xfer = {
+      .daddr       = p_cdc->daddr,
+      .ep_addr     = 0,
+      .setup       = &request_setup,
+      .buffer      = enum_buf,
+      .complete_cb = complete_cb,
+      // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
+      .user_data   = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff )
+  };
+
+  return tuh_control_xfer ( &xfer );
+  return false;
+}
+
+static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
+}
+
+static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
+}
+
+static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
+}
+
+static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
+}
+
+/*
+ * The device line speed is given by the following equation:
+ *
+ *  baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
+ *
+ *    0 <= ps <= 3,
+ *    0 <= fact <= 1,
+ *    2 <= div <= 256 if fact = 0, or
+ *    9 <= div <= 256 if fact = 1
+ */
+// calculate baudrate devisors
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
+{
+  uint32_t fact, div, clk_div;
+  bool force_fact0 = false;
+  int32_t ps;
+  static const uint32_t ch341_min_rates[] = {
+      CH341_MIN_RATE(0),
+      CH341_MIN_RATE(1),
+      CH341_MIN_RATE(2),
+      CH341_MIN_RATE(3),
+  };
+
+  /*
+   * Clamp to supported range, this makes the (ps < 0) and (div < 2)
+   * sanity checks below redundant.
+   */
+  inline uint32_t max       ( uint32_t val,                  uint32_t maxval ) { return val > maxval ? val : maxval; }
+  inline uint32_t min       ( uint32_t val, uint32_t minval                  ) { return val < minval ? val : minval; }
+  inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); }
+  speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS);
+
+  /*
+   * Start with highest possible base clock (fact = 1) that will give a
+   * divisor strictly less than 512.
+   */
+  fact = 1;
+  for (ps = 3; ps >= 0; ps--) {
+    if (speed > ch341_min_rates[ps])
+      break;
+  }
+
+  if (ps < 0)
+    return -EINVAL;
+
+  /* Determine corresponding divisor, rounding down. */
+  clk_div = CH341_CLK_DIV(ps, fact);
+  div = CH341_CLKRATE / (clk_div * speed);
+
+  /* Some devices require a lower base clock if ps < 3. */
+  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
+    force_fact0 = true;
+
+  /* Halve base clock (fact = 0) if required. */
+  if (div < 9 || div > 255 || force_fact0) {
+    div /= 2;
+    clk_div *= 2;
+    fact = 0;
+  }
+
+  if (div < 2)
+    return -EINVAL;
+
+  /*
+   * Pick next divisor if resulting rate is closer to the requested one,
+   * scale up to avoid rounding errors on low rates.
+   */
+  if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
+      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
+    div++;
+
+  /*
+   * Prefer lower base clock (fact = 0) if even divisor.
+   *
+   * Note that this makes the receiver more tolerant to errors.
+   */
+  if (fact == 1 && div % 2 == 0) {
+    div /= 2;
+    fact = 0;
+  }
+
+  return (0x100 - div) << 8 | fact << 2 | ps;
+}
+
+// set baudrate (low level)
+// do not confuse with ch34x_set_baudrate
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  int val;
+
+  if (!baud_rate)
+    return -EINVAL;
+
+  val = ch341_get_divisor(p_cdc, baud_rate);
+  if (val < 0)
+    return -EINVAL;
+
+  /*
+   * CH341A buffers data until a full endpoint-size packet (32 bytes)
+   * has been received unless bit 7 is set.
+   *
+   * At least one device with version 0x27 appears to have this bit
+   * inverted.
+   */
+  if ( p_cdc->ch34x.version > 0x27 )
+    val |= BIT(7);
+
+  return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
+}
+
+// set lcr register
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  /*
+   * Chip versions before version 0x30 as read using
+   * CH341_REQ_READ_VERSION used separate registers for line control
+   * (stop bits, parity and word length). Version 0x30 and above use
+   * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
+   */
+  if ( p_cdc->ch34x.version < 0x30 )
+    return 0;
+
+  return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
+}
+
+// set handshake (modem controls)
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
+}
+
+// detect quirks (special versions of CH34x)
+// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  /*
+   * A subset of CH34x devices does not support all features. The
+   * prescaler is limited and there is no support for sending a RS232
+   * break condition. A read failure when trying to set up the latter is
+   * used to detect these devices.
+   */
+  switch ( step )
+  {
+  case 1:
+    p_cdc->ch34x.quirks = 0;
+    return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
+    break;
+  case 2:
+    if ( xfer->result != XFER_RESULT_SUCCESS )
+      p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
+    return true;
+    break;
+  default:
+    TU_ASSERT ( false ); // suspicious step
+    break;
+  }
+}
+
+// internal control complete to update state such as line state, encoding
+// CH34x needs a special interface recovery due to abnormal wIndex usage
+static void ch34x_control_complete(tuh_xfer_t* xfer)
+{
+  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
+  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
+  cdch_interface_t  *p_cdc  = get_itf ( idx );
+  TU_ASSERT ( p_cdc, );
+  TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
+
+  if (xfer->result == XFER_RESULT_SUCCESS) {
+    switch (xfer->setup->bRequest) {
+    case CH341_REQ_WRITE_REG: { // register write request
+      switch ( tu_le16toh ( xfer->setup->wValue ) ) {
+      case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
+        p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+        break;
+      }
+      default: {
+        TU_ASSERT(false, ); // unexpected register write
+        break;
+      }
+      }
+      break;
+    }
+    default: {
+      TU_ASSERT(false, ); // unexpected request
+      break;
+    }
+    }
+    xfer->complete_cb = p_cdc->user_control_cb;
+    if (xfer->complete_cb)
+      xfer->complete_cb(xfer);
+  }
+}
+
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
+{
+  TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
+  uint32_t baud_le = tu_htole32(baudrate);
+  p_cdc->ch34x.baud_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
+  return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
+}
+
+static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
+  // todo later
+  return false;
+}
+
+static void ch34x_process_config ( tuh_xfer_t* xfer )
+{
+  uintptr_t const   state   = xfer->user_data & 0xff;
+  // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
+  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
+  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
+  cdch_interface_t  *p_cdc  = get_itf ( idx );
+  uint8_t           buffer [ CH34X_BUFFER_SIZE ];
+  cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+  TU_ASSERT ( p_cdc, );
+
+  if ( state == 0 ) {
+    // defaults
+    p_cdc->ch34x.baud_rate = DEFAULT_BAUD_RATE;
+    p_cdc->ch34x.mcr = 0;
+    p_cdc->ch34x.msr = 0;
+    p_cdc->ch34x.quirks = 0;
+    p_cdc->ch34x.version = 0;
+    /*
+     * Some CH340 devices appear unable to change the initial LCR
+     * settings, so set a sane 8N1 default.
+     */
+    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
+  }
+  // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
+  switch ( state ) {
+  case CONFIG_CH34X_STEP1: // request version read
+    TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
+    break;
+  case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
+    p_cdc->ch34x.version = xfer->buffer[0];
+    TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
+    TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
+    break;
+  case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
+    TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
+    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
+    TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP6: // detect quirks step 1
+    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
+    break;
+  case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
+    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+    TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
+#else
+    TU_ATTR_FALLTHROUGH;
 #endif
+    break;
+  case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
+    switch ( line_coding.data_bits ) {
+    case 5:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+      break;
+    case 6:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+      break;
+    case 7:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+      break;
+    case 8:
+      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      break;
+    default:
+      TU_ASSERT ( false, ); // not supported data_bits
+      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      break;
+    }
+    if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
+      p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
+      if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
+        p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
+      if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
+        p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
+    }
+    TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
+    if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
+      p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
+    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
+#else
+    TU_ATTR_FALLTHROUGH;
+#endif
+    break;
+    case CONFIG_CH34X_COMPLETE:
+      set_config_complete ( p_cdc, idx, itf_num );
+      break;
+    default:
+      TU_ASSERT ( false, );
+      break;
+  }
+}
+
+#endif // CFG_TUH_CDC_CH34X
+
+#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC)
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
new file mode 100644
index 000000000..94e18b252
--- /dev/null
+++ b/src/class/cdc/serial/ch34x.h
@@ -0,0 +1,113 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Heiko Kuester (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CH34X_H_
+#define _CH34X_H_
+
+#include <stdint.h>
+
+#define BIT(nr) ( (uint32_t)1 << (nr) )
+
+#define CH34X_BUFFER_SIZE 2
+
+// The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c
+
+#define DEFAULT_BAUD_RATE 9600
+
+/* flags for IO-Bits */
+#define CH341_BIT_RTS (1 << 6)
+#define CH341_BIT_DTR (1 << 5)
+
+/******************************/
+/* interrupt pipe definitions */
+/******************************/
+/* always 4 interrupt bytes */
+/* first irq byte normally 0x08 */
+/* second irq byte base 0x7d + below */
+/* third irq byte base 0x94 + below */
+/* fourth irq byte normally 0xee */
+
+/* second interrupt byte */
+#define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
+
+/* status returned in third interrupt answer byte, inverted in data
+   from irq */
+#define CH341_BIT_CTS 0x01
+#define CH341_BIT_DSR 0x02
+#define CH341_BIT_RI  0x04
+#define CH341_BIT_DCD 0x08
+#define CH341_BITS_MODEM_STAT 0x0f /* all bits */
+
+/* Break support - the information used to implement this was gleaned from
+ * the Net/FreeBSD uchcom.c driver by Takanori Watanabe.  Domo arigato.
+ */
+
+// USB requests
+#define CH341_REQ_READ_VERSION 0x5F // dec 95
+#define CH341_REQ_WRITE_REG    0x9A
+#define CH341_REQ_READ_REG     0x95
+#define CH341_REQ_SERIAL_INIT  0xA1
+#define CH341_REQ_MODEM_CTRL   0xA4
+
+// CH34x registers
+#define CH341_REG_BREAK        0x05
+#define CH341_REG_PRESCALER    0x12
+#define CH341_REG_DIVISOR      0x13
+#define CH341_REG_LCR          0x18
+#define CH341_REG_LCR2         0x25
+
+#define CH341_NBREAK_BITS      0x01
+
+// line control bits
+#define CH341_LCR_ENABLE_RX    0x80
+#define CH341_LCR_ENABLE_TX    0x40
+#define CH341_LCR_MARK_SPACE   0x20
+#define CH341_LCR_PAR_EVEN     0x10
+#define CH341_LCR_ENABLE_PAR   0x08
+#define CH341_LCR_STOP_BITS_2  0x04
+#define CH341_LCR_CS8          0x03
+#define CH341_LCR_CS7          0x02
+#define CH341_LCR_CS6          0x01
+#define CH341_LCR_CS5          0x00
+
+#define CH341_QUIRK_LIMITED_PRESCALER BIT(0)
+#define CH341_QUIRK_SIMULATE_BREAK  BIT(1)
+
+#define CH341_CLKRATE   48000000
+#define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
+#define CH341_MIN_RATE(ps)  (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512))
+
+/* Supported range is 46 to 3000000 bps. */
+#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
+#define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2))
+
+#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
+#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+
+// error codes
+#define EINVAL    22  /* Invalid argument */
+
+#endif /* _CH34X_H_ */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a76281c0c..13151a07b 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -470,6 +470,23 @@
     0xEA60, 0xEA70
 #endif
 
+#ifndef CFG_TUH_CDC_CH34X
+  // CH34X is not part of CDC class, only to re-use CDC driver API
+  #define CFG_TUH_CDC_CH34X 0
+#endif
+
+#ifndef CFG_TUH_CDC_CH34X_VID_PID_LIST
+  // List of product IDs that can use the CH34X CDC driver
+  #define CFG_TUH_CDC_CH34X_VID_PID_LIST \
+    { 0x1a86, 0x7523 }, /* ch340 chip */ \
+    { 0x1a86, 0x7522 }, /* ch340k chip */ \
+    { 0x1a86, 0x5523 }, /* ch341 chip */ \
+    { 0x1a86, 0xe523 }, /* ch330 chip */ \
+    { 0x4348, 0x5523 }, /* ch340 custom chip */ \
+    { 0x2184, 0x0057 }, /* overtaken from Linux driver /drivers/usb/serial/ch341.c */ \
+    { 0x9986, 0x7523 }  /* overtaken from Linux driver /drivers/usb/serial/ch341.c */
+#endif
+
 #ifndef CFG_TUH_HID
   #define CFG_TUH_HID    0
 #endif
-- 
cgit v1.3.1


From 9a1559a35653e34c2fc8b4dccdc9f40ad476913c Mon Sep 17 00:00:00 2001
From: YixingShen <kkman3651878@hotmail.com>
Date: Thu, 28 Dec 2023 00:28:24 +0800
Subject: add __ARM_ARCH_8_1M_MAIN__ for M55

---
 src/common/tusb_verify.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 1b5f53dfc..8aa66b4df 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -75,8 +75,8 @@
   #define _MESS_FAILED() do {} while (0)
 #endif
 
-// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)
   #define TU_BREAKPOINT() do                                                                                \
   {                                                                                                         \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
-- 
cgit v1.3.1


From a4aa454a7a21c022569eccfea493b8a96d182d9c Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sun, 7 Jan 2024 08:25:31 +1030
Subject: [HUB] Fix double status xfer

---
 src/host/hub.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/host/hub.c b/src/host/hub.c
index 32f5e0ac7..3bac18698 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -435,9 +435,12 @@ static void hub_port_get_status_complete (tuh_xfer_t* xfer)
     // Other changes are: L1 state
     // TODO clear change
 
-    // prepare for next hub status
-    // TODO continue with status_change, or maybe we can do it again with status
-    hub_edpt_status_xfer(daddr);
+    else
+    {
+      // prepare for next hub status
+      // TODO continue with status_change, or maybe we can do it again with status
+      hub_edpt_status_xfer(daddr);
+    }
   }
 }
 
-- 
cgit v1.3.1


From d39d06e6d920aadc9e479d4dfb8620dd3871cb98 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Tue, 9 Jan 2024 16:22:54 +1030
Subject: [HUB] Prevent status request to invalid ep_num

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4d30d9f81..53e8a654b 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -456,7 +456,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
 
         #if CFG_TUH_HUB
         // TODO remove
-        if ( event.connection.hub_addr != 0) {
+        if ( event.connection.hub_addr != 0 && event.connection.hub_port != 0) {
           // done with hub, waiting for next data on status pipe
           (void) hub_edpt_status_xfer( event.connection.hub_addr );
         }
-- 
cgit v1.3.1


From 91f65a36bfb1d4516c39306e77fb15d4e1c2fc0b Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 9 Jan 2024 09:53:54 +0100
Subject: [CDC] host: moved acm_open to other acm prototypes

---
 src/class/cdc/cdc_host.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index a6dfb45ae..b20da3723 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -80,6 +80,7 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC];
 //--------------------------------------------------------------------+
 
 //------------- ACM prototypes -------------//
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void acm_process_config(tuh_xfer_t* xfer);
 
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
@@ -605,8 +606,6 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
-
 static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep)
 {
   for(size_t i=0; i<2; i++)
-- 
cgit v1.3.1


From 0d4b24e56cf11e79b46f88f0d8b8656c0444a149 Mon Sep 17 00:00:00 2001
From: Okarss <104319900+Okarss@users.noreply.github.com>
Date: Sun, 7 Jan 2024 20:18:33 +0200
Subject: [STM32 FSDEV] Fix ISR race conditions

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 21cd3da26..5f7944d1f 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -673,13 +673,13 @@ void dcd_int_handler(uint8_t rhport) {
 
   /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
   if(int_status & USB_ISTR_SOF) {
-    USB->ISTR &=~USB_ISTR_SOF;
+    USB->ISTR = ~USB_ISTR_SOF;
     dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
   }
 
   if(int_status & USB_ISTR_RESET) {
     // USBRST is start of reset.
-    USB->ISTR &=~USB_ISTR_RESET;
+    USB->ISTR = ~USB_ISTR_RESET;
     dcd_handle_bus_reset();
     dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
     return; // Don't do the rest of the things here; perhaps they've been cleared?
@@ -697,7 +697,7 @@ void dcd_int_handler(uint8_t rhport) {
     USB->CNTR &= ~USB_CNTR_LPMODE;
     USB->CNTR &= ~USB_CNTR_FSUSP;
 
-    USB->ISTR &=~USB_ISTR_WKUP;
+    USB->ISTR = ~USB_ISTR_WKUP;
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
 
@@ -711,7 +711,7 @@ void dcd_int_handler(uint8_t rhport) {
     USB->CNTR |= USB_CNTR_LPMODE;
 
     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-    USB->ISTR &=~USB_ISTR_SUSP;
+    USB->ISTR = ~USB_ISTR_SUSP;
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 
@@ -724,7 +724,7 @@ void dcd_int_handler(uint8_t rhport) {
     {
       remoteWakeCountdown--;
     }
-    USB->ISTR &=~USB_ISTR_ESOF;
+    USB->ISTR = ~USB_ISTR_ESOF;
   }
 }
 
-- 
cgit v1.3.1


From e7e19f562765999ed76b25b93649e80d9652b088 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sun, 7 Jan 2024 08:30:33 +1030
Subject: [OHCI] Allow more than 16 devices

---
 src/portable/ohci/ohci.c | 16 +++++++++++++---
 src/portable/ohci/ohci.h | 16 +++++++++++++---
 2 files changed, 26 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index f978b0965..c7f4c04ad 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -157,6 +157,7 @@ static ohci_ed_t * const p_ed_head[] =
 
 static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed);
 static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr);
+static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd);
 
 //--------------------------------------------------------------------+
 // USBH-HCD API
@@ -345,7 +346,7 @@ static void gtd_init(ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes)
   tu_memclr(p_td, sizeof(ohci_gtd_t));
 
   p_td->used = 1;
-  p_td->expected_bytes = total_bytes;
+  gtd_get_extra_data(p_td)->expected_bytes = total_bytes;
 
   p_td->buffer_rounding = 1; // less than queued length is not a error
   p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO;
@@ -610,6 +611,16 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
   }
 }
 
+static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd) {
+  if ( gtd_is_control(gtd) )
+  {
+    return &ohci_data.control[((intptr_t)gtd - (intptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0])].gtd_data;
+  }else
+  {
+    return &ohci_data.gtd_data[gtd - ohci_data.gtd_pool];
+  }
+}
+
 static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer)
 {
   // 5.2.9 OHCI sample code
@@ -641,8 +652,7 @@ static void done_queue_isr(uint8_t hostid)
     if ( (qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
     {
       ohci_ed_t * const ed  = gtd_get_ed(qtd);
-
-      uint32_t const xferred_bytes = qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer);
+      uint32_t const xferred_bytes = gtd_get_extra_data(qtd)->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer);
 
       // NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs.
       // When there is a error resulting this ED is halted, and this EP still has other queued TD
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 2081ffabb..cb23396bc 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -45,6 +45,9 @@ enum {
 #define ED_MAX       (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
 #define GTD_MAX      ED_MAX
 
+// tinyUSB's OHCI implementation caps number of EDs to 8 bits
+TU_VERIFY_STATIC (ED_MAX <= 256, "Reduce CFG_TUH_DEVICE_MAX or CFG_TUH_ENDPOINT_MAX");
+
 //--------------------------------------------------------------------+
 // OHCI Data Structure
 //--------------------------------------------------------------------+
@@ -70,9 +73,8 @@ typedef struct TU_ATTR_ALIGNED(16)
 {
 	// Word 0
 	uint32_t used                    : 1;
-	uint32_t index                   : 4;  // endpoint index the td belongs to, or device address in case of control xfer
-  uint32_t expected_bytes          : 13; // TODO available for hcd
-
+  uint32_t index                   : 8; // endpoint index the gtd belongs to, or device address in case of control xfer
+  uint32_t                         : 9; // can be used
   uint32_t buffer_rounding         : 1;
   uint32_t pid                     : 2;
   uint32_t delay_interrupt         : 3;
@@ -152,6 +154,12 @@ typedef struct TU_ATTR_ALIGNED(32)
 
 TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" );
 
+typedef struct
+{
+  uint16_t expected_bytes : 13; // can be up to 8192 bytes long so use 13 bits
+  uint16_t                : 3; // can be used
+} gtd_extra_data_t;
+
 // structure with member alignment required from large to small
 typedef struct TU_ATTR_ALIGNED(256)
 {
@@ -164,11 +172,13 @@ typedef struct TU_ATTR_ALIGNED(256)
   struct {
     ohci_ed_t ed;
     ohci_gtd_t gtd;
+    gtd_extra_data_t gtd_data;
   }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
   ohci_ed_t ed_pool[ED_MAX];
   ohci_gtd_t gtd_pool[GTD_MAX];
+  gtd_extra_data_t gtd_data[GTD_MAX]; // extra data needed by TDs that can't fit in the TD struct
 
   volatile uint16_t frame_number_hi;
 
-- 
cgit v1.3.1


From 3bf6826451536f1afc6eb4e7f088ac65d9b8c707 Mon Sep 17 00:00:00 2001
From: Alex Voinea <voinea.dragos.alexandru@gmail.com>
Date: Wed, 10 Jan 2024 10:27:21 +0100
Subject: Disable ULPI clock during sleep on stm32f7 when using internal phy

---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index dd78ccd06..3237a50f6 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -149,7 +149,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
     // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
     // H7 running on full-speed phy need to disable ULPI clock in sleep mode.
     // Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS.
-    // Note: there may be other family that is affected by this, but only H7 is tested so far
+    // Note: there may be other family that is affected by this, but only H7 and F7 is tested so far
     #if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN)
     if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) {
       RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN;
@@ -161,6 +161,13 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
       RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN;
     }
     #endif
+
+    #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_OTGHSULPILPEN)
+    if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) {
+      RCC->AHB1LPENR &= ~RCC_AHB1LPENR_OTGHSULPILPEN;
+    }
+    #endif
+
   } else {
 #if CFG_TUSB_MCU != OPT_MCU_STM32U5
     // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
-- 
cgit v1.3.1


From 545821399b10243f84509a543ae8c6457e9da803 Mon Sep 17 00:00:00 2001
From: Okarss <104319900+Okarss@users.noreply.github.com>
Date: Thu, 11 Jan 2024 00:59:39 +0200
Subject: [STM32 FSDEV] Introduce a typedef for bus access width

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 10 +++++-----
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h |  3 +++
 2 files changed, 8 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 5f7944d1f..91f90352e 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -673,13 +673,13 @@ void dcd_int_handler(uint8_t rhport) {
 
   /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
   if(int_status & USB_ISTR_SOF) {
-    USB->ISTR = ~USB_ISTR_SOF;
+    USB->ISTR = (fsdev_bus_t)~USB_ISTR_SOF;
     dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
   }
 
   if(int_status & USB_ISTR_RESET) {
     // USBRST is start of reset.
-    USB->ISTR = ~USB_ISTR_RESET;
+    USB->ISTR = (fsdev_bus_t)~USB_ISTR_RESET;
     dcd_handle_bus_reset();
     dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
     return; // Don't do the rest of the things here; perhaps they've been cleared?
@@ -697,7 +697,7 @@ void dcd_int_handler(uint8_t rhport) {
     USB->CNTR &= ~USB_CNTR_LPMODE;
     USB->CNTR &= ~USB_CNTR_FSUSP;
 
-    USB->ISTR = ~USB_ISTR_WKUP;
+    USB->ISTR = (fsdev_bus_t)~USB_ISTR_WKUP;
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
 
@@ -711,7 +711,7 @@ void dcd_int_handler(uint8_t rhport) {
     USB->CNTR |= USB_CNTR_LPMODE;
 
     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-    USB->ISTR = ~USB_ISTR_SUSP;
+    USB->ISTR = (fsdev_bus_t)~USB_ISTR_SUSP;
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 
@@ -724,7 +724,7 @@ void dcd_int_handler(uint8_t rhport) {
     {
       remoteWakeCountdown--;
     }
-    USB->ISTR = ~USB_ISTR_ESOF;
+    USB->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF;
   }
 }
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index b71e4f498..d28eb0d9a 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -173,8 +173,11 @@
 // For type-safety create a new macro for the volatile address of PMAADDR
 // The compiler should warn us if we cast it to a non-volatile type?
 #ifdef PMA_32BIT_ACCESS
+typedef uint32_t fsdev_bus_t;
 static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR;
+
 #else
+typedef uint16_t fsdev_bus_t;
 // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
 static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 
-- 
cgit v1.3.1


From c619a861414d2edeb34c5f59b74ed0fe28b39172 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Thu, 11 Jan 2024 08:53:47 +0100
Subject: bInterfaceClass number replaced by define

---
 src/class/cdc/cdc_host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index b20da3723..79477ef53 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -641,7 +641,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     return acm_open(daddr, itf_desc, max_len);
   }
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
-  else if ( 0xff == itf_desc->bInterfaceClass )
+  else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
   {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
-- 
cgit v1.3.1


From e68c6658c954d0c5daed2952d500c230b7dfb30d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 Jan 2024 17:35:05 +0700
Subject: move gtd extra out of control struct to save sram

also rename gtd_data to gtd_extra
---
 src/portable/ohci/ohci.c | 13 ++++++-------
 src/portable/ohci/ohci.h | 18 ++++++++----------
 2 files changed, 14 insertions(+), 17 deletions(-)

(limited to 'src')

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index c7f4c04ad..c59d4755e 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -612,12 +612,11 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
 }
 
 static gtd_extra_data_t *gtd_get_extra_data(ohci_gtd_t const * const gtd) {
-  if ( gtd_is_control(gtd) )
-  {
-    return &ohci_data.control[((intptr_t)gtd - (intptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0])].gtd_data;
-  }else
-  {
-    return &ohci_data.gtd_data[gtd - ohci_data.gtd_pool];
+  if ( gtd_is_control(gtd) ) {
+    uint8_t idx = ((uintptr_t)gtd - (uintptr_t)&ohci_data.control->gtd) / sizeof(ohci_data.control[0]);
+    return &ohci_data.gtd_extra_control[idx];
+  }else {
+    return &ohci_data.gtd_extra[gtd - ohci_data.gtd_pool];
   }
 }
 
@@ -661,7 +660,7 @@ static void done_queue_isr(uint8_t hostid)
       // --> HC will not process Control list (due to service ratio when Bulk list not empty)
       // To walk-around this, the halted ED will have TailP = HeadP (empty list condition), when clearing halt
       // the TailP must be set back to NULL for processing remaining TDs
-      if ((event != XFER_RESULT_SUCCESS))
+      if (event != XFER_RESULT_SUCCESS)
       {
         ed->td_tail &= 0x0Ful;
         ed->td_tail |= tu_align16(ed->td_head.address); // mark halted EP as empty queue
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index cb23396bc..4feefd771 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -154,15 +154,12 @@ typedef struct TU_ATTR_ALIGNED(32)
 
 TU_VERIFY_STATIC( sizeof(ochi_itd_t) == 32, "size is not correct" );
 
-typedef struct
-{
-  uint16_t expected_bytes : 13; // can be up to 8192 bytes long so use 13 bits
-  uint16_t                : 3; // can be used
+typedef struct {
+  uint16_t expected_bytes; // up to 8192 bytes so max is 13 bits
 } gtd_extra_data_t;
 
 // structure with member alignment required from large to small
-typedef struct TU_ATTR_ALIGNED(256)
-{
+typedef struct TU_ATTR_ALIGNED(256) {
   ohci_hcca_t hcca;
 
   ohci_ed_t bulk_head_ed; // static bulk head (dummy)
@@ -172,16 +169,17 @@ typedef struct TU_ATTR_ALIGNED(256)
   struct {
     ohci_ed_t ed;
     ohci_gtd_t gtd;
-    gtd_extra_data_t gtd_data;
-  }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
+  } control[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1];
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
   ohci_ed_t ed_pool[ED_MAX];
   ohci_gtd_t gtd_pool[GTD_MAX];
-  gtd_extra_data_t gtd_data[GTD_MAX]; // extra data needed by TDs that can't fit in the TD struct
 
-  volatile uint16_t frame_number_hi;
+  // extra data needed by TDs that can't fit in the TD struct
+  gtd_extra_data_t gtd_extra_control[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1];
+  gtd_extra_data_t gtd_extra[GTD_MAX];
 
+  volatile uint16_t frame_number_hi;
 } ohci_data_t;
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 2d3d14891251baedfc965810c650615bdee128cf Mon Sep 17 00:00:00 2001
From: Okarss <104319900+Okarss@users.noreply.github.com>
Date: Thu, 11 Jan 2024 21:02:14 +0200
Subject: [STM32 FSDEV] Align names for consistency

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c      | 30 +++++-----
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h        | 65 +++++++++++-----------
 2 files changed, 48 insertions(+), 47 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 91f90352e..9c37f1f98 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -128,8 +128,8 @@
 #  define DCD_STM32_BTABLE_BASE 0U
 #endif
 
-#ifndef DCD_STM32_BTABLE_LENGTH
-#  define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE)
+#ifndef DCD_STM32_BTABLE_SIZE
+#  define DCD_STM32_BTABLE_SIZE (FSDEV_PMA_SIZE - DCD_STM32_BTABLE_BASE)
 #endif
 
 /***************************************************
@@ -137,7 +137,7 @@
  */
 
 TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
-TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH), "BTABLE does not fit in PMA RAM");
+TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_SIZE)) <= (FSDEV_PMA_SIZE), "BTABLE does not fit in PMA RAM");
 TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
 
 //--------------------------------------------------------------------+
@@ -559,7 +559,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
       // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
       pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
       pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
       dcd_event_setup_received(0, (uint8_t*)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true);
 #else
       // The setup_received function uses memcpy, so this must first copy the setup data into
@@ -786,7 +786,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
   }
 
   // Ensure allocated buffer is aligned
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   length = (length + 3) & ~0x03;
 #else
   length = (length + 1) & ~0x01;
@@ -798,7 +798,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
   ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
 
   // Verify no overflow
-  TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF);
+  TU_ASSERT(ep_buf_ptr <= FSDEV_PMA_SIZE, 0xFFFF);
 
   epXferCtl->pma_ptr = addr;
   epXferCtl->pma_alloc_size = length;
@@ -1227,7 +1227,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   }
 }
 
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
 {
   const uint8_t* srcVal = src;
@@ -1283,7 +1283,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
   __IO uint16_t *pdwVal;
 
   srcVal = src;
-  pdwVal = &pma[PMA_STRIDE*(dst>>1)];
+  pdwVal = &pma[FSDEV_PMA_STRIDE * (dst >> 1)];
 
   while (n--)
   {
@@ -1291,7 +1291,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
     srcVal++;
     temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U)) ;
     *pdwVal = temp2;
-    pdwVal += PMA_STRIDE;
+    pdwVal += FSDEV_PMA_STRIDE;
     srcVal++;
   }
 
@@ -1323,7 +1323,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
   // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
   // last lin byte will be combined with wrapped part
   // To ensure PMA is always access aligned (dst aligned to 16 or 32 bit)
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   if((cnt_lin & 0x03) && cnt_wrap)
   {
     // Copy first linear part
@@ -1386,7 +1386,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
   return true;
 }
 
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
 {
   uint8_t* dstVal = dst;
@@ -1434,13 +1434,13 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
   __IO const uint16_t *pdwVal;
   uint32_t temp;
 
-  pdwVal = &pma[PMA_STRIDE*(src>>1)];
+  pdwVal = &pma[FSDEV_PMA_STRIDE * (src >> 1)];
   uint8_t *dstVal = (uint8_t*)dst;
 
   while (n--)
   {
     temp = *pdwVal;
-    pdwVal += PMA_STRIDE;
+    pdwVal += FSDEV_PMA_STRIDE;
     *dstVal++ = ((temp >> 0) & 0xFF);
     *dstVal++ = ((temp >> 8) & 0xFF);
   }
@@ -1448,7 +1448,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
   if (wNBytes & 0x01)
   {
     temp = *pdwVal;
-    pdwVal += PMA_STRIDE;
+    pdwVal += FSDEV_PMA_STRIDE;
     *dstVal++ = ((temp >> 0) & 0xFF);
   }
   return true;
@@ -1475,7 +1475,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
   // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
   // last lin byte will be combined with wrapped part
   // To ensure PMA is always access aligned (src aligned to 16 or 32 bit)
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   if((cnt_lin & 0x03) && cnt_wrap)
   {
     // Copy first linear part
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index d28eb0d9a..3f4db985d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -28,7 +28,7 @@
 
 // This file contains source copied from ST's HAL, and thus should have their copyright statement.
 
-// PMA_LENGTH is PMA buffer size in bytes.
+// FSDEV_PMA_SIZE is PMA buffer size in bytes.
 // On 512-byte devices, access with a stride of two words (use every other 16-bit address)
 // On 1024-byte devices, access with a stride of one word (use every 16-bit address)
 
@@ -37,7 +37,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_STM32F0
   #include "stm32f0xx.h"
-  #define PMA_LENGTH (1024u)
+  #define FSDEV_PMA_SIZE (1024u)
   // F0x2 models are crystal-less
   // All have internal D+ pull-up
   // 070RB:    2 x 16 bits/word memory     LPM Support, BCD Support
@@ -45,7 +45,7 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F1
   #include "stm32f1xx.h"
-  #define PMA_LENGTH (512u)
+  #define FSDEV_PMA_SIZE (512u)
   // NO internal Pull-ups
   //         *B, and *C:    2 x 16 bits/word
 
@@ -56,7 +56,7 @@
       defined(STM32F303xB) || defined(STM32F303xC) || \
       defined(STM32F373xC)
   #include "stm32f3xx.h"
-  #define PMA_LENGTH (512u)
+  #define FSDEV_PMA_SIZE (512u)
   // NO internal Pull-ups
   //         *B, and *C:    1 x 16 bits/word
   // PMA dedicated to USB (no sharing with CAN)
@@ -65,27 +65,27 @@
       defined(STM32F302xD) || defined(STM32F302xE) || \
       defined(STM32F303xD) || defined(STM32F303xE)
   #include "stm32f3xx.h"
-  #define PMA_LENGTH (1024u)
+  #define FSDEV_PMA_SIZE (1024u)
   // NO internal Pull-ups
   // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
   // When CAN clock is enabled, USB can use first 768 bytes ONLY.
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L0
   #include "stm32l0xx.h"
-  #define PMA_LENGTH (1024u)
+  #define FSDEV_PMA_SIZE (1024u)
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1
   #include "stm32l1xx.h"
-  #define PMA_LENGTH (512u)
+  #define FSDEV_PMA_SIZE (512u)
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G4
   #include "stm32g4xx.h"
-  #define PMA_LENGTH (1024u)
+  #define FSDEV_PMA_SIZE (1024u)
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
   #include "stm32g0xx.h"
-  #define PMA_32BIT_ACCESS
-  #define PMA_LENGTH (2048u)
+  #define FSDEV_BUS_32BIT
+  #define FSDEV_PMA_SIZE (2048u)
   #undef USB_PMAADDR
   #define USB_PMAADDR USB_DRD_PMAADDR
   #define USB_TypeDef USB_DRD_TypeDef
@@ -112,8 +112,8 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
   #include "stm32h5xx.h"
-  #define PMA_32BIT_ACCESS
-  #define PMA_LENGTH (2048u)
+  #define FSDEV_BUS_32BIT
+  #define FSDEV_PMA_SIZE (2048u)
   #undef USB_PMAADDR
   #define USB_PMAADDR USB_DRD_PMAADDR
   #define USB_TypeDef USB_DRD_TypeDef
@@ -141,18 +141,18 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   #include "stm32wbxx.h"
-  #define PMA_LENGTH (1024u)
+  #define FSDEV_PMA_SIZE (1024u)
   /* ST provided header has incorrect value */
   #undef USB_PMAADDR
   #define USB_PMAADDR USB1_PMAADDR
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L4
   #include "stm32l4xx.h"
-  #define PMA_LENGTH (1024u)
+  #define FSDEV_PMA_SIZE (1024u)
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L5
   #include "stm32l5xx.h"
-  #define PMA_LENGTH (1024u)
+  #define FSDEV_PMA_SIZE (1024u)
 
   #ifndef USB_PMAADDR
     #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
@@ -164,15 +164,16 @@
 #endif
 
 // For purposes of accessing the packet
-#if ((PMA_LENGTH) == 512u)
-  #define PMA_STRIDE  (2u)
-#elif ((PMA_LENGTH) == 1024u)
-  #define PMA_STRIDE  (1u)
+#if ((FSDEV_PMA_SIZE) == 512u)
+  #define FSDEV_PMA_STRIDE  (2u)
+#elif ((FSDEV_PMA_SIZE) == 1024u)
+  #define FSDEV_PMA_STRIDE  (1u)
 #endif
 
+// The fsdev_bus_t type can be used for both register and PMA access necessities
 // For type-safety create a new macro for the volatile address of PMAADDR
 // The compiler should warn us if we cast it to a non-volatile type?
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
 typedef uint32_t fsdev_bus_t;
 static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR;
 
@@ -184,7 +185,7 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
 {
   size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
-  total_word_offset *= PMA_STRIDE;
+  total_word_offset *= FSDEV_PMA_STRIDE;
   return &(pma[total_word_offset]);
 }
 
@@ -215,7 +216,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si
 /* SetENDPOINT */
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
   *reg = wRegValue;
@@ -227,7 +228,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, ui
 
 /* GetENDPOINT */
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4);
 #else
@@ -282,7 +283,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx,
   */
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
 #else
@@ -293,7 +294,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
 #else
@@ -320,7 +321,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   return pma32[2*bEpIdx] & 0x0000FFFFu ;
 #else
@@ -330,7 +331,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef *
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
 #else
@@ -340,7 +341,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef *
 
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
 #else
@@ -350,7 +351,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USB
 
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
 #else
@@ -360,7 +361,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USB
 
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
 #else
@@ -371,7 +372,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, u
 
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
 {
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
 #else
@@ -383,7 +384,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, u
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t blocksize, uint32_t numblocks)
 {
   /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
-#ifdef PMA_32BIT_ACCESS
+#ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26);
 #else
-- 
cgit v1.3.1


From 290f4bea91e739979217eb91d589a75f9ac0f6a7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 12 Jan 2024 15:47:08 +0700
Subject: - change tuh_event_hook_cb, tud_event_hook_cb to weak default
 implementation - change code style

---
 src/device/usbd.c         | 362 +++++++++++++++++++++++-----------------------
 src/device/usbd.h         |   2 +-
 src/device/usbd_control.c |  33 ++---
 src/host/usbh.c           | 126 ++++++++--------
 src/host/usbh.h           |   2 +-
 5 files changed, 255 insertions(+), 270 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 59466b42e..5c94ebcc5 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -38,11 +38,19 @@
 //--------------------------------------------------------------------+
 // USBD Configuration
 //--------------------------------------------------------------------+
-
 #ifndef CFG_TUD_TASK_QUEUE_SZ
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
+//--------------------------------------------------------------------+
+// Callback weak stubs (called if application does not provide)
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
+  (void)rhport;
+  (void)eventid;
+  (void)in_isr;
+}
+
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+
@@ -50,10 +58,8 @@
 // Invalid driver ID in itf2drv[] ep2drv[][] mapping
 enum { DRVID_INVALID = 0xFFu };
 
-typedef struct
-{
-  struct TU_ATTR_PACKED
-  {
+typedef struct {
+  struct TU_ATTR_PACKED {
     volatile uint8_t connected    : 1;
     volatile uint8_t addressed    : 1;
     volatile uint8_t suspended    : 1;
@@ -85,151 +91,150 @@ tu_static usbd_device_t _usbd_dev;
 #endif
 
 // Built-in class drivers
-tu_static usbd_class_driver_t const _usbd_driver[] =
-{
-  #if CFG_TUD_CDC
-  {
-    DRIVER_NAME("CDC")
-    .init             = cdcd_init,
-    .reset            = cdcd_reset,
-    .open             = cdcd_open,
-    .control_xfer_cb  = cdcd_control_xfer_cb,
-    .xfer_cb          = cdcd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_MSC
-  {
-    DRIVER_NAME("MSC")
-    .init             = mscd_init,
-    .reset            = mscd_reset,
-    .open             = mscd_open,
-    .control_xfer_cb  = mscd_control_xfer_cb,
-    .xfer_cb          = mscd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_HID
-  {
-    DRIVER_NAME("HID")
-    .init             = hidd_init,
-    .reset            = hidd_reset,
-    .open             = hidd_open,
-    .control_xfer_cb  = hidd_control_xfer_cb,
-    .xfer_cb          = hidd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_AUDIO
-  {
-    DRIVER_NAME("AUDIO")
-    .init             = audiod_init,
-    .reset            = audiod_reset,
-    .open             = audiod_open,
-    .control_xfer_cb  = audiod_control_xfer_cb,
-    .xfer_cb          = audiod_xfer_cb,
-    .sof              = audiod_sof_isr
-  },
-  #endif
-
-  #if CFG_TUD_VIDEO
-  {
-    DRIVER_NAME("VIDEO")
-    .init             = videod_init,
-    .reset            = videod_reset,
-    .open             = videod_open,
-    .control_xfer_cb  = videod_control_xfer_cb,
-    .xfer_cb          = videod_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_MIDI
-  {
-    DRIVER_NAME("MIDI")
-    .init             = midid_init,
-    .open             = midid_open,
-    .reset            = midid_reset,
-    .control_xfer_cb  = midid_control_xfer_cb,
-    .xfer_cb          = midid_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_VENDOR
-  {
-    DRIVER_NAME("VENDOR")
-    .init             = vendord_init,
-    .reset            = vendord_reset,
-    .open             = vendord_open,
-    .control_xfer_cb  = tud_vendor_control_xfer_cb,
-    .xfer_cb          = vendord_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_USBTMC
-  {
-    DRIVER_NAME("TMC")
-    .init             = usbtmcd_init_cb,
-    .reset            = usbtmcd_reset_cb,
-    .open             = usbtmcd_open_cb,
-    .control_xfer_cb  = usbtmcd_control_xfer_cb,
-    .xfer_cb          = usbtmcd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_DFU_RUNTIME
-  {
-    DRIVER_NAME("DFU-RUNTIME")
-    .init             = dfu_rtd_init,
-    .reset            = dfu_rtd_reset,
-    .open             = dfu_rtd_open,
-    .control_xfer_cb  = dfu_rtd_control_xfer_cb,
-    .xfer_cb          = NULL,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_DFU
-  {
-    DRIVER_NAME("DFU")
-    .init             = dfu_moded_init,
-    .reset            = dfu_moded_reset,
-    .open             = dfu_moded_open,
-    .control_xfer_cb  = dfu_moded_control_xfer_cb,
-    .xfer_cb          = NULL,
-    .sof              = NULL
-  },
-  #endif
-
-  #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
-  {
-    DRIVER_NAME("NET")
-    .init             = netd_init,
-    .reset            = netd_reset,
-    .open             = netd_open,
-    .control_xfer_cb  = netd_control_xfer_cb,
-    .xfer_cb          = netd_xfer_cb,
-    .sof                  = NULL,
-  },
-  #endif
-
-  #if CFG_TUD_BTH
-  {
-    DRIVER_NAME("BTH")
-    .init             = btd_init,
-    .reset            = btd_reset,
-    .open             = btd_open,
-    .control_xfer_cb  = btd_control_xfer_cb,
-    .xfer_cb          = btd_xfer_cb,
-    .sof              = NULL
-  },
-  #endif
+tu_static usbd_class_driver_t const _usbd_driver[] = {
+    #if CFG_TUD_CDC
+    {
+        DRIVER_NAME("CDC")
+        .init             = cdcd_init,
+        .reset            = cdcd_reset,
+        .open             = cdcd_open,
+        .control_xfer_cb  = cdcd_control_xfer_cb,
+        .xfer_cb          = cdcd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_MSC
+    {
+        DRIVER_NAME("MSC")
+        .init             = mscd_init,
+        .reset            = mscd_reset,
+        .open             = mscd_open,
+        .control_xfer_cb  = mscd_control_xfer_cb,
+        .xfer_cb          = mscd_xfer_cb,
+        .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_HID
+    {
+      DRIVER_NAME("HID")
+      .init             = hidd_init,
+      .reset            = hidd_reset,
+      .open             = hidd_open,
+      .control_xfer_cb  = hidd_control_xfer_cb,
+      .xfer_cb          = hidd_xfer_cb,
+      .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_AUDIO
+    {
+      DRIVER_NAME("AUDIO")
+      .init             = audiod_init,
+      .reset            = audiod_reset,
+      .open             = audiod_open,
+      .control_xfer_cb  = audiod_control_xfer_cb,
+      .xfer_cb          = audiod_xfer_cb,
+      .sof              = audiod_sof_isr
+    },
+    #endif
+
+    #if CFG_TUD_VIDEO
+    {
+      DRIVER_NAME("VIDEO")
+      .init             = videod_init,
+      .reset            = videod_reset,
+      .open             = videod_open,
+      .control_xfer_cb  = videod_control_xfer_cb,
+      .xfer_cb          = videod_xfer_cb,
+      .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_MIDI
+    {
+      DRIVER_NAME("MIDI")
+      .init             = midid_init,
+      .open             = midid_open,
+      .reset            = midid_reset,
+      .control_xfer_cb  = midid_control_xfer_cb,
+      .xfer_cb          = midid_xfer_cb,
+      .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_VENDOR
+    {
+      DRIVER_NAME("VENDOR")
+      .init             = vendord_init,
+      .reset            = vendord_reset,
+      .open             = vendord_open,
+      .control_xfer_cb  = tud_vendor_control_xfer_cb,
+      .xfer_cb          = vendord_xfer_cb,
+      .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_USBTMC
+    {
+      DRIVER_NAME("TMC")
+      .init             = usbtmcd_init_cb,
+      .reset            = usbtmcd_reset_cb,
+      .open             = usbtmcd_open_cb,
+      .control_xfer_cb  = usbtmcd_control_xfer_cb,
+      .xfer_cb          = usbtmcd_xfer_cb,
+      .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_DFU_RUNTIME
+    {
+      DRIVER_NAME("DFU-RUNTIME")
+      .init             = dfu_rtd_init,
+      .reset            = dfu_rtd_reset,
+      .open             = dfu_rtd_open,
+      .control_xfer_cb  = dfu_rtd_control_xfer_cb,
+      .xfer_cb          = NULL,
+      .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_DFU
+    {
+      DRIVER_NAME("DFU")
+      .init             = dfu_moded_init,
+      .reset            = dfu_moded_reset,
+      .open             = dfu_moded_open,
+      .control_xfer_cb  = dfu_moded_control_xfer_cb,
+      .xfer_cb          = NULL,
+      .sof              = NULL
+    },
+    #endif
+
+    #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
+    {
+      DRIVER_NAME("NET")
+      .init             = netd_init,
+      .reset            = netd_reset,
+      .open             = netd_open,
+      .control_xfer_cb  = netd_control_xfer_cb,
+      .xfer_cb          = netd_xfer_cb,
+      .sof                  = NULL,
+    },
+    #endif
+
+    #if CFG_TUD_BTH
+    {
+      DRIVER_NAME("BTH")
+      .init             = btd_init,
+      .reset            = btd_reset,
+      .open             = btd_open,
+      .control_xfer_cb  = btd_control_xfer_cb,
+      .xfer_cb          = btd_xfer_cb,
+      .sof              = NULL
+    },
+    #endif
 };
 
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
@@ -275,7 +280,7 @@ tu_static osal_queue_t _usbd_q;
 
 TU_ATTR_ALWAYS_INLINE static inline bool queue_event(dcd_event_t const * event, bool in_isr) {
   bool ret = osal_queue_send(_usbd_q, event, in_isr);
-  if (tud_event_hook_cb) tud_event_hook_cb(event->rhport, event->event_id, in_isr);
+  tud_event_hook_cb(event->rhport, event->event_id, in_isr);
   return ret;
 }
 
@@ -297,27 +302,23 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event,
 // Debug
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
-tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
-{
-  "Invalid"        ,
-  "Bus Reset"      ,
-  "Unplugged"      ,
-  "SOF"            ,
-  "Suspend"        ,
-  "Resume"         ,
-  "Setup Received" ,
-  "Xfer Complete"  ,
-  "Func Call"
+tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] = {
+    "Invalid",
+    "Bus Reset",
+    "Unplugged",
+    "SOF",
+    "Suspend",
+    "Resume",
+    "Setup Received",
+    "Xfer Complete",
+    "Func Call"
 };
 
 // for usbd_control to print the name of control complete driver
-void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
-{
-  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
-  {
-    usbd_class_driver_t const * driver = get_driver(i);
-    if ( driver && driver->control_xfer_cb == callback )
-    {
+void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) {
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
+    if (driver && driver->control_xfer_cb == callback) {
       TU_LOG_USBD("  %s control complete\r\n", driver->name);
       return;
     }
@@ -329,43 +330,36 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
-tusb_speed_t tud_speed_get(void)
-{
+tusb_speed_t tud_speed_get(void) {
   return (tusb_speed_t) _usbd_dev.speed;
 }
 
-bool tud_connected(void)
-{
+bool tud_connected(void) {
   return _usbd_dev.connected;
 }
 
-bool tud_mounted(void)
-{
+bool tud_mounted(void) {
   return _usbd_dev.cfg_num ? true : false;
 }
 
-bool tud_suspended(void)
-{
+bool tud_suspended(void) {
   return _usbd_dev.suspended;
 }
 
-bool tud_remote_wakeup(void)
-{
+bool tud_remote_wakeup(void) {
   // only wake up host if this feature is supported and enabled and we are suspended
-  TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en );
+  TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en);
   dcd_remote_wakeup(_usbd_rhport);
   return true;
 }
 
-bool tud_disconnect(void)
-{
+bool tud_disconnect(void) {
   TU_VERIFY(dcd_disconnect);
   dcd_disconnect(_usbd_rhport);
   return true;
 }
 
-bool tud_connect(void)
-{
+bool tud_connect(void) {
   TU_VERIFY(dcd_connect);
   dcd_connect(_usbd_rhport);
   return true;
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 5456148bf..3ab6c813f 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -147,7 +147,7 @@ TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en);
 TU_ATTR_WEAK void tud_resume_cb(void);
 
 // Invoked when there is a new usb event, which need to be processed by tud_task()/tud_task_ext()
-TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
+void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
 
 // Invoked when received control request with VENDOR TYPE
 TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index a6081060e..ea18b28da 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -32,24 +32,32 @@
 #include "tusb.h"
 #include "device/usbd_pvt.h"
 
+//--------------------------------------------------------------------+
+// Callback weak stubs (called if application does not provide)
+//--------------------------------------------------------------------+
+TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) {
+  (void)rhport;
+  (void)request;
+}
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
 #endif
 
-enum
-{
+enum {
   EDPT_CTRL_OUT = 0x00,
   EDPT_CTRL_IN  = 0x80
 };
 
-typedef struct
-{
+typedef struct {
   tusb_control_request_t request;
-
   uint8_t* buffer;
   uint16_t data_len;
   uint16_t total_xferred;
-
   usbd_control_xfer_cb_t complete_cb;
 } usbd_control_xfer_t;
 
@@ -134,23 +142,12 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
 //--------------------------------------------------------------------+
 // USBD API
 //--------------------------------------------------------------------+
-
-TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
-{
-  (void)rhport;
-  (void)request;
-
-  // this is the default implementation that is called when no "real" implementation
-  // of the function exists
-}
-
 void usbd_control_reset(void);
 void usbd_control_set_request(tusb_control_request_t const *request);
 void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
 bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
 
-void usbd_control_reset(void)
-{
+void usbd_control_reset(void) {
   tu_varclr(&_ctrl_xfer);
 }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 53e8a654b..dfe6ddb42 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -36,7 +36,6 @@
 //--------------------------------------------------------------------+
 // USBH Configuration
 //--------------------------------------------------------------------+
-
 #ifndef CFG_TUH_TASK_QUEUE_SZ
   #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
@@ -46,11 +45,18 @@
 #endif
 
 //--------------------------------------------------------------------+
-// USBH-HCD common data structure
+// Callback weak stubs (called if application does not provide)
 //--------------------------------------------------------------------+
+TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
+  (void) rhport;
+  (void) eventid;
+  (void) in_isr;
+}
 
-typedef struct
-{
+//--------------------------------------------------------------------+
+// USBH-HCD common data structure
+//--------------------------------------------------------------------+
+typedef struct {
   // port
   uint8_t rhport;
   uint8_t hub_addr;
@@ -112,60 +118,58 @@ typedef struct {
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
 #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
   #define DRIVER_NAME(_name)    .name = _name,
 #else
   #define DRIVER_NAME(_name)
 #endif
 
-static usbh_class_driver_t const usbh_class_drivers[] =
-{
-  #if CFG_TUH_CDC
+static usbh_class_driver_t const usbh_class_drivers[] = {
+    #if CFG_TUH_CDC
     {
-      DRIVER_NAME("CDC")
-      .init       = cdch_init,
-      .open       = cdch_open,
-      .set_config = cdch_set_config,
-      .xfer_cb    = cdch_xfer_cb,
-      .close      = cdch_close
+        DRIVER_NAME("CDC")
+        .init       = cdch_init,
+        .open       = cdch_open,
+        .set_config = cdch_set_config,
+        .xfer_cb    = cdch_xfer_cb,
+        .close      = cdch_close
     },
-  #endif
+    #endif
 
-  #if CFG_TUH_MSC
+    #if CFG_TUH_MSC
     {
-      DRIVER_NAME("MSC")
-      .init       = msch_init,
-      .open       = msch_open,
-      .set_config = msch_set_config,
-      .xfer_cb    = msch_xfer_cb,
-      .close      = msch_close
+        DRIVER_NAME("MSC")
+        .init       = msch_init,
+        .open       = msch_open,
+        .set_config = msch_set_config,
+        .xfer_cb    = msch_xfer_cb,
+        .close      = msch_close
     },
-  #endif
+    #endif
 
-  #if CFG_TUH_HID
+    #if CFG_TUH_HID
     {
-      DRIVER_NAME("HID")
-      .init       = hidh_init,
-      .open       = hidh_open,
-      .set_config = hidh_set_config,
-      .xfer_cb    = hidh_xfer_cb,
-      .close      = hidh_close
+        DRIVER_NAME("HID")
+        .init       = hidh_init,
+        .open       = hidh_open,
+        .set_config = hidh_set_config,
+        .xfer_cb    = hidh_xfer_cb,
+        .close      = hidh_close
     },
-  #endif
+    #endif
 
-  #if CFG_TUH_HUB
+    #if CFG_TUH_HUB
     {
-      DRIVER_NAME("HUB")
-      .init       = hub_init,
-      .open       = hub_open,
-      .set_config = hub_set_config,
-      .xfer_cb    = hub_xfer_cb,
-      .close      = hub_close
+        DRIVER_NAME("HUB")
+        .init       = hub_init,
+        .open       = hub_open,
+        .set_config = hub_set_config,
+        .xfer_cb    = hub_xfer_cb,
+        .close      = hub_close
     },
-  #endif
+    #endif
 
-  #if CFG_TUH_VENDOR
+    #if CFG_TUH_VENDOR
     {
       DRIVER_NAME("VENDOR")
       .init       = cush_init,
@@ -173,7 +177,7 @@ static usbh_class_driver_t const usbh_class_drivers[] =
       .xfer_cb    = cush_isr,
       .close      = cush_close
     }
-  #endif
+    #endif
 };
 
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
@@ -233,8 +237,7 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 // Control transfers: since most controllers do not support multiple control transfers
 // on multiple devices concurrently and control transfers are not used much except for
 // enumeration, we will only execute control transfers one at a time.
-CFG_TUH_MEM_SECTION struct
-{
+CFG_TUH_MEM_SECTION struct {
   CFG_TUH_MEM_ALIGN tusb_control_request_t request;
   uint8_t* buffer;
   tuh_xfer_cb_t complete_cb;
@@ -268,7 +271,7 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec) {
 
 TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) {
   bool ret = osal_queue_send(_usbh_q, event, in_isr);
-  if (tuh_event_hook_cb) tuh_event_hook_cb(event->rhport, event->event_id, in_isr);
+  tuh_event_hook_cb(event->rhport, event->event_id, in_isr);
   return ret;
 }
 
@@ -367,17 +370,14 @@ bool tuh_init(uint8_t controller_id) {
   tu_memclr(_usbh_devices, sizeof(_usbh_devices));
   tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
 
-  for(uint8_t i=0; i<TOTAL_DEVICES; i++)
-  {
+  for(uint8_t i=0; i<TOTAL_DEVICES; i++) {
     clear_device(&_usbh_devices[i]);
   }
 
   // Class drivers
-  for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
-  {
-    usbh_class_driver_t const * driver = get_driver(drv_id);
-    if ( driver )
-    {
+  for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+    usbh_class_driver_t const* driver = get_driver(drv_id);
+    if (driver) {
       TU_LOG_USBH("%s init\r\n", driver->name);
       driver->init();
     }
@@ -545,8 +545,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
 // Control transfer
 //--------------------------------------------------------------------+
 
-static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
-{
+static void _control_blocking_complete_cb(tuh_xfer_t* xfer) {
   // update result
   *((xfer_result_t*) xfer->user_data) = xfer->result;
 }
@@ -625,21 +624,18 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
-{
+TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) {
   (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
   _ctrl_xfer.stage = stage;
   (void) osal_mutex_unlock(_usbh_mutex);
 }
 
-static void _xfer_complete(uint8_t daddr, xfer_result_t result)
-{
+static void _xfer_complete(uint8_t daddr, xfer_result_t result) {
   TU_LOG_USBH("\r\n");
 
   // duplicate xfer since user can execute control transfer within callback
   tusb_control_request_t const request = _ctrl_xfer.request;
-  tuh_xfer_t xfer_temp =
-  {
+  tuh_xfer_t xfer_temp = {
     .daddr       = daddr,
     .ep_addr     = 0,
     .result      = result,
@@ -652,8 +648,7 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result)
 
   _set_control_xfer_stage(CONTROL_STAGE_IDLE);
 
-  if (xfer_temp.complete_cb)
-  {
+  if (xfer_temp.complete_cb) {
     xfer_temp.complete_cb(&xfer_temp);
   }
 }
@@ -710,17 +705,16 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 //
 //--------------------------------------------------------------------+
 
-bool tuh_edpt_xfer(tuh_xfer_t* xfer)
-{
-  uint8_t const daddr   = xfer->daddr;
+bool tuh_edpt_xfer(tuh_xfer_t* xfer) {
+  uint8_t const daddr = xfer->daddr;
   uint8_t const ep_addr = xfer->ep_addr;
 
   TU_VERIFY(daddr && ep_addr);
 
   TU_VERIFY(usbh_edpt_claim(daddr, ep_addr));
 
-  if ( !usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen, xfer->complete_cb, xfer->user_data) )
-  {
+  if (!usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen,
+                                    xfer->complete_cb, xfer->user_data)) {
     usbh_edpt_release(daddr, ep_addr);
     return false;
   }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 7591c7672..9ff118543 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -94,7 +94,7 @@ TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
 TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 
 // Invoked when there is a new usb event, which need to be processed by tuh_task()/tuh_task_ext()
-TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
+void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr);
 
 //--------------------------------------------------------------------+
 // APPLICATION API
-- 
cgit v1.3.1


From 8eca596fa649a4e32da53f65ac1a41f963b89eb6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 12 Jan 2024 16:05:35 +0700
Subject: style changes

---
 src/device/usbd_control.c | 105 +++++++++++++++++++---------------------------
 1 file changed, 43 insertions(+), 62 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index ea18b28da..35cce1f7e 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -35,9 +35,9 @@
 //--------------------------------------------------------------------+
 // Callback weak stubs (called if application does not provide)
 //--------------------------------------------------------------------+
-TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) {
-  (void)rhport;
-  (void)request;
+TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
+  (void) rhport;
+  (void) request;
 }
 
 //--------------------------------------------------------------------+
@@ -50,7 +50,7 @@ extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callb
 
 enum {
   EDPT_CTRL_OUT = 0x00,
-  EDPT_CTRL_IN  = 0x80
+  EDPT_CTRL_IN = 0x80
 };
 
 typedef struct {
@@ -71,20 +71,18 @@ tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
 //--------------------------------------------------------------------+
 
 // Queue ZLP status transaction
-static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
-{
+static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) {
   // Opposite to endpoint in Data Phase
   uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
   return usbd_edpt_xfer(rhport, ep_addr, NULL, 0);
 }
 
 // Status phase
-bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
-{
-  _ctrl_xfer.request       = (*request);
-  _ctrl_xfer.buffer        = NULL;
+bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) {
+  _ctrl_xfer.request = (*request);
+  _ctrl_xfer.buffer = NULL;
   _ctrl_xfer.total_xferred = 0;
-  _ctrl_xfer.data_len      = 0;
+  _ctrl_xfer.data_len = 0;
 
   return _status_stage_xact(rhport, request);
 }
@@ -92,16 +90,15 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
 // Queue a transaction in Data Stage
 // Each transaction has up to Endpoint0's max packet size.
 // This function can also transfer an zero-length packet
-static bool _data_stage_xact(uint8_t rhport)
-{
-  uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE);
+static bool _data_stage_xact(uint8_t rhport) {
+  uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred,
+                                     CFG_TUD_ENDPOINT0_SIZE);
 
   uint8_t ep_addr = EDPT_CTRL_OUT;
 
-  if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN )
-  {
+  if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) {
     ep_addr = EDPT_CTRL_IN;
-    if ( xact_len ) {
+    if (xact_len) {
       TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len));
     }
   }
@@ -111,29 +108,24 @@ static bool _data_stage_xact(uint8_t rhport)
 
 // Transmit data to/from the control endpoint.
 // If the request's wLength is zero, a status packet is sent instead.
-bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len)
-{
-  _ctrl_xfer.request       = (*request);
-  _ctrl_xfer.buffer        = (uint8_t*) buffer;
+bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, void* buffer, uint16_t len) {
+  _ctrl_xfer.request = (*request);
+  _ctrl_xfer.buffer = (uint8_t*) buffer;
   _ctrl_xfer.total_xferred = 0U;
-  _ctrl_xfer.data_len      = tu_min16(len, request->wLength);
+  _ctrl_xfer.data_len = tu_min16(len, request->wLength);
 
-  if (request->wLength > 0U)
-  {
-    if(_ctrl_xfer.data_len > 0U)
-    {
+  if (request->wLength > 0U) {
+    if (_ctrl_xfer.data_len > 0U) {
       TU_ASSERT(buffer);
     }
 
 //    TU_LOG2("  Control total data length is %u bytes\r\n", _ctrl_xfer.data_len);
 
     // Data stage
-    TU_ASSERT( _data_stage_xact(rhport) );
-  }
-  else
-  {
+    TU_ASSERT(_data_stage_xact(rhport));
+  } else {
     // Status stage
-    TU_ASSERT( _status_stage_xact(rhport, request) );
+    TU_ASSERT(_status_stage_xact(rhport, request));
   }
 
   return true;
@@ -143,46 +135,41 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
 // USBD API
 //--------------------------------------------------------------------+
 void usbd_control_reset(void);
-void usbd_control_set_request(tusb_control_request_t const *request);
-void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
-bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void usbd_control_set_request(tusb_control_request_t const* request);
+void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp);
+bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
 
 void usbd_control_reset(void) {
   tu_varclr(&_ctrl_xfer);
 }
 
 // Set complete callback
-void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp )
-{
+void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp) {
   _ctrl_xfer.complete_cb = fp;
 }
 
 // for dcd_set_address where DCD is responsible for status response
-void usbd_control_set_request(tusb_control_request_t const *request)
-{
-  _ctrl_xfer.request       = (*request);
-  _ctrl_xfer.buffer        = NULL;
+void usbd_control_set_request(tusb_control_request_t const* request) {
+  _ctrl_xfer.request = (*request);
+  _ctrl_xfer.buffer = NULL;
   _ctrl_xfer.total_xferred = 0;
-  _ctrl_xfer.data_len      = 0;
+  _ctrl_xfer.data_len = 0;
 }
 
 // callback when a transaction complete on
 // - DATA stage of control endpoint or
 // - Status stage
-bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
 
   // Endpoint Address is opposite to direction bit, this is Status Stage complete event
-  if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
-  {
+  if (tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction) {
     TU_ASSERT(0 == xferred_bytes);
 
     // invoke optional dcd hook if available
     dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
 
-    if (_ctrl_xfer.complete_cb)
-    {
+    if (_ctrl_xfer.complete_cb) {
       // TODO refactor with usbd_driver_print_control_complete_name
       _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request);
     }
@@ -190,8 +177,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     return true;
   }
 
-  if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT )
-  {
+  if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) {
     TU_VERIFY(_ctrl_xfer.buffer);
     memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
     TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2);
@@ -202,15 +188,14 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
 
   // Data Stage is complete when all request's length are transferred or
   // a short packet is sent including zero-length packet.
-  if ( (_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE) )
-  {
+  if ((_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) ||
+      (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE)) {
     // DATA stage is complete
     bool is_ok = true;
 
     // invoke complete callback if set
     // callback can still stall control in status phase e.g out data does not make sense
-    if ( _ctrl_xfer.complete_cb )
-    {
+    if (_ctrl_xfer.complete_cb) {
       #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
       usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
       #endif
@@ -218,21 +203,17 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
       is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request);
     }
 
-    if ( is_ok )
-    {
+    if (is_ok) {
       // Send status
-      TU_ASSERT( _status_stage_xact(rhport, &_ctrl_xfer.request) );
-    }else
-    {
+      TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request));
+    } else {
       // Stall both IN and OUT control endpoint
       dcd_edpt_stall(rhport, EDPT_CTRL_OUT);
       dcd_edpt_stall(rhport, EDPT_CTRL_IN);
     }
-  }
-  else
-  {
+  } else {
     // More data to transfer
-    TU_ASSERT( _data_stage_xact(rhport) );
+    TU_ASSERT(_data_stage_xact(rhport));
   }
 
   return true;
-- 
cgit v1.3.1


From d92eb38c211899ed963250272d882fcac8dbaf9c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Jan 2024 16:56:18 +0700
Subject: change code style

---
 src/class/cdc/cdc_host.c | 526 +++++++++++++++++++++--------------------------
 1 file changed, 235 insertions(+), 291 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 4f36f7517..05a061487 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -106,7 +106,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 
 static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST };
 enum {
-  FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
+  FTDI_PID_COUNT = TU_ARRAY_SIZE(ftdi_pids)
 };
 
 // Store last request baudrate since divisor to baudrate is not easy
@@ -114,7 +114,6 @@ static uint32_t _ftdi_requested_baud;
 
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
-
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -125,12 +124,11 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 
 static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST };
 enum {
-  CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
+  CP210X_PID_COUNT = TU_ARRAY_SIZE(cp210x_pids)
 };
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
-
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -141,16 +139,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 
 static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
 enum {
-  CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] )
+  CH34X_VID_PID_COUNT = TU_ARRAY_SIZE(ch34x_vids_pids)
 };
 
 static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
 static void ch34x_process_config ( tuh_xfer_t* xfer );
-
 static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 #endif
 
+//------------- Common -------------//
 
 enum {
   SERIAL_DRIVER_ACM = 0,
@@ -204,29 +202,25 @@ static const cdch_serial_driver_t serial_drivers[] = {
 };
 
 enum {
-  SERIAL_DRIVER_COUNT = sizeof(serial_drivers) / sizeof(serial_drivers[0])
+  SERIAL_DRIVER_COUNT = TU_ARRAY_SIZE(serial_drivers)
 };
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-static inline cdch_interface_t* get_itf(uint8_t idx)
-{
+static inline cdch_interface_t* get_itf(uint8_t idx) {
   TU_ASSERT(idx < CFG_TUH_CDC, NULL);
   cdch_interface_t* p_cdc = &cdch_data[idx];
 
   return (p_cdc->daddr != 0) ? p_cdc : NULL;
 }
 
-static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
     if ( (p_cdc->daddr == daddr) &&
-         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr))
-    {
+         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) {
       return i;
     }
   }
@@ -234,14 +228,10 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
   return TUSB_INDEX_INVALID_8;
 }
 
-
-static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     if (cdch_data[i].daddr == 0) {
       cdch_interface_t* p_cdc = &cdch_data[i];
-
       p_cdc->daddr              = daddr;
       p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
       p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
@@ -262,20 +252,16 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 // APPLICATION API
 //--------------------------------------------------------------------+
 
-uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) {
+  for (uint8_t i = 0; i < CFG_TUH_CDC; i++) {
     const cdch_interface_t* p_cdc = &cdch_data[i];
-
     if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
   }
 
   return TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
-{
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && info);
 
@@ -297,30 +283,26 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
   return true;
 }
 
-bool tuh_cdc_mounted(uint8_t idx)
-{
+bool tuh_cdc_mounted(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   return p_cdc != NULL;
 }
 
-bool tuh_cdc_get_dtr(uint8_t idx)
-{
+bool tuh_cdc_get_dtr(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
 }
 
-bool tuh_cdc_get_rts(uint8_t idx)
-{
+bool tuh_cdc_get_rts(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
 
-bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
-{
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -333,32 +315,28 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
 // Write
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_write_flush(uint8_t idx)
-{
+uint32_t tuh_cdc_write_flush(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write_xfer(&p_cdc->stream.tx);
 }
 
-bool tuh_cdc_write_clear(uint8_t idx)
-{
+bool tuh_cdc_write_clear(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_clear(&p_cdc->stream.tx);
 }
 
-uint32_t tuh_cdc_write_available(uint8_t idx)
-{
+uint32_t tuh_cdc_write_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -369,32 +347,28 @@ uint32_t tuh_cdc_write_available(uint8_t idx)
 // Read
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_read_available(uint8_t idx)
-{
+uint32_t tuh_cdc_read_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read_available(&p_cdc->stream.rx);
 }
 
-bool tuh_cdc_peek(uint8_t idx, uint8_t* ch)
-{
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_peek(&p_cdc->stream.rx, ch);
 }
 
-bool tuh_cdc_read_clear (uint8_t idx)
-{
+bool tuh_cdc_read_clear (uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -408,15 +382,13 @@ bool tuh_cdc_read_clear (uint8_t idx)
 //--------------------------------------------------------------------+
 
 // internal control complete to update state such as line state, encoding
-static void cdch_internal_control_complete(tuh_xfer_t* xfer)
-{
+static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc, );
 
-  if (xfer->result == XFER_RESULT_SUCCESS)
-  {
+  if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (p_cdc->serial_drid) {
       case SERIAL_DRIVER_ACM:
         switch (xfer->setup->bRequest) {
@@ -502,7 +474,6 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_state = (uint8_t) line_state;
     return true;
   }
@@ -526,7 +497,6 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_coding.bit_rate = baudrate;
     return true;
   }
@@ -552,7 +522,6 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_coding = *line_coding;
     return true;
   }
@@ -562,31 +531,26 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 // CLASS-USBH API
 //--------------------------------------------------------------------+
 
-void cdch_init(void)
-{
+void cdch_init(void) {
   tu_memclr(cdch_data, sizeof(cdch_data));
 
-  for(size_t i=0; i<CFG_TUH_CDC; i++)
-  {
+  for (size_t i = 0; i < CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
 
     tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
-                          p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
-                          p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
+                        p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
+                        p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
 
     tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false,
-                          p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
-                          p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
+                        p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
+                        p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
   }
 }
 
-void cdch_close(uint8_t daddr)
-{
-  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
-  {
+void cdch_close(uint8_t daddr) {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
     cdch_interface_t* p_cdc = &cdch_data[idx];
-    if (p_cdc->daddr == daddr)
-    {
+    if (p_cdc->daddr == daddr) {
       TU_LOG_DRV("  CDCh close addr = %u index = %u\r\n", daddr, idx);
 
       // Invoke application callback
@@ -618,16 +582,11 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
       // - xferred_bytes is multiple of EP Packet size and not zero
       tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
     }
-  }
-  else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
+  } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
     #if CFG_TUH_CDC_FTDI
     if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) {
       // FTDI reserve 2 bytes for status
-      // FTDI status
-//      uint8_t status[2] = {
-//        p_cdc->stream.rx.ep_buf[0],
-//        p_cdc->stream.rx.ep_buf[1]
-//      };
+      // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]};
       tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2);
     }else
     #endif
@@ -653,20 +612,15 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep)
-{
-  for(size_t i=0; i<2; i++)
-  {
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const* desc_ep) {
+  for (size_t i = 0; i < 2; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
-              TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
-
+              TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
     TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep));
 
-    if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
-    {
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
       tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep);
-    }else
-    {
+    } else {
       tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep);
     }
 
@@ -676,20 +630,17 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co
   return true;
 }
 
-bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
+bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
   (void) rhport;
 
-  // Only support ACM subclass
+  // For CDC: only support ACM subclass
   // Note: Protocol 0xFF can be RNDIS device
-  if ( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
-       CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass)
-  {
+  if (TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
+      CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
     return acm_open(daddr, itf_desc, max_len);
   }
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
-  else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
-  {
+  else if (TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
@@ -721,7 +672,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     }
     #endif
   }
-  #endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
+  #endif
 
   return false;
 }
@@ -767,94 +718,85 @@ enum {
   CONFIG_ACM_COMPLETE,
 };
 
-static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
-  uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len;
 
-  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
   p_cdc->serial_drid = SERIAL_DRIVER_ACM;
 
   //------------- Control Interface -------------//
-  uint8_t const * p_desc = tu_desc_next(itf_desc);
+  uint8_t const* p_desc = tu_desc_next(itf_desc);
 
   // Communication Functional Descriptors
-  while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) )
-  {
-    if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
-    {
+  while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) {
+    if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) {
       // save ACM bmCapabilities
-      p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
+      p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities;
     }
 
     p_desc = tu_desc_next(p_desc);
   }
 
   // Open notification endpoint of control interface if any
-  if (itf_desc->bNumEndpoints == 1)
-  {
+  if (itf_desc->bNumEndpoints == 1) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
-    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
 
-    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
+    TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     p_desc = tu_desc_next(p_desc);
   }
 
   //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
-       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
-  {
+  if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+      (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) {
     // next to endpoint descriptor
     p_desc = tu_desc_next(p_desc);
 
     // data endpoints expected to be in pairs
-    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
+    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc));
   }
 
   return true;
 }
 
-static void acm_process_config(tuh_xfer_t* xfer)
-{
+static void acm_process_config(tuh_xfer_t* xfer) {
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t * p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc, );
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
 
-  switch(state)
-  {
+  switch (state) {
     case CONFIG_ACM_SET_CONTROL_LINE_STATE:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
-        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config,
-                                             CONFIG_ACM_SET_LINE_CODING), );
+      if (p_cdc->acm_capability.support_line_request) {
+        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),);
         break;
       }
-          #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_SET_LINE_CODING:
-        #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request) {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE), );
+        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),);
         break;
       }
-        #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_COMPLETE:
       // itf_num+1 to account for data interface as well
-      set_config_complete(p_cdc, idx, itf_num+1);
+      set_config_complete(p_cdc, idx, itf_num + 1);
       break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
@@ -987,13 +929,12 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1
   return tuh_control_xfer(&xfer);
 }
 
-static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool
+ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
@@ -1001,8 +942,7 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state
   return true;
 }
 
-static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
-{
+static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) {
   const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 };
   uint32_t divisor;
 
@@ -1022,13 +962,11 @@ static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
   return divisor;
 }
 
-static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
-{
+static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) {
   return ftdi_232bm_baud_base_to_divisor(baud, 48000000u);
 }
 
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
@@ -1055,8 +993,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_FTDI_MODEM_CTRL:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
+      TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1172,8 +1109,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
                             complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
-static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
@@ -1213,8 +1149,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CP210X_SET_DTR_RTS:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
+      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1248,8 +1183,7 @@ enum {
   CONFIG_CH34X_COMPLETE
 };
 
-static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len )
-{
+static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) {
   // CH34x Interface includes 1 vendor interface + 3 bulk endpoints
   TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
   TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
@@ -1303,23 +1237,19 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
   return false;
 }
 
-static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
 }
 
-static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
 }
 
-static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
 }
 
-static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
 }
 
@@ -1335,8 +1265,7 @@ static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, u
  */
 // calculate baudrate devisors
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
-{
+static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
   uint32_t fact, div, clk_div;
   bool force_fact0 = false;
   int32_t ps;
@@ -1362,20 +1291,19 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
    */
   fact = 1;
   for (ps = 3; ps >= 0; ps--) {
-    if (speed > ch341_min_rates[ps])
-      break;
+    if (speed > ch341_min_rates[ps]) break;
   }
 
-  if (ps < 0)
-    return -EINVAL;
+  if (ps < 0) return -EINVAL;
 
   /* Determine corresponding divisor, rounding down. */
   clk_div = CH341_CLK_DIV(ps, fact);
   div = CH341_CLKRATE / (clk_div * speed);
 
   /* Some devices require a lower base clock if ps < 3. */
-  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
+  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER)) {
     force_fact0 = true;
+  }
 
   /* Halve base clock (fact = 0) if required. */
   if (div < 9 || div > 255 || force_fact0) {
@@ -1384,16 +1312,16 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
     fact = 0;
   }
 
-  if (div < 2)
-    return -EINVAL;
+  if (div < 2) return -EINVAL;
 
   /*
    * Pick next divisor if resulting rate is closer to the requested one,
    * scale up to avoid rounding errors on low rates.
    */
   if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
-      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
+      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) {
     div++;
+  }
 
   /*
    * Prefer lower base clock (fact = 0) if even divisor.
@@ -1411,16 +1339,13 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
 // set baudrate (low level)
 // do not confuse with ch34x_set_baudrate
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   int val;
 
-  if (!baud_rate)
-    return -EINVAL;
+  if (!baud_rate) return -EINVAL;
 
   val = ch341_get_divisor(p_cdc, baud_rate);
-  if (val < 0)
-    return -EINVAL;
+  if (val < 0) return -EINVAL;
 
   /*
    * CH341A buffers data until a full endpoint-size packet (32 bytes)
@@ -1429,100 +1354,94 @@ static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate,
    * At least one device with version 0x27 appears to have this bit
    * inverted.
    */
-  if ( p_cdc->ch34x.version > 0x27 )
+  if ( p_cdc->ch34x.version > 0x27 ) {
     val |= BIT(7);
+  }
 
   return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
 }
 
 // set lcr register
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   /*
    * Chip versions before version 0x30 as read using
    * CH341_REQ_READ_VERSION used separate registers for line control
    * (stop bits, parity and word length). Version 0x30 and above use
    * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
    */
-  if ( p_cdc->ch34x.version < 0x30 )
-    return 0;
+  if ( p_cdc->ch34x.version < 0x30 ) return 0;
 
   return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
 }
 
 // set handshake (modem controls)
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
 }
 
 // detect quirks (special versions of CH34x)
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   /*
    * A subset of CH34x devices does not support all features. The
    * prescaler is limited and there is no support for sending a RS232
    * break condition. A read failure when trying to set up the latter is
    * used to detect these devices.
    */
-  switch ( step )
-  {
-  case 1:
-    p_cdc->ch34x.quirks = 0;
-    return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
-    break;
-  case 2:
-    if ( xfer->result != XFER_RESULT_SUCCESS )
-      p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
-    return true;
-    break;
-  default:
-    TU_ASSERT ( false ); // suspicious step
-    break;
+  switch (step) {
+    case 1:
+      p_cdc->ch34x.quirks = 0;
+      return ch341_read_reg_request(p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data);
+      break;
+
+    case 2:
+      if (xfer->result != XFER_RESULT_SUCCESS) {
+        p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
+      }
+      return true;
+      break;
+
+    default:
+      TU_ASSERT (false); // suspicious step
+      break;
   }
 }
 
 // internal control complete to update state such as line state, encoding
 // CH34x needs a special interface recovery due to abnormal wIndex usage
-static void ch34x_control_complete(tuh_xfer_t* xfer)
-{
-  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
-  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
-  cdch_interface_t  *p_cdc  = get_itf ( idx );
-  TU_ASSERT ( p_cdc, );
-  TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
+static void ch34x_control_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) ((xfer->user_data & 0xff00) >> 8);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT (p_cdc,);
+  TU_ASSERT (p_cdc->serial_drid == SERIAL_DRIVER_CH34X,); // ch34x_control_complete is only used for CH34x
 
   if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (xfer->setup->bRequest) {
-    case CH341_REQ_WRITE_REG: { // register write request
-      switch ( tu_le16toh ( xfer->setup->wValue ) ) {
-      case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
-        p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+      case CH341_REQ_WRITE_REG: // register write request
+        switch (tu_le16toh (xfer->setup->wValue)) {
+          case (CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER): // baudrate write
+            p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+            break;
+
+          default:
+            TU_ASSERT(false,); // unexpected register write
+            break;
+        }
         break;
-      }
-      default: {
-        TU_ASSERT(false, ); // unexpected register write
+
+      default:
+        TU_ASSERT(false,); // unexpected request
         break;
-      }
-      }
-      break;
-    }
-    default: {
-      TU_ASSERT(false, ); // unexpected request
-      break;
-    }
     }
     xfer->complete_cb = p_cdc->user_control_cb;
-    if (xfer->complete_cb)
-      xfer->complete_cb(xfer);
+    if (xfer->complete_cb) xfer->complete_cb(xfer);
   }
 }
 
-static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
-{
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) /* do not confuse with ch341_set_baudrate */ {
   TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->ch34x.baud_rate = baudrate;
@@ -1530,15 +1449,13 @@ static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh
   return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
 }
 
-static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
   // todo later
   return false;
 }
 
-static void ch34x_process_config ( tuh_xfer_t* xfer )
-{
+static void ch34x_process_config ( tuh_xfer_t* xfer ) {
   uintptr_t const   state   = xfer->user_data & 0xff;
   // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
   uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
@@ -1561,81 +1478,108 @@ static void ch34x_process_config ( tuh_xfer_t* xfer )
      */
     p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
   }
+
   // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
-  switch ( state ) {
-  case CONFIG_CH34X_STEP1: // request version read
-    TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
-    break;
-  case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
-    p_cdc->ch34x.version = xfer->buffer[0];
-    TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
-    TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
-    break;
-  case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
-    TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
-    TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP6: // detect quirks step 1
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
-#else
-    TU_ATTR_FALLTHROUGH;
-#endif
-    break;
-  case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
-    switch ( line_coding.data_bits ) {
-    case 5:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+  switch (state) {
+    case CONFIG_CH34X_STEP1: // request version read
+      TU_ASSERT (ch341_control_in(p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */0,
+                                  buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2),);
       break;
-    case 6:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+
+    case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
+      p_cdc->ch34x.version = xfer->buffer[0];
+      TU_LOG_DRV ("Chip version=%02x\r\n", p_cdc->ch34x.version);
+      TU_ASSERT (ch341_control_out(p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */0,
+                                   ch34x_process_config, CONFIG_CH34X_STEP3),);
       break;
-    case 7:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+
+    case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
+      TU_ASSERT (ch341_set_baudrate(p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config,
+                                    CONFIG_CH34X_STEP4) > 0,);
       break;
-    case 8:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+
+    case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
+      TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5) > 0,);
       break;
-    default:
-      TU_ASSERT ( false, ); // not supported data_bits
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+
+    case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
+      TU_ASSERT (ch341_set_handshake(p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6) > 0,);
       break;
-    }
-    if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
-      p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
-      if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
-      if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
-    }
-    TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
-    if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
-      p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
+
+    case CONFIG_CH34X_STEP6: // detect quirks step 1
+      TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE,
+                                     ch34x_process_config, CONFIG_CH34X_STEP7) > 0,);
+      break;
+
+    case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
+      TU_ASSERT (ch341_detect_quirks(xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0) > 0,);
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      TU_ASSERT (ch34x_set_baudrate(p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8),);
 #else
-    TU_ATTR_FALLTHROUGH;
+      TU_ATTR_FALLTHROUGH;
 #endif
-    break;
+      break;
+
+    case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
+      switch (line_coding.data_bits) {
+        case 5:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+          break;
+
+        case 6:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+          break;
+
+        case 7:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+          break;
+
+        case 8:
+          p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+          break;
+
+        default:
+          TU_ASSERT (false,); // not supported data_bits
+          p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+          break;
+      }
+
+      if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
+        p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
+
+        if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
+          p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
+        }
+
+        if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
+          p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
+        }
+      }
+      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits ==
+                                                                         CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits
+      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+        p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
+      }
+      TU_ASSERT (ch341_set_lcr(p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE) > 0,);
+#else
+      TU_ATTR_FALLTHROUGH;
+#endif
+      break;
+
     case CONFIG_CH34X_COMPLETE:
-      set_config_complete ( p_cdc, idx, itf_num );
+      set_config_complete(p_cdc, idx, itf_num);
       break;
+
     default:
-      TU_ASSERT ( false, );
+      TU_ASSERT (false,);
       break;
   }
 }
 
 #endif // CFG_TUH_CDC_CH34X
 
-#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC)
+#endif
-- 
cgit v1.3.1


From d192868d62b56ef2eab9300bf0698a77e4e01cd3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Jan 2024 18:25:15 +0700
Subject: fix sign-conversion warning

---
 src/class/cdc/cdc_host.c | 34 +++++++++++++++++++++-------------
 1 file changed, 21 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 05a061487..0cc35da52 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1207,7 +1207,7 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
       .bmRequestType_bit = {
           .recipient = TUSB_REQ_RCPT_DEVICE,
           .type      = TUSB_REQ_TYPE_VENDOR,
-          .direction = direction
+          .direction = direction & 0x01u
       },
       .bRequest = request,
       .wValue   = tu_htole16 ( value ),
@@ -1265,6 +1265,11 @@ static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, u
  */
 // calculate baudrate devisors
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
+
+static inline uint32_t clamp_val(uint32_t val, uint32_t minval, uint32_t maxval) {
+  return tu_min32(tu_max32(val, minval), maxval);
+}
+
 static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
   uint32_t fact, div, clk_div;
   bool force_fact0 = false;
@@ -1280,9 +1285,6 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
    * Clamp to supported range, this makes the (ps < 0) and (div < 2)
    * sanity checks below redundant.
    */
-  inline uint32_t max       ( uint32_t val,                  uint32_t maxval ) { return val > maxval ? val : maxval; }
-  inline uint32_t min       ( uint32_t val, uint32_t minval                  ) { return val < minval ? val : minval; }
-  inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); }
   speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS);
 
   /*
@@ -1297,7 +1299,7 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
   if (ps < 0) return -EINVAL;
 
   /* Determine corresponding divisor, rounding down. */
-  clk_div = CH341_CLK_DIV(ps, fact);
+  clk_div = CH341_CLK_DIV((uint32_t) ps, fact);
   div = CH341_CLKRATE / (clk_div * speed);
 
   /* Some devices require a lower base clock if ps < 3. */
@@ -1333,19 +1335,20 @@ static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed ) {
     fact = 0;
   }
 
-  return (0x100 - div) << 8 | fact << 2 | ps;
+  return (int32_t) ((0x100 - div) << 8 | fact << 2 | (uint32_t) ps);
 }
 
 // set baudrate (low level)
 // do not confuse with ch34x_set_baudrate
 // Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
-  int val;
-
+static int32_t ch341_set_baudrate (cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
   if (!baud_rate) return -EINVAL;
 
-  val = ch341_get_divisor(p_cdc, baud_rate);
-  if (val < 0) return -EINVAL;
+  int ret;
+  ret = ch341_get_divisor(p_cdc, baud_rate);
+  if (ret < 0) return -EINVAL;
+
+  uint16_t val = (uint16_t) ret;
 
   /*
    * CH341A buffers data until a full endpoint-size packet (32 bytes)
@@ -1355,7 +1358,7 @@ static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate,
    * inverted.
    */
   if ( p_cdc->ch34x.version > 0x27 ) {
-    val |= BIT(7);
+    val = (val | BIT(7));
   }
 
   return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
@@ -1449,8 +1452,13 @@ static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh
   return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
 }
 
-static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
+  (void) p_cdc;
+  (void) line_state;
+  (void) complete_cb;
+  (void) user_data;
+
   // todo later
   return false;
 }
-- 
cgit v1.3.1


From 1f2901e8b12258c953e3c338897f188c98b5eaed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Jan 2024 18:42:39 +0700
Subject: fix conflict of BIT() macro

---
 src/class/cdc/cdc_host.c     |  2 +-
 src/class/cdc/serial/ch34x.h | 11 ++++-------
 src/common/tusb_common.h     |  1 +
 3 files changed, 6 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 0cc35da52..ca5bfff04 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1358,7 +1358,7 @@ static int32_t ch341_set_baudrate (cdch_interface_t* p_cdc, uint32_t baud_rate,
    * inverted.
    */
   if ( p_cdc->ch34x.version > 0x27 ) {
-    val = (val | BIT(7));
+    val = (val | TU_BIT(7));
   }
 
   return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 94e18b252..4a5e61bbd 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -29,7 +29,7 @@
 
 #include <stdint.h>
 
-#define BIT(nr) ( (uint32_t)1 << (nr) )
+//#define BIT(nr) ( (uint32_t)1 << (nr) )
 
 #define CH34X_BUFFER_SIZE 2
 
@@ -93,20 +93,17 @@
 #define CH341_LCR_CS6          0x01
 #define CH341_LCR_CS5          0x00
 
-#define CH341_QUIRK_LIMITED_PRESCALER BIT(0)
-#define CH341_QUIRK_SIMULATE_BREAK  BIT(1)
+#define CH341_QUIRK_LIMITED_PRESCALER TU_BIT(0)
+#define CH341_QUIRK_SIMULATE_BREAK  TU_BIT(1)
 
 #define CH341_CLKRATE   48000000
 #define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
 #define CH341_MIN_RATE(ps)  (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512))
 
 /* Supported range is 46 to 3000000 bps. */
-#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
+#define CH341_MIN_BPS TU_DIV_CEIL(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
 #define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2))
 
-#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
-#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-
 // error codes
 #define EINVAL    22  /* Invalid argument */
 
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index caeb5f2ef..1f08ce4ed 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -37,6 +37,7 @@
 #define TU_ARRAY_SIZE(_arr)   ( sizeof(_arr) / sizeof(_arr[0]) )
 #define TU_MIN(_x, _y)        ( ( (_x) < (_y) ) ? (_x) : (_y) )
 #define TU_MAX(_x, _y)        ( ( (_x) > (_y) ) ? (_x) : (_y) )
+#define TU_DIV_CEIL(n, d)     (((n) + (d) - 1) / (d))
 
 #define TU_U16(_high, _low)   ((uint16_t) (((_high) << 8) | (_low)))
 #define TU_U16_HIGH(_u16)     ((uint8_t) (((_u16) >> 8) & 0x00ff))
-- 
cgit v1.3.1


From aa58cdcfa6a35cf5d903eaffd304db4834ce56ec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Jan 2024 01:28:29 +0700
Subject: change CFG_TUH_CDC_FTDI/CP210X_PID_LIST to
 CFG_TUH_CDC_FTDI/CP210X_VID_PID_LIST which contains both vid and pid.

---
 .idea/cmake.xml          |  2 +-
 src/class/cdc/cdc_host.c | 24 ++++++++++--------------
 src/tusb_option.h        | 18 ++++++++++--------
 3 files changed, 21 insertions(+), 23 deletions(-)

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 432e44172..3cb883e62 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -80,7 +80,7 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="lpcxpresso1769" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso1769 -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpcxpresso1769" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso1769 -DLOG=3 -DLOGGER=RTT" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 79477ef53..2463671c6 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -91,9 +91,9 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 #if CFG_TUH_CDC_FTDI
 #include "serial/ftdi_sio.h"
 
-static uint16_t const ftdi_pids[] = { CFG_TUH_CDC_FTDI_PID_LIST };
+static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST };
 enum {
-  FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
+  FTDI_PID_COUNT = sizeof(ftdi_vid_pid_list) / sizeof(ftdi_vid_pid_list[0])
 };
 
 // Store last request baudrate since divisor to baudrate is not easy
@@ -110,9 +110,9 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 #if CFG_TUH_CDC_CP210X
 #include "serial/cp210x.h"
 
-static uint16_t const cp210x_pids[] = { CFG_TUH_CDC_CP210X_PID_LIST };
+static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST };
 enum {
-  CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
+  CP210X_PID_COUNT = sizeof(cp210x_vid_pid_list) / sizeof(cp210x_vid_pid_list[0])
 };
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
@@ -647,21 +647,17 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
     #if CFG_TUH_CDC_FTDI
-    if (TU_FTDI_VID == vid) {
-      for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
-        if (ftdi_pids[i] == pid) {
-          return ftdi_open(daddr, itf_desc, max_len);
-        }
+    for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
+      if (ftdi_vid_pid_list[i][0] == vid && ftdi_vid_pid_list[i][1] == pid) {
+        return ftdi_open(daddr, itf_desc, max_len);
       }
     }
     #endif
 
     #if CFG_TUH_CDC_CP210X
-    if (TU_CP210X_VID == vid) {
-      for (size_t i = 0; i < CP210X_PID_COUNT; i++) {
-        if (cp210x_pids[i] == pid) {
-          return cp210x_open(daddr, itf_desc, max_len);
-        }
+    for (size_t i = 0; i < CP210X_PID_COUNT; i++) {
+      if (cp210x_vid_pid_list[i][0] == vid && cp210x_vid_pid_list[i][1] == pid) {
+        return cp210x_open(daddr, itf_desc, max_len);
       }
     }
     #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a76281c0c..57f026312 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -453,10 +453,12 @@
   #define CFG_TUH_CDC_FTDI 0
 #endif
 
-#ifndef CFG_TUH_CDC_FTDI_PID_LIST
-  // List of product IDs that can use the FTDI CDC driver
-  #define CFG_TUH_CDC_FTDI_PID_LIST \
-    0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, 0xCD18
+#ifndef CFG_TUH_CDC_FTDI_VID_PID_LIST
+  // List of product IDs that can use the FTDI CDC driver. 0x0403 is FTDI's VID
+  #define CFG_TUH_CDC_FTDI_VID_PID_LIST \
+    {0x0403, 0x6001}, {0x0403, 0x6006}, {0x0403, 0x6010}, {0x0403, 0x6011}, \
+    {0x0403, 0x6014}, {0x0403, 0x6015}, {0x0403, 0x8372}, {0x0403, 0xFBFA}, \
+    {0x0403, 0xCD18}
 #endif
 
 #ifndef CFG_TUH_CDC_CP210X
@@ -464,10 +466,10 @@
   #define CFG_TUH_CDC_CP210X 0
 #endif
 
-#ifndef CFG_TUH_CDC_CP210X_PID_LIST
-  // List of product IDs that can use the CP210X CDC driver
-  #define CFG_TUH_CDC_CP210X_PID_LIST \
-    0xEA60, 0xEA70
+#ifndef CFG_TUH_CDC_CP210X_VID_PID_LIST
+  // List of product IDs that can use the CP210X CDC driver. 0x10C4 is Silicon Labs' VID
+  #define CFG_TUH_CDC_CP210X_VID_PID_LIST \
+    {0x10C4, 0xEA60}, {0x10C4, 0xEA70}
 #endif
 
 #ifndef CFG_TUH_HID
-- 
cgit v1.3.1


From e2aa671346103d3ed80c2849350488d5ddf2e0dc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Jan 2024 12:54:39 +0700
Subject: move open() ad vid_pid_list into serial driver struct

---
 src/class/cdc/cdc_host.c | 102 ++++++++++++++++++++++-------------------------
 1 file changed, 47 insertions(+), 55 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index c018cf057..91e35ec8c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -104,10 +104,7 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 #if CFG_TUH_CDC_FTDI
 #include "serial/ftdi_sio.h"
 
-static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST };
-enum {
-  FTDI_PID_COUNT = TU_ARRAY_SIZE(ftdi_vid_pid_list)
-};
+static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST};
 
 // Store last request baudrate since divisor to baudrate is not easy
 static uint32_t _ftdi_requested_baud;
@@ -122,10 +119,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 #if CFG_TUH_CDC_CP210X
 #include "serial/cp210x.h"
 
-static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST };
-enum {
-  CP210X_PID_COUNT = TU_ARRAY_SIZE(cp210x_vid_pid_list)
-};
+static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST};
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
@@ -137,10 +131,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 #if CFG_TUH_CDC_CH34X
 #include "serial/ch34x.h"
 
-static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
-enum {
-  CH34X_VID_PID_COUNT = TU_ARRAY_SIZE(ch34x_vids_pids)
-};
+static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST};
 
 static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
 static void ch34x_process_config ( tuh_xfer_t* xfer );
@@ -164,9 +155,14 @@ enum {
 #if CFG_TUH_CDC_CH34X
   SERIAL_DRIVER_CH34X,
 #endif
+
+  SERIAL_DRIVER_COUNT
 };
 
 typedef struct {
+  uint16_t const (*vid_pid_list)[2];
+  uint16_t const vid_pid_count;
+  bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
   void (*const process_set_config)(tuh_xfer_t* xfer);
   bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
@@ -174,36 +170,50 @@ typedef struct {
 
 // Note driver list must be in the same order as SERIAL_DRIVER enum
 static const cdch_serial_driver_t serial_drivers[] = {
-  { .process_set_config     = acm_process_config,
-    .set_control_line_state = acm_set_control_line_state,
-    .set_baudrate           = acm_set_baudrate
+  {
+      .vid_pid_list           = NULL,
+      .vid_pid_count          = 0,
+      .open                   = acm_open,
+      .process_set_config     = acm_process_config,
+      .set_control_line_state = acm_set_control_line_state,
+      .set_baudrate           = acm_set_baudrate
   },
 
   #if CFG_TUH_CDC_FTDI
-  { .process_set_config     = ftdi_process_config,
-    .set_control_line_state = ftdi_sio_set_modem_ctrl,
-    .set_baudrate           = ftdi_sio_set_baudrate
+  {
+      .vid_pid_list           = ftdi_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ftdi_vid_pid_list),
+      .open                   = ftdi_open,
+      .process_set_config     = ftdi_process_config,
+      .set_control_line_state = ftdi_sio_set_modem_ctrl,
+      .set_baudrate           = ftdi_sio_set_baudrate
   },
   #endif
 
   #if CFG_TUH_CDC_CP210X
-  { .process_set_config     = cp210x_process_config,
-    .set_control_line_state = cp210x_set_modem_ctrl,
-    .set_baudrate           = cp210x_set_baudrate
+  {
+      .vid_pid_list           = cp210x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(cp210x_vid_pid_list),
+      .open                   = cp210x_open,
+      .process_set_config     = cp210x_process_config,
+      .set_control_line_state = cp210x_set_modem_ctrl,
+      .set_baudrate           = cp210x_set_baudrate
   },
   #endif
 
   #if CFG_TUH_CDC_CH34X
-  { .process_set_config     = ch34x_process_config,
-    .set_control_line_state = ch34x_set_modem_ctrl,
-    .set_baudrate           = ch34x_set_baudrate
+  {
+      .vid_pid_list           = ch34x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ch34x_vid_pid_list),
+      .open                   = ch34x_open,
+      .process_set_config     = ch34x_process_config,
+      .set_control_line_state = ch34x_set_modem_ctrl,
+      .set_baudrate           = ch34x_set_baudrate
   },
-#endif
+  #endif
 };
 
-enum {
-  SERIAL_DRIVER_COUNT = TU_ARRAY_SIZE(serial_drivers)
-};
+TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial driver count mismatch");
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -639,36 +649,20 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
       CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
     return acm_open(daddr, itf_desc, max_len);
   }
-  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
-  else if (TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
+  else if (SERIAL_DRIVER_COUNT > 1 &&
+           TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
-    #if CFG_TUH_CDC_FTDI
-    for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
-      if (ftdi_vid_pid_list[i][0] == vid && ftdi_vid_pid_list[i][1] == pid) {
-        return ftdi_open(daddr, itf_desc, max_len);
-      }
-    }
-    #endif
-
-    #if CFG_TUH_CDC_CP210X
-    for (size_t i = 0; i < CP210X_PID_COUNT; i++) {
-      if (cp210x_vid_pid_list[i][0] == vid && cp210x_vid_pid_list[i][1] == pid) {
-        return cp210x_open(daddr, itf_desc, max_len);
-      }
-    }
-    #endif
-
-    #if CFG_TUH_CDC_CH34X
-    for (size_t i = 0; i < CH34X_VID_PID_COUNT; i++) {
-      if ( ch34x_vids_pids[i][0] == vid && ch34x_vids_pids[i][1] == pid ) {
-        return ch34x_open(daddr, itf_desc, max_len);
+    for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) {
+      cdch_serial_driver_t const* driver = &serial_drivers[dr];
+      for (size_t i = 0; i < driver->vid_pid_count; i++) {
+        if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) {
+          return driver->open(daddr, itf_desc, max_len);
+        }
       }
     }
-    #endif
   }
-  #endif
 
   return false;
 }
@@ -683,9 +677,7 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i
   usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
 }
 
-
-bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
-{
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num) {
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
-- 
cgit v1.3.1


From 4e6408ea4940085f66c676772d77e3951e82ea11 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 16 Jan 2024 08:07:22 +0100
Subject: CDCh host: further work on CH340/CH341 support

---
 examples/host/cdc_msc_hid/src/tusb_config.h        |   3 +-
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    |   3 +-
 src/class/cdc/cdc_debug.h                          |  65 +++
 src/class/cdc/cdc_device.c                         |  21 +-
 src/class/cdc/cdc_host.c                           | 568 ++++++++++-----------
 src/class/cdc/cdc_host.h                           |   4 +-
 src/class/cdc/serial/ch34x.h                       | 103 +---
 7 files changed, 369 insertions(+), 398 deletions(-)
 create mode 100644 src/class/cdc/cdc_debug.h

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 76d59c316..ac14ef97e 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -120,8 +120,7 @@
 //------------- CDC -------------//
 
 // Set Line Control state on enumeration/mounted:
-// DTR ( bit 0), RTS (bit 1)
-#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM ( CDC_CONTROL_LINE_STATE_RTS | CDC_CONTROL_LINE_STATE_DTR )
 
 // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
 // bit rate = 115200, 1 stop bit, no parity, 8 bit data width
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index bb7c3388d..1b68dd2d8 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -125,8 +125,7 @@
 //------------- CDC -------------//
 
 // Set Line Control state on enumeration/mounted:
-// DTR ( bit 0), RTS (bit 1)
-#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM ( CDC_CONTROL_LINE_STATE_RTS | CDC_CONTROL_LINE_STATE_DTR )
 
 // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
 // bit rate = 115200, 1 stop bit, no parity, 8 bit data width
diff --git a/src/class/cdc/cdc_debug.h b/src/class/cdc/cdc_debug.h
new file mode 100644
index 000000000..879e49a50
--- /dev/null
+++ b/src/class/cdc/cdc_debug.h
@@ -0,0 +1,65 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 IngHK Heiko Kuester
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_CDC_DEBUG_H_
+#define _TUSB_CDC_DEBUG_H_
+
+#include "cdc.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// logging of line coding
+#define TU_LOG_LINE_CODING(PRE_TEXT,LINE_CODING)                            \
+  TU_LOG_DRV(PRE_TEXT "Line Coding %lu Bd, %u%c%s\r\n",                     \
+    LINE_CODING.bit_rate,                                                   \
+    LINE_CODING.data_bits,                                                  \
+    LINE_CODING.parity == CDC_LINE_CODING_PARITY_NONE ? 'N' :               \
+      LINE_CODING.parity == CDC_LINE_CODING_PARITY_ODD ? 'O' :              \
+        LINE_CODING.parity == CDC_LINE_CODING_PARITY_EVEN ? 'E' :           \
+          LINE_CODING.parity == CDC_LINE_CODING_PARITY_MARK ? 'M' :         \
+            LINE_CODING.parity == CDC_LINE_CODING_PARITY_SPACE ? 'S' : '?', \
+    LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ? "1" :            \
+      LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_1_5 ? "1.5" :      \
+        LINE_CODING.stop_bits == CDC_LINE_CODING_STOP_BITS_2 ? "2" : "?")
+
+// logging of baudrate
+#define TU_LOG_BAUDRATE(PRE_TEXT,BAUDRATE) \
+  TU_LOG_DRV(PRE_TEXT "Baudrate %lu Bd\r\n", BAUDRATE)
+
+ // logging of control line state
+#define TU_LOG_CONTROL_LINE_STATE(PRE_TEXT,LINE_STATE)            \
+  TU_LOG_DRV(PRE_TEXT "Control Line State RTS%c DTR%c\r\n", \
+    LINE_STATE & CDC_CONTROL_LINE_STATE_RTS ? '+' : '-',           \
+    LINE_STATE & CDC_CONTROL_LINE_STATE_DTR ? '+' : '-' )
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CDC_DEBUG_H_ */
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index c26264e60..b763419e7 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -32,6 +32,9 @@
 #include "device/usbd_pvt.h"
 
 #include "cdc_device.h"
+#if 0 // TODO activate and test
+#include "cdc_debug.h"
+#endif
 
 // Level where CFG_TUSB_DEBUG must be at least for this driver is logged
 #ifndef CFG_TUD_CDC_LOG_LEVEL
@@ -360,7 +363,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_SET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG_DRV("  Set Line Coding\r\n");
+        #if 0 // TODO activate, test and remove else
+          TU_LOG_LINE_CODING("  Set ", p_cdc->line_coding);
+        #else
+          TU_LOG_DRV("  Set Line Coding\r\n");
+        #endif
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
       else if ( stage == CONTROL_STAGE_ACK)
@@ -372,7 +379,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_GET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG_DRV("  Get Line Coding\r\n");
+        #if 0 // TODO activate, test and remove else
+          TU_LOG_LINE_CODING("  Get ", p_cdc->line_coding);
+        #else
+          TU_LOG_DRV("  Get Line Coding\r\n");
+        #endif
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
     break;
@@ -397,7 +408,11 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         // Disable fifo overwriting if DTR bit is set
         tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
 
-        TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+        #if 0 // TODO activate, test and remove else
+          TU_LOG_CONTROL_LINE_STATE("  Set ", p_cdc->line_state);
+        #else
+          TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+        #endif
 
         // Invoke callback
         if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f6a6773e0..d46bfecb4 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -2,7 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Copyright (c) 2023 Heiko Kuester (CH34x support)
+ * Copyright (c) 2023 IngHK Heiko Kuester
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -33,6 +33,7 @@
 #include "host/usbh_pvt.h"
 
 #include "cdc_host.h"
+#include "cdc_debug.h"
 
 // Level where CFG_TUSB_DEBUG must be at least for this driver is logged
 #ifndef CFG_TUH_CDC_LOG_LEVEL
@@ -55,7 +56,7 @@ typedef struct {
   cdc_acm_capability_t acm_capability;
   uint8_t ep_notif;
 
-  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
+  uint8_t line_state;                               // RTS, DTR (refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR)
   TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
 
   tuh_xfer_cb_t user_control_cb;
@@ -70,16 +71,9 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-  #if CFG_TUH_CDC_CH34X
-  struct {
-    uint32_t  baud_rate;
-    uint8_t   mcr;
-    uint8_t   msr;
-    uint8_t   lcr;
-    uint32_t  quirks;
-    uint8_t   version;
-  } ch34x;
-  #endif
+#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X
+  uint32_t  baudrate_requested;
+#endif
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -106,12 +100,10 @@ enum {
   FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
 };
 
-// Store last request baudrate since divisor to baudrate is not easy
-static uint32_t _ftdi_requested_baud;
-
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
 
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -128,6 +120,7 @@ enum {
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
 
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
@@ -144,6 +137,7 @@ enum {
 static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
 static void ch34x_process_config ( tuh_xfer_t* xfer );
 
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
 #endif
@@ -169,35 +163,40 @@ typedef struct {
   void (*const process_set_config)(tuh_xfer_t* xfer);
   bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 } cdch_serial_driver_t;
 
 // Note driver list must be in the same order as SERIAL_DRIVER enum
 static const cdch_serial_driver_t serial_drivers[] = {
   { .process_set_config     = acm_process_config,
     .set_control_line_state = acm_set_control_line_state,
-    .set_baudrate           = acm_set_baudrate
+    .set_baudrate           = acm_set_baudrate,
+    .set_line_coding        = acm_set_line_coding
   },
 
   #if CFG_TUH_CDC_FTDI
   { .process_set_config     = ftdi_process_config,
     .set_control_line_state = ftdi_sio_set_modem_ctrl,
-    .set_baudrate           = ftdi_sio_set_baudrate
+    .set_baudrate           = ftdi_sio_set_baudrate,
+    .set_line_coding        = ftdi_set_line_coding
   },
   #endif
 
   #if CFG_TUH_CDC_CP210X
   { .process_set_config     = cp210x_process_config,
     .set_control_line_state = cp210x_set_modem_ctrl,
-    .set_baudrate           = cp210x_set_baudrate
+    .set_baudrate           = cp210x_set_baudrate,
+    .set_line_coding        = cp210x_set_line_coding
   },
   #endif
 
   #if CFG_TUH_CDC_CH34X
   { .process_set_config     = ch34x_process_config,
     .set_control_line_state = ch34x_set_modem_ctrl,
-    .set_baudrate           = ch34x_set_baudrate
+    .set_baudrate           = ch34x_set_baudrate,
+    .set_line_coding        = ch34x_set_line_coding
   },
-#endif
+  #endif
 };
 
 enum {
@@ -304,6 +303,7 @@ bool tuh_cdc_get_dtr(uint8_t idx)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
+  TU_LOG_CONTROL_LINE_STATE("CDCh Local ", p_cdc->line_state);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
 }
@@ -312,6 +312,7 @@ bool tuh_cdc_get_rts(uint8_t idx)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
+  TU_LOG_CONTROL_LINE_STATE("CDCh Local ", p_cdc->line_state);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
@@ -322,6 +323,7 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
   TU_VERIFY(p_cdc);
 
   *line_coding = p_cdc->line_coding;
+  TU_LOG_LINE_CODING("CDCh Get ", p_cdc->line_coding);
 
   return true;
 }
@@ -440,7 +442,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
 
           case FTDI_SIO_SET_BAUD_RATE:
             // convert from divisor to baudrate is not supported
-            p_cdc->line_coding.bit_rate = _ftdi_requested_baud;
+            p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
             break;
 
           default: break;
@@ -465,12 +467,6 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
         break;
       #endif
 
-      #if CFG_TUH_CDC_CH34X
-      case SERIAL_DRIVER_CH34X:
-        TU_ASSERT(false, ); // see special ch34x_control_complete function
-        break;
-      #endif
-
       default: break;
     }
   }
@@ -487,7 +483,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
   if ( complete_cb ) {
-    return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
+    TU_VERIFY(driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data));
   }else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
@@ -501,8 +497,10 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
     p_cdc->line_state = (uint8_t) line_state;
-    return true;
   }
+  TU_LOG_CONTROL_LINE_STATE("CDCh Set ", p_cdc->line_state);
+
+  return true;
 }
 
 bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
@@ -511,7 +509,7 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
   if ( complete_cb ) {
-    return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
+    TU_VERIFY(driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data));
   }else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
@@ -525,23 +523,24 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
     p_cdc->line_coding.bit_rate = baudrate;
-    return true;
   }
+  TU_LOG_BAUDRATE("CDCh Set ", p_cdc->line_coding.bit_rate);
+
+  return true;
 }
 
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  // only ACM support this set line coding request
-  TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM);
-  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
   if ( complete_cb ) {
-    return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
-  }else {
+    TU_VERIFY(driver->set_line_coding(p_cdc, line_coding, complete_cb, user_data));
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
-    bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
+    bool ret = driver->set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
 
     if (user_data) {
       // user_data is not NULL, return result via user_data
@@ -551,8 +550,10 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
     p_cdc->line_coding = *line_coding;
-    return true;
   }
+  TU_LOG_LINE_CODING("CDCh Set ", p_cdc->line_coding);
+
+  return true;
 }
 
 //--------------------------------------------------------------------+
@@ -684,13 +685,8 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
   {
     return acm_open(daddr, itf_desc, max_len);
   }
-<<<<<<< HEAD
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
-  else if ( 0xff == itf_desc->bInterfaceClass )
-=======
-  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
   else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
->>>>>>> remotes/hathach/master
   {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
@@ -816,6 +812,8 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint1
     TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
   }
 
+  TU_LOG_DRV("[%u] CDCh ACM opened\r\n", daddr);
+
   return true;
 }
 
@@ -852,6 +850,12 @@ static void acm_process_config(tuh_xfer_t* xfer)
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_COMPLETE:
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+        TU_LOG_LINE_CODING("CDCh ACM Init ", p_cdc->line_coding);
+      #endif
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+        TU_LOG_CONTROL_LINE_STATE("CDCh ACM Init", p_cdc->line_state);
+      #endif
       // itf_num+1 to account for data interface as well
       set_config_complete(p_cdc, idx, itf_num+1);
       break;
@@ -893,6 +897,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st
 
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC ACM Set Line Conding\r\n");
+  TU_VERIFY(p_cdc->acm_capability.support_line_request);
 
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
@@ -994,6 +999,12 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_ASSERT(false, false); // TODO
+  return false;
+}
+
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
@@ -1035,7 +1046,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
-  _ftdi_requested_baud = baudrate;
+  p_cdc->baudrate_requested = baudrate;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
                                  complete_cb ? cdch_internal_control_complete : NULL, user_data));
 
@@ -1088,6 +1099,14 @@ static void ftdi_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_FTDI_COMPLETE:
       set_config_complete(p_cdc, idx, itf_num);
+      #if 0 // TODO set data format
+        #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+          TU_LOG_LINE_CODING("CDCh FTDI Init ", p_cdc->line_coding);
+        #endif
+      #endif
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+        TU_LOG_CONTROL_LINE_STATE("CDCh FTDI Init ", p_cdc->line_state);
+      #endif
       break;
 
     default:
@@ -1166,6 +1185,12 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
   return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data);
 }
 
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_ASSERT(false, false); // TODO
+  return false;
+}
+
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
@@ -1224,6 +1249,12 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CP210X_COMPLETE:
       set_config_complete(p_cdc, idx, itf_num);
+      #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now
+        TU_LOG_LINE_CODING("CDCh CP210x Init ", p_cdc->line_coding);
+      #endif
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+        TU_LOG_CONTROL_LINE_STATE("CDCh CP210x Init ", p_cdc->line_state);
+      #endif
       break;
 
     default: break;
@@ -1233,20 +1264,19 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 #endif
 
 //--------------------------------------------------------------------+
-// CH34x
+// CH34x (CH340 & CH341)
 //--------------------------------------------------------------------+
 
 #if CFG_TUH_CDC_CH34X
 
+#define CH34X_LOGS false
+
 enum {
-  CONFIG_CH34X_STEP1 = 0,
-  CONFIG_CH34X_STEP2,
-  CONFIG_CH34X_STEP3,
-  CONFIG_CH34X_STEP4,
-  CONFIG_CH34X_STEP5,
-  CONFIG_CH34X_STEP6,
-  CONFIG_CH34X_STEP7,
-  CONFIG_CH34X_STEP8,
+  CONFIG_CH34X_READ_VERSION = 0,
+  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SPECIAL_REG_WRITE,
+  CONFIG_CH34X_FLOW_CONTROL,
+  CONFIG_CH34X_MODEM_CONTROL,
   CONFIG_CH34X_COMPLETE
 };
 
@@ -1259,17 +1289,22 @@ static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, u
   cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc );
   TU_VERIFY ( p_cdc );
 
-  TU_LOG_DRV ( "CH34x opened\r\n" );
+
   p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
 
   // endpoint pair
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc );
 
   // data endpoints expected to be in pairs
-  return open_ep_stream_pair ( p_cdc, desc_ep );
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep), false);
+
+  TU_LOG_DRV("[%u] CDCh CH34x opened\r\n", daddr);
+
+  return true;
 }
 
-static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index,
+                                uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
   tusb_control_request_t const request_setup = {
       .bmRequestType_bit = {
@@ -1297,212 +1332,66 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
       .setup       = &request_setup,
       .buffer      = enum_buf,
       .complete_cb = complete_cb,
-      // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-      .user_data   = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff )
+      .user_data   = user_data
   };
 
   return tuh_control_xfer ( &xfer );
-  return false;
 }
 
-static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
   return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
 }
 
-static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                               uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
   return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
 }
 
-static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+static bool ch34x_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
-  return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
+  return ch34x_control_out ( p_cdc, CH34X_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
 }
 
-static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
-}
+//static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
+//                                     uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+//{
+//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
+//}
 
-/*
- * The device line speed is given by the following equation:
- *
- *  baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
- *
- *    0 <= ps <= 3,
- *    0 <= fact <= 1,
- *    2 <= div <= 256 if fact = 0, or
- *    9 <= div <= 256 if fact = 1
- */
-// calculate baudrate devisors
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
+uint8_t ch34x_xfer_get_itf_num ( tuh_xfer_t* xfer )
+// CH34x needs a special handling to get bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
+// CH340 and CH341 derivates have always only one interface, so it's OK to check only daddr
 {
-  uint32_t fact, div, clk_div;
-  bool force_fact0 = false;
-  int32_t ps;
-  static const uint32_t ch341_min_rates[] = {
-      CH341_MIN_RATE(0),
-      CH341_MIN_RATE(1),
-      CH341_MIN_RATE(2),
-      CH341_MIN_RATE(3),
-  };
-
-  /*
-   * Clamp to supported range, this makes the (ps < 0) and (div < 2)
-   * sanity checks below redundant.
-   */
-  inline uint32_t max       ( uint32_t val,                  uint32_t maxval ) { return val > maxval ? val : maxval; }
-  inline uint32_t min       ( uint32_t val, uint32_t minval                  ) { return val < minval ? val : minval; }
-  inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); }
-  speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS);
-
-  /*
-   * Start with highest possible base clock (fact = 1) that will give a
-   * divisor strictly less than 512.
-   */
-  fact = 1;
-  for (ps = 3; ps >= 0; ps--) {
-    if (speed > ch341_min_rates[ps])
-      break;
-  }
-
-  if (ps < 0)
-    return -EINVAL;
-
-  /* Determine corresponding divisor, rounding down. */
-  clk_div = CH341_CLK_DIV(ps, fact);
-  div = CH341_CLKRATE / (clk_div * speed);
-
-  /* Some devices require a lower base clock if ps < 3. */
-  if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
-    force_fact0 = true;
-
-  /* Halve base clock (fact = 0) if required. */
-  if (div < 9 || div > 255 || force_fact0) {
-    div /= 2;
-    clk_div *= 2;
-    fact = 0;
-  }
-
-  if (div < 2)
-    return -EINVAL;
-
-  /*
-   * Pick next divisor if resulting rate is closer to the requested one,
-   * scale up to avoid rounding errors on low rates.
-   */
-  if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
-      16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
-    div++;
-
-  /*
-   * Prefer lower base clock (fact = 0) if even divisor.
-   *
-   * Note that this makes the receiver more tolerant to errors.
-   */
-  if (fact == 1 && div % 2 == 0) {
-    div /= 2;
-    fact = 0;
-  }
-
-  return (0x100 - div) << 8 | fact << 2 | ps;
-}
-
-// set baudrate (low level)
-// do not confuse with ch34x_set_baudrate
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  int val;
-
-  if (!baud_rate)
-    return -EINVAL;
-
-  val = ch341_get_divisor(p_cdc, baud_rate);
-  if (val < 0)
-    return -EINVAL;
-
-  /*
-   * CH341A buffers data until a full endpoint-size packet (32 bytes)
-   * has been received unless bit 7 is set.
-   *
-   * At least one device with version 0x27 appears to have this bit
-   * inverted.
-   */
-  if ( p_cdc->ch34x.version > 0x27 )
-    val |= BIT(7);
-
-  return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
-}
-
-// set lcr register
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  /*
-   * Chip versions before version 0x30 as read using
-   * CH341_REQ_READ_VERSION used separate registers for line control
-   * (stop bits, parity and word length). Version 0x30 and above use
-   * CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
-   */
-  if ( p_cdc->ch34x.version < 0x30 )
-    return 0;
-
-  return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
-}
-
-// set handshake (modem controls)
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
-}
-
-// detect quirks (special versions of CH34x)
-// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
-static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
-  /*
-   * A subset of CH34x devices does not support all features. The
-   * prescaler is limited and there is no support for sending a RS232
-   * break condition. A read failure when trying to set up the latter is
-   * used to detect these devices.
-   */
-  switch ( step )
+  for ( uint8_t i=0; i<CFG_TUH_CDC; i++ )
   {
-  case 1:
-    p_cdc->ch34x.quirks = 0;
-    return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
-    break;
-  case 2:
-    if ( xfer->result != XFER_RESULT_SUCCESS )
-      p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
-    return true;
-    break;
-  default:
-    TU_ASSERT ( false ); // suspicious step
-    break;
+    const cdch_interface_t* p_cdc = &cdch_data[i];
+    if ( p_cdc->daddr == xfer->daddr ) return p_cdc->bInterfaceNumber;
   }
+
+  return INTERFACE_INVALID_NUMBER;
 }
 
 // internal control complete to update state such as line state, encoding
-// CH34x needs a special interface recovery due to abnormal wIndex usage
-static void ch34x_control_complete(tuh_xfer_t* xfer)
+static void ch34x_control_complete ( tuh_xfer_t* xfer )
 {
-  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
+  uint8_t const     itf_num = ch34x_xfer_get_itf_num ( xfer );
   uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
   cdch_interface_t  *p_cdc  = get_itf ( idx );
+  uint16_t          value   = tu_le16toh ( xfer->setup->wValue );
   TU_ASSERT ( p_cdc, );
   TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
 
-  if (xfer->result == XFER_RESULT_SUCCESS) {
-    switch (xfer->setup->bRequest) {
-    case CH341_REQ_WRITE_REG: { // register write request
-      switch ( tu_le16toh ( xfer->setup->wValue ) ) {
-      case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
-        p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
+  if ( xfer->result == XFER_RESULT_SUCCESS ) {
+    switch ( xfer->setup->bRequest ) {
+    case CH34X_REQ_WRITE_REG: { // register write request
+      switch ( value ) {
+      case ( 0x1312 ): { // baudrate write
+        p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+        #if CH34X_LOGS
+          TU_LOG_BAUDRATE("CDCh CH34x Control Complete ", p_cdc->line_coding.bit_rate);
+        #endif
         break;
       }
       default: {
@@ -1512,6 +1401,20 @@ static void ch34x_control_complete(tuh_xfer_t* xfer)
       }
       break;
     }
+    case CH34X_REQ_MODEM_CTRL: { // set modem controls RTS/DTR request
+      if ( ~value & CH34X_BIT_RTS )
+        p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
+      else
+        p_cdc->line_state &= ~CDC_CONTROL_LINE_STATE_RTS;
+      if ( ~value & CH34X_BIT_DTR )
+        p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
+      else
+        p_cdc->line_state &= ~CDC_CONTROL_LINE_STATE_DTR;
+      #if CH34X_LOGS
+        TU_LOG_CONTROL_LINE_STATE("CDCh CH34x Control Complete ", p_cdc->line_state);
+      #endif
+      break;
+    }
     default: {
       TU_ASSERT(false, ); // unexpected request
       break;
@@ -1523,118 +1426,161 @@ static void ch34x_control_complete(tuh_xfer_t* xfer)
   }
 }
 
-static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
+static bool ch34x_get_factor_divisor ( uint32_t baval, uint8_t *factor, uint8_t *divisor )
+{ // calc baudrate factor and divisor
+  uint8_t  a;
+  uint8_t  b;
+  uint32_t c;
+
+  switch (baval) {
+  case 921600:
+    a = 0xf3;
+    b = 7;
+    break;
+  case 307200:
+    a = 0xd9;
+    b = 7;
+    break;
+  default:
+    if (baval > 6000000 / 255) {
+      b = 3;
+      c = 6000000;
+    } else if (baval > 750000 / 255) {
+      b = 2;
+      c = 750000;
+    } else if (baval > 93750 / 255) {
+      b = 1;
+      c = 93750;
+    } else {
+      b = 0;
+      c = 11719;
+    }
+    a = (unsigned char)(c / baval);
+    if (a == 0 || a == 0xFF)
+      return false;
+    if ((c / a - baval) > (baval - c / (a + 1)))
+      a++;
+    a = 256 - a;
+    break;
+  }
+  *factor = a;
+  *divisor = b;
+
+  return true;
+}
+
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
-  uint32_t baud_le = tu_htole32(baudrate);
-  p_cdc->ch34x.baud_rate = baudrate;
+  TU_ASSERT(false, false); // TODO
+  return false;
+}
+
+static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+{
+  p_cdc->baudrate_requested = baudrate;
   p_cdc->user_control_cb = complete_cb;
-  return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
+  uint8_t factor, divisor;
+  TU_ASSERT ( ch34x_get_factor_divisor ( baudrate, &factor, &divisor ), false );
+  TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x1312, /* value */ (uint16_t)factor << 8 | 0x80 | divisor,
+                                complete_cb ? ch34x_control_complete : NULL, user_data ), false );
+
+  return true;
 }
 
 static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 {
-  TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
-  // todo later
-  return false;
+  p_cdc->user_control_cb = complete_cb;
+  uint16_t control = 0;
+  if ( line_state & CDC_CONTROL_LINE_STATE_RTS )
+    control |= CH34X_BIT_RTS;
+  if ( line_state & CDC_CONTROL_LINE_STATE_DTR )
+    control |= CH34X_BIT_DTR;
+  TU_ASSERT ( ch34x_control_out ( p_cdc, /* request */ CH34X_REQ_MODEM_CTRL, /* value */ (uint8_t)~control,
+                                  /* index */ 0, complete_cb ? ch34x_control_complete : NULL, user_data ), false );
+  return true;
 }
 
 static void ch34x_process_config ( tuh_xfer_t* xfer )
 {
-  uintptr_t const   state   = xfer->user_data & 0xff;
-  // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-  uint8_t const     itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
-  uint8_t const     idx     = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
-  cdch_interface_t  *p_cdc  = get_itf ( idx );
-  uint8_t           buffer [ CH34X_BUFFER_SIZE ];
-  cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+  uint8_t const           itf_num     = ch34x_xfer_get_itf_num ( xfer );
+  uintptr_t const         state       = xfer->user_data;
+  uint8_t const           idx         = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
+  cdch_interface_t        *p_cdc      = get_itf ( idx );
+  cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
+  uint8_t                 buffer[2];
   TU_ASSERT ( p_cdc, );
 
-  if ( state == 0 ) {
-    // defaults
-    p_cdc->ch34x.baud_rate = DEFAULT_BAUD_RATE;
-    p_cdc->ch34x.mcr = 0;
-    p_cdc->ch34x.msr = 0;
-    p_cdc->ch34x.quirks = 0;
-    p_cdc->ch34x.version = 0;
-    /*
-     * Some CH340 devices appear unable to change the initial LCR
-     * settings, so set a sane 8N1 default.
-     */
-    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
-  }
-  // This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
   switch ( state ) {
-  case CONFIG_CH34X_STEP1: // request version read
-    TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
-    break;
-  case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
-    p_cdc->ch34x.version = xfer->buffer[0];
-    TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
-    TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
-    break;
-  case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
-    TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
-    TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP6: // detect quirks step 1
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
-    break;
-  case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
-    TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
-#else
-    TU_ATTR_FALLTHROUGH;
-#endif
+  case CONFIG_CH34X_READ_VERSION: // request version read
+    #if CH34X_LOGS
+      TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
+    #endif
+    TU_ASSERT ( ch34x_control_in ( p_cdc, /* request */ CH34X_REQ_READ_VERSION, /* value */ 0,
+                                   /* index */ 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT ), );
     break;
-  case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
+  case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
+    uint8_t version = xfer->buffer[0];
+    #if CH34X_LOGS
+      TU_LOG_DRV ( "[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version );
+    #endif
+    // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
+    TU_ASSERT ( version >= 0x30, );
+    uint8_t factor, divisor;
+    TU_ASSERT ( ch34x_get_factor_divisor ( line_coding.bit_rate, &factor, &divisor ), );
+    uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
     switch ( line_coding.data_bits ) {
     case 5:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS5;
+      lcr |= CH34X_LCR_CS5;
       break;
     case 6:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS6;
+      lcr |= CH34X_LCR_CS6;
       break;
     case 7:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS7;
+      lcr |= CH34X_LCR_CS7;
       break;
     case 8:
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      lcr |= CH34X_LCR_CS8;
       break;
     default:
       TU_ASSERT ( false, ); // not supported data_bits
-      p_cdc->ch34x.lcr |= CH341_LCR_CS8;
+      lcr |= CH34X_LCR_CS8;
       break;
     }
     if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
-      p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
+      lcr |= CH34X_LCR_ENABLE_PAR;
       if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
+        lcr |= CH34X_LCR_PAR_EVEN;
       if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
-        p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
+        lcr |= CH34X_LCR_MARK_SPACE;
     }
     TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
     if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
-      p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
-    TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
-#else
-    TU_ATTR_FALLTHROUGH;
-#endif
+      lcr |= CH34X_LCR_STOP_BITS_2;
+    TU_ASSERT ( ch34x_control_out ( p_cdc, /* request */ CH34X_REQ_SERIAL_INIT, /* value */ (uint16_t)lcr << 8 | 0x9c,
+                                    /* index */ (uint16_t)factor << 8 | 0x80 | divisor, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE ), );
+    break;
+  }
+  case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver
+    TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x0f2c, /* value */ 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL ), );
+    break;
+  case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control
+    TU_ASSERT ( ch34x_write_reg ( p_cdc, /* reg */ 0x2727, /* value */ 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL ), );
+    break;
+  case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
+    TU_ASSERT ( ch34x_set_modem_ctrl ( p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE ), );
+    break;
+  case CONFIG_CH34X_COMPLETE:
+    p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
+    #if CH34X_LOGS
+      TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
+      TU_LOG_LINE_CODING("  ", p_cdc->line_coding);
+      TU_LOG_CONTROL_LINE_STATE("  ", p_cdc->line_state);
+    #endif
+    set_config_complete ( p_cdc, idx, itf_num );
+    break;
+  default:
+    TU_ASSERT ( false, );
     break;
-    case CONFIG_CH34X_COMPLETE:
-      set_config_complete ( p_cdc, idx, itf_num );
-      break;
-    default:
-      TU_ASSERT ( false, );
-      break;
   }
 }
 
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 9e5edd94e..8e3a2352a 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -37,7 +37,7 @@
 // Class Driver Configuration
 //--------------------------------------------------------------------+
 
-// Set Line Control state on enumeration/mounted: DTR ( bit 0), RTS (bit 1)
+// Set Line Control state on enumeration/mounted, refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR
 #ifndef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
 #define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0
 #endif
@@ -142,7 +142,7 @@ bool tuh_cdc_read_clear (uint8_t idx);
 //   - The function will return true if transfer is successful, false otherwise.
 //--------------------------------------------------------------------+
 
-// Request to Set Control Line State: DTR (bit 0), RTS (bit 1)
+// Request to Set Control Line State, refer enums CDC_CONTROL_LINE_STATE_RTS, CDC_CONTROL_LINE_STATE_DTR
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Request to set baudrate
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 94e18b252..262e012fd 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2023 Heiko Kuester (tinyusb.org)
+ * Copyright (c) 2023 IngHK Heiko Kuester (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -27,87 +27,34 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
-#include <stdint.h>
-
-#define BIT(nr) ( (uint32_t)1 << (nr) )
-
-#define CH34X_BUFFER_SIZE 2
-
-// The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c
-
-#define DEFAULT_BAUD_RATE 9600
-
-/* flags for IO-Bits */
-#define CH341_BIT_RTS (1 << 6)
-#define CH341_BIT_DTR (1 << 5)
-
-/******************************/
-/* interrupt pipe definitions */
-/******************************/
-/* always 4 interrupt bytes */
-/* first irq byte normally 0x08 */
-/* second irq byte base 0x7d + below */
-/* third irq byte base 0x94 + below */
-/* fourth irq byte normally 0xee */
-
-/* second interrupt byte */
-#define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
-
-/* status returned in third interrupt answer byte, inverted in data
-   from irq */
-#define CH341_BIT_CTS 0x01
-#define CH341_BIT_DSR 0x02
-#define CH341_BIT_RI  0x04
-#define CH341_BIT_DCD 0x08
-#define CH341_BITS_MODEM_STAT 0x0f /* all bits */
-
-/* Break support - the information used to implement this was gleaned from
- * the Net/FreeBSD uchcom.c driver by Takanori Watanabe.  Domo arigato.
- */
+// set line_coding @ enumeration
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#else // this default is necessary to work properly
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#endif
 
 // USB requests
-#define CH341_REQ_READ_VERSION 0x5F // dec 95
-#define CH341_REQ_WRITE_REG    0x9A
-#define CH341_REQ_READ_REG     0x95
-#define CH341_REQ_SERIAL_INIT  0xA1
-#define CH341_REQ_MODEM_CTRL   0xA4
+#define CH34X_REQ_READ_VERSION 0x5F // dec  95
+#define CH34X_REQ_WRITE_REG    0x9A // dec 154
+#define CH34X_REQ_READ_REG     0x95 // dec 149
+#define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
+#define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
 
-// CH34x registers
-#define CH341_REG_BREAK        0x05
-#define CH341_REG_PRESCALER    0x12
-#define CH341_REG_DIVISOR      0x13
-#define CH341_REG_LCR          0x18
-#define CH341_REG_LCR2         0x25
-
-#define CH341_NBREAK_BITS      0x01
+// modem control bits
+#define CH34X_BIT_RTS ( 1 << 6 )
+#define CH34X_BIT_DTR ( 1 << 5 )
 
 // line control bits
-#define CH341_LCR_ENABLE_RX    0x80
-#define CH341_LCR_ENABLE_TX    0x40
-#define CH341_LCR_MARK_SPACE   0x20
-#define CH341_LCR_PAR_EVEN     0x10
-#define CH341_LCR_ENABLE_PAR   0x08
-#define CH341_LCR_STOP_BITS_2  0x04
-#define CH341_LCR_CS8          0x03
-#define CH341_LCR_CS7          0x02
-#define CH341_LCR_CS6          0x01
-#define CH341_LCR_CS5          0x00
-
-#define CH341_QUIRK_LIMITED_PRESCALER BIT(0)
-#define CH341_QUIRK_SIMULATE_BREAK  BIT(1)
-
-#define CH341_CLKRATE   48000000
-#define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
-#define CH341_MIN_RATE(ps)  (CH341_CLKRATE / (CH341_CLK_DIV((ps), 1) * 512))
-
-/* Supported range is 46 to 3000000 bps. */
-#define CH341_MIN_BPS DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
-#define CH341_MAX_BPS (CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2))
-
-#define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
-#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
-
-// error codes
-#define EINVAL    22  /* Invalid argument */
+#define CH34X_LCR_ENABLE_RX    0x80
+#define CH34X_LCR_ENABLE_TX    0x40
+#define CH34X_LCR_MARK_SPACE   0x20
+#define CH34X_LCR_PAR_EVEN     0x10
+#define CH34X_LCR_ENABLE_PAR   0x08
+#define CH34X_LCR_STOP_BITS_2  0x04
+#define CH34X_LCR_CS8          0x03
+#define CH34X_LCR_CS7          0x02
+#define CH34X_LCR_CS6          0x01
+#define CH34X_LCR_CS5          0x00
 
 #endif /* _CH34X_H_ */
-- 
cgit v1.3.1


From 07e3d5c69192b1c45d52fc9760ab0ee65d8b0f0c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Jan 2024 13:16:53 +0700
Subject: fix number of endpoint for ch340x, also open notification even not
 used for now

---
 src/class/cdc/cdc_host.c     | 67 +++++++++++++++++++++++---------------------
 src/class/cdc/serial/ch34x.h |  6 ++--
 2 files changed, 38 insertions(+), 35 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 91e35ec8c..f7213d558 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -471,9 +471,9 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result);
@@ -494,9 +494,9 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result);
@@ -512,16 +512,15 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   }
 }
 
-bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   // only ACM support this set line coding request
   TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM);
   TU_VERIFY(p_cdc->acm_capability.support_line_request);
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
@@ -711,7 +710,6 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint1
 
   cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
-
   p_cdc->serial_drid = SERIAL_DRIVER_ACM;
 
   //------------- Control Interface -------------//
@@ -881,7 +879,6 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint
   TU_VERIFY(p_cdc);
 
   TU_LOG_DRV("FTDI opened\r\n");
-
   p_cdc->serial_drid = SERIAL_DRIVER_FTDI;
 
   // endpoint pair
@@ -921,8 +918,7 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-static bool
-ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
@@ -1171,26 +1167,34 @@ enum {
   CONFIG_CH34X_COMPLETE
 };
 
-static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len ) {
-  // CH34x Interface includes 1 vendor interface + 3 bulk endpoints
-  TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
-  TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
+  TU_VERIFY (itf_desc->bNumEndpoints == 3);
+  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
 
-  cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc );
-  TU_VERIFY ( p_cdc );
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY (p_cdc);
 
-  TU_LOG_DRV ( "CH34x opened\r\n" );
+  TU_LOG_DRV ("CH34x opened\r\n");
   p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
 
-  // endpoint pair
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc );
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
 
   // data endpoints expected to be in pairs
-  return open_ep_stream_pair ( p_cdc, desc_ep );
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
+  desc_ep += 2;
+
+  // Interrupt endpoint: not used for now
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
+            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
+  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
+  p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+  return true;
 }
 
-static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
-{
+static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
+                              uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request_setup = {
       .bmRequestType_bit = {
           .recipient = TUSB_REQ_RCPT_DEVICE,
@@ -1198,17 +1202,17 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
           .direction = direction & 0x01u
       },
       .bRequest = request,
-      .wValue   = tu_htole16 ( value ),
-      .wIndex   = tu_htole16 ( index ),
-      .wLength  = tu_htole16 ( length )
+      .wValue   = tu_htole16 (value),
+      .wIndex   = tu_htole16 (index),
+      .wLength  = tu_htole16 (length)
   };
 
   // use usbh enum buf since application variable does not live long enough
   uint8_t* enum_buf = NULL;
 
-  if ( buffer && length > 0 ) {
+  if (buffer && length > 0) {
     enum_buf = usbh_get_enum_buf();
-    tu_memcpy_s ( enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length );
+    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
   }
 
   tuh_xfer_t xfer = {
@@ -1218,11 +1222,10 @@ static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint
       .buffer      = enum_buf,
       .complete_cb = complete_cb,
       // CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-      .user_data   = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff )
+      .user_data   = (uintptr_t) ((p_cdc->bInterfaceNumber & 0xff) << 8) | (user_data & 0xff)
   };
 
-  return tuh_control_xfer ( &xfer );
-  return false;
+  return tuh_control_xfer(&xfer);
 }
 
 static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) {
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 4a5e61bbd..cc3ac99fe 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2023 Heiko Kuester (tinyusb.org)
+ * Copyright (c) 2023 Heiko Kuester
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -34,6 +34,7 @@
 #define CH34X_BUFFER_SIZE 2
 
 // The following defines have been taken over from Linux driver /drivers/usb/serial/ch341.c
+// Note: updated driver can also be found in https://github.com/WCHSoftGroup/ch341ser_linux/tree/main/driver
 
 #define DEFAULT_BAUD_RATE 9600
 
@@ -53,8 +54,7 @@
 /* second interrupt byte */
 #define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
 
-/* status returned in third interrupt answer byte, inverted in data
-   from irq */
+/* status returned in third interrupt answer byte, inverted in data from irq */
 #define CH341_BIT_CTS 0x01
 #define CH341_BIT_DSR 0x02
 #define CH341_BIT_RI  0x04
-- 
cgit v1.3.1


From 46ac03ba8537a32ae2bf1f7d864879657b696f81 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Jan 2024 17:45:16 +0700
Subject: change code style

---
 src/class/cdc/cdc_host.c | 97 +++++++++++++++++++++++-------------------------
 1 file changed, 46 insertions(+), 51 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 8ef26a7d9..5541b5dee 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1291,25 +1291,22 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
 
   if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (xfer->setup->bRequest) {
-      case CH34X_REQ_WRITE_REG: { // register write request
+      case CH34X_REQ_WRITE_REG:
+        // register write request
         switch (value) {
-          case (0x1312): { // baudrate write
+          case (0x1312):
+            // baudrate write
             p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
-            #if CH34X_LOGS
-            TU_LOG_BAUDRATE("CDCh CH34x Control Complete ", p_cdc->line_coding.bit_rate);
-            #endif
             break;
-          }
 
-          default: {
+          default:
             TU_ASSERT(false,); // unexpected register write
             break;
-          }
         }
         break;
-      }
 
-      case CH34X_REQ_MODEM_CTRL: { // set modem controls RTS/DTR request
+      case CH34X_REQ_MODEM_CTRL:
+        // set modem controls RTS/DTR request
         if (~value & CH34X_BIT_RTS) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
         } else {
@@ -1322,16 +1319,11 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR;
         }
 
-        #if CH34X_LOGS
-        TU_LOG_CONTROL_LINE_STATE("CDCh CH34x Control Complete ", p_cdc->line_state);
-        #endif
         break;
-      }
 
-      default: {
+      default:
         TU_ASSERT(false,); // unexpected request
         break;
-      }
     }
 
     xfer->complete_cb = p_cdc->user_control_cb;
@@ -1393,33 +1385,31 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t con
   return false;
 }
 
-static bool
-ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb,
-                   uintptr_t user_data) {
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->baudrate_requested = baudrate;
   p_cdc->user_control_cb = complete_cb;
   uint8_t factor, divisor;
-  TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor), false);
+  TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor));
   uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor);
-  TU_ASSERT (
-      ch34x_write_reg(p_cdc, /* reg */ 0x1312, /* value */ value,
-                      complete_cb ? ch34x_control_complete : NULL, user_data), false);
+  TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value,
+                             complete_cb ? ch34x_control_complete : NULL, user_data));
 
   return true;
 }
 
-static bool
-ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb,
-                     uintptr_t user_data) {
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->user_control_cb = complete_cb;
   uint16_t control = 0;
-  if (line_state & CDC_CONTROL_LINE_STATE_RTS)
+  if (line_state & CDC_CONTROL_LINE_STATE_RTS) {
     control |= CH34X_BIT_RTS;
-  if (line_state & CDC_CONTROL_LINE_STATE_DTR)
+  }
+  if (line_state & CDC_CONTROL_LINE_STATE_DTR) {
     control |= CH34X_BIT_DTR;
-  TU_ASSERT (
-      ch34x_control_out(p_cdc, /* request */ CH34X_REQ_MODEM_CTRL, /* value */ (uint8_t) ~control,
-          /* index */ 0, complete_cb ? ch34x_control_complete : NULL, user_data), false);
+  }
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, (uint8_t) ~control, 0,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
 }
 
@@ -1437,9 +1427,9 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
       #if CH34X_LOGS
       TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
       #endif
-      TU_ASSERT (ch34x_control_in(p_cdc, /* request */ CH34X_REQ_READ_VERSION, /* value */ 0,
-          /* index */ 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
+
     case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
       uint8_t version = xfer->buffer[0];
       #if CH34X_LOGS
@@ -1468,46 +1458,51 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
           lcr |= CH34X_LCR_CS8;
           break;
       }
+
       if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
         lcr |= CH34X_LCR_ENABLE_PAR;
         if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE)
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
           lcr |= CH34X_LCR_PAR_EVEN;
+        }
         if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE)
+            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
           lcr |= CH34X_LCR_MARK_SPACE;
+        }
       }
       TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits ==
                                                                          CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits
-      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2)
+      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
         lcr |= CH34X_LCR_STOP_BITS_2;
-      TU_ASSERT (ch34x_control_out(p_cdc, /* request */ CH34X_REQ_SERIAL_INIT, /* value */
-                                   (uint16_t) (lcr << 8 | 0x9c),
-          /* index */ (uint16_t) (factor << 8 | 0x80 | divisor), ch34x_process_config,
-                                   CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      }
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
+                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
     }
-    case CONFIG_CH34X_SPECIAL_REG_WRITE: // do special reg write, purpose unknown, overtaken from WCH driver
-      TU_ASSERT (ch34x_write_reg(p_cdc, /* reg */ 0x0f2c, /* value */ 0x0007, ch34x_process_config,
-                                 CONFIG_CH34X_FLOW_CONTROL),);
+
+    case CONFIG_CH34X_SPECIAL_REG_WRITE:
+      // do special reg write, purpose unknown, overtaken from WCH driver
+      TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
-    case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control
-      TU_ASSERT (ch34x_write_reg(p_cdc, /* reg */ 0x2727, /* value */ 0x0000, ch34x_process_config,
-                                 CONFIG_CH34X_MODEM_CONTROL),);
+
+    case CONFIG_CH34X_FLOW_CONTROL:
+      // no hardware flow control
+      TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
-    case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
-      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config,
-                                      CONFIG_CH34X_COMPLETE),);
+
+    case CONFIG_CH34X_MODEM_CONTROL:
+      // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
+      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
       break;
+
     case CONFIG_CH34X_COMPLETE:
       p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
       #if CH34X_LOGS
       TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
-      TU_LOG_LINE_CODING("  ", p_cdc->line_coding);
-      TU_LOG_CONTROL_LINE_STATE("  ", p_cdc->line_state);
       #endif
       set_config_complete(p_cdc, idx, itf_num);
       break;
+
     default:
       TU_ASSERT (false,);
       break;
-- 
cgit v1.3.1


From 482a8068a51025ee8c31ccdb4355801c185172cc Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 16 Jan 2024 14:51:04 +0100
Subject: change code style and code cleanup

---
 src/class/cdc/cdc_host.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 5541b5dee..4cecc79a1 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1260,13 +1260,13 @@ static bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t
 }
 
 static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data);
+  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, value, complete_cb, user_data);
 }
 
 //static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
 //                                     uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
 //{
-//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
+//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
 //}
 
 uint8_t ch34x_xfer_get_itf_num(tuh_xfer_t* xfer) {
@@ -1327,7 +1327,9 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
     }
 
     xfer->complete_cb = p_cdc->user_control_cb;
-    if (xfer->complete_cb)xfer->complete_cb(xfer);
+    if (xfer->complete_cb) {
+      xfer->complete_cb(xfer);
+    }
   }
 }
 
@@ -1363,8 +1365,12 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
         c = 11719;
       }
       a = (unsigned char) (c / baval);
-      if (a == 0 || a == 0xFF) return false;
-      if ((c / a - baval) > (baval - c / (a + 1))) a++;
+      if (a == 0 || a == 0xFF) {
+        return false;
+      }
+      if ((c / a - baval) > (baval - c / (a + 1))) {
+        a++;
+      }
       a = (uint8_t) (256 - a);
       break;
   }
@@ -1425,7 +1431,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   switch (state) {
     case CONFIG_CH34X_READ_VERSION: // request version read
       #if CH34X_LOGS
-      TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
+        TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
       #endif
       TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
@@ -1433,7 +1439,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
     case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
       uint8_t version = xfer->buffer[0];
       #if CH34X_LOGS
-      TU_LOG_DRV ( "[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version );
+        TU_LOG_DRV("[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version);
       #endif
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
       TU_ASSERT (version >= 0x30,);
@@ -1470,8 +1476,8 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
           lcr |= CH34X_LCR_MARK_SPACE;
         }
       }
-      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits ==
-                                                                         CDC_LINE_CODING_STOP_BITS_2,); // not supported 1.5 stop bits
+      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ||
+                 line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // 1.5 stop bits not supported
       if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
         lcr |= CH34X_LCR_STOP_BITS_2;
       }
@@ -1498,7 +1504,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
     case CONFIG_CH34X_COMPLETE:
       p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
       #if CH34X_LOGS
-      TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
+        TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
       #endif
       set_config_complete(p_cdc, idx, itf_num);
       break;
-- 
cgit v1.3.1


From f221c0fb6683fc552febbb9a52300d66f031d275 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Jan 2024 14:45:09 +0700
Subject: more clean up

---
 src/class/cdc/cdc_host.c     | 28 ++++++++++------------------
 src/class/cdc/serial/ch34x.h | 13 +++++++++++++
 2 files changed, 23 insertions(+), 18 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 4cecc79a1..faee062cf 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -670,6 +670,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
 }
 
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
+  TU_LOG_DRV("CDCh Set Configure complete\r\n");
   if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
 
   // Prepare for incoming data
@@ -1176,8 +1177,6 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 #if CFG_TUH_CDC_CH34X
 
-#define CH34X_LOGS false
-
 enum {
   CONFIG_CH34X_READ_VERSION = 0,
   CONFIG_CH34X_SERIAL_INIT,
@@ -1247,14 +1246,13 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_
   return tuh_control_xfer(&xfer);
 }
 
-static bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
-                              tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data);
+static inline bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data);
 }
 
-static bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
-                 uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb,
-                 uintptr_t user_data) {
+static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                    uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize,
                            complete_cb, user_data);
 }
@@ -1425,27 +1423,24 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
-  uint8_t buffer[2];
+  uint8_t buffer[2]; // TODO remove
   TU_ASSERT (p_cdc,);
 
   switch (state) {
     case CONFIG_CH34X_READ_VERSION: // request version read
-      #if CH34X_LOGS
-        TU_LOG_DRV ( "[%u] CDCh CH34x Process Config started\r\n", p_cdc->daddr );
-      #endif
+      TU_LOG_DRV("[%u] CDCh CH34x attempt to read version\r\n", p_cdc->daddr);
       TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
 
     case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
       uint8_t version = xfer->buffer[0];
-      #if CH34X_LOGS
-        TU_LOG_DRV("[%u] CDCh CH34x Chip version=%02x\r\n", p_cdc->daddr, version);
-      #endif
+      TU_LOG_DRV("[%u] CDCh CH34x Chip version = %02x\r\n", p_cdc->daddr, version);
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
       TU_ASSERT (version >= 0x30,);
       uint8_t factor, divisor;
       TU_ASSERT (ch34x_get_factor_divisor(line_coding.bit_rate, &factor, &divisor),);
       uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+
       switch (line_coding.data_bits) {
         case 5:
           lcr |= CH34X_LCR_CS5;
@@ -1503,9 +1498,6 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CH34X_COMPLETE:
       p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
-      #if CH34X_LOGS
-        TU_LOG_DRV("CDCh CH34x Process Config Complete\r\n");
-      #endif
       set_config_complete(p_cdc, idx, itf_num);
       break;
 
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 557e093a9..54b5b3560 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -27,6 +27,10 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
+// There is no official documentation for the CH34x chips. Reference can be found
+// - https://github.com/WCHSoftGroup/ch341ser_linux
+// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
+
 // set line_coding @ enumeration
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
 #define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
@@ -41,6 +45,15 @@
 #define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
 #define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
 
+#define CH34X_REG_BREAK        0x05
+#define CH34X_REG_PRESCALER    0x12
+#define CH34X_REG_DIVISOR      0x13
+#define CH34X_REG_LCR          0x18
+#define CH34X_REG_LCR2         0x25
+#define CH34X_REG_MCR_MSR      0x06
+#define CH34X_REG_MCR_MSR2     0x07
+#define CH34X_NBREAK_BITS      0x01
+
 // modem control bits
 #define CH34X_BIT_RTS ( 1 << 6 )
 #define CH34X_BIT_DTR ( 1 << 5 )
-- 
cgit v1.3.1


From 3968a0fff87c794266284af7901e334d122e894c Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Wed, 17 Jan 2024 16:04:31 +0100
Subject: implemented ch34x_set_line_coding() and some code cleanup

---
 src/class/cdc/cdc_host.c     | 177 ++++++++++++++++++++++++++-----------------
 src/class/cdc/serial/ch34x.h |   7 ++
 2 files changed, 116 insertions(+), 68 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index faee062cf..45a03a31d 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1179,7 +1179,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 enum {
   CONFIG_CH34X_READ_VERSION = 0,
-  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SET_LINE_CODING,
   CONFIG_CH34X_SPECIAL_REG_WRITE,
   CONFIG_CH34X_FLOW_CONTROL,
   CONFIG_CH34X_MODEM_CONTROL,
@@ -1292,11 +1292,10 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
       case CH34X_REQ_WRITE_REG:
         // register write request
         switch (value) {
-          case (0x1312):
+          case 0x1312: 
             // baudrate write
             p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
             break;
-
           default:
             TU_ASSERT(false,); // unexpected register write
             break;
@@ -1310,13 +1309,60 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         } else {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS;
         }
-
         if (~value & CH34X_BIT_DTR) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
         } else {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR;
         }
+        break;
 
+      case CH34X_REQ_SERIAL_INIT:
+        // serial init request (set line coding incl. baudrate)
+        p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+        uint8_t lcr = (uint8_t) (value >> 8);
+        TU_ASSERT (lcr & CH34X_LCR_ENABLE_RX && lcr & CH34X_LCR_ENABLE_TX,); // both have to be enabled
+        switch (lcr & CH34X_LCR_CS_MASK) {
+          case CH34X_LCR_CS5:
+            p_cdc->line_coding.data_bits = 5;
+            break;
+          case CH34X_LCR_CS6:
+            p_cdc->line_coding.data_bits = 6;
+            break;
+          case CH34X_LCR_CS7:
+            p_cdc->line_coding.data_bits = 7;
+            break;
+          case CH34X_LCR_CS8:
+            p_cdc->line_coding.data_bits = 8;
+            break;
+          default:
+            TU_ASSERT (false,); // unexpected data_bits lcr
+            break;
+        }
+        if (lcr & CH34X_LCR_STOP_BITS_2) {
+          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_2;
+        } else {
+          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_1;
+        }
+        switch (lcr & CH34X_LCR_PAR_MASK) {
+          case 0:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_NONE;
+            break;
+          case CH34X_LCR_ENABLE_PAR:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_ODD;
+            break;
+          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_EVEN;
+            break;
+          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_MARK;
+            break;
+          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN:
+            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_SPACE;
+            break;
+          default:
+            TU_ASSERT (false,); // unexpected parity lcr
+            break;
+        }
         break;
 
       default:
@@ -1378,15 +1424,57 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
   return true;
 }
 
+// calc lcr register value (data bits, parity, stop bits)
+static bool ch34x_get_lcr(cdc_line_coding_t const* line_coding, uint8_t *lcr) {
+  *lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+  switch (line_coding->data_bits) {
+    case 5:
+      *lcr |= CH34X_LCR_CS5;
+      break;
+    case 6:
+      *lcr |= CH34X_LCR_CS6;
+      break;
+    case 7:
+      *lcr |= CH34X_LCR_CS7;
+      break;
+    case 8:
+      *lcr |= CH34X_LCR_CS8;
+      break;
+    default:
+      TU_ASSERT (false); // data_bits not supported
+      break;
+  }
+  TU_ASSERT (line_coding->parity == CDC_LINE_CODING_PARITY_NONE || // supported parities
+             line_coding->parity == CDC_LINE_CODING_PARITY_ODD  || line_coding->parity == CDC_LINE_CODING_PARITY_EVEN ||
+             line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE);
+  if (line_coding->parity != CDC_LINE_CODING_PARITY_NONE) {
+    *lcr |= CH34X_LCR_ENABLE_PAR;
+    if (line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
+      *lcr |= CH34X_LCR_PAR_EVEN;
+    }
+    if (line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
+      *lcr |= CH34X_LCR_MARK_SPACE;
+    }
+  }
+  TU_ASSERT (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_1 || 
+             line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2); // not supported 1.5 stop bits
+  if (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+    *lcr |= CH34X_LCR_STOP_BITS_2;
+  }
+
+  return true;
+}
+
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  // TODO implement later
-  (void) p_cdc;
-  (void) line_coding;
-  (void) complete_cb;
-  (void) user_data;
-
-  return false;
+  p_cdc->baudrate_requested = line_coding->bit_rate;
+  p_cdc->user_control_cb = complete_cb;
+  uint8_t factor, divisor, lcr;
+  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
+  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
 }
 
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
@@ -1398,7 +1486,6 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
   uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor);
   TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value,
                              complete_cb ? ch34x_control_complete : NULL, user_data));
-
   return true;
 }
 
@@ -1427,82 +1514,36 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   TU_ASSERT (p_cdc,);
 
   switch (state) {
-    case CONFIG_CH34X_READ_VERSION: // request version read
-      TU_LOG_DRV("[%u] CDCh CH34x attempt to read version\r\n", p_cdc->daddr);
-      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
+    case CONFIG_CH34X_READ_VERSION:
+      // version read request
+      TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SET_LINE_CODING),);
       break;
-
-    case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
+    case CONFIG_CH34X_SET_LINE_CODING:
+      // handle version read data, set CH34x line coding (incl. baudrate)
       uint8_t version = xfer->buffer[0];
-      TU_LOG_DRV("[%u] CDCh CH34x Chip version = %02x\r\n", p_cdc->daddr, version);
-      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
+      TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
+      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
-      uint8_t factor, divisor;
-      TU_ASSERT (ch34x_get_factor_divisor(line_coding.bit_rate, &factor, &divisor),);
-      uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
-
-      switch (line_coding.data_bits) {
-        case 5:
-          lcr |= CH34X_LCR_CS5;
-          break;
-        case 6:
-          lcr |= CH34X_LCR_CS6;
-          break;
-        case 7:
-          lcr |= CH34X_LCR_CS7;
-          break;
-        case 8:
-          lcr |= CH34X_LCR_CS8;
-          break;
-        default:
-          TU_ASSERT (false,); // not supported data_bits
-          lcr |= CH34X_LCR_CS8;
-          break;
-      }
-
-      if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
-        lcr |= CH34X_LCR_ENABLE_PAR;
-        if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
-          lcr |= CH34X_LCR_PAR_EVEN;
-        }
-        if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
-            line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
-          lcr |= CH34X_LCR_MARK_SPACE;
-        }
-      }
-      TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ||
-                 line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // 1.5 stop bits not supported
-      if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
-        lcr |= CH34X_LCR_STOP_BITS_2;
-      }
-      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
-                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      TU_ASSERT (ch34x_set_line_coding(p_cdc, &line_coding, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
-    }
-
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
       // do special reg write, purpose unknown, overtaken from WCH driver
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
-
     case CONFIG_CH34X_FLOW_CONTROL:
       // no hardware flow control
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
-
     case CONFIG_CH34X_MODEM_CONTROL:
       // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
       TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
       break;
-
     case CONFIG_CH34X_COMPLETE:
-      p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
       set_config_complete(p_cdc, idx, itf_num);
       break;
-
     default:
-      TU_ASSERT (false,);
+      TU_ASSERT (false,); // something gone wrong, should never reached
       break;
   }
 }
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 54b5b3560..b4ed7420c 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -27,9 +27,13 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
+// For simplicity, only the name CH34X is used here,
+// but specifically only CH340 and CH341 are supported.
+
 // There is no official documentation for the CH34x chips. Reference can be found
 // - https://github.com/WCHSoftGroup/ch341ser_linux
 // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
+// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
 
 // set line_coding @ enumeration
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
@@ -45,6 +49,7 @@
 #define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
 #define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
 
+// registers
 #define CH34X_REG_BREAK        0x05
 #define CH34X_REG_PRESCALER    0x12
 #define CH34X_REG_DIVISOR      0x13
@@ -64,10 +69,12 @@
 #define CH34X_LCR_MARK_SPACE   0x20
 #define CH34X_LCR_PAR_EVEN     0x10
 #define CH34X_LCR_ENABLE_PAR   0x08
+#define CH34X_LCR_PAR_MASK     0x38 // all parity bits
 #define CH34X_LCR_STOP_BITS_2  0x04
 #define CH34X_LCR_CS8          0x03
 #define CH34X_LCR_CS7          0x02
 #define CH34X_LCR_CS6          0x01
 #define CH34X_LCR_CS5          0x00
+#define CH34X_LCR_CS_MASK      0x03 // all CSx bits
 
 #endif /* _CH34X_H_ */
-- 
cgit v1.3.1


From 30eb35f17f1baa4698da0cd45dbc3dff8906d7c0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 01:06:24 +0700
Subject: - revert the use of serial init for set line coding - update
 ch34x_get_lcr and ch34x_get_factor_divisor

---
 src/class/cdc/cdc_host.c     | 146 ++++++++++++++++++++++++-------------------
 src/class/cdc/serial/ch34x.h |   6 ++
 2 files changed, 87 insertions(+), 65 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 45a03a31d..150ac21f2 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1179,7 +1179,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 enum {
   CONFIG_CH34X_READ_VERSION = 0,
-  CONFIG_CH34X_SET_LINE_CODING,
+  CONFIG_CH34X_SERIAL_INIT,
   CONFIG_CH34X_SPECIAL_REG_WRITE,
   CONFIG_CH34X_FLOW_CONTROL,
   CONFIG_CH34X_MODEM_CONTROL,
@@ -1231,7 +1231,9 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_
 
   if (buffer && length > 0) {
     enum_buf = usbh_get_enum_buf();
-    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+    if (direction == TUSB_DIR_OUT) {
+      tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+    }
   }
 
   tuh_xfer_t xfer = {
@@ -1257,8 +1259,8 @@ static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, ui
                            complete_cb, user_data);
 }
 
-static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, value, complete_cb, user_data);
+static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data);
 }
 
 //static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
@@ -1292,10 +1294,11 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
       case CH34X_REQ_WRITE_REG:
         // register write request
         switch (value) {
-          case 0x1312: 
+          case CH34X_REG16_DIVISOR_PRESCALER:
             // baudrate write
             p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
             break;
+
           default:
             TU_ASSERT(false,); // unexpected register write
             break;
@@ -1309,6 +1312,7 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         } else {
           p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS;
         }
+
         if (~value & CH34X_BIT_DTR) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
         } else {
@@ -1377,8 +1381,8 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   }
 }
 
-// calc baudrate factor and divisor
-static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* divisor) {
+// calculate divisor and prescaler for baudrate, return it as 16-bit combined value
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   uint8_t a;
   uint8_t b;
   uint32_t c;
@@ -1410,7 +1414,7 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
       }
       a = (unsigned char) (c / baval);
       if (a == 0 || a == 0xFF) {
-        return false;
+        return 0;
       }
       if ((c / a - baval) > (baval - c / (a + 1))) {
         a++;
@@ -1418,74 +1422,75 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
       a = (uint8_t) (256 - a);
       break;
   }
-  *factor = a;
-  *divisor = b;
 
-  return true;
+  // reg divisor = a, reg prescaler = b
+  // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
+  // otherwise the chip will buffer data.
+  return (uint16_t) (a << 8 | 0x80 | b);
 }
 
-// calc lcr register value (data bits, parity, stop bits)
-static bool ch34x_get_lcr(cdc_line_coding_t const* line_coding, uint8_t *lcr) {
-  *lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
-  switch (line_coding->data_bits) {
-    case 5:
-      *lcr |= CH34X_LCR_CS5;
-      break;
-    case 6:
-      *lcr |= CH34X_LCR_CS6;
-      break;
-    case 7:
-      *lcr |= CH34X_LCR_CS7;
+static inline uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
+  uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+  TU_VERIFY(data_bits >= 5, 0);
+  lcr |= (uint8_t) (data_bits - 5);
+
+  if (parity) {
+    lcr |= CH34X_LCR_ENABLE_PAR;
+  }
+  switch(parity) {
+    case CDC_LINE_CODING_PARITY_EVEN:
+      lcr |= CH34X_LCR_PAR_EVEN;
       break;
-    case 8:
-      *lcr |= CH34X_LCR_CS8;
+
+    case CDC_LINE_CODING_PARITY_MARK:
+      lcr |= CH34X_LCR_MARK_SPACE;
       break;
-    default:
-      TU_ASSERT (false); // data_bits not supported
+
+    case CDC_LINE_CODING_PARITY_SPACE:
+      lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
       break;
+
+    default: break;
   }
-  TU_ASSERT (line_coding->parity == CDC_LINE_CODING_PARITY_NONE || // supported parities
-             line_coding->parity == CDC_LINE_CODING_PARITY_ODD  || line_coding->parity == CDC_LINE_CODING_PARITY_EVEN ||
-             line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE);
-  if (line_coding->parity != CDC_LINE_CODING_PARITY_NONE) {
-    *lcr |= CH34X_LCR_ENABLE_PAR;
-    if (line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
-      *lcr |= CH34X_LCR_PAR_EVEN;
-    }
-    if (line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
-      *lcr |= CH34X_LCR_MARK_SPACE;
-    }
-  }
-  TU_ASSERT (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_1 || 
-             line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2); // not supported 1.5 stop bits
-  if (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
-    *lcr |= CH34X_LCR_STOP_BITS_2;
+
+  // 1.5 stop bits not supported
+  TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0);
+  if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+    lcr |= CH34X_LCR_STOP_BITS_2;
   }
 
-  return true;
+  return lcr;
 }
 
-static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->baudrate_requested = line_coding->bit_rate;
-  p_cdc->user_control_cb = complete_cb;
-  uint8_t factor, divisor, lcr;
-  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
-  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
-  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
-                               complete_cb ? ch34x_control_complete : NULL, user_data));
-  return true;
-}
+//static bool ch34x_set_line_data(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+//                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
 
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->baudrate_requested = baudrate;
   p_cdc->user_control_cb = complete_cb;
-  uint8_t factor, divisor;
-  TU_ASSERT (ch34x_get_factor_divisor(baudrate, &factor, &divisor));
-  uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor);
-  TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value,
-                             complete_cb ? ch34x_control_complete : NULL, user_data));
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps != 0);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb ? ch34x_control_complete : NULL, user_data));
+
+  return true;
+}
+
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+//  p_cdc->baudrate_requested = line_coding->bit_rate;
+//  p_cdc->user_control_cb = complete_cb;
+//  uint8_t factor, divisor, lcr;
+//  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
+//  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
+//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
+//                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  (void) p_cdc;
+  (void) line_coding;
+  (void) complete_cb;
+  (void) user_data;
+
   return true;
 }
 
@@ -1515,35 +1520,46 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
 
   switch (state) {
     case CONFIG_CH34X_READ_VERSION:
-      // version read request
       TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
-      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SET_LINE_CODING),);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
       break;
-    case CONFIG_CH34X_SET_LINE_CODING:
+
+    case CONFIG_CH34X_SERIAL_INIT: {
       // handle version read data, set CH34x line coding (incl. baudrate)
       uint8_t version = xfer->buffer[0];
       TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
-      TU_ASSERT (ch34x_set_line_coding(p_cdc, &line_coding, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
+      TU_ASSERT(div_ps != 0, );
+
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
+                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
+    }
+
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
       // do special reg write, purpose unknown, overtaken from WCH driver
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
+
     case CONFIG_CH34X_FLOW_CONTROL:
       // no hardware flow control
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
+
     case CONFIG_CH34X_MODEM_CONTROL:
       // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
       TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
       break;
+
     case CONFIG_CH34X_COMPLETE:
       set_config_complete(p_cdc, idx, itf_num);
       break;
+
     default:
-      TU_ASSERT (false,); // something gone wrong, should never reached
+      TU_ASSERT (false,);
       break;
   }
 }
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index b4ed7420c..3f78a3007 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -59,6 +59,12 @@
 #define CH34X_REG_MCR_MSR2     0x07
 #define CH34X_NBREAK_BITS      0x01
 
+#define CH341_REG_0x0F         0x0F // undocumented register
+#define CH341_REG_0x2C         0x2C // undocumented register
+#define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
+
+#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+
 // modem control bits
 #define CH34X_BIT_RTS ( 1 << 6 )
 #define CH34X_BIT_DTR ( 1 << 5 )
-- 
cgit v1.3.1


From c568a6793e99dde311802d4b4cb0633d2d6f5830 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 12:14:45 +0700
Subject: - add requested line coding to make update data format easier -
 change ch34x_xfer_get_itf_num() to simply 0

---
 src/class/cdc/cdc_host.c | 295 ++++++++++++++++++++++-------------------------
 1 file changed, 136 insertions(+), 159 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 150ac21f2..3843a8edc 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -60,6 +60,11 @@ typedef struct {
   uint8_t line_state;                               // DTR (bit0), RTS (bit1)
   TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
 
+  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
+  cdc_line_coding_t requested_line_coding;
+  // 1 byte padding
+  #endif
+
   tuh_xfer_cb_t user_control_cb;
 
   struct {
@@ -72,10 +77,6 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-
-#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X
-  uint32_t  baudrate_requested;
-#endif
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -429,7 +430,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
 
           case FTDI_SIO_SET_BAUD_RATE:
             // convert from divisor to baudrate is not supported
-            p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
             break;
 
           default: break;
@@ -968,7 +969,7 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
-  p_cdc->baudrate_requested = baudrate;
+  p_cdc->requested_line_coding.bit_rate = baudrate;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
                                  complete_cb ? cdch_internal_control_complete : NULL, user_data));
 
@@ -1186,6 +1187,9 @@ enum {
   CONFIG_CH34X_COMPLETE
 };
 
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
+
 static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
   // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
   TU_VERIFY (itf_desc->bNumEndpoints == 3);
@@ -1269,20 +1273,10 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_
 //  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
 //}
 
-uint8_t ch34x_xfer_get_itf_num(tuh_xfer_t* xfer) {
-// CH34x needs a special handling to get bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
-// CH340 and CH341 derivates have always only one interface, so it's OK to check only daddr
-  for (uint8_t i = 0; i < CFG_TUH_CDC; i++) {
-    const cdch_interface_t* p_cdc = &cdch_data[i];
-    if (p_cdc->daddr == xfer->daddr) return p_cdc->bInterfaceNumber;
-  }
-
-  return INTERFACE_INVALID_NUMBER;
-}
-
 // internal control complete to update state such as line state, encoding
 static void ch34x_control_complete(tuh_xfer_t* xfer) {
-  uint8_t const itf_num = ch34x_xfer_get_itf_num(xfer);
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   uint16_t value = tu_le16toh (xfer->setup->wValue);
@@ -1296,7 +1290,14 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         switch (value) {
           case CH34X_REG16_DIVISOR_PRESCALER:
             // baudrate write
-            p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
+            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+            break;
+
+          case CH32X_REG16_LCR2_LCR:
+            // data format write
+            p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
+            p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
+            p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
             break;
 
           default:
@@ -1305,68 +1306,26 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
         }
         break;
 
-      case CH34X_REQ_MODEM_CTRL:
-        // set modem controls RTS/DTR request
-        if (~value & CH34X_BIT_RTS) {
+      case CH34X_REQ_MODEM_CTRL: {
+        // set modem controls RTS/DTR request. Note: signals are inverted
+        uint16_t const modem_signal = ~value;
+        if (modem_signal & CH34X_BIT_RTS) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
         } else {
-          p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS;
+          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
         }
 
-        if (~value & CH34X_BIT_DTR) {
+        if (modem_signal & CH34X_BIT_DTR) {
           p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
         } else {
-          p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR;
+          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
         }
         break;
+      }
 
       case CH34X_REQ_SERIAL_INIT:
         // serial init request (set line coding incl. baudrate)
-        p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
-        uint8_t lcr = (uint8_t) (value >> 8);
-        TU_ASSERT (lcr & CH34X_LCR_ENABLE_RX && lcr & CH34X_LCR_ENABLE_TX,); // both have to be enabled
-        switch (lcr & CH34X_LCR_CS_MASK) {
-          case CH34X_LCR_CS5:
-            p_cdc->line_coding.data_bits = 5;
-            break;
-          case CH34X_LCR_CS6:
-            p_cdc->line_coding.data_bits = 6;
-            break;
-          case CH34X_LCR_CS7:
-            p_cdc->line_coding.data_bits = 7;
-            break;
-          case CH34X_LCR_CS8:
-            p_cdc->line_coding.data_bits = 8;
-            break;
-          default:
-            TU_ASSERT (false,); // unexpected data_bits lcr
-            break;
-        }
-        if (lcr & CH34X_LCR_STOP_BITS_2) {
-          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_2;
-        } else {
-          p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_1;
-        }
-        switch (lcr & CH34X_LCR_PAR_MASK) {
-          case 0:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_NONE;
-            break;
-          case CH34X_LCR_ENABLE_PAR:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_ODD;
-            break;
-          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_EVEN;
-            break;
-          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_MARK;
-            break;
-          case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN:
-            p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_SPACE;
-            break;
-          default:
-            TU_ASSERT (false,); // unexpected parity lcr
-            break;
-        }
+        p_cdc->line_coding = p_cdc->requested_line_coding;
         break;
 
       default:
@@ -1381,93 +1340,17 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   }
 }
 
-// calculate divisor and prescaler for baudrate, return it as 16-bit combined value
-static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
-  uint8_t a;
-  uint8_t b;
-  uint32_t c;
-
-  switch (baval) {
-    case 921600:
-      a = 0xf3;
-      b = 7;
-      break;
-
-    case 307200:
-      a = 0xd9;
-      b = 7;
-      break;
-
-    default:
-      if (baval > 6000000 / 255) {
-        b = 3;
-        c = 6000000;
-      } else if (baval > 750000 / 255) {
-        b = 2;
-        c = 750000;
-      } else if (baval > 93750 / 255) {
-        b = 1;
-        c = 93750;
-      } else {
-        b = 0;
-        c = 11719;
-      }
-      a = (unsigned char) (c / baval);
-      if (a == 0 || a == 0xFF) {
-        return 0;
-      }
-      if ((c / a - baval) > (baval - c / (a + 1))) {
-        a++;
-      }
-      a = (uint8_t) (256 - a);
-      break;
-  }
-
-  // reg divisor = a, reg prescaler = b
-  // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
-  // otherwise the chip will buffer data.
-  return (uint16_t) (a << 8 | 0x80 | b);
-}
-
-static inline uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
-  uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
-  TU_VERIFY(data_bits >= 5, 0);
-  lcr |= (uint8_t) (data_bits - 5);
-
-  if (parity) {
-    lcr |= CH34X_LCR_ENABLE_PAR;
-  }
-  switch(parity) {
-    case CDC_LINE_CODING_PARITY_EVEN:
-      lcr |= CH34X_LCR_PAR_EVEN;
-      break;
-
-    case CDC_LINE_CODING_PARITY_MARK:
-      lcr |= CH34X_LCR_MARK_SPACE;
-      break;
-
-    case CDC_LINE_CODING_PARITY_SPACE:
-      lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
-      break;
-
-    default: break;
-  }
-
-  // 1.5 stop bits not supported
-  TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0);
-  if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
-    lcr |= CH34X_LCR_STOP_BITS_2;
-  }
-
-  return lcr;
-}
-
-//static bool ch34x_set_line_data(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+//static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
 //                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+//  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
+//                                complete_cb ? ch34x_control_complete : NULL, user_data));
+//  return false;
+//}
 
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->baudrate_requested = baudrate;
+  p_cdc->requested_line_coding.bit_rate = baudrate;
   p_cdc->user_control_cb = complete_cb;
   uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
   TU_VERIFY(div_ps != 0);
@@ -1496,24 +1379,29 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t con
 
 static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->user_control_cb = complete_cb;
-  uint16_t control = 0;
+  uint8_t control = 0;
   if (line_state & CDC_CONTROL_LINE_STATE_RTS) {
     control |= CH34X_BIT_RTS;
   }
   if (line_state & CDC_CONTROL_LINE_STATE_DTR) {
     control |= CH34X_BIT_DTR;
   }
-  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, (uint8_t) ~control, 0,
+
+  // CH34x signals are inverted
+  control = ~control;
+
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0,
                                complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
 }
 
 static void ch34x_process_config(tuh_xfer_t* xfer) {
-  uint8_t const itf_num = ch34x_xfer_get_itf_num(xfer);
-  uintptr_t const state = xfer->user_data;
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
+  uintptr_t const state = xfer->user_data;
   cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
   uint8_t buffer[2]; // TODO remove
   TU_ASSERT (p_cdc,);
@@ -1526,14 +1414,17 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CH34X_SERIAL_INIT: {
       // handle version read data, set CH34x line coding (incl. baudrate)
-      uint8_t version = xfer->buffer[0];
+      uint8_t const version = xfer->buffer[0];
       TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
+
       uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
       TU_ASSERT(div_ps != 0, );
 
       uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+
+      // Init CH34x with line coding
       TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
                                    ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
@@ -1541,6 +1432,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
       // do special reg write, purpose unknown, overtaken from WCH driver
+      p_cdc->line_coding = line_coding;
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
 
@@ -1564,6 +1456,91 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   }
 }
 
+//------------- CH34x helper  -------------//
+
+// calculate divisor and prescaler for baudrate, return it as 16-bit combined value
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
+  uint8_t a;
+  uint8_t b;
+  uint32_t c;
+
+  switch (baval) {
+    case 921600:
+      a = 0xf3;
+      b = 7;
+      break;
+
+    case 307200:
+      a = 0xd9;
+      b = 7;
+      break;
+
+    default:
+      if (baval > 6000000 / 255) {
+        b = 3;
+        c = 6000000;
+      } else if (baval > 750000 / 255) {
+        b = 2;
+        c = 750000;
+      } else if (baval > 93750 / 255) {
+        b = 1;
+        c = 93750;
+      } else {
+        b = 0;
+        c = 11719;
+      }
+      a = (unsigned char) (c / baval);
+      if (a == 0 || a == 0xFF) {
+        return 0;
+      }
+      if ((c / a - baval) > (baval - c / (a + 1))) {
+        a++;
+      }
+      a = (uint8_t) (256 - a);
+      break;
+  }
+
+  // reg divisor = a, reg prescaler = b
+  // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
+  // otherwise the chip will buffer data.
+  return (uint16_t) (a << 8 | 0x80 | b);
+}
+
+// calculate lcr value from data coding
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
+  uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+  TU_VERIFY(data_bits >= 5, 0);
+  lcr |= (uint8_t) (data_bits - 5);
+
+  if (parity) {
+    lcr |= CH34X_LCR_ENABLE_PAR;
+  }
+  switch(parity) {
+    case CDC_LINE_CODING_PARITY_EVEN:
+      lcr |= CH34X_LCR_PAR_EVEN;
+      break;
+
+    case CDC_LINE_CODING_PARITY_MARK:
+      lcr |= CH34X_LCR_MARK_SPACE;
+      break;
+
+    case CDC_LINE_CODING_PARITY_SPACE:
+      lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
+      break;
+
+    default: break;
+  }
+
+  // 1.5 stop bits not supported
+  TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0);
+  if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+    lcr |= CH34X_LCR_STOP_BITS_2;
+  }
+
+  return lcr;
+}
+
+
 #endif // CFG_TUH_CDC_CH34X
 
 #endif
-- 
cgit v1.3.1


From 23c2d929a1bae39578b195c7c7b068fb718212bd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 12:40:37 +0700
Subject: refactor process_internal_control_complete()

---
 src/class/cdc/cdc_host.c | 142 +++++++++++++++++++++++------------------------
 1 file changed, 69 insertions(+), 73 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 3843a8edc..bfaa64a77 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -396,26 +396,23 @@ bool tuh_cdc_read_clear (uint8_t idx) {
 // Control Endpoint API
 //--------------------------------------------------------------------+
 
-// internal control complete to update state such as line state, encoding
-static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
-  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t* p_cdc = get_itf(idx);
+static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t* xfer) {
   TU_ASSERT(p_cdc, );
+  uint16_t const value = tu_le16toh(xfer->setup->wValue);
 
   if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (p_cdc->serial_drid) {
       case SERIAL_DRIVER_ACM:
         switch (xfer->setup->bRequest) {
           case CDC_REQUEST_SET_CONTROL_LINE_STATE:
-            p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case CDC_REQUEST_SET_LINE_CODING: {
             uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
             memcpy(&p_cdc->line_coding, xfer->buffer, len);
-          }
             break;
+          }
 
           default: break;
         }
@@ -425,11 +422,10 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
       case SERIAL_DRIVER_FTDI:
         switch (xfer->setup->bRequest) {
           case FTDI_SIO_MODEM_CTRL:
-            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case FTDI_SIO_SET_BAUD_RATE:
-            // convert from divisor to baudrate is not supported
             p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
             break;
 
@@ -442,22 +438,62 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
       case SERIAL_DRIVER_CP210X:
         switch(xfer->setup->bRequest) {
           case CP210X_SET_MHS:
-            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case CP210X_SET_BAUDRATE: {
             uint32_t baudrate;
             memcpy(&baudrate, xfer->buffer, sizeof(uint32_t));
             p_cdc->line_coding.bit_rate = tu_le32toh(baudrate);
-          }
             break;
+          }
+
+          default: break;
         }
         break;
       #endif
 
       #if CFG_TUH_CDC_CH34X
       case SERIAL_DRIVER_CH34X:
-        TU_ASSERT(false, ); // see special ch34x_control_complete function
+        switch (xfer->setup->bRequest) {
+          case CH34X_REQ_WRITE_REG:
+            // register write request
+            switch (value) {
+              case CH34X_REG16_DIVISOR_PRESCALER:
+                // baudrate
+                p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+                break;
+
+              case CH32X_REG16_LCR2_LCR:
+                // data format
+                p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
+                p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
+                p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
+                break;
+
+              default: break;
+            }
+            break;
+
+          case CH34X_REQ_MODEM_CTRL: {
+            // set modem controls RTS/DTR request. Note: signals are inverted
+            uint16_t const modem_signal = ~value;
+            if (modem_signal & CH34X_BIT_RTS) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
+            }
+
+            if (modem_signal & CH34X_BIT_DTR) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
+            }
+            break;
+          }
+
+          default: break;
+        }
         break;
       #endif
 
@@ -471,6 +507,15 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
   }
 }
 
+// internal control complete to update state such as line state, encoding
+static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+
+  process_internal_control_complete(p_cdc, xfer);
+}
+
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
@@ -1279,70 +1324,16 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = 0;
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
-  uint16_t value = tu_le16toh (xfer->setup->wValue);
-  TU_ASSERT (p_cdc,);
-  TU_ASSERT (p_cdc->serial_drid == SERIAL_DRIVER_CH34X,);
-
-  if (xfer->result == XFER_RESULT_SUCCESS) {
-    switch (xfer->setup->bRequest) {
-      case CH34X_REQ_WRITE_REG:
-        // register write request
-        switch (value) {
-          case CH34X_REG16_DIVISOR_PRESCALER:
-            // baudrate write
-            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
-            break;
-
-          case CH32X_REG16_LCR2_LCR:
-            // data format write
-            p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
-            p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
-            p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
-            break;
-
-          default:
-            TU_ASSERT(false,); // unexpected register write
-            break;
-        }
-        break;
-
-      case CH34X_REQ_MODEM_CTRL: {
-        // set modem controls RTS/DTR request. Note: signals are inverted
-        uint16_t const modem_signal = ~value;
-        if (modem_signal & CH34X_BIT_RTS) {
-          p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
-        } else {
-          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
-        }
-
-        if (modem_signal & CH34X_BIT_DTR) {
-          p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
-        } else {
-          p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
-        }
-        break;
-      }
-
-      case CH34X_REQ_SERIAL_INIT:
-        // serial init request (set line coding incl. baudrate)
-        p_cdc->line_coding = p_cdc->requested_line_coding;
-        break;
-
-      default:
-        TU_ASSERT(false,); // unexpected request
-        break;
-    }
-
-    xfer->complete_cb = p_cdc->user_control_cb;
-    if (xfer->complete_cb) {
-      xfer->complete_cb(xfer);
-    }
-  }
+  process_internal_control_complete(p_cdc, xfer);
 }
 
 //static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
 //                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
 //  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+//  p_cdc->requested_line_coding.stop_bits = stop_bits;
+//  p_cdc->requested_line_coding.parity = parity;
+//  p_cdc->requested_line_coding.data_bits = data_bits;
+//
 //  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
 //                                complete_cb ? ch34x_control_complete : NULL, user_data));
 //  return false;
@@ -1350,16 +1341,21 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
 
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  p_cdc->requested_line_coding.bit_rate = baudrate;
-  p_cdc->user_control_cb = complete_cb;
   uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
   TU_VERIFY(div_ps != 0);
+
+  p_cdc->requested_line_coding.bit_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
                             complete_cb ? ch34x_control_complete : NULL, user_data));
 
   return true;
 }
 
+//static void ch34x_set_line_coding_stage1(tuh_xfer_t* xfer) {
+//
+//}
+
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
 //  p_cdc->baudrate_requested = line_coding->bit_rate;
-- 
cgit v1.3.1


From 98781bb903d94190d57ad4b9436a85a31d67404c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 15:58:05 +0700
Subject: - add ch34x_set_data_format() - add ch34x_set_line_coding()

---
 examples/host/cdc_msc_hid/src/cdc_app.c |  68 ++++++++++------------
 src/class/cdc/cdc_host.c                | 100 ++++++++++++++++++++++----------
 src/class/cdc/serial/ch34x.h            |   3 +-
 3 files changed, 102 insertions(+), 69 deletions(-)

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index a1b26e49c..81052047c 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -27,20 +27,11 @@
 #include "tusb.h"
 #include "bsp/board_api.h"
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-
-//------------- IMPLEMENTATION -------------//
-
-size_t get_console_inputs(uint8_t* buf, size_t bufsize)
-{
+size_t get_console_inputs(uint8_t* buf, size_t bufsize) {
   size_t count = 0;
-  while (count < bufsize)
-  {
+  while (count < bufsize) {
     int ch = board_getchar();
-    if ( ch <= 0 ) break;
+    if (ch <= 0) break;
 
     buf[count] = (uint8_t) ch;
     count++;
@@ -49,22 +40,18 @@ size_t get_console_inputs(uint8_t* buf, size_t bufsize)
   return count;
 }
 
-void cdc_app_task(void)
-{
-  uint8_t buf[64+1]; // +1 for extra null character
-  uint32_t const bufsize = sizeof(buf)-1;
+void cdc_app_task(void) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
 
   uint32_t count = get_console_inputs(buf, bufsize);
   buf[count] = 0;
 
   // loop over all mounted interfaces
-  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
-  {
-    if ( tuh_cdc_mounted(idx) )
-    {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+    if (tuh_cdc_mounted(idx)) {
       // console --> cdc interfaces
-      if (count)
-      {
+      if (count) {
         tuh_cdc_write(idx, buf, count);
         tuh_cdc_write_flush(idx);
       }
@@ -72,11 +59,14 @@ void cdc_app_task(void)
   }
 }
 
+//--------------------------------------------------------------------+
+// TinyUSB callbacks
+//--------------------------------------------------------------------+
+
 // Invoked when received new data
-void tuh_cdc_rx_cb(uint8_t idx)
-{
-  uint8_t buf[64+1]; // +1 for extra null character
-  uint32_t const bufsize = sizeof(buf)-1;
+void tuh_cdc_rx_cb(uint8_t idx) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
 
   // forward cdc interfaces -> console
   uint32_t count = tuh_cdc_read(idx, buf, bufsize);
@@ -85,29 +75,31 @@ void tuh_cdc_rx_cb(uint8_t idx)
   printf((char*) buf);
 }
 
-void tuh_cdc_mount_cb(uint8_t idx)
-{
-  tuh_itf_info_t itf_info = { 0 };
+// Invoked when a device with CDC interface is mounted
+// idx is index of cdc interface in the internal pool.
+void tuh_cdc_mount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
 
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
   // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
   // otherwise you need to call tuh_cdc_set_line_coding() first
-  cdc_line_coding_t line_coding = { 0 };
-  if ( tuh_cdc_get_local_line_coding(idx, &line_coding) )
-  {
+  cdc_line_coding_t line_coding = {0};
+  if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
     printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
-    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity  , line_coding.data_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
   }
 #endif
 }
 
-void tuh_cdc_umount_cb(uint8_t idx)
-{
-  tuh_itf_info_t itf_info = { 0 };
+// Invoked when a device with CDC interface is unmounted
+void tuh_cdc_umount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
 }
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index bfaa64a77..37fa30982 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1327,48 +1327,88 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
   process_internal_control_complete(p_cdc, xfer);
 }
 
-//static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
-//                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-//  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
-//  p_cdc->requested_line_coding.stop_bits = stop_bits;
-//  p_cdc->requested_line_coding.parity = parity;
-//  p_cdc->requested_line_coding.data_bits = data_bits;
-//
-//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
-//                                complete_cb ? ch34x_control_complete : NULL, user_data));
-//  return false;
-//}
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.stop_bits = stop_bits;
+  p_cdc->requested_line_coding.parity = parity;
+  p_cdc->requested_line_coding.data_bits = data_bits;
+
+  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
 
-static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
   TU_VERIFY(div_ps != 0);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb, user_data));
+  return true;
+}
 
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->requested_line_coding.bit_rate = baudrate;
   p_cdc->user_control_cb = complete_cb;
-  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
-                            complete_cb ? ch34x_control_complete : NULL, user_data));
-
+  TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate,
+                                     complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
 }
 
-//static void ch34x_set_line_coding_stage1(tuh_xfer_t* xfer) {
-//
-//}
+static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = 0;
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
 
+  if (xfer->result == XFER_RESULT_SUCCESS) {
+    // stage 1 success, continue to stage 2
+    p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+    TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity,
+                                    p_cdc->requested_line_coding.data_bits, ch34x_control_complete, xfer->user_data), );
+  } else {
+    // stage 1 failed, notify user
+    xfer->complete_cb = p_cdc->user_control_cb;
+    if (xfer->complete_cb) {
+      xfer->complete_cb(xfer);
+    }
+  }
+}
+
+// 2 stages: set baudrate (stage1) + set data format (stage2)
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-//  p_cdc->baudrate_requested = line_coding->bit_rate;
-//  p_cdc->user_control_cb = complete_cb;
-//  uint8_t factor, divisor, lcr;
-//  TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
-//  TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
-//  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
-//                               complete_cb ? ch34x_control_complete : NULL, user_data));
-  (void) p_cdc;
-  (void) line_coding;
-  (void) complete_cb;
-  (void) user_data;
+  p_cdc->requested_line_coding = *line_coding;
+  p_cdc->user_control_cb = complete_cb;
+
+  if (complete_cb) {
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate,
+                                       ch34x_set_line_coding_stage1_complete, user_data));
+  } else {
+    // sync call
+    xfer_result_t result;
+
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.bit_rate = line_coding->bit_rate;
+
+    // stage 2 set data format
+    TU_ASSERT(ch34x_set_data_format(p_cdc, line_coding->stop_bits, line_coding->parity, line_coding->data_bits,
+                                    NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = line_coding->stop_bits;
+    p_cdc->line_coding.parity = line_coding->parity;
+    p_cdc->line_coding.data_bits = line_coding->data_bits;
+
+    // update transfer result, user_data is expected to point to xfer_result_t
+    if (user_data) {
+      user_data = result;
+    }
+  }
 
   return true;
 }
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 3f78a3007..5def8d212 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -63,7 +63,8 @@
 #define CH341_REG_0x2C         0x2C // undocumented register
 #define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
 
-#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH34X_REG16_DIVISOR_PRESCALER  TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH32X_REG16_LCR2_LCR           TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
 
 // modem control bits
 #define CH34X_BIT_RTS ( 1 << 6 )
-- 
cgit v1.3.1


From c196a2ed9cbd27188472d76ec428fdb24931d0b6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 16:04:30 +0700
Subject: move code around

---
 src/class/cdc/cdc_host.c | 94 +++++++++++++++++++++++++-----------------------
 1 file changed, 49 insertions(+), 45 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 37fa30982..8965ee261 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1223,46 +1223,12 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 #if CFG_TUH_CDC_CH34X
 
-enum {
-  CONFIG_CH34X_READ_VERSION = 0,
-  CONFIG_CH34X_SERIAL_INIT,
-  CONFIG_CH34X_SPECIAL_REG_WRITE,
-  CONFIG_CH34X_FLOW_CONTROL,
-  CONFIG_CH34X_MODEM_CONTROL,
-  CONFIG_CH34X_COMPLETE
-};
-
 static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
 static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
 
-static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
-  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
-  TU_VERIFY (itf_desc->bNumEndpoints == 3);
-  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
-
-  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
-  TU_VERIFY (p_cdc);
-
-  TU_LOG_DRV ("CH34x opened\r\n");
-  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
-
-  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
-
-  // data endpoints expected to be in pairs
-  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
-  desc_ep += 2;
-
-  // Interrupt endpoint: not used for now
-  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
-            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
-  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
-  p_cdc->ep_notif = desc_ep->bEndpointAddress;
-
-  return true;
-}
-
+//------------- control requestt -------------//
 static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
-                  uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+                              uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request_setup = {
       .bmRequestType_bit = {
           .recipient = TUSB_REQ_RCPT_DEVICE,
@@ -1318,6 +1284,17 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_
 //  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
 //}
 
+static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps != 0);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb, user_data));
+  return true;
+}
+
+//------------- Driver API -------------//
+
 // internal control complete to update state such as line state, encoding
 static void ch34x_control_complete(tuh_xfer_t* xfer) {
   // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
@@ -1339,15 +1316,6 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui
   return true;
 }
 
-static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
-                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
-  TU_VERIFY(div_ps != 0);
-  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
-                            complete_cb, user_data));
-  return true;
-}
-
 static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   p_cdc->requested_line_coding.bit_rate = baudrate;
@@ -1432,6 +1400,42 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
   return true;
 }
 
+//------------- Enumeration -------------//
+enum {
+  CONFIG_CH34X_READ_VERSION = 0,
+  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SPECIAL_REG_WRITE,
+  CONFIG_CH34X_FLOW_CONTROL,
+  CONFIG_CH34X_MODEM_CONTROL,
+  CONFIG_CH34X_COMPLETE
+};
+
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
+  TU_VERIFY (itf_desc->bNumEndpoints == 3);
+  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY (p_cdc);
+
+  TU_LOG_DRV ("CH34x opened\r\n");
+  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
+
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
+  desc_ep += 2;
+
+  // Interrupt endpoint: not used for now
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
+            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
+  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
+  p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+  return true;
+}
+
 static void ch34x_process_config(tuh_xfer_t* xfer) {
   // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
   uint8_t const itf_num = 0;
-- 
cgit v1.3.1


From 55cb713264a1fe531b548a05290ee8fe1289828f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Jan 2024 16:56:32 +0700
Subject: - add new API tuh_cdc_set_data_format() - add typedef for cdc enum

---
 src/class/cdc/cdc.h      | 20 +++++------
 src/class/cdc/cdc_host.c | 90 ++++++++++++++++++++++++++++++++++++++++++------
 src/class/cdc/cdc_host.h | 13 +++----
 3 files changed, 95 insertions(+), 28 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index deec32ae4..5cbd658fe 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -136,8 +136,7 @@ typedef enum{
 //--------------------------------------------------------------------+
 
 /// Communication Interface Management Element Request Codes
-typedef enum
-{
+typedef enum {
   CDC_REQUEST_SEND_ENCAPSULATED_COMMAND                    = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface
   CDC_REQUEST_GET_ENCAPSULATED_RESPONSE                    = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface.
   CDC_REQUEST_SET_COMM_FEATURE                             = 0x02,
@@ -180,39 +179,38 @@ typedef enum
   CDC_REQUEST_GET_ATM_VC_STATISTICS                        = 0x53,
 
   CDC_REQUEST_MDLM_SEMANTIC_MODEL                          = 0x60,
-}cdc_management_request_t;
+} cdc_management_request_t;
 
-enum {
+typedef enum {
   CDC_CONTROL_LINE_STATE_DTR = 0x01,
   CDC_CONTROL_LINE_STATE_RTS = 0x02,
-};
+} cdc_control_line_state_t;
 
-enum {
+typedef enum {
   CDC_LINE_CODING_STOP_BITS_1   = 0, // 1   bit
   CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits
   CDC_LINE_CODING_STOP_BITS_2   = 2, // 2   bits
-};
+} cdc_line_coding_stopbits_t;
 
 // TODO Backward compatible for typos. Maybe removed in the future release
 #define CDC_LINE_CONDING_STOP_BITS_1   CDC_LINE_CODING_STOP_BITS_1
 #define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5
 #define CDC_LINE_CONDING_STOP_BITS_2   CDC_LINE_CODING_STOP_BITS_2
 
-enum {
+typedef enum {
   CDC_LINE_CODING_PARITY_NONE  = 0,
   CDC_LINE_CODING_PARITY_ODD   = 1,
   CDC_LINE_CODING_PARITY_EVEN  = 2,
   CDC_LINE_CODING_PARITY_MARK  = 3,
   CDC_LINE_CODING_PARITY_SPACE = 4,
-};
+} cdc_line_coding_parity_t;
 
 //--------------------------------------------------------------------+
 // Management Element Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
 
 /// 6.3 Notification Codes
-typedef enum
-{
+typedef enum {
   CDC_NOTIF_NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
   CDC_NOTIF_RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
   CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 8965ee261..f5182efc2 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -90,9 +90,10 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC];
 static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void acm_process_config(tuh_xfer_t* xfer);
 
+static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 //------------- FTDI prototypes -------------//
 #if CFG_TUH_CDC_FTDI
@@ -100,15 +101,13 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe
 
 static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST};
 
-// Store last request baudrate since divisor to baudrate is not easy
-// static uint32_t _ftdi_requested_baud;
-
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
 
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
 //------------- CP210X prototypes -------------//
@@ -120,9 +119,10 @@ static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIS
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
 
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
 //------------- CH34x prototypes -------------//
@@ -131,16 +131,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 
 static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST};
 
-static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
-static void ch34x_process_config ( tuh_xfer_t* xfer );
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len);
+static void ch34x_process_config(tuh_xfer_t* xfer);
 
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
-static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
 //------------- Common -------------//
-
 enum {
   SERIAL_DRIVER_ACM = 0,
 
@@ -166,6 +166,7 @@ typedef struct {
   void (*const process_set_config)(tuh_xfer_t* xfer);
   bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_data_format)(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 } cdch_serial_driver_t;
 
@@ -178,6 +179,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = acm_process_config,
       .set_control_line_state = acm_set_control_line_state,
       .set_baudrate           = acm_set_baudrate,
+      .set_data_format        = acm_set_data_format,
       .set_line_coding        = acm_set_line_coding
   },
 
@@ -189,6 +191,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = ftdi_process_config,
       .set_control_line_state = ftdi_sio_set_modem_ctrl,
       .set_baudrate           = ftdi_sio_set_baudrate,
+      .set_data_format        = ftdi_set_data_format,
       .set_line_coding        = ftdi_set_line_coding
   },
   #endif
@@ -201,6 +204,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = cp210x_process_config,
       .set_control_line_state = cp210x_set_modem_ctrl,
       .set_baudrate           = cp210x_set_baudrate,
+      .set_data_format        = cp210x_set_data_format,
       .set_line_coding        = cp210x_set_line_coding
   },
   #endif
@@ -213,6 +217,7 @@ static const cdch_serial_driver_t serial_drivers[] = {
       .process_set_config     = ch34x_process_config,
       .set_control_line_state = ch34x_set_modem_ctrl,
       .set_baudrate           = ch34x_set_baudrate,
+      .set_data_format        = ch34x_set_data_format,
       .set_line_coding        = ch34x_set_line_coding
   },
   #endif
@@ -562,6 +567,32 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   }
 }
 
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if (complete_cb) {
+    return driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, user_data);
+  } else {
+    // blocking
+    xfer_result_t result = XFER_RESULT_INVALID;
+    bool ret = driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = stop_bits;
+    p_cdc->line_coding.parity = parity;
+    p_cdc->line_coding.data_bits = data_bits;
+    return true;
+  }
+}
+
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
@@ -900,6 +931,19 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const
   return true;
 }
 
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC ACM Set Data Format\r\n");
+
+  cdc_line_coding_t line_coding;
+  line_coding.bit_rate = p_cdc->line_coding.bit_rate;
+  line_coding.stop_bits = stop_bits;
+  line_coding.parity = parity;
+  line_coding.data_bits = data_bits;
+
+  return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
+}
+
 static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_VERIFY(p_cdc->acm_capability.support_line_request);
   cdc_line_coding_t line_coding = p_cdc->line_coding;
@@ -968,6 +1012,18 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
 static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   (void) p_cdc;
   (void) line_coding;
@@ -1161,6 +1217,18 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
                             complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 9e5edd94e..d512a23a5 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -148,8 +148,11 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 // Request to set baudrate
 bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
-// Request to Set Line Coding (ACM only)
-// Should only use if you don't work with serial devices such as FTDI/CP210x
+// Request to set data format
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to Set Line Coding = baudrate + data format
+// Note: only implemented by ACM and CH34x, not supported by FTDI and CP210x yet
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Request to Get Line Coding (ACM only)
@@ -159,15 +162,13 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 
 // Connect by set both DTR, RTS
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data);
 }
 
 // Disconnect by clear both DTR, RTS
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data);
 }
 
-- 
cgit v1.3.1


From 87d509d416ea7c250f4256f897f6cc9a7b7d2121 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 20 Jan 2024 01:42:31 +0700
Subject: make CFG_TUH_CDC_LINE_CODING_ON_ENUM optional for ch34x

---
 examples/host/cdc_msc_hid/src/cdc_app.c |  8 ++++++--
 src/class/cdc/cdc_host.c                | 19 ++++++++++++++-----
 src/class/cdc/serial/ch34x.h            | 12 +-----------
 3 files changed, 21 insertions(+), 18 deletions(-)

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index 81052047c..e275e7943 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -85,13 +85,17 @@ void tuh_cdc_mount_cb(uint8_t idx) {
          itf_info.desc.bInterfaceNumber);
 
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-  // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
-  // otherwise you need to call tuh_cdc_set_line_coding() first
+  // If CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined, line coding will be set by tinyusb stack
+  // while eneumerating new cdc device
   cdc_line_coding_t line_coding = {0};
   if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
     printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
     printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
   }
+#else
+  // Set Line Coding upon mounted
+  cdc_line_coding_t new_line_coding = { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 };
+  tuh_cdc_set_line_coding(idx, &new_line_coding, NULL, 0);
 #endif
 }
 
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f5182efc2..cd948243d 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1510,10 +1510,11 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   uintptr_t const state = xfer->user_data;
-  cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
   uint8_t buffer[2]; // TODO remove
   TU_ASSERT (p_cdc,);
 
+  // TODO check xfer->result
+
   switch (state) {
     case CONFIG_CH34X_READ_VERSION:
       TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
@@ -1527,20 +1528,28 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
 
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      uint16_t const first_arg = tu_u16(lcr, 0x9c);
       uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
       TU_ASSERT(div_ps != 0, );
-
-      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      #else
+      uint16_t const first_arg = 0;
+      uint16_t const div_ps = 0;
+      #endif
 
       // Init CH34x with line coding
-      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, first_arg, div_ps,
                                    ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
     }
 
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
       // do special reg write, purpose unknown, overtaken from WCH driver
-      p_cdc->line_coding = line_coding;
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM);
+      #endif
       TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
 
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index 5def8d212..b9121afb3 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -27,21 +27,11 @@
 #ifndef _CH34X_H_
 #define _CH34X_H_
 
-// For simplicity, only the name CH34X is used here,
-// but specifically only CH340 and CH341 are supported.
-
-// There is no official documentation for the CH34x chips. Reference can be found
+// There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found
 // - https://github.com/WCHSoftGroup/ch341ser_linux
 // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
 // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
 
-// set line_coding @ enumeration
-#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
-#else // this default is necessary to work properly
-#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
-#endif
-
 // USB requests
 #define CH34X_REQ_READ_VERSION 0x5F // dec  95
 #define CH34X_REQ_WRITE_REG    0x9A // dec 154
-- 
cgit v1.3.1


From 769a237b19bbe5254e1c83869b463c79afb1af34 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 20 Jan 2024 20:34:50 +0100
Subject: accumulated review changes

---
 src/class/cdc/cdc_host.c     | 68 ++++++++++++++++++++------------------------
 src/class/cdc/serial/ch34x.h |  7 +++++
 2 files changed, 38 insertions(+), 37 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index cd948243d..7adaa0c8c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -401,7 +401,9 @@ bool tuh_cdc_read_clear (uint8_t idx) {
 // Control Endpoint API
 //--------------------------------------------------------------------+
 
-static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t* xfer) {
+static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) {
+  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc, );
   uint16_t const value = tu_le16toh(xfer->setup->wValue);
 
@@ -515,10 +517,7 @@ static void process_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_
 // internal control complete to update state such as line state, encoding
 static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t* p_cdc = get_itf(idx);
-
-  process_internal_control_complete(p_cdc, xfer);
+  process_internal_control_complete(xfer, itf_num);
 }
 
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
@@ -1294,7 +1293,8 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
 static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
 
-//------------- control requestt -------------//
+//------------- control request -------------//
+
 static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
                               uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request_setup = {
@@ -1366,10 +1366,7 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
 // internal control complete to update state such as line state, encoding
 static void ch34x_control_complete(tuh_xfer_t* xfer) {
   // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
-  uint8_t const itf_num = 0;
-  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t* p_cdc = get_itf(idx);
-  process_internal_control_complete(p_cdc, xfer);
+  process_internal_control_complete(xfer, 0);
 }
 
 static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
@@ -1379,6 +1376,7 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui
   p_cdc->requested_line_coding.data_bits = data_bits;
 
   uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+  TU_VERIFY(lcr != 0);
   TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
                                complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
@@ -1527,35 +1525,26 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
       TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
       // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
       TU_ASSERT (version >= 0x30,);
-
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
-      uint16_t const first_arg = tu_u16(lcr, 0x9c);
+      // init CH34x with line coding
+      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
       uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
       TU_ASSERT(div_ps != 0, );
-      #else
-      uint16_t const first_arg = 0;
-      uint16_t const div_ps = 0;
-      #endif
-
-      // Init CH34x with line coding
-      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, first_arg, div_ps,
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      TU_ASSERT(lcr != 0, );
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
                                    ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
     }
 
     case CONFIG_CH34X_SPECIAL_REG_WRITE:
-      // do special reg write, purpose unknown, overtaken from WCH driver
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM);
-      #endif
-      TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
+      // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver
+      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X);
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
       break;
 
     case CONFIG_CH34X_FLOW_CONTROL:
       // no hardware flow control
-      TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
       break;
 
     case CONFIG_CH34X_MODEM_CONTROL:
@@ -1581,6 +1570,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   uint8_t b;
   uint32_t c;
 
+  TU_VERIFY(baval != 0, 0);
   switch (baval) {
     case 921600:
       a = 0xf3;
@@ -1606,7 +1596,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
         b = 0;
         c = 11719;
       }
-      a = (unsigned char) (c / baval);
+      a = (uint8_t) (c / baval);
       if (a == 0 || a == 0xFF) {
         return 0;
       }
@@ -1620,29 +1610,33 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   // reg divisor = a, reg prescaler = b
   // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
   // otherwise the chip will buffer data.
-  return (uint16_t) (a << 8 | 0x80 | b);
+  return (uint16_t) ((uint16_t)a << 8 | 0x80 | b);
 }
 
 // calculate lcr value from data coding
 static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
   uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
-  TU_VERIFY(data_bits >= 5, 0);
+  TU_VERIFY(data_bits >= 5 && data_bits <= 8, 0);
   lcr |= (uint8_t) (data_bits - 5);
 
-  if (parity) {
-    lcr |= CH34X_LCR_ENABLE_PAR;
-  }
   switch(parity) {
+    case CDC_LINE_CODING_PARITY_NONE:
+      break;
+
+    case CDC_LINE_CODING_PARITY_ODD:
+    lcr |= CH34X_LCR_ENABLE_PAR;
+      break;
+
     case CDC_LINE_CODING_PARITY_EVEN:
-      lcr |= CH34X_LCR_PAR_EVEN;
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN;
       break;
 
     case CDC_LINE_CODING_PARITY_MARK:
-      lcr |= CH34X_LCR_MARK_SPACE;
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE;
       break;
 
     case CDC_LINE_CODING_PARITY_SPACE:
-      lcr |= CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
       break;
 
     default: break;
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
index b9121afb3..c18066f57 100644
--- a/src/class/cdc/serial/ch34x.h
+++ b/src/class/cdc/serial/ch34x.h
@@ -32,6 +32,13 @@
 // - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
 // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
 
+// set line_coding @ enumeration
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#else // this default is necessary to work properly
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#endif
+
 // USB requests
 #define CH34X_REQ_READ_VERSION 0x5F // dec  95
 #define CH34X_REQ_WRITE_REG    0x9A // dec 154
-- 
cgit v1.3.1


From af3c6be79fe9a9829f30831bd7525d2a22cb5529 Mon Sep 17 00:00:00 2001
From: Jonathan Zentgraf <jonathan@zentgraf.dev>
Date: Sat, 20 Jan 2024 20:16:54 -0500
Subject: msc_device: Fix check for including MSC lookup tables

The _msc_scsi_cmd_lookup and _msc_scsi_cmd_table variables are needed
when logging is enabled for the MSC device via CFG_TUD_MSC_LOG_LEVEL.
Update the preprocessor check around them to use that definition when
deciding whether to define those variables.

Closes #2419
---
 src/class/msc/msc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 2589dcd2c..c145d86a6 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -203,7 +203,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL
 
 TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
 {
-- 
cgit v1.3.1


From 1c9a839401cb7323f93202f600c6f3148100e10a Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Tue, 23 Jan 2024 13:48:09 +0100
Subject: audio_device: Fix unused variable warning

In some configurations local variable p_desc_parse_for_params
is declared and never used resulting in warning that can
be escalated to build error (for mynewt)

Now variable is surrounded with same preprocessor condition
as function that uses it audiod_parse_for_AS_params()
---
 src/class/audio/audio_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index d438d0715..4adc558a6 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1729,7 +1729,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     // Find correct interface
     if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt)
     {
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
       uint8_t const * p_desc_parse_for_params = p_desc;
 #endif
       // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary
-- 
cgit v1.3.1


From 0b8b8af83dfac97caa7c41f9d5c8c1a3af1b9ac1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 Jan 2024 17:25:48 +0700
Subject: minor update to video capture example

---
 examples/device/video_capture/src/main.c           |  15 +-
 examples/device/video_capture/src/tusb_config.h    |   2 +-
 .../device/video_capture/src/usb_descriptors.h     |  69 +++------
 src/class/video/video_device.c                     |   6 +-
 src/common/tusb_types.h                            | 154 ++++++++-------------
 5 files changed, 92 insertions(+), 154 deletions(-)

(limited to 'src')

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 7b180dd6b..e63335e67 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -131,8 +131,7 @@ static struct {
 static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8];
 
 static void fill_color_bar(uint8_t* buffer, unsigned start_position) {
-  /* EBU color bars
-   * See also https://stackoverflow.com/questions/6939422 */
+  /* EBU color bars: https://stackoverflow.com/questions/6939422 */
   static uint8_t const bar_color[8][4] = {
       /*  Y,   U,   Y,   V */
       { 235, 128, 235, 128}, /* 100% White */
@@ -184,12 +183,12 @@ void video_task(void) {
     already_sent = 1;
     start_ms = board_millis();
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+    #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
     tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                            FRAME_WIDTH * FRAME_HEIGHT * 16/8);
-# else
+    #else
     tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
-# endif
+    #endif
 #else
     fill_color_bar(frame_buffer, frame_num);
     tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8);
@@ -202,12 +201,12 @@ void video_task(void) {
   start_ms += interval_ms;
 
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+  #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
   tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                          FRAME_WIDTH * FRAME_HEIGHT * 16/8);
-# else
+  #else
   tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
-# endif
+  #endif
 #else
   fill_color_bar(frame_buffer, frame_num);
   tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8);
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 8440b47ef..d563c6f5c 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -97,7 +97,7 @@
 // The number of video streaming interfaces
 #define CFG_TUD_VIDEO_STREAMING  1
 
-// video streaming endpoint size
+// video streaming endpoint buffer size
 #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
 
 // use bulk endpoint for streaming interface
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index b924c8dbe..fa3c1fbd2 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -126,23 +126,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                  \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -163,23 +157,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -202,22 +190,17 @@ enum {
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
   TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
         /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -235,23 +218,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                     \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 3b29454a3..c16a45fcd 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -434,8 +434,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   uint_fast32_t interval_ms = interval / 10000;
   TU_ASSERT(interval_ms);
   uint_fast32_t payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
-  if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+  if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) {
     payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
+  }
   param->dwMaxPayloadTransferSize = payload_size;
   return true;
 }
@@ -577,8 +578,9 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       } else {
         payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
       }
-      if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+      if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) {
         payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
+      }
       param->dwMaxPayloadTransferSize = payload_size;
     }
     return true;
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index fab680989..d4ef1fd09 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -44,43 +44,38 @@
  *------------------------------------------------------------------*/
 
 /// defined base on EHCI specs value for Endpoint Speed
-typedef enum
-{
+typedef enum {
   TUSB_SPEED_FULL = 0,
   TUSB_SPEED_LOW  = 1,
   TUSB_SPEED_HIGH = 2,
   TUSB_SPEED_INVALID = 0xff,
-}tusb_speed_t;
+} tusb_speed_t;
 
 /// defined base on USB Specs Endpoint's bmAttributes
-typedef enum
-{
+typedef enum {
   TUSB_XFER_CONTROL = 0 ,
   TUSB_XFER_ISOCHRONOUS ,
   TUSB_XFER_BULK        ,
   TUSB_XFER_INTERRUPT
-}tusb_xfer_type_t;
+} tusb_xfer_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_DIR_OUT = 0,
   TUSB_DIR_IN  = 1,
 
   TUSB_DIR_IN_MASK = 0x80
-}tusb_dir_t;
+} tusb_dir_t;
 
-enum
-{
+enum {
   TUSB_EPSIZE_BULK_FS = 64,
-  TUSB_EPSIZE_BULK_HS= 512,
+  TUSB_EPSIZE_BULK_HS = 512,
 
   TUSB_EPSIZE_ISO_FS_MAX = 1023,
   TUSB_EPSIZE_ISO_HS_MAX = 1024,
 };
 
-/// Isochronous End Point Attributes
-typedef enum
-{
+/// Isochronous Endpoint Attributes
+typedef enum {
   TUSB_ISO_EP_ATT_NO_SYNC         = 0x00,
   TUSB_ISO_EP_ATT_ASYNCHRONOUS    = 0x04,
   TUSB_ISO_EP_ATT_ADAPTIVE        = 0x08,
@@ -88,11 +83,10 @@ typedef enum
   TUSB_ISO_EP_ATT_DATA            = 0x00, ///< Data End Point
   TUSB_ISO_EP_ATT_EXPLICIT_FB     = 0x10, ///< Feedback End Point
   TUSB_ISO_EP_ATT_IMPLICIT_FB     = 0x20, ///< Data endpoint that also serves as an implicit feedback
-}tusb_iso_ep_attribute_t;
+} tusb_iso_ep_attribute_t;
 
 /// USB Descriptor Types
-typedef enum
-{
+typedef enum {
   TUSB_DESC_DEVICE                = 0x01,
   TUSB_DESC_CONFIGURATION         = 0x02,
   TUSB_DESC_STRING                = 0x03,
@@ -119,10 +113,9 @@ typedef enum
 
   TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION     = 0x30,
   TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31
-}tusb_desc_type_t;
+} tusb_desc_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_GET_STATUS        = 0  ,
   TUSB_REQ_CLEAR_FEATURE     = 1  ,
   TUSB_REQ_RESERVED          = 2  ,
@@ -136,25 +129,22 @@ typedef enum
   TUSB_REQ_GET_INTERFACE     = 10 ,
   TUSB_REQ_SET_INTERFACE     = 11 ,
   TUSB_REQ_SYNCH_FRAME       = 12
-}tusb_request_code_t;
+} tusb_request_code_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_FEATURE_EDPT_HALT     = 0,
   TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1,
   TUSB_REQ_FEATURE_TEST_MODE     = 2
-}tusb_request_feature_selector_t;
+} tusb_request_feature_selector_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_TYPE_STANDARD = 0,
   TUSB_REQ_TYPE_CLASS,
   TUSB_REQ_TYPE_VENDOR,
   TUSB_REQ_TYPE_INVALID
 } tusb_request_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_RCPT_DEVICE =0,
   TUSB_REQ_RCPT_INTERFACE,
   TUSB_REQ_RCPT_ENDPOINT,
@@ -162,8 +152,7 @@ typedef enum
 } tusb_request_recipient_t;
 
 // https://www.usb.org/defined-class-codes
-typedef enum
-{
+typedef enum {
   TUSB_CLASS_UNSPECIFIED          = 0    ,
   TUSB_CLASS_AUDIO                = 1    ,
   TUSB_CLASS_CDC                  = 2    ,
@@ -187,26 +176,23 @@ typedef enum
   TUSB_CLASS_MISC                 = 0xEF ,
   TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE ,
   TUSB_CLASS_VENDOR_SPECIFIC      = 0xFF
-}tusb_class_code_t;
+} tusb_class_code_t;
 
 typedef enum
 {
   MISC_SUBCLASS_COMMON = 2
 }misc_subclass_type_t;
 
-typedef enum
-{
+typedef enum {
   MISC_PROTOCOL_IAD = 1
-}misc_protocol_type_t;
+} misc_protocol_type_t;
 
-typedef enum
-{
+typedef enum {
   APP_SUBCLASS_USBTMC = 0x03,
   APP_SUBCLASS_DFU_RUNTIME = 0x01
 } app_subclass_type_t;
 
-typedef enum
-{
+typedef enum {
   DEVICE_CAPABILITY_WIRELESS_USB               = 0x01,
   DEVICE_CAPABILITY_USB20_EXTENSION            = 0x02,
   DEVICE_CAPABILITY_SUPERSPEED_USB             = 0x03,
@@ -223,7 +209,7 @@ typedef enum
   DEVICE_CAPABILITY_AUTHENTICATION             = 0x0E,
   DEVICE_CAPABILITY_BILLBOARD_EX               = 0x0F,
   DEVICE_CAPABILITY_CONFIGURATION_SUMMARY      = 0x10
-}device_capability_type_t;
+} device_capability_type_t;
 
 enum {
   TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5),
@@ -235,28 +221,25 @@ enum {
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
-typedef enum
-{
+typedef enum {
   XFER_RESULT_SUCCESS = 0,
   XFER_RESULT_FAILED,
   XFER_RESULT_STALLED,
   XFER_RESULT_TIMEOUT,
   XFER_RESULT_INVALID
-}xfer_result_t;
+} xfer_result_t;
 
-enum // TODO remove
-{
+// TODO remove
+enum {
   DESC_OFFSET_LEN  = 0,
   DESC_OFFSET_TYPE = 1
 };
 
-enum
-{
+enum {
   INTERFACE_INVALID_NUMBER = 0xff
 };
 
-typedef enum
-{
+typedef enum {
   MS_OS_20_SET_HEADER_DESCRIPTOR       = 0x00,
   MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01,
   MS_OS_20_SUBSET_HEADER_FUNCTION      = 0x02,
@@ -268,16 +251,14 @@ typedef enum
   MS_OS_20_FEATURE_VENDOR_REVISION     = 0x08
 } microsoft_os_20_type_t;
 
-enum
-{
+enum {
   CONTROL_STAGE_IDLE,
   CONTROL_STAGE_SETUP,
   CONTROL_STAGE_DATA,
   CONTROL_STAGE_ACK
 };
 
-enum
-{
+enum {
   TUSB_INDEX_INVALID_8 = 0xFFu
 };
 
@@ -290,8 +271,7 @@ TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
 /// USB Device Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes.
   uint8_t  bDescriptorType    ; ///< DEVICE Descriptor Type.
   uint16_t bcdUSB             ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant.
@@ -314,8 +294,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct");
 
 // USB Binary Device Object Store (BOS) Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< CONFIGURATION Descriptor Type
   uint16_t wTotalLength    ; ///< Total length of data returned for this descriptor
@@ -325,8 +304,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_bos_t) == 5, "size is not correct");
 
 /// USB Configuration Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength             ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType     ; ///< CONFIGURATION Descriptor Type
   uint16_t wTotalLength        ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration.
@@ -341,8 +319,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_configuration_t) == 9, "size is not correct");
 
 /// USB Interface Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType    ; ///< INTERFACE Descriptor Type
 
@@ -358,8 +335,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct");
 
 /// USB Endpoint Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength          ; // Size of this descriptor in bytes
   uint8_t  bDescriptorType  ; // ENDPOINT Descriptor Type
 
@@ -379,8 +355,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_endpoint_t) == 7, "size is not correct");
 
 /// USB Other Speed Configuration Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength             ; ///< Size of descriptor
   uint8_t  bDescriptorType     ; ///< Other_speed_Configuration Type
   uint16_t wTotalLength        ; ///< Total length of data returned
@@ -393,8 +368,7 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_other_speed_t;
 
 /// USB Device Qualifier Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of descriptor
   uint8_t  bDescriptorType    ; ///< Device Qualifier Type
   uint16_t bcdUSB             ; ///< USB specification version number (e.g., 0200H for V2.00)
@@ -411,8 +385,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct");
 
 /// USB Interface Association Descriptor (IAD ECN)
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength           ; ///< Size of descriptor
   uint8_t bDescriptorType   ; ///< Other_speed_Configuration Type
 
@@ -427,16 +400,14 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_interface_assoc_t;
 
 // USB String Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< Descriptor Type
   uint16_t unicode_string[];
 } tusb_desc_string_t;
 
 // USB Binary Device Object Store (BOS)
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType ;
   uint8_t bDevCapabilityType;
@@ -445,9 +416,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t CapabilityData[];
 } tusb_desc_bos_platform_t;
 
-// USB WebuSB URL Descriptor
-typedef struct TU_ATTR_PACKED
-{
+// USB WebUSB URL Descriptor
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bScheme;
@@ -455,8 +425,7 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_webusb_url_t;
 
 // DFU Functional Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
 
@@ -481,7 +450,7 @@ typedef struct TU_ATTR_PACKED
 //
 //--------------------------------------------------------------------+
 
-typedef struct TU_ATTR_PACKED{
+typedef struct TU_ATTR_PACKED {
   union {
     struct TU_ATTR_PACKED {
       uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
@@ -509,36 +478,30 @@ TU_ATTR_BIT_FIELD_ORDER_END
 //--------------------------------------------------------------------+
 
 // Get direction from Endpoint address
-TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr) {
   return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
 }
 
 // Get Endpoint number from address
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr) {
   return (uint8_t)(addr & (~TUSB_DIR_IN_MASK));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) {
   return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) {
   return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
 }
 
 #if CFG_TUSB_DEBUG
-TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) {
   tu_static const char *str[] = {"out", "in"};
   return str[dir];
 }
 
-TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
-{
+TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) {
   tu_static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
 }
@@ -549,21 +512,18 @@ TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_
 //--------------------------------------------------------------------+
 
 // return next descriptor
-TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) {
   uint8_t const* desc8 = (uint8_t const*) desc;
   return desc8 + desc8[DESC_OFFSET_LEN];
 }
 
 // get descriptor type
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) {
   return ((uint8_t const*) desc)[DESC_OFFSET_TYPE];
 }
 
 // get descriptor length
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) {
   return ((uint8_t const*) desc)[DESC_OFFSET_LEN];
 }
 
-- 
cgit v1.3.1


From a7de4ac9b7a2dfb1fa44921fb0f41f249c8cdd5e Mon Sep 17 00:00:00 2001
From: YixingShen <kkman3651878@hotmail.com>
Date: Fri, 26 Jan 2024 02:37:15 +0800
Subject: Correct VIDEO_CS_VS_INTERFACE_FRAME_MJPEG to
 VIDEO_CS_ITF_VS_FRAME_MJPEG for #define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC

---
 src/class/video/video.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/video/video.h b/src/class/video/video.h
index d9880c291..268e219e2 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -537,7 +537,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 /* Motion-JPEG 3.1.1 Table 3-2 and 3-4 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \
   TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
-  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_MJPEG, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_MJPEG, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
-- 
cgit v1.3.1


From b5cd673330fc87f2981ecf139b24940df5cb3cfe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 Jan 2024 22:55:55 +0700
Subject: rename and add more video descriptors

use struct to define uvc descriptor for video_capture since uvc is
rather too complicated to use macro templates
---
 .../device/video_capture/src/usb_descriptors.c     | 233 +++++++++++++++++++--
 .../device/video_capture/src/usb_descriptors.h     |   4 +-
 src/class/video/video.h                            | 224 ++++++++++++++------
 src/class/video/video_device.c                     |  20 +-
 src/common/tusb_types.h                            |   3 +-
 5 files changed, 389 insertions(+), 95 deletions(-)

(limited to 'src')

diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index d38f158c8..8e54d3afd 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -40,6 +40,26 @@
 #define USB_VID   0xCafe
 #define USB_BCD   0x0200
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+  STRID_UVC_CONTROL,
+  STRID_UVC_STREAMING,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr[] = {
+    (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                     // 1: Manufacturer
+    "TinyUSB Device",              // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "TinyUSB UVC Control",         // 4: UVC Interface
+    "TinyUSB UVC Streaming",       // 5: UVC Interface
+};
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
@@ -60,9 +80,9 @@ tusb_desc_device_t const desc_device = {
     .idProduct          = USB_PID,
     .bcdDevice          = 0x0100,
 
-    .iManufacturer      = 0x01,
-    .iProduct           = 0x02,
-    .iSerialNumber      = 0x03,
+    .iManufacturer      = STRID_MANUFACTURER,
+    .iProduct           = STRID_PRODUCT,
+    .iSerialNumber      = STRID_SERIAL,
 
     .bNumConfigurations = 0x01
 };
@@ -164,6 +184,193 @@ uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
 }
 #endif // highspeed
 
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_control_header_1itf_t header;
+  tusb_desc_video_control_camera_terminal_t camera_terminal;
+  tusb_desc_video_control_output_terminal_t output_terminal;
+} uvc_control_desc_t;
+
+/* Windows support YUY2 and NV12
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_streaming_input_header_1byte_t header;
+  tusb_desc_video_format_uncompressed_t format;
+  tusb_desc_video_frame_uncompressed_continuous_t frame;
+  tusb_desc_video_streaming_color_matching_t color;
+  tusb_desc_endpoint_t ep;
+} uvc_streaming_desc_t;
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_configuration_t config;
+  tusb_desc_interface_assoc_t iad;
+  uvc_control_desc_t video_control;
+  uvc_streaming_desc_t video_streaming;
+} uvc_cfg_desc_t;
+
+const uvc_cfg_desc_t config_desc = {
+    .config = {
+        .bLength = sizeof(tusb_desc_configuration_t),
+        .bDescriptorType = TUSB_DESC_CONFIGURATION,
+
+        .wTotalLength = sizeof(uvc_cfg_desc_t),
+        .bNumInterfaces = ITF_NUM_TOTAL,
+        .bConfigurationValue = 1,
+        .iConfiguration = 0,
+        .bmAttributes = TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP,
+        .bMaxPower = 100 / 2
+    },
+    .iad = {
+        .bLength = sizeof(tusb_desc_interface_assoc_t),
+        .bDescriptorType = TUSB_DESC_INTERFACE_ASSOCIATION,
+
+        .bFirstInterface = ITF_NUM_VIDEO_CONTROL,
+        .bInterfaceCount = 2,
+        .bFunctionClass = TUSB_CLASS_VIDEO,
+        .bFunctionSubClass = VIDEO_SUBCLASS_INTERFACE_COLLECTION,
+        .bFunctionProtocol = VIDEO_ITF_PROTOCOL_UNDEFINED,
+        .iFunction = 0
+    },
+
+    .video_control = {
+        .itf = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_CONTROL,
+            .bAlternateSetting = 0,
+            .bNumEndpoints = 0,
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_CONTROL,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_CONTROL
+        },
+        .header = {
+            .bLength = sizeof(tusb_desc_video_control_header_1itf_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_HEADER,
+
+            .bcdUVC = VIDEO_BCD_1_50,
+            .wTotalLength = sizeof(uvc_control_desc_t) - sizeof(tusb_desc_interface_t), // CS VC descriptors only
+            .dwClockFrequency = UVC_CLOCK_FREQUENCY,
+            .bInCollection = 1,
+            .baInterfaceNr = { ITF_NUM_VIDEO_STREAMING }
+        },
+        .camera_terminal = {
+            .bLength = sizeof(tusb_desc_video_control_camera_terminal_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_INPUT_TERMINAL,
+
+            .bTerminalID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+            .wTerminalType = VIDEO_ITT_CAMERA,
+            .bAssocTerminal = 0,
+            .iTerminal = 0,
+            .wObjectiveFocalLengthMin = 0,
+            .wObjectiveFocalLengthMax = 0,
+            .wOcularFocalLength = 0,
+            .bControlSize = 3,
+            .bmControls = { 0, 0, 0 }
+        },
+        .output_terminal = {
+            .bLength = sizeof(tusb_desc_video_control_output_terminal_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_OUTPUT_TERMINAL,
+
+            .bTerminalID = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+            .wTerminalType = VIDEO_TT_STREAMING,
+            .bAssocTerminal = 0,
+            .bSourceID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+            .iTerminal = 0
+        }
+    },
+
+    .video_streaming = {
+        .itf = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING,
+            .bAlternateSetting = 0,
+            .bNumEndpoints = 1,
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_STREAMING
+        },
+        .header = {
+            .bLength = sizeof(tusb_desc_video_streaming_input_header_1byte_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_INPUT_HEADER,
+
+            .bNumFormats = 1,
+            .wTotalLength = sizeof(uvc_streaming_desc_t) - sizeof(tusb_desc_interface_t) - sizeof(tusb_desc_endpoint_t), // CS VS descriptors only
+            .bEndpointAddress = EPNUM_VIDEO_IN,
+            .bmInfo = 0,
+            .bTerminalLink = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+            .bStillCaptureMethod = 0,
+            .bTriggerSupport = 0,
+            .bTriggerUsage = 0,
+            .bControlSize = 1,
+            .bmaControls = { 0 }
+        },
+        .format = {
+            .bLength = sizeof(tusb_desc_video_format_uncompressed_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED,
+
+            .bFormatIndex = 1, // 1-based index
+            .bNumFrameDescriptors = 1,
+            .guidFormat = { TUD_VIDEO_GUID_YUY2 },
+            .bBitsPerPixel = 16,
+            .bDefaultFrameIndex = 1,
+            .bAspectRatioX = 0,
+            .bAspectRatioY = 0,
+            .bmInterlaceFlags = 0,
+            .bCopyProtect = 0
+        },
+        .frame = {
+            .bLength = sizeof(tusb_desc_video_frame_uncompressed_continuous_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED,
+
+            .bFrameIndex = 1, // 1-based index
+            .bmCapabilities = 0,
+            .wWidth = FRAME_WIDTH,
+            .wHeight = FRAME_HEIGHT,
+            .dwMinBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * 1,
+            .dwMaxBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * FRAME_RATE,
+            .dwMaxVideoFrameBufferSize = FRAME_WIDTH * FRAME_HEIGHT * 16 / 8,
+            .dwDefaultFrameInterval = 10000000 / FRAME_RATE,
+            .bFrameIntervalType = 0, // continuous
+            .dwFrameInterval = {
+                10000000 / FRAME_RATE, // min
+                10000000, // max
+                10000000 / FRAME_RATE // step
+            }
+        },
+        .color = {
+            .bLength = sizeof(tusb_desc_video_streaming_color_matching_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_COLORFORMAT,
+
+            .bColorPrimaries = VIDEO_COLOR_PRIMARIES_BT709,
+            .bTransferCharacteristics = VIDEO_COLOR_XFER_CH_BT709,
+            .bMatrixCoefficients = VIDEO_COLOR_COEF_SMPTE170M
+        },
+        .ep = {
+            .bLength = sizeof(tusb_desc_endpoint_t),
+            .bDescriptorType = TUSB_DESC_ENDPOINT,
+
+            .bEndpointAddress = EPNUM_VIDEO_IN,
+            .bmAttributes = { .xfer = TUSB_XFER_BULK },
+            .wMaxPacketSize = CFG_TUD_VIDEO_STREAMING_BULK ? 64 : CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE,
+            .bInterval = 1
+        }
+    }
+};
+
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
@@ -174,7 +381,8 @@ uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
   // Although we are highspeed, host may be fullspeed.
   return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
 #else
-  return desc_fs_configuration;
+//  return desc_fs_configuration;
+  return (uint8_t const*) &config_desc;
 #endif
 }
 
@@ -182,23 +390,6 @@ uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
 // String Descriptors
 //--------------------------------------------------------------------+
 
-// String Descriptor Index
-enum {
-  STRID_LANGID = 0,
-  STRID_MANUFACTURER,
-  STRID_PRODUCT,
-  STRID_SERIAL,
-};
-
-// array of pointer to string descriptors
-char const* string_desc_arr[] = {
-    (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
-    "TinyUSB",                     // 1: Manufacturer
-    "TinyUSB Device",              // 2: Product
-    NULL,                          // 3: Serials will use unique ID if possible
-    "TinyUSB UVC",                 // 4: UVC Interface
-};
-
 static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index fa3c1fbd2..fd908c9c2 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -210,7 +210,7 @@ enum {
         /* Video stream frame format */ \
         TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
-            _width * _height * 16, \
+            _width * _height * 16 / 8, \
             (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
         TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
@@ -223,7 +223,7 @@ enum {
     TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
       /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
       TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
-      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, UVC_ENTITY_CAP_INPUT_TERMINAL, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
     /* Video stream header for without still image capture */ \
diff --git a/src/class/video/video.h b/src/class/video/video.h
index d9880c291..162d4e4c4 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -29,6 +29,10 @@
 
 #include "common/tusb_common.h"
 
+enum {
+  VIDEO_BCD_1_50 = 0x0150,
+};
+
 // Table 3-19 Color Matching Descriptor
 typedef enum {
   VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00,
@@ -198,55 +202,98 @@ typedef enum {
 } video_terminal_type_t;
 
 //--------------------------------------------------------------------+
-// Descriptors
+// Video Control (VC) Descriptors
 //--------------------------------------------------------------------+
 
 /* 2.3.4.2 */
+#define tusb_desc_video_control_header_nitf_t(_nitf) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint16_t bcdUVC; \
+    uint16_t wTotalLength; \
+    uint32_t dwClockFrequency; /* deprecated */ \
+    uint8_t  bInCollection; \
+    uint8_t  baInterfaceNr[_nitf]; \
+  }
+
+typedef tusb_desc_video_control_header_nitf_t()  tusb_desc_video_control_header_t;
+typedef tusb_desc_video_control_header_nitf_t(1) tusb_desc_video_control_header_1itf_t;
+typedef tusb_desc_video_control_header_nitf_t(2) tusb_desc_video_control_header_2itf_t;
+typedef tusb_desc_video_control_header_nitf_t(3) tusb_desc_video_control_header_3itf_t;
+typedef tusb_desc_video_control_header_nitf_t(4) tusb_desc_video_control_header_4itf_t;
+
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
   uint8_t  bDescriptorSubType;
-  uint16_t bcdUVC;
-  uint16_t wTotalLength;
-  uint32_t dwClockFrequency;
-  uint8_t  bInCollection;
-  uint8_t  baInterfaceNr[];
-} tusb_desc_cs_video_ctl_itf_hdr_t;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  iTerminal;
+} tusb_desc_video_control_input_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_input_terminal_t) == 8, "size is not correct");
 
-/* 2.4.3.3 */
 typedef struct TU_ATTR_PACKED {
-  uint8_t bHeaderLength;
-  union {
-    uint8_t bmHeaderInfo;
-    struct {
-      uint8_t FrameID:              1;
-      uint8_t EndOfFrame:           1;
-      uint8_t PresentationTime:     1;
-      uint8_t SourceClockReference: 1;
-      uint8_t PayloadSpecific:      1;
-      uint8_t StillImage:           1;
-      uint8_t Error:                1;
-      uint8_t EndOfHeader:          1;
-    };
-  };
-} tusb_video_payload_header_t;
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  bSourceID;
+  uint8_t  iTerminal;
+} tusb_desc_video_control_output_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_output_terminal_t) == 9, "size is not correct");
 
-/* 3.9.2.1 */
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
   uint8_t  bDescriptorSubType;
-  uint8_t  bNumFormats;
-  uint16_t wTotalLength;
-  uint8_t  bEndpointAddress;
-  uint8_t  bmInfo;
-  uint8_t  bTerminalLink;
-  uint8_t  bStillCaptureMethod;
-  uint8_t  bTriggerSupport;
-  uint8_t  bTriggerUsage;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  iTerminal;
+
+  uint16_t wObjectiveFocalLengthMin;
+  uint16_t wObjectiveFocalLengthMax;
+  uint16_t wOcularFocalLength;
   uint8_t  bControlSize;
-  uint8_t  bmaControls[];
-} tusb_desc_cs_video_stm_itf_in_hdr_t;
+  uint8_t  bmControls[3];
+} tusb_desc_video_control_camera_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_camera_terminal_t) == 18, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Video Streaming (VS) Descriptors
+//--------------------------------------------------------------------+
+
+/* 3.9.2.1 */
+#define tusb_desc_video_streaming_input_header_nbyte_t(_nb) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint8_t  bNumFormats; /* Number of video payload Format descriptors for this interface */ \
+    uint16_t wTotalLength; \
+    uint8_t  bEndpointAddress; \
+    uint8_t  bmInfo; /* Bit 0: dynamic format change supported */ \
+    uint8_t  bTerminalLink; \
+    uint8_t  bStillCaptureMethod; \
+    uint8_t  bTriggerSupport; /* Hardware trigger supported */ \
+    uint8_t  bTriggerUsage; \
+    uint8_t  bControlSize; /* sizeof of each control item */ \
+    uint8_t  bmaControls[_nb]; \
+  }
+
+typedef tusb_desc_video_streaming_input_header_nbyte_t() tusb_desc_video_streaming_input_header_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(1) tusb_desc_video_streaming_input_header_1byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(2) tusb_desc_video_streaming_input_header_2byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(3) tusb_desc_video_streaming_input_header_3byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(4) tusb_desc_video_streaming_input_header_4byte_t;
 
 /* 3.9.2.2 */
 typedef struct TU_ATTR_PACKED {
@@ -259,7 +306,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bTerminalLink;
   uint8_t  bControlSize;
   uint8_t  bmaControls[];
-} tusb_desc_cs_video_stm_itf_out_hdr_t;
+} tusb_desc_video_streaming_output_header_t;
 
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -285,14 +332,33 @@ typedef struct TU_ATTR_PACKED {
       uint8_t  bmaControls[];
     } output;
   };
-} tusb_desc_cs_video_stm_itf_hdr_t;
+} tusb_desc_video_streaming_inout_header_t;
 
+// 3.9.2.6 Color Matching Descriptor
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bColorPrimaries;
+  uint8_t  bTransferCharacteristics;
+  uint8_t  bMatrixCoefficients;
+} tusb_desc_video_streaming_color_matching_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_streaming_color_matching_t) == 6, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Format and Frame Descriptor
+// Note: bFormatIndex & bFrameIndex are 1-based index
+//--------------------------------------------------------------------+
+
+//------------- Uncompressed -------------//
+// Uncompressed payload specs: 3.1.1 format descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bDescriptorSubType;
   uint8_t bFormatIndex;
-  uint8_t bNumFrameDescriptors;
+  uint8_t bNumFrameDescriptors; // Number of frame descriptors for this format
   uint8_t guidFormat[16];
   uint8_t bBitsPerPixel;
   uint8_t bDefaultFrameIndex;
@@ -300,8 +366,39 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bAspectRatioY;
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
-} tusb_desc_cs_video_fmt_uncompressed_t;
-
+} tusb_desc_video_format_uncompressed_t;
+
+// Uncompressed payload specs: 3.1.2 frame descriptor
+#define tusb_desc_video_frame_uncompressed_nint_t(_nint) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint8_t  bFrameIndex; \
+    uint8_t  bmCapabilities; \
+    uint16_t wWidth; \
+    uint16_t wHeight; \
+    uint32_t dwMinBitRate; \
+    uint32_t dwMaxBitRate; \
+    uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \
+    uint32_t dwDefaultFrameInterval; \
+    uint8_t  bFrameIntervalType; \
+    uint32_t dwFrameInterval[_nint]; \
+  }
+
+typedef tusb_desc_video_frame_uncompressed_nint_t() tusb_desc_video_frame_uncompressed_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(1) tusb_desc_video_frame_uncompressed_1int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(2) tusb_desc_video_frame_uncompressed_2int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(3) tusb_desc_video_frame_uncompressed_3int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(4) tusb_desc_video_frame_uncompressed_4int_t;
+
+// continuous = 3 intervals: min, max, step
+typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_uncompressed_continuous_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_frame_uncompressed_continuous_t) == 38, "size is not correct");
+
+//------------- MJPEG -------------//
+// MJPEG payload specs: 3.1.1 formatt descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
@@ -314,8 +411,12 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bAspectRatioY;
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
-} tusb_desc_cs_video_fmt_mjpeg_t;
+} tusb_desc_video_format_mjpeg_t;
 
+// MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
+typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
+
+// DV payload specs: 3.1.1
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
@@ -323,8 +424,9 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bFormatIndex;
   uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
   uint8_t  bFormatType;
-} tusb_desc_cs_video_fmt_dv_t;
+} tusb_desc_video_format_dv_t;
 
+// Frame Based payload specs: 3.1.1
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
@@ -339,25 +441,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
   uint8_t bVaribaleSize;
-} tusb_desc_cs_video_fmt_frame_based_t;
-
-typedef struct TU_ATTR_PACKED {
-  uint8_t  bLength;
-  uint8_t  bDescriptorType;
-  uint8_t  bDescriptorSubType;
-  uint8_t  bFrameIndex;
-  uint8_t  bmCapabilities;
-  uint16_t wWidth;
-  uint16_t wHeight;
-  uint32_t dwMinBitRate;
-  uint32_t dwMaxBitRate;
-  uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
-  uint32_t dwDefaultFrameInterval;
-  uint8_t  bFrameIntervalType;
-  uint32_t dwFrameInterval[];
-} tusb_desc_cs_video_frm_uncompressed_t;
-
-typedef tusb_desc_cs_video_frm_uncompressed_t tusb_desc_cs_video_frm_mjpeg_t;
+} tusb_desc_video_format_framebased_t;
 
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -373,12 +457,30 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bFrameIntervalType;
   uint32_t dwBytesPerLine;
   uint32_t dwFrameInterval[];
-} tusb_desc_cs_video_frm_frame_based_t;
+} tusb_desc_video_frame_framebased_t;
 
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
 
+/* 2.4.3.3 */
+typedef struct TU_ATTR_PACKED {
+  uint8_t bHeaderLength;
+  union {
+    uint8_t bmHeaderInfo;
+    struct {
+      uint8_t FrameID:              1;
+      uint8_t EndOfFrame:           1;
+      uint8_t PresentationTime:     1;
+      uint8_t SourceClockReference: 1;
+      uint8_t PayloadSpecific:      1;
+      uint8_t StillImage:           1;
+      uint8_t Error:                1;
+      uint8_t EndOfHeader:          1;
+    };
+  };
+} tusb_video_payload_header_t;
+
 /* 4.3.1.1 */
 typedef struct TU_ATTR_PACKED {
   union {
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index c16a45fcd..1affd615e 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -50,17 +50,17 @@
 
 typedef struct {
   tusb_desc_interface_t            std;
-  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
+  tusb_desc_video_control_header_t ctl;
 } tusb_desc_vc_itf_t;
 
 typedef struct {
   tusb_desc_interface_t            std;
-  tusb_desc_cs_video_stm_itf_hdr_t stm;
+  tusb_desc_video_streaming_inout_header_t stm;
 } tusb_desc_vs_itf_t;
 
 typedef union {
-  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
-  tusb_desc_cs_video_stm_itf_hdr_t stm;
+  tusb_desc_video_control_header_t ctl;
+  tusb_desc_video_streaming_inout_header_t stm;
 } tusb_desc_video_itf_hdr_t;
 
 typedef struct TU_ATTR_PACKED {
@@ -78,9 +78,9 @@ typedef union {
     uint8_t bFormatIndex;
     uint8_t bNumFrameDescriptors;
   };
-  tusb_desc_cs_video_fmt_uncompressed_t uncompressed;
-  tusb_desc_cs_video_fmt_mjpeg_t        mjpeg;
-  tusb_desc_cs_video_fmt_frame_based_t  frame_based;
+  tusb_desc_video_format_uncompressed_t uncompressed;
+  tusb_desc_video_format_mjpeg_t        mjpeg;
+  tusb_desc_video_format_framebased_t  frame_based;
 } tusb_desc_cs_video_fmt_t;
 
 typedef union {
@@ -93,9 +93,9 @@ typedef union {
     uint16_t wWidth;
     uint16_t wHeight;
   };
-  tusb_desc_cs_video_frm_uncompressed_t uncompressed;
-  tusb_desc_cs_video_frm_mjpeg_t        mjpeg;
-  tusb_desc_cs_video_frm_frame_based_t  frame_based;
+  tusb_desc_video_frame_uncompressed_t uncompressed;
+  tusb_desc_video_frame_mjpeg_t        mjpeg;
+  tusb_desc_video_frame_framebased_t  frame_based;
 } tusb_desc_cs_video_frm_t;
 
 /* video streaming interface */
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index d4ef1fd09..2c5dce723 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -399,6 +399,8 @@ typedef struct TU_ATTR_PACKED {
   uint8_t iFunction         ; ///< Index of the string descriptor describing the interface association.
 } tusb_desc_interface_assoc_t;
 
+TU_VERIFY_STATIC( sizeof(tusb_desc_interface_assoc_t) == 8, "size is not correct");
+
 // USB String Descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
@@ -469,7 +471,6 @@ typedef struct TU_ATTR_PACKED {
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
-
 TU_ATTR_PACKED_END  // End of all packed definitions
 TU_ATTR_BIT_FIELD_ORDER_END
 
-- 
cgit v1.3.1


From 0daf8ec51b9513fbab9601fedb2150dda3927b05 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 Jan 2024 23:23:38 +0700
Subject: update example to work bulk mjpeg

---
 .../device/video_capture/src/usb_descriptors.c     | 27 +++++++++++++++++++++-
 src/class/video/video.h                            | 10 +++++++-
 2 files changed, 35 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 8e54d3afd..90a6b27a2 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -109,6 +109,10 @@ uint8_t const* tud_descriptor_device_cb(void) {
   #define EPNUM_VIDEO_IN    0x81
 #endif
 
+#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+  #define USE_MJPEG
+#endif
+
 // For mcus that does not have enough SRAM for frame buffer, we use fixed frame data.
 // To further reduce the size, we use MJPEG format instead of YUY2.
 // Select interface descriptor and length accordingly.
@@ -197,8 +201,15 @@ typedef struct TU_ATTR_PACKED {
 typedef struct TU_ATTR_PACKED {
   tusb_desc_interface_t itf;
   tusb_desc_video_streaming_input_header_1byte_t header;
+
+#ifdef USE_MJPEG
+  tusb_desc_video_format_mjpeg_t format;
+  tusb_desc_video_frame_mjpeg_continuous_t frame;
+#else
   tusb_desc_video_format_uncompressed_t format;
   tusb_desc_video_frame_uncompressed_continuous_t frame;
+#endif
+
   tusb_desc_video_streaming_color_matching_t color;
   tusb_desc_endpoint_t ep;
 } uvc_streaming_desc_t;
@@ -316,14 +327,22 @@ const uvc_cfg_desc_t config_desc = {
             .bmaControls = { 0 }
         },
         .format = {
+#ifdef USE_MJPEG
+            .bLength = sizeof(tusb_desc_video_format_mjpeg_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_MJPEG,
+            .bFormatIndex = 1, // 1-based index
+            .bNumFrameDescriptors = 1,
+            .bmFlags = 0,
+#else
             .bLength = sizeof(tusb_desc_video_format_uncompressed_t),
             .bDescriptorType = TUSB_DESC_CS_INTERFACE,
             .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED,
-
             .bFormatIndex = 1, // 1-based index
             .bNumFrameDescriptors = 1,
             .guidFormat = { TUD_VIDEO_GUID_YUY2 },
             .bBitsPerPixel = 16,
+#endif
             .bDefaultFrameIndex = 1,
             .bAspectRatioX = 0,
             .bAspectRatioY = 0,
@@ -331,9 +350,15 @@ const uvc_cfg_desc_t config_desc = {
             .bCopyProtect = 0
         },
         .frame = {
+#ifdef USE_MJPEG
+            .bLength = sizeof(tusb_desc_video_frame_mjpeg_continuous_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_MJPEG,
+#else
             .bLength = sizeof(tusb_desc_video_frame_uncompressed_continuous_t),
             .bDescriptorType = TUSB_DESC_CS_INTERFACE,
             .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED,
+#endif
 
             .bFrameIndex = 1, // 1-based index
             .bmCapabilities = 0,
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 162d4e4c4..bed8eeecf 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -405,7 +405,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bDescriptorSubType;
   uint8_t bFormatIndex;
   uint8_t bNumFrameDescriptors;
-  uint8_t bmFlags;
+  uint8_t bmFlags; // Bit 0: fixed size samples (1 = yes)
   uint8_t bDefaultFrameIndex;
   uint8_t bAspectRatioX;
   uint8_t bAspectRatioY;
@@ -415,7 +415,15 @@ typedef struct TU_ATTR_PACKED {
 
 // MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
 typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
+typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t;
+typedef tusb_desc_video_frame_uncompressed_2int_t tusb_desc_video_frame_mjpeg_2int_t;
+typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_mjpeg_3int_t;
+typedef tusb_desc_video_frame_uncompressed_4int_t tusb_desc_video_frame_mjpeg_4int_t;
 
+// continuous = 3 intervals: min, max, step
+typedef tusb_desc_video_frame_mjpeg_3int_t tusb_desc_video_frame_mjpeg_continuous_t;
+
+//------------- DV -------------//
 // DV payload specs: 3.1.1
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
-- 
cgit v1.3.1


From 82be2477e8201fe6ea61324b8995b79d1b4cab46 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Mon, 29 Jan 2024 12:04:00 +0100
Subject: fixed #2437

---
 src/class/cdc/cdc_host.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 7adaa0c8c..36b5d4234 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -77,6 +77,8 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
+
+  bool configured;
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -257,6 +259,7 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const
       p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
       p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
       p_cdc->line_state         = 0;
+      p_cdc->configured         = false;
       return p_cdc;
     }
   }
@@ -305,7 +308,8 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) {
 
 bool tuh_cdc_mounted(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
-  return p_cdc != NULL;
+  TU_VERIFY(p_cdc);
+  return p_cdc->configured;
 }
 
 bool tuh_cdc_get_dtr(uint8_t idx) {
@@ -747,6 +751,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
 
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
   TU_LOG_DRV("CDCh Set Configure complete\r\n");
+  p_cdc->configured = true;
   if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
 
   // Prepare for incoming data
-- 
cgit v1.3.1


From 55950656cbee915662a9a33477ddd549489ffcf0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 29 Jan 2024 23:23:06 +0700
Subject: add freertos build support for video_capture example

---
 examples/device/video_capture/src/CMakeLists.txt   |   4 +
 examples/device/video_capture/src/main.c           | 131 ++++++++++++++++++---
 examples/device/video_capture/src/tusb_config.h    |   8 ++
 .../device/video_capture/src/usb_descriptors.c     |  29 +++--
 hw/bsp/board_api.h                                 |  19 ++-
 src/class/video/video.h                            |   2 +-
 6 files changed, 170 insertions(+), 23 deletions(-)
 create mode 100644 examples/device/video_capture/src/CMakeLists.txt

(limited to 'src')

diff --git a/examples/device/video_capture/src/CMakeLists.txt b/examples/device/video_capture/src/CMakeLists.txt
new file mode 100644
index 000000000..cef2b46ee
--- /dev/null
+++ b/examples/device/video_capture/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index e63335e67..091eb8d0c 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -48,13 +48,25 @@ enum {
 
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-void led_blinking_task(void);
-void video_task(void);
+void led_blinking_task(void* param);
+void usb_device_task(void *param);
+void video_task(void* param);
 
-/*------------- MAIN -------------*/
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+void freertos_init_task(void);
+#endif
+
+
+//--------------------------------------------------------------------+
+// Main
+//--------------------------------------------------------------------+
 int main(void) {
   board_init();
 
+  // If using FreeRTOS: create blinky, tinyusb device, video task
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  freertos_init_task();
+#else
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
@@ -64,10 +76,10 @@ int main(void) {
 
   while (1) {
     tud_task(); // tinyusb device task
-    led_blinking_task();
-
-    video_task();
+    led_blinking_task(NULL);
+    video_task(NULL);
   }
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -169,7 +181,7 @@ static void fill_color_bar(uint8_t* buffer, unsigned start_position) {
 
 #endif
 
-void video_task(void) {
+void video_send_frame(void) {
   static unsigned start_ms = 0;
   static unsigned already_sent = 0;
 
@@ -213,6 +225,21 @@ void video_task(void) {
 #endif
 }
 
+
+void video_task(void* param) {
+  (void) param;
+
+  while(1) {
+    video_send_frame();
+
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(interval_ms / portTICK_PERIOD_MS);
+    #else
+    return;
+    #endif
+  }
+}
+
 void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
   (void) ctl_idx;
   (void) stm_idx;
@@ -231,16 +258,92 @@ int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
 }
 
 //--------------------------------------------------------------------+
-// BLINKING TASK
+// Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void) {
+void led_blinking_task(void* param) {
+  (void) param;
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
-  // Blink every interval ms
-  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
-  start_ms += blink_interval_ms;
+  while (1) {
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    #else
+    if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+    #endif
+
+    start_ms += blink_interval_ms;
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
+
+//--------------------------------------------------------------------+
+// FreeRTOS
+//--------------------------------------------------------------------+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#define VIDEO_STACK_SIZE    (configMINIMAL_STACK_SIZE*4)
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  #define USBD_STACK_SIZE     4096
+  int main(void);
+  void app_main(void) {
+    main();
+  }
+#else
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+
+StackType_t  video_stack[VIDEO_STACK_SIZE];
+StaticTask_t video_taskdef;
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void *param) {
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tud_init(BOARD_TUD_RHPORT);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
 
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tud_task();
+  }
 }
+
+void freertos_init_task(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(video_task, "cdc", VIDEO_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, video_stack, &video_taskdef);
+  #else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(video_task, "video", VIDEO_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
+  #endif
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+  #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  vTaskStartScheduler();
+  #endif
+}
+#endif
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index d563c6f5c..bdfc37d87 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -57,6 +57,11 @@
 #define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
+// Espressif IDF requires "freertos/" prefix in include path
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
 #ifndef CFG_TUSB_DEBUG
 #define CFG_TUSB_DEBUG        0
 #endif
@@ -103,6 +108,9 @@
 // use bulk endpoint for streaming interface
 #define CFG_TUD_VIDEO_STREAMING_BULK 1
 
+//#define CFG_EXAMPLE_VIDEO_READONLY
+//#define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 17e11229d..f308c75a7 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -364,7 +364,22 @@ const uvc_cfg_desc_t desc_fs_configuration = {
 };
 
 #if TUD_OPT_HIGH_SPEED
-uvc_cfg_desc_t desc_hs_configuration = desc_fs_configuration;
+uvc_cfg_desc_t desc_hs_configuration;
+
+static uint8_t * get_hs_configuration_desc(void) {
+  static bool init = false;
+
+  if (!init) {
+    desc_hs_configuration = desc_fs_configuration;
+    // change endpoint bulk size to 512 if bulk streaming
+    if (CFG_TUD_VIDEO_STREAMING_BULK) {
+      desc_hs_configuration.video_streaming.ep.wMaxPacketSize = 512;
+    }
+  }
+  init = true;
+
+  return (uint8_t *) &desc_hs_configuration;
+}
 
 // device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
 tusb_desc_device_qualifier_t const desc_device_qualifier = {
@@ -395,7 +410,11 @@ uint8_t const* tud_descriptor_device_qualifier_cb(void) {
 uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
   // if link speed is high return fullspeed config, and vice versa
-  return (uint8_t const*) ((tud_speed_get() == TUSB_SPEED_HIGH) ?  &desc_fs_configuration : &desc_hs_configuration);
+  if (tud_speed_get() == TUSB_SPEED_HIGH) {
+    return (uint8_t const*) &desc_fs_configuration;
+  } else {
+    return get_hs_configuration_desc();
+  }
 }
 #endif // highspeed
 
@@ -408,11 +427,7 @@ uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
 #if TUD_OPT_HIGH_SPEED
   // Although we are highspeed, host may be fullspeed.
   if (tud_speed_get() == TUSB_SPEED_HIGH) {
-    // change endpoint bulk size to 512 if bulk streaming
-    if (CFG_TUD_VIDEO_STREAMING_BULK) {
-      desc_hs_configuration.video_streaming.ep.wMaxPacketSize = 512;
-    }
-    return (uint8_t const*) &desc_hs_configuration;
+    return get_hs_configuration_desc();
   } else
 #endif
   {
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index 404509a28..0c8a35924 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -33,9 +33,26 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-
 #include "tusb.h"
 
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+#else
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+#endif
+#endif
+
 // Define the default baudrate
 #ifndef CFG_BOARD_UART_BAUDRATE
 #define CFG_BOARD_UART_BAUDRATE 115200   ///< Default baud rate
diff --git a/src/class/video/video.h b/src/class/video/video.h
index bed8eeecf..fb0d0af1d 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -398,7 +398,7 @@ typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_uncompre
 TU_VERIFY_STATIC(sizeof(tusb_desc_video_frame_uncompressed_continuous_t) == 38, "size is not correct");
 
 //------------- MJPEG -------------//
-// MJPEG payload specs: 3.1.1 formatt descriptor
+// MJPEG payload specs: 3.1.1 format descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
-- 
cgit v1.3.1


From 00ba4e95acec64da4446fa89a40c3a2e38beed3c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Jan 2024 10:59:12 +0700
Subject: cdch: de-configure when closing, rename configured to mounted

---
 src/class/cdc/cdc_host.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 36b5d4234..4e0a9499f 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -53,12 +53,13 @@ typedef struct {
   uint8_t bInterfaceSubClass;
   uint8_t bInterfaceProtocol;
 
+  uint8_t ep_notif;
   uint8_t serial_drid; // Serial Driver ID
+  bool mounted;        // Enumeration is complete
   cdc_acm_capability_t acm_capability;
-  uint8_t ep_notif;
 
-  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
   TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
+  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
 
   #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
   cdc_line_coding_t requested_line_coding;
@@ -77,8 +78,6 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-
-  bool configured;
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -259,7 +258,6 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const
       p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
       p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
       p_cdc->line_state         = 0;
-      p_cdc->configured         = false;
       return p_cdc;
     }
   }
@@ -309,7 +307,7 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) {
 bool tuh_cdc_mounted(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
-  return p_cdc->configured;
+  return p_cdc->mounted;
 }
 
 bool tuh_cdc_get_dtr(uint8_t idx) {
@@ -648,9 +646,9 @@ void cdch_close(uint8_t daddr) {
       // Invoke application callback
       if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx);
 
-      //tu_memclr(p_cdc, sizeof(cdch_interface_t));
       p_cdc->daddr = 0;
       p_cdc->bInterfaceNumber = 0;
+      p_cdc->mounted = false;
       tu_edpt_stream_close(&p_cdc->stream.tx);
       tu_edpt_stream_close(&p_cdc->stream.rx);
     }
@@ -751,7 +749,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
 
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
   TU_LOG_DRV("CDCh Set Configure complete\r\n");
-  p_cdc->configured = true;
+  p_cdc->mounted = true;
   if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
 
   // Prepare for incoming data
-- 
cgit v1.3.1


From f600a8a0fc263b764ea018f0d0912f8001dd3160 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 30 Jan 2024 10:33:55 +0100
Subject: fix tuh_hid_mounted() similar to #2437

---
 src/class/hid/hid_host.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index db52b503f..709fa3dd8 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -50,6 +50,7 @@ typedef struct
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
+  bool mounted;           // Enumeration is complete
 
   uint8_t itf_protocol;   // None, Keyboard, Mouse
   uint8_t protocol_mode;  // Boot (0) or Report protocol (1)
@@ -139,7 +140,8 @@ uint8_t tuh_hid_itf_get_total_count(void)
 bool tuh_hid_mounted(uint8_t daddr, uint8_t idx)
 {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
-  return p_hid != NULL;
+  TU_VERIFY(p_hid);
+  return p_hid->mounted;
 }
 
 bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info)
@@ -463,6 +465,7 @@ void hidh_close(uint8_t daddr)
       TU_LOG_DRV("  HIDh close addr = %u index = %u\r\n", daddr, i);
       if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
       p_hid->daddr = 0;
+      p_hid->mounted = false;
     }
   }
 }
@@ -632,6 +635,7 @@ static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t con
 {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid, );
+  p_hid->mounted = true;
 
   // enumeration is complete
   if (tuh_hid_mount_cb) tuh_hid_mount_cb(daddr, idx, desc_report, desc_len);
-- 
cgit v1.3.1


From 82776aaca9f7a8ae1b627c42cd69a021b1b50fe3 Mon Sep 17 00:00:00 2001
From: mamiral <mahic.miral@gmx.com>
Date: Wed, 31 Jan 2024 10:48:15 +0100
Subject: Update vendor_device.c fifo mutex config similar to cdc_device.c.

---
 src/class/vendor/vendor_device.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 389a29696..a68cb2156 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -49,10 +49,8 @@ typedef struct
   uint8_t rx_ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
   uint8_t tx_ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
 
-#if CFG_FIFO_MUTEX
-  osal_mutex_def_t rx_ff_mutex;
-  osal_mutex_def_t tx_ff_mutex;
-#endif
+  OSAL_MUTEX_DEF(rx_ff_mutex);
+  OSAL_MUTEX_DEF(tx_ff_mutex);
 
   // Endpoint Transfer buffer
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_VENDOR_EPSIZE];
@@ -183,10 +181,8 @@ void vendord_init(void)
     tu_fifo_config(&p_itf->rx_ff, p_itf->rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, 1, false);
     tu_fifo_config(&p_itf->tx_ff, p_itf->tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, 1, false);
 
-#if CFG_FIFO_MUTEX
     tu_fifo_config_mutex(&p_itf->rx_ff, NULL, osal_mutex_create(&p_itf->rx_ff_mutex));
     tu_fifo_config_mutex(&p_itf->tx_ff, osal_mutex_create(&p_itf->tx_ff_mutex), NULL);
-#endif
   }
 }
 
-- 
cgit v1.3.1


From e63a2f5c58b111a5f990ad1b6a0260f09a248c53 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Wed, 31 Jan 2024 18:00:25 +0100
Subject: fix #2444 and other small things

---
 src/class/cdc/cdc_host.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 4e0a9499f..2fb37d835 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1345,7 +1345,7 @@ static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, ui
                            complete_cb, user_data);
 }
 
-static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+static inline bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data);
 }
 
@@ -1358,7 +1358,7 @@ static bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_
 static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
-  TU_VERIFY(div_ps != 0);
+  TU_VERIFY(div_ps);
   TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
                             complete_cb, user_data));
   return true;
@@ -1379,7 +1379,7 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui
   p_cdc->requested_line_coding.data_bits = data_bits;
 
   uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
-  TU_VERIFY(lcr != 0);
+  TU_VERIFY(lcr);
   TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
                                complete_cb ? ch34x_control_complete : NULL, user_data));
   return true;
@@ -1395,6 +1395,7 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
 }
 
 static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
   uint8_t const itf_num = 0;
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
@@ -1443,7 +1444,7 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t con
 
     // update transfer result, user_data is expected to point to xfer_result_t
     if (user_data) {
-      user_data = result;
+      *((xfer_result_t*) user_data) = result;
     }
   }
 
@@ -1513,8 +1514,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
   uintptr_t const state = xfer->user_data;
   uint8_t buffer[2]; // TODO remove
   TU_ASSERT (p_cdc,);
-
-  // TODO check xfer->result
+  TU_ASSERT (xfer->result == XFER_RESULT_SUCCESS,);
 
   switch (state) {
     case CONFIG_CH34X_READ_VERSION:
@@ -1531,9 +1531,9 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
       // init CH34x with line coding
       cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
       uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
-      TU_ASSERT(div_ps != 0, );
+      TU_ASSERT(div_ps, );
       uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
-      TU_ASSERT(lcr != 0, );
+      TU_ASSERT(lcr, );
       TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
                                    ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
       break;
@@ -1573,7 +1573,7 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
   uint8_t b;
   uint32_t c;
 
-  TU_VERIFY(baval != 0, 0);
+  TU_VERIFY(baval != 0 && baval <= 2000000, 0);
   switch (baval) {
     case 921600:
       a = 0xf3;
@@ -1627,7 +1627,7 @@ static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bit
       break;
 
     case CDC_LINE_CODING_PARITY_ODD:
-    lcr |= CH34X_LCR_ENABLE_PAR;
+      lcr |= CH34X_LCR_ENABLE_PAR;
       break;
 
     case CDC_LINE_CODING_PARITY_EVEN:
-- 
cgit v1.3.1


From e784e20b93068f4b063e066eb50ea005aeec99f4 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Wed, 7 Feb 2024 10:11:28 +0100
Subject: changes after review

---
 src/host/usbh.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index ee7424ed9..d4f308e48 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -291,9 +291,6 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) {
   *vid = dev->vid;
   *pid = dev->pid;
 
-  TU_LOG_HEX_USBH(*vid);
-  TU_LOG_HEX_USBH(*pid);
-
   return true;
 }
 
@@ -863,7 +860,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
     // HCD error, mark endpoint as ready to allow next transfer
     ep_state->busy    = 0;
     ep_state->claimed = 0;
-    TU_LOG_USBH("Failed\r\n");
+    TU_LOG1("Failed\r\n");
 //    TU_BREAKPOINT();
     return false;
   }
@@ -1321,7 +1318,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     if ( retry ) {
       failed_count++;
       osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit
-      TU_LOG_USBH("Enumeration attempt %u\r\n", failed_count);
+      TU_LOG1("Enumeration attempt %u\r\n", failed_count);
       retry = tuh_control_xfer(xfer);
     }
 
-- 
cgit v1.3.1


From 0531027b57e9401d49afa13e70f5a6a9763a3b85 Mon Sep 17 00:00:00 2001
From: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
Date: Mon, 22 Jan 2024 23:19:43 +0100
Subject: usbd: log outbound xfer bytes in debug

---
 src/device/usbd.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 5c94ebcc5..28eb9aa6e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1232,6 +1232,11 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   // TU_VERIFY(tud_ready());
 
   TU_LOG_USBD("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
+#if CFG_TUD_LOG_LEVEL >= 3
+  if(tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
+    TU_LOG_MEM(CFG_TUD_LOG_LEVEL, buffer, total_bytes, 2);
+  }
+#endif
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
-- 
cgit v1.3.1


From 6c4a5292a6a59dec1b7f37be42725ea85205f3c9 Mon Sep 17 00:00:00 2001
From: Jerry Palacios <jerry.palacios@wavenumber.net>
Date: Wed, 7 Feb 2024 17:03:13 -0600
Subject: Back to original

---
 .github/workflows/build_aarch64.yml                |   2 +-
 .github/workflows/build_arm.yml                    |   2 +-
 .github/workflows/build_esp.yml                    |   6 +-
 .github/workflows/build_iar.yml                    |   2 +
 .github/workflows/build_msp430.yml                 |   2 +-
 .github/workflows/build_renesas.yml                |   2 +-
 .github/workflows/build_riscv.yml                  |   2 +-
 .github/workflows/build_win_mac.yml                |   2 +-
 .github/workflows/cmake_arm.yml                    |   4 +-
 .github/workflows/pre-commit.yml                   |   2 +-
 examples/device/video_capture/src/CMakeLists.txt   |   4 +
 examples/device/video_capture/src/images.h         |   3 +
 examples/device/video_capture/src/main.c           | 228 +++--
 examples/device/video_capture/src/tusb_config.h    |  12 +-
 .../device/video_capture/src/usb_descriptors.c     | 450 +++++++---
 .../device/video_capture/src/usb_descriptors.h     |  87 +-
 examples/host/cdc_msc_hid/src/cdc_app.c            |  76 +-
 examples/host/cdc_msc_hid/src/tusb_config.h        |   1 +
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    |   1 +
 hw/bsp/board_api.h                                 |  19 +-
 hw/bsp/espressif/boards/family.c                   |  30 +-
 hw/bsp/espressif/components/led_strip/CHANGELOG.md |  38 +
 .../espressif/components/led_strip/CMakeLists.txt  |  27 +-
 hw/bsp/espressif/components/led_strip/LICENSE      | 202 +++++
 hw/bsp/espressif/components/led_strip/README.md    |  97 +++
 hw/bsp/espressif/components/led_strip/api.md       | 454 ++++++++++
 .../examples/led_strip_rmt_ws2812/CMakeLists.txt   |   9 +
 .../examples/led_strip_rmt_ws2812/README.md        |  31 +
 .../led_strip_rmt_ws2812/dependencies.lock         |  15 +
 .../led_strip_rmt_ws2812/main/CMakeLists.txt       |   2 +
 .../led_strip_rmt_ws2812/main/idf_component.yml    |   5 +
 .../main/led_strip_rmt_ws2812_main.c               |  75 ++
 .../components/led_strip/idf_component.yml         |   5 +
 .../components/led_strip/include/led_strip.h       | 191 ++---
 .../components/led_strip/include/led_strip_rmt.h   |  53 ++
 .../components/led_strip/include/led_strip_spi.h   |  46 ++
 .../components/led_strip/include/led_strip_types.h |  54 ++
 .../led_strip/interface/led_strip_interface.h      |  95 +++
 .../components/led_strip/src/led_strip_api.c       |  94 +++
 .../components/led_strip/src/led_strip_rmt_dev.c   | 164 ++++
 .../led_strip/src/led_strip_rmt_dev_idf4.c         | 194 +++++
 .../led_strip/src/led_strip_rmt_encoder.c          | 146 ++++
 .../led_strip/src/led_strip_rmt_encoder.h          |  38 +
 .../led_strip/src/led_strip_rmt_ws2812.c           | 171 ----
 .../components/led_strip/src/led_strip_spi_dev.c   | 209 +++++
 hw/bsp/family_support.cmake                        |   1 -
 hw/bsp/mcx/boards/bunny-brain/board.cmake          |  21 -
 hw/bsp/mcx/boards/bunny-brain/board.h              |  66 --
 hw/bsp/mcx/boards/bunny-brain/board.mk             |  11 -
 hw/bsp/mcx/boards/bunny-brain/clock_config.c       | 338 --------
 hw/bsp/mcx/boards/bunny-brain/clock_config.h       | 177 ----
 hw/bsp/mcx/boards/bunny-brain/pin_mux.c            | 141 ----
 hw/bsp/mcx/boards/bunny-brain/pin_mux.h            |  51 --
 hw/bsp/mcx/boards/frdm-mcxn947/board.cmake         |  21 -
 hw/bsp/mcx/boards/frdm-mcxn947/board.h             |  66 --
 hw/bsp/mcx/boards/frdm-mcxn947/board.mk            |  11 -
 hw/bsp/mcx/boards/frdm-mcxn947/clock_config.c      | 338 --------
 hw/bsp/mcx/boards/frdm-mcxn947/clock_config.h      | 177 ----
 hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.c           | 143 ----
 hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.h           |  51 --
 src/class/audio/audio_device.c                     |   2 +-
 src/class/cdc/cdc.h                                |  20 +-
 src/class/cdc/cdc_host.c                           | 916 ++++++++++++++++-----
 src/class/cdc/cdc_host.h                           |  13 +-
 src/class/cdc/serial/ch34x.h                       |  84 ++
 src/class/hid/hid_host.c                           |   6 +-
 src/class/vendor/vendor_device.c                   |   8 +-
 src/class/video/video.h                            | 236 ++++--
 src/class/video/video_device.c                     |  26 +-
 src/common/tusb_common.h                           |   1 +
 src/common/tusb_types.h                            | 157 ++--
 src/portable/synopsys/dwc2/dcd_dwc2.c              |   4 +-
 src/tusb_option.h                                  |  17 +
 test/hil/hil_test.py                               |  11 +-
 74 files changed, 3839 insertions(+), 2627 deletions(-)
 create mode 100644 examples/device/video_capture/src/CMakeLists.txt
 create mode 100644 hw/bsp/espressif/components/led_strip/CHANGELOG.md
 create mode 100644 hw/bsp/espressif/components/led_strip/LICENSE
 create mode 100644 hw/bsp/espressif/components/led_strip/README.md
 create mode 100644 hw/bsp/espressif/components/led_strip/api.md
 create mode 100644 hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/CMakeLists.txt
 create mode 100644 hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/README.md
 create mode 100644 hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/dependencies.lock
 create mode 100644 hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/CMakeLists.txt
 create mode 100644 hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/idf_component.yml
 create mode 100644 hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/led_strip_rmt_ws2812_main.c
 create mode 100644 hw/bsp/espressif/components/led_strip/idf_component.yml
 create mode 100644 hw/bsp/espressif/components/led_strip/include/led_strip_rmt.h
 create mode 100644 hw/bsp/espressif/components/led_strip/include/led_strip_spi.h
 create mode 100644 hw/bsp/espressif/components/led_strip/include/led_strip_types.h
 create mode 100644 hw/bsp/espressif/components/led_strip/interface/led_strip_interface.h
 create mode 100644 hw/bsp/espressif/components/led_strip/src/led_strip_api.c
 create mode 100644 hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev.c
 create mode 100644 hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev_idf4.c
 create mode 100644 hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.c
 create mode 100644 hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.h
 delete mode 100644 hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c
 create mode 100644 hw/bsp/espressif/components/led_strip/src/led_strip_spi_dev.c
 delete mode 100644 hw/bsp/mcx/boards/bunny-brain/board.cmake
 delete mode 100644 hw/bsp/mcx/boards/bunny-brain/board.h
 delete mode 100644 hw/bsp/mcx/boards/bunny-brain/board.mk
 delete mode 100644 hw/bsp/mcx/boards/bunny-brain/clock_config.c
 delete mode 100644 hw/bsp/mcx/boards/bunny-brain/clock_config.h
 delete mode 100644 hw/bsp/mcx/boards/bunny-brain/pin_mux.c
 delete mode 100644 hw/bsp/mcx/boards/bunny-brain/pin_mux.h
 delete mode 100644 hw/bsp/mcx/boards/frdm-mcxn947/board.cmake
 delete mode 100644 hw/bsp/mcx/boards/frdm-mcxn947/board.h
 delete mode 100644 hw/bsp/mcx/boards/frdm-mcxn947/board.mk
 delete mode 100644 hw/bsp/mcx/boards/frdm-mcxn947/clock_config.c
 delete mode 100644 hw/bsp/mcx/boards/frdm-mcxn947/clock_config.h
 delete mode 100644 hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.c
 delete mode 100644 hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.h
 create mode 100644 src/class/cdc/serial/ch34x.h

(limited to 'src')

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 40fc8d63a..e5dbf9494 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -36,7 +36,7 @@ jobs:
         - 'broadcom_64bit'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 4127db5bf..9f3270c91 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -46,7 +46,7 @@ jobs:
         - 'tm4c123 xmc4000'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 33caa0edb..8fbdb31ff 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -8,6 +8,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - 'test/hil/**'
       - '.github/workflows/build_esp.yml'
   pull_request:
     branches: [ master ]
@@ -16,6 +17,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - 'test/hil/**'
       - '.github/workflows/build_esp.yml'
 
 concurrency:
@@ -35,7 +37,7 @@ jobs:
         - 'espressif_s3_devkitc'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
@@ -46,7 +48,7 @@ jobs:
       uses: actions/checkout@v4
 
     - name: Build
-      run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32.py ${{ matrix.board }}
+      run: docker run --rm -v $PWD:/project -w /project espressif/idf:v5.1.1 python3 tools/build_esp32.py ${{ matrix.board }}
 
     - name: Upload Artifacts for Hardware Testing
       if: matrix.board == 'espressif_s3_devkitc' && github.repository_owner == 'hathach'
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 9f2cc0351..a0a022ecc 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -9,6 +9,7 @@ on:
       - 'lib/**'
       - 'hw/**'
       - 'tools/get_deps.py'
+      - 'test/hil/**'
       - '.github/workflows/build_iar.yml'
   pull_request:
     branches: [ master ]
@@ -18,6 +19,7 @@ on:
       - 'lib/**'
       - 'hw/**'
       - 'tools/get_deps.py'
+      - 'test/hil/**'
       - '.github/workflows/build_iar.yml'
 
 concurrency:
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 296dbb766..f913df913 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -36,7 +36,7 @@ jobs:
 
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 017a29eee..ec06c9426 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -35,7 +35,7 @@ jobs:
         - 'rx'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index e030bb77f..e891a3a51 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -37,7 +37,7 @@ jobs:
         - 'gd32vf103'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 7fa1a6943..b33b5b593 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -35,7 +35,7 @@ jobs:
 
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 8b87fef21..f97645ad1 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -8,6 +8,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - 'test/hil/**'
       - 'tools/get_deps.py'
       - '.github/workflows/cmake_arm.yml'
   pull_request:
@@ -17,6 +18,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - 'test/hil/**'
       - 'tools/get_deps.py'
       - '.github/workflows/cmake_arm.yml'
 
@@ -57,7 +59,7 @@ jobs:
           - 'stm32u5'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 2e9ae9264..e36259daa 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -15,7 +15,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v4
+      uses: actions/setup-python@v5
       with:
         python-version: '3.x'
 
diff --git a/examples/device/video_capture/src/CMakeLists.txt b/examples/device/video_capture/src/CMakeLists.txt
new file mode 100644
index 000000000..cef2b46ee
--- /dev/null
+++ b/examples/device/video_capture/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "main.c" "usb_descriptors.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h
index 784e7754c..ac372cb16 100644
--- a/examples/device/video_capture/src/images.h
+++ b/examples/device/video_capture/src/images.h
@@ -1,4 +1,5 @@
 #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+// uncopmressed frame
 static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
   /* 0 */
   0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
@@ -1650,8 +1651,10 @@ static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
 };
+
 #else
 
+// mpeg compressed data (not CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
 #define color_bar_0_jpg_len  511
 #define color_bar_1_jpg_len  512
 #define color_bar_2_jpg_len  511
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 711d4710a..2a2b0961f 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -40,7 +40,7 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -48,14 +48,25 @@ enum  {
 
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-void led_blinking_task(void);
-void video_task(void);
+void led_blinking_task(void* param);
+void usb_device_task(void *param);
+void video_task(void* param);
 
-/*------------- MAIN -------------*/
-int main(void)
-{
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+void freertos_init_task(void);
+#endif
+
+
+//--------------------------------------------------------------------+
+// Main
+//--------------------------------------------------------------------+
+int main(void) {
   board_init();
 
+  // If using FreeRTOS: create blinky, tinyusb device, video task
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  freertos_init_task();
+#else
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
@@ -63,13 +74,12 @@ int main(void)
     board_init_after_tusb();
   }
 
-  while (1)
-  {
+  while (1) {
     tud_task(); // tinyusb device task
-    led_blinking_task();
-
-    video_task();
+    led_blinking_task(NULL);
+    video_task(NULL);
   }
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -77,33 +87,28 @@ int main(void)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
+void tud_resume_cb(void) {
   blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
-
 //--------------------------------------------------------------------+
 // USB Video
 //--------------------------------------------------------------------+
@@ -111,11 +116,12 @@ static unsigned frame_num = 0;
 static unsigned tx_busy = 0;
 static unsigned interval_ms = 1000 / FRAME_RATE;
 
-/* YUY2 frame buffer */
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
+// For mcus that does not have enough SRAM for frame buffer, we use fixed frame data.
+// To further reduce the size, we use MJPEG format instead of YUY2.
 #include "images.h"
 
-# if !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+#if !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
 static struct {
   uint32_t       size;
   uint8_t const *buffer;
@@ -129,29 +135,30 @@ static struct {
   {color_bar_6_jpg_len, color_bar_6_jpg},
   {color_bar_7_jpg_len, color_bar_7_jpg},
 };
-# endif
+#endif
 
 #else
+
+// YUY2 frame buffer
 static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8];
-static void fill_color_bar(uint8_t *buffer, unsigned start_position)
-{
-  /* EBU color bars
-   * See also https://stackoverflow.com/questions/6939422 */
+
+static void fill_color_bar(uint8_t* buffer, unsigned start_position) {
+  /* EBU color bars: https://stackoverflow.com/questions/6939422 */
   static uint8_t const bar_color[8][4] = {
-    /*  Y,   U,   Y,   V */
-    { 235, 128, 235, 128}, /* 100% White */
-    { 219,  16, 219, 138}, /* Yellow */
-    { 188, 154, 188,  16}, /* Cyan */
-    { 173,  42, 173,  26}, /* Green */
-    {  78, 214,  78, 230}, /* Magenta */
-    {  63, 102,  63, 240}, /* Red */
-    {  32, 240,  32, 118}, /* Blue */
-    {  16, 128,  16, 128}, /* Black */
+      /*  Y,   U,   Y,   V */
+      { 235, 128, 235, 128}, /* 100% White */
+      { 219,  16, 219, 138}, /* Yellow */
+      { 188, 154, 188,  16}, /* Cyan */
+      { 173,  42, 173,  26}, /* Green */
+      {  78, 214,  78, 230}, /* Magenta */
+      {  63, 102,  63, 240}, /* Red */
+      {  32, 240,  32, 118}, /* Blue */
+      {  16, 128,  16, 128}, /* Black */
   };
-  uint8_t *p;
+  uint8_t* p;
 
   /* Generate the 1st line */
-  uint8_t *end = &buffer[FRAME_WIDTH * 2];
+  uint8_t* end = &buffer[FRAME_WIDTH * 2];
   unsigned idx = (FRAME_WIDTH / 2 - 1) - (start_position % (FRAME_WIDTH / 2));
   p = &buffer[idx * 4];
   for (unsigned i = 0; i < 8; ++i) {
@@ -163,6 +170,7 @@ static void fill_color_bar(uint8_t *buffer, unsigned start_position)
       }
     }
   }
+
   /* Duplicate the 1st line to the others */
   p = &buffer[FRAME_WIDTH * 2];
   for (unsigned i = 1; i < FRAME_HEIGHT; ++i) {
@@ -170,32 +178,33 @@ static void fill_color_bar(uint8_t *buffer, unsigned start_position)
     p += FRAME_WIDTH * 2;
   }
 }
+
 #endif
 
-void video_task(void)
-{
+void video_send_frame(void) {
   static unsigned start_ms = 0;
   static unsigned already_sent = 0;
 
   if (!tud_video_n_streaming(0, 0)) {
-    already_sent  = 0;
-    frame_num     = 0;
+    already_sent = 0;
+    frame_num = 0;
     return;
   }
 
   if (!already_sent) {
     already_sent = 1;
+    tx_busy = 1;
     start_ms = board_millis();
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+    #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
     tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                            FRAME_WIDTH * FRAME_HEIGHT * 16/8);
-# else
+    #else
     tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
-# endif
+    #endif
 #else
     fill_color_bar(frame_buffer, frame_num);
-    tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+    tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8);
 #endif
   }
 
@@ -203,49 +212,140 @@ void video_task(void)
   if (cur - start_ms < interval_ms) return; // not enough time
   if (tx_busy) return;
   start_ms += interval_ms;
+  tx_busy = 1;
 
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+  #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
   tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                          FRAME_WIDTH * FRAME_HEIGHT * 16/8);
-# else
+  #else
   tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
-# endif
+  #endif
 #else
   fill_color_bar(frame_buffer, frame_num);
-  tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+  tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8);
 #endif
 }
 
-void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
-{
-  (void)ctl_idx; (void)stm_idx;
+
+void video_task(void* param) {
+  (void) param;
+
+  while(1) {
+    video_send_frame();
+
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(interval_ms / portTICK_PERIOD_MS);
+    #else
+    return;
+    #endif
+  }
+}
+
+void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
+  (void) ctl_idx;
+  (void) stm_idx;
   tx_busy = 0;
   /* flip buffer */
   ++frame_num;
 }
 
 int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
-			video_probe_and_commit_control_t const *parameters)
-{
-  (void)ctl_idx; (void)stm_idx;
+                        video_probe_and_commit_control_t const* parameters) {
+  (void) ctl_idx;
+  (void) stm_idx;
   /* convert unit to ms from 100 ns */
   interval_ms = parameters->dwFrameInterval / 10000;
   return VIDEO_ERROR_NONE;
 }
 
 //--------------------------------------------------------------------+
-// BLINKING TASK
+// Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void* param) {
+  (void) param;
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
-  // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
-  start_ms += blink_interval_ms;
+  while (1) {
+    #if CFG_TUSB_OS == OPT_OS_FREERTOS
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    #else
+    if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
+    #endif
+
+    start_ms += blink_interval_ms;
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
+}
+
+//--------------------------------------------------------------------+
+// FreeRTOS
+//--------------------------------------------------------------------+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#define VIDEO_STACK_SIZE    (configMINIMAL_STACK_SIZE*4)
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  #define USBD_STACK_SIZE     4096
+  int main(void);
+  void app_main(void) {
+    main();
+  }
+#else
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+// static task
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
+
+StackType_t  usb_device_stack[USBD_STACK_SIZE];
+StaticTask_t usb_device_taskdef;
+
+StackType_t  video_stack[VIDEO_STACK_SIZE];
+StaticTask_t video_taskdef;
+#endif
+
+// USB Device Driver task
+// This top level thread process all usb events and invoke callbacks
+void usb_device_task(void *param) {
+  (void) param;
+
+  // init device stack on configured roothub port
+  // This should be called after scheduler/kernel is started.
+  // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+  tud_init(BOARD_TUD_RHPORT);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tud_task();
+  }
+}
 
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+void freertos_init_task(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(video_task, "cdc", VIDEO_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, video_stack, &video_taskdef);
+  #else
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(video_task, "video", VIDEO_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
+  #endif
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+  #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  vTaskStartScheduler();
+  #endif
 }
+#endif
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 274bf2b9c..bdfc37d87 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -57,6 +57,11 @@
 #define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
+// Espressif IDF requires "freertos/" prefix in include path
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
 #ifndef CFG_TUSB_DEBUG
 #define CFG_TUSB_DEBUG        0
 #endif
@@ -97,11 +102,14 @@
 // The number of video streaming interfaces
 #define CFG_TUD_VIDEO_STREAMING  1
 
-// video streaming endpoint size
+// video streaming endpoint buffer size
 #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
 
 // use bulk endpoint for streaming interface
-#define CFG_TUD_VIDEO_STREAMING_BULK 0
+#define CFG_TUD_VIDEO_STREAMING_BULK 1
+
+//#define CFG_EXAMPLE_VIDEO_READONLY
+//#define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG
 
 #ifdef __cplusplus
  }
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 49919fc58..f308c75a7 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -40,11 +40,30 @@
 #define USB_VID   0xCafe
 #define USB_BCD   0x0200
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+  STRID_UVC_CONTROL,
+  STRID_UVC_STREAMING,
+};
+
+// array of pointer to string descriptors
+char const* string_desc_arr[] = {
+    (const char[]) {0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                     // 1: Manufacturer
+    "TinyUSB Device",              // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "TinyUSB UVC Control",         // 4: UVC Interface
+    "TinyUSB UVC Streaming",       // 5: UVC Interface
+};
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
+tusb_desc_device_t const desc_device = {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = USB_BCD,
@@ -61,201 +80,374 @@ tusb_desc_device_t const desc_device =
     .idProduct          = USB_PID,
     .bcdDevice          = 0x0100,
 
-    .iManufacturer      = 0x01,
-    .iProduct           = 0x02,
-    .iSerialNumber      = 0x03,
+    .iManufacturer      = STRID_MANUFACTURER,
+    .iProduct           = STRID_PRODUCT,
+    .iSerialNumber      = STRID_SERIAL,
 
     .bNumConfigurations = 0x01
 };
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
-  return (uint8_t const *) &desc_device;
+uint8_t const* tud_descriptor_device_cb(void) {
+  return (uint8_t const*) &desc_device;
 }
 
 //--------------------------------------------------------------------+
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
-# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
-#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_BULK_LEN)
-# else
-#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
-# endif
-#else
-# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
-#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN)
-# else
-#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
-# endif
-#endif
+/* Time stamp base clock. It is a deprecated parameter. */
+#define UVC_CLOCK_FREQUENCY    27000000
+
+/* video capture path */
+#define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
+#define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
+
+enum {
+  ITF_NUM_VIDEO_CONTROL,
+  ITF_NUM_VIDEO_STREAMING,
+  ITF_NUM_TOTAL
+};
 
+// Select appropriate endpoint number
 #if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
-#if 1 == CFG_TUD_VIDEO_STREAMING_BULK
-  #define EPNUM_VIDEO_IN    0x82
-#else
-  #define EPNUM_VIDEO_IN    0x83
-#endif
-
+  #define EPNUM_VIDEO_IN    (CFG_TUD_VIDEO_STREAMING_BULK ? 0x82 : 0x83)
 #elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
-  #define EPNUM_VIDEO_IN    0x88
-
+  #define EPNUM_VIDEO_IN    (CFG_TUD_VIDEO_STREAMING_BULK ? 0x81 : 0x88)
 #else
   #define EPNUM_VIDEO_IN    0x81
+#endif
 
+#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+  #define USE_MJPEG 1
+#else
+  #define USE_MJPEG 0
 #endif
 
-uint8_t const desc_fs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
+#define USE_ISO_STREAMING (!CFG_TUD_VIDEO_STREAMING_BULK)
 
-  // IAD for Video Control
-#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
-# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(4, EPNUM_VIDEO_IN,
-                                          FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                          64)
-# else
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
-                                     FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                     CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
-# endif
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_control_header_1itf_t header;
+  tusb_desc_video_control_camera_terminal_t camera_terminal;
+  tusb_desc_video_control_output_terminal_t output_terminal;
+} uvc_control_desc_t;
+
+/* Windows support YUY2 and NV12
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_interface_t itf;
+  tusb_desc_video_streaming_input_header_1byte_t header;
+
+#if USE_MJPEG
+  tusb_desc_video_format_mjpeg_t format;
+  tusb_desc_video_frame_mjpeg_continuous_t frame;
 #else
-# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(4, EPNUM_VIDEO_IN,
-                                            FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                            64)
-# else
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(4, EPNUM_VIDEO_IN,
-                                       FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                       CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
-# endif
+  tusb_desc_video_format_uncompressed_t format;
+  tusb_desc_video_frame_uncompressed_continuous_t frame;
 #endif
-};
 
-#if TUD_OPT_HIGH_SPEED
-// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+  tusb_desc_video_streaming_color_matching_t color;
 
-uint8_t const desc_hs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
+#if USE_ISO_STREAMING
+  // For ISO streaming, USB spec requires to alternate interface
+  tusb_desc_interface_t itf_alt;
+#endif
 
-  // IAD for Video Control
-#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
-# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(4, EPNUM_VIDEO_IN,
-                                          FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                          512)
-# else
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
-                                     FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                     CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
-# endif
+  tusb_desc_endpoint_t ep;
+} uvc_streaming_desc_t;
+
+typedef struct TU_ATTR_PACKED {
+  tusb_desc_configuration_t config;
+  tusb_desc_interface_assoc_t iad;
+  uvc_control_desc_t video_control;
+  uvc_streaming_desc_t video_streaming;
+} uvc_cfg_desc_t;
+
+const uvc_cfg_desc_t desc_fs_configuration = {
+    .config = {
+        .bLength = sizeof(tusb_desc_configuration_t),
+        .bDescriptorType = TUSB_DESC_CONFIGURATION,
+
+        .wTotalLength = sizeof(uvc_cfg_desc_t),
+        .bNumInterfaces = ITF_NUM_TOTAL,
+        .bConfigurationValue = 1,
+        .iConfiguration = 0,
+        .bmAttributes =  TU_BIT(7),
+        .bMaxPower = 100 / 2
+    },
+    .iad = {
+        .bLength = sizeof(tusb_desc_interface_assoc_t),
+        .bDescriptorType = TUSB_DESC_INTERFACE_ASSOCIATION,
+
+        .bFirstInterface = ITF_NUM_VIDEO_CONTROL,
+        .bInterfaceCount = 2,
+        .bFunctionClass = TUSB_CLASS_VIDEO,
+        .bFunctionSubClass = VIDEO_SUBCLASS_INTERFACE_COLLECTION,
+        .bFunctionProtocol = VIDEO_ITF_PROTOCOL_UNDEFINED,
+        .iFunction = 0
+    },
+
+    .video_control = {
+        .itf = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_CONTROL,
+            .bAlternateSetting = 0,
+            .bNumEndpoints = 0,
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_CONTROL,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_CONTROL
+        },
+        .header = {
+            .bLength = sizeof(tusb_desc_video_control_header_1itf_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_HEADER,
+
+            .bcdUVC = VIDEO_BCD_1_50,
+            .wTotalLength = sizeof(uvc_control_desc_t) - sizeof(tusb_desc_interface_t), // CS VC descriptors only
+            .dwClockFrequency = UVC_CLOCK_FREQUENCY,
+            .bInCollection = 1,
+            .baInterfaceNr = { ITF_NUM_VIDEO_STREAMING }
+        },
+        .camera_terminal = {
+            .bLength = sizeof(tusb_desc_video_control_camera_terminal_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_INPUT_TERMINAL,
+
+            .bTerminalID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+            .wTerminalType = VIDEO_ITT_CAMERA,
+            .bAssocTerminal = 0,
+            .iTerminal = 0,
+            .wObjectiveFocalLengthMin = 0,
+            .wObjectiveFocalLengthMax = 0,
+            .wOcularFocalLength = 0,
+            .bControlSize = 3,
+            .bmControls = { 0, 0, 0 }
+        },
+        .output_terminal = {
+            .bLength = sizeof(tusb_desc_video_control_output_terminal_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VC_OUTPUT_TERMINAL,
+
+            .bTerminalID = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+            .wTerminalType = VIDEO_TT_STREAMING,
+            .bAssocTerminal = 0,
+            .bSourceID = UVC_ENTITY_CAP_INPUT_TERMINAL,
+            .iTerminal = 0
+        }
+    },
+
+    .video_streaming = {
+        .itf = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING,
+            .bAlternateSetting = 0,
+            .bNumEndpoints = CFG_TUD_VIDEO_STREAMING_BULK, // bulk 1, iso 0
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_STREAMING
+        },
+        .header = {
+            .bLength = sizeof(tusb_desc_video_streaming_input_header_1byte_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_INPUT_HEADER,
+
+            .bNumFormats = 1,
+            .wTotalLength = sizeof(uvc_streaming_desc_t) - sizeof(tusb_desc_interface_t)
+                - sizeof(tusb_desc_endpoint_t) - (USE_ISO_STREAMING ? sizeof(tusb_desc_interface_t) : 0) , // CS VS descriptors only
+            .bEndpointAddress = EPNUM_VIDEO_IN,
+            .bmInfo = 0,
+            .bTerminalLink = UVC_ENTITY_CAP_OUTPUT_TERMINAL,
+            .bStillCaptureMethod = 0,
+            .bTriggerSupport = 0,
+            .bTriggerUsage = 0,
+            .bControlSize = 1,
+            .bmaControls = { 0 }
+        },
+        .format = {
+#if USE_MJPEG
+            .bLength = sizeof(tusb_desc_video_format_mjpeg_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_MJPEG,
+            .bFormatIndex = 1, // 1-based index
+            .bNumFrameDescriptors = 1,
+            .bmFlags = 0,
+#else
+            .bLength = sizeof(tusb_desc_video_format_uncompressed_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED,
+            .bFormatIndex = 1, // 1-based index
+            .bNumFrameDescriptors = 1,
+            .guidFormat = { TUD_VIDEO_GUID_YUY2 },
+            .bBitsPerPixel = 16,
+#endif
+            .bDefaultFrameIndex = 1,
+            .bAspectRatioX = 0,
+            .bAspectRatioY = 0,
+            .bmInterlaceFlags = 0,
+            .bCopyProtect = 0
+        },
+        .frame = {
+#if USE_MJPEG
+            .bLength = sizeof(tusb_desc_video_frame_mjpeg_continuous_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_MJPEG,
 #else
-# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(4, EPNUM_VIDEO_IN,
-                                            FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                            512)
-# else
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(4, EPNUM_VIDEO_IN,
-                                       FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                       CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
-# endif
+            .bLength = sizeof(tusb_desc_video_frame_uncompressed_continuous_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED,
 #endif
+            .bFrameIndex = 1, // 1-based index
+            .bmCapabilities = 0,
+            .wWidth = FRAME_WIDTH,
+            .wHeight = FRAME_HEIGHT,
+            .dwMinBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * 1,
+            .dwMaxBitRate = FRAME_WIDTH * FRAME_HEIGHT * 16 * FRAME_RATE,
+            .dwMaxVideoFrameBufferSize = FRAME_WIDTH * FRAME_HEIGHT * 16 / 8,
+            .dwDefaultFrameInterval = 10000000 / FRAME_RATE,
+            .bFrameIntervalType = 0, // continuous
+            .dwFrameInterval = {
+                10000000 / FRAME_RATE, // min
+                10000000, // max
+                10000000 / FRAME_RATE // step
+            }
+        },
+        .color = {
+            .bLength = sizeof(tusb_desc_video_streaming_color_matching_t),
+            .bDescriptorType = TUSB_DESC_CS_INTERFACE,
+            .bDescriptorSubType = VIDEO_CS_ITF_VS_COLORFORMAT,
+
+            .bColorPrimaries = VIDEO_COLOR_PRIMARIES_BT709,
+            .bTransferCharacteristics = VIDEO_COLOR_XFER_CH_BT709,
+            .bMatrixCoefficients = VIDEO_COLOR_COEF_SMPTE170M
+        },
+
+#if USE_ISO_STREAMING
+        .itf_alt = {
+            .bLength = sizeof(tusb_desc_interface_t),
+            .bDescriptorType = TUSB_DESC_INTERFACE,
+
+            .bInterfaceNumber = ITF_NUM_VIDEO_STREAMING,
+            .bAlternateSetting = 1,
+            .bNumEndpoints = 1,
+            .bInterfaceClass = TUSB_CLASS_VIDEO,
+            .bInterfaceSubClass = VIDEO_SUBCLASS_STREAMING,
+            .bInterfaceProtocol = VIDEO_ITF_PROTOCOL_15,
+            .iInterface = STRID_UVC_STREAMING
+        },
+#endif
+
+        .ep = {
+            .bLength = sizeof(tusb_desc_endpoint_t),
+            .bDescriptorType = TUSB_DESC_ENDPOINT,
+
+            .bEndpointAddress = EPNUM_VIDEO_IN,
+            .bmAttributes = {
+                .xfer = CFG_TUD_VIDEO_STREAMING_BULK ? TUSB_XFER_BULK : TUSB_XFER_ISOCHRONOUS,
+                .sync = CFG_TUD_VIDEO_STREAMING_BULK ? 0 : 1 // asynchronous
+            },
+            .wMaxPacketSize = CFG_TUD_VIDEO_STREAMING_BULK ? 64 : CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE,
+            .bInterval = 1
+        }
+    }
 };
 
+#if TUD_OPT_HIGH_SPEED
+uvc_cfg_desc_t desc_hs_configuration;
+
+static uint8_t * get_hs_configuration_desc(void) {
+  static bool init = false;
+
+  if (!init) {
+    desc_hs_configuration = desc_fs_configuration;
+    // change endpoint bulk size to 512 if bulk streaming
+    if (CFG_TUD_VIDEO_STREAMING_BULK) {
+      desc_hs_configuration.video_streaming.ep.wMaxPacketSize = 512;
+    }
+  }
+  init = true;
+
+  return (uint8_t *) &desc_hs_configuration;
+}
+
 // device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
-tusb_desc_device_qualifier_t const desc_device_qualifier =
-{
-  .bLength            = sizeof(tusb_desc_device_t),
-  .bDescriptorType    = TUSB_DESC_DEVICE,
-  .bcdUSB             = USB_BCD,
-
-  .bDeviceClass       = TUSB_CLASS_MISC,
-  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
-  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
-
-  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
-  .bNumConfigurations = 0x01,
-  .bReserved          = 0x00
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
+
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved          = 0x00
 };
 
 // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
 // device_qualifier descriptor describes information about a high-speed capable device that would
 // change if the device were operating at the other speed. If not highspeed capable stall this request.
-uint8_t const* tud_descriptor_device_qualifier_cb(void)
-{
+uint8_t const* tud_descriptor_device_qualifier_cb(void) {
   return (uint8_t const*) &desc_device_qualifier;
 }
 
 // Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 // Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
-{
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
-
   // if link speed is high return fullspeed config, and vice versa
-  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_fs_configuration : desc_hs_configuration;
+  if (tud_speed_get() == TUSB_SPEED_HIGH) {
+    return (uint8_t const*) &desc_fs_configuration;
+  } else {
+    return get_hs_configuration_desc();
+  }
 }
-
 #endif // highspeed
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const* tud_descriptor_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
 #if TUD_OPT_HIGH_SPEED
   // Although we are highspeed, host may be fullspeed.
-  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
-#else
-  return desc_fs_configuration;
+  if (tud_speed_get() == TUSB_SPEED_HIGH) {
+    return get_hs_configuration_desc();
+  } else
 #endif
+  {
+    return (uint8_t const*) &desc_fs_configuration;
+  }
 }
 
 //--------------------------------------------------------------------+
 // String Descriptors
 //--------------------------------------------------------------------+
 
-// String Descriptor Index
-enum {
-  STRID_LANGID = 0,
-  STRID_MANUFACTURER,
-  STRID_PRODUCT,
-  STRID_SERIAL,
-};
-
-// array of pointer to string descriptors
-char const *string_desc_arr[] =
-{
-  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
-  "TinyUSB",                     // 1: Manufacturer
-  "TinyUSB Device",              // 2: Product
-  NULL,                          // 3: Serials will use unique ID if possible
-  "TinyUSB UVC",                 // 4: UVC Interface
-};
-
 static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
   size_t chr_count;
 
-  switch ( index ) {
+  switch (index) {
     case STRID_LANGID:
       memcpy(&_desc_str[1], string_desc_arr[0], 2);
       chr_count = 1;
@@ -269,17 +461,17 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
       // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
       // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
+      if (index >= sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) return NULL;
 
-      const char *str = string_desc_arr[index];
+      const char* str = string_desc_arr[index];
 
       // Cap at max char
       chr_count = strlen(str);
       size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
-      if ( chr_count > max_count ) chr_count = max_count;
+      if (chr_count > max_count) chr_count = max_count;
 
       // Convert ASCII string into UTF-16
-      for ( size_t i = 0; i < chr_count; i++ ) {
+      for (size_t i = 0; i < chr_count; i++) {
         _desc_str[1 + i] = str[i];
       }
       break;
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index b924c8dbe..12d41b2f3 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -27,21 +27,11 @@
 #ifndef _USB_DESCRIPTORS_H_
 #define _USB_DESCRIPTORS_H_
 
-/* Time stamp base clock. It is a deprecated parameter. */
-#define UVC_CLOCK_FREQUENCY    27000000
-/* video capture path */
-#define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
-#define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
-
 #define FRAME_WIDTH   128
 #define FRAME_HEIGHT  96
 #define FRAME_RATE    10
 
-enum {
-  ITF_NUM_VIDEO_CONTROL,
-  ITF_NUM_VIDEO_STREAMING,
-  ITF_NUM_TOTAL
-};
+// NOTE: descriptor template is not used but leave here as reference
 
 #define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN (\
     TUD_VIDEO_DESC_IAD_LEN\
@@ -126,23 +116,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                  \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -152,7 +136,7 @@ enum {
         /* Video stream frame format */ \
         TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
-            _width * _height * 16, \
+            _width * _height * 16 / 8, \
             (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
   /* VS alt 1 */\
@@ -163,23 +147,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -202,22 +180,17 @@ enum {
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
   TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
         /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
@@ -227,7 +200,7 @@ enum {
         /* Video stream frame format */ \
         TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
-            _width * _height * 16, \
+            _width * _height * 16 / 8, \
             (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
         TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
@@ -235,23 +208,17 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
-  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-         /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
-      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
-                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
-                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
-      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx),                                     \
+    /* Header: UVC 1.5, length of followed descs, clock (deprecated), streaming interfaces */ \
+    TUD_VIDEO_DESC_CS_VC(0x0150, TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      /* Camera Terminal: ID, bAssocTerminal, iTerminal, focal min, max, length, bmControl */ \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0, 0, 0, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, UVC_ENTITY_CAP_INPUT_TERMINAL, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-        /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
-        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        /*wTotalLength - bLength */ TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index a1b26e49c..e275e7943 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -27,20 +27,11 @@
 #include "tusb.h"
 #include "bsp/board_api.h"
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-
-//------------- IMPLEMENTATION -------------//
-
-size_t get_console_inputs(uint8_t* buf, size_t bufsize)
-{
+size_t get_console_inputs(uint8_t* buf, size_t bufsize) {
   size_t count = 0;
-  while (count < bufsize)
-  {
+  while (count < bufsize) {
     int ch = board_getchar();
-    if ( ch <= 0 ) break;
+    if (ch <= 0) break;
 
     buf[count] = (uint8_t) ch;
     count++;
@@ -49,22 +40,18 @@ size_t get_console_inputs(uint8_t* buf, size_t bufsize)
   return count;
 }
 
-void cdc_app_task(void)
-{
-  uint8_t buf[64+1]; // +1 for extra null character
-  uint32_t const bufsize = sizeof(buf)-1;
+void cdc_app_task(void) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
 
   uint32_t count = get_console_inputs(buf, bufsize);
   buf[count] = 0;
 
   // loop over all mounted interfaces
-  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
-  {
-    if ( tuh_cdc_mounted(idx) )
-    {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+    if (tuh_cdc_mounted(idx)) {
       // console --> cdc interfaces
-      if (count)
-      {
+      if (count) {
         tuh_cdc_write(idx, buf, count);
         tuh_cdc_write_flush(idx);
       }
@@ -72,11 +59,14 @@ void cdc_app_task(void)
   }
 }
 
+//--------------------------------------------------------------------+
+// TinyUSB callbacks
+//--------------------------------------------------------------------+
+
 // Invoked when received new data
-void tuh_cdc_rx_cb(uint8_t idx)
-{
-  uint8_t buf[64+1]; // +1 for extra null character
-  uint32_t const bufsize = sizeof(buf)-1;
+void tuh_cdc_rx_cb(uint8_t idx) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
 
   // forward cdc interfaces -> console
   uint32_t count = tuh_cdc_read(idx, buf, bufsize);
@@ -85,29 +75,35 @@ void tuh_cdc_rx_cb(uint8_t idx)
   printf((char*) buf);
 }
 
-void tuh_cdc_mount_cb(uint8_t idx)
-{
-  tuh_itf_info_t itf_info = { 0 };
+// Invoked when a device with CDC interface is mounted
+// idx is index of cdc interface in the internal pool.
+void tuh_cdc_mount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
 
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-  // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
-  // otherwise you need to call tuh_cdc_set_line_coding() first
-  cdc_line_coding_t line_coding = { 0 };
-  if ( tuh_cdc_get_local_line_coding(idx, &line_coding) )
-  {
+  // If CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined, line coding will be set by tinyusb stack
+  // while eneumerating new cdc device
+  cdc_line_coding_t line_coding = {0};
+  if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
     printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
-    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity  , line_coding.data_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
   }
+#else
+  // Set Line Coding upon mounted
+  cdc_line_coding_t new_line_coding = { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 };
+  tuh_cdc_set_line_coding(idx, &new_line_coding, NULL, 0);
 #endif
 }
 
-void tuh_cdc_umount_cb(uint8_t idx)
-{
-  tuh_itf_info_t itf_info = { 0 };
+// Invoked when a device with CDC interface is unmounted
+void tuh_cdc_umount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = {0};
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr,
+         itf_info.desc.bInterfaceNumber);
 }
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 61abb85eb..76d59c316 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -105,6 +105,7 @@
 #define CFG_TUH_CDC                 1 // CDC ACM
 #define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index c661f47be..bb7c3388d 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -110,6 +110,7 @@
 #define CFG_TUH_CDC                 1 // CDC ACM
 #define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CH34X           1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index 404509a28..0c8a35924 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -33,9 +33,26 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
-
 #include "tusb.h"
 
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+#else
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+#endif
+#endif
+
 // Define the default baudrate
 #ifndef CFG_BOARD_UART_BAUDRATE
 #define CFG_BOARD_UART_BAUDRATE 115200   ///< Default baud rate
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 325e9ab0f..5599d1504 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -33,7 +33,7 @@
 #include "hal/usb_hal.h"
 #include "soc/usb_periph.h"
 
-#include "driver/rmt.h"
+#include "driver/gpio.h"
 #include "driver/uart.h"
 
 #if ESP_IDF_VERSION_MAJOR > 4
@@ -48,7 +48,7 @@
 
 #ifdef NEOPIXEL_PIN
 #include "led_strip.h"
-static led_strip_t* strip;
+static led_strip_handle_t led_strip;
 #endif
 
 #if CFG_TUH_ENABLED && CFG_TUH_MAX3421
@@ -85,15 +85,23 @@ void board_init(void) {
   #endif
 
   // WS2812 Neopixel driver with RMT peripheral
-  rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
-  config.clk_div = 2; // set counter clock to 40MHz
+  led_strip_rmt_config_t rmt_config = {
+      .clk_src = RMT_CLK_SRC_DEFAULT, // different clock source can lead to different power consumption
+      .resolution_hz = 10 * 1000 * 1000,  // RMT counter clock frequency, default = 10 Mhz
+      .flags.with_dma = false,        // DMA feature is available on ESP target like ESP32-S3
+  };
+
+  led_strip_config_t strip_config = {
+      .strip_gpio_num = NEOPIXEL_PIN,           // The GPIO that connected to the LED strip's data line
+      .max_leds = 1,                            // The number of LEDs in the strip,
+      .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+      .led_model = LED_MODEL_WS2812,            // LED strip model
+      .flags.invert_out = false,                // whether to invert the output signal
+  };
 
-  rmt_config(&config);
-  rmt_driver_install(config.channel, 0, 0);
+  ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
 
-  led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
-  strip = led_strip_new_rmt_ws2812(&strip_config);
-  strip->clear(strip, 100); // off led
+  led_strip_clear(led_strip); // off
 #endif
 
   // Button
@@ -158,8 +166,8 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) {
 
 void board_led_write(bool state) {
 #ifdef NEOPIXEL_PIN
-  strip->set_pixel(strip, 0, state ? 0x08 : 0x00, 0x00, 0x00);
-  strip->refresh(strip, 100);
+  led_strip_set_pixel(led_strip, 0, state ? 0x08 : 0x00, 0x00, 0x00);
+  led_strip_refresh(led_strip);
 #endif
 }
 
diff --git a/hw/bsp/espressif/components/led_strip/CHANGELOG.md b/hw/bsp/espressif/components/led_strip/CHANGELOG.md
new file mode 100644
index 000000000..51c0cd30c
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/CHANGELOG.md
@@ -0,0 +1,38 @@
+## 2.5.0
+
+- Enabled support for IDF4.4 and above
+  - with RMT backend only
+- Added API `led_strip_set_pixel_hsv`
+
+## 2.4.0
+
+- Support configurable SPI mode to control leds
+  - recommend enabling DMA when using SPI mode
+
+## 2.3.0
+
+- Support configurable RMT channel size by setting `mem_block_symbols`
+
+## 2.2.0
+
+- Support for 4 components RGBW leds (SK6812):
+  - in led_strip_config_t new fields
+      led_pixel_format, controlling byte format (LED_PIXEL_FORMAT_GRB, LED_PIXEL_FORMAT_GRBW)
+      led_model, used to configure bit timing (LED_MODEL_WS2812, LED_MODEL_SK6812)
+  - new API led_strip_set_pixel_rgbw
+  - new interface type set_pixel_rgbw
+
+## 2.1.0
+
+- Support DMA feature, which offloads the CPU by a lot when it comes to drive a bunch of LEDs
+- Support various RMT clock sources
+- Acquire and release the power management lock before and after each refresh
+- New driver flag: `invert_out` which can invert the led control signal by hardware
+
+## 2.0.0
+
+- Reimplemented the driver using the new RMT driver (`driver/rmt_tx.h`)
+
+## 1.0.0
+
+- Initial driver version, based on the legacy RMT driver (`driver/rmt.h`)
diff --git a/hw/bsp/espressif/components/led_strip/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/CMakeLists.txt
index 8266c5a1c..15de610cc 100644
--- a/hw/bsp/espressif/components/led_strip/CMakeLists.txt
+++ b/hw/bsp/espressif/components/led_strip/CMakeLists.txt
@@ -1,7 +1,22 @@
-set(component_srcs "src/led_strip_rmt_ws2812.c")
+include($ENV{IDF_PATH}/tools/cmake/version.cmake)
 
-idf_component_register(SRCS "${component_srcs}"
-                       INCLUDE_DIRS "include"
-                       PRIV_INCLUDE_DIRS ""
-                       PRIV_REQUIRES "driver"
-                       REQUIRES "")
+set(srcs "src/led_strip_api.c")
+
+if("${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}" VERSION_GREATER_EQUAL "5.0")
+    if(CONFIG_SOC_RMT_SUPPORTED)
+        list(APPEND srcs "src/led_strip_rmt_dev.c" "src/led_strip_rmt_encoder.c")
+    endif()
+else()
+    list(APPEND srcs "src/led_strip_rmt_dev_idf4.c")
+endif()
+
+# the SPI backend driver relies on something that was added in IDF 5.1
+if("${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}" VERSION_GREATER_EQUAL "5.1")
+    if(CONFIG_SOC_GPSPI_SUPPORTED)
+        list(APPEND srcs "src/led_strip_spi_dev.c")
+    endif()
+endif()
+
+idf_component_register(SRCS ${srcs}
+                       INCLUDE_DIRS "include" "interface"
+                       REQUIRES "driver")
diff --git a/hw/bsp/espressif/components/led_strip/LICENSE b/hw/bsp/espressif/components/led_strip/LICENSE
new file mode 100644
index 000000000..d64569567
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/LICENSE
@@ -0,0 +1,202 @@
+
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diff --git a/hw/bsp/espressif/components/led_strip/README.md b/hw/bsp/espressif/components/led_strip/README.md
new file mode 100644
index 000000000..543d29642
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/README.md
@@ -0,0 +1,97 @@
+# LED Strip Driver
+
+[![Component Registry](https://components.espressif.com/components/espressif/led_strip/badge.svg)](https://components.espressif.com/components/espressif/led_strip)
+
+This driver is designed for addressable LEDs like [WS2812](http://www.world-semi.com/Certifications/WS2812B.html), where each LED is controlled by a single data line.
+
+## Backend Controllers
+
+### The [RMT](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/rmt.html) Peripheral
+
+This is the most economical way to drive the LEDs because it only consumes one RMT channel, leaving other channels free to use. However, the memory usage increases dramatically with the number of LEDs. If the RMT hardware can't be assist by DMA, the driver will going into interrupt very frequently, thus result in a high CPU usage. What's worse, if the RMT interrupt is delayed or not serviced in time (e.g. if Wi-Fi interrupt happens on the same CPU core), the RMT transaction will be corrupted and the LEDs will display incorrect colors. If you want to use RMT to drive a large number of LEDs, you'd better to enable the DMA feature if possible [^1].
+
+#### Allocate LED Strip Object with RMT Backend
+
+```c
+#define BLINK_GPIO 0
+
+led_strip_handle_t led_strip;
+
+/* LED strip initialization with the GPIO and pixels number*/
+led_strip_config_t strip_config = {
+    .strip_gpio_num = BLINK_GPIO, // The GPIO that connected to the LED strip's data line
+    .max_leds = 1, // The number of LEDs in the strip,
+    .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+    .led_model = LED_MODEL_WS2812, // LED strip model
+    .flags.invert_out = false, // whether to invert the output signal (useful when your hardware has a level inverter)
+};
+
+led_strip_rmt_config_t rmt_config = {
+#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 0, 0)
+    .rmt_channel = 0,
+#else
+    .clk_src = RMT_CLK_SRC_DEFAULT, // different clock source can lead to different power consumption
+    .resolution_hz = 10 * 1000 * 1000, // 10MHz
+    .flags.with_dma = false, // whether to enable the DMA feature
+#endif
+};
+ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
+```
+
+You can create multiple LED strip objects with different GPIOs and pixel numbers. The backend driver will automatically allocate the RMT channel for you if there is more available.
+
+### The [SPI](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/spi_master.html) Peripheral
+
+SPI peripheral can also be used to generate the timing required by the LED strip. However this backend is not as economical as the RMT one, because it will take up the whole **bus**, unlike the RMT just takes one **channel**. You **CAN'T** connect other devices to the same SPI bus if it's been used by the led_strip, because the led_strip doesn't have the concept of "Chip Select".
+
+Please note, the SPI backend has a dependency of **ESP-IDF >= 5.1**
+
+#### Allocate LED Strip Object with SPI Backend
+
+```c
+#define BLINK_GPIO 0
+
+led_strip_handle_t led_strip;
+
+/* LED strip initialization with the GPIO and pixels number*/
+led_strip_config_t strip_config = {
+    .strip_gpio_num = BLINK_GPIO, // The GPIO that connected to the LED strip's data line
+    .max_leds = 1, // The number of LEDs in the strip,
+    .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+    .led_model = LED_MODEL_WS2812, // LED strip model
+    .flags.invert_out = false, // whether to invert the output signal (useful when your hardware has a level inverter)
+};
+
+led_strip_spi_config_t spi_config = {
+    .clk_src = SPI_CLK_SRC_DEFAULT, // different clock source can lead to different power consumption
+    .flags.with_dma = true, // Using DMA can improve performance and help drive more LEDs
+    .spi_bus = SPI2_HOST,   // SPI bus ID
+};
+ESP_ERROR_CHECK(led_strip_new_spi_device(&strip_config, &spi_config, &led_strip));
+```
+
+The number of LED strip objects can be created depends on how many free SPI buses are free to use in your project.
+
+## FAQ
+
+* Which led_strip backend should I choose?
+  * It depends on your application requirement and target chip's ability.
+
+    ```mermaid
+    flowchart LR
+    A{Is RMT supported?}
+    A --> |No| B[SPI backend]
+    B --> C{Does the led strip has \n a larger number of LEDs?}
+    C --> |No| D[Don't have to enable the DMA of the backend]
+    C --> |Yes| E[Enable the DMA of the backend]
+    A --> |Yes| F{Does the led strip has \n a larger number of LEDs?}
+    F --> |Yes| G{Does RMT support DMA?}
+    G --> |Yes| E
+    G --> |No| B
+    F --> |No| H[RMT backend] --> D
+    ```
+
+* How to set the brightness of the LED strip?
+  * You can tune the brightness by scaling the value of each R-G-B element with a **same** factor. But pay attention to the overflow of the value.
+
+[^1]: The RMT DMA feature is not available on all ESP chips. Please check the data sheet before using it.
diff --git a/hw/bsp/espressif/components/led_strip/api.md b/hw/bsp/espressif/components/led_strip/api.md
new file mode 100644
index 000000000..6581d6604
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/api.md
@@ -0,0 +1,454 @@
+# API Reference
+
+## Header files
+
+- [include/led_strip.h](#file-includeled_striph)
+- [include/led_strip_rmt.h](#file-includeled_strip_rmth)
+- [include/led_strip_spi.h](#file-includeled_strip_spih)
+- [include/led_strip_types.h](#file-includeled_strip_typesh)
+- [interface/led_strip_interface.h](#file-interfaceled_strip_interfaceh)
+
+## File include/led_strip.h
+
+## Functions
+
+| Type | Name |
+| ---: | :--- |
+|  esp\_err\_t | [**led\_strip\_clear**](#function-led_strip_clear) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip) <br>_Clear LED strip (turn off all LEDs)_ |
+|  esp\_err\_t | [**led\_strip\_del**](#function-led_strip_del) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip) <br>_Free LED strip resources._ |
+|  esp\_err\_t | [**led\_strip\_refresh**](#function-led_strip_refresh) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip) <br>_Refresh memory colors to LEDs._ |
+|  esp\_err\_t | [**led\_strip\_set\_pixel**](#function-led_strip_set_pixel) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip, uint32\_t index, uint32\_t red, uint32\_t green, uint32\_t blue) <br>_Set RGB for a specific pixel._ |
+|  esp\_err\_t | [**led\_strip\_set\_pixel\_hsv**](#function-led_strip_set_pixel_hsv) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip, uint32\_t index, uint16\_t hue, uint8\_t saturation, uint8\_t value) <br>_Set HSV for a specific pixel._ |
+|  esp\_err\_t | [**led\_strip\_set\_pixel\_rgbw**](#function-led_strip_set_pixel_rgbw) ([**led\_strip\_handle\_t**](#struct-led_strip_t) strip, uint32\_t index, uint32\_t red, uint32\_t green, uint32\_t blue, uint32\_t white) <br>_Set RGBW for a specific pixel._ |
+
+## Functions Documentation
+
+### function `led_strip_clear`
+
+_Clear LED strip (turn off all LEDs)_
+
+```c
+esp_err_t led_strip_clear (
+    led_strip_handle_t strip
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Clear LEDs successfully
+- ESP\_FAIL: Clear LEDs failed because some other error occurred
+
+### function `led_strip_del`
+
+_Free LED strip resources._
+
+```c
+esp_err_t led_strip_del (
+    led_strip_handle_t strip
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Free resources successfully
+- ESP\_FAIL: Free resources failed because error occurred
+
+### function `led_strip_refresh`
+
+_Refresh memory colors to LEDs._
+
+```c
+esp_err_t led_strip_refresh (
+    led_strip_handle_t strip
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Refresh successfully
+- ESP\_FAIL: Refresh failed because some other error occurred
+
+**Note:**
+
+: After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+
+### function `led_strip_set_pixel`
+
+_Set RGB for a specific pixel._
+
+```c
+esp_err_t led_strip_set_pixel (
+    led_strip_handle_t strip,
+    uint32_t index,
+    uint32_t red,
+    uint32_t green,
+    uint32_t blue
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+
+**Returns:**
+
+- ESP\_OK: Set RGB for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGB for a specific pixel failed because of invalid parameters
+- ESP\_FAIL: Set RGB for a specific pixel failed because other error occurred
+
+### function `led_strip_set_pixel_hsv`
+
+_Set HSV for a specific pixel._
+
+```c
+esp_err_t led_strip_set_pixel_hsv (
+    led_strip_handle_t strip,
+    uint32_t index,
+    uint16_t hue,
+    uint8_t saturation,
+    uint8_t value
+)
+```
+
+**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `hue` hue part of color (0 - 360)
+- `saturation` saturation part of color (0 - 255)
+- `value` value part of color (0 - 255)
+
+**Returns:**
+
+- ESP\_OK: Set HSV color for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set HSV color for a specific pixel failed because of an invalid argument
+- ESP\_FAIL: Set HSV color for a specific pixel failed because other error occurred
+
+### function `led_strip_set_pixel_rgbw`
+
+_Set RGBW for a specific pixel._
+
+```c
+esp_err_t led_strip_set_pixel_rgbw (
+    led_strip_handle_t strip,
+    uint32_t index,
+    uint32_t red,
+    uint32_t green,
+    uint32_t blue,
+    uint32_t white
+)
+```
+
+**Note:**
+
+Only call this function if your led strip does have the white component (e.g. SK6812-RGBW)
+
+**Note:**
+
+Also see `led_strip_set_pixel` if you only want to specify the RGB part of the color and bypass the white component
+
+**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+- `white` separate white component
+
+**Returns:**
+
+- ESP\_OK: Set RGBW color for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+- ESP\_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+
+## File include/led_strip_rmt.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| struct | [**led\_strip\_rmt\_config\_t**](#struct-led_strip_rmt_config_t) <br>_LED Strip RMT specific configuration._ |
+
+## Functions
+
+| Type | Name |
+| ---: | :--- |
+|  esp\_err\_t | [**led\_strip\_new\_rmt\_device**](#function-led_strip_new_rmt_device) (const [**led\_strip\_config\_t**](#struct-led_strip_config_t) \*led\_config, const [**led\_strip\_rmt\_config\_t**](#struct-led_strip_rmt_config_t) \*rmt\_config, [**led\_strip\_handle\_t**](#struct-led_strip_t) \*ret\_strip) <br>_Create LED strip based on RMT TX channel._ |
+
+## Structures and Types Documentation
+
+### struct `led_strip_rmt_config_t`
+
+_LED Strip RMT specific configuration._
+
+Variables:
+
+- rmt\_clock\_source\_t clk_src  <br>RMT clock source
+
+- struct [**led\_strip\_rmt\_config\_t**](#struct-led_strip_rmt_config_t) flags  <br>Extra driver flags
+
+- size\_t mem_block_symbols  <br>How many RMT symbols can one RMT channel hold at one time. Set to 0 will fallback to use the default size.
+
+- uint32\_t resolution_hz  <br>RMT tick resolution, if set to zero, a default resolution (10MHz) will be applied
+
+- uint32\_t with_dma  <br>Use DMA to transmit data
+
+## Functions Documentation
+
+### function `led_strip_new_rmt_device`
+
+_Create LED strip based on RMT TX channel._
+
+```c
+esp_err_t led_strip_new_rmt_device (
+    const led_strip_config_t *led_config,
+    const led_strip_rmt_config_t *rmt_config,
+    led_strip_handle_t *ret_strip
+)
+```
+
+**Parameters:**
+
+- `led_config` LED strip configuration
+- `rmt_config` RMT specific configuration
+- `ret_strip` Returned LED strip handle
+
+**Returns:**
+
+- ESP\_OK: create LED strip handle successfully
+- ESP\_ERR\_INVALID\_ARG: create LED strip handle failed because of invalid argument
+- ESP\_ERR\_NO\_MEM: create LED strip handle failed because of out of memory
+- ESP\_FAIL: create LED strip handle failed because some other error
+
+## File include/led_strip_spi.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| struct | [**led\_strip\_spi\_config\_t**](#struct-led_strip_spi_config_t) <br>_LED Strip SPI specific configuration._ |
+
+## Functions
+
+| Type | Name |
+| ---: | :--- |
+|  esp\_err\_t | [**led\_strip\_new\_spi\_device**](#function-led_strip_new_spi_device) (const [**led\_strip\_config\_t**](#struct-led_strip_config_t) \*led\_config, const [**led\_strip\_spi\_config\_t**](#struct-led_strip_spi_config_t) \*spi\_config, [**led\_strip\_handle\_t**](#struct-led_strip_t) \*ret\_strip) <br>_Create LED strip based on SPI MOSI channel._ |
+
+## Structures and Types Documentation
+
+### struct `led_strip_spi_config_t`
+
+_LED Strip SPI specific configuration._
+
+Variables:
+
+- spi\_clock\_source\_t clk_src  <br>SPI clock source
+
+- struct [**led\_strip\_spi\_config\_t**](#struct-led_strip_spi_config_t) flags  <br>Extra driver flags
+
+- spi\_host\_device\_t spi_bus  <br>SPI bus ID. Which buses are available depends on the specific chip
+
+- uint32\_t with_dma  <br>Use DMA to transmit data
+
+## Functions Documentation
+
+### function `led_strip_new_spi_device`
+
+_Create LED strip based on SPI MOSI channel._
+
+```c
+esp_err_t led_strip_new_spi_device (
+    const led_strip_config_t *led_config,
+    const led_strip_spi_config_t *spi_config,
+    led_strip_handle_t *ret_strip
+)
+```
+
+**Note:**
+
+Although only the MOSI line is used for generating the signal, the whole SPI bus can't be used for other purposes.
+
+**Parameters:**
+
+- `led_config` LED strip configuration
+- `spi_config` SPI specific configuration
+- `ret_strip` Returned LED strip handle
+
+**Returns:**
+
+- ESP\_OK: create LED strip handle successfully
+- ESP\_ERR\_INVALID\_ARG: create LED strip handle failed because of invalid argument
+- ESP\_ERR\_NOT\_SUPPORTED: create LED strip handle failed because of unsupported configuration
+- ESP\_ERR\_NO\_MEM: create LED strip handle failed because of out of memory
+- ESP\_FAIL: create LED strip handle failed because some other error
+
+## File include/led_strip_types.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| enum  | [**led\_model\_t**](#enum-led_model_t)  <br>_LED strip model._ |
+| enum  | [**led\_pixel\_format\_t**](#enum-led_pixel_format_t)  <br>_LED strip pixel format._ |
+| struct | [**led\_strip\_config\_t**](#struct-led_strip_config_t) <br>_LED Strip Configuration._ |
+| typedef struct [**led\_strip\_t**](#struct-led_strip_t) \* | [**led\_strip\_handle\_t**](#typedef-led_strip_handle_t)  <br>_LED strip handle._ |
+
+## Structures and Types Documentation
+
+### enum `led_model_t`
+
+_LED strip model._
+
+```c
+enum led_model_t {
+    LED_MODEL_WS2812,
+    LED_MODEL_SK6812,
+    LED_MODEL_INVALID
+};
+```
+
+**Note:**
+
+Different led model may have different timing parameters, so we need to distinguish them.
+
+### enum `led_pixel_format_t`
+
+_LED strip pixel format._
+
+```c
+enum led_pixel_format_t {
+    LED_PIXEL_FORMAT_GRB,
+    LED_PIXEL_FORMAT_GRBW,
+    LED_PIXEL_FORMAT_INVALID
+};
+```
+
+### struct `led_strip_config_t`
+
+_LED Strip Configuration._
+
+Variables:
+
+- struct [**led\_strip\_config\_t**](#struct-led_strip_config_t) flags  <br>Extra driver flags
+
+- uint32\_t invert_out  <br>Invert output signal
+
+- led\_model\_t led_model  <br>LED model
+
+- led\_pixel\_format\_t led_pixel_format  <br>LED pixel format
+
+- uint32\_t max_leds  <br>Maximum LEDs in a single strip
+
+- int strip_gpio_num  <br>GPIO number that used by LED strip
+
+### typedef `led_strip_handle_t`
+
+_LED strip handle._
+
+```c
+typedef struct led_strip_t* led_strip_handle_t;
+```
+
+## File interface/led_strip_interface.h
+
+## Structures and Types
+
+| Type | Name |
+| ---: | :--- |
+| struct | [**led\_strip\_t**](#struct-led_strip_t) <br>_LED strip interface definition._ |
+| typedef struct [**led\_strip\_t**](#struct-led_strip_t) | [**led\_strip\_t**](#typedef-led_strip_t)  <br> |
+
+## Structures and Types Documentation
+
+### struct `led_strip_t`
+
+_LED strip interface definition._
+
+Variables:
+
+- esp\_err\_t(\* clear  <br>_Clear LED strip (turn off all LEDs)_<br>**Parameters:**
+
+- `strip` LED strip
+- `timeout_ms` timeout value for clearing task
+
+**Returns:**
+
+- ESP\_OK: Clear LEDs successfully
+- ESP\_FAIL: Clear LEDs failed because some other error occurred
+
+- esp\_err\_t(\* del  <br>_Free LED strip resources._<br>**Parameters:**
+
+- `strip` LED strip
+
+**Returns:**
+
+- ESP\_OK: Free resources successfully
+- ESP\_FAIL: Free resources failed because error occurred
+
+- esp\_err\_t(\* refresh  <br>_Refresh memory colors to LEDs._<br>**Parameters:**
+
+- `strip` LED strip
+- `timeout_ms` timeout value for refreshing task
+
+**Returns:**
+
+- ESP\_OK: Refresh successfully
+- ESP\_FAIL: Refresh failed because some other error occurred
+
+**Note:**
+
+: After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+
+- esp\_err\_t(\* set_pixel  <br>_Set RGB for a specific pixel._<br>**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+
+**Returns:**
+
+- ESP\_OK: Set RGB for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGB for a specific pixel failed because of invalid parameters
+- ESP\_FAIL: Set RGB for a specific pixel failed because other error occurred
+
+- esp\_err\_t(\* set_pixel_rgbw  <br>_Set RGBW for a specific pixel. Similar to_ `set_pixel`_but also set the white component._<br>**Parameters:**
+
+- `strip` LED strip
+- `index` index of pixel to set
+- `red` red part of color
+- `green` green part of color
+- `blue` blue part of color
+- `white` separate white component
+
+**Returns:**
+
+- ESP\_OK: Set RGBW color for a specific pixel successfully
+- ESP\_ERR\_INVALID\_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+- ESP\_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+
+### typedef `led_strip_t`
+
+```c
+typedef struct led_strip_t led_strip_t;
+```
+
+Type of LED strip
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/CMakeLists.txt
new file mode 100644
index 000000000..923c46310
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/CMakeLists.txt
@@ -0,0 +1,9 @@
+# For more information about build system see
+# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+set(IDF_TARGET "esp32s3")
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(led_strip_rmt_ws2812)
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/README.md b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/README.md
new file mode 100644
index 000000000..ad52235d5
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/README.md
@@ -0,0 +1,31 @@
+# LED Strip Example (RMT backend + WS2812)
+
+This example demonstrates how to blink the WS2812 LED using the [led_strip](https://components.espressif.com/component/espressif/led_strip) component.
+
+## How to Use Example
+
+### Hardware Required
+
+* A development board with Espressif SoC
+* A USB cable for Power supply and programming
+* WS2812 LED strip
+
+### Configure the Example
+
+Before project configuration and build, be sure to set the correct chip target using `idf.py set-target <chip_name>`. Then assign the proper GPIO in the [source file](main/led_strip_rmt_ws2812_main.c). If your led strip has multiple LEDs, don't forget update the number.
+
+### Build and Flash
+
+Run `idf.py -p PORT build flash monitor` to build, flash and monitor the project.
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.
+
+## Example Output
+
+```text
+I (299) gpio: GPIO[8]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
+I (309) example: Created LED strip object with RMT backend
+I (309) example: Start blinking LED strip
+```
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/dependencies.lock b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/dependencies.lock
new file mode 100644
index 000000000..97840a153
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/dependencies.lock
@@ -0,0 +1,15 @@
+dependencies:
+  espressif/led_strip:
+    component_hash: null
+    source:
+      path: /home/hathach/code/idf-extra-components/led_strip
+      type: local
+    version: 2.5.2
+  idf:
+    component_hash: null
+    source:
+      type: idf
+    version: 5.1.1
+manifest_hash: 47d47762be26168b388cb0e6cbfee6b22c68d630ebf4b27a49c47c4c54191590
+target: esp32s3
+version: 1.0.0
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/CMakeLists.txt
new file mode 100644
index 000000000..37b9c1458
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "led_strip_rmt_ws2812_main.c"
+                       INCLUDE_DIRS ".")
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/idf_component.yml b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/idf_component.yml
new file mode 100644
index 000000000..916c366c7
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/idf_component.yml
@@ -0,0 +1,5 @@
+## IDF Component Manager Manifest File
+dependencies:
+  espressif/led_strip:
+    version: '^2'
+    override_path: '../../../'
diff --git a/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/led_strip_rmt_ws2812_main.c b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/led_strip_rmt_ws2812_main.c
new file mode 100644
index 000000000..4b20a5958
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/examples/led_strip_rmt_ws2812/main/led_strip_rmt_ws2812_main.c
@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include <stdio.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "led_strip.h"
+#include "esp_log.h"
+#include "esp_err.h"
+
+// GPIO assignment
+#define LED_STRIP_BLINK_GPIO  48
+// Numbers of the LED in the strip
+#define LED_STRIP_LED_NUMBERS 1
+// 10MHz resolution, 1 tick = 0.1us (led strip needs a high resolution)
+#define LED_STRIP_RMT_RES_HZ  (10 * 1000 * 1000)
+
+static const char *TAG = "example";
+
+led_strip_handle_t configure_led(void)
+{
+    // LED strip general initialization, according to your led board design
+    led_strip_config_t strip_config = {
+        .strip_gpio_num = LED_STRIP_BLINK_GPIO,   // The GPIO that connected to the LED strip's data line
+        .max_leds = LED_STRIP_LED_NUMBERS,        // The number of LEDs in the strip,
+        .led_pixel_format = LED_PIXEL_FORMAT_GRB, // Pixel format of your LED strip
+        .led_model = LED_MODEL_WS2812,            // LED strip model
+        .flags.invert_out = false,                // whether to invert the output signal
+    };
+
+    // LED strip backend configuration: RMT
+    led_strip_rmt_config_t rmt_config = {
+#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 0, 0)
+        .rmt_channel = 0,
+#else
+        .clk_src = RMT_CLK_SRC_DEFAULT,        // different clock source can lead to different power consumption
+        .resolution_hz = LED_STRIP_RMT_RES_HZ, // RMT counter clock frequency
+        .flags.with_dma = false,               // DMA feature is available on ESP target like ESP32-S3
+#endif
+    };
+
+    // LED Strip object handle
+    led_strip_handle_t led_strip;
+    ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
+    ESP_LOGI(TAG, "Created LED strip object with RMT backend");
+    return led_strip;
+}
+
+void app_main(void)
+{
+    led_strip_handle_t led_strip = configure_led();
+    bool led_on_off = false;
+
+    ESP_LOGI(TAG, "Start blinking LED strip");
+    while (1) {
+        if (led_on_off) {
+            /* Set the LED pixel using RGB from 0 (0%) to 255 (100%) for each color */
+            for (int i = 0; i < LED_STRIP_LED_NUMBERS; i++) {
+                ESP_ERROR_CHECK(led_strip_set_pixel(led_strip, i, 5, 5, 5));
+            }
+            /* Refresh the strip to send data */
+            ESP_ERROR_CHECK(led_strip_refresh(led_strip));
+            ESP_LOGI(TAG, "LED ON!");
+        } else {
+            /* Set all LED off to clear all pixels */
+            ESP_ERROR_CHECK(led_strip_clear(led_strip));
+            ESP_LOGI(TAG, "LED OFF!");
+        }
+
+        led_on_off = !led_on_off;
+        vTaskDelay(pdMS_TO_TICKS(500));
+    }
+}
diff --git a/hw/bsp/espressif/components/led_strip/idf_component.yml b/hw/bsp/espressif/components/led_strip/idf_component.yml
new file mode 100644
index 000000000..1fd9b83ee
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/idf_component.yml
@@ -0,0 +1,5 @@
+version: "2.5.2"
+description: Driver for Addressable LED Strip (WS2812, etc)
+url: https://github.com/espressif/idf-extra-components/tree/master/led_strip
+dependencies:
+  idf: ">=4.4"
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip.h b/hw/bsp/espressif/components/led_strip/include/led_strip.h
index a9dffc325..38711744a 100644
--- a/hw/bsp/espressif/components/led_strip/include/led_strip.h
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip.h
@@ -1,125 +1,110 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
+#include <stdint.h>
+#include "esp_err.h"
+#include "led_strip_rmt.h"
+#include "esp_idf_version.h"
+
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 0)
+#include "led_strip_spi.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "esp_err.h"
-
 /**
-* @brief LED Strip Type
-*
-*/
-typedef struct led_strip_s led_strip_t;
+ * @brief Set RGB for a specific pixel
+ *
+ * @param strip: LED strip
+ * @param index: index of pixel to set
+ * @param red: red part of color
+ * @param green: green part of color
+ * @param blue: blue part of color
+ *
+ * @return
+ *      - ESP_OK: Set RGB for a specific pixel successfully
+ *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
+ *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
+ */
+esp_err_t led_strip_set_pixel(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
 
 /**
-* @brief LED Strip Device Type
-*
-*/
-typedef void *led_strip_dev_t;
+ * @brief Set RGBW for a specific pixel
+ *
+ * @note Only call this function if your led strip does have the white component (e.g. SK6812-RGBW)
+ * @note Also see `led_strip_set_pixel` if you only want to specify the RGB part of the color and bypass the white component
+ *
+ * @param strip: LED strip
+ * @param index: index of pixel to set
+ * @param red: red part of color
+ * @param green: green part of color
+ * @param blue: blue part of color
+ * @param white: separate white component
+ *
+ * @return
+ *      - ESP_OK: Set RGBW color for a specific pixel successfully
+ *      - ESP_ERR_INVALID_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+ *      - ESP_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+ */
+esp_err_t led_strip_set_pixel_rgbw(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white);
 
 /**
-* @brief Declare of LED Strip Type
-*
-*/
-struct led_strip_s {
-    /**
-    * @brief Set RGB for a specific pixel
-    *
-    * @param strip: LED strip
-    * @param index: index of pixel to set
-    * @param red: red part of color
-    * @param green: green part of color
-    * @param blue: blue part of color
-    *
-    * @return
-    *      - ESP_OK: Set RGB for a specific pixel successfully
-    *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
-    *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
-    */
-    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
-
-    /**
-    * @brief Refresh memory colors to LEDs
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for refreshing task
-    *
-    * @return
-    *      - ESP_OK: Refresh successfully
-    *      - ESP_ERR_TIMEOUT: Refresh failed because of timeout
-    *      - ESP_FAIL: Refresh failed because some other error occurred
-    *
-    * @note:
-    *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
-    */
-    esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Clear LED strip (turn off all LEDs)
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for clearing task
-    *
-    * @return
-    *      - ESP_OK: Clear LEDs successfully
-    *      - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout
-    *      - ESP_FAIL: Clear LEDs failed because some other error occurred
-    */
-    esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Free LED strip resources
-    *
-    * @param strip: LED strip
-    *
-    * @return
-    *      - ESP_OK: Free resources successfully
-    *      - ESP_FAIL: Free resources failed because error occurred
-    */
-    esp_err_t (*del)(led_strip_t *strip);
-};
+ * @brief Set HSV for a specific pixel
+ *
+ * @param strip: LED strip
+ * @param index: index of pixel to set
+ * @param hue: hue part of color (0 - 360)
+ * @param saturation: saturation part of color (0 - 255)
+ * @param value: value part of color (0 - 255)
+ *
+ * @return
+ *      - ESP_OK: Set HSV color for a specific pixel successfully
+ *      - ESP_ERR_INVALID_ARG: Set HSV color for a specific pixel failed because of an invalid argument
+ *      - ESP_FAIL: Set HSV color for a specific pixel failed because other error occurred
+ */
+esp_err_t led_strip_set_pixel_hsv(led_strip_handle_t strip, uint32_t index, uint16_t hue, uint8_t saturation, uint8_t value);
 
 /**
-* @brief LED Strip Configuration Type
-*
-*/
-typedef struct {
-    uint32_t max_leds;   /*!< Maximum LEDs in a single strip */
-    led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */
-} led_strip_config_t;
+ * @brief Refresh memory colors to LEDs
+ *
+ * @param strip: LED strip
+ *
+ * @return
+ *      - ESP_OK: Refresh successfully
+ *      - ESP_FAIL: Refresh failed because some other error occurred
+ *
+ * @note:
+ *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+ */
+esp_err_t led_strip_refresh(led_strip_handle_t strip);
 
 /**
- * @brief Default configuration for LED strip
+ * @brief Clear LED strip (turn off all LEDs)
+ *
+ * @param strip: LED strip
  *
+ * @return
+ *      - ESP_OK: Clear LEDs successfully
+ *      - ESP_FAIL: Clear LEDs failed because some other error occurred
  */
-#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \
-    {                                             \
-        .max_leds = number,                       \
-        .dev = dev_hdl,                           \
-    }
+esp_err_t led_strip_clear(led_strip_handle_t strip);
 
 /**
-* @brief Install a new ws2812 driver (based on RMT peripheral)
-*
-* @param config: LED strip configuration
-* @return
-*      LED strip instance or NULL
-*/
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config);
+ * @brief Free LED strip resources
+ *
+ * @param strip: LED strip
+ *
+ * @return
+ *      - ESP_OK: Free resources successfully
+ *      - ESP_FAIL: Free resources failed because error occurred
+ */
+esp_err_t led_strip_del(led_strip_handle_t strip);
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip_rmt.h b/hw/bsp/espressif/components/led_strip/include/led_strip_rmt.h
new file mode 100644
index 000000000..b575aeaba
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip_rmt.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "led_strip_types.h"
+#include "esp_idf_version.h"
+
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
+#include "driver/rmt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LED Strip RMT specific configuration
+ */
+typedef struct {
+#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 0, 0)
+    uint8_t rmt_channel;        /*!< Specify the channel number, the legacy RMT driver doesn't support channel allocator */
+#else // new driver supports specify the clock source and clock resolution
+    rmt_clock_source_t clk_src; /*!< RMT clock source */
+    uint32_t resolution_hz;     /*!< RMT tick resolution, if set to zero, a default resolution (10MHz) will be applied */
+#endif
+    size_t mem_block_symbols;   /*!< How many RMT symbols can one RMT channel hold at one time. Set to 0 will fallback to use the default size. */
+    struct {
+        uint32_t with_dma: 1;   /*!< Use DMA to transmit data */
+    } flags;                    /*!< Extra driver flags */
+} led_strip_rmt_config_t;
+
+/**
+ * @brief Create LED strip based on RMT TX channel
+ *
+ * @param led_config LED strip configuration
+ * @param rmt_config RMT specific configuration
+ * @param ret_strip Returned LED strip handle
+ * @return
+ *      - ESP_OK: create LED strip handle successfully
+ *      - ESP_ERR_INVALID_ARG: create LED strip handle failed because of invalid argument
+ *      - ESP_ERR_NO_MEM: create LED strip handle failed because of out of memory
+ *      - ESP_FAIL: create LED strip handle failed because some other error
+ */
+esp_err_t led_strip_new_rmt_device(const led_strip_config_t *led_config, const led_strip_rmt_config_t *rmt_config, led_strip_handle_t *ret_strip);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip_spi.h b/hw/bsp/espressif/components/led_strip/include/led_strip_spi.h
new file mode 100644
index 000000000..eb3524936
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip_spi.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/spi_master.h"
+#include "led_strip_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LED Strip SPI specific configuration
+ */
+typedef struct {
+    spi_clock_source_t clk_src; /*!< SPI clock source */
+    spi_host_device_t spi_bus;  /*!< SPI bus ID. Which buses are available depends on the specific chip */
+    struct {
+        uint32_t with_dma: 1;   /*!< Use DMA to transmit data */
+    } flags;                    /*!< Extra driver flags */
+} led_strip_spi_config_t;
+
+/**
+ * @brief Create LED strip based on SPI MOSI channel
+ * @note Although only the MOSI line is used for generating the signal, the whole SPI bus can't be used for other purposes.
+ *
+ * @param led_config LED strip configuration
+ * @param spi_config SPI specific configuration
+ * @param ret_strip Returned LED strip handle
+ * @return
+ *      - ESP_OK: create LED strip handle successfully
+ *      - ESP_ERR_INVALID_ARG: create LED strip handle failed because of invalid argument
+ *      - ESP_ERR_NOT_SUPPORTED: create LED strip handle failed because of unsupported configuration
+ *      - ESP_ERR_NO_MEM: create LED strip handle failed because of out of memory
+ *      - ESP_FAIL: create LED strip handle failed because some other error
+ */
+esp_err_t led_strip_new_spi_device(const led_strip_config_t *led_config, const led_strip_spi_config_t *spi_config, led_strip_handle_t *ret_strip);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/include/led_strip_types.h b/hw/bsp/espressif/components/led_strip/include/led_strip_types.h
new file mode 100644
index 000000000..691f0bc39
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/include/led_strip_types.h
@@ -0,0 +1,54 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LED strip pixel format
+ */
+typedef enum {
+    LED_PIXEL_FORMAT_GRB,    /*!< Pixel format: GRB */
+    LED_PIXEL_FORMAT_GRBW,   /*!< Pixel format: GRBW */
+    LED_PIXEL_FORMAT_INVALID /*!< Invalid pixel format */
+} led_pixel_format_t;
+
+/**
+ * @brief LED strip model
+ * @note Different led model may have different timing parameters, so we need to distinguish them.
+ */
+typedef enum {
+    LED_MODEL_WS2812, /*!< LED strip model: WS2812 */
+    LED_MODEL_SK6812, /*!< LED strip model: SK6812 */
+    LED_MODEL_INVALID /*!< Invalid LED strip model */
+} led_model_t;
+
+/**
+ * @brief LED strip handle
+ */
+typedef struct led_strip_t *led_strip_handle_t;
+
+/**
+ * @brief LED Strip Configuration
+ */
+typedef struct {
+    int strip_gpio_num;      /*!< GPIO number that used by LED strip */
+    uint32_t max_leds;       /*!< Maximum LEDs in a single strip */
+    led_pixel_format_t led_pixel_format; /*!< LED pixel format */
+    led_model_t led_model;   /*!< LED model */
+
+    struct {
+        uint32_t invert_out: 1; /*!< Invert output signal */
+    } flags;                    /*!< Extra driver flags */
+} led_strip_config_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/interface/led_strip_interface.h b/hw/bsp/espressif/components/led_strip/interface/led_strip_interface.h
new file mode 100644
index 000000000..3de4c2715
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/interface/led_strip_interface.h
@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct led_strip_t led_strip_t; /*!< Type of LED strip */
+
+/**
+ * @brief LED strip interface definition
+ */
+struct led_strip_t {
+    /**
+     * @brief Set RGB for a specific pixel
+     *
+     * @param strip: LED strip
+     * @param index: index of pixel to set
+     * @param red: red part of color
+     * @param green: green part of color
+     * @param blue: blue part of color
+     *
+     * @return
+     *      - ESP_OK: Set RGB for a specific pixel successfully
+     *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
+     *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
+     */
+    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
+
+    /**
+     * @brief Set RGBW for a specific pixel. Similar to `set_pixel` but also set the white component
+     *
+     * @param strip: LED strip
+     * @param index: index of pixel to set
+     * @param red: red part of color
+     * @param green: green part of color
+     * @param blue: blue part of color
+     * @param white: separate white component
+     *
+     * @return
+     *      - ESP_OK: Set RGBW color for a specific pixel successfully
+     *      - ESP_ERR_INVALID_ARG: Set RGBW color for a specific pixel failed because of an invalid argument
+     *      - ESP_FAIL: Set RGBW color for a specific pixel failed because other error occurred
+     */
+    esp_err_t (*set_pixel_rgbw)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white);
+
+    /**
+     * @brief Refresh memory colors to LEDs
+     *
+     * @param strip: LED strip
+     * @param timeout_ms: timeout value for refreshing task
+     *
+     * @return
+     *      - ESP_OK: Refresh successfully
+     *      - ESP_FAIL: Refresh failed because some other error occurred
+     *
+     * @note:
+     *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
+     */
+    esp_err_t (*refresh)(led_strip_t *strip);
+
+    /**
+     * @brief Clear LED strip (turn off all LEDs)
+     *
+     * @param strip: LED strip
+     * @param timeout_ms: timeout value for clearing task
+     *
+     * @return
+     *      - ESP_OK: Clear LEDs successfully
+     *      - ESP_FAIL: Clear LEDs failed because some other error occurred
+     */
+    esp_err_t (*clear)(led_strip_t *strip);
+
+    /**
+     * @brief Free LED strip resources
+     *
+     * @param strip: LED strip
+     *
+     * @return
+     *      - ESP_OK: Free resources successfully
+     *      - ESP_FAIL: Free resources failed because error occurred
+     */
+    esp_err_t (*del)(led_strip_t *strip);
+};
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_api.c b/hw/bsp/espressif/components/led_strip/src/led_strip_api.c
new file mode 100644
index 000000000..6eb86b8f1
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_api.c
@@ -0,0 +1,94 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_log.h"
+#include "esp_check.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+
+static const char *TAG = "led_strip";
+
+esp_err_t led_strip_set_pixel(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->set_pixel(strip, index, red, green, blue);
+}
+
+esp_err_t led_strip_set_pixel_hsv(led_strip_handle_t strip, uint32_t index, uint16_t hue, uint8_t saturation, uint8_t value)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+
+    uint32_t red = 0;
+    uint32_t green = 0;
+    uint32_t blue = 0;
+
+    uint32_t rgb_max = value;
+    uint32_t rgb_min = rgb_max * (255 - saturation) / 255.0f;
+
+    uint32_t i = hue / 60;
+    uint32_t diff = hue % 60;
+
+    // RGB adjustment amount by hue
+    uint32_t rgb_adj = (rgb_max - rgb_min) * diff / 60;
+
+    switch (i) {
+    case 0:
+        red = rgb_max;
+        green = rgb_min + rgb_adj;
+        blue = rgb_min;
+        break;
+    case 1:
+        red = rgb_max - rgb_adj;
+        green = rgb_max;
+        blue = rgb_min;
+        break;
+    case 2:
+        red = rgb_min;
+        green = rgb_max;
+        blue = rgb_min + rgb_adj;
+        break;
+    case 3:
+        red = rgb_min;
+        green = rgb_max - rgb_adj;
+        blue = rgb_max;
+        break;
+    case 4:
+        red = rgb_min + rgb_adj;
+        green = rgb_min;
+        blue = rgb_max;
+        break;
+    default:
+        red = rgb_max;
+        green = rgb_min;
+        blue = rgb_max - rgb_adj;
+        break;
+    }
+
+    return strip->set_pixel(strip, index, red, green, blue);
+}
+
+esp_err_t led_strip_set_pixel_rgbw(led_strip_handle_t strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->set_pixel_rgbw(strip, index, red, green, blue, white);
+}
+
+esp_err_t led_strip_refresh(led_strip_handle_t strip)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->refresh(strip);
+}
+
+esp_err_t led_strip_clear(led_strip_handle_t strip)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->clear(strip);
+}
+
+esp_err_t led_strip_del(led_strip_handle_t strip)
+{
+    ESP_RETURN_ON_FALSE(strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    return strip->del(strip);
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev.c
new file mode 100644
index 000000000..1cbf0e45a
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev.c
@@ -0,0 +1,164 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "driver/rmt_tx.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+#include "led_strip_rmt_encoder.h"
+
+#define LED_STRIP_RMT_DEFAULT_RESOLUTION 10000000 // 10MHz resolution
+#define LED_STRIP_RMT_DEFAULT_TRANS_QUEUE_SIZE 4
+// the memory size of each RMT channel, in words (4 bytes)
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 64
+#else
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 48
+#endif
+
+static const char *TAG = "led_strip_rmt";
+
+typedef struct {
+    led_strip_t base;
+    rmt_channel_handle_t rmt_chan;
+    rmt_encoder_handle_t strip_encoder;
+    uint32_t strip_len;
+    uint8_t bytes_per_pixel;
+    uint8_t pixel_buf[];
+} led_strip_rmt_obj;
+
+static esp_err_t led_strip_rmt_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_FALSE(index < rmt_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    uint32_t start = index * rmt_strip->bytes_per_pixel;
+    // In thr order of GRB, as LED strip like WS2812 sends out pixels in this order
+    rmt_strip->pixel_buf[start + 0] = green & 0xFF;
+    rmt_strip->pixel_buf[start + 1] = red & 0xFF;
+    rmt_strip->pixel_buf[start + 2] = blue & 0xFF;
+    if (rmt_strip->bytes_per_pixel > 3) {
+        rmt_strip->pixel_buf[start + 3] = 0;
+    }
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_set_pixel_rgbw(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_FALSE(index < rmt_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    ESP_RETURN_ON_FALSE(rmt_strip->bytes_per_pixel == 4, ESP_ERR_INVALID_ARG, TAG, "wrong LED pixel format, expected 4 bytes per pixel");
+    uint8_t *buf_start = rmt_strip->pixel_buf + index * 4;
+    // SK6812 component order is GRBW
+    *buf_start = green & 0xFF;
+    *++buf_start = red & 0xFF;
+    *++buf_start = blue & 0xFF;
+    *++buf_start = white & 0xFF;
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_refresh(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    rmt_transmit_config_t tx_conf = {
+        .loop_count = 0,
+    };
+
+    ESP_RETURN_ON_ERROR(rmt_enable(rmt_strip->rmt_chan), TAG, "enable RMT channel failed");
+    ESP_RETURN_ON_ERROR(rmt_transmit(rmt_strip->rmt_chan, rmt_strip->strip_encoder, rmt_strip->pixel_buf,
+                                     rmt_strip->strip_len * rmt_strip->bytes_per_pixel, &tx_conf), TAG, "transmit pixels by RMT failed");
+    ESP_RETURN_ON_ERROR(rmt_tx_wait_all_done(rmt_strip->rmt_chan, -1), TAG, "flush RMT channel failed");
+    ESP_RETURN_ON_ERROR(rmt_disable(rmt_strip->rmt_chan), TAG, "disable RMT channel failed");
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_clear(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    // Write zero to turn off all leds
+    memset(rmt_strip->pixel_buf, 0, rmt_strip->strip_len * rmt_strip->bytes_per_pixel);
+    return led_strip_rmt_refresh(strip);
+}
+
+static esp_err_t led_strip_rmt_del(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_ERROR(rmt_del_channel(rmt_strip->rmt_chan), TAG, "delete RMT channel failed");
+    ESP_RETURN_ON_ERROR(rmt_del_encoder(rmt_strip->strip_encoder), TAG, "delete strip encoder failed");
+    free(rmt_strip);
+    return ESP_OK;
+}
+
+esp_err_t led_strip_new_rmt_device(const led_strip_config_t *led_config, const led_strip_rmt_config_t *rmt_config, led_strip_handle_t *ret_strip)
+{
+    led_strip_rmt_obj *rmt_strip = NULL;
+    esp_err_t ret = ESP_OK;
+    ESP_GOTO_ON_FALSE(led_config && rmt_config && ret_strip, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    ESP_GOTO_ON_FALSE(led_config->led_pixel_format < LED_PIXEL_FORMAT_INVALID, ESP_ERR_INVALID_ARG, err, TAG, "invalid led_pixel_format");
+    uint8_t bytes_per_pixel = 3;
+    if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRBW) {
+        bytes_per_pixel = 4;
+    } else if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRB) {
+        bytes_per_pixel = 3;
+    } else {
+        assert(false);
+    }
+    rmt_strip = calloc(1, sizeof(led_strip_rmt_obj) + led_config->max_leds * bytes_per_pixel);
+    ESP_GOTO_ON_FALSE(rmt_strip, ESP_ERR_NO_MEM, err, TAG, "no mem for rmt strip");
+    uint32_t resolution = rmt_config->resolution_hz ? rmt_config->resolution_hz : LED_STRIP_RMT_DEFAULT_RESOLUTION;
+
+    // for backward compatibility, if the user does not set the clk_src, use the default value
+    rmt_clock_source_t clk_src = RMT_CLK_SRC_DEFAULT;
+    if (rmt_config->clk_src) {
+        clk_src = rmt_config->clk_src;
+    }
+    size_t mem_block_symbols = LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS;
+    // override the default value if the user sets it
+    if (rmt_config->mem_block_symbols) {
+        mem_block_symbols = rmt_config->mem_block_symbols;
+    }
+    rmt_tx_channel_config_t rmt_chan_config = {
+        .clk_src = clk_src,
+        .gpio_num = led_config->strip_gpio_num,
+        .mem_block_symbols = mem_block_symbols,
+        .resolution_hz = resolution,
+        .trans_queue_depth = LED_STRIP_RMT_DEFAULT_TRANS_QUEUE_SIZE,
+        .flags.with_dma = rmt_config->flags.with_dma,
+        .flags.invert_out = led_config->flags.invert_out,
+    };
+    ESP_GOTO_ON_ERROR(rmt_new_tx_channel(&rmt_chan_config, &rmt_strip->rmt_chan), err, TAG, "create RMT TX channel failed");
+
+    led_strip_encoder_config_t strip_encoder_conf = {
+        .resolution = resolution,
+        .led_model = led_config->led_model
+    };
+    ESP_GOTO_ON_ERROR(rmt_new_led_strip_encoder(&strip_encoder_conf, &rmt_strip->strip_encoder), err, TAG, "create LED strip encoder failed");
+
+
+    rmt_strip->bytes_per_pixel = bytes_per_pixel;
+    rmt_strip->strip_len = led_config->max_leds;
+    rmt_strip->base.set_pixel = led_strip_rmt_set_pixel;
+    rmt_strip->base.set_pixel_rgbw = led_strip_rmt_set_pixel_rgbw;
+    rmt_strip->base.refresh = led_strip_rmt_refresh;
+    rmt_strip->base.clear = led_strip_rmt_clear;
+    rmt_strip->base.del = led_strip_rmt_del;
+
+    *ret_strip = &rmt_strip->base;
+    return ESP_OK;
+err:
+    if (rmt_strip) {
+        if (rmt_strip->rmt_chan) {
+            rmt_del_channel(rmt_strip->rmt_chan);
+        }
+        if (rmt_strip->strip_encoder) {
+            rmt_del_encoder(rmt_strip->strip_encoder);
+        }
+        free(rmt_strip);
+    }
+    return ret;
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev_idf4.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev_idf4.c
new file mode 100644
index 000000000..a1067cd7c
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_dev_idf4.c
@@ -0,0 +1,194 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "driver/rmt.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+
+static const char *TAG = "led_strip_rmt";
+
+#define WS2812_T0H_NS   (300)
+#define WS2812_T0L_NS   (900)
+#define WS2812_T1H_NS   (900)
+#define WS2812_T1L_NS   (300)
+
+#define SK6812_T0H_NS   (300)
+#define SK6812_T0L_NS   (900)
+#define SK6812_T1H_NS   (600)
+#define SK6812_T1L_NS   (600)
+
+#define LED_STRIP_RESET_MS (10)
+
+// the memory size of each RMT channel, in words (4 bytes)
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 64
+#else
+#define LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS 48
+#endif
+
+static uint32_t led_t0h_ticks = 0;
+static uint32_t led_t1h_ticks = 0;
+static uint32_t led_t0l_ticks = 0;
+static uint32_t led_t1l_ticks = 0;
+
+typedef struct {
+    led_strip_t base;
+    rmt_channel_t rmt_channel;
+    uint32_t strip_len;
+    uint8_t bytes_per_pixel;
+    uint8_t buffer[0];
+} led_strip_rmt_obj;
+
+static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
+        size_t wanted_num, size_t *translated_size, size_t *item_num)
+{
+    if (src == NULL || dest == NULL) {
+        *translated_size = 0;
+        *item_num = 0;
+        return;
+    }
+    const rmt_item32_t bit0 = {{{ led_t0h_ticks, 1, led_t0l_ticks, 0 }}}; //Logical 0
+    const rmt_item32_t bit1 = {{{ led_t1h_ticks, 1, led_t1l_ticks, 0 }}}; //Logical 1
+    size_t size = 0;
+    size_t num = 0;
+    uint8_t *psrc = (uint8_t *)src;
+    rmt_item32_t *pdest = dest;
+    while (size < src_size && num < wanted_num) {
+        for (int i = 0; i < 8; i++) {
+            // MSB first
+            if (*psrc & (1 << (7 - i))) {
+                pdest->val =  bit1.val;
+            } else {
+                pdest->val =  bit0.val;
+            }
+            num++;
+            pdest++;
+        }
+        size++;
+        psrc++;
+    }
+    *translated_size = size;
+    *item_num = num;
+}
+
+static esp_err_t led_strip_rmt_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_FALSE(index < rmt_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of the maximum number of leds");
+    uint32_t start = index * rmt_strip->bytes_per_pixel;
+    // In thr order of GRB
+    rmt_strip->buffer[start + 0] = green & 0xFF;
+    rmt_strip->buffer[start + 1] = red & 0xFF;
+    rmt_strip->buffer[start + 2] = blue & 0xFF;
+    if (rmt_strip->bytes_per_pixel > 3) {
+        rmt_strip->buffer[start + 3] = 0;
+    }
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_refresh(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_ERROR(rmt_write_sample(rmt_strip->rmt_channel, rmt_strip->buffer, rmt_strip->strip_len * rmt_strip->bytes_per_pixel, true), TAG,
+                        "transmit RMT samples failed");
+    vTaskDelay(pdMS_TO_TICKS(LED_STRIP_RESET_MS));
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_rmt_clear(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    // Write zero to turn off all LEDs
+    memset(rmt_strip->buffer, 0, rmt_strip->strip_len * rmt_strip->bytes_per_pixel);
+    return led_strip_rmt_refresh(strip);
+}
+
+static esp_err_t led_strip_rmt_del(led_strip_t *strip)
+{
+    led_strip_rmt_obj *rmt_strip = __containerof(strip, led_strip_rmt_obj, base);
+    ESP_RETURN_ON_ERROR(rmt_driver_uninstall(rmt_strip->rmt_channel), TAG, "uninstall RMT driver failed");
+    free(rmt_strip);
+    return ESP_OK;
+}
+
+esp_err_t led_strip_new_rmt_device(const led_strip_config_t *led_config, const led_strip_rmt_config_t *dev_config, led_strip_handle_t *ret_strip)
+{
+    led_strip_rmt_obj *rmt_strip = NULL;
+    esp_err_t ret = ESP_OK;
+    ESP_RETURN_ON_FALSE(led_config && dev_config && ret_strip, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    ESP_RETURN_ON_FALSE(led_config->led_pixel_format < LED_PIXEL_FORMAT_INVALID, ESP_ERR_INVALID_ARG, TAG, "invalid led_pixel_format");
+    ESP_RETURN_ON_FALSE(dev_config->flags.with_dma == 0, ESP_ERR_NOT_SUPPORTED, TAG, "DMA is not supported");
+
+    uint8_t bytes_per_pixel = 3;
+    if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRBW) {
+        bytes_per_pixel = 4;
+    } else if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRB) {
+        bytes_per_pixel = 3;
+    } else {
+        assert(false);
+    }
+
+    // allocate memory for led_strip object
+    rmt_strip = calloc(1, sizeof(led_strip_rmt_obj) + led_config->max_leds * bytes_per_pixel);
+    ESP_RETURN_ON_FALSE(rmt_strip, ESP_ERR_NO_MEM, TAG, "request memory for les_strip failed");
+
+    // install RMT channel driver
+    rmt_config_t config = RMT_DEFAULT_CONFIG_TX(led_config->strip_gpio_num, dev_config->rmt_channel);
+    // set the minimal clock division because the LED strip needs a high clock resolution
+    config.clk_div = 2;
+
+    uint8_t mem_block_num = 2;
+    // override the default value if the user specify the mem block size
+    if (dev_config->mem_block_symbols) {
+        mem_block_num = (dev_config->mem_block_symbols + LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS / 2) / LED_STRIP_RMT_DEFAULT_MEM_BLOCK_SYMBOLS;
+    }
+    config.mem_block_num = mem_block_num;
+
+    ESP_GOTO_ON_ERROR(rmt_config(&config), err, TAG, "RMT config failed");
+    ESP_GOTO_ON_ERROR(rmt_driver_install(config.channel, 0, 0), err, TAG, "RMT install failed");
+
+    uint32_t counter_clk_hz = 0;
+    rmt_get_counter_clock((rmt_channel_t)dev_config->rmt_channel, &counter_clk_hz);
+    // ns -> ticks
+    float ratio = (float)counter_clk_hz / 1e9;
+    if (led_config->led_model == LED_MODEL_WS2812) {
+        led_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
+        led_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
+        led_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
+        led_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
+    } else if (led_config->led_model == LED_MODEL_SK6812) {
+        led_t0h_ticks = (uint32_t)(ratio * SK6812_T0H_NS);
+        led_t0l_ticks = (uint32_t)(ratio * SK6812_T0L_NS);
+        led_t1h_ticks = (uint32_t)(ratio * SK6812_T1H_NS);
+        led_t1l_ticks = (uint32_t)(ratio * SK6812_T1L_NS);
+    } else {
+        assert(false);
+    }
+
+    // adapter to translates the LES strip date frame into RMT symbols
+    rmt_translator_init((rmt_channel_t)dev_config->rmt_channel, ws2812_rmt_adapter);
+
+    rmt_strip->bytes_per_pixel = bytes_per_pixel;
+    rmt_strip->rmt_channel = (rmt_channel_t)dev_config->rmt_channel;
+    rmt_strip->strip_len = led_config->max_leds;
+    rmt_strip->base.set_pixel = led_strip_rmt_set_pixel;
+    rmt_strip->base.refresh = led_strip_rmt_refresh;
+    rmt_strip->base.clear = led_strip_rmt_clear;
+    rmt_strip->base.del = led_strip_rmt_del;
+
+    *ret_strip = &rmt_strip->base;
+    return ESP_OK;
+
+err:
+    if (rmt_strip) {
+        free(rmt_strip);
+    }
+    return ret;
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.c
new file mode 100644
index 000000000..d352ac07f
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.c
@@ -0,0 +1,146 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_check.h"
+#include "led_strip_rmt_encoder.h"
+
+static const char *TAG = "led_rmt_encoder";
+
+typedef struct {
+    rmt_encoder_t base;
+    rmt_encoder_t *bytes_encoder;
+    rmt_encoder_t *copy_encoder;
+    int state;
+    rmt_symbol_word_t reset_code;
+} rmt_led_strip_encoder_t;
+
+static size_t rmt_encode_led_strip(rmt_encoder_t *encoder, rmt_channel_handle_t channel, const void *primary_data, size_t data_size, rmt_encode_state_t *ret_state)
+{
+    rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base);
+    rmt_encoder_handle_t bytes_encoder = led_encoder->bytes_encoder;
+    rmt_encoder_handle_t copy_encoder = led_encoder->copy_encoder;
+    rmt_encode_state_t session_state = 0;
+    rmt_encode_state_t state = 0;
+    size_t encoded_symbols = 0;
+    switch (led_encoder->state) {
+    case 0: // send RGB data
+        encoded_symbols += bytes_encoder->encode(bytes_encoder, channel, primary_data, data_size, &session_state);
+        if (session_state & RMT_ENCODING_COMPLETE) {
+            led_encoder->state = 1; // switch to next state when current encoding session finished
+        }
+        if (session_state & RMT_ENCODING_MEM_FULL) {
+            state |= RMT_ENCODING_MEM_FULL;
+            goto out; // yield if there's no free space for encoding artifacts
+        }
+    // fall-through
+    case 1: // send reset code
+        encoded_symbols += copy_encoder->encode(copy_encoder, channel, &led_encoder->reset_code,
+                                                sizeof(led_encoder->reset_code), &session_state);
+        if (session_state & RMT_ENCODING_COMPLETE) {
+            led_encoder->state = 0; // back to the initial encoding session
+            state |= RMT_ENCODING_COMPLETE;
+        }
+        if (session_state & RMT_ENCODING_MEM_FULL) {
+            state |= RMT_ENCODING_MEM_FULL;
+            goto out; // yield if there's no free space for encoding artifacts
+        }
+    }
+out:
+    *ret_state = state;
+    return encoded_symbols;
+}
+
+static esp_err_t rmt_del_led_strip_encoder(rmt_encoder_t *encoder)
+{
+    rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base);
+    rmt_del_encoder(led_encoder->bytes_encoder);
+    rmt_del_encoder(led_encoder->copy_encoder);
+    free(led_encoder);
+    return ESP_OK;
+}
+
+static esp_err_t rmt_led_strip_encoder_reset(rmt_encoder_t *encoder)
+{
+    rmt_led_strip_encoder_t *led_encoder = __containerof(encoder, rmt_led_strip_encoder_t, base);
+    rmt_encoder_reset(led_encoder->bytes_encoder);
+    rmt_encoder_reset(led_encoder->copy_encoder);
+    led_encoder->state = 0;
+    return ESP_OK;
+}
+
+esp_err_t rmt_new_led_strip_encoder(const led_strip_encoder_config_t *config, rmt_encoder_handle_t *ret_encoder)
+{
+    esp_err_t ret = ESP_OK;
+    rmt_led_strip_encoder_t *led_encoder = NULL;
+    ESP_GOTO_ON_FALSE(config && ret_encoder, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    ESP_GOTO_ON_FALSE(config->led_model < LED_MODEL_INVALID, ESP_ERR_INVALID_ARG, err, TAG, "invalid led model");
+    led_encoder = calloc(1, sizeof(rmt_led_strip_encoder_t));
+    ESP_GOTO_ON_FALSE(led_encoder, ESP_ERR_NO_MEM, err, TAG, "no mem for led strip encoder");
+    led_encoder->base.encode = rmt_encode_led_strip;
+    led_encoder->base.del = rmt_del_led_strip_encoder;
+    led_encoder->base.reset = rmt_led_strip_encoder_reset;
+    rmt_bytes_encoder_config_t bytes_encoder_config;
+    if (config->led_model == LED_MODEL_SK6812) {
+        bytes_encoder_config = (rmt_bytes_encoder_config_t) {
+            .bit0 = {
+                .level0 = 1,
+                .duration0 = 0.3 * config->resolution / 1000000, // T0H=0.3us
+                .level1 = 0,
+                .duration1 = 0.9 * config->resolution / 1000000, // T0L=0.9us
+            },
+            .bit1 = {
+                .level0 = 1,
+                .duration0 = 0.6 * config->resolution / 1000000, // T1H=0.6us
+                .level1 = 0,
+                .duration1 = 0.6 * config->resolution / 1000000, // T1L=0.6us
+            },
+            .flags.msb_first = 1 // SK6812 transfer bit order: G7...G0R7...R0B7...B0(W7...W0)
+        };
+    } else if (config->led_model == LED_MODEL_WS2812) {
+        // different led strip might have its own timing requirements, following parameter is for WS2812
+        bytes_encoder_config = (rmt_bytes_encoder_config_t) {
+            .bit0 = {
+                .level0 = 1,
+                .duration0 = 0.3 * config->resolution / 1000000, // T0H=0.3us
+                .level1 = 0,
+                .duration1 = 0.9 * config->resolution / 1000000, // T0L=0.9us
+            },
+            .bit1 = {
+                .level0 = 1,
+                .duration0 = 0.9 * config->resolution / 1000000, // T1H=0.9us
+                .level1 = 0,
+                .duration1 = 0.3 * config->resolution / 1000000, // T1L=0.3us
+            },
+            .flags.msb_first = 1 // WS2812 transfer bit order: G7...G0R7...R0B7...B0
+        };
+    } else {
+        assert(false);
+    }
+    ESP_GOTO_ON_ERROR(rmt_new_bytes_encoder(&bytes_encoder_config, &led_encoder->bytes_encoder), err, TAG, "create bytes encoder failed");
+    rmt_copy_encoder_config_t copy_encoder_config = {};
+    ESP_GOTO_ON_ERROR(rmt_new_copy_encoder(&copy_encoder_config, &led_encoder->copy_encoder), err, TAG, "create copy encoder failed");
+
+    uint32_t reset_ticks = config->resolution / 1000000 * 50 / 2; // reset code duration defaults to 50us
+    led_encoder->reset_code = (rmt_symbol_word_t) {
+        .level0 = 0,
+        .duration0 = reset_ticks,
+        .level1 = 0,
+        .duration1 = reset_ticks,
+    };
+    *ret_encoder = &led_encoder->base;
+    return ESP_OK;
+err:
+    if (led_encoder) {
+        if (led_encoder->bytes_encoder) {
+            rmt_del_encoder(led_encoder->bytes_encoder);
+        }
+        if (led_encoder->copy_encoder) {
+            rmt_del_encoder(led_encoder->copy_encoder);
+        }
+        free(led_encoder);
+    }
+    return ret;
+}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.h b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.h
new file mode 100644
index 000000000..ba71e60ab
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_encoder.h
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "driver/rmt_encoder.h"
+#include "led_strip_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Type of led strip encoder configuration
+ */
+typedef struct {
+    uint32_t resolution;   /*!< Encoder resolution, in Hz */
+    led_model_t led_model; /*!< LED model */
+} led_strip_encoder_config_t;
+
+/**
+ * @brief Create RMT encoder for encoding LED strip pixels into RMT symbols
+ *
+ * @param[in] config Encoder configuration
+ * @param[out] ret_encoder Returned encoder handle
+ * @return
+ *      - ESP_ERR_INVALID_ARG for any invalid arguments
+ *      - ESP_ERR_NO_MEM out of memory when creating led strip encoder
+ *      - ESP_OK if creating encoder successfully
+ */
+esp_err_t rmt_new_led_strip_encoder(const led_strip_encoder_config_t *config, rmt_encoder_handle_t *ret_encoder);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c
deleted file mode 100644
index fd1746cad..000000000
--- a/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdlib.h>
-#include <string.h>
-#include <sys/cdefs.h>
-#include "esp_log.h"
-#include "esp_attr.h"
-#include "led_strip.h"
-#include "driver/rmt.h"
-
-static const char *TAG = "ws2812";
-#define STRIP_CHECK(a, str, goto_tag, ret_value, ...)                             \
-    do                                                                            \
-    {                                                                             \
-        if (!(a))                                                                 \
-        {                                                                         \
-            ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
-            ret = ret_value;                                                      \
-            goto goto_tag;                                                        \
-        }                                                                         \
-    } while (0)
-
-#define WS2812_T0H_NS (350)
-#define WS2812_T0L_NS (1000)
-#define WS2812_T1H_NS (1000)
-#define WS2812_T1L_NS (350)
-#define WS2812_RESET_US (280)
-
-static uint32_t ws2812_t0h_ticks = 0;
-static uint32_t ws2812_t1h_ticks = 0;
-static uint32_t ws2812_t0l_ticks = 0;
-static uint32_t ws2812_t1l_ticks = 0;
-
-typedef struct {
-    led_strip_t parent;
-    rmt_channel_t rmt_channel;
-    uint32_t strip_len;
-    uint8_t buffer[0];
-} ws2812_t;
-
-/**
- * @brief Convert RGB data to RMT format.
- *
- * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
- *
- * @param[in] src: source data, to converted to RMT format
- * @param[in] dest: place where to store the convert result
- * @param[in] src_size: size of source data
- * @param[in] wanted_num: number of RMT items that want to get
- * @param[out] translated_size: number of source data that got converted
- * @param[out] item_num: number of RMT items which are converted from source data
- */
-static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
-        size_t wanted_num, size_t *translated_size, size_t *item_num)
-{
-    if (src == NULL || dest == NULL) {
-        *translated_size = 0;
-        *item_num = 0;
-        return;
-    }
-    const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0
-    const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1
-    size_t size = 0;
-    size_t num = 0;
-    uint8_t *psrc = (uint8_t *)src;
-    rmt_item32_t *pdest = dest;
-    while (size < src_size && num < wanted_num) {
-        for (int i = 0; i < 8; i++) {
-            // MSB first
-            if (*psrc & (1 << (7 - i))) {
-                pdest->val =  bit1.val;
-            } else {
-                pdest->val =  bit0.val;
-            }
-            num++;
-            pdest++;
-        }
-        size++;
-        psrc++;
-    }
-    *translated_size = size;
-    *item_num = num;
-}
-
-static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG);
-    uint32_t start = index * 3;
-    // In thr order of GRB
-    ws2812->buffer[start + 0] = green & 0xFF;
-    ws2812->buffer[start + 1] = red & 0xFF;
-    ws2812->buffer[start + 2] = blue & 0xFF;
-    return ESP_OK;
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK,
-                "transmit RMT samples failed", err, ESP_FAIL);
-    return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms));
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    // Write zero to turn off all leds
-    memset(ws2812->buffer, 0, ws2812->strip_len * 3);
-    return ws2812_refresh(strip, timeout_ms);
-}
-
-static esp_err_t ws2812_del(led_strip_t *strip)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    free(ws2812);
-    return ESP_OK;
-}
-
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config)
-{
-    led_strip_t *ret = NULL;
-    STRIP_CHECK(config, "configuration can't be null", err, NULL);
-
-    // 24 bits per led
-    uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3;
-    ws2812_t *ws2812 = calloc(1, ws2812_size);
-    STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL);
-
-    uint32_t counter_clk_hz = 0;
-    STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK,
-                "get rmt counter clock failed", err, NULL);
-    // ns -> ticks
-    float ratio = (float)counter_clk_hz / 1e9;
-    ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
-    ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
-    ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
-    ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
-
-    // set ws2812 to rmt adapter
-    rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter);
-
-    ws2812->rmt_channel = (rmt_channel_t)config->dev;
-    ws2812->strip_len = config->max_leds;
-
-    ws2812->parent.set_pixel = ws2812_set_pixel;
-    ws2812->parent.refresh = ws2812_refresh;
-    ws2812->parent.clear = ws2812_clear;
-    ws2812->parent.del = ws2812_del;
-
-    return &ws2812->parent;
-err:
-    return ret;
-}
diff --git a/hw/bsp/espressif/components/led_strip/src/led_strip_spi_dev.c b/hw/bsp/espressif/components/led_strip/src/led_strip_spi_dev.c
new file mode 100644
index 000000000..12ea8fbf3
--- /dev/null
+++ b/hw/bsp/espressif/components/led_strip/src/led_strip_spi_dev.c
@@ -0,0 +1,209 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <sys/cdefs.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "esp_rom_gpio.h"
+#include "soc/spi_periph.h"
+#include "led_strip.h"
+#include "led_strip_interface.h"
+#include "hal/spi_hal.h"
+
+#define LED_STRIP_SPI_DEFAULT_RESOLUTION (2.5 * 1000 * 1000) // 2.5MHz resolution
+#define LED_STRIP_SPI_DEFAULT_TRANS_QUEUE_SIZE 4
+
+#define SPI_BYTES_PER_COLOR_BYTE 3
+#define SPI_BITS_PER_COLOR_BYTE (SPI_BYTES_PER_COLOR_BYTE * 8)
+
+static const char *TAG = "led_strip_spi";
+
+typedef struct {
+    led_strip_t base;
+    spi_host_device_t spi_host;
+    spi_device_handle_t spi_device;
+    uint32_t strip_len;
+    uint8_t bytes_per_pixel;
+    uint8_t pixel_buf[];
+} led_strip_spi_obj;
+
+// please make sure to zero-initialize the buf before calling this function
+static void __led_strip_spi_bit(uint8_t data, uint8_t *buf)
+{
+    // Each color of 1 bit is represented by 3 bits of SPI, low_level:100 ,high_level:110
+    // So a color byte occupies 3 bytes of SPI.
+    *(buf + 2) |= data & BIT(0) ? BIT(2) | BIT(1) : BIT(2);
+    *(buf + 2) |= data & BIT(1) ? BIT(5) | BIT(4) : BIT(5);
+    *(buf + 2) |= data & BIT(2) ? BIT(7) : 0x00;
+    *(buf + 1) |= BIT(0);
+    *(buf + 1) |= data & BIT(3) ? BIT(3) | BIT(2) : BIT(3);
+    *(buf + 1) |= data & BIT(4) ? BIT(6) | BIT(5) : BIT(6);
+    *(buf + 0) |= data & BIT(5) ? BIT(1) | BIT(0) : BIT(1);
+    *(buf + 0) |= data & BIT(6) ? BIT(4) | BIT(3) : BIT(4);
+    *(buf + 0) |= data & BIT(7) ? BIT(7) | BIT(6) : BIT(7);
+}
+
+static esp_err_t led_strip_spi_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    ESP_RETURN_ON_FALSE(index < spi_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    // LED_PIXEL_FORMAT_GRB takes 72bits(9bytes)
+    uint32_t start = index * spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE;
+    memset(spi_strip->pixel_buf + start, 0, spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE);
+    __led_strip_spi_bit(green, &spi_strip->pixel_buf[start]);
+    __led_strip_spi_bit(red, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE]);
+    __led_strip_spi_bit(blue, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 2]);
+    if (spi_strip->bytes_per_pixel > 3) {
+        __led_strip_spi_bit(0, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 3]);
+    }
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_spi_set_pixel_rgbw(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue, uint32_t white)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    ESP_RETURN_ON_FALSE(index < spi_strip->strip_len, ESP_ERR_INVALID_ARG, TAG, "index out of maximum number of LEDs");
+    ESP_RETURN_ON_FALSE(spi_strip->bytes_per_pixel == 4, ESP_ERR_INVALID_ARG, TAG, "wrong LED pixel format, expected 4 bytes per pixel");
+    // LED_PIXEL_FORMAT_GRBW takes 96bits(12bytes)
+    uint32_t start = index * spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE;
+    // SK6812 component order is GRBW
+    memset(spi_strip->pixel_buf + start, 0, spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE);
+    __led_strip_spi_bit(green, &spi_strip->pixel_buf[start]);
+    __led_strip_spi_bit(red, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE]);
+    __led_strip_spi_bit(blue, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 2]);
+    __led_strip_spi_bit(white, &spi_strip->pixel_buf[start + SPI_BYTES_PER_COLOR_BYTE * 3]);
+
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_spi_refresh(led_strip_t *strip)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    spi_transaction_t tx_conf;
+    memset(&tx_conf, 0, sizeof(tx_conf));
+
+    tx_conf.length = spi_strip->strip_len * spi_strip->bytes_per_pixel * SPI_BITS_PER_COLOR_BYTE;
+    tx_conf.tx_buffer = spi_strip->pixel_buf;
+    tx_conf.rx_buffer = NULL;
+    ESP_RETURN_ON_ERROR(spi_device_transmit(spi_strip->spi_device, &tx_conf), TAG, "transmit pixels by SPI failed");
+
+    return ESP_OK;
+}
+
+static esp_err_t led_strip_spi_clear(led_strip_t *strip)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+    //Write zero to turn off all leds
+    memset(spi_strip->pixel_buf, 0, spi_strip->strip_len * spi_strip->bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE);
+    uint8_t *buf = spi_strip->pixel_buf;
+    for (int index = 0; index < spi_strip->strip_len * spi_strip->bytes_per_pixel; index++) {
+        __led_strip_spi_bit(0, buf);
+        buf += SPI_BYTES_PER_COLOR_BYTE;
+    }
+
+    return led_strip_spi_refresh(strip);
+}
+
+static esp_err_t led_strip_spi_del(led_strip_t *strip)
+{
+    led_strip_spi_obj *spi_strip = __containerof(strip, led_strip_spi_obj, base);
+
+    ESP_RETURN_ON_ERROR(spi_bus_remove_device(spi_strip->spi_device), TAG, "delete spi device failed");
+    ESP_RETURN_ON_ERROR(spi_bus_free(spi_strip->spi_host), TAG, "free spi bus failed");
+
+    free(spi_strip);
+    return ESP_OK;
+}
+
+esp_err_t led_strip_new_spi_device(const led_strip_config_t *led_config, const led_strip_spi_config_t *spi_config, led_strip_handle_t *ret_strip)
+{
+    led_strip_spi_obj *spi_strip = NULL;
+    esp_err_t ret = ESP_OK;
+    ESP_GOTO_ON_FALSE(led_config && spi_config && ret_strip, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
+    ESP_GOTO_ON_FALSE(led_config->led_pixel_format < LED_PIXEL_FORMAT_INVALID, ESP_ERR_INVALID_ARG, err, TAG, "invalid led_pixel_format");
+    uint8_t bytes_per_pixel = 3;
+    if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRBW) {
+        bytes_per_pixel = 4;
+    } else if (led_config->led_pixel_format == LED_PIXEL_FORMAT_GRB) {
+        bytes_per_pixel = 3;
+    } else {
+        assert(false);
+    }
+    uint32_t mem_caps = MALLOC_CAP_DEFAULT;
+    if (spi_config->flags.with_dma) {
+        // DMA buffer must be placed in internal SRAM
+        mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA;
+    }
+    spi_strip = heap_caps_calloc(1, sizeof(led_strip_spi_obj) + led_config->max_leds * bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE, mem_caps);
+
+    ESP_GOTO_ON_FALSE(spi_strip, ESP_ERR_NO_MEM, err, TAG, "no mem for spi strip");
+
+    spi_strip->spi_host = spi_config->spi_bus;
+    // for backward compatibility, if the user does not set the clk_src, use the default value
+    spi_clock_source_t clk_src = SPI_CLK_SRC_DEFAULT;
+    if (spi_config->clk_src) {
+        clk_src = spi_config->clk_src;
+    }
+
+    spi_bus_config_t spi_bus_cfg = {
+        .mosi_io_num = led_config->strip_gpio_num,
+        //Only use MOSI to generate the signal, set -1 when other pins are not used.
+        .miso_io_num = -1,
+        .sclk_io_num = -1,
+        .quadwp_io_num = -1,
+        .quadhd_io_num = -1,
+        .max_transfer_sz = led_config->max_leds * bytes_per_pixel * SPI_BYTES_PER_COLOR_BYTE,
+    };
+    ESP_GOTO_ON_ERROR(spi_bus_initialize(spi_strip->spi_host, &spi_bus_cfg, spi_config->flags.with_dma ? SPI_DMA_CH_AUTO : SPI_DMA_DISABLED), err, TAG, "create SPI bus failed");
+
+    if (led_config->flags.invert_out == true) {
+        esp_rom_gpio_connect_out_signal(led_config->strip_gpio_num, spi_periph_signal[spi_strip->spi_host].spid_out, true, false);
+    }
+
+    spi_device_interface_config_t spi_dev_cfg = {
+        .clock_source = clk_src,
+        .command_bits = 0,
+        .address_bits = 0,
+        .dummy_bits = 0,
+        .clock_speed_hz = LED_STRIP_SPI_DEFAULT_RESOLUTION,
+        .mode = 0,
+        //set -1 when CS is not used
+        .spics_io_num = -1,
+        .queue_size = LED_STRIP_SPI_DEFAULT_TRANS_QUEUE_SIZE,
+    };
+
+    ESP_GOTO_ON_ERROR(spi_bus_add_device(spi_strip->spi_host, &spi_dev_cfg, &spi_strip->spi_device), err, TAG, "Failed to add spi device");
+
+    int clock_resolution_khz = 0;
+    spi_device_get_actual_freq(spi_strip->spi_device, &clock_resolution_khz);
+    // TODO: ideally we should decide the SPI_BYTES_PER_COLOR_BYTE by the real clock resolution
+    // But now, let's fixed the resolution, the downside is, we don't support a clock source whose frequency is not multiple of LED_STRIP_SPI_DEFAULT_RESOLUTION
+    ESP_GOTO_ON_FALSE(clock_resolution_khz == LED_STRIP_SPI_DEFAULT_RESOLUTION / 1000, ESP_ERR_NOT_SUPPORTED, err,
+                      TAG, "unsupported clock resolution:%dKHz", clock_resolution_khz);
+
+    spi_strip->bytes_per_pixel = bytes_per_pixel;
+    spi_strip->strip_len = led_config->max_leds;
+    spi_strip->base.set_pixel = led_strip_spi_set_pixel;
+    spi_strip->base.set_pixel_rgbw = led_strip_spi_set_pixel_rgbw;
+    spi_strip->base.refresh = led_strip_spi_refresh;
+    spi_strip->base.clear = led_strip_spi_clear;
+    spi_strip->base.del = led_strip_spi_del;
+
+    *ret_strip = &spi_strip->base;
+    return ESP_OK;
+err:
+    if (spi_strip) {
+        if (spi_strip->spi_device) {
+            spi_bus_remove_device(spi_strip->spi_device);
+        }
+        if (spi_strip->spi_host) {
+            spi_bus_free(spi_strip->spi_host);
+        }
+        free(spi_strip);
+    }
+    return ret;
+}
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 539a776a6..ff3393cfd 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -211,7 +211,6 @@ function(family_configure_common TARGET RTOS)
     target_link_options(${TARGET} PUBLIC "LINKER:--map=$<TARGET_FILE:${TARGET}>.map")
   endif()
 
-
   # ETM Trace option
   if (TRACE_ETM STREQUAL "1")
     target_compile_definitions(${TARGET} PUBLIC TRACE_ETM)
diff --git a/hw/bsp/mcx/boards/bunny-brain/board.cmake b/hw/bsp/mcx/boards/bunny-brain/board.cmake
deleted file mode 100644
index 8c3280743..000000000
--- a/hw/bsp/mcx/boards/bunny-brain/board.cmake
+++ /dev/null
@@ -1,21 +0,0 @@
-set(MCU_VARIANT MCXN947)
-set(MCU_CORE MCXN947_cm33_core0)
-
-set(JLINK_DEVICE MCXN947_M33_0)
-set(PYOCD_TARGET MCXN947)
-set(NXPLINK_DEVICE MCXN947:MCXN947)
-
-set(PORT 1)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    CPU_MCXN947VDF_cm33_core0
-    BOARD_TUD_RHPORT=${PORT}
-    # port 0 is fullspeed, port 1 is highspeed
-    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    )
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
-    )
-endfunction()
diff --git a/hw/bsp/mcx/boards/bunny-brain/board.h b/hw/bsp/mcx/boards/bunny-brain/board.h
deleted file mode 100644
index eae98bfa7..000000000
--- a/hw/bsp/mcx/boards/bunny-brain/board.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_GPIO              GPIO3
-#define LED_CLK               kCLOCK_Gpio3
-#define LED_PIN               4 // red
-#define LED_STATE_ON          0
-
-// WAKE button (Dummy, use unused pin
-#define BUTTON_GPIO           GPIO0
-#define BUTTON_CLK            kCLOCK_Gpio0
-#define BUTTON_PIN            6
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              LPUART4
-
-static inline void board_uart_init_clock(void) {
-  /* attach FRO 12M to FLEXCOMM4 */
-  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
-  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
-
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/mcx/boards/bunny-brain/board.mk b/hw/bsp/mcx/boards/bunny-brain/board.mk
deleted file mode 100644
index aaad5e73e..000000000
--- a/hw/bsp/mcx/boards/bunny-brain/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = MCXN947
-MCU_CORE = MCXN947_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_MCXN947VDF_cm33_core0
-
-JLINK_DEVICE = MCXN947_M33_0
-PYOCD_TARGET = MCXN947
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/bunny-brain/clock_config.c b/hw/bsp/mcx/boards/bunny-brain/clock_config.c
deleted file mode 100644
index 37d2b4dfc..000000000
--- a/hw/bsp/mcx/boards/bunny-brain/clock_config.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v10.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
-board: MCX-N9XX-EVK
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "clock_config.h"
-#include "fsl_clock.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 18 MHz}
-- {id: System_clock.outFreq, value: 72 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
diff --git a/hw/bsp/mcx/boards/bunny-brain/clock_config.h b/hw/bsp/mcx/boards/bunny-brain/clock_config.h
deleted file mode 100644
index c238a0423..000000000
--- a/hw/bsp/mcx/boards/bunny-brain/clock_config.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/bunny-brain/pin_mux.c b/hw/bsp/mcx/boards/bunny-brain/pin_mux.c
deleted file mode 100644
index acc2f3e45..000000000
--- a/hw/bsp/mcx/boards/bunny-brain/pin_mux.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v12.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitPins(void)
-{
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-    /* Enables the clock for PORT3: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port3);
-
-    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P0 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
-
-    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P1 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
-
-    const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
-                                                     kPORT_PullDisable,
-                                                     /* Low internal pull resistor value is selected. */
-                                                     kPORT_LowPullResistor,
-                                                     /* Fast slew rate is configured */
-                                                     kPORT_FastSlewRate,
-                                                     /* Passive input filter is disabled */
-                                                     kPORT_PassiveFilterDisable,
-                                                     /* Open drain output is disabled */
-                                                     kPORT_OpenDrainDisable,
-                                                     /* Low drive strength is configured */
-                                                     kPORT_LowDriveStrength,
-                                                     /* Pin is configured as PIO3_4 */
-                                                     kPORT_MuxAlt0,
-                                                     /* Digital input enabled */
-                                                     kPORT_InputBufferEnable,
-                                                     /* Digital input is not inverted */
-                                                     kPORT_InputNormal,
-                                                     /* Pin Control Register fields [15:0] are not locked */
-                                                     kPORT_UnlockRegister};
-    /* PORT3_4 (pin F14) is configured as PIO3_4 */
-    PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/bunny-brain/pin_mux.h b/hw/bsp/mcx/boards/bunny-brain/pin_mux.h
deleted file mode 100644
index 40968c275..000000000
--- a/hw/bsp/mcx/boards/bunny-brain/pin_mux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm-mcxn947/board.cmake b/hw/bsp/mcx/boards/frdm-mcxn947/board.cmake
deleted file mode 100644
index 8c3280743..000000000
--- a/hw/bsp/mcx/boards/frdm-mcxn947/board.cmake
+++ /dev/null
@@ -1,21 +0,0 @@
-set(MCU_VARIANT MCXN947)
-set(MCU_CORE MCXN947_cm33_core0)
-
-set(JLINK_DEVICE MCXN947_M33_0)
-set(PYOCD_TARGET MCXN947)
-set(NXPLINK_DEVICE MCXN947:MCXN947)
-
-set(PORT 1)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    CPU_MCXN947VDF_cm33_core0
-    BOARD_TUD_RHPORT=${PORT}
-    # port 0 is fullspeed, port 1 is highspeed
-    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    )
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
-    )
-endfunction()
diff --git a/hw/bsp/mcx/boards/frdm-mcxn947/board.h b/hw/bsp/mcx/boards/frdm-mcxn947/board.h
deleted file mode 100644
index acb73363f..000000000
--- a/hw/bsp/mcx/boards/frdm-mcxn947/board.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_GPIO              GPIO0
-#define LED_CLK               kCLOCK_Gpio0
-#define LED_PIN               10 // red
-#define LED_STATE_ON          0
-
-// WAKE button (Dummy, use unused pin
-#define BUTTON_GPIO           GPIO0
-#define BUTTON_CLK            kCLOCK_Gpio0
-#define BUTTON_PIN            23
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              LPUART4
-
-static inline void board_uart_init_clock(void) {
-  /* attach FRO 12M to FLEXCOMM4 */
-  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
-  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
-
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/mcx/boards/frdm-mcxn947/board.mk b/hw/bsp/mcx/boards/frdm-mcxn947/board.mk
deleted file mode 100644
index aaad5e73e..000000000
--- a/hw/bsp/mcx/boards/frdm-mcxn947/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = MCXN947
-MCU_CORE = MCXN947_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_MCXN947VDF_cm33_core0
-
-JLINK_DEVICE = MCXN947_M33_0
-PYOCD_TARGET = MCXN947
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdm-mcxn947/clock_config.c b/hw/bsp/mcx/boards/frdm-mcxn947/clock_config.c
deleted file mode 100644
index 37d2b4dfc..000000000
--- a/hw/bsp/mcx/boards/frdm-mcxn947/clock_config.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v10.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
-board: MCX-N9XX-EVK
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "clock_config.h"
-#include "fsl_clock.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 18 MHz}
-- {id: System_clock.outFreq, value: 72 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
diff --git a/hw/bsp/mcx/boards/frdm-mcxn947/clock_config.h b/hw/bsp/mcx/boards/frdm-mcxn947/clock_config.h
deleted file mode 100644
index c238a0423..000000000
--- a/hw/bsp/mcx/boards/frdm-mcxn947/clock_config.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.c b/hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.c
deleted file mode 100644
index 30a5ae456..000000000
--- a/hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v12.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: B12, peripheral: GPIO0, signal: 'GPIO, 10', pin_signal: PIO0_12/ADC0_B10/FC0_P6/CT0O_MAT0/FLEXIO0_D2, slew_rate: fast, open_drain: disable, drive_strength: low,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitPins(void)
-{
-  /* Enables the clock for PORT0: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-
-
-    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P0 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
-
-    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P1 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
-
-    const port_pin_config_t port0_10_pinB12_config = {/* Internal pull-up/down resistor is disabled */
-                                                     kPORT_PullDisable,
-                                                     /* Low internal pull resistor value is selected. */
-                                                     kPORT_LowPullResistor,
-                                                     /* Fast slew rate is configured */
-                                                     kPORT_FastSlewRate,
-                                                     /* Passive input filter is disabled */
-                                                     kPORT_PassiveFilterDisable,
-                                                     /* Open drain output is disabled */
-                                                     kPORT_OpenDrainDisable,
-                                                     /* Low drive strength is configured */
-                                                     kPORT_LowDriveStrength,
-                                                     /* Pin is configured as PIO0_10 */
-                                                     kPORT_MuxAlt0,
-                                                     /* Digital input enabled */
-                                                     kPORT_InputBufferEnable,
-                                                     /* Digital input is not inverted */
-                                                     kPORT_InputNormal,
-                                                     /* Pin Control Register fields [15:0] are not locked */
-                                                     kPORT_UnlockRegister};
-    /* PORT0_10 (pin B12) is configured as PIO0_10 */
-    PORT_SetPinConfig(PORT0, 10U, &port0_10_pinB12_config);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.h b/hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.h
deleted file mode 100644
index 40968c275..000000000
--- a/hw/bsp/mcx/boards/frdm-mcxn947/pin_mux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index d438d0715..4adc558a6 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1729,7 +1729,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     // Find correct interface
     if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt)
     {
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
       uint8_t const * p_desc_parse_for_params = p_desc;
 #endif
       // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary
diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index deec32ae4..5cbd658fe 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -136,8 +136,7 @@ typedef enum{
 //--------------------------------------------------------------------+
 
 /// Communication Interface Management Element Request Codes
-typedef enum
-{
+typedef enum {
   CDC_REQUEST_SEND_ENCAPSULATED_COMMAND                    = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface
   CDC_REQUEST_GET_ENCAPSULATED_RESPONSE                    = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface.
   CDC_REQUEST_SET_COMM_FEATURE                             = 0x02,
@@ -180,39 +179,38 @@ typedef enum
   CDC_REQUEST_GET_ATM_VC_STATISTICS                        = 0x53,
 
   CDC_REQUEST_MDLM_SEMANTIC_MODEL                          = 0x60,
-}cdc_management_request_t;
+} cdc_management_request_t;
 
-enum {
+typedef enum {
   CDC_CONTROL_LINE_STATE_DTR = 0x01,
   CDC_CONTROL_LINE_STATE_RTS = 0x02,
-};
+} cdc_control_line_state_t;
 
-enum {
+typedef enum {
   CDC_LINE_CODING_STOP_BITS_1   = 0, // 1   bit
   CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits
   CDC_LINE_CODING_STOP_BITS_2   = 2, // 2   bits
-};
+} cdc_line_coding_stopbits_t;
 
 // TODO Backward compatible for typos. Maybe removed in the future release
 #define CDC_LINE_CONDING_STOP_BITS_1   CDC_LINE_CODING_STOP_BITS_1
 #define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5
 #define CDC_LINE_CONDING_STOP_BITS_2   CDC_LINE_CODING_STOP_BITS_2
 
-enum {
+typedef enum {
   CDC_LINE_CODING_PARITY_NONE  = 0,
   CDC_LINE_CODING_PARITY_ODD   = 1,
   CDC_LINE_CODING_PARITY_EVEN  = 2,
   CDC_LINE_CODING_PARITY_MARK  = 3,
   CDC_LINE_CODING_PARITY_SPACE = 4,
-};
+} cdc_line_coding_parity_t;
 
 //--------------------------------------------------------------------+
 // Management Element Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
 
 /// 6.3 Notification Codes
-typedef enum
-{
+typedef enum {
   CDC_NOTIF_NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
   CDC_NOTIF_RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
   CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 2463671c6..2fb37d835 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -22,6 +22,9 @@
  * THE SOFTWARE.
  *
  * This file is part of the TinyUSB stack.
+ *
+ * Contribution
+ * - Heiko Kuester: CH34x support
  */
 
 #include "tusb_option.h"
@@ -50,12 +53,18 @@ typedef struct {
   uint8_t bInterfaceSubClass;
   uint8_t bInterfaceProtocol;
 
+  uint8_t ep_notif;
   uint8_t serial_drid; // Serial Driver ID
+  bool mounted;        // Enumeration is complete
   cdc_acm_capability_t acm_capability;
-  uint8_t ep_notif;
 
-  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
   TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
+  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
+
+  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
+  cdc_line_coding_t requested_line_coding;
+  // 1 byte padding
+  #endif
 
   tuh_xfer_cb_t user_control_cb;
 
@@ -69,7 +78,6 @@ typedef struct {
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
     CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
-
 } cdch_interface_t;
 
 CFG_TUH_MEM_SECTION
@@ -83,45 +91,57 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC];
 static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void acm_process_config(tuh_xfer_t* xfer);
 
+static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 //------------- FTDI prototypes -------------//
 #if CFG_TUH_CDC_FTDI
 #include "serial/ftdi_sio.h"
 
-static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST };
-enum {
-  FTDI_PID_COUNT = sizeof(ftdi_vid_pid_list) / sizeof(ftdi_vid_pid_list[0])
-};
-
-// Store last request baudrate since divisor to baudrate is not easy
-static uint32_t _ftdi_requested_baud;
+static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST};
 
 static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
 static void ftdi_process_config(tuh_xfer_t* xfer);
 
-static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
 //------------- CP210X prototypes -------------//
 #if CFG_TUH_CDC_CP210X
 #include "serial/cp210x.h"
 
-static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST };
-enum {
-  CP210X_PID_COUNT = sizeof(cp210x_vid_pid_list) / sizeof(cp210x_vid_pid_list[0])
-};
+static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST};
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 static void cp210x_process_config(tuh_xfer_t* xfer);
 
-static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
+//------------- CH34x prototypes -------------//
+#if CFG_TUH_CDC_CH34X
+#include "serial/ch34x.h"
+
+static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST};
+
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len);
+static void ch34x_process_config(tuh_xfer_t* xfer);
+
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+#endif
+
+//------------- Common -------------//
 enum {
   SERIAL_DRIVER_ACM = 0,
 
@@ -132,60 +152,96 @@ enum {
 #if CFG_TUH_CDC_CP210X
   SERIAL_DRIVER_CP210X,
 #endif
+
+#if CFG_TUH_CDC_CH34X
+  SERIAL_DRIVER_CH34X,
+#endif
+
+  SERIAL_DRIVER_COUNT
 };
 
 typedef struct {
+  uint16_t const (*vid_pid_list)[2];
+  uint16_t const vid_pid_count;
+  bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
   void (*const process_set_config)(tuh_xfer_t* xfer);
   bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
   bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_data_format)(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 } cdch_serial_driver_t;
 
 // Note driver list must be in the same order as SERIAL_DRIVER enum
 static const cdch_serial_driver_t serial_drivers[] = {
-  { .process_set_config     = acm_process_config,
-    .set_control_line_state = acm_set_control_line_state,
-    .set_baudrate           = acm_set_baudrate
+  {
+      .vid_pid_list           = NULL,
+      .vid_pid_count          = 0,
+      .open                   = acm_open,
+      .process_set_config     = acm_process_config,
+      .set_control_line_state = acm_set_control_line_state,
+      .set_baudrate           = acm_set_baudrate,
+      .set_data_format        = acm_set_data_format,
+      .set_line_coding        = acm_set_line_coding
   },
 
   #if CFG_TUH_CDC_FTDI
-  { .process_set_config     = ftdi_process_config,
-    .set_control_line_state = ftdi_sio_set_modem_ctrl,
-    .set_baudrate           = ftdi_sio_set_baudrate
+  {
+      .vid_pid_list           = ftdi_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ftdi_vid_pid_list),
+      .open                   = ftdi_open,
+      .process_set_config     = ftdi_process_config,
+      .set_control_line_state = ftdi_sio_set_modem_ctrl,
+      .set_baudrate           = ftdi_sio_set_baudrate,
+      .set_data_format        = ftdi_set_data_format,
+      .set_line_coding        = ftdi_set_line_coding
   },
   #endif
 
   #if CFG_TUH_CDC_CP210X
-  { .process_set_config     = cp210x_process_config,
-    .set_control_line_state = cp210x_set_modem_ctrl,
-    .set_baudrate           = cp210x_set_baudrate
+  {
+      .vid_pid_list           = cp210x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(cp210x_vid_pid_list),
+      .open                   = cp210x_open,
+      .process_set_config     = cp210x_process_config,
+      .set_control_line_state = cp210x_set_modem_ctrl,
+      .set_baudrate           = cp210x_set_baudrate,
+      .set_data_format        = cp210x_set_data_format,
+      .set_line_coding        = cp210x_set_line_coding
   },
   #endif
-};
 
-enum {
-  SERIAL_DRIVER_COUNT = sizeof(serial_drivers) / sizeof(serial_drivers[0])
+  #if CFG_TUH_CDC_CH34X
+  {
+      .vid_pid_list           = ch34x_vid_pid_list,
+      .vid_pid_count          = TU_ARRAY_SIZE(ch34x_vid_pid_list),
+      .open                   = ch34x_open,
+      .process_set_config     = ch34x_process_config,
+      .set_control_line_state = ch34x_set_modem_ctrl,
+      .set_baudrate           = ch34x_set_baudrate,
+      .set_data_format        = ch34x_set_data_format,
+      .set_line_coding        = ch34x_set_line_coding
+  },
+  #endif
 };
 
+TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial driver count mismatch");
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-static inline cdch_interface_t* get_itf(uint8_t idx)
-{
+static inline cdch_interface_t* get_itf(uint8_t idx) {
   TU_ASSERT(idx < CFG_TUH_CDC, NULL);
   cdch_interface_t* p_cdc = &cdch_data[idx];
 
   return (p_cdc->daddr != 0) ? p_cdc : NULL;
 }
 
-static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
     if ( (p_cdc->daddr == daddr) &&
-         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr))
-    {
+         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) {
       return i;
     }
   }
@@ -193,14 +249,10 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
   return TUSB_INDEX_INVALID_8;
 }
 
-
-static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) {
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++) {
     if (cdch_data[i].daddr == 0) {
       cdch_interface_t* p_cdc = &cdch_data[i];
-
       p_cdc->daddr              = daddr;
       p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
       p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
@@ -221,20 +273,16 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 // APPLICATION API
 //--------------------------------------------------------------------+
 
-uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
-{
-  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
-  {
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) {
+  for (uint8_t i = 0; i < CFG_TUH_CDC; i++) {
     const cdch_interface_t* p_cdc = &cdch_data[i];
-
     if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
   }
 
   return TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
-{
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && info);
 
@@ -256,30 +304,27 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
   return true;
 }
 
-bool tuh_cdc_mounted(uint8_t idx)
-{
+bool tuh_cdc_mounted(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
-  return p_cdc != NULL;
+  TU_VERIFY(p_cdc);
+  return p_cdc->mounted;
 }
 
-bool tuh_cdc_get_dtr(uint8_t idx)
-{
+bool tuh_cdc_get_dtr(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
 }
 
-bool tuh_cdc_get_rts(uint8_t idx)
-{
+bool tuh_cdc_get_rts(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
 
-bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
-{
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -292,32 +337,28 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
 // Write
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_write_flush(uint8_t idx)
-{
+uint32_t tuh_cdc_write_flush(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_write_xfer(&p_cdc->stream.tx);
 }
 
-bool tuh_cdc_write_clear(uint8_t idx)
-{
+bool tuh_cdc_write_clear(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_clear(&p_cdc->stream.tx);
 }
 
-uint32_t tuh_cdc_write_available(uint8_t idx)
-{
+uint32_t tuh_cdc_write_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -328,32 +369,28 @@ uint32_t tuh_cdc_write_available(uint8_t idx)
 // Read
 //--------------------------------------------------------------------+
 
-uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
-{
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize);
 }
 
-uint32_t tuh_cdc_read_available(uint8_t idx)
-{
+uint32_t tuh_cdc_read_available(uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_read_available(&p_cdc->stream.rx);
 }
 
-bool tuh_cdc_peek(uint8_t idx, uint8_t* ch)
-{
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
   return tu_edpt_stream_peek(&p_cdc->stream.rx, ch);
 }
 
-bool tuh_cdc_read_clear (uint8_t idx)
-{
+bool tuh_cdc_read_clear (uint8_t idx) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
@@ -366,28 +403,25 @@ bool tuh_cdc_read_clear (uint8_t idx)
 // Control Endpoint API
 //--------------------------------------------------------------------+
 
-// internal control complete to update state such as line state, encoding
-static void cdch_internal_control_complete(tuh_xfer_t* xfer)
-{
-  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) {
   uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc, );
+  uint16_t const value = tu_le16toh(xfer->setup->wValue);
 
-  if (xfer->result == XFER_RESULT_SUCCESS)
-  {
+  if (xfer->result == XFER_RESULT_SUCCESS) {
     switch (p_cdc->serial_drid) {
       case SERIAL_DRIVER_ACM:
         switch (xfer->setup->bRequest) {
           case CDC_REQUEST_SET_CONTROL_LINE_STATE:
-            p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case CDC_REQUEST_SET_LINE_CODING: {
             uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
             memcpy(&p_cdc->line_coding, xfer->buffer, len);
-          }
             break;
+          }
 
           default: break;
         }
@@ -397,12 +431,11 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
       case SERIAL_DRIVER_FTDI:
         switch (xfer->setup->bRequest) {
           case FTDI_SIO_MODEM_CTRL:
-            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case FTDI_SIO_SET_BAUD_RATE:
-            // convert from divisor to baudrate is not supported
-            p_cdc->line_coding.bit_rate = _ftdi_requested_baud;
+            p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
             break;
 
           default: break;
@@ -414,15 +447,61 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
       case SERIAL_DRIVER_CP210X:
         switch(xfer->setup->bRequest) {
           case CP210X_SET_MHS:
-            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            p_cdc->line_state = (uint8_t) value;
             break;
 
           case CP210X_SET_BAUDRATE: {
             uint32_t baudrate;
             memcpy(&baudrate, xfer->buffer, sizeof(uint32_t));
             p_cdc->line_coding.bit_rate = tu_le32toh(baudrate);
+            break;
           }
+
+          default: break;
+        }
+        break;
+      #endif
+
+      #if CFG_TUH_CDC_CH34X
+      case SERIAL_DRIVER_CH34X:
+        switch (xfer->setup->bRequest) {
+          case CH34X_REQ_WRITE_REG:
+            // register write request
+            switch (value) {
+              case CH34X_REG16_DIVISOR_PRESCALER:
+                // baudrate
+                p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+                break;
+
+              case CH32X_REG16_LCR2_LCR:
+                // data format
+                p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits;
+                p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity;
+                p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits;
+                break;
+
+              default: break;
+            }
+            break;
+
+          case CH34X_REQ_MODEM_CTRL: {
+            // set modem controls RTS/DTR request. Note: signals are inverted
+            uint16_t const modem_signal = ~value;
+            if (modem_signal & CH34X_BIT_RTS) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS;
+            }
+
+            if (modem_signal & CH34X_BIT_DTR) {
+              p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
+            } else {
+              p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR;
+            }
             break;
+          }
+
+          default: break;
         }
         break;
       #endif
@@ -437,14 +516,20 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
   }
 }
 
+// internal control complete to update state such as line state, encoding
+static void cdch_internal_control_complete(tuh_xfer_t* xfer) {
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  process_internal_control_complete(xfer, itf_num);
+}
+
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result);
@@ -455,7 +540,6 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_state = (uint8_t) line_state;
     return true;
   }
@@ -466,9 +550,9 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
   cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
-  if ( complete_cb ) {
+  if (complete_cb) {
     return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
-  }else {
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result);
@@ -479,25 +563,23 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
-
     p_cdc->line_coding.bit_rate = baudrate;
     return true;
   }
 }
 
-bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
-  // only ACM support this set line coding request
-  TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM);
-  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
 
-  if ( complete_cb ) {
-    return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
-  }else {
+  if (complete_cb) {
+    return driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, user_data);
+  } else {
     // blocking
     xfer_result_t result = XFER_RESULT_INVALID;
-    bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
+    bool ret = driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, (uintptr_t) &result);
 
     if (user_data) {
       // user_data is not NULL, return result via user_data
@@ -505,7 +587,31 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     }
 
     TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = stop_bits;
+    p_cdc->line_coding.parity = parity;
+    p_cdc->line_coding.data_bits = data_bits;
+    return true;
+  }
+}
+
+bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if ( complete_cb ) {
+    return driver->set_line_coding(p_cdc, line_coding, complete_cb, user_data);
+  } else {
+    // blocking
+    xfer_result_t result = XFER_RESULT_INVALID;
+    bool ret = driver->set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
 
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
     p_cdc->line_coding = *line_coding;
     return true;
   }
@@ -515,39 +621,34 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 // CLASS-USBH API
 //--------------------------------------------------------------------+
 
-void cdch_init(void)
-{
+void cdch_init(void) {
   tu_memclr(cdch_data, sizeof(cdch_data));
 
-  for(size_t i=0; i<CFG_TUH_CDC; i++)
-  {
+  for (size_t i = 0; i < CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
 
     tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
-                          p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
-                          p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
+                        p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
+                        p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
 
     tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false,
-                          p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
-                          p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
+                        p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
+                        p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
   }
 }
 
-void cdch_close(uint8_t daddr)
-{
-  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
-  {
+void cdch_close(uint8_t daddr) {
+  for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
     cdch_interface_t* p_cdc = &cdch_data[idx];
-    if (p_cdc->daddr == daddr)
-    {
+    if (p_cdc->daddr == daddr) {
       TU_LOG_DRV("  CDCh close addr = %u index = %u\r\n", daddr, idx);
 
       // Invoke application callback
       if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx);
 
-      //tu_memclr(p_cdc, sizeof(cdch_interface_t));
       p_cdc->daddr = 0;
       p_cdc->bInterfaceNumber = 0;
+      p_cdc->mounted = false;
       tu_edpt_stream_close(&p_cdc->stream.tx);
       tu_edpt_stream_close(&p_cdc->stream.rx);
     }
@@ -571,16 +672,11 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
       // - xferred_bytes is multiple of EP Packet size and not zero
       tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
     }
-  }
-  else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
+  } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
     #if CFG_TUH_CDC_FTDI
     if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) {
       // FTDI reserve 2 bytes for status
-      // FTDI status
-//      uint8_t status[2] = {
-//        p_cdc->stream.rx.ep_buf[0],
-//        p_cdc->stream.rx.ep_buf[1]
-//      };
+      // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]};
       tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2);
     }else
     #endif
@@ -606,20 +702,15 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep)
-{
-  for(size_t i=0; i<2; i++)
-  {
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const* desc_ep) {
+  for (size_t i = 0; i < 2; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
-              TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
-
+              TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
     TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep));
 
-    if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
-    {
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
       tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep);
-    }else
-    {
+    } else {
       tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep);
     }
 
@@ -629,45 +720,36 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co
   return true;
 }
 
-bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
+bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
   (void) rhport;
 
-  // Only support ACM subclass
+  // For CDC: only support ACM subclass
   // Note: Protocol 0xFF can be RNDIS device
-  if ( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
-       CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass)
-  {
+  if (TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
+      CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
     return acm_open(daddr, itf_desc, max_len);
   }
-  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
-  else if ( TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass )
-  {
+  else if (SERIAL_DRIVER_COUNT > 1 &&
+           TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
-    #if CFG_TUH_CDC_FTDI
-    for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
-      if (ftdi_vid_pid_list[i][0] == vid && ftdi_vid_pid_list[i][1] == pid) {
-        return ftdi_open(daddr, itf_desc, max_len);
-      }
-    }
-    #endif
-
-    #if CFG_TUH_CDC_CP210X
-    for (size_t i = 0; i < CP210X_PID_COUNT; i++) {
-      if (cp210x_vid_pid_list[i][0] == vid && cp210x_vid_pid_list[i][1] == pid) {
-        return cp210x_open(daddr, itf_desc, max_len);
+    for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) {
+      cdch_serial_driver_t const* driver = &serial_drivers[dr];
+      for (size_t i = 0; i < driver->vid_pid_count; i++) {
+        if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) {
+          return driver->open(daddr, itf_desc, max_len);
+        }
       }
     }
-    #endif
   }
-  #endif
 
   return false;
 }
 
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
+  TU_LOG_DRV("CDCh Set Configure complete\r\n");
+  p_cdc->mounted = true;
   if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
 
   // Prepare for incoming data
@@ -677,9 +759,7 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i
   usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
 }
 
-
-bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
-{
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num) {
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
@@ -708,94 +788,84 @@ enum {
   CONFIG_ACM_COMPLETE,
 };
 
-static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
-  uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len;
 
-  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
-
   p_cdc->serial_drid = SERIAL_DRIVER_ACM;
 
   //------------- Control Interface -------------//
-  uint8_t const * p_desc = tu_desc_next(itf_desc);
+  uint8_t const* p_desc = tu_desc_next(itf_desc);
 
   // Communication Functional Descriptors
-  while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) )
-  {
-    if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
-    {
+  while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) {
+    if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) {
       // save ACM bmCapabilities
-      p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
+      p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities;
     }
 
     p_desc = tu_desc_next(p_desc);
   }
 
   // Open notification endpoint of control interface if any
-  if (itf_desc->bNumEndpoints == 1)
-  {
+  if (itf_desc->bNumEndpoints == 1) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
-    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
 
-    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
+    TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     p_desc = tu_desc_next(p_desc);
   }
 
   //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
-       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
-  {
+  if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+      (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) {
     // next to endpoint descriptor
     p_desc = tu_desc_next(p_desc);
 
     // data endpoints expected to be in pairs
-    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
+    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc));
   }
 
   return true;
 }
 
-static void acm_process_config(tuh_xfer_t* xfer)
-{
+static void acm_process_config(tuh_xfer_t* xfer) {
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t * p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc, );
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
 
-  switch(state)
-  {
+  switch (state) {
     case CONFIG_ACM_SET_CONTROL_LINE_STATE:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
-        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config,
-                                             CONFIG_ACM_SET_LINE_CODING), );
+      if (p_cdc->acm_capability.support_line_request) {
+        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),);
         break;
       }
-          #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_SET_LINE_CODING:
-        #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
-      {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request) {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE), );
+        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),);
         break;
       }
-        #endif
+      #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_COMPLETE:
       // itf_num+1 to account for data interface as well
-      set_config_complete(p_cdc, idx, itf_num+1);
+      set_config_complete(p_cdc, idx, itf_num + 1);
       break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
@@ -863,6 +933,19 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const
   return true;
 }
 
+static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_DRV("CDC ACM Set Data Format\r\n");
+
+  cdc_line_coding_t line_coding;
+  line_coding.bit_rate = p_cdc->line_coding.bit_rate;
+  line_coding.stop_bits = stop_bits;
+  line_coding.parity = parity;
+  line_coding.data_bits = data_bits;
+
+  return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
+}
+
 static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_VERIFY(p_cdc->acm_capability.support_line_request);
   cdc_line_coding_t line_coding = p_cdc->line_coding;
@@ -892,7 +975,6 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint
   TU_VERIFY(p_cdc);
 
   TU_LOG_DRV("FTDI opened\r\n");
-
   p_cdc->serial_drid = SERIAL_DRIVER_FTDI;
 
   // endpoint pair
@@ -928,13 +1010,32 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1
   return tuh_control_xfer(&xfer);
 }
 
-static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
+static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) line_coding;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
@@ -942,8 +1043,7 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state
   return true;
 }
 
-static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
-{
+static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) {
   const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 };
   uint32_t divisor;
 
@@ -963,18 +1063,16 @@ static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
   return divisor;
 }
 
-static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
-{
+static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) {
   return ftdi_232bm_baud_base_to_divisor(baud, 48000000u);
 }
 
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
   TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
-  _ftdi_requested_baud = baudrate;
+  p_cdc->requested_line_coding.bit_rate = baudrate;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
                                  complete_cb ? cdch_internal_control_complete : NULL, user_data));
 
@@ -996,8 +1094,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_FTDI_MODEM_CTRL:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
+      TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1105,6 +1202,15 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
   return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data);
 }
 
+static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  // TODO implement later
+  (void) p_cdc;
+  (void) line_coding;
+  (void) complete_cb;
+  (void) user_data;
+  return false;
+}
+
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
@@ -1113,8 +1219,19 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
                             complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
-static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  (void) p_cdc;
+  (void) stop_bits;
+  (void) parity;
+  (void) data_bits;
+  (void) complete_cb;
+  (void) user_data;
+  // TODO not implemented yet
+  return false;
+}
+
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
@@ -1154,8 +1271,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CP210X_SET_DTR_RTS:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
+      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1171,4 +1287,374 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
 
 #endif
 
+//--------------------------------------------------------------------+
+// CH34x (CH340 & CH341)
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_CDC_CH34X
+
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits);
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval);
+
+//------------- control request -------------//
+
+static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value,
+                              uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request_setup = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_VENDOR,
+          .direction = direction & 0x01u
+      },
+      .bRequest = request,
+      .wValue   = tu_htole16 (value),
+      .wIndex   = tu_htole16 (index),
+      .wLength  = tu_htole16 (length)
+  };
+
+  // use usbh enum buf since application variable does not live long enough
+  uint8_t* enum_buf = NULL;
+
+  if (buffer && length > 0) {
+    enum_buf = usbh_get_enum_buf();
+    if (direction == TUSB_DIR_OUT) {
+      tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+    }
+  }
+
+  tuh_xfer_t xfer = {
+      .daddr       = p_cdc->daddr,
+      .ep_addr     = 0,
+      .setup       = &request_setup,
+      .buffer      = enum_buf,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
+static inline bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data);
+}
+
+static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index,
+                                    uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize,
+                           complete_cb, user_data);
+}
+
+static inline bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data);
+}
+
+//static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg,
+//                                     uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
+//{
+//  return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data );
+//}
+
+static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                                     tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate);
+  TU_VERIFY(div_ps);
+  TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps,
+                            complete_cb, user_data));
+  return true;
+}
+
+//------------- Driver API -------------//
+
+// internal control complete to update state such as line state, encoding
+static void ch34x_control_complete(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  process_internal_control_complete(xfer, 0);
+}
+
+static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits,
+                                tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.stop_bits = stop_bits;
+  p_cdc->requested_line_coding.parity = parity;
+  p_cdc->requested_line_coding.data_bits = data_bits;
+
+  uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits);
+  TU_VERIFY(lcr);
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding.bit_rate = baudrate;
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate,
+                                     complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+
+  if (xfer->result == XFER_RESULT_SUCCESS) {
+    // stage 1 success, continue to stage 2
+    p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate;
+    TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity,
+                                    p_cdc->requested_line_coding.data_bits, ch34x_control_complete, xfer->user_data), );
+  } else {
+    // stage 1 failed, notify user
+    xfer->complete_cb = p_cdc->user_control_cb;
+    if (xfer->complete_cb) {
+      xfer->complete_cb(xfer);
+    }
+  }
+}
+
+// 2 stages: set baudrate (stage1) + set data format (stage2)
+static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  p_cdc->requested_line_coding = *line_coding;
+  p_cdc->user_control_cb = complete_cb;
+
+  if (complete_cb) {
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate,
+                                       ch34x_set_line_coding_stage1_complete, user_data));
+  } else {
+    // sync call
+    xfer_result_t result;
+
+    // stage 1 set baudrate
+    TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.bit_rate = line_coding->bit_rate;
+
+    // stage 2 set data format
+    TU_ASSERT(ch34x_set_data_format(p_cdc, line_coding->stop_bits, line_coding->parity, line_coding->data_bits,
+                                    NULL, (uintptr_t) &result));
+    TU_VERIFY(result == XFER_RESULT_SUCCESS);
+    p_cdc->line_coding.stop_bits = line_coding->stop_bits;
+    p_cdc->line_coding.parity = line_coding->parity;
+    p_cdc->line_coding.data_bits = line_coding->data_bits;
+
+    // update transfer result, user_data is expected to point to xfer_result_t
+    if (user_data) {
+      *((xfer_result_t*) user_data) = result;
+    }
+  }
+
+  return true;
+}
+
+static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
+                                 tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  uint8_t control = 0;
+  if (line_state & CDC_CONTROL_LINE_STATE_RTS) {
+    control |= CH34X_BIT_RTS;
+  }
+  if (line_state & CDC_CONTROL_LINE_STATE_DTR) {
+    control |= CH34X_BIT_DTR;
+  }
+
+  // CH34x signals are inverted
+  control = ~control;
+
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0,
+                               complete_cb ? ch34x_control_complete : NULL, user_data));
+  return true;
+}
+
+//------------- Enumeration -------------//
+enum {
+  CONFIG_CH34X_READ_VERSION = 0,
+  CONFIG_CH34X_SERIAL_INIT,
+  CONFIG_CH34X_SPECIAL_REG_WRITE,
+  CONFIG_CH34X_FLOW_CONTROL,
+  CONFIG_CH34X_MODEM_CONTROL,
+  CONFIG_CH34X_COMPLETE
+};
+
+static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) {
+  // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints
+  TU_VERIFY (itf_desc->bNumEndpoints == 3);
+  TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY (p_cdc);
+
+  TU_LOG_DRV ("CH34x opened\r\n");
+  p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
+
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
+  desc_ep += 2;
+
+  // Interrupt endpoint: not used for now
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) &&
+            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer);
+  TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
+  p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+  return true;
+}
+
+static void ch34x_process_config(tuh_xfer_t* xfer) {
+  // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber
+  uint8_t const itf_num = 0;
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  uintptr_t const state = xfer->user_data;
+  uint8_t buffer[2]; // TODO remove
+  TU_ASSERT (p_cdc,);
+  TU_ASSERT (xfer->result == XFER_RESULT_SUCCESS,);
+
+  switch (state) {
+    case CONFIG_CH34X_READ_VERSION:
+      TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
+      TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
+      break;
+
+    case CONFIG_CH34X_SERIAL_INIT: {
+      // handle version read data, set CH34x line coding (incl. baudrate)
+      uint8_t const version = xfer->buffer[0];
+      TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
+      // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
+      TU_ASSERT (version >= 0x30,);
+      // init CH34x with line coding
+      cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X;
+      uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate);
+      TU_ASSERT(div_ps, );
+      uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits);
+      TU_ASSERT(lcr, );
+      TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps,
+                                   ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
+      break;
+    }
+
+    case CONFIG_CH34X_SPECIAL_REG_WRITE:
+      // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver
+      p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X);
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
+      break;
+
+    case CONFIG_CH34X_FLOW_CONTROL:
+      // no hardware flow control
+      TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
+      break;
+
+    case CONFIG_CH34X_MODEM_CONTROL:
+      // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
+      TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
+      break;
+
+    case CONFIG_CH34X_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default:
+      TU_ASSERT (false,);
+      break;
+  }
+}
+
+//------------- CH34x helper  -------------//
+
+// calculate divisor and prescaler for baudrate, return it as 16-bit combined value
+static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) {
+  uint8_t a;
+  uint8_t b;
+  uint32_t c;
+
+  TU_VERIFY(baval != 0 && baval <= 2000000, 0);
+  switch (baval) {
+    case 921600:
+      a = 0xf3;
+      b = 7;
+      break;
+
+    case 307200:
+      a = 0xd9;
+      b = 7;
+      break;
+
+    default:
+      if (baval > 6000000 / 255) {
+        b = 3;
+        c = 6000000;
+      } else if (baval > 750000 / 255) {
+        b = 2;
+        c = 750000;
+      } else if (baval > 93750 / 255) {
+        b = 1;
+        c = 93750;
+      } else {
+        b = 0;
+        c = 11719;
+      }
+      a = (uint8_t) (c / baval);
+      if (a == 0 || a == 0xFF) {
+        return 0;
+      }
+      if ((c / a - baval) > (baval - c / (a + 1))) {
+        a++;
+      }
+      a = (uint8_t) (256 - a);
+      break;
+  }
+
+  // reg divisor = a, reg prescaler = b
+  // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE,
+  // otherwise the chip will buffer data.
+  return (uint16_t) ((uint16_t)a << 8 | 0x80 | b);
+}
+
+// calculate lcr value from data coding
+static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) {
+  uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
+  TU_VERIFY(data_bits >= 5 && data_bits <= 8, 0);
+  lcr |= (uint8_t) (data_bits - 5);
+
+  switch(parity) {
+    case CDC_LINE_CODING_PARITY_NONE:
+      break;
+
+    case CDC_LINE_CODING_PARITY_ODD:
+      lcr |= CH34X_LCR_ENABLE_PAR;
+      break;
+
+    case CDC_LINE_CODING_PARITY_EVEN:
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN;
+      break;
+
+    case CDC_LINE_CODING_PARITY_MARK:
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE;
+      break;
+
+    case CDC_LINE_CODING_PARITY_SPACE:
+      lcr |= CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN;
+      break;
+
+    default: break;
+  }
+
+  // 1.5 stop bits not supported
+  TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0);
+  if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
+    lcr |= CH34X_LCR_STOP_BITS_2;
+  }
+
+  return lcr;
+}
+
+
+#endif // CFG_TUH_CDC_CH34X
+
 #endif
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 9e5edd94e..d512a23a5 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -148,8 +148,11 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 // Request to set baudrate
 bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
-// Request to Set Line Coding (ACM only)
-// Should only use if you don't work with serial devices such as FTDI/CP210x
+// Request to set data format
+bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to Set Line Coding = baudrate + data format
+// Note: only implemented by ACM and CH34x, not supported by FTDI and CP210x yet
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Request to Get Line Coding (ACM only)
@@ -159,15 +162,13 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 
 // Connect by set both DTR, RTS
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data);
 }
 
 // Disconnect by clear both DTR, RTS
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data);
 }
 
diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h
new file mode 100644
index 000000000..c18066f57
--- /dev/null
+++ b/src/class/cdc/serial/ch34x.h
@@ -0,0 +1,84 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Heiko Kuester
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CH34X_H_
+#define _CH34X_H_
+
+// There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found
+// - https://github.com/WCHSoftGroup/ch341ser_linux
+// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
+// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
+
+// set line_coding @ enumeration
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM
+#else // this default is necessary to work properly
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+#endif
+
+// USB requests
+#define CH34X_REQ_READ_VERSION 0x5F // dec  95
+#define CH34X_REQ_WRITE_REG    0x9A // dec 154
+#define CH34X_REQ_READ_REG     0x95 // dec 149
+#define CH34X_REQ_SERIAL_INIT  0xA1 // dec 161
+#define CH34X_REQ_MODEM_CTRL   0xA4 // dev 164
+
+// registers
+#define CH34X_REG_BREAK        0x05
+#define CH34X_REG_PRESCALER    0x12
+#define CH34X_REG_DIVISOR      0x13
+#define CH34X_REG_LCR          0x18
+#define CH34X_REG_LCR2         0x25
+#define CH34X_REG_MCR_MSR      0x06
+#define CH34X_REG_MCR_MSR2     0x07
+#define CH34X_NBREAK_BITS      0x01
+
+#define CH341_REG_0x0F         0x0F // undocumented register
+#define CH341_REG_0x2C         0x2C // undocumented register
+#define CH341_REG_0x27         0x27 // hardware flow control (cts/rts)
+
+#define CH34X_REG16_DIVISOR_PRESCALER  TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER)
+#define CH32X_REG16_LCR2_LCR           TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR)
+
+// modem control bits
+#define CH34X_BIT_RTS ( 1 << 6 )
+#define CH34X_BIT_DTR ( 1 << 5 )
+
+// line control bits
+#define CH34X_LCR_ENABLE_RX    0x80
+#define CH34X_LCR_ENABLE_TX    0x40
+#define CH34X_LCR_MARK_SPACE   0x20
+#define CH34X_LCR_PAR_EVEN     0x10
+#define CH34X_LCR_ENABLE_PAR   0x08
+#define CH34X_LCR_PAR_MASK     0x38 // all parity bits
+#define CH34X_LCR_STOP_BITS_2  0x04
+#define CH34X_LCR_CS8          0x03
+#define CH34X_LCR_CS7          0x02
+#define CH34X_LCR_CS6          0x01
+#define CH34X_LCR_CS5          0x00
+#define CH34X_LCR_CS_MASK      0x03 // all CSx bits
+
+#endif /* _CH34X_H_ */
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index db52b503f..709fa3dd8 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -50,6 +50,7 @@ typedef struct
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
+  bool mounted;           // Enumeration is complete
 
   uint8_t itf_protocol;   // None, Keyboard, Mouse
   uint8_t protocol_mode;  // Boot (0) or Report protocol (1)
@@ -139,7 +140,8 @@ uint8_t tuh_hid_itf_get_total_count(void)
 bool tuh_hid_mounted(uint8_t daddr, uint8_t idx)
 {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
-  return p_hid != NULL;
+  TU_VERIFY(p_hid);
+  return p_hid->mounted;
 }
 
 bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info)
@@ -463,6 +465,7 @@ void hidh_close(uint8_t daddr)
       TU_LOG_DRV("  HIDh close addr = %u index = %u\r\n", daddr, i);
       if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
       p_hid->daddr = 0;
+      p_hid->mounted = false;
     }
   }
 }
@@ -632,6 +635,7 @@ static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t con
 {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid, );
+  p_hid->mounted = true;
 
   // enumeration is complete
   if (tuh_hid_mount_cb) tuh_hid_mount_cb(daddr, idx, desc_report, desc_len);
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 389a29696..a68cb2156 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -49,10 +49,8 @@ typedef struct
   uint8_t rx_ff_buf[CFG_TUD_VENDOR_RX_BUFSIZE];
   uint8_t tx_ff_buf[CFG_TUD_VENDOR_TX_BUFSIZE];
 
-#if CFG_FIFO_MUTEX
-  osal_mutex_def_t rx_ff_mutex;
-  osal_mutex_def_t tx_ff_mutex;
-#endif
+  OSAL_MUTEX_DEF(rx_ff_mutex);
+  OSAL_MUTEX_DEF(tx_ff_mutex);
 
   // Endpoint Transfer buffer
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_VENDOR_EPSIZE];
@@ -183,10 +181,8 @@ void vendord_init(void)
     tu_fifo_config(&p_itf->rx_ff, p_itf->rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, 1, false);
     tu_fifo_config(&p_itf->tx_ff, p_itf->tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, 1, false);
 
-#if CFG_FIFO_MUTEX
     tu_fifo_config_mutex(&p_itf->rx_ff, NULL, osal_mutex_create(&p_itf->rx_ff_mutex));
     tu_fifo_config_mutex(&p_itf->tx_ff, osal_mutex_create(&p_itf->tx_ff_mutex), NULL);
-#endif
   }
 }
 
diff --git a/src/class/video/video.h b/src/class/video/video.h
index d9880c291..6319c6536 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -29,6 +29,10 @@
 
 #include "common/tusb_common.h"
 
+enum {
+  VIDEO_BCD_1_50 = 0x0150,
+};
+
 // Table 3-19 Color Matching Descriptor
 typedef enum {
   VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00,
@@ -198,55 +202,98 @@ typedef enum {
 } video_terminal_type_t;
 
 //--------------------------------------------------------------------+
-// Descriptors
+// Video Control (VC) Descriptors
 //--------------------------------------------------------------------+
 
 /* 2.3.4.2 */
+#define tusb_desc_video_control_header_nitf_t(_nitf) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint16_t bcdUVC; \
+    uint16_t wTotalLength; \
+    uint32_t dwClockFrequency; /* deprecated */ \
+    uint8_t  bInCollection; \
+    uint8_t  baInterfaceNr[_nitf]; \
+  }
+
+typedef tusb_desc_video_control_header_nitf_t()  tusb_desc_video_control_header_t;
+typedef tusb_desc_video_control_header_nitf_t(1) tusb_desc_video_control_header_1itf_t;
+typedef tusb_desc_video_control_header_nitf_t(2) tusb_desc_video_control_header_2itf_t;
+typedef tusb_desc_video_control_header_nitf_t(3) tusb_desc_video_control_header_3itf_t;
+typedef tusb_desc_video_control_header_nitf_t(4) tusb_desc_video_control_header_4itf_t;
+
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
   uint8_t  bDescriptorSubType;
-  uint16_t bcdUVC;
-  uint16_t wTotalLength;
-  uint32_t dwClockFrequency;
-  uint8_t  bInCollection;
-  uint8_t  baInterfaceNr[];
-} tusb_desc_cs_video_ctl_itf_hdr_t;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  iTerminal;
+} tusb_desc_video_control_input_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_input_terminal_t) == 8, "size is not correct");
 
-/* 2.4.3.3 */
 typedef struct TU_ATTR_PACKED {
-  uint8_t bHeaderLength;
-  union {
-    uint8_t bmHeaderInfo;
-    struct {
-      uint8_t FrameID:              1;
-      uint8_t EndOfFrame:           1;
-      uint8_t PresentationTime:     1;
-      uint8_t SourceClockReference: 1;
-      uint8_t PayloadSpecific:      1;
-      uint8_t StillImage:           1;
-      uint8_t Error:                1;
-      uint8_t EndOfHeader:          1;
-    };
-  };
-} tusb_video_payload_header_t;
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  bSourceID;
+  uint8_t  iTerminal;
+} tusb_desc_video_control_output_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_output_terminal_t) == 9, "size is not correct");
 
-/* 3.9.2.1 */
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
   uint8_t  bDescriptorSubType;
-  uint8_t  bNumFormats;
-  uint16_t wTotalLength;
-  uint8_t  bEndpointAddress;
-  uint8_t  bmInfo;
-  uint8_t  bTerminalLink;
-  uint8_t  bStillCaptureMethod;
-  uint8_t  bTriggerSupport;
-  uint8_t  bTriggerUsage;
+  uint8_t  bTerminalID;
+  uint16_t wTerminalType;
+  uint8_t  bAssocTerminal;
+  uint8_t  iTerminal;
+
+  uint16_t wObjectiveFocalLengthMin;
+  uint16_t wObjectiveFocalLengthMax;
+  uint16_t wOcularFocalLength;
   uint8_t  bControlSize;
-  uint8_t  bmaControls[];
-} tusb_desc_cs_video_stm_itf_in_hdr_t;
+  uint8_t  bmControls[3];
+} tusb_desc_video_control_camera_terminal_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_control_camera_terminal_t) == 18, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Video Streaming (VS) Descriptors
+//--------------------------------------------------------------------+
+
+/* 3.9.2.1 */
+#define tusb_desc_video_streaming_input_header_nbyte_t(_nb) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint8_t  bNumFormats; /* Number of video payload Format descriptors for this interface */ \
+    uint16_t wTotalLength; \
+    uint8_t  bEndpointAddress; \
+    uint8_t  bmInfo; /* Bit 0: dynamic format change supported */ \
+    uint8_t  bTerminalLink; \
+    uint8_t  bStillCaptureMethod; \
+    uint8_t  bTriggerSupport; /* Hardware trigger supported */ \
+    uint8_t  bTriggerUsage; \
+    uint8_t  bControlSize; /* sizeof of each control item */ \
+    uint8_t  bmaControls[_nb]; \
+  }
+
+typedef tusb_desc_video_streaming_input_header_nbyte_t() tusb_desc_video_streaming_input_header_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(1) tusb_desc_video_streaming_input_header_1byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(2) tusb_desc_video_streaming_input_header_2byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(3) tusb_desc_video_streaming_input_header_3byte_t;
+typedef tusb_desc_video_streaming_input_header_nbyte_t(4) tusb_desc_video_streaming_input_header_4byte_t;
 
 /* 3.9.2.2 */
 typedef struct TU_ATTR_PACKED {
@@ -259,7 +306,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bTerminalLink;
   uint8_t  bControlSize;
   uint8_t  bmaControls[];
-} tusb_desc_cs_video_stm_itf_out_hdr_t;
+} tusb_desc_video_streaming_output_header_t;
 
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -285,14 +332,33 @@ typedef struct TU_ATTR_PACKED {
       uint8_t  bmaControls[];
     } output;
   };
-} tusb_desc_cs_video_stm_itf_hdr_t;
+} tusb_desc_video_streaming_inout_header_t;
+
+// 3.9.2.6 Color Matching Descriptor
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bColorPrimaries;
+  uint8_t  bTransferCharacteristics;
+  uint8_t  bMatrixCoefficients;
+} tusb_desc_video_streaming_color_matching_t;
 
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_streaming_color_matching_t) == 6, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Format and Frame Descriptor
+// Note: bFormatIndex & bFrameIndex are 1-based index
+//--------------------------------------------------------------------+
+
+//------------- Uncompressed -------------//
+// Uncompressed payload specs: 3.1.1 format descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bDescriptorSubType;
   uint8_t bFormatIndex;
-  uint8_t bNumFrameDescriptors;
+  uint8_t bNumFrameDescriptors; // Number of frame descriptors for this format
   uint8_t guidFormat[16];
   uint8_t bBitsPerPixel;
   uint8_t bDefaultFrameIndex;
@@ -300,22 +366,65 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bAspectRatioY;
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
-} tusb_desc_cs_video_fmt_uncompressed_t;
-
+} tusb_desc_video_format_uncompressed_t;
+
+// Uncompressed payload specs: 3.1.2 frame descriptor
+#define tusb_desc_video_frame_uncompressed_nint_t(_nint) \
+  struct TU_ATTR_PACKED { \
+    uint8_t  bLength; \
+    uint8_t  bDescriptorType; \
+    uint8_t  bDescriptorSubType; \
+    uint8_t  bFrameIndex; \
+    uint8_t  bmCapabilities; \
+    uint16_t wWidth; \
+    uint16_t wHeight; \
+    uint32_t dwMinBitRate; \
+    uint32_t dwMaxBitRate; \
+    uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \
+    uint32_t dwDefaultFrameInterval; \
+    uint8_t  bFrameIntervalType; \
+    uint32_t dwFrameInterval[_nint]; \
+  }
+
+typedef tusb_desc_video_frame_uncompressed_nint_t() tusb_desc_video_frame_uncompressed_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(1) tusb_desc_video_frame_uncompressed_1int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(2) tusb_desc_video_frame_uncompressed_2int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(3) tusb_desc_video_frame_uncompressed_3int_t;
+typedef tusb_desc_video_frame_uncompressed_nint_t(4) tusb_desc_video_frame_uncompressed_4int_t;
+
+// continuous = 3 intervals: min, max, step
+typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_uncompressed_continuous_t;
+
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_frame_uncompressed_continuous_t) == 38, "size is not correct");
+
+//------------- MJPEG -------------//
+// MJPEG payload specs: 3.1.1 format descriptor
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bDescriptorSubType;
   uint8_t bFormatIndex;
   uint8_t bNumFrameDescriptors;
-  uint8_t bmFlags;
+  uint8_t bmFlags; // Bit 0: fixed size samples (1 = yes)
   uint8_t bDefaultFrameIndex;
   uint8_t bAspectRatioX;
   uint8_t bAspectRatioY;
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
-} tusb_desc_cs_video_fmt_mjpeg_t;
+} tusb_desc_video_format_mjpeg_t;
 
+// MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
+typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
+typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t;
+typedef tusb_desc_video_frame_uncompressed_2int_t tusb_desc_video_frame_mjpeg_2int_t;
+typedef tusb_desc_video_frame_uncompressed_3int_t tusb_desc_video_frame_mjpeg_3int_t;
+typedef tusb_desc_video_frame_uncompressed_4int_t tusb_desc_video_frame_mjpeg_4int_t;
+
+// continuous = 3 intervals: min, max, step
+typedef tusb_desc_video_frame_mjpeg_3int_t tusb_desc_video_frame_mjpeg_continuous_t;
+
+//------------- DV -------------//
+// DV payload specs: 3.1.1
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
@@ -323,8 +432,9 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bFormatIndex;
   uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
   uint8_t  bFormatType;
-} tusb_desc_cs_video_fmt_dv_t;
+} tusb_desc_video_format_dv_t;
 
+// Frame Based payload specs: 3.1.1
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
@@ -339,25 +449,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bmInterlaceFlags;
   uint8_t bCopyProtect;
   uint8_t bVaribaleSize;
-} tusb_desc_cs_video_fmt_frame_based_t;
-
-typedef struct TU_ATTR_PACKED {
-  uint8_t  bLength;
-  uint8_t  bDescriptorType;
-  uint8_t  bDescriptorSubType;
-  uint8_t  bFrameIndex;
-  uint8_t  bmCapabilities;
-  uint16_t wWidth;
-  uint16_t wHeight;
-  uint32_t dwMinBitRate;
-  uint32_t dwMaxBitRate;
-  uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
-  uint32_t dwDefaultFrameInterval;
-  uint8_t  bFrameIntervalType;
-  uint32_t dwFrameInterval[];
-} tusb_desc_cs_video_frm_uncompressed_t;
-
-typedef tusb_desc_cs_video_frm_uncompressed_t tusb_desc_cs_video_frm_mjpeg_t;
+} tusb_desc_video_format_framebased_t;
 
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -373,12 +465,30 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bFrameIntervalType;
   uint32_t dwBytesPerLine;
   uint32_t dwFrameInterval[];
-} tusb_desc_cs_video_frm_frame_based_t;
+} tusb_desc_video_frame_framebased_t;
 
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
 
+/* 2.4.3.3 */
+typedef struct TU_ATTR_PACKED {
+  uint8_t bHeaderLength;
+  union {
+    uint8_t bmHeaderInfo;
+    struct {
+      uint8_t FrameID:              1;
+      uint8_t EndOfFrame:           1;
+      uint8_t PresentationTime:     1;
+      uint8_t SourceClockReference: 1;
+      uint8_t PayloadSpecific:      1;
+      uint8_t StillImage:           1;
+      uint8_t Error:                1;
+      uint8_t EndOfHeader:          1;
+    };
+  };
+} tusb_video_payload_header_t;
+
 /* 4.3.1.1 */
 typedef struct TU_ATTR_PACKED {
   union {
@@ -537,7 +647,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 /* Motion-JPEG 3.1.1 Table 3-2 and 3-4 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \
   TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
-  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_MJPEG, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_MJPEG, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 3b29454a3..1affd615e 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -50,17 +50,17 @@
 
 typedef struct {
   tusb_desc_interface_t            std;
-  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
+  tusb_desc_video_control_header_t ctl;
 } tusb_desc_vc_itf_t;
 
 typedef struct {
   tusb_desc_interface_t            std;
-  tusb_desc_cs_video_stm_itf_hdr_t stm;
+  tusb_desc_video_streaming_inout_header_t stm;
 } tusb_desc_vs_itf_t;
 
 typedef union {
-  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
-  tusb_desc_cs_video_stm_itf_hdr_t stm;
+  tusb_desc_video_control_header_t ctl;
+  tusb_desc_video_streaming_inout_header_t stm;
 } tusb_desc_video_itf_hdr_t;
 
 typedef struct TU_ATTR_PACKED {
@@ -78,9 +78,9 @@ typedef union {
     uint8_t bFormatIndex;
     uint8_t bNumFrameDescriptors;
   };
-  tusb_desc_cs_video_fmt_uncompressed_t uncompressed;
-  tusb_desc_cs_video_fmt_mjpeg_t        mjpeg;
-  tusb_desc_cs_video_fmt_frame_based_t  frame_based;
+  tusb_desc_video_format_uncompressed_t uncompressed;
+  tusb_desc_video_format_mjpeg_t        mjpeg;
+  tusb_desc_video_format_framebased_t  frame_based;
 } tusb_desc_cs_video_fmt_t;
 
 typedef union {
@@ -93,9 +93,9 @@ typedef union {
     uint16_t wWidth;
     uint16_t wHeight;
   };
-  tusb_desc_cs_video_frm_uncompressed_t uncompressed;
-  tusb_desc_cs_video_frm_mjpeg_t        mjpeg;
-  tusb_desc_cs_video_frm_frame_based_t  frame_based;
+  tusb_desc_video_frame_uncompressed_t uncompressed;
+  tusb_desc_video_frame_mjpeg_t        mjpeg;
+  tusb_desc_video_frame_framebased_t  frame_based;
 } tusb_desc_cs_video_frm_t;
 
 /* video streaming interface */
@@ -434,8 +434,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   uint_fast32_t interval_ms = interval / 10000;
   TU_ASSERT(interval_ms);
   uint_fast32_t payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
-  if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+  if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) {
     payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
+  }
   param->dwMaxPayloadTransferSize = payload_size;
   return true;
 }
@@ -577,8 +578,9 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       } else {
         payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
       }
-      if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+      if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size) {
         payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
+      }
       param->dwMaxPayloadTransferSize = payload_size;
     }
     return true;
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index caeb5f2ef..1f08ce4ed 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -37,6 +37,7 @@
 #define TU_ARRAY_SIZE(_arr)   ( sizeof(_arr) / sizeof(_arr[0]) )
 #define TU_MIN(_x, _y)        ( ( (_x) < (_y) ) ? (_x) : (_y) )
 #define TU_MAX(_x, _y)        ( ( (_x) > (_y) ) ? (_x) : (_y) )
+#define TU_DIV_CEIL(n, d)     (((n) + (d) - 1) / (d))
 
 #define TU_U16(_high, _low)   ((uint16_t) (((_high) << 8) | (_low)))
 #define TU_U16_HIGH(_u16)     ((uint8_t) (((_u16) >> 8) & 0x00ff))
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index fab680989..2c5dce723 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -44,43 +44,38 @@
  *------------------------------------------------------------------*/
 
 /// defined base on EHCI specs value for Endpoint Speed
-typedef enum
-{
+typedef enum {
   TUSB_SPEED_FULL = 0,
   TUSB_SPEED_LOW  = 1,
   TUSB_SPEED_HIGH = 2,
   TUSB_SPEED_INVALID = 0xff,
-}tusb_speed_t;
+} tusb_speed_t;
 
 /// defined base on USB Specs Endpoint's bmAttributes
-typedef enum
-{
+typedef enum {
   TUSB_XFER_CONTROL = 0 ,
   TUSB_XFER_ISOCHRONOUS ,
   TUSB_XFER_BULK        ,
   TUSB_XFER_INTERRUPT
-}tusb_xfer_type_t;
+} tusb_xfer_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_DIR_OUT = 0,
   TUSB_DIR_IN  = 1,
 
   TUSB_DIR_IN_MASK = 0x80
-}tusb_dir_t;
+} tusb_dir_t;
 
-enum
-{
+enum {
   TUSB_EPSIZE_BULK_FS = 64,
-  TUSB_EPSIZE_BULK_HS= 512,
+  TUSB_EPSIZE_BULK_HS = 512,
 
   TUSB_EPSIZE_ISO_FS_MAX = 1023,
   TUSB_EPSIZE_ISO_HS_MAX = 1024,
 };
 
-/// Isochronous End Point Attributes
-typedef enum
-{
+/// Isochronous Endpoint Attributes
+typedef enum {
   TUSB_ISO_EP_ATT_NO_SYNC         = 0x00,
   TUSB_ISO_EP_ATT_ASYNCHRONOUS    = 0x04,
   TUSB_ISO_EP_ATT_ADAPTIVE        = 0x08,
@@ -88,11 +83,10 @@ typedef enum
   TUSB_ISO_EP_ATT_DATA            = 0x00, ///< Data End Point
   TUSB_ISO_EP_ATT_EXPLICIT_FB     = 0x10, ///< Feedback End Point
   TUSB_ISO_EP_ATT_IMPLICIT_FB     = 0x20, ///< Data endpoint that also serves as an implicit feedback
-}tusb_iso_ep_attribute_t;
+} tusb_iso_ep_attribute_t;
 
 /// USB Descriptor Types
-typedef enum
-{
+typedef enum {
   TUSB_DESC_DEVICE                = 0x01,
   TUSB_DESC_CONFIGURATION         = 0x02,
   TUSB_DESC_STRING                = 0x03,
@@ -119,10 +113,9 @@ typedef enum
 
   TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION     = 0x30,
   TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31
-}tusb_desc_type_t;
+} tusb_desc_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_GET_STATUS        = 0  ,
   TUSB_REQ_CLEAR_FEATURE     = 1  ,
   TUSB_REQ_RESERVED          = 2  ,
@@ -136,25 +129,22 @@ typedef enum
   TUSB_REQ_GET_INTERFACE     = 10 ,
   TUSB_REQ_SET_INTERFACE     = 11 ,
   TUSB_REQ_SYNCH_FRAME       = 12
-}tusb_request_code_t;
+} tusb_request_code_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_FEATURE_EDPT_HALT     = 0,
   TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1,
   TUSB_REQ_FEATURE_TEST_MODE     = 2
-}tusb_request_feature_selector_t;
+} tusb_request_feature_selector_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_TYPE_STANDARD = 0,
   TUSB_REQ_TYPE_CLASS,
   TUSB_REQ_TYPE_VENDOR,
   TUSB_REQ_TYPE_INVALID
 } tusb_request_type_t;
 
-typedef enum
-{
+typedef enum {
   TUSB_REQ_RCPT_DEVICE =0,
   TUSB_REQ_RCPT_INTERFACE,
   TUSB_REQ_RCPT_ENDPOINT,
@@ -162,8 +152,7 @@ typedef enum
 } tusb_request_recipient_t;
 
 // https://www.usb.org/defined-class-codes
-typedef enum
-{
+typedef enum {
   TUSB_CLASS_UNSPECIFIED          = 0    ,
   TUSB_CLASS_AUDIO                = 1    ,
   TUSB_CLASS_CDC                  = 2    ,
@@ -187,26 +176,23 @@ typedef enum
   TUSB_CLASS_MISC                 = 0xEF ,
   TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE ,
   TUSB_CLASS_VENDOR_SPECIFIC      = 0xFF
-}tusb_class_code_t;
+} tusb_class_code_t;
 
 typedef enum
 {
   MISC_SUBCLASS_COMMON = 2
 }misc_subclass_type_t;
 
-typedef enum
-{
+typedef enum {
   MISC_PROTOCOL_IAD = 1
-}misc_protocol_type_t;
+} misc_protocol_type_t;
 
-typedef enum
-{
+typedef enum {
   APP_SUBCLASS_USBTMC = 0x03,
   APP_SUBCLASS_DFU_RUNTIME = 0x01
 } app_subclass_type_t;
 
-typedef enum
-{
+typedef enum {
   DEVICE_CAPABILITY_WIRELESS_USB               = 0x01,
   DEVICE_CAPABILITY_USB20_EXTENSION            = 0x02,
   DEVICE_CAPABILITY_SUPERSPEED_USB             = 0x03,
@@ -223,7 +209,7 @@ typedef enum
   DEVICE_CAPABILITY_AUTHENTICATION             = 0x0E,
   DEVICE_CAPABILITY_BILLBOARD_EX               = 0x0F,
   DEVICE_CAPABILITY_CONFIGURATION_SUMMARY      = 0x10
-}device_capability_type_t;
+} device_capability_type_t;
 
 enum {
   TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5),
@@ -235,28 +221,25 @@ enum {
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
-typedef enum
-{
+typedef enum {
   XFER_RESULT_SUCCESS = 0,
   XFER_RESULT_FAILED,
   XFER_RESULT_STALLED,
   XFER_RESULT_TIMEOUT,
   XFER_RESULT_INVALID
-}xfer_result_t;
+} xfer_result_t;
 
-enum // TODO remove
-{
+// TODO remove
+enum {
   DESC_OFFSET_LEN  = 0,
   DESC_OFFSET_TYPE = 1
 };
 
-enum
-{
+enum {
   INTERFACE_INVALID_NUMBER = 0xff
 };
 
-typedef enum
-{
+typedef enum {
   MS_OS_20_SET_HEADER_DESCRIPTOR       = 0x00,
   MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01,
   MS_OS_20_SUBSET_HEADER_FUNCTION      = 0x02,
@@ -268,16 +251,14 @@ typedef enum
   MS_OS_20_FEATURE_VENDOR_REVISION     = 0x08
 } microsoft_os_20_type_t;
 
-enum
-{
+enum {
   CONTROL_STAGE_IDLE,
   CONTROL_STAGE_SETUP,
   CONTROL_STAGE_DATA,
   CONTROL_STAGE_ACK
 };
 
-enum
-{
+enum {
   TUSB_INDEX_INVALID_8 = 0xFFu
 };
 
@@ -290,8 +271,7 @@ TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
 /// USB Device Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes.
   uint8_t  bDescriptorType    ; ///< DEVICE Descriptor Type.
   uint16_t bcdUSB             ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant.
@@ -314,8 +294,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct");
 
 // USB Binary Device Object Store (BOS) Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< CONFIGURATION Descriptor Type
   uint16_t wTotalLength    ; ///< Total length of data returned for this descriptor
@@ -325,8 +304,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_bos_t) == 5, "size is not correct");
 
 /// USB Configuration Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength             ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType     ; ///< CONFIGURATION Descriptor Type
   uint16_t wTotalLength        ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration.
@@ -341,8 +319,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_configuration_t) == 9, "size is not correct");
 
 /// USB Interface Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType    ; ///< INTERFACE Descriptor Type
 
@@ -358,8 +335,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct");
 
 /// USB Endpoint Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength          ; // Size of this descriptor in bytes
   uint8_t  bDescriptorType  ; // ENDPOINT Descriptor Type
 
@@ -379,8 +355,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_endpoint_t) == 7, "size is not correct");
 
 /// USB Other Speed Configuration Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength             ; ///< Size of descriptor
   uint8_t  bDescriptorType     ; ///< Other_speed_Configuration Type
   uint16_t wTotalLength        ; ///< Total length of data returned
@@ -393,8 +368,7 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_other_speed_t;
 
 /// USB Device Qualifier Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of descriptor
   uint8_t  bDescriptorType    ; ///< Device Qualifier Type
   uint16_t bcdUSB             ; ///< USB specification version number (e.g., 0200H for V2.00)
@@ -411,8 +385,7 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct");
 
 /// USB Interface Association Descriptor (IAD ECN)
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength           ; ///< Size of descriptor
   uint8_t bDescriptorType   ; ///< Other_speed_Configuration Type
 
@@ -426,17 +399,17 @@ typedef struct TU_ATTR_PACKED
   uint8_t iFunction         ; ///< Index of the string descriptor describing the interface association.
 } tusb_desc_interface_assoc_t;
 
+TU_VERIFY_STATIC( sizeof(tusb_desc_interface_assoc_t) == 8, "size is not correct");
+
 // USB String Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< Descriptor Type
   uint16_t unicode_string[];
 } tusb_desc_string_t;
 
 // USB Binary Device Object Store (BOS)
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType ;
   uint8_t bDevCapabilityType;
@@ -445,9 +418,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t CapabilityData[];
 } tusb_desc_bos_platform_t;
 
-// USB WebuSB URL Descriptor
-typedef struct TU_ATTR_PACKED
-{
+// USB WebUSB URL Descriptor
+typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bScheme;
@@ -455,8 +427,7 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_webusb_url_t;
 
 // DFU Functional Descriptor
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
 
@@ -481,7 +452,7 @@ typedef struct TU_ATTR_PACKED
 //
 //--------------------------------------------------------------------+
 
-typedef struct TU_ATTR_PACKED{
+typedef struct TU_ATTR_PACKED {
   union {
     struct TU_ATTR_PACKED {
       uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
@@ -500,7 +471,6 @@ typedef struct TU_ATTR_PACKED{
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
-
 TU_ATTR_PACKED_END  // End of all packed definitions
 TU_ATTR_BIT_FIELD_ORDER_END
 
@@ -509,36 +479,30 @@ TU_ATTR_BIT_FIELD_ORDER_END
 //--------------------------------------------------------------------+
 
 // Get direction from Endpoint address
-TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr) {
   return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
 }
 
 // Get Endpoint number from address
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr) {
   return (uint8_t)(addr & (~TUSB_DIR_IN_MASK));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) {
   return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) {
   return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
 }
 
 #if CFG_TUSB_DEBUG
-TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) {
   tu_static const char *str[] = {"out", "in"};
   return str[dir];
 }
 
-TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
-{
+TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) {
   tu_static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
 }
@@ -549,21 +513,18 @@ TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_
 //--------------------------------------------------------------------+
 
 // return next descriptor
-TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) {
   uint8_t const* desc8 = (uint8_t const*) desc;
   return desc8 + desc8[DESC_OFFSET_LEN];
 }
 
 // get descriptor type
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) {
   return ((uint8_t const*) desc)[DESC_OFFSET_TYPE];
 }
 
 // get descriptor length
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) {
   return ((uint8_t const*) desc)[DESC_OFFSET_LEN];
 }
 
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index ac93632be..3e15d51c6 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -1130,8 +1130,8 @@ void dcd_int_handler(uint8_t rhport) {
     dwc2->gotgint = otg_int;
   }
 
-  if (int_status & GINTSTS_SOF) {
-    dwc2->gotgint = GINTSTS_SOF;
+  if(int_status & GINTSTS_SOF) {
+    dwc2->gintsts = GINTSTS_SOF;
 
     if (_sof_en) {
       uint32_t frame = (dwc2->dsts & (DSTS_FNSOF)) >> 8;
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 57f026312..767323bdd 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -472,6 +472,23 @@
     {0x10C4, 0xEA60}, {0x10C4, 0xEA70}
 #endif
 
+#ifndef CFG_TUH_CDC_CH34X
+  // CH34X is not part of CDC class, only to re-use CDC driver API
+  #define CFG_TUH_CDC_CH34X 0
+#endif
+
+#ifndef CFG_TUH_CDC_CH34X_VID_PID_LIST
+  // List of product IDs that can use the CH34X CDC driver
+  #define CFG_TUH_CDC_CH34X_VID_PID_LIST \
+    { 0x1a86, 0x5523 }, /* ch341 chip */ \
+    { 0x1a86, 0x7522 }, /* ch340k chip */ \
+    { 0x1a86, 0x7523 }, /* ch340 chip */ \
+    { 0x1a86, 0xe523 }, /* ch330 chip */ \
+    { 0x4348, 0x5523 }, /* ch340 custom chip */ \
+    { 0x2184, 0x0057 }, /* overtaken from Linux Kernel driver /drivers/usb/serial/ch341.c */ \
+    { 0x9986, 0x7523 }  /* overtaken from Linux Kernel driver /drivers/usb/serial/ch341.c */
+#endif
+
 #ifndef CFG_TUH_HID
   #define CFG_TUH_HID    0
 #endif
diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py
index 7c662aeea..7f03ce43f 100644
--- a/test/hil/hil_test.py
+++ b/test/hil/hil_test.py
@@ -364,8 +364,15 @@ def main(config_file, board):
 
             print(f'  {test} ...', end='')
 
-            # flash firmware
-            ret = globals()[f'flash_{flasher}'](item, fw)
+            # flash firmware. It may fail randomly, retry a few times
+            for i in range(3):
+                ret = globals()[f'flash_{flasher}'](item, fw)
+                if ret.returncode == 0:
+                    break
+                else:
+                    print(f'Flashing failed, retry {i+1}')
+                    time.sleep(1)
+
             assert ret.returncode == 0, 'Flash failed\n' + ret.stdout.decode()
 
             # run test
-- 
cgit v1.3.1


From 45454c53f1d429a314115701ba2360591b811f50 Mon Sep 17 00:00:00 2001
From: Jerry Palacios <jerry.palacios@wavenumber.net>
Date: Wed, 7 Feb 2024 18:33:19 -0600
Subject: frdmmcxa153 files added

---
 hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h   | 149 ++++++++
 hw/bsp/mcxa/boards/frdmmcxa153/board.cmake    |  18 +
 hw/bsp/mcxa/boards/frdmmcxa153/board.h        |  66 ++++
 hw/bsp/mcxa/boards/frdmmcxa153/board.mk       |  26 ++
 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c | 468 ++++++++++++++++++++++++++
 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h | 170 ++++++++++
 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c      | 159 +++++++++
 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h      |  47 +++
 hw/bsp/mcxa/debug.jlinkscript                 |   5 +
 hw/bsp/mcxa/family.c                          | 163 +++++++++
 hw/bsp/mcxa/family.cmake                      | 110 ++++++
 hw/bsp/mcxa/family.mk                         |  42 +++
 src/common/tusb_mcu.h                         |   7 +
 src/portable/chipidea/ci_fs/ci_fs_mcxa.h      |  47 +++
 src/portable/chipidea/ci_fs/dcd_ci_fs.c       |   2 +
 src/tusb_option.h                             |   1 +
 16 files changed, 1480 insertions(+)
 create mode 100644 hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/board.cmake
 create mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/board.h
 create mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/board.mk
 create mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c
 create mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h
 create mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c
 create mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h
 create mode 100644 hw/bsp/mcxa/debug.jlinkscript
 create mode 100644 hw/bsp/mcxa/family.c
 create mode 100644 hw/bsp/mcxa/family.cmake
 create mode 100644 hw/bsp/mcxa/family.mk
 create mode 100644 src/portable/chipidea/ci_fs/ci_fs_mcxa.h

(limited to 'src')

diff --git a/hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6f10a7ab0
--- /dev/null
+++ b/hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/board.cmake b/hw/bsp/mcxa/boards/frdmmcxa153/board.cmake
new file mode 100644
index 000000000..7f3c6c665
--- /dev/null
+++ b/hw/bsp/mcxa/boards/frdmmcxa153/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT MCXA153)
+set(MCU_CORE MCXA153)
+
+set(JLINK_DEVICE MCXA153_M33)
+set(PYOCD_TARGET MCXA153)
+set(NXPLINK_DEVICE MCXA153:MCXA153)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXA153VLH
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/board.h b/hw/bsp/mcxa/boards/frdmmcxa153/board.h
new file mode 100644
index 000000000..d18175c3d
--- /dev/null
+++ b/hw/bsp/mcxa/boards/frdmmcxa153/board.h
@@ -0,0 +1,66 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_GateGPIO3
+#define LED_PIN               12 // red
+#define LED_STATE_ON          0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_GPIO           GPIO1
+#define BUTTON_CLK            kCLOCK_GateGPIO1
+#define BUTTON_PIN            7 //sw3
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART0
+
+static inline void board_uart_init_clock(void) {
+
+  /* attach 12 MHz clock to LPUART0 (debug console) */
+    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+}
+
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/board.mk b/hw/bsp/mcxa/boards/frdmmcxa153/board.mk
new file mode 100644
index 000000000..e8797cd95
--- /dev/null
+++ b/hw/bsp/mcxa/boards/frdmmcxa153/board.mk
@@ -0,0 +1,26 @@
+MCU_VARIANT = MCXA153
+MCU_CORE = MCXA153
+PORT = 0
+
+CFLAGS += \
+	-DCPU_MCXA153VLH \
+	-DCPU_MCXA153VLH_cm33_nodsp \
+	-DPRINTF_FLOAT_ENABLE=0 \
+	-DSCANF_FLOAT_ENABLE=0 \
+	-DPRINTF_ADVANCED_ENABLE=0 \
+	-DSCANF_ADVANCED_ENABLE=0 \
+	-mcpu=cortex-m33+nodsp+nofp+nosimd
+
+#FORCING NOT TO USE DPS AND FPU UNITS (THIS CHIP DOESN'T HAVE)
+CFLAGS += -D__SOFTFP__  
+# Undefine __ARM_FEATURE_DSP if it's already defined
+CFLAGS += -U__ARM_FEATURE_DSP
+# Define __ARM_FEATURE_DSP with the new value
+CFLAGS += -D__ARM_FEATURE_DSP=0
+ 
+
+JLINK_DEVICE = MCXA153
+PYOCD_TARGET = MCXA153
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c b/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c
new file mode 100644
index 000000000..f16bc51f6
--- /dev/null
+++ b/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v12.0
+processor: MCXA153
+package_id: MCXA153VLH
+mcu_data: ksdk2_0
+processor_version: 0.13.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "fsl_spc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockFRO96M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CPU_clock.outFreq, value: 12 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO12M */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO24M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 6 MHz}
+- {id: System_clock.outFreq, value: 24 MHz}
+settings:
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO24M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U);               /* !< Set AHBCLKDIV divider to value 2 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO48M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO48M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO64M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 64 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
+- {id: FRO_HF_clock.outFreq, value: 64 MHz}
+- {id: MAIN_clock.outFreq, value: 64 MHz}
+- {id: Slow_clock.outFreq, value: 16 MHz}
+- {id: System_clock.outFreq, value: 64 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 64 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO64M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(64000000U);               /*!< Enable FRO HF(64MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO96M
+called_from_default_init: true
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 96 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
+- {id: FRO_HF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: CLKOUTDIV_HALT, value: Enable}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO96M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(96000000U);               /*!< Enable FRO HF(96MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h b/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h
new file mode 100644
index 000000000..079d0d312
--- /dev/null
+++ b/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+ 
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK           24000000U  /*!< Core clock frequency: 24000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO24M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK           48000000U  /*!< Core clock frequency: 48000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK           64000000U  /*!< Core clock frequency: 64000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO64M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK           96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c b/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c
new file mode 100644
index 000000000..b0e6de560
--- /dev/null
+++ b/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+ 
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v14.0
+processor: MCXA153
+package_id: MCXA153VLH
+mcu_data: ksdk2_0
+processor_version: 0.14.3
+pin_labels:
+- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
+    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+    /* write to PORT0: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT0);
+
+    /* Write to GPIO3: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GateGPIO3);
+    /* Write to PORT3: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT3);
+    /* GPIO3 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+    /* PORT3 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+
+    const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
+                                       kPORT_PullDisable,
+                                       /* Low internal pull resistor value is selected. */
+                                       kPORT_LowPullResistor,
+                                       /* Fast slew rate is configured */
+                                       kPORT_FastSlewRate,
+                                       /* Passive input filter is disabled */
+                                       kPORT_PassiveFilterDisable,
+                                       /* Open drain output is disabled */
+                                       kPORT_OpenDrainDisable,
+                                       /* Low drive strength is configured */
+                                       kPORT_LowDriveStrength,
+                                       /* Normal drive strength is configured */
+                                       kPORT_NormalDriveStrength,
+                                       /* Pin is configured as P3_12 */
+                                       kPORT_MuxAlt0,
+                                       /* Digital input enabled */
+                                       kPORT_InputBufferEnable,
+                                       /* Digital input is not inverted */
+                                       kPORT_InputNormal,
+                                       /* Pin Control Register fields [15:0] are not locked */
+                                       kPORT_UnlockRegister};
+    /* PORT3_12 (pin 38) is configured as P3_12 */
+      PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
+
+    const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_RXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_2 (pin 51) is configured as LPUART0_RXD */
+    PORT_SetPinConfig(PORT0, 2U, &port0_2_pin51_config);
+
+    const port_pin_config_t port0_3_pin52_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_TXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_3 (pin 52) is configured as LPUART0_TXD */
+    PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
+
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h b/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h
new file mode 100644
index 000000000..06b6fdee9
--- /dev/null
+++ b/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcxa/debug.jlinkscript b/hw/bsp/mcxa/debug.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/mcxa/debug.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+  return 0;
+}
diff --git a/hw/bsp/mcxa/family.c b/hw/bsp/mcxa/family.c
new file mode 100644
index 000000000..97abc1bc3
--- /dev/null
+++ b/hw/bsp/mcxa/family.c
@@ -0,0 +1,163 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board_api.h"
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_lpuart.h"
+#include "board.h"
+
+#include "pin_mux.h"
+#include "clock_config.h"
+#include "fsl_common.h"
+
+
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void board_init(void)
+{
+  BOARD_InitPins();
+  BOARD_InitBootClocks();
+  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
+
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+  // LED
+  CLOCK_EnableClock(LED_CLK);
+  gpio_pin_config_t LED_RED_config = {
+      .pinDirection = kGPIO_DigitalOutput,
+      .outputLogic = 0U
+  };
+  
+  /* Initialize GPIO functionality on pin PIO3_12 (pin 38)  */
+  GPIO_PinInit(LED_GPIO, LED_PIN, &LED_RED_config);
+  board_led_write(1);
+
+  // Button
+#ifdef BUTTON_GPIO
+  CLOCK_EnableClock(BUTTON_CLK);
+  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+#endif
+
+#ifdef UART_DEV
+
+  CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+  CLOCK_AttachClk(kFRO12M_to_LPUART0);
+  RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = 115200;
+  uart_config.enableTx     = true;
+  uart_config.enableRx     = true; 
+  LPUART_Init(UART_DEV, &uart_config, 12000000u);
+
+
+#endif
+
+  // USB VBUS
+  /* PORT0 PIN22 configured as USB0_VBUS */
+
+#if PORT_SUPPORT_DEVICE(0)
+  // Port0 is Full Speed
+
+  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
+  CLOCK_EnableUsbfsClock();
+#endif
+
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+#ifdef BUTTON_GPIO
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#else
+  return 1;
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/mcxa/family.cmake b/hw/bsp/mcxa/family.cmake
new file mode 100644
index 000000000..0aa690afc
--- /dev/null
+++ b/hw/bsp/mcxa/family.cmake
@@ -0,0 +1,110 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS MCXA CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      # external driver
+      #lib/sct_neopixel/sct_neopixel.c
+
+      # driver
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+      # mcu
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+      )
+    #  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    #    )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      # driver
+      # mcu
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_sources(${BOARD_TARGET} PUBLIC
+        ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+        )
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_MCXA ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})  
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/mcxa/family.mk b/hw/bsp/mcxa/family.mk
new file mode 100644
index 000000000..b32282d04
--- /dev/null
+++ b/hw/bsp/mcxa/family.mk
@@ -0,0 +1,42 @@
+UF2_FAMILY_ID = 0x2abc77ec
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5		#not found
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
+
+CFLAGS += \
+  -flto \
+  -DCFG_TUSB_MCU=OPT_MCU_MCXA \
+  -DBOARD_TUD_RHPORT=0 
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
+# All source paths should be relative to the top level.
+LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
+
+# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+$(info "PORT0 Full Speed")
+CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
+
+SRC_C += \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c 
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers 
+	
+
+SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index e589c4c86..21ae3a71e 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -100,6 +100,13 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
+#elif TU_CHECK_MCU(OPT_MCU_MCXA)
+  // USB0 is chipidea FS
+  #define TUP_USBIP_CHIPIDEA_FS
+  #define TUP_USBIP_CHIPIDEA_FS_MCXA
+
+  #define TUP_DCD_ENDPOINT_MAX    16
+
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX)
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcxa.h b/src/portable/chipidea/ci_fs/ci_fs_mcxa.h
new file mode 100644
index 000000000..81786efdf
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/ci_fs_mcxa.h
@@ -0,0 +1,47 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_FS_MCXA_H
+#define _CI_FS_MCXA_H
+
+#include "fsl_device_registers.h"
+
+#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
+#define CI_REG                  CI_FS_REG(0)
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+#endif
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index 9327e09d8..08e73711f 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -35,6 +35,8 @@
   #include "ci_fs_kinetis.h"
 #elif defined(TUP_USBIP_CHIPIDEA_FS_MCX)
   #include "ci_fs_mcx.h"
+#elif defined(TUP_USBIP_CHIPIDEA_FS_MCXA)
+  #include "ci_fs_mcxa.h"
 #else
   #error "MCU is not supported"
 #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 767323bdd..fe9c44e96 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -175,6 +175,7 @@
 
 // NXP LPC MCX
 #define OPT_MCU_MCXN9            2300  ///< NXP MCX N9 Series
+#define OPT_MCU_MCXA             2301  ///< NXP MCX A Series
 
 // Check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
-- 
cgit v1.3.1


From 4d4e20b71efe8d9e1b5a141d84e058ff54801c67 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Thu, 8 Feb 2024 12:00:44 +0100
Subject: missing \r\n after TU_LOG_BUF => moved \r\n to tu_print_buf()

---
 src/common/tusb_debug.h | 1 +
 src/device/usbd.c       | 1 -
 src/host/usbh.c         | 2 --
 3 files changed, 1 insertion(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 8db1606ae..2e9f1d9cd 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -60,6 +60,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
 
 static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
   for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
+  tu_printf("\r\n");
 }
 
 // Log with Level
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 5c94ebcc5..be85d7769 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -500,7 +500,6 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 
       case DCD_EVENT_SETUP_RECEIVED:
         TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
-        TU_LOG_USBD("\r\n");
 
         // Mark as connected after receiving 1st setup packet.
         // But it is easier to set it every time instead of wasting time to check then set
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 67668cebe..f56290a0c 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -589,7 +589,6 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
               (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
                   tu_str_std_request[xfer->setup->bRequest] : "Class Request");
   TU_LOG_BUF_USBH(xfer->setup, 8);
-  TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb) {
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
@@ -662,7 +661,6 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   if (XFER_RESULT_SUCCESS != result) {
     TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     TU_LOG_BUF_USBH(request, 8);
-    TU_LOG_USBH("\r\n");
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);
-- 
cgit v1.3.1


From 68bb85840639b2a3d8c4ad51e31245bd039e5b9f Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Mon, 12 Feb 2024 16:12:32 +0100
Subject: nrf5x: Handle ISOOUT CRC errors

NRF5x USB controller can detect ISO OUT CRC errors.
In such case USBEVENT is signaled with EVENTCAUSE_ISOOUTCRC set.
Even if controller detects corrupted ISO OUT packet it allows
to data transfer from ednpoint to RAM however packet is corrupted
and code could just as well drop packet altogether.

With current implementation incoming ISO OUT packets were put in
FIFO and exact information how much data already in FIFO is correct
was hard to keep track of.
If was observed that on certain configurations HS hub when FS device
was connected occasionally sent invalid (short) packet. In such case
if packet length was reported odd audio stream was not recognizable any
more.

With this change corrupted packets are not passed to upper layers
and are silently dropped.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 4e702aed4..841cda752 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -653,7 +653,11 @@ void dcd_int_handler(uint8_t rhport)
     if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
     {
       iso_enabled = true;
-      xact_out_dma(EP_ISO_NUM);
+      // Transfer from endpoint to RAM only if data is not corrupted
+      if ((int_status & USBD_INTEN_USBEVENT_Msk) == 0 ||
+          (NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_ISOOUTCRC_Msk) == 0) {
+        xact_out_dma(EP_ISO_NUM);
+      }
     }
 
     // ISOIN: Notify client that data was transferred
@@ -683,7 +687,7 @@ void dcd_int_handler(uint8_t rhport)
   {
     TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
 
-    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk };
+    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk };
     uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
     NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt
 
-- 
cgit v1.3.1


From 79aecf3fb7d6a384eb745253d11a95d657469eed Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Wed, 14 Feb 2024 09:16:18 +0100
Subject: fixed #2469

---
 src/common/tusb_fifo.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index d6c3db4ce..76696396b 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -224,6 +224,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
       }
       break;
+    default: break;
   }
 }
 
-- 
cgit v1.3.1


From 5ca99800604ec3ed9d45bf4660db04101aa737ce Mon Sep 17 00:00:00 2001
From: Chris Desjardins <chris@arch-embedded.com>
Date: Thu, 15 Feb 2024 16:27:49 +0100
Subject: Do not enable the Mode mismatch interrupt source, it is not cleared

If this interrupt ever hits it will result in an infinite interrupt
loop as it is never cleared.
---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 3e15d51c6..3f00243e5 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -462,9 +462,7 @@ void dcd_init(uint8_t rhport) {
   dwc2->gotgint |= int_mask;
 
   // Required as part of core initialization.
-  // TODO: How should mode mismatch be handled? It will cause
-  // the core to stop working/require reset.
-  dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_MMISM | GINTMSK_RXFLVLM |
+  dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM |
                   GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
 
   // Enable global interrupt
-- 
cgit v1.3.1


From 27c125416a60986c4bce670097efbd88744fab9b Mon Sep 17 00:00:00 2001
From: Kai <60053077+kaidegit@users.noreply.github.com>
Date: Fri, 16 Feb 2024 15:16:17 +0800
Subject: use rt-thread 5+ mq recv api

---
 src/osal/osal_rtthread.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index 18eb9c693..d03b53bee 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 tfx2001 (2479727366@qq.com)
+ * Copyright (c) 2020 yekai (2857693944@qq.com)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -111,9 +112,12 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void *data, uint32_t msec) {
-
     rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec);
+#if RT_VERSION_MAJOR >= 5
+    return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) > 0;
+#else
     return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK;
+#endif  /* RT_VERSION_MAJOR >= 5 */
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
-- 
cgit v1.3.1


From e9dc8f3e7dc6799ad674139df97e253acc71f4d7 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 19 Feb 2024 18:12:03 +0700
Subject: fix wrong volatile usage in ohci gtd

---
 src/portable/ohci/ohci.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 4feefd771..94bad5df7 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -83,7 +83,7 @@ typedef struct TU_ATTR_ALIGNED(16)
   volatile uint32_t condition_code : 4;
 
 	// Word 1
-	volatile uint8_t* current_buffer_pointer;
+	uint8_t* volatile current_buffer_pointer;
 
 	// Word 2 : next TD
 	volatile uint32_t next;
-- 
cgit v1.3.1


From 3f2df94457e917dda2fed05c7ee17deefe55199e Mon Sep 17 00:00:00 2001
From: Bob Abeles <phil99boyd@gmail.com>
Date: Tue, 20 Feb 2024 08:16:39 -0800
Subject: video_device: fix uninitialized warning

---
 src/class/video/video_device.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 1affd615e..c33dfa0b0 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -559,6 +559,7 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
           uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
           if (num_intervals) {
             interval = 0;
+            interval_ms = 0;
           } else {
             interval = frm->uncompressed.dwFrameInterval[2];
             interval_ms = interval / 10000;
-- 
cgit v1.3.1


From 5c14bd13da211ff2679115b0dba96ac80c1a516c Mon Sep 17 00:00:00 2001
From: Jerry Palacios <jerry.palacios@wavenumber.net>
Date: Tue, 20 Feb 2024 18:02:42 -0600
Subject: MCX A and MCX N merged to MCX family

---
 README.rst                                    |   4 +-
 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h    | 149 ++++++++
 hw/bsp/mcx/boards/frdmmcxa153/board.cmake     |  23 ++
 hw/bsp/mcx/boards/frdmmcxa153/board.h         |  66 ++++
 hw/bsp/mcx/boards/frdmmcxa153/board.mk        |  14 +
 hw/bsp/mcx/boards/frdmmcxa153/clock_config.c  | 468 ++++++++++++++++++++++++++
 hw/bsp/mcx/boards/frdmmcxa153/clock_config.h  | 170 ++++++++++
 hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c       | 159 +++++++++
 hw/bsp/mcx/boards/frdmmcxa153/pin_mux.h       |  47 +++
 hw/bsp/mcx/boards/frdmmcxn947/board.cmake     |  24 ++
 hw/bsp/mcx/boards/frdmmcxn947/board.h         |  66 ++++
 hw/bsp/mcx/boards/frdmmcxn947/board.mk        |  14 +
 hw/bsp/mcx/boards/frdmmcxn947/clock_config.c  | 338 +++++++++++++++++++
 hw/bsp/mcx/boards/frdmmcxn947/clock_config.h  | 177 ++++++++++
 hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c       | 143 ++++++++
 hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h       |  51 +++
 hw/bsp/mcx/boards/mcxn947brk/board.cmake      |  24 ++
 hw/bsp/mcx/boards/mcxn947brk/board.h          |  66 ++++
 hw/bsp/mcx/boards/mcxn947brk/board.mk         |  14 +
 hw/bsp/mcx/boards/mcxn947brk/clock_config.c   | 338 +++++++++++++++++++
 hw/bsp/mcx/boards/mcxn947brk/clock_config.h   | 177 ++++++++++
 hw/bsp/mcx/boards/mcxn947brk/pin_mux.c        | 141 ++++++++
 hw/bsp/mcx/boards/mcxn947brk/pin_mux.h        |  51 +++
 hw/bsp/mcx/debug.jlinkscript                  |   5 +
 hw/bsp/mcx/family.c                           | 267 +++++++++++++++
 hw/bsp/mcx/family.cmake                       | 122 +++++++
 hw/bsp/mcx/family.mk                          |  65 ++++
 hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h   | 149 --------
 hw/bsp/mcxa/boards/frdmmcxa153/board.cmake    |  18 -
 hw/bsp/mcxa/boards/frdmmcxa153/board.h        |  66 ----
 hw/bsp/mcxa/boards/frdmmcxa153/board.mk       |  13 -
 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c | 468 --------------------------
 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h | 170 ----------
 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c      | 159 ---------
 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h      |  47 ---
 hw/bsp/mcxa/debug.jlinkscript                 |   5 -
 hw/bsp/mcxa/family.c                          | 161 ---------
 hw/bsp/mcxa/family.cmake                      | 110 ------
 hw/bsp/mcxa/family.mk                         |  42 ---
 hw/bsp/mcxn/FreeRTOSConfig/FreeRTOSConfig.h   | 149 --------
 hw/bsp/mcxn/boards/frdmmcxn947/board.cmake    |  21 --
 hw/bsp/mcxn/boards/frdmmcxn947/board.h        |  66 ----
 hw/bsp/mcxn/boards/frdmmcxn947/board.mk       |  11 -
 hw/bsp/mcxn/boards/frdmmcxn947/clock_config.c | 338 -------------------
 hw/bsp/mcxn/boards/frdmmcxn947/clock_config.h | 177 ----------
 hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.c      | 143 --------
 hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.h      |  51 ---
 hw/bsp/mcxn/boards/mcxn947brk/board.cmake     |  21 --
 hw/bsp/mcxn/boards/mcxn947brk/board.h         |  66 ----
 hw/bsp/mcxn/boards/mcxn947brk/board.mk        |  11 -
 hw/bsp/mcxn/boards/mcxn947brk/clock_config.c  | 338 -------------------
 hw/bsp/mcxn/boards/mcxn947brk/clock_config.h  | 177 ----------
 hw/bsp/mcxn/boards/mcxn947brk/pin_mux.c       | 141 --------
 hw/bsp/mcxn/boards/mcxn947brk/pin_mux.h       |  51 ---
 hw/bsp/mcxn/debug.jlinkscript                 |   5 -
 hw/bsp/mcxn/family.c                          | 245 --------------
 hw/bsp/mcxn/family.cmake                      | 110 ------
 hw/bsp/mcxn/family.mk                         |  51 ---
 src/common/tusb_mcu.h                         |   4 +-
 src/portable/chipidea/ci_fs/ci_fs_mcx.h       |  17 +-
 src/portable/chipidea/ci_fs/ci_fs_mcxa.h      |  47 ---
 src/portable/chipidea/ci_fs/dcd_ci_fs.c       |   2 -
 src/tusb_option.h                             |   2 +-
 63 files changed, 3197 insertions(+), 3638 deletions(-)
 create mode 100644 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/mcx/boards/frdmmcxa153/board.cmake
 create mode 100644 hw/bsp/mcx/boards/frdmmcxa153/board.h
 create mode 100644 hw/bsp/mcx/boards/frdmmcxa153/board.mk
 create mode 100644 hw/bsp/mcx/boards/frdmmcxa153/clock_config.c
 create mode 100644 hw/bsp/mcx/boards/frdmmcxa153/clock_config.h
 create mode 100644 hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c
 create mode 100644 hw/bsp/mcx/boards/frdmmcxa153/pin_mux.h
 create mode 100644 hw/bsp/mcx/boards/frdmmcxn947/board.cmake
 create mode 100644 hw/bsp/mcx/boards/frdmmcxn947/board.h
 create mode 100644 hw/bsp/mcx/boards/frdmmcxn947/board.mk
 create mode 100644 hw/bsp/mcx/boards/frdmmcxn947/clock_config.c
 create mode 100644 hw/bsp/mcx/boards/frdmmcxn947/clock_config.h
 create mode 100644 hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c
 create mode 100644 hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.cmake
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.h
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.mk
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/clock_config.c
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/clock_config.h
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
 create mode 100644 hw/bsp/mcx/debug.jlinkscript
 create mode 100644 hw/bsp/mcx/family.c
 create mode 100644 hw/bsp/mcx/family.cmake
 create mode 100644 hw/bsp/mcx/family.mk
 delete mode 100644 hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h
 delete mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/board.cmake
 delete mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/board.h
 delete mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/board.mk
 delete mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c
 delete mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h
 delete mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c
 delete mode 100644 hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h
 delete mode 100644 hw/bsp/mcxa/debug.jlinkscript
 delete mode 100644 hw/bsp/mcxa/family.c
 delete mode 100644 hw/bsp/mcxa/family.cmake
 delete mode 100644 hw/bsp/mcxa/family.mk
 delete mode 100644 hw/bsp/mcxn/FreeRTOSConfig/FreeRTOSConfig.h
 delete mode 100644 hw/bsp/mcxn/boards/frdmmcxn947/board.cmake
 delete mode 100644 hw/bsp/mcxn/boards/frdmmcxn947/board.h
 delete mode 100644 hw/bsp/mcxn/boards/frdmmcxn947/board.mk
 delete mode 100644 hw/bsp/mcxn/boards/frdmmcxn947/clock_config.c
 delete mode 100644 hw/bsp/mcxn/boards/frdmmcxn947/clock_config.h
 delete mode 100644 hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.c
 delete mode 100644 hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.h
 delete mode 100644 hw/bsp/mcxn/boards/mcxn947brk/board.cmake
 delete mode 100644 hw/bsp/mcxn/boards/mcxn947brk/board.h
 delete mode 100644 hw/bsp/mcxn/boards/mcxn947brk/board.mk
 delete mode 100644 hw/bsp/mcxn/boards/mcxn947brk/clock_config.c
 delete mode 100644 hw/bsp/mcxn/boards/mcxn947brk/clock_config.h
 delete mode 100644 hw/bsp/mcxn/boards/mcxn947brk/pin_mux.c
 delete mode 100644 hw/bsp/mcxn/boards/mcxn947brk/pin_mux.h
 delete mode 100644 hw/bsp/mcxn/debug.jlinkscript
 delete mode 100644 hw/bsp/mcxn/family.c
 delete mode 100644 hw/bsp/mcxn/family.cmake
 delete mode 100644 hw/bsp/mcxn/family.mk
 delete mode 100644 src/portable/chipidea/ci_fs/ci_fs_mcxa.h

(limited to 'src')

diff --git a/README.rst b/README.rst
index c48007c23..8c3145d33 100644
--- a/README.rst
+++ b/README.rst
@@ -139,9 +139,7 @@ Following CPUs are supported, check out `Supported Devices`_ for comprehensive l
 |              +---------+--------------------------------------------------+
 |              | LPC     | 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55         |
 |              +---------+--------------------------------------------------+
-|              | MCXA    | A153                                             |
-|              +---------+--------------------------------------------------+
-|              | MCXN    | N9                                               |
+|              | MCX     | A15, N9                                          |
 +--------------+---------+--------------------------------------------------+
 | Raspberry Pi | RP2040                                                     |
 +--------------+-----+------------------------------------------------------+
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6f10a7ab0
--- /dev/null
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/board.cmake b/hw/bsp/mcx/boards/frdmmcxa153/board.cmake
new file mode 100644
index 000000000..acde3f46f
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxa153/board.cmake
@@ -0,0 +1,23 @@
+set(MCU_VARIANT MCXA153)
+set(MCU_CORE MCXA153)
+
+set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
+
+set(JLINK_DEVICE MCXA153_M33)
+set(PYOCD_TARGET MCXA153)
+set(NXPLINK_DEVICE MCXA153:MCXA153)
+
+set(PORT 0)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXA153VLH
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/board.h b/hw/bsp/mcx/boards/frdmmcxa153/board.h
new file mode 100644
index 000000000..02a452da5
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxa153/board.h
@@ -0,0 +1,66 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_GateGPIO3
+#define LED_PIN               12 // red
+#define LED_STATE_ON          0
+
+// ISP button (Dummy, use unused pin
+ #define BUTTON_GPIO           GPIO3
+ #define BUTTON_CLK            kCLOCK_GateGPIO3
+ #define BUTTON_PIN            29 //sw2
+ #define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART0
+
+static inline void board_uart_init_clock(void) {
+
+  /* attach 12 MHz clock to LPUART0 (debug console) */
+    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+}
+
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/board.mk b/hw/bsp/mcx/boards/frdmmcxa153/board.mk
new file mode 100644
index 000000000..a70a7dcef
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxa153/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXA153
+MCU_CORE = MCXA153
+PORT = 0
+
+CPU_CORE ?= cortex-m33-nodsp-nofp
+CFLAGS += \
+	-DCPU_MCXA153VLH \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
+ 
+JLINK_DEVICE = MCXA153
+PYOCD_TARGET = MCXA153
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/clock_config.c b/hw/bsp/mcx/boards/frdmmcxa153/clock_config.c
new file mode 100644
index 000000000..f16bc51f6
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxa153/clock_config.c
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v12.0
+processor: MCXA153
+package_id: MCXA153VLH
+mcu_data: ksdk2_0
+processor_version: 0.13.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "fsl_spc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+//uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockFRO96M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CPU_clock.outFreq, value: 12 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO12M */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO24M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 6 MHz}
+- {id: System_clock.outFreq, value: 24 MHz}
+settings:
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO24M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U);               /* !< Set AHBCLKDIV divider to value 2 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO48M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO48M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO64M
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 64 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
+- {id: FRO_HF_clock.outFreq, value: 64 MHz}
+- {id: MAIN_clock.outFreq, value: 64 MHz}
+- {id: Slow_clock.outFreq, value: 16 MHz}
+- {id: System_clock.outFreq, value: 64 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 64 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO64M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(64000000U);               /*!< Enable FRO HF(64MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
+}
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO96M
+called_from_default_init: true
+outputs:
+- {id: CLK_1M_clock.outFreq, value: 1 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CPU_clock.outFreq, value: 96 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
+- {id: FRO_HF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: VDD_CORE, value: voltage_1v1}
+- {id: CLKOUTDIV_HALT, value: Enable}
+- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
+- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
+- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
+sources:
+- {id: SCG.FIRC.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO96M(void)
+{
+    uint32_t coreFreq;
+    spc_active_mode_core_ldo_option_t ldoOption;
+    spc_sram_voltage_config_t sramOption;
+
+    /* Get the CPU Core frequency */
+    coreFreq = CLOCK_GetCoreSysClkFreq();
+
+    /* The flow of increasing voltage and frequency */
+    if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+    }
+
+    CLOCK_SetupFROHFClocking(96000000U);               /*!< Enable FRO HF(96MHz) output */
+
+    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
+
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
+
+    /* The flow of decreasing voltage and frequency */
+    if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+        /* Configure Flash to support different voltage level and frequency */
+        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+        /* Specifies the operating voltage for the SRAM's read/write timing margin */
+        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+        sramOption.requestVoltageUpdate =  true;
+        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+        /* Set the LDO_CORE VDD regulator level */
+        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+    }
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+
+    /*!< Set up dividers */
+    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/clock_config.h b/hw/bsp/mcx/boards/frdmmcxa153/clock_config.h
new file mode 100644
index 000000000..079d0d312
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxa153/clock_config.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+ 
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO24M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK           24000000U  /*!< Core clock frequency: 24000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO24M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO24M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO48M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK           48000000U  /*!< Core clock frequency: 48000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO64M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK           64000000U  /*!< Core clock frequency: 64000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO64M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO64M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK           96000000U  /*!< Core clock frequency: 96000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c
new file mode 100644
index 000000000..b0e6de560
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+ 
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v14.0
+processor: MCXA153
+package_id: MCXA153VLH
+mcu_data: ksdk2_0
+processor_version: 0.14.3
+pin_labels:
+- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+    RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
+    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+
+    /* write to PORT0: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT0);
+
+    /* Write to GPIO3: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GateGPIO3);
+    /* Write to PORT3: Peripheral clock is enabled */
+    CLOCK_EnableClock(kCLOCK_GatePORT3);
+    /* GPIO3 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+    /* PORT3 peripheral is released from reset */
+    RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+
+    const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
+                                       kPORT_PullDisable,
+                                       /* Low internal pull resistor value is selected. */
+                                       kPORT_LowPullResistor,
+                                       /* Fast slew rate is configured */
+                                       kPORT_FastSlewRate,
+                                       /* Passive input filter is disabled */
+                                       kPORT_PassiveFilterDisable,
+                                       /* Open drain output is disabled */
+                                       kPORT_OpenDrainDisable,
+                                       /* Low drive strength is configured */
+                                       kPORT_LowDriveStrength,
+                                       /* Normal drive strength is configured */
+                                       kPORT_NormalDriveStrength,
+                                       /* Pin is configured as P3_12 */
+                                       kPORT_MuxAlt0,
+                                       /* Digital input enabled */
+                                       kPORT_InputBufferEnable,
+                                       /* Digital input is not inverted */
+                                       kPORT_InputNormal,
+                                       /* Pin Control Register fields [15:0] are not locked */
+                                       kPORT_UnlockRegister};
+    /* PORT3_12 (pin 38) is configured as P3_12 */
+      PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
+
+    const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_RXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_2 (pin 51) is configured as LPUART0_RXD */
+    PORT_SetPinConfig(PORT0, 2U, &port0_2_pin51_config);
+
+    const port_pin_config_t port0_3_pin52_config = {/* Internal pull-up resistor is enabled */
+                                                    kPORT_PullUp,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Normal drive strength is configured */
+                                                    kPORT_NormalDriveStrength,
+                                                    /* Pin is configured as LPUART0_TXD */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT0_3 (pin 52) is configured as LPUART0_TXD */
+    PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
+
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.h b/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.h
new file mode 100644
index 000000000..06b6fdee9
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/board.cmake b/hw/bsp/mcx/boards/frdmmcxn947/board.cmake
new file mode 100644
index 000000000..a08d248f5
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxn947/board.cmake
@@ -0,0 +1,24 @@
+set(MCU_VARIANT MCXN947)
+set(MCU_CORE MCXN947_cm33_core0)
+
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
+
+set(JLINK_DEVICE MCXN947_M33_0)
+set(PYOCD_TARGET MCXN947)
+set(NXPLINK_DEVICE MCXN947:MCXN947)
+
+set(PORT 1)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXN947VDF_cm33_core0
+    BOARD_TUD_RHPORT=${PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/board.h b/hw/bsp/mcx/boards/frdmmcxn947/board.h
new file mode 100644
index 000000000..acb73363f
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxn947/board.h
@@ -0,0 +1,66 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO0
+#define LED_CLK               kCLOCK_Gpio0
+#define LED_PIN               10 // red
+#define LED_STATE_ON          0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_GPIO           GPIO0
+#define BUTTON_CLK            kCLOCK_Gpio0
+#define BUTTON_PIN            23
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART4
+
+static inline void board_uart_init_clock(void) {
+  /* attach FRO 12M to FLEXCOMM4 */
+  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
+}
+
+//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
+//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/board.mk b/hw/bsp/mcx/boards/frdmmcxn947/board.mk
new file mode 100644
index 000000000..d90780996
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxn947/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXN947
+MCU_CORE = MCXN947_cm33_core0
+PORT ?= 1
+
+CPU_CORE ?= cortex-m33
+CFLAGS += \
+	-DCPU_MCXN947VDF_cm33_core0 \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
+
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/clock_config.c b/hw/bsp/mcx/boards/frdmmcxn947/clock_config.c
new file mode 100644
index 000000000..37d2b4dfc
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxn947/clock_config.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v10.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+board: MCX-N9XX-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF144M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 144 MHz}
+- {id: MAIN_clock.outFreq, value: 144 MHz}
+- {id: Slow_clock.outFreq, value: 18 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.FIRC.outFreq, value: 144 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF144M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 150 MHz}
+- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
+- {id: Slow_clock.outFreq, value: 37.5 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: RunPowerMode, value: OD}
+- {id: SCGMode, value: PLL0}
+- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
+- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
+- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up PLL0 */
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
+        .pllndiv = SCG_APLLNDIV_NDIV(8U),
+        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+        .pllRate = 150000000U
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CLK_IN_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 100 MHz}
+- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
+- {id: Slow_clock.outFreq, value: 25 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: SCGMode, value: PLL1}
+- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
+- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
+- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupExtClocking(24000000U);
+    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
+
+    /*!< Set up PLL1 */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
+        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
+        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
+        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
+        .pllRate = 100000000U
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
+    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/clock_config.h b/hw/bsp/mcx/boards/frdmmcxn947/clock_config.h
new file mode 100644
index 000000000..c238a0423
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxn947/clock_config.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
+#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
+#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF144M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c b/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c
new file mode 100644
index 000000000..c33790ac5
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v12.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
+    invert_input: normal}
+  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
+ -  {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
+    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+  /* Enables the clock for PORT0: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port0);
+
+    /* Enables the clock for PORT1: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port1);
+
+
+    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P0 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_8 (pin A1) is configured as FC4_P0 */
+    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
+
+    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P1 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_9 (pin B1) is configured as FC4_P1 */
+    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
+
+    const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
+                                   kPORT_PullDisable,
+                                   /* Low internal pull resistor value is selected. */
+                                   kPORT_LowPullResistor,
+                                   /* Fast slew rate is configured */
+                                   kPORT_FastSlewRate,
+                                   /* Passive input filter is disabled */
+                                   kPORT_PassiveFilterDisable,
+                                   /* Open drain output is disabled */
+                                   kPORT_OpenDrainDisable,
+                                   /* Low drive strength is configured */
+                                   kPORT_LowDriveStrength,
+                                   /* Pin is configured as PIO0_23 */
+                                   kPORT_MuxAlt0,
+                                   /* Digital input enabled */
+                                   kPORT_InputBufferEnable,
+                                   /* Digital input is not inverted */
+                                   kPORT_InputNormal,
+                                   /* Pin Control Register fields [15:0] are not locked */
+                                   kPORT_UnlockRegister};
+    /* PORT0_23 (pin B7) is configured as PIO0_23 */
+    PORT_SetPinConfig(PORT0, 23U, &SW2);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h b/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h
new file mode 100644
index 000000000..40968c275
--- /dev/null
+++ b/hw/bsp/mcx/boards/frdmmcxn947/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
new file mode 100644
index 000000000..a08d248f5
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -0,0 +1,24 @@
+set(MCU_VARIANT MCXN947)
+set(MCU_CORE MCXN947_cm33_core0)
+
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
+
+set(JLINK_DEVICE MCXN947_M33_0)
+set(PYOCD_TARGET MCXN947)
+set(NXPLINK_DEVICE MCXN947:MCXN947)
+
+set(PORT 1)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXN947VDF_cm33_core0
+    BOARD_TUD_RHPORT=${PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.h b/hw/bsp/mcx/boards/mcxn947brk/board.h
new file mode 100644
index 000000000..eae98bfa7
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.h
@@ -0,0 +1,66 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_Gpio3
+#define LED_PIN               4 // red
+#define LED_STATE_ON          0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_GPIO           GPIO0
+#define BUTTON_CLK            kCLOCK_Gpio0
+#define BUTTON_PIN            6
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART4
+
+static inline void board_uart_init_clock(void) {
+  /* attach FRO 12M to FLEXCOMM4 */
+  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
+}
+
+//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
+//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
new file mode 100644
index 000000000..d90780996
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -0,0 +1,14 @@
+MCU_VARIANT = MCXN947
+MCU_CORE = MCXN947_cm33_core0
+PORT ?= 1
+
+CPU_CORE ?= cortex-m33
+CFLAGS += \
+	-DCPU_MCXN947VDF_cm33_core0 \
+	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
+
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
+
+# flash using pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.c b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
new file mode 100644
index 000000000..37d2b4dfc
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v10.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+board: MCX-N9XX-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF144M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 144 MHz}
+- {id: MAIN_clock.outFreq, value: 144 MHz}
+- {id: Slow_clock.outFreq, value: 18 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.FIRC.outFreq, value: 144 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF144M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 150 MHz}
+- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
+- {id: Slow_clock.outFreq, value: 37.5 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: RunPowerMode, value: OD}
+- {id: SCGMode, value: PLL0}
+- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
+- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
+- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up PLL0 */
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
+        .pllndiv = SCG_APLLNDIV_NDIV(8U),
+        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+        .pllRate = 150000000U
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CLK_IN_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 100 MHz}
+- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
+- {id: Slow_clock.outFreq, value: 25 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: SCGMode, value: PLL1}
+- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
+- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
+- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupExtClocking(24000000U);
+    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
+
+    /*!< Set up PLL1 */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
+        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
+        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
+        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
+        .pllRate = 100000000U
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
+    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.h b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
new file mode 100644
index 000000000..c238a0423
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
+#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
+#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF144M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
new file mode 100644
index 000000000..acc2f3e45
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v12.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
+    invert_input: normal}
+  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
+  - {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
+    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for PORT1: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port1);
+    /* Enables the clock for PORT3: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port3);
+
+    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P0 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_8 (pin A1) is configured as FC4_P0 */
+    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
+
+    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P1 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_9 (pin B1) is configured as FC4_P1 */
+    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
+
+    const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
+                                                     kPORT_PullDisable,
+                                                     /* Low internal pull resistor value is selected. */
+                                                     kPORT_LowPullResistor,
+                                                     /* Fast slew rate is configured */
+                                                     kPORT_FastSlewRate,
+                                                     /* Passive input filter is disabled */
+                                                     kPORT_PassiveFilterDisable,
+                                                     /* Open drain output is disabled */
+                                                     kPORT_OpenDrainDisable,
+                                                     /* Low drive strength is configured */
+                                                     kPORT_LowDriveStrength,
+                                                     /* Pin is configured as PIO3_4 */
+                                                     kPORT_MuxAlt0,
+                                                     /* Digital input enabled */
+                                                     kPORT_InputBufferEnable,
+                                                     /* Digital input is not inverted */
+                                                     kPORT_InputNormal,
+                                                     /* Pin Control Register fields [15:0] are not locked */
+                                                     kPORT_UnlockRegister};
+    /* PORT3_4 (pin F14) is configured as PIO3_4 */
+    PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
new file mode 100644
index 000000000..40968c275
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/debug.jlinkscript b/hw/bsp/mcx/debug.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/mcx/debug.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+  return 0;
+}
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
new file mode 100644
index 000000000..74b84773d
--- /dev/null
+++ b/hw/bsp/mcx/family.c
@@ -0,0 +1,267 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board_api.h"
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_lpuart.h"
+#include "board.h"
+
+#include "pin_mux.h"
+#include "clock_config.h"
+
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_MCXN9
+void USB0_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void USB1_HS_IRQHandler(void)
+{
+  tud_int_handler(1);
+}
+
+#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
+void USB0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+#endif
+
+
+void board_init(void)
+{
+  BOARD_InitPins();
+  BOARD_InitBootClocks();
+  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
+
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  // LED
+  CLOCK_EnableClock(LED_CLK);
+  gpio_pin_config_t led_config = {
+      kGPIO_DigitalOutput,
+      0,
+  };
+  GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
+  board_led_write(0);
+
+#ifdef NEOPIXEL_PIN
+  // Neopixel
+  static uint32_t pixelData[NEOPIXEL_NUMBER];
+  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
+
+  sctpix_init(NEOPIXEL_TYPE);
+  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
+  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
+  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
+  sctpix_show();
+#endif
+
+  // Button
+#ifdef BUTTON_GPIO
+  CLOCK_EnableClock(BUTTON_CLK);
+  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+#endif
+
+#ifdef UART_DEV
+  // UART
+//  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
+//  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
+
+  // Enable UART when debug log is on
+  board_uart_init_clock();
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx     = true;
+  uart_config.enableRx     = true;
+  LPUART_Init(UART_DEV, &uart_config, 12000000u);
+#endif
+
+  // USB VBUS
+  /* PORT0 PIN22 configured as USB0_VBUS */
+
+
+  /* MCXA15 USB configurations */
+#if PORT_SUPPORT_DEVICE(0) && (CFG_TUSB_MCU == OPT_MCU_MCXA15)
+
+  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
+  CLOCK_EnableUsbfsClock();
+
+#endif
+
+
+  /* MCXN9 USB configurations */
+#if PORT_SUPPORT_DEVICE(0) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
+  // Port0 is Full Speed
+
+  CLOCK_AttachClk(kCLK_48M_to_USB0);
+  CLOCK_EnableClock(kCLOCK_Usb0Ram);
+  CLOCK_EnableClock(kCLOCK_Usb0Fs);
+  CLOCK_EnableUsbfsClock();
+  
+#endif
+
+#if PORT_SUPPORT_DEVICE(1) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
+  // Port1 is High Speed
+
+  // Power
+  SPC0->ACTIVE_VDELAY = 0x0500;
+  /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
+  SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+  SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+                      SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+  /* Wait until it is done */
+  while (SPC0->SC & SPC_SC_BUSY_MASK) {}
+  if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+    SCG0->TRIM_LOCK = 0x5a5a0001U;
+    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+    /* wait LDO ready */
+    while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
+  }
+  SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+  SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+  /* xtal = 20 ~ 30MHz */
+  SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+  SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+  while (1) {
+    if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+      break;
+    }
+  }
+
+  // Clock
+  SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+  CLOCK_EnableClock(kCLOCK_UsbHs);
+  CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+  CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
+  CLOCK_EnableUsbhsClock();
+
+  // USB PHY
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+  USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+#endif
+
+  // Enable PHY support for Low speed device + LS via FS Hub
+  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  USBPHY->PWD = 0;
+
+  // TX Timing
+  uint32_t phytx = USBPHY->TX;
+  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+  phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
+  //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+  USBPHY->TX = phytx;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+
+#ifdef NEOPIXEL_PIN
+  if (state) {
+    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
+    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
+  } else {
+    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
+    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
+  }
+  sctpix_show();
+#endif
+}
+
+uint32_t board_button_read(void)
+{
+#ifdef BUTTON_GPIO
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
new file mode 100644
index 000000000..078d13b9f
--- /dev/null
+++ b/hw/bsp/mcx/family.cmake
@@ -0,0 +1,122 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      # external driver
+      #lib/sct_neopixel/sct_neopixel.c
+
+      # driver
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+      
+      # mcu
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+      )
+    
+      if (${FAMILY_MCUS} STREQUAL "MCXN9")
+        target_sources(${BOARD_TARGET} PRIVATE
+          ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+        )
+      elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
+        target_sources(${BOARD_TARGET} PRIVATE
+        ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c
+      )
+      endif()
+
+    #  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    #    )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      # driver
+      # mcu
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_sources(${BOARD_TARGET} PUBLIC
+        ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+        )
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  if (${FAMILY_MCUS} STREQUAL "MCXN9")
+    family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS})
+  elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
+    family_add_tinyusb(${TARGET} OPT_MCU_MCXA15 ${RTOS})
+  endif()
+  
+  target_sources(${TARGET}-tinyusb PUBLIC
+    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+    ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
new file mode 100644
index 000000000..59170271c
--- /dev/null
+++ b/hw/bsp/mcx/family.mk
@@ -0,0 +1,65 @@
+UF2_FAMILY_ID = 0x2abc77ec
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+# Default to Highspeed PORT1
+PORT ?= 1
+
+CFLAGS += \
+  -flto \
+  -DBOARD_TUD_RHPORT=$(PORT) \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+
+# All source paths should be relative to the top level.
+LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
+
+# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+ifeq ($(PORT), 1)
+  $(info "PORT1 High Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+	SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
+else
+  $(info "PORT0 Full Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+  SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
+endif
+
+SRC_C += \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+	
+
+# fsl_lpflexcomm just needed for MCXN9
+ifeq ($(MCU_VARIANT), MCXN947)
+	SRC_C += \
+		$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
+
+endif
+
+# fsl_spc just needed for MCXNA15
+ifeq ($(MCU_VARIANT), MCXA153)
+	SRC_C += \
+		$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c  \
+
+endif
+
+	
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
+
+SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h
deleted file mode 100644
index 6f10a7ab0..000000000
--- a/hw/bsp/mcxa/FreeRTOSConfig/FreeRTOSConfig.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-// skip if included from IAR assembler
-#ifndef __IASMARM__
-  #include "fsl_device_registers.h"
-#endif
-
-/* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU                        0
-#define configENABLE_FPU                        1
-#define configENABLE_TRUSTZONE                  0
-#define configMINIMAL_SECURE_STACK_SIZE         (1024)
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configCPU_CLOCK_HZ                      SystemCoreClock
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
-#define configMAX_TASK_NAME_LEN                 16
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               4
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
-#define configCHECK_FOR_STACK_OVERFLOW         2
-#define configCHECK_HANDLER_INSTALLATION       0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configRECORD_STACK_HIGH_ADDRESS        1
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
-#define configTIMER_QUEUE_LENGTH               32
-#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      1
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behavior configuration.
-//--------------------------------------------------------------------+
-
-// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       3
-
-/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/board.cmake b/hw/bsp/mcxa/boards/frdmmcxa153/board.cmake
deleted file mode 100644
index 7f3c6c665..000000000
--- a/hw/bsp/mcxa/boards/frdmmcxa153/board.cmake
+++ /dev/null
@@ -1,18 +0,0 @@
-set(MCU_VARIANT MCXA153)
-set(MCU_CORE MCXA153)
-
-set(JLINK_DEVICE MCXA153_M33)
-set(PYOCD_TARGET MCXA153)
-set(NXPLINK_DEVICE MCXA153:MCXA153)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    CPU_MCXA153VLH
-    BOARD_TUD_RHPORT=0
-    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-    )
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
-    )
-endfunction()
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/board.h b/hw/bsp/mcxa/boards/frdmmcxa153/board.h
deleted file mode 100644
index 02a452da5..000000000
--- a/hw/bsp/mcxa/boards/frdmmcxa153/board.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_GPIO              GPIO3
-#define LED_CLK               kCLOCK_GateGPIO3
-#define LED_PIN               12 // red
-#define LED_STATE_ON          0
-
-// ISP button (Dummy, use unused pin
- #define BUTTON_GPIO           GPIO3
- #define BUTTON_CLK            kCLOCK_GateGPIO3
- #define BUTTON_PIN            29 //sw2
- #define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              LPUART0
-
-static inline void board_uart_init_clock(void) {
-
-  /* attach 12 MHz clock to LPUART0 (debug console) */
-    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
-    CLOCK_AttachClk(kFRO12M_to_LPUART0);
-
-    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
-}
-
-
-// XTAL
-#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/board.mk b/hw/bsp/mcxa/boards/frdmmcxa153/board.mk
deleted file mode 100644
index 18f7e3cb5..000000000
--- a/hw/bsp/mcxa/boards/frdmmcxa153/board.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-MCU_VARIANT = MCXA153
-MCU_CORE = MCXA153
-PORT = 0
-
-CFLAGS += \
-	-DCPU_MCXA153VLH \
- 
-
-JLINK_DEVICE = MCXA153
-PYOCD_TARGET = MCXA153
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c b/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c
deleted file mode 100644
index f16bc51f6..000000000
--- a/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.c
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * Copyright 2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v12.0
-processor: MCXA153
-package_id: MCXA153VLH
-mcu_data: ksdk2_0
-processor_version: 0.13.0
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "fsl_clock.h"
-#include "clock_config.h"
-#include "fsl_spc.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-//uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockFRO96M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_1M_clock.outFreq, value: 1 MHz}
-- {id: CPU_clock.outFreq, value: 12 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
-- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    uint32_t coreFreq;
-    spc_active_mode_core_ldo_option_t ldoOption;
-    spc_sram_voltage_config_t sramOption;
-
-    /* Get the CPU Core frequency */
-    coreFreq = CLOCK_GetCoreSysClkFreq();
-
-    /* The flow of increasing voltage and frequency */
-    if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-    }
-
-    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
-
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO12M */
-
-    /* The flow of decreasing voltage and frequency */
-    if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-    }
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-
-    /*!< Set up dividers */
-    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO24M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO24M
-outputs:
-- {id: CLK_1M_clock.outFreq, value: 1 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CPU_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 6 MHz}
-- {id: System_clock.outFreq, value: 24 MHz}
-settings:
-- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
-- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO24M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO24M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO24M(void)
-{
-    uint32_t coreFreq;
-    spc_active_mode_core_ldo_option_t ldoOption;
-    spc_sram_voltage_config_t sramOption;
-
-    /* Get the CPU Core frequency */
-    coreFreq = CLOCK_GetCoreSysClkFreq();
-
-    /* The flow of increasing voltage and frequency */
-    if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-    }
-
-    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
-
-    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
-
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
-
-    /* The flow of decreasing voltage and frequency */
-    if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-    }
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-
-    /*!< Set up dividers */
-    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U);               /* !< Set AHBCLKDIV divider to value 2 */
-    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
-}
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO48M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO48M
-outputs:
-- {id: CLK_1M_clock.outFreq, value: 1 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CPU_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-settings:
-- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO48M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO48M(void)
-{
-    uint32_t coreFreq;
-    spc_active_mode_core_ldo_option_t ldoOption;
-    spc_sram_voltage_config_t sramOption;
-
-    /* Get the CPU Core frequency */
-    coreFreq = CLOCK_GetCoreSysClkFreq();
-
-    /* The flow of increasing voltage and frequency */
-    if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-    }
-
-    CLOCK_SetupFROHFClocking(48000000U);               /*!< Enable FRO HF(48MHz) output */
-
-    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
-
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
-
-    /* The flow of decreasing voltage and frequency */
-    if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-    }
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-
-    /*!< Set up dividers */
-    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
-    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
-}
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO64M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO64M
-outputs:
-- {id: CLK_1M_clock.outFreq, value: 1 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CPU_clock.outFreq, value: 64 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
-- {id: FRO_HF_clock.outFreq, value: 64 MHz}
-- {id: MAIN_clock.outFreq, value: 64 MHz}
-- {id: Slow_clock.outFreq, value: 16 MHz}
-- {id: System_clock.outFreq, value: 64 MHz}
-settings:
-- {id: VDD_CORE, value: voltage_1v1}
-- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
-- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
-- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
-sources:
-- {id: SCG.FIRC.outFreq, value: 64 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO64M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO64M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO64M(void)
-{
-    uint32_t coreFreq;
-    spc_active_mode_core_ldo_option_t ldoOption;
-    spc_sram_voltage_config_t sramOption;
-
-    /* Get the CPU Core frequency */
-    coreFreq = CLOCK_GetCoreSysClkFreq();
-
-    /* The flow of increasing voltage and frequency */
-    if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-    }
-
-    CLOCK_SetupFROHFClocking(64000000U);               /*!< Enable FRO HF(64MHz) output */
-
-    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
-
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
-
-    /* The flow of decreasing voltage and frequency */
-    if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-    }
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-
-    /*!< Set up dividers */
-    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
-    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
-}
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO96M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO96M
-called_from_default_init: true
-outputs:
-- {id: CLK_1M_clock.outFreq, value: 1 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CPU_clock.outFreq, value: 96 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
-- {id: FRO_HF_clock.outFreq, value: 96 MHz}
-- {id: MAIN_clock.outFreq, value: 96 MHz}
-- {id: Slow_clock.outFreq, value: 24 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: VDD_CORE, value: voltage_1v1}
-- {id: CLKOUTDIV_HALT, value: Enable}
-- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
-- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
-- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
-sources:
-- {id: SCG.FIRC.outFreq, value: 96 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO96M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO96M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO96M(void)
-{
-    uint32_t coreFreq;
-    spc_active_mode_core_ldo_option_t ldoOption;
-    spc_sram_voltage_config_t sramOption;
-
-    /* Get the CPU Core frequency */
-    coreFreq = CLOCK_GetCoreSysClkFreq();
-
-    /* The flow of increasing voltage and frequency */
-    if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-    }
-
-    CLOCK_SetupFROHFClocking(96000000U);               /*!< Enable FRO HF(96MHz) output */
-
-    CLOCK_SetupFRO12MClocking();                /*!< Setup FRO12M clock */
-
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);       /* !< Switch MAIN_CLK to FRO_HF */
-
-    /* The flow of decreasing voltage and frequency */
-    if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
-        /* Configure Flash to support different voltage level and frequency */
-        FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
-        /* Specifies the operating voltage for the SRAM's read/write timing margin */
-        sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
-        sramOption.requestVoltageUpdate =  true;
-        (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
-        /* Set the LDO_CORE VDD regulator level */
-        ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
-        ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
-        (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
-    }
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-
-    /*!< Set up dividers */
-    CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);               /* !< Set AHBCLKDIV divider to value 1 */
-    CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U);           /* !< Set FROHFDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
-}
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h b/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h
deleted file mode 100644
index 079d0d312..000000000
--- a/hw/bsp/mcxa/boards/frdmmcxa153/clock_config.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright 2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
- 
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO24M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO24M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK           24000000U  /*!< Core clock frequency: 24000000Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO24M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO24M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO48M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK           48000000U  /*!< Core clock frequency: 48000000Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO64M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO64M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK           64000000U  /*!< Core clock frequency: 64000000Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO64M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO64M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO96M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO96M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK           96000000U  /*!< Core clock frequency: 96000000Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO96M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO96M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c b/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c
deleted file mode 100644
index b0e6de560..000000000
--- a/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright 2023 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
- 
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v14.0
-processor: MCXA153
-package_id: MCXA153VLH
-mcu_data: ksdk2_0
-processor_version: 0.14.3
-pin_labels:
-- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "fsl_gpio.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast,
-    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitPins(void)
-{
-    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
-    RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn);
-    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
-    CLOCK_AttachClk(kFRO12M_to_LPUART0);
-
-    /* write to PORT0: Peripheral clock is enabled */
-    CLOCK_EnableClock(kCLOCK_GatePORT0);
-
-    /* Write to GPIO3: Peripheral clock is enabled */
-    CLOCK_EnableClock(kCLOCK_GateGPIO3);
-    /* Write to PORT3: Peripheral clock is enabled */
-    CLOCK_EnableClock(kCLOCK_GatePORT3);
-    /* GPIO3 peripheral is released from reset */
-    RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
-    /* PORT3 peripheral is released from reset */
-    RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
-
-    const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */
-                                       kPORT_PullDisable,
-                                       /* Low internal pull resistor value is selected. */
-                                       kPORT_LowPullResistor,
-                                       /* Fast slew rate is configured */
-                                       kPORT_FastSlewRate,
-                                       /* Passive input filter is disabled */
-                                       kPORT_PassiveFilterDisable,
-                                       /* Open drain output is disabled */
-                                       kPORT_OpenDrainDisable,
-                                       /* Low drive strength is configured */
-                                       kPORT_LowDriveStrength,
-                                       /* Normal drive strength is configured */
-                                       kPORT_NormalDriveStrength,
-                                       /* Pin is configured as P3_12 */
-                                       kPORT_MuxAlt0,
-                                       /* Digital input enabled */
-                                       kPORT_InputBufferEnable,
-                                       /* Digital input is not inverted */
-                                       kPORT_InputNormal,
-                                       /* Pin Control Register fields [15:0] are not locked */
-                                       kPORT_UnlockRegister};
-    /* PORT3_12 (pin 38) is configured as P3_12 */
-      PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config);
-
-    const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */
-                                                    kPORT_PullUp,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Normal drive strength is configured */
-                                                    kPORT_NormalDriveStrength,
-                                                    /* Pin is configured as LPUART0_RXD */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT0_2 (pin 51) is configured as LPUART0_RXD */
-    PORT_SetPinConfig(PORT0, 2U, &port0_2_pin51_config);
-
-    const port_pin_config_t port0_3_pin52_config = {/* Internal pull-up resistor is enabled */
-                                                    kPORT_PullUp,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Normal drive strength is configured */
-                                                    kPORT_NormalDriveStrength,
-                                                    /* Pin is configured as LPUART0_TXD */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT0_3 (pin 52) is configured as LPUART0_TXD */
-    PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
-
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h b/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h
deleted file mode 100644
index 06b6fdee9..000000000
--- a/hw/bsp/mcxa/boards/frdmmcxa153/pin_mux.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcxa/debug.jlinkscript b/hw/bsp/mcxa/debug.jlinkscript
deleted file mode 100644
index fd8bcffef..000000000
--- a/hw/bsp/mcxa/debug.jlinkscript
+++ /dev/null
@@ -1,5 +0,0 @@
-int SetupTarget(void) {
-  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
-
-  return 0;
-}
diff --git a/hw/bsp/mcxa/family.c b/hw/bsp/mcxa/family.c
deleted file mode 100644
index d2bc35f8c..000000000
--- a/hw/bsp/mcxa/family.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_lpuart.h"
-#include "board.h"
-
-#include "pin_mux.h"
-#include "clock_config.h"
-
-
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void board_init(void)
-{
-  BOARD_InitPins();
-  BOARD_InitBootClocks();
-  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-  // LED
-  CLOCK_EnableClock(LED_CLK);
-  gpio_pin_config_t LED_RED_config = {
-      .pinDirection = kGPIO_DigitalOutput,
-      .outputLogic = 0U
-  };
-  
-  /* Initialize GPIO functionality on pin PIO3_12 (pin 38)  */
-  GPIO_PinInit(LED_GPIO, LED_PIN, &LED_RED_config);
-  board_led_write(1);
-
-  // Button
-#ifdef BUTTON_GPIO
-  CLOCK_EnableClock(BUTTON_CLK);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
-#endif
-
-#ifdef UART_DEV
-
-  CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
-  CLOCK_AttachClk(kFRO12M_to_LPUART0);
-  RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
-
-  lpuart_config_t uart_config;
-  LPUART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = 115200;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = false; 
-  LPUART_Init(UART_DEV, &uart_config, 12000000u);
-
-
-#endif
-
-  // USB VBUS
-  /* PORT0 PIN22 configured as USB0_VBUS */
-
-#if PORT_SUPPORT_DEVICE(0)
-  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
-  CLOCK_EnableUsbfsClock();
-#endif
-
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-#ifdef BUTTON_GPIO
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
-#else
-  return 1;
-#endif
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-#ifdef UART_DEV
-  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
-  return len;
-#else
-  (void) buf; (void) len;
-  return 0;
-#endif
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-  
\ No newline at end of file
diff --git a/hw/bsp/mcxa/family.cmake b/hw/bsp/mcxa/family.cmake
deleted file mode 100644
index d2b2321d6..000000000
--- a/hw/bsp/mcxa/family.cmake
+++ /dev/null
@@ -1,110 +0,0 @@
-include_guard()
-
-if (NOT BOARD)
-  message(FATAL_ERROR "BOARD not specified")
-endif ()
-
-set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# toolchain set up
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-
-set(FAMILY_MCUS MCXA CACHE INTERNAL "")
-
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      # external driver
-      #lib/sct_neopixel/sct_neopixel.c
-
-      # driver
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c 
-      # mcu
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-      )
-    #  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    #    )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      # driver
-      # mcu
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-      )
-
-    update_board(${BOARD_TARGET})
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_sources(${BOARD_TARGET} PUBLIC
-        ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
-        )
-      target_link_options(${BOARD_TARGET} PUBLIC
-        # linker file
-        "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MCXA ${RTOS})
-  target_sources(${TARGET}-tinyusb PUBLIC
-    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
-    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
-    )
-  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})  
-
-  # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
-
-  # Flashing
-  family_flash_jlink(${TARGET})
-  #family_flash_nxplink(${TARGET})
-  #family_flash_pyocd(${TARGET})
-endfunction()
diff --git a/hw/bsp/mcxa/family.mk b/hw/bsp/mcxa/family.mk
deleted file mode 100644
index 87ae92fab..000000000
--- a/hw/bsp/mcxa/family.mk
+++ /dev/null
@@ -1,42 +0,0 @@
-UF2_FAMILY_ID = 0x2abc77ec
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5		#not found
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-CPU_CORE ?= cortex-m33-nodsp-nofp
-
-CFLAGS += \
-  -flto \
-  -DCFG_TUSB_MCU=OPT_MCU_MCXA \
-  -DBOARD_TUD_RHPORT=0 
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-# All source paths should be relative to the top level.
-LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
-
-# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
-$(info "PORT0 Full Speed")
-CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
-
-SRC_C += \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c 
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers 
-	
-
-SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/mcxn/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcxn/FreeRTOSConfig/FreeRTOSConfig.h
deleted file mode 100644
index 6f10a7ab0..000000000
--- a/hw/bsp/mcxn/FreeRTOSConfig/FreeRTOSConfig.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
- *
- * See http://www.freertos.org/a00110.html.
- *----------------------------------------------------------*/
-
-// skip if included from IAR assembler
-#ifndef __IASMARM__
-  #include "fsl_device_registers.h"
-#endif
-
-/* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU                        0
-#define configENABLE_FPU                        1
-#define configENABLE_TRUSTZONE                  0
-#define configMINIMAL_SECURE_STACK_SIZE         (1024)
-
-#define configUSE_PREEMPTION                    1
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#define configCPU_CLOCK_HZ                      SystemCoreClock
-#define configTICK_RATE_HZ                      ( 1000 )
-#define configMAX_PRIORITIES                    ( 5 )
-#define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
-#define configMAX_TASK_NAME_LEN                 16
-#define configUSE_16_BIT_TICKS                  0
-#define configIDLE_SHOULD_YIELD                 1
-#define configUSE_MUTEXES                       1
-#define configUSE_RECURSIVE_MUTEXES             1
-#define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               4
-#define configUSE_QUEUE_SETS                    0
-#define configUSE_TIME_SLICING                  0
-#define configUSE_NEWLIB_REENTRANT              0
-#define configENABLE_BACKWARD_COMPATIBILITY     1
-#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
-
-#define configSUPPORT_STATIC_ALLOCATION         1
-#define configSUPPORT_DYNAMIC_ALLOCATION        0
-
-/* Hook function related definitions. */
-#define configUSE_IDLE_HOOK                    0
-#define configUSE_TICK_HOOK                    0
-#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
-#define configCHECK_FOR_STACK_OVERFLOW         2
-#define configCHECK_HANDLER_INSTALLATION       0
-
-/* Run time and task stats gathering related definitions. */
-#define configGENERATE_RUN_TIME_STATS          0
-#define configRECORD_STACK_HIGH_ADDRESS        1
-#define configUSE_TRACE_FACILITY               1 // legacy trace
-#define configUSE_STATS_FORMATTING_FUNCTIONS   0
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES                  0
-#define configMAX_CO_ROUTINE_PRIORITIES        2
-
-/* Software timer related definitions. */
-#define configUSE_TIMERS                       1
-#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
-#define configTIMER_QUEUE_LENGTH               32
-#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
-
-/* Optional functions - most linkers will remove unused functions anyway. */
-#define INCLUDE_vTaskPrioritySet               0
-#define INCLUDE_uxTaskPriorityGet              0
-#define INCLUDE_vTaskDelete                    0
-#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
-#define INCLUDE_xResumeFromISR                 0
-#define INCLUDE_vTaskDelayUntil                1
-#define INCLUDE_vTaskDelay                     1
-#define INCLUDE_xTaskGetSchedulerState         0
-#define INCLUDE_xTaskGetCurrentTaskHandle      1
-#define INCLUDE_uxTaskGetStackHighWaterMark    0
-#define INCLUDE_xTaskGetIdleTaskHandle         0
-#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#define INCLUDE_pcTaskGetTaskName              0
-#define INCLUDE_eTaskGetState                  0
-#define INCLUDE_xEventGroupSetBitFromISR       0
-#define INCLUDE_xTimerPendFunctionCall         0
-
-/* FreeRTOS hooks to NVIC vectors */
-#define xPortPendSVHandler    PendSV_Handler
-#define xPortSysTickHandler   SysTick_Handler
-#define vPortSVCHandler       SVC_Handler
-
-//--------------------------------------------------------------------+
-// Interrupt nesting behavior configuration.
-//--------------------------------------------------------------------+
-
-// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       3
-
-/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
-#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
-
-/* The highest interrupt priority that can be used by any interrupt service
-routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
-INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
-PRIORITY THAN THIS! (higher priorities are lower numeric values. */
-#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
-
-/* Interrupt priorities used by the kernel port layer itself.  These are generic
-to all Cortex-M ports, and do not rely on any particular library functions. */
-#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
-See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
-
-#endif
diff --git a/hw/bsp/mcxn/boards/frdmmcxn947/board.cmake b/hw/bsp/mcxn/boards/frdmmcxn947/board.cmake
deleted file mode 100644
index 8c3280743..000000000
--- a/hw/bsp/mcxn/boards/frdmmcxn947/board.cmake
+++ /dev/null
@@ -1,21 +0,0 @@
-set(MCU_VARIANT MCXN947)
-set(MCU_CORE MCXN947_cm33_core0)
-
-set(JLINK_DEVICE MCXN947_M33_0)
-set(PYOCD_TARGET MCXN947)
-set(NXPLINK_DEVICE MCXN947:MCXN947)
-
-set(PORT 1)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    CPU_MCXN947VDF_cm33_core0
-    BOARD_TUD_RHPORT=${PORT}
-    # port 0 is fullspeed, port 1 is highspeed
-    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    )
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
-    )
-endfunction()
diff --git a/hw/bsp/mcxn/boards/frdmmcxn947/board.h b/hw/bsp/mcxn/boards/frdmmcxn947/board.h
deleted file mode 100644
index acb73363f..000000000
--- a/hw/bsp/mcxn/boards/frdmmcxn947/board.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_GPIO              GPIO0
-#define LED_CLK               kCLOCK_Gpio0
-#define LED_PIN               10 // red
-#define LED_STATE_ON          0
-
-// WAKE button (Dummy, use unused pin
-#define BUTTON_GPIO           GPIO0
-#define BUTTON_CLK            kCLOCK_Gpio0
-#define BUTTON_PIN            23
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              LPUART4
-
-static inline void board_uart_init_clock(void) {
-  /* attach FRO 12M to FLEXCOMM4 */
-  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
-  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
-
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/mcxn/boards/frdmmcxn947/board.mk b/hw/bsp/mcxn/boards/frdmmcxn947/board.mk
deleted file mode 100644
index aaad5e73e..000000000
--- a/hw/bsp/mcxn/boards/frdmmcxn947/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = MCXN947
-MCU_CORE = MCXN947_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_MCXN947VDF_cm33_core0
-
-JLINK_DEVICE = MCXN947_M33_0
-PYOCD_TARGET = MCXN947
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/hw/bsp/mcxn/boards/frdmmcxn947/clock_config.c b/hw/bsp/mcxn/boards/frdmmcxn947/clock_config.c
deleted file mode 100644
index 37d2b4dfc..000000000
--- a/hw/bsp/mcxn/boards/frdmmcxn947/clock_config.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v10.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
-board: MCX-N9XX-EVK
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "clock_config.h"
-#include "fsl_clock.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 18 MHz}
-- {id: System_clock.outFreq, value: 72 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
diff --git a/hw/bsp/mcxn/boards/frdmmcxn947/clock_config.h b/hw/bsp/mcxn/boards/frdmmcxn947/clock_config.h
deleted file mode 100644
index c238a0423..000000000
--- a/hw/bsp/mcxn/boards/frdmmcxn947/clock_config.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.c b/hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.c
deleted file mode 100644
index c33790ac5..000000000
--- a/hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v12.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
- -  {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
-    open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitPins(void)
-{
-  /* Enables the clock for PORT0: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port0);
-
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-
-
-    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P0 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
-
-    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P1 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
-
-    const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
-                                   kPORT_PullDisable,
-                                   /* Low internal pull resistor value is selected. */
-                                   kPORT_LowPullResistor,
-                                   /* Fast slew rate is configured */
-                                   kPORT_FastSlewRate,
-                                   /* Passive input filter is disabled */
-                                   kPORT_PassiveFilterDisable,
-                                   /* Open drain output is disabled */
-                                   kPORT_OpenDrainDisable,
-                                   /* Low drive strength is configured */
-                                   kPORT_LowDriveStrength,
-                                   /* Pin is configured as PIO0_23 */
-                                   kPORT_MuxAlt0,
-                                   /* Digital input enabled */
-                                   kPORT_InputBufferEnable,
-                                   /* Digital input is not inverted */
-                                   kPORT_InputNormal,
-                                   /* Pin Control Register fields [15:0] are not locked */
-                                   kPORT_UnlockRegister};
-    /* PORT0_23 (pin B7) is configured as PIO0_23 */
-    PORT_SetPinConfig(PORT0, 23U, &SW2);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.h b/hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.h
deleted file mode 100644
index 40968c275..000000000
--- a/hw/bsp/mcxn/boards/frdmmcxn947/pin_mux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcxn/boards/mcxn947brk/board.cmake b/hw/bsp/mcxn/boards/mcxn947brk/board.cmake
deleted file mode 100644
index 8c3280743..000000000
--- a/hw/bsp/mcxn/boards/mcxn947brk/board.cmake
+++ /dev/null
@@ -1,21 +0,0 @@
-set(MCU_VARIANT MCXN947)
-set(MCU_CORE MCXN947_cm33_core0)
-
-set(JLINK_DEVICE MCXN947_M33_0)
-set(PYOCD_TARGET MCXN947)
-set(NXPLINK_DEVICE MCXN947:MCXN947)
-
-set(PORT 1)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    CPU_MCXN947VDF_cm33_core0
-    BOARD_TUD_RHPORT=${PORT}
-    # port 0 is fullspeed, port 1 is highspeed
-    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
-    )
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
-    )
-endfunction()
diff --git a/hw/bsp/mcxn/boards/mcxn947brk/board.h b/hw/bsp/mcxn/boards/mcxn947brk/board.h
deleted file mode 100644
index eae98bfa7..000000000
--- a/hw/bsp/mcxn/boards/mcxn947brk/board.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_GPIO              GPIO3
-#define LED_CLK               kCLOCK_Gpio3
-#define LED_PIN               4 // red
-#define LED_STATE_ON          0
-
-// WAKE button (Dummy, use unused pin
-#define BUTTON_GPIO           GPIO0
-#define BUTTON_CLK            kCLOCK_Gpio0
-#define BUTTON_PIN            6
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_DEV              LPUART4
-
-static inline void board_uart_init_clock(void) {
-  /* attach FRO 12M to FLEXCOMM4 */
-  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
-  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
-}
-
-//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
-//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
-
-// XTAL
-#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/mcxn/boards/mcxn947brk/board.mk b/hw/bsp/mcxn/boards/mcxn947brk/board.mk
deleted file mode 100644
index aaad5e73e..000000000
--- a/hw/bsp/mcxn/boards/mcxn947brk/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-MCU_VARIANT = MCXN947
-MCU_CORE = MCXN947_cm33_core0
-PORT ?= 1
-
-CFLAGS += -DCPU_MCXN947VDF_cm33_core0
-
-JLINK_DEVICE = MCXN947_M33_0
-PYOCD_TARGET = MCXN947
-
-# flash using pyocd
-flash: flash-jlink
diff --git a/hw/bsp/mcxn/boards/mcxn947brk/clock_config.c b/hw/bsp/mcxn/boards/mcxn947brk/clock_config.c
deleted file mode 100644
index 37d2b4dfc..000000000
--- a/hw/bsp/mcxn/boards/mcxn947brk/clock_config.c
+++ /dev/null
@@ -1,338 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Setup clock sources.
- *
- * 2. Set up wait states of the flash.
- *
- * 3. Set up all dividers.
- *
- * 4. Set up all selectors to provide selected clocks.
- *
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v10.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
-board: MCX-N9XX-EVK
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "clock_config.h"
-#include "fsl_clock.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-// extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockPLL150M();
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFRO12M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 12 MHz}
-- {id: Slow_clock.outFreq, value: 3 MHz}
-- {id: System_clock.outFreq, value: 12 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-void BOARD_BootClockFRO12M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF48M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 48 MHz}
-- {id: Slow_clock.outFreq, value: 12 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF48M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockFROHF144M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 144 MHz}
-- {id: MAIN_clock.outFreq, value: 144 MHz}
-- {id: Slow_clock.outFreq, value: 18 MHz}
-- {id: System_clock.outFreq, value: 72 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.FIRC.outFreq, value: 144 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-void BOARD_BootClockFROHF144M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL150M
-called_from_default_init: true
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: FRO_HF_clock.outFreq, value: 48 MHz}
-- {id: MAIN_clock.outFreq, value: 150 MHz}
-- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
-- {id: Slow_clock.outFreq, value: 37.5 MHz}
-- {id: System_clock.outFreq, value: 150 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL0_Mode, value: Normal}
-- {id: RunPowerMode, value: OD}
-- {id: SCGMode, value: PLL0}
-- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
-- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
-- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
-- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL150M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
-
-    /*!< Set up PLL0 */
-    const pll_setup_t pll0Setup = {
-        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
-        .pllndiv = SCG_APLLNDIV_NDIV(8U),
-        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
-        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
-        .pllRate = 150000000U
-    };
-    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
-    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockPLL100M
-outputs:
-- {id: CLK_144M_clock.outFreq, value: 144 MHz}
-- {id: CLK_48M_clock.outFreq, value: 48 MHz}
-- {id: CLK_IN_clock.outFreq, value: 24 MHz}
-- {id: FRO_12M_clock.outFreq, value: 12 MHz}
-- {id: MAIN_clock.outFreq, value: 100 MHz}
-- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
-- {id: Slow_clock.outFreq, value: 25 MHz}
-- {id: System_clock.outFreq, value: 100 MHz}
-- {id: gdet_clock.outFreq, value: 48 MHz}
-- {id: trng_clock.outFreq, value: 48 MHz}
-settings:
-- {id: PLL1_Mode, value: Normal}
-- {id: SCGMode, value: PLL1}
-- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
-- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
-- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
-- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
-- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
-- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
-sources:
-- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-/*******************************************************************************
- * Code for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-void BOARD_BootClockPLL100M(void)
-{
-    /*!< Enable SCG clock */
-    CLOCK_EnableClock(kCLOCK_Scg);
-
-    CLOCK_SetupExtClocking(24000000U);
-    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
-
-    /*!< Set up PLL1 */
-    const pll_setup_t pll1Setup = {
-        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
-        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
-        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
-        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
-        .pllRate = 100000000U
-    };
-    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
-    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
-
-    /*!< Set up clock selectors - Attach clocks to the peripheries */
-    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
-
-    /*!< Set up dividers */
-    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
-
-    /* Set SystemCoreClock variable */
-    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
-}
diff --git a/hw/bsp/mcxn/boards/mcxn947brk/clock_config.h b/hw/bsp/mcxn/boards/mcxn947brk/clock_config.h
deleted file mode 100644
index c238a0423..000000000
--- a/hw/bsp/mcxn/boards/mcxn947brk/clock_config.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockFRO12M **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
-#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFRO12M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFRO12M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF48M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
-#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF48M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF48M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************* Configuration BOARD_BootClockFROHF144M ********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
-#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockFROHF144M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockFROHF144M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL150M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
-#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL150M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL150M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ******************** Configuration BOARD_BootClockPLL100M *********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
-#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
-
-
-/*******************************************************************************
- * API for BOARD_BootClockPLL100M configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockPLL100M(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcxn/boards/mcxn947brk/pin_mux.c b/hw/bsp/mcxn/boards/mcxn947brk/pin_mux.c
deleted file mode 100644
index acc2f3e45..000000000
--- a/hw/bsp/mcxn/boards/mcxn947brk/pin_mux.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Pins v12.0
-processor: MCXN947
-package_id: MCXN947VDF
-mcu_data: ksdk2_0
-processor_version: 0.12.3
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-#include "fsl_common.h"
-#include "fsl_port.h"
-#include "pin_mux.h"
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitBootPins
- * Description   : Calls initialization functions.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitBootPins(void)
-{
-    BOARD_InitPins();
-}
-
-/* clang-format off */
-/*
- * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-BOARD_InitPins:
-- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
-- pin_list:
-  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
-    invert_input: normal}
-  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
-    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
-  - {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
-    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
- */
-/* clang-format on */
-
-/* FUNCTION ************************************************************************************************************
- *
- * Function Name : BOARD_InitPins
- * Description   : Configures pin routing and optionally pin electrical features.
- *
- * END ****************************************************************************************************************/
-void BOARD_InitPins(void)
-{
-    /* Enables the clock for PORT1: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port1);
-    /* Enables the clock for PORT3: Enables clock */
-    CLOCK_EnableClock(kCLOCK_Port3);
-
-    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P0 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_8 (pin A1) is configured as FC4_P0 */
-    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
-
-    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
-                                                    kPORT_PullDisable,
-                                                    /* Low internal pull resistor value is selected. */
-                                                    kPORT_LowPullResistor,
-                                                    /* Fast slew rate is configured */
-                                                    kPORT_FastSlewRate,
-                                                    /* Passive input filter is disabled */
-                                                    kPORT_PassiveFilterDisable,
-                                                    /* Open drain output is disabled */
-                                                    kPORT_OpenDrainDisable,
-                                                    /* Low drive strength is configured */
-                                                    kPORT_LowDriveStrength,
-                                                    /* Pin is configured as FC4_P1 */
-                                                    kPORT_MuxAlt2,
-                                                    /* Digital input enabled */
-                                                    kPORT_InputBufferEnable,
-                                                    /* Digital input is not inverted */
-                                                    kPORT_InputNormal,
-                                                    /* Pin Control Register fields [15:0] are not locked */
-                                                    kPORT_UnlockRegister};
-    /* PORT1_9 (pin B1) is configured as FC4_P1 */
-    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
-
-    const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
-                                                     kPORT_PullDisable,
-                                                     /* Low internal pull resistor value is selected. */
-                                                     kPORT_LowPullResistor,
-                                                     /* Fast slew rate is configured */
-                                                     kPORT_FastSlewRate,
-                                                     /* Passive input filter is disabled */
-                                                     kPORT_PassiveFilterDisable,
-                                                     /* Open drain output is disabled */
-                                                     kPORT_OpenDrainDisable,
-                                                     /* Low drive strength is configured */
-                                                     kPORT_LowDriveStrength,
-                                                     /* Pin is configured as PIO3_4 */
-                                                     kPORT_MuxAlt0,
-                                                     /* Digital input enabled */
-                                                     kPORT_InputBufferEnable,
-                                                     /* Digital input is not inverted */
-                                                     kPORT_InputNormal,
-                                                     /* Pin Control Register fields [15:0] are not locked */
-                                                     kPORT_UnlockRegister};
-    /* PORT3_4 (pin F14) is configured as PIO3_4 */
-    PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
-}
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcxn/boards/mcxn947brk/pin_mux.h b/hw/bsp/mcxn/boards/mcxn947brk/pin_mux.h
deleted file mode 100644
index 40968c275..000000000
--- a/hw/bsp/mcxn/boards/mcxn947brk/pin_mux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2022 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _PIN_MUX_H_
-#define _PIN_MUX_H_
-
-/*!
- * @addtogroup pin_mux
- * @{
- */
-
-/***********************************************************************************************************************
- * API
- **********************************************************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
- * @brief Calls initialization functions.
- *
- */
-void BOARD_InitBootPins(void);
-
-/*!
- * @brief Configures pin routing and optionally pin electrical features.
- *
- */
-void BOARD_InitPins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*!
- * @}
- */
-#endif /* _PIN_MUX_H_ */
-
-/***********************************************************************************************************************
- * EOF
- **********************************************************************************************************************/
diff --git a/hw/bsp/mcxn/debug.jlinkscript b/hw/bsp/mcxn/debug.jlinkscript
deleted file mode 100644
index fd8bcffef..000000000
--- a/hw/bsp/mcxn/debug.jlinkscript
+++ /dev/null
@@ -1,5 +0,0 @@
-int SetupTarget(void) {
-  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
-
-  return 0;
-}
diff --git a/hw/bsp/mcxn/family.c b/hw/bsp/mcxn/family.c
deleted file mode 100644
index 8672ca63f..000000000
--- a/hw/bsp/mcxn/family.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_lpuart.h"
-#include "board.h"
-
-#include "pin_mux.h"
-#include "clock_config.h"
-
-#ifdef BOARD_TUD_RHPORT
-  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_DEVICE(_n)  0
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
-#else
-  #define PORT_SUPPORT_HOST(_n)    0
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-void USB1_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-void board_init(void)
-{
-  BOARD_InitPins();
-  BOARD_InitBootClocks();
-  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
-
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  // LED
-  CLOCK_EnableClock(LED_CLK);
-  gpio_pin_config_t led_config = {
-      kGPIO_DigitalOutput,
-      0,
-  };
-  GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
-  board_led_write(0);
-
-#ifdef NEOPIXEL_PIN
-  // Neopixel
-  static uint32_t pixelData[NEOPIXEL_NUMBER];
-  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
-
-  sctpix_init(NEOPIXEL_TYPE);
-  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
-  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
-  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
-  sctpix_show();
-#endif
-
-  // Button
-#ifdef BUTTON_GPIO
-  CLOCK_EnableClock(BUTTON_CLK);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
-#endif
-
-#ifdef UART_DEV
-  // UART
-//  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
-//  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
-
-  // Enable UART when debug log is on
-  board_uart_init_clock();
-
-  lpuart_config_t uart_config;
-  LPUART_GetDefaultConfig(&uart_config);
-  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
-  LPUART_Init(UART_DEV, &uart_config, 12000000u);
-#endif
-
-  // USB VBUS
-  /* PORT0 PIN22 configured as USB0_VBUS */
-
-#if PORT_SUPPORT_DEVICE(0)
-  // Port0 is Full Speed
-
-  CLOCK_AttachClk(kCLK_48M_to_USB0);
-  CLOCK_EnableClock(kCLOCK_Usb0Ram);
-  CLOCK_EnableClock(kCLOCK_Usb0Fs);
-  CLOCK_EnableUsbfsClock();
-#endif
-
-#if PORT_SUPPORT_DEVICE(1)
-  // Port1 is High Speed
-
-  // Power
-  SPC0->ACTIVE_VDELAY = 0x0500;
-  /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
-  SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
-  SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
-                      SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
-  /* Wait until it is done */
-  while (SPC0->SC & SPC_SC_BUSY_MASK) {}
-  if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
-    SCG0->TRIM_LOCK = 0x5a5a0001U;
-    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
-    /* wait LDO ready */
-    while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
-  }
-  SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
-  SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
-  /* xtal = 20 ~ 30MHz */
-  SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
-  SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
-  while (1) {
-    if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
-      break;
-    }
-  }
-
-  // Clock
-  SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
-  CLOCK_EnableClock(kCLOCK_UsbHs);
-  CLOCK_EnableClock(kCLOCK_UsbHsPhy);
-  CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
-  CLOCK_EnableUsbhsClock();
-
-  // USB PHY
-#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
-  USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
-#endif
-
-  // Enable PHY support for Low speed device + LS via FS Hub
-  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-  // Enable all power for normal operation
-  USBPHY->PWD = 0;
-
-  // TX Timing
-  uint32_t phytx = USBPHY->TX;
-  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-  phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
-  //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-  USBPHY->TX = phytx;
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-
-#ifdef NEOPIXEL_PIN
-  if (state) {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
-  } else {
-    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
-    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
-  }
-  sctpix_show();
-#endif
-}
-
-uint32_t board_button_read(void)
-{
-#ifdef BUTTON_GPIO
-  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
-#endif
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-#ifdef UART_DEV
-  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
-  return len;
-#else
-  (void) buf; (void) len;
-  return 0;
-#endif
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/mcxn/family.cmake b/hw/bsp/mcxn/family.cmake
deleted file mode 100644
index 13d1d44ef..000000000
--- a/hw/bsp/mcxn/family.cmake
+++ /dev/null
@@ -1,110 +0,0 @@
-include_guard()
-
-if (NOT BOARD)
-  message(FATAL_ERROR "BOARD not specified")
-endif ()
-
-set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# toolchain set up
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-
-set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
-
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      # external driver
-      #lib/sct_neopixel/sct_neopixel.c
-
-      # driver
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
-      # mcu
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-      )
-    #  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    #    )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      # driver
-      # mcu
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-      )
-
-    update_board(${BOARD_TARGET})
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_sources(${BOARD_TARGET} PUBLIC
-        ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
-        )
-      target_link_options(${BOARD_TARGET} PUBLIC
-        # linker file
-        "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS})
-  target_sources(${TARGET}-tinyusb PUBLIC
-    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
-    ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
-    )
-  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
-
-  # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
-
-  # Flashing
-  family_flash_jlink(${TARGET})
-  #family_flash_nxplink(${TARGET})
-  #family_flash_pyocd(${TARGET})
-endfunction()
diff --git a/hw/bsp/mcxn/family.mk b/hw/bsp/mcxn/family.mk
deleted file mode 100644
index 526effdfb..000000000
--- a/hw/bsp/mcxn/family.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-UF2_FAMILY_ID = 0x2abc77ec
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-CPU_CORE ?= cortex-m33
-
-# Default to Highspeed PORT1
-PORT ?= 1
-
-CFLAGS += \
-  -flto \
-  -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
-  -DBOARD_TUD_RHPORT=$(PORT) \
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
-
-# All source paths should be relative to the top level.
-LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
-
-# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
-ifeq ($(PORT), 1)
-  $(info "PORT1 High Speed")
-  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-	SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
-else
-  $(info "PORT0 Full Speed")
-  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-  SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
-endif
-
-SRC_C += \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
-	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
-	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
-
-SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 21ae3a71e..7b6da5f59 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -100,10 +100,10 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
-#elif TU_CHECK_MCU(OPT_MCU_MCXA)
+#elif TU_CHECK_MCU(OPT_MCU_MCXA15)
   // USB0 is chipidea FS
   #define TUP_USBIP_CHIPIDEA_FS
-  #define TUP_USBIP_CHIPIDEA_FS_MCXA
+  #define TUP_USBIP_CHIPIDEA_FS_MCX
 
   #define TUP_DCD_ENDPOINT_MAX    16
 
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcx.h b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
index 3bfcd398e..bf88df0f4 100644
--- a/src/portable/chipidea/ci_fs/ci_fs_mcx.h
+++ b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
@@ -29,19 +29,30 @@
 
 #include "fsl_device_registers.h"
 
-#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USBFS0_BASE)
+#if CFG_TUSB_MCU == OPT_MCU_MCXN9
+	#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USBFS0_BASE)
+	#define USB0_IRQN 				USB0_FS_IRQn
+
+#elif CFG_TUSB_MCU == OPT_MCU_MCXA15
+	#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
+	#define USB0_IRQN 				USB0_IRQn
+	
+#else
+  #error "MCU is not supported"
+#endif
+
 #define CI_REG                  CI_FS_REG(0)
 
 void dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
-  NVIC_EnableIRQ(USB0_FS_IRQn);
+  NVIC_EnableIRQ(USB0_IRQN);
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
   (void) rhport;
-  NVIC_DisableIRQ(USB0_FS_IRQn);
+  NVIC_DisableIRQ(USB0_IRQN);
 }
 
 #endif
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcxa.h b/src/portable/chipidea/ci_fs/ci_fs_mcxa.h
deleted file mode 100644
index 81786efdf..000000000
--- a/src/portable/chipidea/ci_fs/ci_fs_mcxa.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2023 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef _CI_FS_MCXA_H
-#define _CI_FS_MCXA_H
-
-#include "fsl_device_registers.h"
-
-#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
-#define CI_REG                  CI_FS_REG(0)
-
-void dcd_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_EnableIRQ(USB0_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB0_IRQn);
-}
-
-#endif
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index 08e73711f..9327e09d8 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -35,8 +35,6 @@
   #include "ci_fs_kinetis.h"
 #elif defined(TUP_USBIP_CHIPIDEA_FS_MCX)
   #include "ci_fs_mcx.h"
-#elif defined(TUP_USBIP_CHIPIDEA_FS_MCXA)
-  #include "ci_fs_mcxa.h"
 #else
   #error "MCU is not supported"
 #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index fe9c44e96..e46e641f3 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -175,7 +175,7 @@
 
 // NXP LPC MCX
 #define OPT_MCU_MCXN9            2300  ///< NXP MCX N9 Series
-#define OPT_MCU_MCXA             2301  ///< NXP MCX A Series
+#define OPT_MCU_MCXA15           2301  ///< NXP MCX A15 Series
 
 // Check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
-- 
cgit v1.3.1


From 13d26d216613792e814dda4742ef7ab4fb9b0d37 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Feb 2024 19:20:28 +0700
Subject: slightly change cdc_msc_freertos example

---
 examples/device/cdc_msc_freertos/src/main.c | 51 +++++++++++++++--------------
 src/class/video/video.h                     |  6 +++-
 2 files changed, 32 insertions(+), 25 deletions(-)

(limited to 'src')

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 1dadc4513..e94e8eaec 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -52,7 +52,8 @@
   #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
-#define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
+#define CDC_STACK_SIZE      configMINIMAL_STACK_SIZE
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPES
@@ -69,21 +70,22 @@ enum {
   BLINK_SUSPENDED = 2500,
 };
 
-// static timer & task
+// static task
 #if configSUPPORT_STATIC_ALLOCATION
-StaticTimer_t blinky_tmdef;
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
 
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
-StackType_t  cdc_stack[CDC_STACK_SZIE];
+StackType_t  cdc_stack[CDC_STACK_SIZE];
 StaticTask_t cdc_taskdef;
 #endif
 
-TimerHandle_t blinky_tm;
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-static void led_blinky_cb(TimerHandle_t xTimer);
 static void usb_device_task(void *param);
+void led_blinking_task(void* param);
 void cdc_task(void *params);
 
 //--------------------------------------------------------------------+
@@ -94,22 +96,20 @@ int main(void) {
   board_init();
 
 #if configSUPPORT_STATIC_ALLOCATION
-  // soft timer for blinky
-  blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
+  // blinky task
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
 
   // Create a task for tinyusb device stack
   xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
 
   // Create CDC task
-  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef);
 #else
-  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
   xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
   xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
 #endif
 
-  xTimerStart(blinky_tm, 0);
-
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
@@ -154,12 +154,12 @@ static void usb_device_task(void *param) {
 
 // Invoked when device is mounted
 void tud_mount_cb(void) {
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
 void tud_umount_cb(void) {
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+  blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
@@ -167,16 +167,12 @@ void tud_umount_cb(void) {
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
 void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
+  blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
 void tud_resume_cb(void) {
-  if (tud_mounted()) {
-    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
-  } else {
-    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
-  }
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -235,10 +231,17 @@ void tud_cdc_rx_cb(uint8_t itf) {
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-static void led_blinky_cb(TimerHandle_t xTimer) {
-  (void) xTimer;
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
   static bool led_state = false;
 
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+  while (1) {
+    // Blink every interval ms
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    start_ms += blink_interval_ms;
+
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
 }
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 6319c6536..abf1e34b9 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -368,6 +368,8 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bCopyProtect;
 } tusb_desc_video_format_uncompressed_t;
 
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_uncompressed_t) == 27, "size is not correct");
+
 // Uncompressed payload specs: 3.1.2 frame descriptor
 #define tusb_desc_video_frame_uncompressed_nint_t(_nint) \
   struct TU_ATTR_PACKED { \
@@ -381,7 +383,7 @@ typedef struct TU_ATTR_PACKED {
     uint32_t dwMinBitRate; \
     uint32_t dwMaxBitRate; \
     uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \
-    uint32_t dwDefaultFrameInterval; \
+    uint32_t dwDefaultFrameInterval; /* 100ns unit */\
     uint8_t  bFrameIntervalType; \
     uint32_t dwFrameInterval[_nint]; \
   }
@@ -413,6 +415,8 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bCopyProtect;
 } tusb_desc_video_format_mjpeg_t;
 
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_mjpeg_t) == 11, "size is not correct");
+
 // MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
 typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
 typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t;
-- 
cgit v1.3.1


From ec91660119c6ce4ccc6aa011f2c6cc9869ab9410 Mon Sep 17 00:00:00 2001
From: Jerry Palacios <jerry.palacios@wavenumber.net>
Date: Thu, 22 Feb 2024 16:11:23 -0600
Subject: Revert "Merge branch 'hathach:master' into MCX"

This reverts commit 6afd4a57896f9c9e794de3ab6eabc73d18be4bd0, reversing
changes made to 5c14bd13da211ff2679115b0dba96ac80c1a516c.
---
 examples/device/cdc_msc_freertos/src/main.c        |  51 +--
 hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk |   3 +
 .../boards/frdm_k32l2a4s/clock_config.c            | 491 ---------------------
 .../boards/frdm_k32l2a4s/clock_config.h            | 164 -------
 hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk   |   3 +
 .../boards/frdm_k32l2b/clock_config.c              | 220 ---------
 .../boards/frdm_k32l2b/clock_config.h              | 110 -----
 hw/bsp/nrf/boards/pca10095/board.cmake             |   3 -
 hw/bsp/nrf/boards/pca10095/board.h                 |   4 +-
 hw/bsp/nrf/boards/pca10095/board.mk                |   3 -
 hw/bsp/nrf/family.c                                |   1 -
 src/class/msc/msc_device.c                         |   2 +-
 src/class/video/video.h                            |   6 +-
 src/class/video/video_device.c                     |   1 -
 src/common/tusb_debug.h                            |   3 +-
 src/common/tusb_fifo.c                             |   1 -
 src/device/usbd.c                                  |   1 +
 src/host/usbh.c                                    |  22 +-
 src/host/usbh_pvt.h                                |   6 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c              |   8 +-
 src/portable/ohci/ohci.h                           |   2 +-
 21 files changed, 52 insertions(+), 1053 deletions(-)
 delete mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
 delete mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
 delete mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
 delete mode 100644 hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h

(limited to 'src')

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index e94e8eaec..1dadc4513 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -52,8 +52,7 @@
   #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
-#define CDC_STACK_SIZE      configMINIMAL_STACK_SIZE
-#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
+#define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPES
@@ -70,22 +69,21 @@ enum {
   BLINK_SUSPENDED = 2500,
 };
 
-// static task
+// static timer & task
 #if configSUPPORT_STATIC_ALLOCATION
-StackType_t blinky_stack[BLINKY_STACK_SIZE];
-StaticTask_t blinky_taskdef;
+StaticTimer_t blinky_tmdef;
 
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
-StackType_t  cdc_stack[CDC_STACK_SIZE];
+StackType_t  cdc_stack[CDC_STACK_SZIE];
 StaticTask_t cdc_taskdef;
 #endif
 
-static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+TimerHandle_t blinky_tm;
 
+static void led_blinky_cb(TimerHandle_t xTimer);
 static void usb_device_task(void *param);
-void led_blinking_task(void* param);
 void cdc_task(void *params);
 
 //--------------------------------------------------------------------+
@@ -96,20 +94,22 @@ int main(void) {
   board_init();
 
 #if configSUPPORT_STATIC_ALLOCATION
-  // blinky task
-  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
+  // soft timer for blinky
+  blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
 
   // Create a task for tinyusb device stack
   xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
 
   // Create CDC task
-  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef);
+  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 #else
-  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
+  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
   xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
   xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
 #endif
 
+  xTimerStart(blinky_tm, 0);
+
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
@@ -154,12 +154,12 @@ static void usb_device_task(void *param) {
 
 // Invoked when device is mounted
 void tud_mount_cb(void) {
-  blink_interval_ms = BLINK_MOUNTED;
+  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
 }
 
 // Invoked when device is unmounted
 void tud_umount_cb(void) {
-  blink_interval_ms = BLINK_NOT_MOUNTED;
+  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
 }
 
 // Invoked when usb bus is suspended
@@ -167,12 +167,16 @@ void tud_umount_cb(void) {
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
 void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
-  blink_interval_ms = BLINK_SUSPENDED;
+  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
 }
 
 // Invoked when usb bus is resumed
 void tud_resume_cb(void) {
-  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
+  if (tud_mounted()) {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  } else {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -231,17 +235,10 @@ void tud_cdc_rx_cb(uint8_t itf) {
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinking_task(void* param) {
-  (void) param;
-  static uint32_t start_ms = 0;
+static void led_blinky_cb(TimerHandle_t xTimer) {
+  (void) xTimer;
   static bool led_state = false;
 
-  while (1) {
-    // Blink every interval ms
-    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
-    start_ms += blink_interval_ms;
-
-    board_led_write(led_state);
-    led_state = 1 - led_state; // toggle
-  }
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
 }
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
index c4dc65b63..f69700139 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
@@ -8,6 +8,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
 
+SRC_C += \
+	$(MCU_DIR)/project_template/clock_config.c \
+
 # For flash-jlink target
 JLINK_DEVICE = K32L2A41xxxxA
 
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
deleted file mode 100644
index 2814efc86..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
- *    Note: The clock could not be set when it is being used as system clock.
- *    In default out of reset, the CPU is clocked from FIRC(IRC48M),
- *    so before setting FIRC, change to use another available clock source.
- *
- * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
- *
- * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
- *    Wait until the system clock source is changed to target source.
- *
- * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
- *    corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
- *    Supported run mode and clock restrictions could be found in Reference Manual.
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v7.0
-processor: K32L2A41xxxxA
-package_id: K32L2A41VLL1A
-mcu_data: ksdk2_0
-processor_version: 9.0.0
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "fsl_smc.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define SCG_CLKOUTCNFG_SIRC                               2U  /*!< SCG CLKOUT clock select: Slow IRC */
-#define SCG_SOSC_DISABLE                                  0U  /*!< System OSC disabled */
-#define SCG_SPLL_DISABLE                                  0U  /*!< System PLL disabled */
-#define SCG_SYS_OSC_CAP_0P                                0U  /*!< Oscillator 0pF capacitor load */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-/*FUNCTION**********************************************************************
- *
- * Function Name : CLOCK_CONFIG_SetScgOutSel
- * Description   : Set the SCG clock out select (CLKOUTSEL).
- * Param setting : The selected clock source.
- *
- *END**************************************************************************/
-static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
-{
-     SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
-}
-
-/*FUNCTION**********************************************************************
- *
- * Function Name : CLOCK_CONFIG_FircSafeConfig
- * Description   : This function is used to safely configure FIRC clock.
- *                 In default out of reset, the CPU is clocked from FIRC(IRC48M).
- *                 Before setting FIRC, change to use SIRC as system clock,
- *                 then configure FIRC. After FIRC is set, change back to use FIRC
- *                 in case SIRC need to be configured.
- * Param fircConfig  : FIRC configuration.
- *
- *END**************************************************************************/
-static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
-{
-    scg_sys_clk_config_t curConfig;
-    const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
-                                             .div1 = kSCG_AsyncClkDisable,
-                                             .div3 = kSCG_AsyncClkDivBy2,
-                                             .range = kSCG_SircRangeHigh};
-    scg_sys_clk_config_t sysClkSafeConfigSource = {
-         .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-         .reserved1 = 0,
-         .reserved2 = 0,
-         .reserved3 = 0,
-#endif
-         .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-         .reserved4 = 0,
-#endif
-         .src = kSCG_SysClkSrcSirc,    /* System clock source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-         .reserved5 = 0,
-#endif
-    };
-    /* Init Sirc. */
-    CLOCK_InitSirc(&scgSircConfig);
-    /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
-    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != sysClkSafeConfigSource.src);
-
-    /* Init Firc. */
-    CLOCK_InitFirc(fircConfig);
-    /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
-    sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
-    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != sysClkSafeConfigSource.src);
-}
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockRUN();
-}
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockRUN
-called_from_default_init: true
-outputs:
-- {id: Core_clock.outFreq, value: 48 MHz}
-- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
-- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
-- {id: SIRCDIV3_CLK.outFreq, value: 4 MHz}
-- {id: SIRC_CLK.outFreq, value: 8 MHz}
-- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
-- {id: Slow_clock.outFreq, value: 24 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-settings:
-- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
-- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
-- {id: SCG.SIRCDIV3.scale, value: '2', locked: true}
-- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
-- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
-sources:
-- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockRUN configuration
- ******************************************************************************/
-const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
-    {
-        .divSlow = kSCG_SysClkDivBy2,             /* Slow Clock Divider: divided by 2 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved1 = 0,
-        .reserved2 = 0,
-        .reserved3 = 0,
-#endif
-        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved4 = 0,
-#endif
-        .src = kSCG_SysClkSrcFirc,                /* Fast IRC is selected as System Clock Source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved5 = 0,
-#endif
-    };
-const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
-    {
-        .freq = 32768U,                           /* System Oscillator frequency: 32768Hz */
-        .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
-        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 3: divided by 1 */
-        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
-        .workMode = kSCG_SysOscModeOscLowPower,   /* Oscillator low power */
-    };
-const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
-    {
-        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
-        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDivBy2,              /* Slow IRC Clock Divider 3: divided by 2 */
-        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
-    };
-const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
-    {
-        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
-        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
-        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
-        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
-    };
-const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
-    {
-        .enableMode = SCG_SPLL_DISABLE,           /* System PLL disabled */
-        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 3: Clock output is disabled */
-        .src = kSCG_SysPllSrcSysOsc,              /* System PLL clock source is System OSC */
-        .prediv = 0,                              /* Divided by 1 */
-        .mult = 0,                                /* Multiply Factor is 16 */
-    };
-/*******************************************************************************
- * Code for BOARD_BootClockRUN configuration
- ******************************************************************************/
-void BOARD_BootClockRUN(void)
-{
-    scg_sys_clk_config_t curConfig;
-
-    /* Init SOSC according to board configuration. */
-    CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
-    /* Set the XTAL0 frequency based on board settings. */
-    CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
-    /* Init FIRC. */
-    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
-    /* Init SIRC. */
-    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
-    /* Set SCG to FIRC mode. */
-    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockHSRUN **********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockHSRUN
-outputs:
-- {id: CLKOUT.outFreq, value: 8 MHz}
-- {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
-- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
-- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
-- {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
-- {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
-- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
-- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
-- {id: SIRC_CLK.outFreq, value: 8 MHz}
-- {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
-- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
-- {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SCGMode, value: SPLL}
-- {id: powerMode, value: HSRUN}
-- {id: CLKOUTConfig, value: 'yes'}
-- {id: SCG.DIVSLOW.scale, value: '4'}
-- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
-- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
-- {id: SCG.PREDIV.scale, value: '4'}
-- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
-- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
-- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
-- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
-- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
-- {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
-- {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
-- {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
-- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
-- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
-- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
-sources:
-- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
-    {
-        .divSlow = kSCG_SysClkDivBy4,             /* Slow Clock Divider: divided by 4 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved1 = 0,
-        .reserved2 = 0,
-        .reserved3 = 0,
-#endif
-        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved4 = 0,
-#endif
-        .src = kSCG_SysClkSrcSysPll,              /* System PLL is selected as System Clock Source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved5 = 0,
-#endif
-    };
-const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
-    {
-        .freq = 32768U,                           /* System Oscillator frequency: 32768Hz */
-        .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
-        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* System OSC Clock Divider 3: divided by 1 */
-        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
-        .workMode = kSCG_SysOscModeOscLowPower,   /* Oscillator low power */
-    };
-const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
-    {
-        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
-        .div1 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
-        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
-    };
-const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
-    {
-        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
-        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
-        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
-        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
-    };
-const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN =
-    {
-        .enableMode = kSCG_SysPllEnable,          /* Enable SPLL clock */
-        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDivBy1,              /* System PLL Clock Divider 1: divided by 1 */
-        .div3 = kSCG_AsyncClkDivBy1,              /* System PLL Clock Divider 3: divided by 1 */
-        .src = kSCG_SysPllSrcFirc,                /* System PLL clock source is Fast IRC */
-        .prediv = 3,                              /* Divided by 4 */
-        .mult = 0,                                /* Multiply Factor is 16 */
-    };
-/*******************************************************************************
- * Code for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-void BOARD_BootClockHSRUN(void)
-{
-    scg_sys_clk_config_t curConfig;
-
-    /* Init SOSC according to board configuration. */
-    CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
-    /* Set the XTAL0 frequency based on board settings. */
-    CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
-    /* Init FIRC. */
-    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
-    /* Init SIRC. */
-    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
-    /* Init SysPll. */
-    CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
-    /* Set HSRUN power mode. */
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-    SMC_SetPowerModeHsrun(SMC);
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
-    {
-    }
-
-    /* Set SCG to SPLL mode. */
-    CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
-    /* Wait for clock source switch finished. */
-    do
-    {
-         CLOCK_GetCurSysClkConfig(&curConfig);
-    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
-    /* Set SCG CLKOUT selection. */
-    CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockVLPR
-outputs:
-- {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: SIRC_CLK.outFreq, value: 8 MHz}
-- {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
-- {id: System_clock.outFreq, value: 8 MHz}
-settings:
-- {id: SCGMode, value: SIRC}
-- {id: powerMode, value: VLPR}
-- {id: SCG.DIVSLOW.scale, value: '8'}
-- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
-- {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
-sources:
-- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
-    {
-        .divSlow = kSCG_SysClkDivBy8,             /* Slow Clock Divider: divided by 8 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved1 = 0,
-        .reserved2 = 0,
-        .reserved3 = 0,
-#endif
-        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved4 = 0,
-#endif
-        .src = kSCG_SysClkSrcSirc,                /* Slow IRC is selected as System Clock Source */
-#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
-        .reserved5 = 0,
-#endif
-    };
-const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
-    {
-        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
-        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
-        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
-        .capLoad = SCG_SYS_OSC_CAP_0P,            /* Oscillator capacity load: 0pF */
-        .workMode = kSCG_SysOscModeExt,           /* Use external clock */
-    };
-const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
-    {
-        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
-        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 3: Clock output is disabled */
-        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
-    };
-const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
-    {
-        .enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower,/* Enable FIRC clock, Enable FIRC in low power mode */
-        .div1 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 3: Clock output is disabled */
-        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
-        .trimConfig = NULL,                       /* Fast IRC Trim disabled */
-    };
-const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR =
-    {
-        .enableMode = SCG_SPLL_DISABLE,           /* System PLL disabled */
-        .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
-        .div1 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 1: Clock output is disabled */
-        .div3 = kSCG_AsyncClkDisable,             /* System PLL Clock Divider 3: Clock output is disabled */
-        .src = kSCG_SysPllSrcSysOsc,              /* System PLL clock source is System OSC */
-        .prediv = 0,                              /* Divided by 1 */
-        .mult = 0,                                /* Multiply Factor is 16 */
-    };
-/*******************************************************************************
- * Code for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-void BOARD_BootClockVLPR(void)
-{
-    /* Init FIRC. */
-    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
-    /* Init SIRC. */
-    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
-    /* Allow SMC all power modes. */
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-    /* Set VLPR power mode. */
-    SMC_SetPowerModeVlpr(SMC);
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
-    {
-    }
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
-}
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
deleted file mode 100644
index c01d5e03c..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/clock_config.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ                            32768U  /*!< Board xtal0 frequency in Hz */
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
-
-/*! @brief SCG set for BOARD_BootClockRUN configuration.
- */
-extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
-/*! @brief System OSC set for BOARD_BootClockRUN configuration.
- */
-extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
-/*! @brief SIRC set for BOARD_BootClockRUN configuration.
- */
-extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
-/*! @brief FIRC set for BOARD_BootClockRUN configuration.
- */
-extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
-extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockRUN;
-/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
- */
-
-/*******************************************************************************
- * API for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockRUN(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockHSRUN **********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK            96000000U  /*!< Core clock frequency: 96000000Hz */
-
-/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
-/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
-/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
-/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
- */
-extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
-extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
-/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
- */
-
-/*******************************************************************************
- * API for BOARD_BootClockHSRUN configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockHSRUN(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              8000000U  /*!< Core clock frequency: 8000000Hz */
-
-/*! @brief SCG set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
-/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
-/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
-/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
- */
-extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
-extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockVLPR;
-/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
- */
-
-/*******************************************************************************
- * API for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockVLPR(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
index 9cf36c500..82456b721 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
@@ -8,6 +8,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
 
+SRC_C += \
+	$(MCU_DIR)/project_template/clock_config.c \
+
 # For flash-jlink target
 JLINK_DEVICE = K32L2B31xxxxA
 
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
deleted file mode 100644
index e74000827..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-/*
- * How to setup clock using clock driver functions:
- *
- * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
- *    and flash clock are in allowed range during clock mode switch.
- *
- * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
- *
- * 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
- *
- * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
- */
-
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!GlobalInfo
-product: Clocks v7.0
-processor: K32L2B31xxxxA
-package_id: K32L2B31VLH0A
-mcu_data: ksdk2_0
-processor_version: 9.0.0
-board: FRDM-K32L2B
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-#include "fsl_smc.h"
-#include "clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
-#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
-#define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-void BOARD_InitBootClocks(void)
-{
-    BOARD_BootClockRUN();
-}
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockRUN
-called_from_default_init: true
-outputs:
-- {id: Bus_clock.outFreq, value: 24 MHz}
-- {id: Core_clock.outFreq, value: 48 MHz}
-- {id: Flash_clock.outFreq, value: 24 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: MCGIRCLK.outFreq, value: 8 MHz}
-- {id: MCGPCLK.outFreq, value: 48 MHz}
-- {id: System_clock.outFreq, value: 48 MHz}
-settings:
-- {id: MCGMode, value: HIRC}
-- {id: MCG.CLKS.sel, value: MCG.HIRC}
-- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: MCG_C2_RANGE0_CFG, value: Very_high}
-- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
-- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
-- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
-- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
-- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
-- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
-- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
-sources:
-- {id: MCG.HIRC.outFreq, value: 48 MHz}
-- {id: OSC.OSC.outFreq, value: 32 MHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockRUN configuration
- ******************************************************************************/
-const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
-    {
-        .outSrc = kMCGLITE_ClkSrcHirc,            /* MCGOUTCLK source is HIRC */
-        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
-        .ircs = kMCGLITE_Lirc8M,                  /* Slow internal reference (LIRC) 8 MHz clock selected */
-        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .hircEnableInNotHircMode = true,          /* HIRC source is enabled */
-    };
-const sim_clock_config_t simConfig_BOARD_BootClockRUN =
-    {
-        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
-        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
-    };
-const osc_config_t oscConfig_BOARD_BootClockRUN =
-    {
-        .freq = 0U,                               /* Oscillator frequency: 0Hz */
-        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
-        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
-        .oscerConfig =
-            {
-                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
-            }
-    };
-
-/*******************************************************************************
- * Code for BOARD_BootClockRUN configuration
- ******************************************************************************/
-void BOARD_BootClockRUN(void)
-{
-    /* Set the system clock dividers in SIM to safe value. */
-    CLOCK_SetSimSafeDivs();
-    /* Set MCG to HIRC mode. */
-    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
-    /* Set the clock configuration in SIM module. */
-    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
-}
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/* clang-format off */
-/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
-!!Configuration
-name: BOARD_BootClockVLPR
-outputs:
-- {id: Bus_clock.outFreq, value: 1 MHz}
-- {id: Core_clock.outFreq, value: 2 MHz}
-- {id: Flash_clock.outFreq, value: 1 MHz}
-- {id: LPO_clock.outFreq, value: 1 kHz}
-- {id: MCGIRCLK.outFreq, value: 2 MHz}
-- {id: System_clock.outFreq, value: 2 MHz}
-settings:
-- {id: MCGMode, value: LIRC2M}
-- {id: powerMode, value: VLPR}
-- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
-- {id: RTCCLKOUTConfig, value: 'yes'}
-- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
-- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
-sources:
-- {id: MCG.LIRC.outFreq, value: 2 MHz}
-- {id: OSC.OSC.outFreq, value: 32.768 kHz}
- * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
-/* clang-format on */
-
-/*******************************************************************************
- * Variables for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
-    {
-        .outSrc = kMCGLITE_ClkSrcLirc,            /* MCGOUTCLK source is LIRC */
-        .irclkEnableMode = kMCGLITE_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
-        .ircs = kMCGLITE_Lirc2M,                  /* Slow internal reference (LIRC) 2 MHz clock selected */
-        .fcrdiv = kMCGLITE_LircDivBy1,            /* Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .lircDiv2 = kMCGLITE_LircDivBy1,          /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
-        .hircEnableInNotHircMode = false,         /* HIRC source is not enabled */
-    };
-const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
-    {
-        .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
-        .clkdiv1 = 0x10000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
-    };
-const osc_config_t oscConfig_BOARD_BootClockVLPR =
-    {
-        .freq = 0U,                               /* Oscillator frequency: 0Hz */
-        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
-        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
-        .oscerConfig =
-            {
-                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
-            }
-    };
-
-/*******************************************************************************
- * Code for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-void BOARD_BootClockVLPR(void)
-{
-    /* Set the system clock dividers in SIM to safe value. */
-    CLOCK_SetSimSafeDivs();
-    /* Set MCG to LIRC2M mode. */
-    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
-    /* Set the clock configuration in SIM module. */
-    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
-    /* Set VLPR power mode. */
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
-    SMC_SetPowerModeVlpr(SMC, false);
-#else
-    SMC_SetPowerModeVlpr(SMC);
-#endif
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
-    {
-    }
-    /* Set SystemCoreClock variable. */
-    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
-}
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
deleted file mode 100644
index 37328e7d8..000000000
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/clock_config.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2019 ,2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/***********************************************************************************************************************
- * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
- * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
- **********************************************************************************************************************/
-
-#ifndef _CLOCK_CONFIG_H_
-#define _CLOCK_CONFIG_H_
-
-#include "fsl_common.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*******************************************************************************
- ************************ BOARD_InitBootClocks function ************************
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes default configuration of clocks.
- *
- */
-void BOARD_InitBootClocks(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************** Configuration BOARD_BootClockRUN ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
-
-/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
- */
-extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
-/*! @brief SIM module set for BOARD_BootClockRUN configuration.
- */
-extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
-/*! @brief OSC set for BOARD_BootClockRUN configuration.
- */
-extern const osc_config_t oscConfig_BOARD_BootClockRUN;
-
-/*******************************************************************************
- * API for BOARD_BootClockRUN configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockRUN(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-/*******************************************************************************
- ********************* Configuration BOARD_BootClockVLPR ***********************
- ******************************************************************************/
-/*******************************************************************************
- * Definitions for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              2000000U  /*!< Core clock frequency: 2000000Hz */
-
-/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
- */
-extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
-/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
- */
-extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
-/*! @brief OSC set for BOARD_BootClockVLPR configuration.
- */
-extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
-
-/*******************************************************************************
- * API for BOARD_BootClockVLPR configuration
- ******************************************************************************/
-#if defined(__cplusplus)
-extern "C" {
-#endif /* __cplusplus*/
-
-/*!
- * @brief This function executes configuration of clocks.
- *
- */
-void BOARD_BootClockVLPR(void);
-
-#if defined(__cplusplus)
-}
-#endif /* __cplusplus*/
-
-#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index 0fbc1d31f..ca5399a3a 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT nrf5340_application)
 set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
 
-# enable max3421 host driver for this board
-set(MAX3421_HOST 1)
-
 function(update_board TARGET)
   target_sources(${TARGET} PRIVATE
     ${NRFX_DIR}/drivers/src/nrfx_usbreg.c
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
index 7437dad48..ad3379bf6 100644
--- a/hw/bsp/nrf/boards/pca10095/board.h
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -42,8 +42,8 @@
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-#define UART_RX_PIN           22
-#define UART_TX_PIN           20
+#define UART_RX_PIN           32
+#define UART_TX_PIN           33
 
 // SPI for USB host shield
 #define MAX3421_SCK_PIN  _PINNUM(1, 15)
diff --git a/hw/bsp/nrf/boards/pca10095/board.mk b/hw/bsp/nrf/boards/pca10095/board.mk
index 20580d619..9c4edbafc 100644
--- a/hw/bsp/nrf/boards/pca10095/board.mk
+++ b/hw/bsp/nrf/boards/pca10095/board.mk
@@ -2,9 +2,6 @@ CPU_CORE = cortex-m33
 MCU_VARIANT = nrf5340_application
 CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
 
-# enable max3421 host driver for this board
-MAX3421_HOST = 1
-
 LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf5340_xxaa_application.ld
 
 SRC_C += hw/mcu/nordic/nrfx/drivers/src/nrfx_usbreg.c
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 55119ef02..7a970f52e 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -76,7 +76,6 @@ enum {
   #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
   #define VBUSDETECT_Msk USBREG_USBREGSTATUS_VBUSDETECT_Msk
   #define OUTPUTRDY_Msk USBREG_USBREGSTATUS_OUTPUTRDY_Msk
-  #define GPIOTE_IRQn GPIOTE1_IRQn
 #else
   #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_RC
   #define VBUSDETECT_Msk POWER_USBREGSTATUS_VBUSDETECT_Msk
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index c145d86a6..2589dcd2c 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -203,7 +203,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL
+#if CFG_TUSB_DEBUG >= 2
 
 TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
 {
diff --git a/src/class/video/video.h b/src/class/video/video.h
index abf1e34b9..6319c6536 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -368,8 +368,6 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bCopyProtect;
 } tusb_desc_video_format_uncompressed_t;
 
-TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_uncompressed_t) == 27, "size is not correct");
-
 // Uncompressed payload specs: 3.1.2 frame descriptor
 #define tusb_desc_video_frame_uncompressed_nint_t(_nint) \
   struct TU_ATTR_PACKED { \
@@ -383,7 +381,7 @@ TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_uncompressed_t) == 27, "size is n
     uint32_t dwMinBitRate; \
     uint32_t dwMaxBitRate; \
     uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \
-    uint32_t dwDefaultFrameInterval; /* 100ns unit */\
+    uint32_t dwDefaultFrameInterval; \
     uint8_t  bFrameIntervalType; \
     uint32_t dwFrameInterval[_nint]; \
   }
@@ -415,8 +413,6 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bCopyProtect;
 } tusb_desc_video_format_mjpeg_t;
 
-TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_mjpeg_t) == 11, "size is not correct");
-
 // MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
 typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
 typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t;
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index c33dfa0b0..1affd615e 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -559,7 +559,6 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
           uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
           if (num_intervals) {
             interval = 0;
-            interval_ms = 0;
           } else {
             interval = frm->uncompressed.dwFrameInterval[2];
             interval_ms = interval / 10000;
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 2e9f1d9cd..0f4dc93f3 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -60,7 +60,6 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
 
 static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
   for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
-  tu_printf("\r\n");
 }
 
 // Log with Level
@@ -77,7 +76,7 @@ static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_BUF(_x, _n)   tu_print_buf((uint8_t const*)(_x), _n)
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = 0x%lX\r\n", (unsigned long) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 76696396b..d6c3db4ce 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -224,7 +224,6 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
       }
       break;
-    default: break;
   }
 }
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index be85d7769..5c94ebcc5 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -500,6 +500,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 
       case DCD_EVENT_SETUP_RECEIVED:
         TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
+        TU_LOG_USBD("\r\n");
 
         // Mark as connected after receiving 1st setup packet.
         // But it is easier to set it every time instead of wasting time to check then set
diff --git a/src/host/usbh.c b/src/host/usbh.c
index f56290a0c..dfe6ddb42 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -343,12 +343,12 @@ bool tuh_init(uint8_t controller_id) {
   if ( tuh_inited() ) return true;
 
   TU_LOG_USBH("USBH init on controller %u\r\n", controller_id);
-  TU_LOG_INT_USBH(sizeof(usbh_device_t));
-  TU_LOG_INT_USBH(sizeof(hcd_event_t));
-  TU_LOG_INT_USBH(sizeof(_ctrl_xfer));
-  TU_LOG_INT_USBH(sizeof(tuh_xfer_t));
-  TU_LOG_INT_USBH(sizeof(tu_fifo_t));
-  TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(usbh_device_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(hcd_event_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(_ctrl_xfer));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tuh_xfer_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_fifo_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_edpt_stream_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -588,7 +588,8 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
   TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
               (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
                   tu_str_std_request[xfer->setup->bRequest] : "Class Request");
-  TU_LOG_BUF_USBH(xfer->setup, 8);
+  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8);
+  TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb) {
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
@@ -659,8 +660,9 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
-    TU_LOG_BUF_USBH(request, 8);
+    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG1_BUF(request, 8);
+    TU_LOG1("\r\n");
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);
@@ -678,7 +680,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
       case CONTROL_STAGE_DATA:
         if (request->wLength) {
           TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2);
+          TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
         _ctrl_xfer.actual_len = (uint16_t) xferred_bytes;
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 4ed2a72b5..4a97a1c18 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -35,11 +35,7 @@
  extern "C" {
 #endif
 
-#define TU_LOG_USBH(...)      TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
-#define TU_LOG_MEM_USBH(...)  TU_LOG_MEM(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
-#define TU_LOG_BUF_USBH(...)  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
-#define TU_LOG_INT_USBH(...)  TU_LOG_INT(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
-#define TU_LOG_HEX_USBH(...)  TU_LOG_HEX(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
 
 enum {
   USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 841cda752..4e702aed4 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -653,11 +653,7 @@ void dcd_int_handler(uint8_t rhport)
     if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
     {
       iso_enabled = true;
-      // Transfer from endpoint to RAM only if data is not corrupted
-      if ((int_status & USBD_INTEN_USBEVENT_Msk) == 0 ||
-          (NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_ISOOUTCRC_Msk) == 0) {
-        xact_out_dma(EP_ISO_NUM);
-      }
+      xact_out_dma(EP_ISO_NUM);
     }
 
     // ISOIN: Notify client that data was transferred
@@ -687,7 +683,7 @@ void dcd_int_handler(uint8_t rhport)
   {
     TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
 
-    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk };
+    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk };
     uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
     NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt
 
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 94bad5df7..4feefd771 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -83,7 +83,7 @@ typedef struct TU_ATTR_ALIGNED(16)
   volatile uint32_t condition_code : 4;
 
 	// Word 1
-	uint8_t* volatile current_buffer_pointer;
+	volatile uint8_t* current_buffer_pointer;
 
 	// Word 2 : next TD
 	volatile uint32_t next;
-- 
cgit v1.3.1


From 3d3bf45102ded992fc10be09f3e9b9c981379ad1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Feb 2024 00:36:07 +0700
Subject: frdm k64f usb work well, add kinetis_k to ci cmake

---
 .github/workflows/cmake_arm.yml                 |  2 +-
 hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex | 43 +++++++++++++++++++++++--
 hw/bsp/kinetis_k/family.c                       |  4 ++-
 hw/bsp/kinetis_k/family.cmake                   |  1 +
 hw/bsp/kinetis_k/family.mk                      |  1 +
 src/portable/chipidea/ci_fs/ci_fs_kinetis.h     |  6 ++--
 src/portable/chipidea/ci_fs/dcd_ci_fs.c         |  8 +++++
 src/portable/nxp/khci/dcd_khci.c                | 14 +++-----
 8 files changed, 60 insertions(+), 19 deletions(-)

(limited to 'src')

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index f97645ad1..80ab1ea71 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -38,7 +38,7 @@ jobs:
         family:
           # Alphabetical order
           - 'imxrt'
-          - 'kinetis_kl'
+          - 'kinetis_k kinetis_kl'
           - 'lpc17 lpc18 lpc40 lpc43'
           - 'lpc54 lpc55'
           - 'mcx'
diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex b/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex
index 28d1ea612..4a8c77f95 100644
--- a/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex
+++ b/hw/bsp/kinetis_k/boards/frdm_k64f/frdm_k64f.mex
@@ -732,15 +732,27 @@
       </dcdx>
       <periphs name="Peripherals" version="13.0" enabled="true" update_project_code="true">
          <dependencies>
-            <dependency resourceType="Tool" resourceId="Clocks" description="The Clocks tool is required by the Peripherals tool, but it is disabled." problem_level="2" source="Peripherals">
+            <dependency resourceType="SWComponent" resourceId="middleware.usb.common_header" description="USB Common Header is not found in the toolchain/IDE project. The project will not compile!" problem_level="2" source="Peripherals">
                <feature name="enabled" evaluation="equal">
-                  <data>true</data>
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="middleware.usb.common_header" description="An unsupported version of the USB Common Header in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. The project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="compatible">
+                  <data type="Version">2.8.0</data>
                </feature>
             </dependency>
          </dependencies>
          <generated_project_files>
             <file path="board/peripherals.c" update_enabled="true"/>
             <file path="board/peripherals.h" update_enabled="true"/>
+            <file path="source/generated/usb_device_composite.c" update_enabled="true"/>
+            <file path="source/generated/usb_device_composite.h" update_enabled="true"/>
+            <file path="source/generated/usb_device_config.h" update_enabled="true"/>
+            <file path="source/generated/usb_device_descriptor.c" update_enabled="true"/>
+            <file path="source/generated/usb_device_descriptor.h" update_enabled="true"/>
+            <file path="source/usb_device_interface_0_cic_vcom.c" update_enabled="true"/>
+            <file path="source/usb_device_interface_0_cic_vcom.h" update_enabled="true"/>
          </generated_project_files>
          <peripherals_profile>
             <processor_version>14.0.0</processor_version>
@@ -755,6 +767,31 @@
                         <data type="Boolean">true</data>
                      </feature>
                   </dependency>
+                  <dependency resourceType="SWComponent" resourceId="middleware.usb.device_controller_khci" description="&quot;USB Device KHCI Controller Driver(FS)&quot; component is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="&quot;Common&quot; driver is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="ClockOutput" resourceId="USB48MCLK" description="USB Function Clock (USB48MCLK) is inactive and USB module will not work." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="middleware.usb.device.cdc.external" description="&quot;USB device CDC&quot; driver is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="middleware.usb.device.cdc.external" description="&quot;USB device CDC&quot; driver is missing in the project." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="enabled" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
                </dependencies>
                <instances>
                   <instance name="NVIC" uuid="e1a88231-4d9e-46a3-b134-d2c743110640" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
@@ -789,7 +826,7 @@
                         <setting name="mpuInit" value="disabled"/>
                      </config_set>
                   </instance>
-                  <instance name="USB0" uuid="cc0eb411-8fed-4548-b79c-9a8340cc02fd" type="usb" type_id="usb_cbf31fb9a3cef21890d93e737c3d2690" mode="device" peripheral="USB0" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
+                  <instance name="USB0" uuid="cc0eb411-8fed-4548-b79c-9a8340cc02fd" type="usb" type_id="usb_cbf31fb9a3cef21890d93e737c3d2690" mode="device" peripheral="USB0" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
                      <config_set name="deviceSetting" quick_selection="QS_DEVICE_CDC_VCOM">
                         <setting name="vendor_id" value="0x1FC9"/>
                         <setting name="product_id" value="0x0094"/>
diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c
index 38cfc45e3..6df29c1fc 100644
--- a/hw/bsp/kinetis_k/family.c
+++ b/hw/bsp/kinetis_k/family.c
@@ -30,6 +30,7 @@
 #include "fsl_port.h"
 #include "fsl_clock.h"
 #include "fsl_uart.h"
+#include "fsl_sysmpu.h"
 
 #include "board/clock_config.h"
 #include "board/pin_mux.h"
@@ -50,6 +51,7 @@ void board_init(void) {
   BOARD_InitBootPins();
   BOARD_BootClockRUN();
   SystemCoreClockUpdate();
+  SYSMPU_Enable(SYSMPU, 0);
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -84,7 +86,7 @@ void board_init(void) {
 #endif
 
   // USB
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
+  // USB clock is configured in BOARD_BootClockRUN()
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake
index 6d642c101..e0b5fcfc8 100644
--- a/hw/bsp/kinetis_k/family.cmake
+++ b/hw/bsp/kinetis_k/family.cmake
@@ -40,6 +40,7 @@ function(add_board_target BOARD_TARGET)
       ${SDK_DIR}/drivers/gpio
       ${SDK_DIR}/drivers/port
       ${SDK_DIR}/drivers/smc
+      ${SDK_DIR}/drivers/sysmpu
       ${SDK_DIR}/drivers/uart
       )
 
diff --git a/hw/bsp/kinetis_k/family.mk b/hw/bsp/kinetis_k/family.mk
index de352a6a9..995873eec 100644
--- a/hw/bsp/kinetis_k/family.mk
+++ b/hw/bsp/kinetis_k/family.mk
@@ -29,6 +29,7 @@ INC += \
 	$(TOP)/$(SDK_DIR)/drivers/gpio \
 	$(TOP)/$(SDK_DIR)/drivers/port \
 	$(TOP)/$(SDK_DIR)/drivers/smc \
+	$(TOP)/$(SDK_DIR)/drivers/sysmpu \
 	$(TOP)/$(SDK_DIR)/drivers/uart \
 
 SRC_S += ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
diff --git a/src/portable/chipidea/ci_fs/ci_fs_kinetis.h b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
index cd21af1c7..31e14a546 100644
--- a/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
+++ b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
@@ -36,14 +36,12 @@
 #define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
 #define CI_REG                  CI_FS_REG(0)
 
-void dcd_int_enable(uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   (void) rhport;
   NVIC_EnableIRQ(USB0_IRQn);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   (void) rhport;
   NVIC_DisableIRQ(USB0_IRQn);
 }
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index 9327e09d8..4b1d488b5 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -271,9 +271,17 @@ void dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
+  // save crystal-less setting (recovery clock)
+  uint32_t clk_recover_irc_en = CI_REG->CLK_RECOVER_IRC_EN;
+  uint32_t clk_recover_ctrl = CI_REG->CLK_RECOVER_CTRL;;
+
   CI_REG->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (CI_REG->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
 
+  // restore crystal-less setting
+  CI_REG->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
+  CI_REG->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
+
   tu_memclr(&_dcd, sizeof(_dcd));
   CI_REG->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
   CI_REG->BDT_PAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 5a2f768b3..5d04a524a 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -269,22 +269,16 @@ void dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
-#if (CFG_TUSB_MCU == OPT_MCU_KINETIS_K)
-  uint32_t clk_recover_irc_en;
-  uint32_t clk_recover_ctrl;
-
-  clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN;
-  clk_recover_ctrl   = KHCI->CLK_RECOVER_CTRL;
+  // save crystal-less setting (recovery clock)
+  uint32_t clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN;
+  uint32_t clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL;
 
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
 
+  // restore crystal-less setting
   KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
   KHCI->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
-#else
-  KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
-  while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
-#endif
 
   tu_memclr(&_dcd, sizeof(_dcd));
   KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
-- 
cgit v1.3.1


From 65a2e5cdf8d708b88bb8edf7b718f698e5a18ffc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Feb 2024 00:53:05 +0700
Subject: fix build with cpu without USB_CLK_RECOVER using old dcd_khci driver

---
 .idea/cmake.xml                  | 2 +-
 src/portable/nxp/khci/dcd_khci.c | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index dbb34aaab..ebc6a0570 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -59,7 +59,7 @@
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="frdm_k64f" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_k64f -DLOG=2 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="frdm_k64f" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_k64f -DLOG=2 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
       <configuration PROFILE_NAME="stm32f411disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f411disco -DLOG=2 -DLOGGER=RTT" />
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 5d04a524a..3419c2565 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -270,15 +270,19 @@ void dcd_init(uint8_t rhport)
   (void) rhport;
 
   // save crystal-less setting (recovery clock)
+  #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN
   uint32_t clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN;
   uint32_t clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL;
+  #endif
 
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
 
   // restore crystal-less setting
+  #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN
   KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
   KHCI->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
+  #endif
 
   tu_memclr(&_dcd, sizeof(_dcd));
   KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
-- 
cgit v1.3.1


From a52b4647ec20414bbfde986c13a18598ffd426d6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Feb 2024 17:18:30 +0700
Subject: only save/restore CLK_RECOVER_IRC_EN/CTRL if
 FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED is defined to 1

---
 src/portable/chipidea/ci_fs/dcd_ci_fs.c | 10 +++++++---
 src/portable/nxp/khci/dcd_khci.c        |  8 ++++----
 2 files changed, 11 insertions(+), 7 deletions(-)

(limited to 'src')

diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index 4b1d488b5..a68ecf8c9 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -271,16 +271,20 @@ void dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
-  // save crystal-less setting (recovery clock)
+  // save crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
   uint32_t clk_recover_irc_en = CI_REG->CLK_RECOVER_IRC_EN;
-  uint32_t clk_recover_ctrl = CI_REG->CLK_RECOVER_CTRL;;
+  uint32_t clk_recover_ctrl = CI_REG->CLK_RECOVER_CTRL;
+  #endif
 
   CI_REG->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (CI_REG->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
 
-  // restore crystal-less setting
+  // restore crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
   CI_REG->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
   CI_REG->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
+  #endif
 
   tu_memclr(&_dcd, sizeof(_dcd));
   CI_REG->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 3419c2565..dc71117b3 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -269,8 +269,8 @@ void dcd_init(uint8_t rhport)
 {
   (void) rhport;
 
-  // save crystal-less setting (recovery clock)
-  #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN
+  // save crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
   uint32_t clk_recover_irc_en = KHCI->CLK_RECOVER_IRC_EN;
   uint32_t clk_recover_ctrl = KHCI->CLK_RECOVER_CTRL;
   #endif
@@ -278,8 +278,8 @@ void dcd_init(uint8_t rhport)
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
 
-  // restore crystal-less setting
-  #ifdef USB_CLK_RECOVER_IRC_EN_IRC_EN
+  // restore crystal-less setting (if available)
+  #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1
   KHCI->CLK_RECOVER_IRC_EN = clk_recover_irc_en;
   KHCI->CLK_RECOVER_CTRL  |= clk_recover_ctrl;
   #endif
-- 
cgit v1.3.1


From 23450d4f6bba4b5b92e242a61684dfcf171e6cbe Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 24 Feb 2024 15:51:02 +0100
Subject: fixed compiler warning src/tusb.c

---
 src/tusb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/tusb.c b/src/tusb.c
index 7943ea5ef..3ef380c83 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -477,7 +477,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
   uint8_t const *buf8 = (uint8_t const *) buf;
 
   char format[] = "%00X";
-  format[2] += 2*size;
+  format[2] += (uint8_t) (2*size); // 1 byte = 2 hex digits
 
   const uint8_t item_per_line  = 16 / size;
 
-- 
cgit v1.3.1


From 5ce7b147117826dd75c2d7b347df80b0177e7252 Mon Sep 17 00:00:00 2001
From: Tommie Gannert <tommie@gannert.se>
Date: Mon, 26 Feb 2024 11:41:50 +0100
Subject: add notification support for device class USBTMC.

The ep_int_in is already used for responding to USB488
READ_STATUS_BYTE requests, but that EP is defined for all of USBTMC.
This extends the functionality to let callers send notifications and
receive ACKs.
---
 src/class/usbtmc/usbtmc.h        | 25 +++++++++++++++++++++++++
 src/class/usbtmc/usbtmc_device.c | 16 +++++++++++++++-
 src/class/usbtmc/usbtmc_device.h | 20 +++++++++++++++-----
 3 files changed, 55 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index 090ab3c4a..327de087c 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -183,6 +183,23 @@ typedef enum {
 
 } usmtmc_request_type_enum;
 
+typedef enum {
+  // The last and first valid bNotify1 for use by the USBTMC class specification.
+  USBTMC_bNOTIFY1_USBTMC_FIRST          = 0x00,
+  USBTMC_bNOTIFY1_USBTMC_LAST           = 0x3F,
+
+  // The last and first valid bNotify1 for use by vendors.
+  USBTMC_bNOTIFY1_VENDOR_SPECIFIC_FIRST = 0x40,
+  USBTMC_bNOTIFY1_VENDOR_SPECIFIC_LAST  = 0x7F,
+
+  // The last and first valid bNotify1 for use by USBTMC subclass specifications.
+  USBTMC_bNOTIFY1_SUBCLASS_FIRST        = 0x80,
+  USBTMC_bNOTIFY1_SUBCLASS_LAST         = 0xFF,
+
+  // From the USB488 Subclass Specification, Section 3.4.
+  USB488_bNOTIFY1_SRQ                   = 0x81,
+} usbtmc_int_in_payload_format;
+
 typedef enum {
   USBTMC_STATUS_SUCCESS = 0x01,
   USBTMC_STATUS_PENDING = 0x02,
@@ -303,6 +320,14 @@ typedef struct TU_ATTR_PACKED
 
 TU_VERIFY_STATIC(sizeof(usbtmc_read_stb_rsp_488_t) == 3u, "struct wrong length");
 
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t bNotify1; // Must be USB488_bNOTIFY1_SRQ
+  uint8_t StatusByte;
+} usbtmc_srq_interrupt_488_t;
+
+TU_VERIFY_STATIC(sizeof(usbtmc_srq_interrupt_488_t) == 2u, "struct wrong length");
+
 typedef struct TU_ATTR_PACKED
 {
   struct TU_ATTR_PACKED
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 573654d58..debe445fd 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -240,6 +240,18 @@ bool tud_usbtmc_transmit_dev_msg_data(
   return true;
 }
 
+bool tud_usbtmc_transmit_notification_data(const void * data, size_t len)
+{
+#ifndef NDEBUG
+  TU_ASSERT(len >= 1);
+  TU_ASSERT(usbtmc_state.ep_int_in != 0);
+#endif
+  if (usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in)) return false;
+
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, (void *)data, len));
+  return true;
+}
+
 void usbtmcd_init_cb(void)
 {
   usbtmc_state.capabilities = tud_usbtmc_get_capabilities_cb();
@@ -578,7 +590,9 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     }
   }
   else if (ep_addr == usbtmc_state.ep_int_in) {
-    // Good?
+    if (tud_usbtmc_notification_complete_cb) {
+      TU_VERIFY(tud_usbtmc_notification_complete_cb());
+    }
     return true;
   }
   return false;
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index c1298ddb8..2f3c91dbd 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -73,6 +73,10 @@ bool tud_usbtmc_check_abort_bulk_in_cb(usbtmc_check_abort_bulk_rsp_t *rsp);
 bool tud_usbtmc_check_abort_bulk_out_cb(usbtmc_check_abort_bulk_rsp_t *rsp);
 bool tud_usbtmc_check_clear_cb(usbtmc_get_clear_status_rsp_t *rsp);
 
+// The interrupt-IN endpoint buffer was transmitted to the host. Use
+// tud_usbtmc_transmit_notification_data to send another notification.
+TU_ATTR_WEAK bool tud_usbtmc_notification_complete_cb(void);
+
 // Indicator pulse should be 0.5 to 1.0 seconds long
 TU_ATTR_WEAK bool tud_usbtmc_indicator_pulse_cb(tusb_control_request_t const * msg, uint8_t *tmcResult);
 
@@ -93,6 +97,17 @@ bool tud_usbtmc_transmit_dev_msg_data(
     const void * data, size_t len,
     bool endOfMessage, bool usingTermChar);
 
+// Buffers a notification to be sent to the host. The buffer must be
+// valid until the tud_usbtmc_notification_complete_cb callback. The
+// data starts with the bNotify1 field, see the USBTMC Specification,
+// Table 13.
+//
+// If the previous notification data has not yet been sent, this
+// returns false.
+//
+// Requires an interrupt endpoint in the interface.
+bool tud_usbtmc_transmit_notification_data(const void * data, size_t len);
+
 bool tud_usbtmc_start_bus_read(void);
 
 
@@ -104,9 +119,4 @@ bool     usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result,
 bool     usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 void     usbtmcd_init_cb(void);
 
-/************************************************************
- * USBTMC Descriptor Templates
- *************************************************************/
-
-
 #endif /* CLASS_USBTMC_USBTMC_DEVICE_H_ */
-- 
cgit v1.3.1


From 473d400cfde768e26fe8644bab3d655c81777b64 Mon Sep 17 00:00:00 2001
From: Taylor Yu <code@argon.blue>
Date: Sun, 25 Feb 2024 11:12:24 -0600
Subject: work around possible RP2040 erratum

RP2040 device controller does not seem to clear pending transactions
configured in EP0 buffer controls when the host aborts a control
transfer. This causes assertion failures, including when a buffer
AVAILABLE flag set for a previous transfer causes an unexpected
transaction completion.
---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 31 ++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

(limited to 'src')

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index e8cee73fd..51174f709 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -217,6 +217,18 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 
 TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void)
 {
+    // Abort any transactions from a prior control transfer, because
+    // receiving SETUP doesn't reset buffer control state. This works around
+    // a possible USB hardware erratum.
+
+    // With this workaround a race window still exists, but smaller.
+    // ABORT flag is unusable prior to hardware B2 (RP2040-E2), so a larger
+    // race window exists for B1 and earlier.
+    if (rp2040_chip_version() >= 2) {
+        usb_hw_set->abort = 0x3;
+        while ((usb_hw->abort_done & 0x3) != 0x3)
+            ;
+    }
     // If we have finished this transfer on EP0 set pid back to 1 for next
     // setup transfer. Also clear a stall in case
     uint8_t addrs[] = {0x0, 0x80};
@@ -224,6 +236,25 @@ TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void)
     {
         struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]);
         ep->next_pid = 1u;
+        // Reset the buffer control now to minimize race conditions
+        _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL);
+        // Explicit delay, because the one in
+        // _hw_endpoint_buffer_control_set_value32 is only to set AVAILABLE
+        __asm volatile (
+            "b 1f\n"
+            "1: b 1f\n"
+            "1: b 1f\n"
+            "1: b 1f\n"
+            "1: b 1f\n"
+            "1: b 1f\n"
+            "1:\n"
+            : : : "memory");
+        // Make sure local ep state matches peripheral
+        hw_endpoint_reset_transfer(ep);
+    }
+    if (rp2040_chip_version() >= 2) {
+        usb_hw_clear->abort = 0x3;
+        usb_hw_clear->abort_done = 0x3;
     }
 }
 
-- 
cgit v1.3.1


From 4ed02ae5f97b57bd442521234b81a381c507d3a1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Mar 2024 17:34:14 +0700
Subject: reformat code hid_host.c

- fix ceedling with ruby 3.1
- allow overwrite CMAKE_C_COMPILER/CMAKE_CXX_COMPILER from command line
---
 .../build_system/cmake/toolchain/arm_gcc.cmake     |  12 +-
 src/class/hid/hid_host.c                           | 519 +++++++++------------
 test/unit-test/project.yml                         |  13 +-
 3 files changed, 231 insertions(+), 313 deletions(-)

(limited to 'src')

diff --git a/examples/build_system/cmake/toolchain/arm_gcc.cmake b/examples/build_system/cmake/toolchain/arm_gcc.cmake
index 7680d75ab..d3fd5b557 100644
--- a/examples/build_system/cmake/toolchain/arm_gcc.cmake
+++ b/examples/build_system/cmake/toolchain/arm_gcc.cmake
@@ -1,8 +1,14 @@
 set(CMAKE_SYSTEM_NAME Generic)
 
-set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
-set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
-set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc")
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
+endif ()
+
+if (NOT DEFINED CMAKE_CXX_COMPILER)
+  set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
+endif ()
+
+set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
 
 set(CMAKE_SIZE "arm-none-eabi-size" CACHE FILEPATH "")
 set(CMAKE_OBJCOPY "arm-none-eabi-objcopy" CACHE FILEPATH "")
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 709fa3dd8..21aee531a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -39,12 +39,11 @@
 #endif
 
 #define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_HID_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
-typedef struct
-{
+typedef struct {
   uint8_t daddr;
 
   uint8_t itf_num;
@@ -55,7 +54,7 @@ typedef struct
   uint8_t itf_protocol;   // None, Keyboard, Mouse
   uint8_t protocol_mode;  // Boot (0) or Report protocol (1)
 
-  uint8_t  report_desc_type;
+  uint8_t report_desc_type;
   uint16_t report_desc_len;
 
   uint16_t epin_size;
@@ -73,79 +72,57 @@ tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
 //--------------------------------------------------------------------+
 // Helper
 //--------------------------------------------------------------------+
-
-TU_ATTR_ALWAYS_INLINE static inline
-hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx)
-{
+TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx) {
   TU_ASSERT(daddr > 0 && idx < CFG_TUH_HID, NULL);
   hidh_interface_t* p_hid = &_hidh_itf[idx];
   return (p_hid->daddr == daddr) ? p_hid : NULL;
 }
 
 // Get instance ID by endpoint address
-static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr)
-{
-  for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ )
-  {
-    hidh_interface_t const * p_hid = &_hidh_itf[idx];
-
-    if ( p_hid->daddr == daddr &&
-         (p_hid->ep_in == ep_addr || p_hid->ep_out == ep_addr) )
-    {
+static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr) {
+  for (uint8_t idx = 0; idx < CFG_TUH_HID; idx++) {
+    hidh_interface_t const* p_hid = &_hidh_itf[idx];
+    if (p_hid->daddr == daddr &&
+        (p_hid->ep_in == ep_addr || p_hid->ep_out == ep_addr)) {
       return idx;
     }
   }
-
   return TUSB_INDEX_INVALID_8;
 }
 
-static hidh_interface_t* find_new_itf(void)
-{
-  for(uint8_t i=0; i<CFG_TUH_HID; i++)
-  {
+static hidh_interface_t* find_new_itf(void) {
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
     if (_hidh_itf[i].daddr == 0) return &_hidh_itf[i];
   }
-
   return NULL;
 }
 
 //--------------------------------------------------------------------+
 // Interface API
 //--------------------------------------------------------------------+
-
-uint8_t tuh_hid_itf_get_count(uint8_t daddr)
-{
+uint8_t tuh_hid_itf_get_count(uint8_t daddr) {
   uint8_t count = 0;
-
-  for(uint8_t i=0; i<CFG_TUH_HID; i++)
-  {
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
     if (_hidh_itf[i].daddr == daddr) count++;
   }
-
   return count;
 }
 
-uint8_t tuh_hid_itf_get_total_count(void)
-{
+uint8_t tuh_hid_itf_get_total_count(void) {
   uint8_t count = 0;
-
-  for(uint8_t i=0; i<CFG_TUH_HID; i++)
-  {
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
     if (_hidh_itf[i].daddr != 0) count++;
   }
-
   return count;
 }
 
-bool tuh_hid_mounted(uint8_t daddr, uint8_t idx)
-{
+bool tuh_hid_mounted(uint8_t daddr, uint8_t idx) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid);
   return p_hid->mounted;
 }
 
-bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info)
-{
+bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid && info);
 
@@ -153,34 +130,30 @@ bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info)
 
   // re-construct descriptor
   tusb_desc_interface_t* desc = &info->desc;
-  desc->bLength            = sizeof(tusb_desc_interface_t);
-  desc->bDescriptorType    = TUSB_DESC_INTERFACE;
+  desc->bLength = sizeof(tusb_desc_interface_t);
+  desc->bDescriptorType = TUSB_DESC_INTERFACE;
 
-  desc->bInterfaceNumber   = p_hid->itf_num;
-  desc->bAlternateSetting  = 0;
-  desc->bNumEndpoints      = (uint8_t) ((p_hid->ep_in ? 1u : 0u) + (p_hid->ep_out ? 1u : 0u));
-  desc->bInterfaceClass    = TUSB_CLASS_HID;
+  desc->bInterfaceNumber = p_hid->itf_num;
+  desc->bAlternateSetting = 0;
+  desc->bNumEndpoints = (uint8_t) ((p_hid->ep_in ? 1u : 0u) + (p_hid->ep_out ? 1u : 0u));
+  desc->bInterfaceClass = TUSB_CLASS_HID;
   desc->bInterfaceSubClass = (p_hid->itf_protocol ? HID_SUBCLASS_BOOT : HID_SUBCLASS_NONE);
   desc->bInterfaceProtocol = p_hid->itf_protocol;
-  desc->iInterface         = 0; // not used yet
+  desc->iInterface = 0; // not used yet
 
   return true;
 }
 
-uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num)
-{
-  for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ )
-  {
-    hidh_interface_t const * p_hid = &_hidh_itf[idx];
-
-    if ( p_hid->daddr == daddr && p_hid->itf_num == itf_num) return idx;
+uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num) {
+  for (uint8_t idx = 0; idx < CFG_TUH_HID; idx++) {
+    hidh_interface_t const* p_hid = &_hidh_itf[idx];
+    if (p_hid->daddr == daddr && p_hid->itf_num == itf_num) return idx;
   }
 
   return TUSB_INDEX_INVALID_8;
 }
 
-uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx)
-{
+uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   return p_hid ? p_hid->itf_protocol : 0;
 }
@@ -188,29 +161,24 @@ uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx)
 //--------------------------------------------------------------------+
 // Control Endpoint API
 //--------------------------------------------------------------------+
-
-uint8_t tuh_hid_get_protocol(uint8_t daddr, uint8_t idx)
-{
+uint8_t tuh_hid_get_protocol(uint8_t daddr, uint8_t idx) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   return p_hid ? p_hid->protocol_mode : 0;
 }
 
-static void set_protocol_complete(tuh_xfer_t* xfer)
-{
+static void set_protocol_complete(tuh_xfer_t* xfer) {
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const daddr   = xfer->daddr;
-  uint8_t const idx     = tuh_hid_itf_get_index(daddr, itf_num);
+  uint8_t const daddr = xfer->daddr;
+  uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num);
 
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
-  TU_VERIFY(p_hid, );
+  TU_VERIFY(p_hid,);
 
-  if (XFER_RESULT_SUCCESS == xfer->result)
-  {
+  if (XFER_RESULT_SUCCESS == xfer->result) {
     p_hid->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue);
   }
 
-  if (tuh_hid_set_protocol_complete_cb)
-  {
+  if (tuh_hid_set_protocol_complete_cb) {
     tuh_hid_set_protocol_complete_cb(daddr, idx, p_hid->protocol_mode);
   }
 }
@@ -219,123 +187,109 @@ void tuh_hid_set_default_protocol(uint8_t protocol) {
   _hidh_default_protocol = protocol;
 }
 
-static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol,
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol);
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
-    .wValue   = protocol,
-    .wIndex   = itf_num,
-    .wLength  = 0
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
+      .wValue   = protocol,
+      .wIndex   = itf_num,
+      .wLength  = 0
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
 }
 
-bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol)
-{
+bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid && p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE);
 
   return _hidh_set_protocol(daddr, p_hid->itf_num, protocol, set_protocol_complete, 0);
 }
 
-static void set_report_complete(tuh_xfer_t* xfer)
-{
+static void set_report_complete(tuh_xfer_t* xfer) {
   TU_LOG_DRV("HID Set Report complete\r\n");
 
-  if (tuh_hid_set_report_complete_cb)
-  {
+  if (tuh_hid_set_report_complete_cb) {
     uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-    uint8_t const idx     = tuh_hid_itf_get_index(xfer->daddr, itf_num);
+    uint8_t const idx = tuh_hid_itf_get_index(xfer->daddr, itf_num);
 
     uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
-    uint8_t const report_id   = tu_u16_low(xfer->setup->wValue);
+    uint8_t const report_id = tu_u16_low(xfer->setup->wValue);
 
     tuh_hid_set_report_complete_cb(xfer->daddr, idx, report_id, report_type,
                                    (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
   }
 }
 
-bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len)
-{
+bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid);
-
   TU_LOG_DRV("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = HID_REQ_CONTROL_SET_REPORT,
-    .wValue   = tu_htole16(tu_u16(report_type, report_id)),
-    .wIndex   = tu_htole16((uint16_t)p_hid->itf_num),
-    .wLength  = len
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_REPORT,
+      .wValue   = tu_htole16(tu_u16(report_type, report_id)),
+      .wIndex   = tu_htole16((uint16_t) p_hid->itf_num),
+      .wLength  = len
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = report,
-    .complete_cb = set_report_complete,
-    .user_data   = 0
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = report,
+      .complete_cb = set_report_complete,
+      .user_data   = 0
   };
 
   return tuh_control_xfer(&xfer);
 }
 
-static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate,
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   // SET IDLE request, device can stall if not support this request
   TU_LOG_DRV("HID Set Idle \r\n");
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = HID_REQ_CONTROL_SET_IDLE,
-    .wValue   = tu_htole16(idle_rate),
-    .wIndex   = tu_htole16((uint16_t)itf_num),
-    .wLength  = 0
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_IDLE,
+      .wValue   = tu_htole16(idle_rate),
+      .wIndex   = tu_htole16((uint16_t) itf_num),
+      .wLength  = 0
   };
 
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
@@ -346,24 +300,20 @@ static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, t
 //--------------------------------------------------------------------+
 
 // Check if HID interface is ready to receive report
-bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx)
-{
+bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx) {
   hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
   TU_VERIFY(p_hid);
-
   return !usbh_edpt_busy(dev_addr, p_hid->ep_in);
 }
 
-bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx)
-{
+bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid);
 
   // claim endpoint
-  TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_in) );
+  TU_VERIFY(usbh_edpt_claim(daddr, p_hid->ep_in));
 
-  if ( !usbh_edpt_xfer(daddr, p_hid->ep_in, p_hid->epin_buf, p_hid->epin_size) )
-  {
+  if (!usbh_edpt_xfer(daddr, p_hid->ep_in, p_hid->epin_buf, p_hid->epin_size)) {
     usbh_edpt_release(daddr, p_hid->ep_in);
     return false;
   }
@@ -371,43 +321,34 @@ bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx)
   return true;
 }
 
-bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx)
-{
+bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) {
   hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
   TU_VERIFY(p_hid);
-
   return !usbh_edpt_busy(dev_addr, p_hid->ep_out);
 }
 
-bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len)
-{
+bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len) {
   TU_LOG_DRV("HID Send Report %d\r\n", report_id);
 
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid);
 
-  if (p_hid->ep_out == 0)
-  {
+  if (p_hid->ep_out == 0) {
     // This HID does not have an out endpoint (other than control)
     return false;
-  }
-  else if (len > CFG_TUH_HID_EPOUT_BUFSIZE ||
-           (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1)))
-  {
+  } else if (len > CFG_TUH_HID_EPOUT_BUFSIZE ||
+             (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1))) {
     // ep_out buffer is not large enough to hold contents
     return false;
   }
 
   // claim endpoint
-  TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_out) );
+  TU_VERIFY(usbh_edpt_claim(daddr, p_hid->ep_out));
 
-  if (report_id == 0)
-  {
+  if (report_id == 0) {
     // No report ID in transmission
     memcpy(&p_hid->epout_buf[0], report, len);
-  }
-  else
-  {
+  } else {
     p_hid->epout_buf[0] = report_id;
     memcpy(&p_hid->epout_buf[1], report, len);
     ++len; // 1 more byte for report_id
@@ -415,8 +356,7 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo
 
   TU_LOG3_MEM(p_hid->epout_buf, len, 2);
 
-  if ( !usbh_edpt_xfer(daddr, p_hid->ep_out, p_hid->epout_buf, len) )
-  {
+  if (!usbh_edpt_xfer(daddr, p_hid->ep_out, p_hid->epout_buf, len)) {
     usbh_edpt_release(daddr, p_hid->ep_out);
     return false;
   }
@@ -427,13 +367,11 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo
 //--------------------------------------------------------------------+
 // USBH API
 //--------------------------------------------------------------------+
-void hidh_init(void)
-{
+void hidh_init(void) {
   tu_memclr(_hidh_itf, sizeof(_hidh_itf));
 }
 
-bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
 
   uint8_t const dir = tu_edpt_dir(ep_addr);
@@ -442,28 +380,25 @@ bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid);
 
-  if ( dir == TUSB_DIR_IN )
-  {
+  if (dir == TUSB_DIR_IN) {
     TU_LOG_DRV("  Get Report callback (%u, %u)\r\n", daddr, idx);
     TU_LOG3_MEM(p_hid->epin_buf, xferred_bytes, 2);
     tuh_hid_report_received_cb(daddr, idx, p_hid->epin_buf, (uint16_t) xferred_bytes);
-  }else
-  {
-    if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(daddr, idx, p_hid->epout_buf, (uint16_t) xferred_bytes);
+  } else {
+    if (tuh_hid_report_sent_cb) {
+      tuh_hid_report_sent_cb(daddr, idx, p_hid->epout_buf, (uint16_t) xferred_bytes);
+    }
   }
 
   return true;
 }
 
-void hidh_close(uint8_t daddr)
-{
-  for(uint8_t i=0; i<CFG_TUH_HID; i++)
-  {
+void hidh_close(uint8_t daddr) {
+  for (uint8_t i = 0; i < CFG_TUH_HID; i++) {
     hidh_interface_t* p_hid = &_hidh_itf[i];
-    if (p_hid->daddr == daddr)
-    {
+    if (p_hid->daddr == daddr) {
       TU_LOG_DRV("  HIDh close addr = %u index = %u\r\n", daddr, i);
-      if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
+      if (tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
       p_hid->daddr = 0;
       p_hid->mounted = false;
     }
@@ -474,25 +409,22 @@ void hidh_close(uint8_t daddr)
 // Enumeration
 //--------------------------------------------------------------------+
 
-bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
-{
+bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) {
   (void) rhport;
   (void) max_len;
 
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
-
   TU_LOG_DRV("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber);
 
   // len = interface + hid + n*endpoints
   uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
                                        desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(max_len >= drv_len);
-
-  uint8_t const *p_desc = (uint8_t const *) desc_itf;
+  uint8_t const* p_desc = (uint8_t const*) desc_itf;
 
   //------------- HID descriptor -------------//
   p_desc = tu_desc_next(p_desc);
-  tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
+  tusb_hid_descriptor_hid_t const* desc_hid = (tusb_hid_descriptor_hid_t const*) p_desc;
   TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType);
 
   hidh_interface_t* p_hid = find_new_itf();
@@ -501,38 +433,33 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_
 
   //------------- Endpoint Descriptors -------------//
   p_desc = tu_desc_next(p_desc);
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+  tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc;
 
-  for(int i = 0; i < desc_itf->bNumEndpoints; i++)
-  {
+  for (int i = 0; i < desc_itf->bNumEndpoints; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
-    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
+    TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
 
-    if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
-    {
-      p_hid->ep_in     = desc_ep->bEndpointAddress;
+    if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) {
+      p_hid->ep_in = desc_ep->bEndpointAddress;
       p_hid->epin_size = tu_edpt_packet_size(desc_ep);
-    }
-    else
-    {
-      p_hid->ep_out     = desc_ep->bEndpointAddress;
+    } else {
+      p_hid->ep_out = desc_ep->bEndpointAddress;
       p_hid->epout_size = tu_edpt_packet_size(desc_ep);
     }
 
     p_desc = tu_desc_next(p_desc);
-    desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    desc_ep = (tusb_desc_endpoint_t const*) p_desc;
   }
 
-  p_hid->itf_num   = desc_itf->bInterfaceNumber;
+  p_hid->itf_num = desc_itf->bInterfaceNumber;
 
   // Assume bNumDescriptors = 1
   p_hid->report_desc_type = desc_hid->bReportType;
-  p_hid->report_desc_len  = tu_unaligned_read16(&desc_hid->wReportLength);
+  p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength);
 
   // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config
   p_hid->protocol_mode = _hidh_default_protocol;
-  if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass )
-  {
+  if (HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass) {
     p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
   }
 
@@ -553,15 +480,14 @@ enum {
 static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len);
 static void process_set_config(tuh_xfer_t* xfer);
 
-bool hidh_set_config(uint8_t daddr, uint8_t itf_num)
-{
+bool hidh_set_config(uint8_t daddr, uint8_t itf_num) {
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
   tuh_xfer_t xfer;
-  xfer.daddr     = daddr;
-  xfer.result    = XFER_RESULT_SUCCESS;
-  xfer.setup     = &request;
+  xfer.daddr = daddr;
+  xfer.result = XFER_RESULT_SUCCESS;
+  xfer.setup = &request;
   xfer.user_data = CONFG_SET_IDLE;
 
   // fake request to kick-off the set config process
@@ -570,71 +496,67 @@ bool hidh_set_config(uint8_t daddr, uint8_t itf_num)
   return true;
 }
 
-static void process_set_config(tuh_xfer_t* xfer)
-{
+static void process_set_config(tuh_xfer_t* xfer) {
   // Stall is a valid response for SET_IDLE, sometime SET_PROTOCOL as well
   // therefore we could ignore its result
-  if ( !(xfer->setup->bRequest == HID_REQ_CONTROL_SET_IDLE ||
-         xfer->setup->bRequest == HID_REQ_CONTROL_SET_PROTOCOL) )
-  {
-    TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
+  if (!(xfer->setup->bRequest == HID_REQ_CONTROL_SET_IDLE ||
+        xfer->setup->bRequest == HID_REQ_CONTROL_SET_PROTOCOL)) {
+    TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS,);
   }
 
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const daddr   = xfer->daddr;
+  uint8_t const daddr = xfer->daddr;
 
-  uint8_t const idx       = tuh_hid_itf_get_index(daddr, itf_num);
+  uint8_t const idx = tuh_hid_itf_get_index(daddr, itf_num);
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
-  TU_VERIFY(p_hid, );
+  TU_VERIFY(p_hid,);
 
-  switch(state)
-  {
-    case CONFG_SET_IDLE:
-    {
+  switch (state) {
+    case CONFG_SET_IDLE: {
       // Idle rate = 0 mean only report when there is changes
       const uint16_t idle_rate = 0;
-      const uintptr_t next_state = (p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
+      const uintptr_t next_state = (p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE)
+                                   ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
       _hidh_set_idle(daddr, itf_num, idle_rate, process_set_config, next_state);
+      break;
     }
-    break;
 
     case CONFIG_SET_PROTOCOL:
       _hidh_set_protocol(daddr, p_hid->itf_num, _hidh_default_protocol, process_set_config, CONFIG_GET_REPORT_DESC);
-    break;
+      break;
 
     case CONFIG_GET_REPORT_DESC:
       // Get Report Descriptor if possible
       // using usbh enumeration buffer since report descriptor can be very long
-      if( p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
-      {
+      if (p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE) {
         TU_LOG_DRV("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len);
 
         // Driver is mounted without report descriptor
         config_driver_mount_complete(daddr, idx, NULL, 0);
-      }else
-      {
-        tuh_descriptor_get_hid_report(daddr, itf_num, p_hid->report_desc_type, 0, usbh_get_enum_buf(), p_hid->report_desc_len, process_set_config, CONFIG_COMPLETE);
+      } else {
+        tuh_descriptor_get_hid_report(daddr, itf_num, p_hid->report_desc_type, 0,
+                                      usbh_get_enum_buf(), p_hid->report_desc_len,
+                                      process_set_config, CONFIG_COMPLETE);
       }
       break;
 
-    case CONFIG_COMPLETE:
-    {
+    case CONFIG_COMPLETE: {
       uint8_t const* desc_report = usbh_get_enum_buf();
-      uint16_t const desc_len    = tu_le16toh(xfer->setup->wLength);
+      uint16_t const desc_len = tu_le16toh(xfer->setup->wLength);
 
       config_driver_mount_complete(daddr, idx, desc_report, desc_len);
+      break;
     }
-    break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
-static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len)
-{
+static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len) {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
-  TU_VERIFY(p_hid, );
+  TU_VERIFY(p_hid,);
   p_hid->mounted = true;
 
   // enumeration is complete
@@ -648,21 +570,19 @@ static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t con
 // Report Descriptor Parser
 //--------------------------------------------------------------------+
 
-uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len)
-{
+uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t arr_count,
+                                        uint8_t const* desc_report, uint16_t desc_len) {
   // Report Item 6.2.2.2 USB HID 1.11
-  union TU_ATTR_PACKED
-  {
+  union TU_ATTR_PACKED {
     uint8_t byte;
-    struct TU_ATTR_PACKED
-    {
-        uint8_t size : 2;
-        uint8_t type : 2;
-        uint8_t tag  : 4;
+    struct TU_ATTR_PACKED {
+      uint8_t size : 2;
+      uint8_t type : 2;
+      uint8_t tag : 4;
     };
   } header;
 
-  tu_memclr(report_info_arr, arr_count*sizeof(tuh_hid_report_info_t));
+  tu_memclr(report_info_arr, arr_count * sizeof(tuh_hid_report_info_t));
 
   uint8_t report_num = 0;
   tuh_hid_report_info_t* info = report_info_arr;
@@ -672,114 +592,105 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr,
 //  uint8_t ri_report_size = 0;
 
   uint8_t ri_collection_depth = 0;
-
-  while(desc_len && report_num < arr_count)
-  {
+  while (desc_len && report_num < arr_count) {
     header.byte = *desc_report++;
     desc_len--;
 
-    uint8_t const tag  = header.tag;
+    uint8_t const tag = header.tag;
     uint8_t const type = header.type;
     uint8_t const size = header.size;
 
     uint8_t const data8 = desc_report[0];
 
     TU_LOG(3, "tag = %d, type = %d, size = %d, data = ", tag, type, size);
-    for(uint32_t i=0; i<size; i++) TU_LOG(3, "%02X ", desc_report[i]);
+    for (uint32_t i = 0; i < size; i++) TU_LOG(3, "%02X ", desc_report[i]);
     TU_LOG(3, "\r\n");
 
-    switch(type)
-    {
+    switch (type) {
       case RI_TYPE_MAIN:
-        switch (tag)
-        {
+        switch (tag) {
           case RI_MAIN_INPUT: break;
           case RI_MAIN_OUTPUT: break;
           case RI_MAIN_FEATURE: break;
-
           case RI_MAIN_COLLECTION:
             ri_collection_depth++;
-          break;
+            break;
 
           case RI_MAIN_COLLECTION_END:
             ri_collection_depth--;
-            if (ri_collection_depth == 0)
-            {
+            if (ri_collection_depth == 0) {
               info++;
               report_num++;
             }
-          break;
+            break;
 
-          default: break;
+          default:break;
         }
-      break;
+        break;
 
       case RI_TYPE_GLOBAL:
-        switch(tag)
-        {
+        switch (tag) {
           case RI_GLOBAL_USAGE_PAGE:
             // only take in account the "usage page" before REPORT ID
-            if ( ri_collection_depth == 0 ) memcpy(&info->usage_page, desc_report, size);
-          break;
+            if (ri_collection_depth == 0) memcpy(&info->usage_page, desc_report, size);
+            break;
 
-          case RI_GLOBAL_LOGICAL_MIN   : break;
-          case RI_GLOBAL_LOGICAL_MAX   : break;
-          case RI_GLOBAL_PHYSICAL_MIN  : break;
-          case RI_GLOBAL_PHYSICAL_MAX  : break;
+          case RI_GLOBAL_LOGICAL_MIN: break;
+          case RI_GLOBAL_LOGICAL_MAX: break;
+          case RI_GLOBAL_PHYSICAL_MIN: break;
+          case RI_GLOBAL_PHYSICAL_MAX: break;
 
           case RI_GLOBAL_REPORT_ID:
             info->report_id = data8;
-          break;
+            break;
 
           case RI_GLOBAL_REPORT_SIZE:
 //            ri_report_size = data8;
-          break;
+            break;
 
           case RI_GLOBAL_REPORT_COUNT:
 //            ri_report_count = data8;
-          break;
+            break;
 
-          case RI_GLOBAL_UNIT_EXPONENT : break;
-          case RI_GLOBAL_UNIT          : break;
-          case RI_GLOBAL_PUSH          : break;
-          case RI_GLOBAL_POP           : break;
+          case RI_GLOBAL_UNIT_EXPONENT: break;
+          case RI_GLOBAL_UNIT: break;
+          case RI_GLOBAL_PUSH: break;
+          case RI_GLOBAL_POP: break;
 
           default: break;
         }
-      break;
+        break;
 
       case RI_TYPE_LOCAL:
-        switch(tag)
-        {
+        switch (tag) {
           case RI_LOCAL_USAGE:
             // only take in account the "usage" before starting REPORT ID
-            if ( ri_collection_depth == 0 ) info->usage = data8;
-          break;
-
-          case RI_LOCAL_USAGE_MIN        : break;
-          case RI_LOCAL_USAGE_MAX        : break;
-          case RI_LOCAL_DESIGNATOR_INDEX : break;
-          case RI_LOCAL_DESIGNATOR_MIN   : break;
-          case RI_LOCAL_DESIGNATOR_MAX   : break;
-          case RI_LOCAL_STRING_INDEX     : break;
-          case RI_LOCAL_STRING_MIN       : break;
-          case RI_LOCAL_STRING_MAX       : break;
-          case RI_LOCAL_DELIMITER        : break;
+            if (ri_collection_depth == 0) info->usage = data8;
+            break;
+
+          case RI_LOCAL_USAGE_MIN: break;
+          case RI_LOCAL_USAGE_MAX: break;
+          case RI_LOCAL_DESIGNATOR_INDEX: break;
+          case RI_LOCAL_DESIGNATOR_MIN: break;
+          case RI_LOCAL_DESIGNATOR_MAX: break;
+          case RI_LOCAL_STRING_INDEX: break;
+          case RI_LOCAL_STRING_MIN: break;
+          case RI_LOCAL_STRING_MAX: break;
+          case RI_LOCAL_DELIMITER: break;
           default: break;
         }
-      break;
+        break;
 
-      // error
+        // error
       default: break;
     }
 
     desc_report += size;
-    desc_len    -= size;
+    desc_len -= size;
   }
 
-  for ( uint8_t i = 0; i < report_num; i++ )
-  {
-    info = report_info_arr+i;
+  for (uint8_t i = 0; i < report_num; i++) {
+    info = report_info_arr + i;
     TU_LOG_DRV("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage);
   }
 
diff --git a/test/unit-test/project.yml b/test/unit-test/project.yml
index 562dbca09..82528f68c 100644
--- a/test/unit-test/project.yml
+++ b/test/unit-test/project.yml
@@ -44,12 +44,13 @@
   # in order to add common defines:
   #  1) remove the trailing [] from the :common: section
   #  2) add entries to the :common: section (e.g. :test: has TEST defined)
-  :common: &common_defines
-    - _UNITY_TEST_
+  :common: &common_defines []
   :test:
-    - *common_defines
+    - _UNITY_TEST_
+    #- *common_defines
   :test_preprocess:
-    - *common_defines
+    - _UNITY_TEST_
+    #- *common_defines
 
 :cmock:
   :mock_prefix: mock_
@@ -106,9 +107,9 @@
   :flag: "${1}"  # or "-L ${1}" for example
   :common: &common_libraries []
   :test:
-    - *common_libraries
+    #- *common_libraries
   :release:
-    - *common_libraries
+    #- *common_libraries
 
 :plugins:
   :load_paths:
-- 
cgit v1.3.1


From 4f5d80d3976fb0dc5cd190b1768225aacf34211b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Mar 2024 17:40:38 +0700
Subject: add tuh_hid_receive_abort() API

---
 src/class/hid/hid_host.c |  5 +++++
 src/class/hid/hid_host.h | 28 ++++++++++++++++------------
 2 files changed, 21 insertions(+), 12 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 21aee531a..7330fa237 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -320,6 +320,11 @@ bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) {
 
   return true;
 }
+bool tuh_hid_receive_abort(uint8_t dev_addr, uint8_t idx) {
+  hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
+  TU_VERIFY(p_hid);
+  return tuh_edpt_abort_xfer(dev_addr, p_hid->ep_in);
+}
 
 bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx) {
   hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 238b7c627..17f4e27c0 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -30,7 +30,7 @@
 #include "hid.h"
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
@@ -47,10 +47,9 @@
 #endif
 
 
-typedef struct
-{
-  uint8_t  report_id;
-  uint8_t  usage;
+typedef struct {
+  uint8_t report_id;
+  uint8_t usage;
   uint16_t usage_page;
 
   // TODO still use the endpoint size for now
@@ -86,7 +85,8 @@ bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx);
 
 // Parse report descriptor into array of report_info struct and return number of reports.
 // For complicated report, application should write its own parser.
-uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) TU_ATTR_UNUSED;
+TU_ATTR_UNUSED uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count,
+                                                       uint8_t const* desc_report, uint16_t desc_len);
 
 //--------------------------------------------------------------------+
 // Control Endpoint API
@@ -107,7 +107,8 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol);
 
 // Set Report using control endpoint
 // report_type is either Input, Output or Feature, (value from hid_report_type_t)
-bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
+bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type,
+                        void* report, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Interrupt Endpoint API
@@ -121,6 +122,9 @@ bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx);
 // - false if failed to queue the transfer e.g endpoint is busy
 bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t idx);
 
+// Abort receiving report on Interrupt Endpoint
+bool tuh_hid_receive_abort(uint8_t dev_addr, uint8_t idx);
+
 // Check if HID interface is ready to send report
 bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx);
 
@@ -159,11 +163,11 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void hidh_init       (void);
-bool hidh_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
-bool hidh_set_config (uint8_t dev_addr, uint8_t itf_num);
-bool hidh_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-void hidh_close      (uint8_t dev_addr);
+void hidh_init(void);
+bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len);
+bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num);
+bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+void hidh_close(uint8_t dev_addr);
 
 #ifdef __cplusplus
 }
-- 
cgit v1.3.1


From ff76eca311f4026c1a9b36e9ad37bbb53b39cf5d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 4 Mar 2024 16:15:26 +0700
Subject: code reformat

---
 src/host/usbh.c | 563 ++++++++++++++++++++++++--------------------------------
 src/tusb.c      |  12 +-
 2 files changed, 245 insertions(+), 330 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index f56290a0c..407d97234 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -420,20 +420,18 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
-  if ( !tuh_inited() ) return;
+  if (!tuh_inited()) return;
 
   // Loop until there is no more events in the queue
-  while (1)
-  {
+  while (1) {
     hcd_event_t event;
-    if ( !osal_queue_receive(_usbh_q, &event, timeout_ms) ) return;
+    if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return;
 
-    switch (event.event_id)
-    {
+    switch (event.event_id) {
       case HCD_EVENT_DEVICE_ATTACH:
         // due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one.
         // TODO better to have an separated queue for newly attached devices
-        if ( _dev0.enumerating ) {
+        if (_dev0.enumerating) {
           TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
 
           bool is_empty = osal_queue_empty(_usbh_q);
@@ -443,12 +441,12 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
             // Exit if this is the only event in the queue, otherwise we may loop forever
             return;
           }
-        }else {
+        } else {
           TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
           _dev0.enumerating = 1;
           enum_new_device(&event);
         }
-      break;
+        break;
 
       case HCD_EVENT_DEVICE_REMOVE:
         TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
@@ -456,37 +454,34 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
 
         #if CFG_TUH_HUB
         // TODO remove
-        if ( event.connection.hub_addr != 0 && event.connection.hub_port != 0) {
+        if (event.connection.hub_addr != 0 && event.connection.hub_port != 0) {
           // done with hub, waiting for next data on status pipe
-          (void) hub_edpt_status_xfer( event.connection.hub_addr );
+          (void) hub_edpt_status_xfer(event.connection.hub_addr);
         }
         #endif
-      break;
+        break;
 
-      case HCD_EVENT_XFER_COMPLETE:
-      {
+      case HCD_EVENT_XFER_COMPLETE: {
         uint8_t const ep_addr = event.xfer_complete.ep_addr;
-        uint8_t const epnum   = tu_edpt_number(ep_addr);
-        uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
+        uint8_t const epnum = tu_edpt_number(ep_addr);
+        uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr);
 
-        TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len,
-                    tu_str_xfer_result[event.xfer_complete.result]);
+        TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, tu_str_xfer_result[event.xfer_complete.result]);
 
         if (event.dev_addr == 0) {
           // device 0 only has control endpoint
-          TU_ASSERT(epnum == 0, );
+          TU_ASSERT(epnum == 0,);
           usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
         } else {
           usbh_device_t* dev = get_device(event.dev_addr);
-          TU_VERIFY(dev && dev->connected, );
+          TU_VERIFY(dev && dev->connected,);
 
-          dev->ep_status[epnum][ep_dir].busy    = 0;
+          dev->ep_status[epnum][ep_dir].busy = 0;
           dev->ep_status[epnum][ep_dir].claimed = 0;
 
-          if ( 0 == epnum ) {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
-                                 event.xfer_complete.len);
-          }else {
+          if (0 == epnum) {
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
+          } else {
             // Prefer application callback over built-in one if available. This occurs when tuh_edpt_xfer() is used
             // with enabled driver e.g HID endpoint
             #if CFG_TUH_API_EDPT_XFER
@@ -503,35 +498,32 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
                   .complete_cb = complete_cb,
                   .user_data   = dev->ep_callback[epnum][ep_dir].user_data
               };
-
               complete_cb(&xfer);
             }else
             #endif
             {
               uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-              usbh_class_driver_t const * driver = get_driver(drv_id);
-              if ( driver )
-              {
+              usbh_class_driver_t const* driver = get_driver(drv_id);
+              if (driver) {
                 TU_LOG_USBH("%s xfer callback\r\n", driver->name);
                 driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
                                 event.xfer_complete.len);
-              }
-              else
-              {
+              } else {
                 // no driver/callback responsible for this transfer
                 TU_ASSERT(false,);
               }
             }
           }
         }
+        break;
       }
-      break;
 
       case USBH_EVENT_FUNC_CALL:
-        if ( event.func_call.func ) event.func_call.func(event.func_call.param);
-      break;
+        if (event.func_call.func) event.func_call.func(event.func_call.param);
+        break;
 
-      default: break;
+      default:
+        break;
     }
 
 #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
@@ -708,7 +700,6 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer) {
   uint8_t const ep_addr = xfer->ep_addr;
 
   TU_VERIFY(daddr && ep_addr);
-
   TU_VERIFY(usbh_edpt_claim(daddr, ep_addr));
 
   if (!usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen,
@@ -783,14 +774,13 @@ void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
 //--------------------------------------------------------------------+
 
 // Claim an endpoint for transfer
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr) {
   // Note: addr0 only use tuh_control_xfer
   usbh_device_t* dev = get_device(dev_addr);
   TU_ASSERT(dev && dev->connected);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   TU_VERIFY(tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex));
   TU_LOG_USBH("[%u] Claimed EP 0x%02x\r\n", dev_addr, ep_addr);
@@ -799,14 +789,13 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 }
 
 // Release an claimed endpoint due to failed transfer attempt
-bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr) {
   // Note: addr0 only use tuh_control_xfer
   usbh_device_t* dev = get_device(dev_addr);
   TU_VERIFY(dev && dev->connected);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   TU_VERIFY(tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex));
   TU_LOG_USBH("[%u] Released EP 0x%02x\r\n", dev_addr, ep_addr);
@@ -816,9 +805,8 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 
 // Submit an transfer
 // TODO call usbh_edpt_release if failed
-bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   (void) complete_cb;
   (void) user_data;
 
@@ -826,7 +814,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
   TU_VERIFY(dev);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
   TU_LOG_USBH("  Queue EP %02X with %u bytes ... \r\n", ep_addr, total_bytes);
@@ -843,14 +831,12 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
   dev->ep_callback[epnum][dir].user_data   = user_data;
 #endif
 
-  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
-  {
+  if (hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes)) {
     TU_LOG_USBH("OK\r\n");
     return true;
-  }else
-  {
+  } else {
     // HCD error, mark endpoint as ready to allow next transfer
-    ep_state->busy    = 0;
+    ep_state->busy = 0;
     ep_state->claimed = 0;
     TU_LOG1("Failed\r\n");
 //    TU_BREAKPOINT();
@@ -858,12 +844,9 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
   }
 }
 
-static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
-{
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size) {
   TU_LOG_USBH("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size);
-
-  tusb_desc_endpoint_t ep0_desc =
-  {
+  tusb_desc_endpoint_t ep0_desc = {
     .bLength          = sizeof(tusb_desc_endpoint_t),
     .bDescriptorType  = TUSB_DESC_ENDPOINT,
     .bEndpointAddress = 0,
@@ -875,10 +858,8 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
 }
 
-bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
-  TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) );
-
+bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) {
+  TU_ASSERT(tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)));
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep);
 }
 
@@ -887,7 +868,7 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) {
   TU_VERIFY(dev);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   return dev->ep_status[epnum][dir].busy;
 }
@@ -896,22 +877,18 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) {
 // HCD Event Handler
 //--------------------------------------------------------------------+
 
-void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
-{
+void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info) {
   usbh_device_t const* dev = get_device(dev_addr);
-
-  if (dev)
-  {
-    devtree_info->rhport   = dev->rhport;
+  if (dev) {
+    devtree_info->rhport = dev->rhport;
     devtree_info->hub_addr = dev->hub_addr;
     devtree_info->hub_port = dev->hub_port;
-    devtree_info->speed    = dev->speed;
-  }else
-  {
-    devtree_info->rhport   = _dev0.rhport;
+    devtree_info->speed = dev->speed;
+  } else {
+    devtree_info->rhport = _dev0.rhport;
     devtree_info->hub_addr = _dev0.hub_addr;
     devtree_info->hub_port = _dev0.hub_port;
-    devtree_info->speed    = _dev0.speed;
+    devtree_info->speed = _dev0.speed;
   }
 }
 
@@ -941,12 +918,9 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
 // generic helper to get a descriptor
 // if blocking, user_data is pointed to xfer_result
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                            tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
+                            tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_DEVICE,
       .type      = TUSB_REQ_TYPE_STANDARD,
       .direction = TUSB_DIR_IN
@@ -956,9 +930,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .wIndex   = tu_htole16(language_id),
     .wLength  = tu_htole16(len)
   };
-
-  tuh_xfer_t xfer =
-  {
+  tuh_xfer_t xfer = {
     .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
@@ -971,29 +943,25 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
 }
 
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
-                        tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                        tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return _get_descriptor(daddr, type, index, 0x0000, buffer, len, complete_cb, user_data);
 }
 
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   len = tu_min16(len, sizeof(tusb_desc_device_t));
   return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb, user_data);
 }
 
 bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_data);
 }
 
 //------------- String Descriptor -------------//
 
 bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_data);
 }
 
@@ -1008,8 +976,7 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id,
 
 // Get product string descriptor
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                       tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                                       tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_product);
   return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_data);
@@ -1017,8 +984,7 @@ bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void
 
 // Get serial string descriptor
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_serial);
   return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_data);
@@ -1027,95 +993,78 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void*
 // Get HID report descriptor
 // if blocking, user_data is pointed to xfer_result
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
-                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_USBH("HID Get Report Descriptor\r\n");
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = tu_htole16(TU_U16(desc_type, index)),
-    .wIndex   = tu_htole16((uint16_t) itf_num),
-    .wLength  = len
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_IN
+      },
+      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+      .wValue   = tu_htole16(TU_U16(desc_type, index)),
+      .wIndex   = tu_htole16((uint16_t) itf_num),
+      .wLength  = len
   };
-
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = buffer,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = buffer,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
 }
 
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
-                           tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_USBH("Set Configuration = %d\r\n", config_num);
-
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = TUSB_REQ_SET_CONFIGURATION,
-    .wValue   = tu_htole16(config_num),
-    .wIndex   = 0,
-    .wLength  = 0
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_CONFIGURATION,
+      .wValue   = tu_htole16(config_num),
+      .wIndex   = 0,
+      .wLength  = 0
   };
-
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
 }
 
 bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
-                       tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+                       tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_USBH("Set Interface %u Alternate %u\r\n", itf_num, itf_alt);
-
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = TUSB_REQ_SET_INTERFACE,
-    .wValue   = tu_htole16(itf_alt),
-    .wIndex   = tu_htole16(itf_num),
-    .wLength  = 0
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_INTERFACE,
+      .wValue   = tu_htole16(itf_alt),
+      .wIndex   = tu_htole16(itf_num),
+      .wLength  = 0
   };
-
-  tuh_xfer_t xfer =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = complete_cb,
+      .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
@@ -1174,9 +1123,7 @@ uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_i
 // Detaching
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE
-static inline bool is_hub_addr(uint8_t daddr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) {
   return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX);
 }
 
@@ -1201,8 +1148,7 @@ static inline bool is_hub_addr(uint8_t daddr)
 //}
 
 // a device unplugged from rhport:hub_addr:hub_port
-static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
-{
+static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
   // TODO mark as disconnected in ISR, also handle dev0
 
@@ -1217,8 +1163,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
   uint8_t nop_count = 0;
 #endif
 
-  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++)
-  {
+  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
     usbh_device_t *dev = &_usbh_devices[dev_id];
     uint8_t const daddr = dev_id + 1;
 
@@ -1325,165 +1270,160 @@ static void process_enumeration(tuh_xfer_t* xfer) {
   uint8_t const daddr = xfer->daddr;
   uintptr_t const state = xfer->user_data;
 
-  switch(state)
-  {
-#if CFG_TUH_HUB
+  switch (state) {
+    #if CFG_TUH_HUB
     //case ENUM_HUB_GET_STATUS_1: break;
 
-    case ENUM_HUB_CLEAR_RESET_1:
-    {
+    case ENUM_HUB_CLEAR_RESET_1: {
       hub_port_status_response_t port_status;
       memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
 
-      if ( !port_status.status.connection )
-      {
+      if (!port_status.status.connection) {
         // device unplugged while delaying, nothing else to do
         enum_full_complete();
         return;
       }
 
       _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
-                    (port_status.status.low_speed ) ? TUSB_SPEED_LOW  : TUSB_SPEED_FULL;
+                    (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
 
       // Acknowledge Port Reset Change
-      if (port_status.change.reset)
-      {
-        hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_ADDR0_DEVICE_DESC);
+      if (port_status.change.reset) {
+        hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port,
+                                    process_enumeration, ENUM_ADDR0_DEVICE_DESC);
       }
+      break;
     }
-    break;
 
     case ENUM_HUB_GET_STATUS_2:
       osal_task_delay(ENUM_RESET_DELAY);
-      TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2), );
-    break;
+      TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf,
+                                    process_enumeration, ENUM_HUB_CLEAR_RESET_2),);
+      break;
 
-    case ENUM_HUB_CLEAR_RESET_2:
-    {
+    case ENUM_HUB_CLEAR_RESET_2: {
       hub_port_status_response_t port_status;
       memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
 
       // Acknowledge Port Reset Change if Reset Successful
-      if (port_status.change.reset)
-      {
-        TU_ASSERT( hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_SET_ADDR), );
+      if (port_status.change.reset) {
+        TU_ASSERT(hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port,
+                                              process_enumeration, ENUM_SET_ADDR),);
       }
+      break;
     }
-    break;
-#endif
+    #endif
 
-    case ENUM_ADDR0_DEVICE_DESC:
-    {
+    case ENUM_ADDR0_DEVICE_DESC: {
       // TODO probably doesn't need to open/close each enumeration
       uint8_t const addr0 = 0;
-      TU_ASSERT( usbh_edpt_control_open(addr0, 8), );
+      TU_ASSERT(usbh_edpt_control_open(addr0, 8),);
 
       // Get first 8 bytes of device descriptor for Control Endpoint size
       TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR), );
+      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8,
+                                          process_enumeration, ENUM_SET_ADDR),);
+      break;
     }
-    break;
 
 #if 0
-    case ENUM_RESET_2:
-      // TODO not used by now, but may be needed for some devices !?
-      // Reset device again before Set Address
-      TU_LOG_USBH("Port reset2 \r\n");
-      if (_dev0.hub_addr == 0)
-      {
-        // connected directly to roothub
-        hcd_port_reset( _dev0.rhport );
-        osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                      // sof of controller may not running while resetting
-        hcd_port_reset_end(_dev0.rhport);
-        // TODO: fall through to SET ADDRESS, refactor later
-      }
-      #if CFG_TUH_HUB
-      else
-      {
-        // after RESET_DELAY the hub_port_reset() already complete
-        TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_HUB_GET_STATUS_2), );
-        break;
-      }
-      #endif
-      TU_ATTR_FALLTHROUGH;
+      case ENUM_RESET_2:
+        // TODO not used by now, but may be needed for some devices !?
+        // Reset device again before Set Address
+        TU_LOG_USBH("Port reset2 \r\n");
+        if (_dev0.hub_addr == 0) {
+          // connected directly to roothub
+          hcd_port_reset( _dev0.rhport );
+          osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
+                                        // sof of controller may not running while resetting
+          hcd_port_reset_end(_dev0.rhport);
+          // TODO: fall through to SET ADDRESS, refactor later
+        }
+#if CFG_TUH_HUB
+        else {
+          // after RESET_DELAY the hub_port_reset() already complete
+          TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port,
+                                    process_enumeration, ENUM_HUB_GET_STATUS_2), );
+          break;
+        }
+#endif
+        TU_ATTR_FALLTHROUGH;
 #endif
 
     case ENUM_SET_ADDR:
       enum_request_set_addr();
-    break;
+      break;
 
-    case ENUM_GET_DEVICE_DESC:
-    {
+    case ENUM_GET_DEVICE_DESC: {
       uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue);
 
       usbh_device_t* new_dev = get_device(new_addr);
-      TU_ASSERT(new_dev, );
+      TU_ASSERT(new_dev,);
       new_dev->addressed = 1;
 
       // Close device 0
       hcd_device_close(_dev0.rhport, 0);
 
       // open control pipe for new address
-      TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size), );
+      TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),);
 
       // Get full device descriptor
       TU_LOG_USBH("Get Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC), );
+      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t),
+                                          process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC),);
+      break;
     }
-    break;
 
-    case ENUM_GET_9BYTE_CONFIG_DESC:
-    {
-      tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+    case ENUM_GET_9BYTE_CONFIG_DESC: {
+      tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
       usbh_device_t* dev = get_device(daddr);
-      TU_ASSERT(dev, );
+      TU_ASSERT(dev,);
 
-      dev->vid            = desc_device->idVendor;
-      dev->pid            = desc_device->idProduct;
+      dev->vid = desc_device->idVendor;
+      dev->pid = desc_device->idProduct;
       dev->i_manufacturer = desc_device->iManufacturer;
-      dev->i_product      = desc_device->iProduct;
-      dev->i_serial       = desc_device->iSerialNumber;
+      dev->i_product = desc_device->iProduct;
+      dev->i_serial = desc_device->iSerialNumber;
 
-    //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
+      //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
 
       // Get 9-byte for total length
       uint8_t const config_idx = CONFIG_NUM - 1;
       TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), );
+      TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9,
+                                                 process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
+      break;
     }
-    break;
 
-    case ENUM_GET_FULL_CONFIG_DESC:
-    {
-      uint8_t const * desc_config = _usbh_ctrl_buf;
+    case ENUM_GET_FULL_CONFIG_DESC: {
+      uint8_t const* desc_config = _usbh_ctrl_buf;
 
       // Use offsetof to avoid pointer to the odd/misaligned address
-      uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
+      uint16_t const total_len = tu_le16toh(
+          tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)));
 
       // TODO not enough buffer to hold configuration descriptor
-      TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE, );
+      TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE,);
 
       // Get full configuration descriptor
       uint8_t const config_idx = CONFIG_NUM - 1;
       TU_LOG_USBH("Get Configuration[0] Descriptor\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), );
+      TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len,
+                                                 process_enumeration, ENUM_SET_CONFIG),);
+      break;
     }
-    break;
 
     case ENUM_SET_CONFIG:
       // Parse configuration & set up drivers
       // Driver open aren't allowed to make any usb transfer yet
-      TU_ASSERT( _parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf), );
-
-      TU_ASSERT( tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER), );
-    break;
+      TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),);
+      TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),);
+      break;
 
-    case ENUM_CONFIG_DRIVER:
-    {
+    case ENUM_CONFIG_DRIVER: {
       TU_LOG_USBH("Device configured\r\n");
       usbh_device_t* dev = get_device(daddr);
-      TU_ASSERT(dev, );
+      TU_ASSERT(dev,);
 
       dev->configured = 1;
 
@@ -1492,60 +1432,58 @@ static void process_enumeration(tuh_xfer_t* xfer) {
       // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
       // TODO use separated API instead of using TUSB_INDEX_INVALID_8
       usbh_driver_set_config_complete(daddr, TUSB_INDEX_INVALID_8);
+      break;
     }
-    break;
 
     default:
       // stop enumeration if unknown state
       enum_full_complete();
-    break;
+      break;
   }
 }
 
-static bool enum_new_device(hcd_event_t* event)
-{
-  _dev0.rhport   = event->rhport;
+static bool enum_new_device(hcd_event_t* event) {
+  _dev0.rhport = event->rhport;
   _dev0.hub_addr = event->connection.hub_addr;
   _dev0.hub_port = event->connection.hub_port;
 
-  if (_dev0.hub_addr == 0)
-  {
+  if (_dev0.hub_addr == 0) {
     // connected/disconnected directly with roothub
     hcd_port_reset(_dev0.rhport);
     osal_task_delay(ENUM_RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                        // sof of controller may not running while resetting
-    hcd_port_reset_end( _dev0.rhport);
+    // sof of controller may not running while resetting
+    hcd_port_reset_end(_dev0.rhport);
 
     // wait until device connection is stable TODO non blocking
     osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY);
 
     // device unplugged while delaying
-    if ( !hcd_port_connect_status(_dev0.rhport) ) {
+    if (!hcd_port_connect_status(_dev0.rhport)) {
       enum_full_complete();
       return true;
     }
 
-    _dev0.speed = hcd_port_speed_get(_dev0.rhport );
+    _dev0.speed = hcd_port_speed_get(_dev0.rhport);
     TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
     // fake transfer to kick-off the enumeration process
     tuh_xfer_t xfer;
-    xfer.daddr     = 0;
-    xfer.result    = XFER_RESULT_SUCCESS;
+    xfer.daddr = 0;
+    xfer.result = XFER_RESULT_SUCCESS;
     xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
     process_enumeration(&xfer);
   }
 #if CFG_TUH_HUB
-  else
-  {
+  else {
     // connected/disconnected via external hub
     // wait until device connection is stable TODO non blocking
     osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY);
 
     // ENUM_HUB_GET_STATUS
     //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) );
-    TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_1) );
+    TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf,
+                                  process_enumeration, ENUM_HUB_CLEAR_RESET_1));
   }
 #endif // hub
 
@@ -1571,58 +1509,48 @@ static uint8_t get_new_address(bool is_hub) {
   return 0; // invalid address
 }
 
-static bool enum_request_set_addr(void)
-{
-  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+static bool enum_request_set_addr(void) {
+  tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
 
   // Get new address
   uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
   TU_ASSERT(new_addr != 0);
-
   TU_LOG_USBH("Set Address = %d\r\n", new_addr);
 
   usbh_device_t* new_dev = get_device(new_addr);
-
-  new_dev->rhport    = _dev0.rhport;
-  new_dev->hub_addr  = _dev0.hub_addr;
-  new_dev->hub_port  = _dev0.hub_port;
-  new_dev->speed     = _dev0.speed;
+  new_dev->rhport = _dev0.rhport;
+  new_dev->hub_addr = _dev0.hub_addr;
+  new_dev->hub_port = _dev0.hub_port;
+  new_dev->speed = _dev0.speed;
   new_dev->connected = 1;
-  new_dev->ep0_size  = desc_device->bMaxPacketSize0;
-
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = TUSB_REQ_SET_ADDRESS,
-    .wValue   = tu_htole16(new_addr),
-    .wIndex   = 0,
-    .wLength  = 0
+  new_dev->ep0_size = desc_device->bMaxPacketSize0;
+
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_DEVICE,
+          .type      = TUSB_REQ_TYPE_STANDARD,
+          .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_ADDRESS,
+      .wValue   = tu_htole16(new_addr),
+      .wIndex   = 0,
+      .wLength  = 0
   };
-
-  tuh_xfer_t xfer =
-  {
-    .daddr       = 0, // dev0
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = process_enumeration,
-    .user_data   = ENUM_GET_DEVICE_DESC
+  tuh_xfer_t xfer = {
+      .daddr       = 0, // dev0
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = process_enumeration,
+      .user_data   = ENUM_GET_DEVICE_DESC
   };
 
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-
+  TU_ASSERT(tuh_control_xfer(&xfer));
   return true;
 }
 
-static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
-{
+static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) {
   usbh_device_t* dev = get_device(dev_addr);
-
   uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength);
   uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len;
   uint8_t const* p_desc   = tu_desc_next(desc_cfg);
@@ -1630,13 +1558,11 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
   TU_LOG_USBH("Parsing Configuration descriptor (wTotalLength = %u)\r\n", total_len);
 
   // parse each interfaces
-  while( p_desc < desc_end )
-  {
+  while( p_desc < desc_end ) {
     uint8_t assoc_itf_count = 1;
 
     // Class will always starts with Interface Association (if any) and then Interface descriptor
-    if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
-    {
+    if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) {
       tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
       assoc_itf_count = desc_iad->bInterfaceCount;
 
@@ -1656,8 +1582,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     if (1                              == assoc_itf_count              &&
         TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
         AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
-        AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol)
-    {
+        AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) {
       assoc_itf_count = 2;
     }
 #endif
@@ -1667,8 +1592,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     // manually force associated count = 2
     if (1                                        == assoc_itf_count              &&
         TUSB_CLASS_CDC                           == desc_itf->bInterfaceClass    &&
-        CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == desc_itf->bInterfaceSubClass)
-    {
+        CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == desc_itf->bInterfaceSubClass) {
       assoc_itf_count = 2;
     }
 #endif
@@ -1677,18 +1601,14 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
-    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
-    {
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
       usbh_class_driver_t const * driver = get_driver(drv_id);
-
-      if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
-      {
+      if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) {
         // open successfully
         TU_LOG_USBH("  %s opened\r\n", driver->name);
 
         // bind (associated) interfaces to found driver
-        for(uint8_t i=0; i<assoc_itf_count; i++)
-        {
+        for(uint8_t i=0; i<assoc_itf_count; i++) {
           uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
 
           // Interface number must not be used already
@@ -1702,8 +1622,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
         break; // exit driver find loop
       }
 
-      if ( drv_id == TOTAL_DRIVER_COUNT - 1 )
-      {
+      if ( drv_id == TOTAL_DRIVER_COUNT - 1 ) {
         TU_LOG_USBH("[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
                dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
       }
diff --git a/src/tusb.c b/src/tusb.c
index 3ef380c83..7c86f1ca5 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -112,8 +112,7 @@ uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t b
 // Endpoint Helper for both Host and Device stack
 //--------------------------------------------------------------------+
 
-bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
-{
+bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   (void) mutex;
 
   // pre-check to help reducing mutex lock
@@ -122,8 +121,7 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
 
   // can only claim the endpoint if it is not busy and not claimed yet.
   bool const available = (ep_state->busy == 0) && (ep_state->claimed == 0);
-  if (available)
-  {
+  if (available) {
     ep_state->claimed = 1;
   }
 
@@ -132,16 +130,14 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
   return available;
 }
 
-bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
-{
+bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   (void) mutex;
 
   (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   // can only release the endpoint if it is claimed and not busy
   bool const ret = (ep_state->claimed == 1) && (ep_state->busy == 0);
-  if (ret)
-  {
+  if (ret) {
     ep_state->claimed = 0;
   }
 
-- 
cgit v1.3.1


From 1d3969acbd1d85753c8ad085097a26dcd628afcb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 4 Mar 2024 17:44:53 +0700
Subject: - usbh enumeration: move _parse_configuration_descriptor after
 SET_CONFIGURATION is successful - usbh: abort all pending xfer when
 SET_CONFIGURATION is complete - use tu_edpt_release in tuh_edpt_abort_xfer
 instead of usbh_edpt_release - rename _xfer_complete ->
 _control_xfer_complete

---
 src/host/usbh.c | 44 ++++++++++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 407d97234..625857683 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -621,7 +621,7 @@ TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
   (void) osal_mutex_unlock(_usbh_mutex);
 }
 
-static void _xfer_complete(uint8_t daddr, xfer_result_t result) {
+static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) {
   TU_LOG_USBH("\r\n");
 
   // duplicate xfer since user can execute control transfer within callback
@@ -644,32 +644,32 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result) {
   }
 }
 
-static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
+static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) ep_addr;
 
-  const uint8_t rhport = usbh_get_rhport(dev_addr);
+  const uint8_t rhport = usbh_get_rhport(daddr);
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     TU_LOG_BUF_USBH(request, 8);
 
     // terminate transfer if any stage failed
-    _xfer_complete(dev_addr, result);
+    _control_xfer_complete(daddr, result);
   }else {
     switch(_ctrl_xfer.stage) {
       case CONTROL_STAGE_SETUP:
         if (request->wLength) {
           // DATA stage: initial data toggle is always 1
           _set_control_xfer_stage(CONTROL_STAGE_DATA);
-          TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
+          TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
           return true;
         }
         TU_ATTR_FALLTHROUGH;
 
       case CONTROL_STAGE_DATA:
         if (request->wLength) {
-          TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
+          TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, daddr);
           TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
@@ -677,12 +677,23 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
         // ACK stage: toggle is always 1
         _set_control_xfer_stage(CONTROL_STAGE_ACK);
-        TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0) );
-      break;
+        TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction), NULL, 0) );
+        break;
 
-      case CONTROL_STAGE_ACK:
-        _xfer_complete(dev_addr, result);
-      break;
+      case CONTROL_STAGE_ACK: {
+        // Abort all pending transfers if SET_CONFIGURATION request
+        // NOTE: should we force closing all non-control endpoints in the future?
+        if (request->bRequest == TUSB_REQ_SET_CONFIGURATION && request->bmRequestType == 0x00) {
+          for(uint8_t epnum=1; epnum<CFG_TUH_ENDPOINT_MAX; epnum++) {
+            for(uint8_t dir=0; dir<2; dir++) {
+              tuh_edpt_abort_xfer(daddr, tu_edpt_addr(epnum, dir));
+            }
+          }
+        }
+
+        _control_xfer_complete(daddr, result);
+        break;
+      }
 
       default: return false;
     }
@@ -732,7 +743,7 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
     TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr));
     // mark as ready and release endpoint if transfer is aborted
     dev->ep_status[epnum][dir].busy = false;
-    usbh_edpt_release(daddr, ep_addr);
+    tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex);
   }
 
   return true;
@@ -1414,9 +1425,6 @@ static void process_enumeration(tuh_xfer_t* xfer) {
     }
 
     case ENUM_SET_CONFIG:
-      // Parse configuration & set up drivers
-      // Driver open aren't allowed to make any usb transfer yet
-      TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),);
       TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),);
       break;
 
@@ -1427,6 +1435,10 @@ static void process_enumeration(tuh_xfer_t* xfer) {
 
       dev->configured = 1;
 
+      // Parse configuration & set up drivers
+      // driver_open() must not make any usb transfer
+      TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),);
+
       // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8)
       // Since driver can perform control transfer within its set_config, this is done asynchronously.
       // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
-- 
cgit v1.3.1


From eed37476612b6c2074cc3cdabbdef88c59822114 Mon Sep 17 00:00:00 2001
From: Camila <s1000325098@senor0lunlx0240.eu.sony.com>
Date: Mon, 11 Mar 2024 13:11:07 +0100
Subject: Changes required for SDK 3.2.0:  - Define EP_ALLOCREQ  - Define
 EP_FREEREQ  - Define EP_ALLOCBUFFER  - Define EP_FREEBUFFER

Those were previously defined in spresense-exported-sdk, but now have been removed.
---
 src/portable/sony/cxd56/dcd_cxd56.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'src')

diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index 6677891a5..9a939bc6c 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -39,6 +39,25 @@
 #define CXD56_SETUP_QUEUE_DEPTH (4)
 #define CXD56_MAX_DATA_OUT_SIZE (64)
 
+/* Allocate/free I/O requests.
+ * Should not be called from interrupt processing!
+ */
+
+#define EP_ALLOCREQ(ep)            (ep)->ops->allocreq(ep)
+#define EP_FREEREQ(ep,req)         (ep)->ops->freereq(ep,req)
+
+/* Allocate/free an I/O buffer.
+ * Should not be called from interrupt processing!
+ */
+
+#ifdef CONFIG_USBDEV_DMA
+#  define EP_ALLOCBUFFER(ep,nb)    (ep)->ops->allocbuffer(ep,nb)
+#  define EP_FREEBUFFER(ep,buf)    (ep)->ops->freebuffer(ep,buf)
+#else
+#  define EP_ALLOCBUFFER(ep,nb)    kmm_malloc(nb)
+#  define EP_FREEBUFFER(ep,buf)    kmm_free(buf)
+#endif
+
 OSAL_QUEUE_DEF(usbd_int_set, _setup_queue_def, CXD56_SETUP_QUEUE_DEPTH, struct usb_ctrlreq_s);
 
 struct usbdcd_driver_s
-- 
cgit v1.3.1


From 56532321443ed1ada8c2f33bd9eb6f075da66394 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 5 Mar 2024 19:43:37 +0700
Subject: reformat code

---
 src/device/usbd.c                            | 306 +++++++++----------------
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 330 +++++++++++----------------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 167 ++++++--------
 3 files changed, 316 insertions(+), 487 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index be85d7769..87542e9aa 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -372,10 +372,9 @@ bool tud_inited(void) {
   return _usbd_rhport != RHPORT_INVALID;
 }
 
-bool tud_init (uint8_t rhport)
-{
+bool tud_init(uint8_t rhport) {
   // skip if already initialized
-  if ( tud_inited() ) return true;
+  if (tud_inited()) return true;
 
   TU_LOG_USBD("USBD init on controller %u\r\n", rhport);
   TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
@@ -395,15 +394,13 @@ bool tud_init (uint8_t rhport)
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
-  if ( usbd_app_driver_get_cb )
-  {
+  if (usbd_app_driver_get_cb) {
     _app_driver = usbd_app_driver_get_cb(&_app_driver_count);
   }
 
   // Init class drivers
-  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
-  {
-    usbd_class_driver_t const * driver = get_driver(i);
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
     TU_ASSERT(driver);
     TU_LOG_USBD("%s init\r\n", driver->name);
     driver->init();
@@ -418,31 +415,26 @@ bool tud_init (uint8_t rhport)
   return true;
 }
 
-static void configuration_reset(uint8_t rhport)
-{
-  for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
-  {
-    usbd_class_driver_t const * driver = get_driver(i);
-    TU_ASSERT(driver, );
+static void configuration_reset(uint8_t rhport) {
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
+    TU_ASSERT(driver,);
     driver->reset(rhport);
   }
 
   tu_varclr(&_usbd_dev);
   memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping
-  memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping
+  memset(_usbd_dev.ep2drv, DRVID_INVALID, sizeof(_usbd_dev.ep2drv)); // invalid mapping
 }
 
-static void usbd_reset(uint8_t rhport)
-{
+static void usbd_reset(uint8_t rhport) {
   configuration_reset(rhport);
   usbd_control_reset();
 }
 
-bool tud_task_event_ready(void)
-{
+bool tud_task_event_ready(void) {
   // Skip if stack is not initialized
-  if ( !tud_inited() ) return false;
-
+  if (!tud_inited()) return false;
   return !osal_queue_empty(_usbd_q);
 }
 
@@ -450,53 +442,44 @@ bool tud_task_event_ready(void)
  * This top level thread manages all device controller event and delegates events to class-specific drivers.
  * This should be called periodically within the mainloop or rtos thread.
  *
-   @code
-    int main(void)
-    {
+    int main(void) {
       application_init();
       tusb_init();
 
-      while(1) // the mainloop
-      {
+      while(1) { // the mainloop
         application_code();
         tud_task(); // tinyusb device task
       }
     }
-    @endcode
  */
-void tud_task_ext(uint32_t timeout_ms, bool in_isr)
-{
+void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
-  if ( !tud_inited() ) return;
+  if (!tud_inited()) return;
 
   // Loop until there is no more events in the queue
-  while (1)
-  {
+  while (1) {
     dcd_event_t event;
-    if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return;
+    if (!osal_queue_receive(_usbd_q, &event, timeout_ms)) return;
 
 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
     if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG_USBD("\r\n"); // extra line for setup
     TU_LOG_USBD("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
 #endif
 
-    switch ( event.event_id )
-    {
+    switch (event.event_id) {
       case DCD_EVENT_BUS_RESET:
         TU_LOG_USBD(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
-      break;
+        break;
 
       case DCD_EVENT_UNPLUGGED:
         TU_LOG_USBD("\r\n");
         usbd_reset(event.rhport);
-
-        // invoke callback
         if (tud_umount_cb) tud_umount_cb();
-      break;
+        break;
 
       case DCD_EVENT_SETUP_RECEIVED:
         TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
@@ -508,81 +491,72 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         // mark both in & out control as free
         _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = 0;
         _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0;
-        _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = 0;
-        _usbd_dev.ep_status[0][TUSB_DIR_IN ].claimed = 0;
+        _usbd_dev.ep_status[0][TUSB_DIR_IN].busy = 0;
+        _usbd_dev.ep_status[0][TUSB_DIR_IN].claimed = 0;
 
         // Process control request
-        if ( !process_control_request(event.rhport, &event.setup_received) )
-        {
+        if (!process_control_request(event.rhport, &event.setup_received)) {
           TU_LOG_USBD("  Stall EP0\r\n");
           // Failed -> stall both control endpoint IN and OUT
           dcd_edpt_stall(event.rhport, 0);
           dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK);
         }
-      break;
+        break;
 
-      case DCD_EVENT_XFER_COMPLETE:
-      {
+      case DCD_EVENT_XFER_COMPLETE: {
         // Invoke the class callback associated with the endpoint address
         uint8_t const ep_addr = event.xfer_complete.ep_addr;
-        uint8_t const epnum   = tu_edpt_number(ep_addr);
-        uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
+        uint8_t const epnum = tu_edpt_number(ep_addr);
+        uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
         TU_LOG_USBD("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
         _usbd_dev.ep_status[epnum][ep_dir].busy = 0;
         _usbd_dev.ep_status[epnum][ep_dir].claimed = 0;
 
-        if ( 0 == epnum )
-        {
-          usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete
-          .len);
-        }
-        else
-        {
-          usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] );
-          TU_ASSERT(driver, );
+        if (0 == epnum) {
+          usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result,
+                               event.xfer_complete.len);
+        } else {
+          usbd_class_driver_t const* driver = get_driver(_usbd_dev.ep2drv[epnum][ep_dir]);
+          TU_ASSERT(driver,);
 
           TU_LOG_USBD("  %s xfer callback\r\n", driver->name);
           driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
         }
+        break;
       }
-      break;
 
       case DCD_EVENT_SUSPEND:
         // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
         // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ), which result in a series of event
         // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
-        if ( _usbd_dev.connected )
-        {
+        if (_usbd_dev.connected) {
           TU_LOG_USBD(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
           if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
-        }else
-        {
+        } else {
           TU_LOG_USBD(" Skipped\r\n");
         }
-      break;
+        break;
 
       case DCD_EVENT_RESUME:
-        if ( _usbd_dev.connected )
-        {
+        if (_usbd_dev.connected) {
           TU_LOG_USBD("\r\n");
           if (tud_resume_cb) tud_resume_cb();
-        }else
-        {
+        } else {
           TU_LOG_USBD(" Skipped\r\n");
         }
-      break;
+        break;
 
       case USBD_EVENT_FUNC_CALL:
         TU_LOG_USBD("\r\n");
-        if ( event.func_call.func ) event.func_call.func(event.func_call.param);
-      break;
+        if (event.func_call.func) event.func_call.func(event.func_call.param);
+        break;
 
       case DCD_EVENT_SOF:
       default:
         TU_BREAKPOINT();
-      break;
+        break;
     }
 
 #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
@@ -597,8 +571,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 //--------------------------------------------------------------------+
 
 // Helper to invoke class driver control request handler
-static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
-{
+static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request) {
   usbd_control_set_complete_callback(driver->control_xfer_cb);
   TU_LOG_USBD("  %s control request\r\n", driver->name);
   return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request);
@@ -606,15 +579,12 @@ static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * dri
 
 // This handles the actual request and its response.
 // return false will cause its caller to stall control endpoint
-static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
-{
+static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request) {
   usbd_control_set_complete_callback(NULL);
-
   TU_ASSERT(p_request->bmRequestType_bit.type < TUSB_REQ_TYPE_INVALID);
 
   // Vendor request
-  if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR )
-  {
+  if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR ) {
     TU_VERIFY(tud_vendor_control_xfer_cb);
 
     usbd_control_set_complete_callback(tud_vendor_control_xfer_cb);
@@ -622,19 +592,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
   }
 
 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
-  if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME)
-  {
+  if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) {
     TU_LOG_USBD("  %s", tu_str_std_request[p_request->bRequest]);
     if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n");
   }
 #endif
 
-  switch ( p_request->bmRequestType_bit.recipient )
-  {
+  switch ( p_request->bmRequestType_bit.recipient ) {
     //------------- Device Requests e.g in enumeration -------------//
     case TUSB_REQ_RCPT_DEVICE:
-      if ( TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type )
-      {
+      if ( TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type ) {
         uint8_t const itf = tu_u16_low(p_request->wIndex);
         TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv));
 
@@ -645,15 +612,13 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
         return invoke_class_control(rhport, driver, p_request);
       }
 
-      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type )
-      {
+      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) {
         // Non standard request is not supported
         TU_BREAKPOINT();
         return false;
       }
 
-      switch ( p_request->bRequest )
-      {
+      switch ( p_request->bRequest ) {
         case TUSB_REQ_SET_ADDRESS:
           // Depending on mcu, status phase could be sent either before or after changing device address,
           // or even require stack to not response with status at all
@@ -664,22 +629,18 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           _usbd_dev.addressed = 1;
         break;
 
-        case TUSB_REQ_GET_CONFIGURATION:
-        {
+        case TUSB_REQ_GET_CONFIGURATION: {
           uint8_t cfg_num = _usbd_dev.cfg_num;
           tud_control_xfer(rhport, p_request, &cfg_num, 1);
         }
         break;
 
-        case TUSB_REQ_SET_CONFIGURATION:
-        {
+        case TUSB_REQ_SET_CONFIGURATION: {
           uint8_t const cfg_num = (uint8_t) p_request->wValue;
 
           // Only process if new configure is different
-          if (_usbd_dev.cfg_num != cfg_num)
-          {
-            if ( _usbd_dev.cfg_num )
-            {
+          if (_usbd_dev.cfg_num != cfg_num) {
+            if ( _usbd_dev.cfg_num ) {
               // already configured: need to clear all endpoints and driver first
               TU_LOG_USBD("  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
 
@@ -694,15 +655,11 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
             }
 
             // Handle the new configuration and execute the corresponding callback
-            if ( cfg_num )
-            {
+            if ( cfg_num ) {
               // switch to new configuration if not zero
               TU_ASSERT( process_set_config(rhport, cfg_num) );
-
               if ( tud_mount_cb ) tud_mount_cb();
-            }
-            else
-            {
+            } else {
               if ( tud_umount_cb ) tud_umount_cb();
             }
           }
@@ -738,15 +695,14 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           tud_control_status(rhport, p_request);
         break;
 
-        case TUSB_REQ_GET_STATUS:
-        {
+        case TUSB_REQ_GET_STATUS: {
           // Device status bit mask
           // - Bit 0: Self Powered
           // - Bit 1: Remote Wakeup enabled
           uint16_t status = (uint16_t) ((_usbd_dev.self_powered ? 1u : 0u) | (_usbd_dev.remote_wakeup_en ? 2u : 0u));
           tud_control_xfer(rhport, p_request, &status, 2);
+          break;
         }
-        break;
 
         // Unknown/Unsupported request
         default: TU_BREAKPOINT(); return false;
@@ -754,8 +710,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
     break;
 
     //------------- Class/Interface Specific Request -------------//
-    case TUSB_REQ_RCPT_INTERFACE:
-    {
+    case TUSB_REQ_RCPT_INTERFACE: {
       uint8_t const itf = tu_u16_low(p_request->wIndex);
       TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv));
 
@@ -764,25 +719,21 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 
       // all requests to Interface (STD or Class) is forwarded to class driver.
       // notable requests are: GET HID REPORT DESCRIPTOR, SET_INTERFACE, GET_INTERFACE
-      if ( !invoke_class_control(rhport, driver, p_request) )
-      {
+      if ( !invoke_class_control(rhport, driver, p_request) ) {
         // For GET_INTERFACE and SET_INTERFACE, it is mandatory to respond even if the class
         // driver doesn't use alternate settings or implement this
         TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type);
 
-        switch(p_request->bRequest)
-        {
+        switch(p_request->bRequest) {
           case TUSB_REQ_GET_INTERFACE:
           case TUSB_REQ_SET_INTERFACE:
             // Clear complete callback if driver set since it can also stall the request.
             usbd_control_set_complete_callback(NULL);
 
-            if (TUSB_REQ_GET_INTERFACE == p_request->bRequest)
-            {
+            if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) {
               uint8_t alternate = 0;
               tud_control_xfer(rhport, p_request, &alternate, 1);
-            }else
-            {
+            }else {
               tud_control_status(rhport, p_request);
             }
           break;
@@ -790,54 +741,42 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           default: return false;
         }
       }
+      break;
     }
-    break;
 
     //------------- Endpoint Request -------------//
-    case TUSB_REQ_RCPT_ENDPOINT:
-    {
+    case TUSB_REQ_RCPT_ENDPOINT: {
       uint8_t const ep_addr = tu_u16_low(p_request->wIndex);
       uint8_t const ep_num  = tu_edpt_number(ep_addr);
       uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
       TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv) );
-
       usbd_class_driver_t const * driver = get_driver(_usbd_dev.ep2drv[ep_num][ep_dir]);
 
-      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type )
-      {
+      if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type ) {
         // Forward class request to its driver
         TU_VERIFY(driver);
         return invoke_class_control(rhport, driver, p_request);
-      }
-      else
-      {
+      } else {
         // Handle STD request to endpoint
-        switch ( p_request->bRequest )
-        {
-          case TUSB_REQ_GET_STATUS:
-          {
+        switch ( p_request->bRequest ) {
+          case TUSB_REQ_GET_STATUS: {
             uint16_t status = usbd_edpt_stalled(rhport, ep_addr) ? 0x0001 : 0x0000;
             tud_control_xfer(rhport, p_request, &status, 2);
           }
           break;
 
           case TUSB_REQ_CLEAR_FEATURE:
-          case TUSB_REQ_SET_FEATURE:
-          {
-            if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue )
-            {
-              if ( TUSB_REQ_CLEAR_FEATURE ==  p_request->bRequest )
-              {
+          case TUSB_REQ_SET_FEATURE: {
+            if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue ) {
+              if ( TUSB_REQ_CLEAR_FEATURE ==  p_request->bRequest ) {
                 usbd_edpt_clear_stall(rhport, ep_addr);
-              }else
-              {
+              }else {
                 usbd_edpt_stall(rhport, ep_addr);
               }
             }
 
-            if (driver)
-            {
+            if (driver) {
               // Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request
               // We will also forward std request targeted endpoint to class drivers as well
 
@@ -853,14 +792,18 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           break;
 
           // Unknown/Unsupported request
-          default: TU_BREAKPOINT(); return false;
+          default:
+            TU_BREAKPOINT();
+            return false;
         }
       }
     }
     break;
 
     // Unknown recipient
-    default: TU_BREAKPOINT(); return false;
+    default:
+      TU_BREAKPOINT();
+      return false;
   }
 
   return true;
@@ -1185,8 +1128,7 @@ void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr) {
 // USBD Endpoint API
 //--------------------------------------------------------------------+
 
-bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
-{
+bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) {
   rhport = _usbd_rhport;
 
   TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
@@ -1195,37 +1137,34 @@ bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
   return dcd_edpt_open(rhport, desc_ep);
 }
 
-bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   // TODO add this check later, also make sure we don't starve an out endpoint while suspending
   // TU_VERIFY(tud_ready());
 
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
   return tu_edpt_claim(ep_state, _usbd_mutex);
 }
 
-bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
   return tu_edpt_release(ep_state, _usbd_mutex);
 }
 
-bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // TODO skip ready() check for now since enumeration also use this API
   // TU_VERIFY(tud_ready());
@@ -1239,11 +1178,9 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   // could return and USBD task can preempt and clear the busy
   _usbd_dev.ep_status[epnum][dir].busy = 1;
 
-  if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) )
-  {
+  if (dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes)) {
     return true;
-  }else
-  {
+  } else {
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
@@ -1257,12 +1194,11 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 // bytes should be written and second to keep the return value free to give back a boolean
 // success message. If total_bytes is too big, the FIFO will copy only what is available
 // into the USB buffer!
-bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
+bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t total_bytes) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   TU_LOG_USBD("  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
@@ -1273,12 +1209,10 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   // and usbd task can preempt and clear the busy
   _usbd_dev.ep_status[epnum][dir].busy = 1;
 
-  if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
-  {
+  if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) {
     TU_LOG_USBD("OK\r\n");
     return true;
-  }else
-  {
+  } else {
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
@@ -1288,26 +1222,23 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   }
 }
 
-bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   return _usbd_dev.ep_status[epnum][dir].busy;
 }
 
-void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // only stalled if currently cleared
-  if ( !_usbd_dev.ep_status[epnum][dir].stalled )
-  {
+  if (!_usbd_dev.ep_status[epnum][dir].stalled) {
     TU_LOG_USBD("    Stall EP %02X\r\n", ep_addr);
     dcd_edpt_stall(rhport, ep_addr);
     _usbd_dev.ep_status[epnum][dir].stalled = 1;
@@ -1315,16 +1246,14 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   }
 }
 
-void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // only clear if currently stalled
-  if ( _usbd_dev.ep_status[epnum][dir].stalled )
-  {
+  if (_usbd_dev.ep_status[epnum][dir].stalled) {
     TU_LOG_USBD("    Clear Stall EP %02X\r\n", ep_addr);
     dcd_edpt_clear_stall(rhport, ep_addr);
     _usbd_dev.ep_status[epnum][dir].stalled = 0;
@@ -1332,31 +1261,27 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   }
 }
 
-bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   return _usbd_dev.ep_status[epnum][dir].stalled;
 }
 
 /**
  * usbd_edpt_close will disable an endpoint.
- *
  * In progress transfers on this EP may be delivered after this call.
- *
  */
-void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
+void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
   rhport = _usbd_rhport;
 
   TU_ASSERT(dcd_edpt_close, /**/);
   TU_LOG_USBD("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   dcd_edpt_close(rhport, ep_addr);
   _usbd_dev.ep_status[epnum][dir].stalled = 0;
@@ -1366,8 +1291,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   return;
 }
 
-void usbd_sof_enable(uint8_t rhport, bool en)
-{
+void usbd_sof_enable(uint8_t rhport, bool en) {
   rhport = _usbd_rhport;
 
   // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more.
@@ -1375,8 +1299,7 @@ void usbd_sof_enable(uint8_t rhport, bool en)
   dcd_sof_enable(rhport, en);
 }
 
-bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
-{
+bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
   rhport = _usbd_rhport;
 
   TU_ASSERT(dcd_edpt_iso_alloc);
@@ -1385,12 +1308,11 @@ bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packe
   return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
 }
 
-bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
-{
+bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) {
   rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_ep->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress);
 
   TU_ASSERT(dcd_edpt_iso_activate);
   TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX);
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index e8cee73fd..ba7e9f912 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -48,7 +48,7 @@
  *------------------------------------------------------------------*/
 
 // Init these in dcd_init
-static uint8_t *next_buffer_ptr;
+static uint8_t* next_buffer_ptr;
 
 // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in.
 static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
@@ -56,79 +56,70 @@ static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
 // SOF may be used by remote wakeup as RESUME, this indicate whether SOF is actually used by usbd
 static bool _sof_enable = false;
 
-TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
-{
+TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir) {
   return &hw_endpoints[num][dir];
 }
 
-static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
-{
+static struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) {
   uint8_t num = tu_edpt_number(ep_addr);
   tusb_dir_t dir = tu_edpt_dir(ep_addr);
   return hw_endpoint_get_by_num(num, dir);
 }
 
-static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
-{
+static void _hw_endpoint_alloc(struct hw_endpoint* ep, uint8_t transfer_type) {
   // size must be multiple of 64
   uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
 
   // double buffered Bulk endpoint
-  if ( transfer_type == TUSB_XFER_BULK )
-  {
+  if (transfer_type == TUSB_XFER_BULK) {
     size *= 2u;
   }
 
   ep->hw_data_buf = next_buffer_ptr;
   next_buffer_ptr += size;
 
-  assert(((uintptr_t )next_buffer_ptr & 0b111111u) == 0);
+  assert(((uintptr_t) next_buffer_ptr & 0b111111u) == 0);
   uint dpram_offset = hw_data_offset(ep->hw_data_buf);
   hard_assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
 
   pico_info("  Allocated %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
 
   // Fill in endpoint control register with buffer offset
-  uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
+  uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
 
   *ep->endpoint_control = reg;
 }
 
-static void _hw_endpoint_close(struct hw_endpoint *ep)
-{
-    // Clear hardware registers and then zero the struct
-    // Clears endpoint enable
-    *ep->endpoint_control = 0;
-    // Clears buffer available, etc
-    *ep->buffer_control = 0;
-    // Clear any endpoint state
-    memset(ep, 0, sizeof(struct hw_endpoint));
-
-    // Reclaim buffer space if all endpoints are closed
-    bool reclaim_buffers = true;
-    for ( uint8_t i = 1; i < USB_MAX_ENDPOINTS; i++ )
-    {
-        if (hw_endpoint_get_by_num(i, TUSB_DIR_OUT)->hw_data_buf != NULL || hw_endpoint_get_by_num(i, TUSB_DIR_IN)->hw_data_buf != NULL)
-        {
-            reclaim_buffers = false;
-            break;
-        }
-    }
-    if (reclaim_buffers)
-    {
-        next_buffer_ptr = &usb_dpram->epx_data[0];
+static void _hw_endpoint_close(struct hw_endpoint* ep) {
+  // Clear hardware registers and then zero the struct
+  // Clears endpoint enable
+  *ep->endpoint_control = 0;
+  // Clears buffer available, etc
+  *ep->buffer_control = 0;
+  // Clear any endpoint state
+  memset(ep, 0, sizeof(struct hw_endpoint));
+
+  // Reclaim buffer space if all endpoints are closed
+  bool reclaim_buffers = true;
+  for (uint8_t i = 1; i < USB_MAX_ENDPOINTS; i++) {
+    if (hw_endpoint_get_by_num(i, TUSB_DIR_OUT)->hw_data_buf != NULL ||
+        hw_endpoint_get_by_num(i, TUSB_DIR_IN)->hw_data_buf != NULL) {
+      reclaim_buffers = false;
+      break;
     }
+  }
+  if (reclaim_buffers) {
+    next_buffer_ptr = &usb_dpram->epx_data[0];
+  }
 }
 
-static void hw_endpoint_close(uint8_t ep_addr)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_close(ep);
+static void hw_endpoint_close(uint8_t ep_addr) {
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
+  _hw_endpoint_close(ep);
 }
 
-static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
-{
-  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) {
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
 
   const uint8_t num = tu_edpt_number(ep_addr);
   const tusb_dir_t dir = tu_edpt_dir(ep_addr);
@@ -143,35 +134,26 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
   ep->transfer_type = transfer_type;
 
   // Every endpoint has a buffer control register in dpram
-  if ( dir == TUSB_DIR_IN )
-  {
+  if (dir == TUSB_DIR_IN) {
     ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
-  }
-  else
-  {
+  } else {
     ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
   }
 
   // Clear existing buffer control state
   *ep->buffer_control = 0;
 
-  if ( num == 0 )
-  {
+  if (num == 0) {
     // EP0 has no endpoint control register because the buffer offsets are fixed
     ep->endpoint_control = NULL;
 
     // Buffer offset is fixed (also double buffered)
     ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
-  }
-  else
-  {
+  } else {
     // Set the endpoint control register (starts at EP1, hence num-1)
-    if ( dir == TUSB_DIR_IN )
-    {
+    if (dir == TUSB_DIR_IN) {
       ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in;
-    }
-    else
-    {
+    } else {
       ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
     }
 
@@ -180,76 +162,65 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
   }
 }
 
-static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    hw_endpoint_xfer_start(ep, buffer, total_bytes);
+static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
+  hw_endpoint_xfer_start(ep, buffer, total_bytes);
 }
 
-static void __tusb_irq_path_func(hw_handle_buff_status)(void)
-{
-    uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers);
-    uint bit = 1u;
-    for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
-    {
-        if (remaining_buffers & bit)
-        {
-            // clear this in advance
-            usb_hw_clear->buf_status = bit;
-
-            // IN transfer for even i, OUT transfer for odd i
-            struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, (i & 1u) ? TUSB_DIR_OUT : TUSB_DIR_IN);
-
-            // Continue xfer
-            bool done = hw_endpoint_xfer_continue(ep);
-            if (done)
-            {
-                // Notify
-                dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true);
-                hw_endpoint_reset_transfer(ep);
-            }
-            remaining_buffers &= ~bit;
-        }
-        bit <<= 1u;
+static void __tusb_irq_path_func(hw_handle_buff_status)(void) {
+  uint32_t remaining_buffers = usb_hw->buf_status;
+  pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers);
+  uint bit = 1u;
+  for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++) {
+    if (remaining_buffers & bit) {
+      // clear this in advance
+      usb_hw_clear->buf_status = bit;
+
+      // IN transfer for even i, OUT transfer for odd i
+      struct hw_endpoint* ep = hw_endpoint_get_by_num(i >> 1u, (i & 1u) ? TUSB_DIR_OUT : TUSB_DIR_IN);
+
+      // Continue xfer
+      bool done = hw_endpoint_xfer_continue(ep);
+      if (done) {
+        // Notify
+        dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true);
+        hw_endpoint_reset_transfer(ep);
+      }
+      remaining_buffers &= ~bit;
     }
+    bit <<= 1u;
+  }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void)
-{
-    // If we have finished this transfer on EP0 set pid back to 1 for next
-    // setup transfer. Also clear a stall in case
-    uint8_t addrs[] = {0x0, 0x80};
-    for (uint i = 0 ; i < TU_ARRAY_SIZE(addrs); i++)
-    {
-        struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]);
-        ep->next_pid = 1u;
-    }
+TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void) {
+  // If we have finished this transfer on EP0 set pid back to 1 for next
+  // setup transfer. Also clear a stall in case
+  uint8_t addrs[] = {0x0, 0x80};
+  for (uint i = 0; i < TU_ARRAY_SIZE(addrs); i++) {
+    struct hw_endpoint* ep = hw_endpoint_get_by_addr(addrs[i]);
+    ep->next_pid = 1u;
+  }
 }
 
-static void __tusb_irq_path_func(reset_non_control_endpoints)(void)
-{
+static void __tusb_irq_path_func(reset_non_control_endpoints)(void) {
   // Disable all non-control
-  for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ )
-  {
+  for (uint8_t i = 0; i < USB_MAX_ENDPOINTS - 1; i++) {
     usb_dpram->ep_ctrl[i].in = 0;
     usb_dpram->ep_ctrl[i].out = 0;
   }
 
   // clear non-control hw endpoints
-  tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t));
+  tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2 * sizeof(hw_endpoint_t));
 
   // reclaim buffer space
   next_buffer_ptr = &usb_dpram->epx_data[0];
 }
 
-static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
-{
+static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
   uint32_t const status = usb_hw->ints;
   uint32_t handled = 0;
 
-  if ( status & USB_INTF_DEV_SOF_BITS )
-  {
+  if (status & USB_INTF_DEV_SOF_BITS) {
     bool keep_sof_alive = false;
 
     handled |= USB_INTF_DEV_SOF_BITS;
@@ -258,20 +229,17 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
     // Errata 15 workaround for Device Bulk-In endpoint
     e15_last_sof = time_us_32();
 
-    for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++ )
-    {
-      struct hw_endpoint * ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
+    for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) {
+      struct hw_endpoint* ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
 
       // Active Bulk IN endpoint requires SOF
-      if ( (ep->transfer_type == TUSB_XFER_BULK) && ep->active )
-      {
+      if ((ep->transfer_type == TUSB_XFER_BULK) && ep->active) {
         keep_sof_alive = true;
 
         hw_endpoint_lock_update(ep, 1);
 
         // Deferred enable?
-        if ( ep->pending )
-        {
+        if (ep->pending) {
           ep->pending = 0;
           hw_endpoint_start_next_buffer(ep);
         }
@@ -282,23 +250,21 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 #endif
 
     // disable SOF interrupt if it is used for RESUME in remote wakeup
-    if ( !keep_sof_alive && !_sof_enable ) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+    if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
 
     dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
   }
 
   // xfer events are handled before setup req. So if a transfer completes immediately
   // before closing the EP, the events will be delivered in same order.
-  if ( status & USB_INTS_BUFF_STATUS_BITS )
-  {
+  if (status & USB_INTS_BUFF_STATUS_BITS) {
     handled |= USB_INTS_BUFF_STATUS_BITS;
     hw_handle_buff_status();
   }
 
-  if ( status & USB_INTS_SETUP_REQ_BITS )
-  {
+  if (status & USB_INTS_SETUP_REQ_BITS) {
     handled |= USB_INTS_SETUP_REQ_BITS;
-    uint8_t const * setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet);
+    uint8_t const* setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet);
 
     // reset pid to both 1 (data and ack)
     reset_ep0_pid();
@@ -329,8 +295,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 #endif
 
   // SE0 for 2.5 us or more (will last at least 10ms)
-  if ( status & USB_INTS_BUS_RESET_BITS )
-  {
+  if (status & USB_INTS_BUS_RESET_BITS) {
     pico_trace("BUS RESET\r\n");
 
     handled |= USB_INTS_BUS_RESET_BITS;
@@ -342,7 +307,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
     // Only run enumeration workaround if pull up is enabled
-    if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix();
+    if (usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS) rp2040_usb_device_enumeration_fix();
 #endif
   }
 
@@ -354,22 +319,19 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
    * because without VBUS detection, it is impossible to tell the difference between
    * being disconnected and suspended.
    */
-  if ( status & USB_INTS_DEV_SUSPEND_BITS )
-  {
+  if (status & USB_INTS_DEV_SUSPEND_BITS) {
     handled |= USB_INTS_DEV_SUSPEND_BITS;
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
     usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS;
   }
 
-  if ( status & USB_INTS_DEV_RESUME_FROM_HOST_BITS )
-  {
+  if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS) {
     handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS;
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
     usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
   }
 
-  if ( status ^ handled )
-  {
+  if (status ^ handled) {
     panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
   }
 }
@@ -390,8 +352,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 #define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
 #endif
 
-void dcd_init (uint8_t rhport)
-{
+void dcd_init(uint8_t rhport) {
   assert(rhport == 0);
 
   // Reset hardware to default state
@@ -405,7 +366,7 @@ void dcd_init (uint8_t rhport)
   irq_add_shared_handler(USBCTRL_IRQ, dcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
 
   // Init control endpoints
-  tu_memclr(hw_endpoints[0], 2*sizeof(hw_endpoint_t));
+  tu_memclr(hw_endpoints[0], 2 * sizeof(hw_endpoint_t));
   hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
   hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
 
@@ -420,27 +381,24 @@ void dcd_init (uint8_t rhport)
   // for the global interrupt enable...
   // Note: Force VBUS detect cause disconnection not detectable
   usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS;
-  usb_hw->inte     = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
-                     USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS |
-                     (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
+  usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
+                 USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS |
+                 (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
 
   dcd_connect(rhport);
 }
 
-void dcd_int_enable(__unused uint8_t rhport)
-{
-    assert(rhport == 0);
-    irq_set_enabled(USBCTRL_IRQ, true);
+void dcd_int_enable(__unused uint8_t rhport) {
+  assert(rhport == 0);
+  irq_set_enabled(USBCTRL_IRQ, true);
 }
 
-void dcd_int_disable(__unused uint8_t rhport)
-{
-    assert(rhport == 0);
-    irq_set_enabled(USBCTRL_IRQ, false);
+void dcd_int_disable(__unused uint8_t rhport) {
+  assert(rhport == 0);
+  irq_set_enabled(USBCTRL_IRQ, false);
 }
 
-void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr)
-{
+void dcd_set_address(__unused uint8_t rhport, __unused uint8_t dev_addr) {
   assert(rhport == 0);
 
   // Can't set device address in hardware until status xfer has complete
@@ -448,8 +406,7 @@ void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr)
   hw_endpoint_xfer(0x80, NULL, 0);
 }
 
-void dcd_remote_wakeup(__unused uint8_t rhport)
-{
+void dcd_remote_wakeup(__unused uint8_t rhport) {
   pico_info("dcd_remote_wakeup %d\n", rhport);
   assert(rhport == 0);
 
@@ -460,100 +417,88 @@ void dcd_remote_wakeup(__unused uint8_t rhport)
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(__unused uint8_t rhport)
-{
+void dcd_disconnect(__unused uint8_t rhport) {
   (void) rhport;
   usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
 // connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(__unused uint8_t rhport)
-{
+void dcd_connect(__unused uint8_t rhport) {
   (void) rhport;
   usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void) rhport;
 
   _sof_enable = en;
 
-  if (en)
-  {
+  if (en) {
     usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
-  }else
-  {
+  }
+#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+  else {
     // Don't clear immediately if the SOF workaround is in use.
     // The SOF handler will conditionally disable the interrupt.
-#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
     usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
-#endif
   }
+#endif
 }
 
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
 
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
-{
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) {
   (void) rhport;
 
-  if ( request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
-       request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-       request->bRequest == TUSB_REQ_SET_ADDRESS )
-  {
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS) {
     usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
   }
 }
 
-bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
-    assert(rhport == 0);
-    hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer);
-    return true;
+bool dcd_edpt_open(__unused uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
+  assert(rhport == 0);
+  hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer);
+  return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
-{
+void dcd_edpt_close_all(uint8_t rhport) {
   (void) rhport;
 
   // may need to use EP Abort
   reset_non_control_endpoints();
 }
 
-bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-    assert(rhport == 0);
-    hw_endpoint_xfer(ep_addr, buffer, total_bytes);
-    return true;
+bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
+  assert(rhport == 0);
+  hw_endpoint_xfer(ep_addr, buffer, total_bytes);
+  return true;
 }
 
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
-  if ( tu_edpt_number(ep_addr) == 0 )
-  {
+  if (tu_edpt_number(ep_addr) == 0) {
     // A stall on EP0 has to be armed so it can be cleared on the next setup packet
-    usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
+    usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS
+                                                                     : USB_EP_STALL_ARM_EP0_OUT_BITS;
   }
 
-  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+  struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
 
   // stall and clear current pending buffer
   // may need to use EP_ABORT
   _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_STALL);
 }
 
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
-  if (tu_edpt_number(ep_addr))
-  {
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+  if (tu_edpt_number(ep_addr)) {
+    struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr);
 
     // clear stall also reset toggle to DATA0, ready for next transfer
     ep->next_pid = 0;
@@ -561,16 +506,13 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   }
 }
 
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
-    (void) rhport;
-
-    pico_trace("dcd_edpt_close %02x\r\n", ep_addr);
-    hw_endpoint_close(ep_addr);
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+  pico_trace("dcd_edpt_close %02x\r\n", ep_addr);
+  hw_endpoint_close(ep_addr);
 }
 
-void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport)
-{
+void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport) {
   (void) rhport;
   dcd_rp2040_irq();
 }
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index a512dc34f..b5bace972 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -37,24 +37,23 @@
 //--------------------------------------------------------------------+
 
 // Direction strings for debug
-const char *ep_dir_string[] = {
-        "out",
-        "in",
+const char* ep_dir_string[] = {
+    "out",
+    "in",
 };
 
-static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
+static void _hw_endpoint_xfer_sync(struct hw_endpoint* ep);
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-  static bool e15_is_bulkin_ep(struct hw_endpoint *ep);
-  static bool e15_is_critical_frame_period(struct hw_endpoint *ep);
+  static bool e15_is_bulkin_ep(struct hw_endpoint* ep);
+  static bool e15_is_critical_frame_period(struct hw_endpoint* ep);
 #else
   #define e15_is_bulkin_ep(x)             (false)
   #define e15_is_critical_frame_period(x) (false)
 #endif
 
 // if usb hardware is in host mode
-TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void) {
   return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
 }
 
@@ -62,8 +61,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
 // Implementation
 //--------------------------------------------------------------------+
 
-void rp2040_usb_init(void)
-{
+void rp2040_usb_init(void) {
   // Reset usb controller
   reset_block(RESETS_RESET_USBCTRL_BITS);
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
@@ -88,45 +86,40 @@ void rp2040_usb_init(void)
   TU_LOG2_INT(sizeof(hw_endpoint_t));
 }
 
-void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
-{
+void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint* ep) {
   ep->active = false;
   ep->remaining_len = 0;
   ep->xferred_len = 0;
   ep->user_buf = 0;
 }
 
-void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask)
-{
+void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint* ep, uint32_t and_mask,
+                                                               uint32_t or_mask) {
   uint32_t value = 0;
 
-  if ( and_mask )
-  {
+  if (and_mask) {
     value = *ep->buffer_control & and_mask;
   }
 
-  if ( or_mask )
-  {
+  if (or_mask) {
     value |= or_mask;
-    if ( or_mask & USB_BUF_CTRL_AVAIL )
-    {
-      if ( *ep->buffer_control & USB_BUF_CTRL_AVAIL )
-      {
+    if (or_mask & USB_BUF_CTRL_AVAIL) {
+      if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
         panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
       }
       *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
       // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
       // Don't need delay in host mode as host is in charge
 #if !CFG_TUH_ENABLED
-            __asm volatile (
-                    "b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1: b 1f\n"
-                    "1:\n"
-                    : : : "memory");
+      __asm volatile (
+          "b 1f\n"
+          "1: b 1f\n"
+          "1: b 1f\n"
+          "1: b 1f\n"
+          "1: b 1f\n"
+          "1: b 1f\n"
+          "1:\n"
+          : : : "memory");
 #endif
     }
   }
@@ -135,10 +128,9 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi
 }
 
 // prepare buffer, return buffer control
-static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
-{
+static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) {
   uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
-  ep->remaining_len = (uint16_t)(ep->remaining_len - buflen);
+  ep->remaining_len = (uint16_t) (ep->remaining_len - buflen);
 
   uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL;
 
@@ -146,10 +138,9 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
   buf_ctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
   ep->next_pid ^= 1u;
 
-  if ( !ep->rx )
-  {
+  if (!ep->rx) {
     // Copy data from user buffer to hw buffer
-    memcpy(ep->hw_data_buf + buf_id*64, ep->user_buf, buflen);
+    memcpy(ep->hw_data_buf + buf_id * 64, ep->user_buf, buflen);
     ep->user_buf += buflen;
 
     // Mark as full
@@ -159,8 +150,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
   // Is this the last buffer? Only really matters for host mode. Will trigger
   // the trans complete irq but also stop it polling. We only really care about
   // trans complete for setup packets being sent
-  if (ep->remaining_len == 0)
-  {
+  if (ep->remaining_len == 0) {
     buf_ctrl |= USB_BUF_CTRL_LAST;
   }
 
@@ -170,8 +160,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
 }
 
 // Prepare buffer control register value
-void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
-{
+void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint* ep) {
   uint32_t ep_ctrl = *ep->endpoint_control;
 
   // always compute and start with buffer 0
@@ -186,8 +175,7 @@ void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
   bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) ||
                             (is_host && tu_edpt_number(ep->ep_addr) != 0);
 
-  if(ep->remaining_len && !force_single)
-  {
+  if (ep->remaining_len && !force_single) {
     // Use buffer 1 (double buffered) if there is still data
     // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
 
@@ -196,8 +184,7 @@ void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
     // Set endpoint control double buffered bit if needed
     ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
     ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
-  }else
-  {
+  } else {
     // Single buffered since 1 is enough
     ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
     ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
@@ -212,35 +199,30 @@ void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
   _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl);
 }
 
-void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
-{
+void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t total_len) {
   hw_endpoint_lock_update(ep, 1);
 
-  if ( ep->active )
-  {
+  if (ep->active) {
     // TODO: Is this acceptable for interrupt packets?
     TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\r\n", tu_edpt_number(ep->ep_addr),
-              ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+           ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
     hw_endpoint_reset_transfer(ep);
   }
 
   // Fill in info now that we're kicking off the hw
   ep->remaining_len = total_len;
-  ep->xferred_len   = 0;
-  ep->active        = true;
-  ep->user_buf      = buffer;
+  ep->xferred_len = 0;
+  ep->active = true;
+  ep->user_buf = buffer;
 
-  if ( e15_is_bulkin_ep(ep) )
-  {
+  if (e15_is_bulkin_ep(ep)) {
     usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
   }
 
-  if ( e15_is_critical_frame_period(ep) )
-  {
+  if (e15_is_critical_frame_period(ep)) {
     ep->pending = 1;
-  } else
-  {
+  } else {
     hw_endpoint_start_next_buffer(ep);
   }
 
@@ -248,34 +230,30 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
 }
 
 // sync endpoint buffer and return transferred bytes
-static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
-{
+static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint* ep, uint8_t buf_id) {
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-  if (buf_id)  buf_ctrl = buf_ctrl >> 16;
+  if (buf_id) buf_ctrl = buf_ctrl >> 16;
 
   uint16_t xferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
 
-  if ( !ep->rx )
-  {
+  if (!ep->rx) {
     // We are continuing a transfer here. If we are TX, we have successfully
     // sent some data can increase the length we have sent
     assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
 
-    ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
-  }else
-  {
+    ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
+  } else {
     // If we have received some data, so can increase the length
     // we have received AFTER we have copied it to the user buffer at the appropriate offset
     assert(buf_ctrl & USB_BUF_CTRL_FULL);
 
-    memcpy(ep->user_buf, ep->hw_data_buf + buf_id*64, xferred_bytes);
-    ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
+    memcpy(ep->user_buf, ep->hw_data_buf + buf_id * 64, xferred_bytes);
+    ep->xferred_len = (uint16_t) (ep->xferred_len + xferred_bytes);
     ep->user_buf += xferred_bytes;
   }
 
   // Short packet
-  if (xferred_bytes < ep->wMaxPacketSize)
-  {
+  if (xferred_bytes < ep->wMaxPacketSize) {
     pico_trace("  Short packet on buffer %d with %u bytes\r\n", buf_id, xferred_bytes);
     // Reduce total length as this is last packet
     ep->remaining_len = 0;
@@ -284,8 +262,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uin
   return xferred_bytes;
 }
 
-static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep)
-{
+static void __tusb_irq_path_func(_hw_endpoint_xfer_sync)(struct hw_endpoint* ep) {
   // Update hw endpoint struct with info from hardware
   // after a buff status interrupt
 
@@ -296,14 +273,11 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
   uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
 
   // sync buffer 1 if double buffered
-  if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
-  {
-    if (buf0_bytes == ep->wMaxPacketSize)
-    {
+  if ((*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS) {
+    if (buf0_bytes == ep->wMaxPacketSize) {
       // sync buffer 1 if not short packet
       sync_ep_buffer(ep, 1);
-    }else
-    {
+    } else {
       // short packet on buffer 0
       // TODO couldn't figure out how to handle this case which happen with net_lwip_webserver example
       // At this time (currently trigger per 2 buffer), the buffer1 is probably filled with data from
@@ -335,14 +309,13 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
 }
 
 // Returns true if transfer is complete
-bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
-{
+bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
   hw_endpoint_lock_update(ep, 1);
 
   // Part way through a transfer
-  if (!ep->active)
-  {
-    panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+  if (!ep->active) {
+    panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr),
+          ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
   }
 
   // Update EP struct from hardware state
@@ -350,21 +323,16 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
 
   // Now we have synced our state with the hardware. Is there more data to transfer?
   // If we are done then notify tinyusb
-  if (ep->remaining_len == 0)
-  {
+  if (ep->remaining_len == 0) {
     pico_trace("Completed transfer of %d bytes on ep %d %s\r\n",
                ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
     // Notify caller we are done so it can notify the tinyusb stack
     hw_endpoint_lock_update(ep, -1);
     return true;
-  }
-  else
-  {
-    if ( e15_is_critical_frame_period(ep) )
-    {
+  } else {
+    if (e15_is_critical_frame_period(ep)) {
       ep->pending = 1;
-    } else
-    {
+    } else {
       hw_endpoint_start_next_buffer(ep);
     }
   }
@@ -399,16 +367,14 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
 volatile uint32_t e15_last_sof = 0;
 
 // check if Errata 15 is needed for this endpoint i.e device bulk-in
-static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep)
-{
+static bool __tusb_irq_path_func(e15_is_bulkin_ep)(struct hw_endpoint* ep) {
   return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
           ep->transfer_type == TUSB_XFER_BULK);
 }
 
 // check if we need to apply Errata 15 workaround : i.e
 // Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame
-static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep)
-{
+static bool __tusb_irq_path_func(e15_is_critical_frame_period)(struct hw_endpoint* ep) {
   TU_VERIFY(e15_is_bulkin_ep(ep));
 
   /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
@@ -419,11 +385,10 @@ static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoi
   if (delta < 800 || delta > 998) {
     return false;
   }
-  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
+  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(),
+         e15_last_sof);
   return true;
 }
 
-#endif
-
-
+#endif // TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
 #endif
-- 
cgit v1.3.1


From 6dc714b6de8eaa58e4239f831786d383b7f9bb86 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 13 Mar 2024 11:41:58 +0700
Subject: - only abort ep0 if it is active - rename reset_ep0_pid() to
 reset_ep0() - minor update log message

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 70 +++++++++++-----------------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 35 ++++----------
 2 files changed, 36 insertions(+), 69 deletions(-)

(limited to 'src')

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 0e9dd84e5..5c564cb1c 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -60,7 +60,7 @@ TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_num(u
   return &hw_endpoints[num][dir];
 }
 
-static struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) {
+TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_addr(uint8_t ep_addr) {
   uint8_t num = tu_edpt_number(ep_addr);
   tusb_dir_t dir = tu_edpt_dir(ep_addr);
   return hw_endpoint_get_by_num(num, dir);
@@ -192,47 +192,31 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) {
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void)
-{
-    // Abort any transactions from a prior control transfer, because
-    // receiving SETUP doesn't reset buffer control state. This works around
-    // a possible USB hardware erratum.
-
-    // With this workaround a race window still exists, but smaller.
-    // ABORT flag is unusable prior to hardware B2 (RP2040-E2), so a larger
-    // race window exists for B1 and earlier.
-    if (rp2040_chip_version() >= 2) {
-        usb_hw_set->abort = 0x3;
-        while ((usb_hw->abort_done & 0x3) != 0x3)
-            ;
-    }
-    // If we have finished this transfer on EP0 set pid back to 1 for next
-    // setup transfer. Also clear a stall in case
-    uint8_t addrs[] = {0x0, 0x80};
-    for (uint i = 0 ; i < TU_ARRAY_SIZE(addrs); i++)
-    {
-        struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]);
-        ep->next_pid = 1u;
-        // Reset the buffer control now to minimize race conditions
-        _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL);
-        // Explicit delay, because the one in
-        // _hw_endpoint_buffer_control_set_value32 is only to set AVAILABLE
-        __asm volatile (
-            "b 1f\n"
-            "1: b 1f\n"
-            "1: b 1f\n"
-            "1: b 1f\n"
-            "1: b 1f\n"
-            "1: b 1f\n"
-            "1:\n"
-            : : : "memory");
-        // Make sure local ep state matches peripheral
-        hw_endpoint_reset_transfer(ep);
-    }
-    if (rp2040_chip_version() >= 2) {
-        usb_hw_clear->abort = 0x3;
-        usb_hw_clear->abort_done = 0x3;
+TU_ATTR_ALWAYS_INLINE static inline void reset_ep0(void) {
+  // If we have finished this transfer on EP0 set pid back to 1 for next
+  // setup transfer. Also clear a stall in case
+  for (uint8_t dir = 0; dir < 2; dir++) {
+    struct hw_endpoint* ep = hw_endpoint_get_by_num(0, dir);
+    if (ep->active) {
+      // Abort any pending transfer from a prior control transfer per USB specs
+      // Due to Errata RP2040-E2: ABORT flag is only applicable for B2 and later (unusable for B0, B1).
+      // Which means we are not guaranteed to safely abort pending transfer on B0 and B1.
+      uint32_t const abort_mask = (dir ? USB_EP_ABORT_EP0_IN_BITS : USB_EP_ABORT_EP0_OUT_BITS);
+      if (rp2040_chip_version() >= 2) {
+        usb_hw_set->abort = abort_mask;
+        while ((usb_hw->abort_done & abort_mask) != abort_mask) {}
+      }
+
+      _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL);
+      hw_endpoint_reset_transfer(ep);
+
+      if (rp2040_chip_version() >= 2) {
+        usb_hw_clear->abort_done = abort_mask;
+        usb_hw_clear->abort = abort_mask;
+      }
     }
+    ep->next_pid = 1u;
+  }
 }
 
 static void __tusb_irq_path_func(reset_non_control_endpoints)(void) {
@@ -300,7 +284,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
     uint8_t const* setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet);
 
     // reset pid to both 1 (data and ack)
-    reset_ep0_pid();
+    reset_ep0();
 
     // Pass setup packet to tiny usb
     dcd_event_setup_received(0, setup, true);
@@ -388,6 +372,8 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) {
 void dcd_init(uint8_t rhport) {
   assert(rhport == 0);
 
+  TU_LOG(2, "Chip Version B%u\r\n", rp2040_chip_version());
+
   // Reset hardware to default state
   rp2040_usb_init();
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index b5bace972..1ca711c77 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -35,13 +35,6 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPE
 //--------------------------------------------------------------------+
-
-// Direction strings for debug
-const char* ep_dir_string[] = {
-    "out",
-    "in",
-};
-
 static void _hw_endpoint_xfer_sync(struct hw_endpoint* ep);
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
@@ -105,22 +98,14 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi
     value |= or_mask;
     if (or_mask & USB_BUF_CTRL_AVAIL) {
       if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
-        panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+        panic("ep %02X was already available", ep->ep_addr);
       }
       *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
-      // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
+      // 4.1.2.5.1 Con-current access: 12 cycles (should be good for 48*12Mhz = 576Mhz) after write to buffer control
       // Don't need delay in host mode as host is in charge
-#if !CFG_TUH_ENABLED
-      __asm volatile (
-          "b 1f\n"
-          "1: b 1f\n"
-          "1: b 1f\n"
-          "1: b 1f\n"
-          "1: b 1f\n"
-          "1: b 1f\n"
-          "1:\n"
-          : : : "memory");
-#endif
+      if ( !is_host_mode()) {
+        busy_wait_at_least_cycles(12);
+      }
     }
   }
 
@@ -204,9 +189,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint* ep, uint8_t* buffer, uint16_t to
 
   if (ep->active) {
     // TODO: Is this acceptable for interrupt packets?
-    TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\r\n", tu_edpt_number(ep->ep_addr),
-           ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-
+    TU_LOG(1, "WARN: starting new transfer on already active ep %02X\r\n", ep->ep_addr);
     hw_endpoint_reset_transfer(ep);
   }
 
@@ -314,8 +297,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
 
   // Part way through a transfer
   if (!ep->active) {
-    panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr),
-          ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+    panic("Can't continue xfer on inactive ep %02X", ep->ep_addr);
   }
 
   // Update EP struct from hardware state
@@ -324,8 +306,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint* ep) {
   // Now we have synced our state with the hardware. Is there more data to transfer?
   // If we are done then notify tinyusb
   if (ep->remaining_len == 0) {
-    pico_trace("Completed transfer of %d bytes on ep %d %s\r\n",
-               ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+    pico_trace("Completed transfer of %d bytes on ep %02X\r\n", ep->xferred_len, ep->ep_addr);
     // Notify caller we are done so it can notify the tinyusb stack
     hw_endpoint_lock_update(ep, -1);
     return true;
-- 
cgit v1.3.1


From 834e2c956007709b69f5f85c426dcf51bb2abf63 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 13 Mar 2024 11:46:23 +0700
Subject: usbd only process last setup packet in the event queue

---
 .idea/.gitignore  |  2 ++
 src/device/usbd.c | 13 ++++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/.idea/.gitignore b/.idea/.gitignore
index 73f69e095..b0811f163 100644
--- a/.idea/.gitignore
+++ b/.idea/.gitignore
@@ -6,3 +6,5 @@
 /dataSources.local.xml
 # Editor-based HTTP Client requests
 /httpRequests/
+# GitHub Copilot persisted chat sessions
+/copilot/chatSessions
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 87542e9aa..ab572e095 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -68,9 +68,9 @@ typedef struct {
     uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute
     uint8_t self_powered          : 1; // configuration descriptor's attribute
   };
-
   volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
   uint8_t speed;
+  volatile uint8_t setup_count;
 
   uint8_t itf2drv[CFG_TUD_INTERFACE_MAX];   // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each
@@ -378,6 +378,7 @@ bool tud_init(uint8_t rhport) {
 
   TU_LOG_USBD("USBD init on controller %u\r\n", rhport);
   TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t));
   TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
   TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t));
 
@@ -482,7 +483,12 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) {
         break;
 
       case DCD_EVENT_SETUP_RECEIVED:
+        _usbd_dev.setup_count--;
         TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
+        if (_usbd_dev.setup_count) {
+          TU_LOG_USBD("  Skipped since there is other SETUP in queue\r\n");
+          break;
+        }
 
         // Mark as connected after receiving 1st setup packet.
         // But it is easier to set it every time instead of wasting time to check then set
@@ -1063,6 +1069,11 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr)
       // skip osal queue for SOF in usbd task
       break;
 
+    case DCD_EVENT_SETUP_RECEIVED:
+      _usbd_dev.setup_count++;
+      send = true;
+      break;
+
     default:
       send = true;
       break;
-- 
cgit v1.3.1


From 5a854ef2dc03373f125b48e93accf302c2fbdd66 Mon Sep 17 00:00:00 2001
From: henneboi <william.hennebois@st.com>
Date: Mon, 11 Mar 2024 13:36:25 +0100
Subject: dcd_stm32_fsdev.c:  Fix a bug seend with  stm32h5xxx when the driver
 is compiled with cubeide O1/O2/O3

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 3f4db985d..e0df21860 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -296,6 +296,19 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB
 {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
+  volatile uint32_t count = 10;
+  /*
+  WA: few cycles for RX PMA descriptor to update
+  This workaround is ported from stm32h5xx_hal_pcd.h : PCD_GET_EP_RX_CNT H5
+  This code fixes an issue when the code is compiled in GCC with a fast optimization(O2/O3) and device with an high frequency.
+  The function doesn't return the correct value.
+  Issue observed on Windows 10 and stm32h573i_dk and tud_task() scheduled by IT, the device is not migrated the USB device is not visible .
+  */
+  while (count > 0U)
+  {
+    asm("NOP");
+    count--;
+  }
   return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
 #else
   __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
-- 
cgit v1.3.1


From f9c85ae47b0aacd6716b671a5b6ea289b43275c0 Mon Sep 17 00:00:00 2001
From: henneboi <william.hennebois@st.com>
Date: Wed, 6 Mar 2024 17:46:47 +0100
Subject: IAR Warning: Fixed due to an boolean operation between enum (Pa089)

Warning[Pa089]: enumerated type mixed with another enumerated type	...tusb_uac2_audio.c	199
This issue stops the build if we treat warning as error
---
 src/device/usbd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/device/usbd.h b/src/device/usbd.h
index 3ab6c813f..cf500143a 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -421,7 +421,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */
 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7
 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \
-  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
+  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_NO_SYNC | (uint8_t)TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
 
 // AUDIO simple descriptor (UAC2) for 1 microphone input
 // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source
-- 
cgit v1.3.1


From 9e674fa109348d97fb4280ac534be665f619a4d8 Mon Sep 17 00:00:00 2001
From: Tommie Gannert <tommie@gannert.se>
Date: Fri, 15 Mar 2024 15:02:13 +0100
Subject: [usbtmc] cast to uintptr_t to get rid of const for usbd_edpt_xfer.

---
 src/class/usbtmc/usbtmc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index debe445fd..4092c37ea 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -248,7 +248,7 @@ bool tud_usbtmc_transmit_notification_data(const void * data, size_t len)
 #endif
   if (usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in)) return false;
 
-  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, (void *)data, len));
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, (void *)(uintptr_t) data, len));
   return true;
 }
 
-- 
cgit v1.3.1


From 5d1f6934fbbeee3238267b0444172d47033a2fd9 Mon Sep 17 00:00:00 2001
From: Li Junru <lijunru@espressif.com>
Date: Thu, 14 Mar 2024 20:55:05 +0800
Subject: fix: uvc multiple interface support

1. fix next interface may have IAD_DESC
2. fix vs_itf can't be open on bulk mode.
---
 src/class/video/video_device.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index c33dfa0b0..249ced83d 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -207,6 +207,24 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des
   return cur;
 }
 
+/** Find the first descriptor of two given types
+ *
+ * @param[in] beg        The head of descriptor byte array.
+ * @param[in] end        The tail of descriptor byte array.
+ * @param[in] desc_type_0 The first target descriptor type.
+ * @param[in] desc_type_1 The second target descriptor type.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* _find_desc_2_type(void const *beg, void const *end, uint_fast8_t desc_type_0, uint_fast8_t desc_type_1)
+{
+  void const *cur = beg;
+  while ((cur < end) && (desc_type_0 != tu_desc_type(cur)) && (desc_type_1 != tu_desc_type(cur))) {
+    cur = tu_desc_next(cur);
+  }
+  return cur;
+}
+
 /** Find the first descriptor specified by the arguments
  *
  * @param[in] beg        The head of descriptor byte array.
@@ -233,6 +251,10 @@ static void const* _find_desc_3(void const *beg, void const *end,
 }
 
 /** Return the next interface descriptor which has another interface number.
+ *  If there are multiple VC interfaces, there will be an IAD descriptor before
+ *  the next interface descriptor. Check both the IAD descriptor and the interface
+ *  descriptor.
+ *  3.1 Descriptor Layout Overview
  *
  * @param[in] beg     The head of descriptor byte array.
  * @param[in] end     The tail of descriptor byte array.
@@ -245,7 +267,7 @@ static void const* _next_desc_itf(void const *beg, void const *end)
   uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
   while ((cur < end) &&
          (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) {
-    cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE);
+    cur = _find_desc_2_type(tu_desc_next(cur), end, TUSB_DESC_INTERFACE, TUSB_DESC_INTERFACE_ASSOCIATION);
   }
   return cur;
 }
@@ -1216,7 +1238,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
        * host may not issue set_interface so open the streaming interface here. */
       uint8_t const *sbeg = (uint8_t const*)itf_desc + stm->desc.beg;
       uint8_t const *send = (uint8_t const*)itf_desc + stm->desc.end;
-      if (end == _find_desc_itf(sbeg, send, _desc_itfnum(sbeg), 1)) {
+      if (send == _find_desc_itf(sbeg, send, _desc_itfnum(sbeg), 1)) {
         TU_VERIFY(_open_vs_itf(rhport, stm, 0), 0);
       }
     }
-- 
cgit v1.3.1


From 6352081ded448ef64d5d3285dafab684d14fd649 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 15 Mar 2024 17:58:27 +0700
Subject: code format

---
 src/tusb.c | 248 +++++++++++++++++++++++--------------------------------------
 1 file changed, 93 insertions(+), 155 deletions(-)

(limited to 'src')

diff --git a/src/tusb.c b/src/tusb.c
index 7c86f1ca5..ccb2a44bf 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -43,8 +43,7 @@
 // Public API
 //--------------------------------------------------------------------+
 
-bool tusb_init(void)
-{
+bool tusb_init(void) {
 #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
   // init device stack CFG_TUSB_RHPORTx_MODE must be defined
   TU_ASSERT ( tud_init(TUD_OPT_RHPORT) );
@@ -58,8 +57,7 @@ bool tusb_init(void)
   return true;
 }
 
-bool tusb_inited(void)
-{
+bool tusb_inited(void) {
   bool ret = false;
 
 #if CFG_TUD_ENABLED
@@ -77,37 +75,30 @@ bool tusb_inited(void)
 // Descriptor helper
 //--------------------------------------------------------------------+
 
-uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1)
-{
-  while(desc+1 < end)
-  {
-    if ( desc[1] == byte1 ) return desc;
+uint8_t const* tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) {
+  while (desc + 1 < end) {
+    if (desc[1] == byte1) return desc;
     desc += desc[DESC_OFFSET_LEN];
   }
   return NULL;
 }
 
-uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2)
-{
-  while(desc+2 < end)
-  {
-    if ( desc[1] == byte1 && desc[2] == byte2) return desc;
+uint8_t const* tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) {
+  while (desc + 2 < end) {
+    if (desc[1] == byte1 && desc[2] == byte2) return desc;
     desc += desc[DESC_OFFSET_LEN];
   }
   return NULL;
 }
 
-uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3)
-{
-  while(desc+3 < end)
-  {
+uint8_t const* tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) {
+  while (desc + 3 < end) {
     if (desc[1] == byte1 && desc[2] == byte2 && desc[3] == byte3) return desc;
     desc += desc[DESC_OFFSET_LEN];
   }
   return NULL;
 }
 
-
 //--------------------------------------------------------------------+
 // Endpoint Helper for both Host and Device stack
 //--------------------------------------------------------------------+
@@ -126,13 +117,11 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   }
 
   (void) osal_mutex_unlock(mutex);
-
   return available;
 }
 
 bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   (void) mutex;
-
   (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   // can only release the endpoint if it is claimed and not busy
@@ -142,58 +131,49 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   }
 
   (void) osal_mutex_unlock(mutex);
-
   return ret;
 }
 
-bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
-{
+bool tu_edpt_validate(tusb_desc_endpoint_t const* desc_ep, tusb_speed_t speed) {
   uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep);
   TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
 
-  switch (desc_ep->bmAttributes.xfer)
-  {
-    case TUSB_XFER_ISOCHRONOUS:
-    {
+  switch (desc_ep->bmAttributes.xfer) {
+    case TUSB_XFER_ISOCHRONOUS: {
       uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023);
       TU_ASSERT(max_packet_size <= spec_size);
+      break;
     }
-    break;
 
     case TUSB_XFER_BULK:
-      if (speed == TUSB_SPEED_HIGH)
-      {
+      if (speed == TUSB_SPEED_HIGH) {
         // Bulk highspeed must be EXACTLY 512
         TU_ASSERT(max_packet_size == 512);
-      }else
-      {
+      } else {
         // TODO Bulk fullspeed can only be 8, 16, 32, 64
         TU_ASSERT(max_packet_size <= 64);
       }
-    break;
+      break;
 
-    case TUSB_XFER_INTERRUPT:
-    {
+    case TUSB_XFER_INTERRUPT: {
       uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64);
       TU_ASSERT(max_packet_size <= spec_size);
+      break;
     }
-    break;
 
-    default: return false;
+    default:
+      return false;
   }
 
   return true;
 }
 
-void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id)
-{
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id) {
   uint8_t const* p_desc = (uint8_t const*) desc_itf;
   uint8_t const* desc_end = p_desc + desc_len;
 
-  while( p_desc < desc_end )
-  {
-    if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-    {
+  while (p_desc < desc_end) {
+    if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) {
       uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
 
       TU_LOG(2, "  Bind EP %02x to driver id %u\r\n", ep_addr, driver_id);
@@ -204,25 +184,21 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_
   }
 }
 
-uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
-{
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) {
   uint8_t const* p_desc = (uint8_t const*) desc_itf;
   uint16_t len = 0;
 
-  while (itf_count--)
-  {
+  while (itf_count--) {
     // Next on interface desc
     len += tu_desc_len(desc_itf);
     p_desc = tu_desc_next(p_desc);
 
-    while (len < max_len)
-    {
+    while (len < max_len) {
       // return on IAD regardless of itf count
-      if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
+      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) return len;
 
-      if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
-           ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 )
-      {
+      if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
+          ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0) {
         break;
       }
 
@@ -239,8 +215,7 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
 //--------------------------------------------------------------------+
 
 bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
-                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize)
-{
+                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) {
   osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex);
   (void) new_mutex;
   (void) is_tx;
@@ -255,16 +230,12 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline
-bool stream_claim(tu_edpt_stream_t* s)
-{
-  if (s->is_host)
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool stream_claim(tu_edpt_stream_t* s) {
+  if (s->is_host) {
     #if CFG_TUH_ENABLED
     return usbh_edpt_claim(s->daddr, s->ep_addr);
     #endif
-  }else
-  {
+  } else {
     #if CFG_TUD_ENABLED
     return usbd_edpt_claim(s->rhport, s->ep_addr);
     #endif
@@ -273,16 +244,12 @@ bool stream_claim(tu_edpt_stream_t* s)
   return false;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline
-bool stream_xfer(tu_edpt_stream_t* s, uint16_t count)
-{
-  if (s->is_host)
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) {
+  if (s->is_host) {
     #if CFG_TUH_ENABLED
     return usbh_edpt_xfer(s->daddr, s->ep_addr, count ? s->ep_buf : NULL, count);
     #endif
-  }else
-  {
+  } else {
     #if CFG_TUD_ENABLED
     return usbd_edpt_xfer(s->rhport, s->ep_addr, count ? s->ep_buf : NULL, count);
     #endif
@@ -291,16 +258,12 @@ bool stream_xfer(tu_edpt_stream_t* s, uint16_t count)
   return false;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline
-bool stream_release(tu_edpt_stream_t* s)
-{
-  if (s->is_host)
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool stream_release(tu_edpt_stream_t* s) {
+  if (s->is_host) {
     #if CFG_TUH_ENABLED
     return usbh_edpt_release(s->daddr, s->ep_addr);
     #endif
-  }else
-  {
+  } else {
     #if CFG_TUD_ENABLED
     return usbd_edpt_release(s->rhport, s->ep_addr);
     #endif
@@ -313,34 +276,29 @@ bool stream_release(tu_edpt_stream_t* s)
 // Stream Write
 //--------------------------------------------------------------------+
 
-bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes)
-{
+bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) {
   // ZLP condition: no pending data, last transferred bytes is multiple of packet size
-  TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) );
-
-  TU_VERIFY( stream_claim(s) );
-  TU_ASSERT( stream_xfer(s, 0) );
+  TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize - 1))));
+  TU_VERIFY(stream_claim(s));
+  TU_ASSERT(stream_xfer(s, 0));
 
   return true;
 }
 
-uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
-{
+uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) {
   // skip if no data
-  TU_VERIFY( tu_fifo_count(&s->ff), 0 );
+  TU_VERIFY(tu_fifo_count(&s->ff), 0);
 
   // Claim the endpoint
-  TU_VERIFY( stream_claim(s), 0 );
+  TU_VERIFY(stream_claim(s), 0);
 
   // Pull data from FIFO -> EP buf
   uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
 
-  if ( count )
-  {
-    TU_ASSERT( stream_xfer(s, count), 0 );
+  if (count) {
+    TU_ASSERT(stream_xfer(s, count), 0);
     return count;
-  }else
-  {
+  } else {
     // Release endpoint since we don't make any transfer
     // Note: data is dropped if terminal is not connected
     stream_release(s);
@@ -348,16 +306,14 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
   }
 }
 
-uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize)
-{
+uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const* buffer, uint32_t bufsize) {
   TU_VERIFY(bufsize); // TODO support ZLP
 
   uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
 
   // flush if fifo has more than packet size or
   // in rare case: fifo depth is configured too small (which never reach packet size)
-  if ( (tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize) )
-  {
+  if ((tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize)) {
     tu_edpt_stream_write_xfer(s);
   }
 
@@ -368,8 +324,7 @@ uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t
 // Stream Read
 //--------------------------------------------------------------------+
 
-uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
-{
+uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) {
   uint16_t available = tu_fifo_remaining(&s->ff);
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
@@ -384,25 +339,20 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
   // get available again since fifo can be changed before endpoint is claimed
   available = tu_fifo_remaining(&s->ff);
 
-  if ( available >= s->ep_packetsize )
-  {
+  if (available >= s->ep_packetsize) {
     // multiple of packet size limit by ep bufsize
-    uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1));
+    uint16_t count = (uint16_t) (available & ~(s->ep_packetsize - 1));
     count = tu_min16(count, s->ep_bufsize);
-
-    TU_ASSERT( stream_xfer(s, count), 0 );
-
+    TU_ASSERT(stream_xfer(s, count), 0);
     return count;
-  }else
-  {
+  } else {
     // Release endpoint since we don't make any transfer
     stream_release(s);
     return 0;
   }
 }
 
-uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize)
-{
+uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) {
   uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize);
   tu_edpt_stream_read_xfer(s);
   return num_read;
@@ -416,38 +366,33 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize
 #include <ctype.h>
 
 #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
-
-char const* const tu_str_speed[] = { "Full", "Low", "High" };
-char const* const tu_str_std_request[] =
-{
-  "Get Status"        ,
-  "Clear Feature"     ,
-  "Reserved"          ,
-  "Set Feature"       ,
-  "Reserved"          ,
-  "Set Address"       ,
-  "Get Descriptor"    ,
-  "Set Descriptor"    ,
-  "Get Configuration" ,
-  "Set Configuration" ,
-  "Get Interface"     ,
-  "Set Interface"     ,
-  "Synch Frame"
+char const* const tu_str_speed[] = {"Full", "Low", "High"};
+char const* const tu_str_std_request[] = {
+    "Get Status",
+    "Clear Feature",
+    "Reserved",
+    "Set Feature",
+    "Reserved",
+    "Set Address",
+    "Get Descriptor",
+    "Set Descriptor",
+    "Get Configuration",
+    "Set Configuration",
+    "Get Interface",
+    "Set Interface",
+    "Synch Frame"
 };
 
 char const* const tu_str_xfer_result[] = {
     "OK", "FAILED", "STALLED", "TIMEOUT"
 };
-
 #endif
 
-static void dump_str_line(uint8_t const* buf, uint16_t count)
-{
+static void dump_str_line(uint8_t const* buf, uint16_t count) {
   tu_printf("  |");
 
   // each line is 16 bytes
-  for(uint16_t i=0; i<count; i++)
-  {
+  for (uint16_t i = 0; i < count; i++) {
     const char ch = buf[i];
     tu_printf("%c", isprint(ch) ? ch : '.');
   }
@@ -460,39 +405,34 @@ static void dump_str_line(uint8_t const* buf, uint16_t count)
  *  - count : number of item
  *  - indent: prefix spaces on every line
  */
-void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
-{
+void tu_print_mem(void const* buf, uint32_t count, uint8_t indent) {
   uint8_t const size = 1; // fixed 1 byte for now
 
-  if ( !buf || !count )
-  {
+  if (!buf || !count) {
     tu_printf("NULL\r\n");
     return;
   }
 
-  uint8_t const *buf8 = (uint8_t const *) buf;
+  uint8_t const* buf8 = (uint8_t const*) buf;
 
   char format[] = "%00X";
-  format[2] += (uint8_t) (2*size); // 1 byte = 2 hex digits
+  format[2] += (uint8_t) (2 * size); // 1 byte = 2 hex digits
 
-  const uint8_t item_per_line  = 16 / size;
+  const uint8_t item_per_line = 16 / size;
 
-  for(unsigned int i=0; i<count; i++)
-  {
-    unsigned int value=0;
+  for (unsigned int i = 0; i < count; i++) {
+    unsigned int value = 0;
 
-    if ( i%item_per_line == 0 )
-    {
+    if (i % item_per_line == 0) {
       // Print Ascii
-      if ( i != 0 )
-      {
-        dump_str_line(buf8-16, 16);
+      if (i != 0) {
+        dump_str_line(buf8 - 16, 16);
       }
 
-      for(uint8_t s=0; s < indent; s++) tu_printf(" ");
+      for (uint8_t s = 0; s < indent; s++) tu_printf(" ");
 
       // print offset or absolute address
-      tu_printf("%04X: ", 16*i/item_per_line);
+      tu_printf("%04X: ", 16 * i / item_per_line);
     }
 
     tu_memcpy_s(&value, sizeof(value), buf8, size);
@@ -503,19 +443,17 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
   }
 
   // fill up last row to 16 for printing ascii
-  const uint32_t remain = count%16;
-  uint8_t nback = (uint8_t)(remain ? remain : 16);
+  const uint32_t remain = count % 16;
+  uint8_t nback = (uint8_t) (remain ? remain : 16);
 
-  if ( remain )
-  {
-    for(uint32_t i=0; i< 16-remain; i++)
-    {
+  if (remain) {
+    for (uint32_t i = 0; i < 16 - remain; i++) {
       tu_printf(" ");
-      for(int j=0; j<2*size; j++) tu_printf(" ");
+      for (int j = 0; j < 2 * size; j++) tu_printf(" ");
     }
   }
 
-  dump_str_line(buf8-nback, nback);
+  dump_str_line(buf8 - nback, nback);
 }
 
 #endif
-- 
cgit v1.3.1


From 5630030a22cc850672c62bfe3a12c0054a7f84a2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 15 Mar 2024 20:39:45 +0700
Subject: improve uvc debug message

---
 src/class/video/video.h               |  23 ++--
 src/class/video/video_device.c        | 223 ++++++++++++++++++++++------------
 src/device/usbd.c                     |   2 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c |   4 +-
 4 files changed, 157 insertions(+), 95 deletions(-)

(limited to 'src')

diff --git a/src/class/video/video.h b/src/class/video/video.h
index abf1e34b9..b8a9b6369 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -160,22 +160,23 @@ typedef enum {
 /* A.9.1 VideoControl Interface Control Selectors */
 typedef enum {
   VIDEO_VC_CTL_UNDEFINED = 0x00,
-  VIDEO_VC_CTL_VIDEO_POWER_MODE,
-  VIDEO_VC_CTL_REQUEST_ERROR_CODE,
+  VIDEO_VC_CTL_VIDEO_POWER_MODE,   // 0x01
+  VIDEO_VC_CTL_REQUEST_ERROR_CODE, // 0x02
 } video_interface_control_selector_t;
 
 /* A.9.8 VideoStreaming Interface Control Selectors */
 typedef enum {
   VIDEO_VS_CTL_UNDEFINED = 0x00,
-  VIDEO_VS_CTL_PROBE,
-  VIDEO_VS_CTL_COMMIT,
-  VIDEO_VS_CTL_STILL_PROBE,
-  VIDEO_VS_CTL_STILL_COMMIT,
-  VIDEO_VS_CTL_STILL_IMAGE_TRIGGER,
-  VIDEO_VS_CTL_STREAM_ERROR_CODE,
-  VIDEO_VS_CTL_GENERATE_KEY_FRAME,
-  VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT,
-  VIDEO_VS_CTL_SYNCH_DELAY_CONTROL,
+  VIDEO_VS_CTL_PROBE,                // 0x01
+  VIDEO_VS_CTL_COMMIT,               // 0x02
+  VIDEO_VS_CTL_STILL_PROBE,          // 0x03
+  VIDEO_VS_CTL_STILL_COMMIT,         // 0x04
+  VIDEO_VS_CTL_STILL_IMAGE_TRIGGER,  // 0x05
+  VIDEO_VS_CTL_STREAM_ERROR_CODE,    // 0x06
+  VIDEO_VS_CTL_GENERATE_KEY_FRAME,   // 0x07
+  VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT, // 0x08
+  VIDEO_VS_CTL_SYNCH_DELAY_CONTROL,  // 0x09
+
 } video_interface_streaming_selector_t;
 
 /* B. Terminal Types */
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 249ced83d..dc3f8d897 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -143,13 +143,65 @@ CFG_TUD_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf
 tu_static uint8_t const _cap_get     = 0x1u; /* support for GET */
 tu_static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
 
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
+#if CFG_TUSB_DEBUG >= CFG_TUD_VIDEO_LOG_LEVEL
+
+static tu_lookup_entry_t const tu_lookup_video_request[] = {
+    {.key = VIDEO_REQUEST_UNDEFINED, .data = "Undefined"},
+    {.key = VIDEO_REQUEST_SET_CUR, .data = "SetCur"},
+    {.key = VIDEO_REQUEST_SET_CUR_ALL, .data = "SetCurAll"},
+    {.key = VIDEO_REQUEST_GET_CUR, .data = "GetCur"},
+    {.key = VIDEO_REQUEST_GET_MIN, .data = "GetMin"},
+    {.key = VIDEO_REQUEST_GET_MAX, .data = "GetMax"},
+    {.key = VIDEO_REQUEST_GET_RES, .data = "GetRes"},
+    {.key = VIDEO_REQUEST_GET_LEN, .data = "GetLen"},
+    {.key = VIDEO_REQUEST_GET_INFO, .data = "GetInfo"},
+    {.key = VIDEO_REQUEST_GET_DEF, .data = "GetDef"},
+    {.key = VIDEO_REQUEST_GET_CUR_ALL, .data = "GetCurAll"},
+    {.key = VIDEO_REQUEST_GET_MIN_ALL, .data = "GetMinAll"},
+    {.key = VIDEO_REQUEST_GET_MAX_ALL, .data = "GetMaxAll"},
+    {.key = VIDEO_REQUEST_GET_RES_ALL, .data = "GetResAll"},
+    {.key = VIDEO_REQUEST_GET_DEF_ALL, .data = "GetDefAll"},
+};
+
+static tu_lookup_table_t const tu_table_video_request = {
+    .count = TU_ARRAY_SIZE(tu_lookup_video_request),
+    .items = tu_lookup_video_request
+};
+
+static char const* const tu_str_video_vc_control_selector[] = {
+    "Undefined",
+    "Video Power Mode",
+    "Request Error Code",
+};
+
+static char const* const tu_str_video_vs_control_selector[] = {
+    "Undefined",
+    "Probe",
+    "Commit",
+    "Still Probe",
+    "Still Commit",
+    "Still Image Trigger",
+    "Stream Error Code",
+    "Generate Key Frame",
+    "Update Frame Segment",
+    "Sync Delay",
+};
+
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 /** Get interface number from the interface descriptor
  *
  * @param[in] desc    interface descriptor
  *
  * @return bInterfaceNumber */
-static inline uint8_t _desc_itfnum(void const *desc)
-{
+static inline uint8_t _desc_itfnum(void const *desc) {
   return ((uint8_t const*)desc)[2];
 }
 
@@ -158,8 +210,7 @@ static inline uint8_t _desc_itfnum(void const *desc)
  * @param[in] desc    endpoint descriptor
  *
  * @return bEndpointAddress */
-static inline uint8_t _desc_ep_addr(void const *desc)
-{
+static inline uint8_t _desc_ep_addr(void const *desc) {
   return ((uint8_t const*)desc)[2];
 }
 
@@ -169,8 +220,7 @@ static inline uint8_t _desc_ep_addr(void const *desc)
  * @param[in] stm_idx    index number of streaming interface
  *
  * @return instance */
-static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
-{
+static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx) {
   videod_interface_t *ctl = &_videod_itf[ctl_idx];
   if (!ctl->beg) return NULL;
   videod_streaming_interface_t *stm = &_videod_streaming_itf[ctl->stm[stm_idx]];
@@ -178,13 +228,11 @@ static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_id
   return stm;
 }
 
-static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
-{
+static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self) {
   return (tusb_desc_vc_itf_t const *)(self->beg + self->cur);
 }
 
-static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self)
-{
+static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self) {
   if (!self->desc.cur) return NULL;
   uint8_t const *desc = _videod_itf[self->index_vc].beg;
   return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur);
@@ -198,8 +246,7 @@ static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type)
-{
+static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type) {
   void const *cur = beg;
   while ((cur < end) && (desc_type != tu_desc_type(cur))) {
     cur = tu_desc_next(cur);
@@ -238,8 +285,7 @@ static void const* _find_desc_2_type(void const *beg, void const *end, uint_fast
 static void const* _find_desc_3(void const *beg, void const *end,
                                 uint_fast8_t desc_type,
                                 uint_fast8_t element_0,
-                                uint_fast8_t element_1)
-{
+                                uint_fast8_t element_1) {
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) {
     uint8_t const *p = (uint8_t const *)cur;
     if ((p[2] == element_0) && (p[3] == element_1)) {
@@ -261,8 +307,7 @@ static void const* _find_desc_3(void const *beg, void const *end,
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _next_desc_itf(void const *beg, void const *end)
-{
+static void const* _next_desc_itf(void const *beg, void const *end) {
   void const *cur = beg;
   uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
   while ((cur < end) &&
@@ -413,8 +458,10 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
     case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
       param->wCompQuality = 1; /* 1 to 10000 */
       break;
-  case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
+
+    case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
       break;
+
     default: return false;
   }
 
@@ -435,9 +482,11 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
       case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8;
         break;
+
       case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
         break;
+
       default: break;
     }
     param->dwMaxVideoFrameSize = frame_size;
@@ -478,10 +527,12 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
         if (_get_desc_vs(stm))
           param->bFormatIndex = _get_desc_vs(stm)->stm.bNumFormats;
         break;
+
       case VIDEO_REQUEST_GET_MIN:
       case VIDEO_REQUEST_GET_DEF:
         param->bFormatIndex = 1;
         break;
+
       default: return false;
     }
     /* Set the parameters determined by the format  */
@@ -510,18 +561,22 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       case VIDEO_REQUEST_GET_MAX:
         frmnum = fmt->bNumFrameDescriptors;
         break;
+
       case VIDEO_REQUEST_GET_MIN:
         frmnum = 1;
         break;
+
       case VIDEO_REQUEST_GET_DEF:
         switch (fmt->bDescriptorSubType) {
-        case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
-          frmnum = fmt->uncompressed.bDefaultFrameIndex;
-          break;
-        case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
-          frmnum = fmt->mjpeg.bDefaultFrameIndex;
-          break;
-        default: return false;
+          case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
+            frmnum = fmt->uncompressed.bDefaultFrameIndex;
+            break;
+
+          case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
+            frmnum = fmt->mjpeg.bDefaultFrameIndex;
+            break;
+
+          default: return false;
         }
         break;
       default: return false;
@@ -534,9 +589,11 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8;
         break;
+
       case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
         frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
         break;
+
       default: return false;
     }
     param->dwMaxVideoFrameSize = frame_size;
@@ -552,42 +609,43 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
 
     uint_fast32_t interval, interval_ms;
     switch (request) {
-      case VIDEO_REQUEST_GET_MAX:
-        {
-          uint_fast32_t min_interval, max_interval;
-          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
-          max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
-          min_interval = frm->uncompressed.dwFrameInterval[0];
-          interval = max_interval;
-          interval_ms = min_interval / 10000;
-        }
+      case VIDEO_REQUEST_GET_MAX: {
+        uint_fast32_t min_interval, max_interval;
+        uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+        max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
+        min_interval = frm->uncompressed.dwFrameInterval[0];
+        interval = max_interval;
+        interval_ms = min_interval / 10000;
         break;
-      case VIDEO_REQUEST_GET_MIN:
-        {
-          uint_fast32_t min_interval, max_interval;
-          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
-          max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
-          min_interval = frm->uncompressed.dwFrameInterval[0];
-          interval = min_interval;
-          interval_ms = max_interval / 10000;
-        }
+      }
+
+      case VIDEO_REQUEST_GET_MIN: {
+        uint_fast32_t min_interval, max_interval;
+        uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+        max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
+        min_interval = frm->uncompressed.dwFrameInterval[0];
+        interval = min_interval;
+        interval_ms = max_interval / 10000;
         break;
+      }
+
       case VIDEO_REQUEST_GET_DEF:
         interval = frm->uncompressed.dwDefaultFrameInterval;
         interval_ms = interval / 10000;
         break;
-      case VIDEO_REQUEST_GET_RES:
-        {
-          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
-          if (num_intervals) {
-            interval = 0;
-            interval_ms = 0;
-          } else {
-            interval = frm->uncompressed.dwFrameInterval[2];
-            interval_ms = interval / 10000;
-          }
+
+      case VIDEO_REQUEST_GET_RES: {
+        uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+        if (num_intervals) {
+          interval = 0;
+          interval_ms = 0;
+        } else {
+          interval = frm->uncompressed.dwFrameInterval[2];
+          interval_ms = interval / 10000;
         }
         break;
+      }
+
       default: return false;
     }
     param->dwFrameInterval = interval;
@@ -681,8 +739,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm)
   /* initialize streaming settings */
   stm->state = VS_STATE_PROBING;
   stm->max_payload_transfer_size = 0;
-  video_probe_and_commit_control_t *param =
-    (video_probe_and_commit_control_t *)&stm->ep_buf;
+  video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t *)&stm->ep_buf;
   tu_memclr(param, sizeof(*param));
   return _update_streaming_parameters(stm, param);
 }
@@ -760,6 +817,10 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm)
     pkt_len = hdr_len + remaining;
   }
   uint_fast16_t data_len = pkt_len - hdr_len;
+  TU_LOG2("    prepare remain = %u, hdr_len = %u, pkt_len = %u, offset = %lu, data_len = %u\r\n", remaining, hdr_len, pkt_len, stm->offset, data_len);
+  if ( data_len > sizeof(stm->ep_buf) ) {
+    TU_BREAKPOINT();
+  }
   memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len);
   stm->offset += data_len;
   remaining -= data_len;
@@ -775,6 +836,7 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage,
                                     tusb_control_request_t const *request,
                                     uint_fast8_t ctl_idx)
 {
+  TU_LOG_DRV("\r\n");
   switch (request->bRequest) {
     case TUSB_REQ_GET_INTERFACE:
       if (stage == CONTROL_STAGE_SETUP)
@@ -812,7 +874,10 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
   videod_interface_t *self = &_videod_itf[ctl_idx];
 
   /* 4.2.1 Interface Control Request */
-  switch (TU_U16_HIGH(request->wValue)) {
+  uint8_t const ctrl_sel = TU_U16_HIGH(request->wValue);
+  TU_LOG_DRV("%s_Control(%s)\r\n",  tu_str_video_vc_control_selector[ctrl_sel], tu_lookup_find(&tu_table_video_request, request->bRequest));
+
+  switch (ctrl_sel) {
     case VIDEO_VC_CTL_VIDEO_POWER_MODE:
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
@@ -876,19 +941,19 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage,
                                 tusb_control_request_t const *request,
                                 uint_fast8_t ctl_idx)
 {
-  uint_fast8_t entity_id;
   switch (request->bmRequestType_bit.type) {
     case TUSB_REQ_TYPE_STANDARD:
       return handle_video_ctl_std_req(rhport, stage, request, ctl_idx);
 
-    case TUSB_REQ_TYPE_CLASS:
-      entity_id = TU_U16_HIGH(request->wIndex);
+    case TUSB_REQ_TYPE_CLASS: {
+      uint_fast8_t entity_id = TU_U16_HIGH(request->wIndex);
       if (!entity_id) {
         return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx);
       } else {
         TU_VERIFY(_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id), VIDEO_ERROR_INVALID_REQUEST);
         return VIDEO_ERROR_NONE;
       }
+    }
 
     default:
       return VIDEO_ERROR_INVALID_REQUEST;
@@ -899,6 +964,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
                                     tusb_control_request_t const *request,
                                     uint_fast8_t stm_idx)
 {
+  TU_LOG_DRV("\r\n");
   videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
   switch (request->bRequest) {
     case TUSB_REQ_GET_INTERFACE:
@@ -914,8 +980,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
       return VIDEO_ERROR_NONE;
 
     case TUSB_REQ_SET_INTERFACE:
-      if (stage == CONTROL_STAGE_SETUP)
-      {
+      if (stage == CONTROL_STAGE_SETUP) {
         TU_VERIFY(_open_vs_itf(rhport, self, request->wValue), VIDEO_ERROR_UNKNOWN);
         tud_control_status(rhport, request);
       }
@@ -929,26 +994,26 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
 
 static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
                                    tusb_control_request_t const *request,
-                                   uint_fast8_t stm_idx)
-{
+                                   uint_fast8_t stm_idx) {
   (void)rhport;
   videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
 
+  uint8_t const ctrl_sel = TU_U16_HIGH(request->wValue);
+  TU_LOG_DRV("%s_Control(%s)\r\n", tu_str_video_vs_control_selector[ctrl_sel], tu_lookup_find(&tu_table_video_request, request->bRequest));
+
   /* 4.2.1 Interface Control Request */
-  switch (TU_U16_HIGH(request->wValue)) {
+  switch (ctrl_sel) {
     case VIDEO_VS_CTL_STREAM_ERROR_CODE:
       switch (request->bRequest) {
         case VIDEO_REQUEST_GET_CUR:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             /* TODO */
             TU_VERIFY(tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_INFO:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
@@ -962,6 +1027,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         self->state = VS_STATE_PROBING;
         _init_vs_configuration(self);
       }
+
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
@@ -975,8 +1041,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_CUR:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
@@ -986,8 +1051,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         case VIDEO_REQUEST_GET_MAX:
         case VIDEO_REQUEST_GET_RES:
         case VIDEO_REQUEST_GET_DEF:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
             video_probe_and_commit_control_t tmp;
             tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
@@ -997,8 +1061,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_LEN:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN);
             uint16_t len = sizeof(video_probe_and_commit_control_t);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN);
@@ -1006,8 +1069,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_INFO:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
@@ -1046,16 +1108,14 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_CUR:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_LEN:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN);
             uint16_t len = sizeof(video_probe_and_commit_control_t);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN);
@@ -1063,8 +1123,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_INFO:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
+          if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
@@ -1264,6 +1323,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   }
 
   if (itf < CFG_TUD_VIDEO) {
+    TU_LOG_DRV("  VC[%d]: ", itf);
     err = handle_video_ctl_req(rhport, stage, request, itf);
     _videod_itf[itf].error_code = (uint8_t)err;
     if (err) return false;
@@ -1279,6 +1339,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   }
 
   if (itf < CFG_TUD_VIDEO_STREAMING) {
+    TU_LOG_DRV("  VS[%d]: ", itf);
     err = handle_video_stm_req(rhport, stage, request, itf);
     _videod_streaming_itf[itf].error_code = (uint8_t)err;
     if (err) return false;
diff --git a/src/device/usbd.c b/src/device/usbd.c
index ab572e095..96d0b698b 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -319,7 +319,7 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) {
   for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
     usbd_class_driver_t const* driver = get_driver(i);
     if (driver && driver->control_xfer_cb == callback) {
-      TU_LOG_USBD("  %s control complete\r\n", driver->name);
+      TU_LOG_USBD("%s control complete\r\n", driver->name);
       return;
     }
   }
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 841cda752..80a285ef0 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -246,7 +246,7 @@ static void xact_in_dma(uint8_t epnum)
 //--------------------------------------------------------------------+
 void dcd_init (uint8_t rhport)
 {
-  TU_LOG1("dcd init\r\n");
+  TU_LOG2("dcd init\r\n");
   (void) rhport;
 }
 
@@ -685,7 +685,7 @@ void dcd_int_handler(uint8_t rhport)
 
   if ( int_status & USBD_INTEN_USBEVENT_Msk )
   {
-    TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
+    TU_LOG(3, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
 
     enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk };
     uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
-- 
cgit v1.3.1


From ff12544c9ac1f61c5d25d58608f16f5991e9f776 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 20 Mar 2024 22:45:46 +0700
Subject: added dedicate buffer for probe commit payload

---
 src/class/video/video_device.c | 45 ++++++++++++++++--------------------------
 1 file changed, 17 insertions(+), 28 deletions(-)

(limited to 'src')

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index dc3f8d897..5306356ba 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -114,6 +114,8 @@ typedef struct TU_ATTR_PACKED {
   uint32_t max_payload_transfer_size;
   uint8_t  error_code;/* error code */
   uint8_t  state;    /* 0:probing 1:committed 2:streaming */
+
+  video_probe_and_commit_control_t probe_commit_payload; /* Probe and Commit control */
   /*------------- From this point, data is not cleared by bus reset -------------*/
   CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */
 } videod_streaming_interface_t;
@@ -734,12 +736,11 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   return true;
 }
 
-static bool _init_vs_configuration(videod_streaming_interface_t *stm)
-{
+static bool _init_vs_configuration(videod_streaming_interface_t *stm) {
   /* initialize streaming settings */
   stm->state = VS_STATE_PROBING;
   stm->max_payload_transfer_size = 0;
-  video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t *)&stm->ep_buf;
+  video_probe_and_commit_control_t *param = &stm->probe_commit_payload;
   tu_memclr(param, sizeof(*param));
   return _update_streaming_parameters(stm, param);
 }
@@ -816,11 +817,8 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm)
   if (hdr_len + remaining < pkt_len) {
     pkt_len = hdr_len + remaining;
   }
+  TU_ASSERT(pkt_len >= hdr_len);
   uint_fast16_t data_len = pkt_len - hdr_len;
-  TU_LOG2("    prepare remain = %u, hdr_len = %u, pkt_len = %u, offset = %lu, data_len = %u\r\n", remaining, hdr_len, pkt_len, stm->offset, data_len);
-  if ( data_len > sizeof(stm->ep_buf) ) {
-    TU_BREAKPOINT();
-  }
   memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len);
   stm->offset += data_len;
   remaining -= data_len;
@@ -1025,17 +1023,15 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
     case VIDEO_VS_CTL_PROBE:
       if (self->state != VS_STATE_PROBING) {
         self->state = VS_STATE_PROBING;
-        _init_vs_configuration(self);
       }
 
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
-            TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)),
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)),
                       VIDEO_ERROR_UNKNOWN);
           } else if (stage == CONTROL_STAGE_DATA) {
-            TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf),
+            TU_VERIFY(_update_streaming_parameters(self, &self->probe_commit_payload),
                       VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
           }
           return VIDEO_ERROR_NONE;
@@ -1043,7 +1039,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         case VIDEO_REQUEST_GET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -1053,8 +1049,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         case VIDEO_REQUEST_GET_DEF:
           if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-            video_probe_and_commit_control_t tmp;
-            tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
+            video_probe_and_commit_control_t tmp = self->probe_commit_payload;
             TU_VERIFY(_negotiate_streaming_parameters(self, request->bRequest, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(tmp)), VIDEO_ERROR_UNKNOWN);
           }
@@ -1083,10 +1078,9 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
-            TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           } else if (stage == CONTROL_STAGE_DATA) {
-            video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t*)self->ep_buf;
+            video_probe_and_commit_control_t *param = &self->probe_commit_payload;
             TU_VERIFY(_update_streaming_parameters(self, param), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             /* Set the negotiated value */
             self->max_payload_transfer_size = param->dwMaxPayloadTransferSize;
@@ -1110,7 +1104,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         case VIDEO_REQUEST_GET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->probe_commit_payload, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -1224,8 +1218,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void videod_init(void)
-{
+void videod_init(void) {
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) {
     videod_interface_t* ctl = &_videod_itf[i];
     tu_memclr(ctl, sizeof(*ctl));
@@ -1236,8 +1229,7 @@ void videod_init(void)
   }
 }
 
-void videod_reset(uint8_t rhport)
-{
+void videod_reset(uint8_t rhport) {
   (void) rhport;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) {
     videod_interface_t* ctl = &_videod_itf[i];
@@ -1249,8 +1241,7 @@ void videod_reset(uint8_t rhport)
   }
 }
 
-uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
-{
+uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) {
   TU_VERIFY((TUSB_CLASS_VIDEO       == itf_desc->bInterfaceClass) &&
             (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) &&
             (VIDEO_ITF_PROTOCOL_15  == itf_desc->bInterfaceProtocol), 0);
@@ -1309,8 +1300,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
-{
+bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) {
   int err;
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
   uint_fast8_t itfnum = tu_u16_low(request->wIndex);
@@ -1348,8 +1338,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   return false;
 }
 
-bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void)result; (void)xferred_bytes;
 
   /* find streaming handle */
-- 
cgit v1.3.1


From 61a31db8ecf66460e4888aef7915da66d98964d0 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 20 Mar 2024 15:20:24 -0700
Subject: Tweaks for ESP-IDF 5.2.1

---
 src/portable/espressif/esp32sx/dcd_esp32sx.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index 1fcfb6241..bfc0baa56 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -31,16 +31,26 @@
 #if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) ||  (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && CFG_TUD_ENABLED)
 
 // Espressif
-#include "freertos/xtensa_api.h"
+#include "xtensa_api.h"
 #include "esp_intr_alloc.h"
 #include "esp_log.h"
 #include "soc/dport_reg.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/usb_periph.h"
+#include "soc/usb_reg.h"
+#include "soc/usb_struct.h"
 #include "soc/periph_defs.h" // for interrupt source
 
 #include "device/dcd.h"
 
+#ifndef USB_OUT_EP_NUM
+#define USB_OUT_EP_NUM ((int) (sizeof(USB0.out_ep_reg) / sizeof(USB0.out_ep_reg[0])))
+#endif
+
+#ifndef USB_IN_EP_NUM
+#define USB_IN_EP_NUM ((int) (sizeof(USB0.in_ep_reg) / sizeof(USB0.in_ep_reg[0])))
+#endif
+
 // Max number of bi-directional endpoints including EP0
 // Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0
 // We should probably prohibit enabling Endpoint IN > 4 (not done yet)
-- 
cgit v1.3.1


From 74bd2647589790b3bee49146774133c2061a34fe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Mar 2024 11:42:33 +0700
Subject: adding deinit() stub for usbh/hcd class driver

add TUSB_VERSION_BUILD, also add TUSB_VERSION_NUMBER
---
 src/class/cdc/cdc_host.c |  4 ++++
 src/class/cdc/cdc_host.h |  1 +
 src/class/hid/hid_host.c |  4 ++++
 src/class/hid/hid_host.h |  1 +
 src/class/msc/msc_host.c |  5 +++++
 src/class/msc/msc_host.h |  1 +
 src/host/hcd.h           |  3 +++
 src/host/hub.c           |  7 ++++--
 src/host/hub.h           |  1 +
 src/host/usbh.c          | 55 ++++++++++++++++++++++++++++++++++++------------
 src/host/usbh.h          |  4 ++++
 src/host/usbh_pvt.h      |  4 +---
 src/tusb_option.h        |  5 +++++
 13 files changed, 76 insertions(+), 19 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 2fb37d835..14f380b40 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -637,6 +637,10 @@ void cdch_init(void) {
   }
 }
 
+bool cdch_deinit(void) {
+  return true;
+}
+
 void cdch_close(uint8_t daddr) {
   for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
     cdch_interface_t* p_cdc = &cdch_data[idx];
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index d512a23a5..7530b1e9d 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -193,6 +193,7 @@ TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void cdch_init       (void);
+bool cdch_deinit     (void);
 bool cdch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 bool cdch_set_config (uint8_t dev_addr, uint8_t itf_num);
 bool cdch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 7330fa237..16e2d3c2c 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -376,6 +376,10 @@ void hidh_init(void) {
   tu_memclr(_hidh_itf, sizeof(_hidh_itf));
 }
 
+bool hidh_deinit(void) {
+  return true;
+}
+
 bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) result;
 
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 17f4e27c0..9ea222b3d 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -164,6 +164,7 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void hidh_init(void);
+bool hidh_deinit(void);
 bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len);
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num);
 bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 39f2d9f1c..61ecb8e4e 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -288,6 +288,11 @@ void msch_init(void) {
   tu_memclr(_msch_itf, sizeof(_msch_itf));
 }
 
+bool msch_deinit(void) {
+  return true;
+}
+
+
 void msch_close(uint8_t dev_addr) {
   TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,);
   msch_interface_t* p_msc = get_itf(dev_addr);
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 9ca1b4703..5bf2e62e3 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -114,6 +114,7 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr);
 //--------------------------------------------------------------------+
 
 void msch_init       (void);
+bool msch_deinit     (void);
 bool msch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
 bool msch_set_config (uint8_t dev_addr, uint8_t itf_num);
 void msch_close      (uint8_t dev_addr);
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 2bde289df..d5804c608 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -130,6 +130,9 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_AT
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport);
 
+// De-initialize controller
+bool hcd_deinit(uint8_t rhport);
+
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport, bool in_isr);
 
diff --git a/src/host/hub.c b/src/host/hub.c
index 3bac18698..0853ff27a 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -182,11 +182,14 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
 //--------------------------------------------------------------------+
 // CLASS-USBH API (don't require to verify parameters)
 //--------------------------------------------------------------------+
-void hub_init(void)
-{
+void hub_init(void) {
   tu_memclr(hub_data, sizeof(hub_data));
 }
 
+bool hub_deinit(void) {
+  return true;
+}
+
 bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
   (void) rhport;
diff --git a/src/host/hub.h b/src/host/hub.h
index 390740e1f..c3f4a3612 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -205,6 +205,7 @@ static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_por
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void hub_init       (void);
+bool hub_deinit     (void);
 bool hub_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 bool hub_set_config (uint8_t dev_addr, uint8_t itf_num);
 bool hub_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 625857683..cf348bbb2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -45,8 +45,13 @@
 #endif
 
 //--------------------------------------------------------------------+
-// Callback weak stubs (called if application does not provide)
+// Weak stubs: invoked if no strong implementation is available
 //--------------------------------------------------------------------+
+TU_ATTR_WEAK bool hcd_deinit(uint8_t rhport) {
+  (void) rhport;
+  return false;
+}
+
 TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
   (void) rhport;
   (void) eventid;
@@ -119,16 +124,17 @@ typedef struct {
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
-  #define DRIVER_NAME(_name)    .name = _name,
+  #define DRIVER_NAME(_name)  _name
 #else
-  #define DRIVER_NAME(_name)
+  #define DRIVER_NAME(_name)  NULL
 #endif
 
 static usbh_class_driver_t const usbh_class_drivers[] = {
     #if CFG_TUH_CDC
     {
-        DRIVER_NAME("CDC")
+        .name       = DRIVER_NAME("CDC"),
         .init       = cdch_init,
+        .deinit     = cdch_deinit,
         .open       = cdch_open,
         .set_config = cdch_set_config,
         .xfer_cb    = cdch_xfer_cb,
@@ -138,8 +144,9 @@ static usbh_class_driver_t const usbh_class_drivers[] = {
 
     #if CFG_TUH_MSC
     {
-        DRIVER_NAME("MSC")
+        .name       = DRIVER_NAME("MSC"),
         .init       = msch_init,
+        .deinit     = msch_deinit,
         .open       = msch_open,
         .set_config = msch_set_config,
         .xfer_cb    = msch_xfer_cb,
@@ -149,8 +156,9 @@ static usbh_class_driver_t const usbh_class_drivers[] = {
 
     #if CFG_TUH_HID
     {
-        DRIVER_NAME("HID")
+        .name       = DRIVER_NAME("HID"),
         .init       = hidh_init,
+        .deinit     = hidh_deinit,
         .open       = hidh_open,
         .set_config = hidh_set_config,
         .xfer_cb    = hidh_xfer_cb,
@@ -160,8 +168,9 @@ static usbh_class_driver_t const usbh_class_drivers[] = {
 
     #if CFG_TUH_HUB
     {
-        DRIVER_NAME("HUB")
+        .name       = DRIVER_NAME("HUB"),
         .init       = hub_init,
+        .deinit     = hub_deinit,
         .open       = hub_open,
         .set_config = hub_set_config,
         .xfer_cb    = hub_xfer_cb,
@@ -171,9 +180,11 @@ static usbh_class_driver_t const usbh_class_drivers[] = {
 
     #if CFG_TUH_VENDOR
     {
-      DRIVER_NAME("VENDOR")
+      .name       = DRIVER_NAME("VENDOR"),
       .init       = cush_init,
-      .open       = cush_open_subtask,
+      .deinit     = cush_deinit,
+      .open       = cush_open,
+      .set_config = cush_set_config,
       .xfer_cb    = cush_isr,
       .close      = cush_close
     }
@@ -338,11 +349,11 @@ bool tuh_inited(void) {
   return _usbh_controller != TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_init(uint8_t controller_id) {
+bool tuh_init(uint8_t rhport) {
   // skip if already initialized
   if ( tuh_inited() ) return true;
 
-  TU_LOG_USBH("USBH init on controller %u\r\n", controller_id);
+  TU_LOG_USBH("USBH init on controller %u\r\n", rhport);
   TU_LOG_INT_USBH(sizeof(usbh_device_t));
   TU_LOG_INT_USBH(sizeof(hcd_event_t));
   TU_LOG_INT_USBH(sizeof(_ctrl_xfer));
@@ -383,10 +394,26 @@ bool tuh_init(uint8_t controller_id) {
     }
   }
 
-  _usbh_controller = controller_id;;
+  _usbh_controller = rhport;;
+
+  TU_ASSERT(hcd_init(rhport));
+  hcd_int_enable(rhport);
+
+  return true;
+}
+
+bool tuh_deinit(uint8_t rhport) {
+  if (!tuh_rhport_is_active(rhport)) return true;
+
+  hcd_int_disable(rhport);
+  hcd_deinit(rhport);
 
-  TU_ASSERT(hcd_init(controller_id));
-  hcd_int_enable(controller_id);
+  _usbh_controller = TUSB_INDEX_INVALID_8;
+
+  // no other controller is active, deinit the stack
+  if (!tuh_inited()) {
+
+  }
 
   return true;
 }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 9ff118543..0e31e80a7 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -109,7 +109,11 @@ bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
 // Init host stack
 bool tuh_init(uint8_t rhport);
 
+// Deinit host stack on rhport
+bool tuh_deinit(uint8_t rhport);
+
 // Check if host stack is already initialized with any roothub ports
+// To check if an rhport is initialized, use tuh_rhport_is_active()
 bool tuh_inited(void);
 
 // Task function should be called in main/rtos loop, extended version of tuh_task()
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 4ed2a72b5..204315175 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -50,11 +50,9 @@ enum {
 //--------------------------------------------------------------------+
 
 typedef struct {
-  #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL
   char const* name;
-  #endif
-
   void (* const init       )(void);
+  bool (* const deinit     )(void);
   bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
   bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
   bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 96378cb80..22f27e9e1 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -29,9 +29,14 @@
 
 #include "common/tusb_compiler.h"
 
+// Version is release as major.minor.revision eg 1.0.0. though there could be notable APIs before a new release.
+// For notable API changes within a release, we increase the build number.
 #define TUSB_VERSION_MAJOR     0
 #define TUSB_VERSION_MINOR     16
 #define TUSB_VERSION_REVISION  0
+#define TUSB_VERSION_BUILD     1
+
+#define TUSB_VERSION_NUMBER    (TUSB_VERSION_MAJOR << 24 | TUSB_VERSION_MINOR << 16 | TUSB_VERSION_REVISION << 8 | TUSB_VERSION_BUILD)
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 2cf171095e02d8562ff138520cbe686e013f4522 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Mar 2024 12:30:14 +0700
Subject: code format

---
 src/common/tusb_fifo.h |  31 ++----
 src/tusb.c             | 277 ++++++++++++++++++-------------------------------
 2 files changed, 113 insertions(+), 195 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 2f60ec2f4..2d9f5e667 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -102,10 +102,8 @@ extern "C" {
  *                  |
  *      -------------------------
  *      | R | 1 | 2 | W | 4 | 5 |
-
  */
-typedef struct
-{
+typedef struct {
   uint8_t* buffer          ; // buffer pointer
   uint16_t depth           ; // max items
 
@@ -124,16 +122,14 @@ typedef struct
 
 } tu_fifo_t;
 
-typedef struct
-{
+typedef struct {
   uint16_t len_lin  ; ///< linear length in item size
   uint16_t len_wrap ; ///< wrapped length in item size
   void * ptr_lin    ; ///< linear part start pointer
   void * ptr_wrap   ; ///< wrapped part start pointer
 } tu_fifo_buffer_info_t;
 
-#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \
-{                                                           \
+#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable){\
   .buffer               = _buffer,                          \
   .depth                = _depth,                           \
   .item_size            = sizeof(_type),                    \
@@ -144,23 +140,18 @@ typedef struct
     uint8_t _name##_buf[_depth*sizeof(_type)];                                \
     tu_fifo_t _name = TU_FIFO_INIT(_name##_buf, _depth, _type, _overwritable)
 
-
 bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable);
 bool tu_fifo_clear(tu_fifo_t *f);
 bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
 
 #if OSAL_MUTEX_REQUIRED
-TU_ATTR_ALWAYS_INLINE static inline
-void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex)
-{
-  f->mutex_wr = wr_mutex;
-  f->mutex_rd = rd_mutex;
-}
-
+  TU_ATTR_ALWAYS_INLINE static inline
+  void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) {
+    f->mutex_wr = wr_mutex;
+    f->mutex_rd = rd_mutex;
+  }
 #else
-
-#define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
-
+  #define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
 #endif
 
 bool     tu_fifo_write                  (tu_fifo_t* f, void const * p_data);
@@ -182,8 +173,7 @@ bool     tu_fifo_overflowed             (tu_fifo_t* f);
 void     tu_fifo_correct_read_pointer   (tu_fifo_t* f);
 
 TU_ATTR_ALWAYS_INLINE static inline
-uint16_t tu_fifo_depth(tu_fifo_t* f)
-{
+uint16_t tu_fifo_depth(tu_fifo_t* f) {
   return f->depth;
 }
 
@@ -198,7 +188,6 @@ void tu_fifo_advance_read_pointer (tu_fifo_t *f, uint16_t n);
 void tu_fifo_get_read_info (tu_fifo_t *f, tu_fifo_buffer_info_t *info);
 void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
 
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/tusb.c b/src/tusb.c
index 7c86f1ca5..2256dc3b9 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -43,32 +43,30 @@
 // Public API
 //--------------------------------------------------------------------+
 
-bool tusb_init(void)
-{
-#if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
+bool tusb_init(void) {
+  #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
   // init device stack CFG_TUSB_RHPORTx_MODE must be defined
   TU_ASSERT ( tud_init(TUD_OPT_RHPORT) );
-#endif
+  #endif
 
-#if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT)
+  #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT)
   // init host stack CFG_TUSB_RHPORTx_MODE must be defined
   TU_ASSERT( tuh_init(TUH_OPT_RHPORT) );
-#endif
+  #endif
 
   return true;
 }
 
-bool tusb_inited(void)
-{
+bool tusb_inited(void) {
   bool ret = false;
 
-#if CFG_TUD_ENABLED
+  #if CFG_TUD_ENABLED
   ret = ret || tud_inited();
-#endif
+  #endif
 
-#if CFG_TUH_ENABLED
+  #if CFG_TUH_ENABLED
   ret = ret || tuh_inited();
-#endif
+  #endif
 
   return ret;
 }
@@ -77,30 +75,24 @@ bool tusb_inited(void)
 // Descriptor helper
 //--------------------------------------------------------------------+
 
-uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1)
-{
-  while(desc+1 < end)
-  {
-    if ( desc[1] == byte1 ) return desc;
+uint8_t const* tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1) {
+  while (desc + 1 < end) {
+    if (desc[1] == byte1) return desc;
     desc += desc[DESC_OFFSET_LEN];
   }
   return NULL;
 }
 
-uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2)
-{
-  while(desc+2 < end)
-  {
-    if ( desc[1] == byte1 && desc[2] == byte2) return desc;
+uint8_t const* tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2) {
+  while (desc + 2 < end) {
+    if (desc[1] == byte1 && desc[2] == byte2) return desc;
     desc += desc[DESC_OFFSET_LEN];
   }
   return NULL;
 }
 
-uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3)
-{
-  while(desc+3 < end)
-  {
+uint8_t const* tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3) {
+  while (desc + 3 < end) {
     if (desc[1] == byte1 && desc[2] == byte2 && desc[3] == byte3) return desc;
     desc += desc[DESC_OFFSET_LEN];
   }
@@ -146,83 +138,71 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex) {
   return ret;
 }
 
-bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
-{
+bool tu_edpt_validate(tusb_desc_endpoint_t const* desc_ep, tusb_speed_t speed) {
   uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep);
   TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
 
-  switch (desc_ep->bmAttributes.xfer)
-  {
-    case TUSB_XFER_ISOCHRONOUS:
-    {
+  switch (desc_ep->bmAttributes.xfer) {
+    case TUSB_XFER_ISOCHRONOUS: {
       uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023);
       TU_ASSERT(max_packet_size <= spec_size);
+      break;
     }
-    break;
 
     case TUSB_XFER_BULK:
-      if (speed == TUSB_SPEED_HIGH)
-      {
+      if (speed == TUSB_SPEED_HIGH) {
         // Bulk highspeed must be EXACTLY 512
         TU_ASSERT(max_packet_size == 512);
-      }else
-      {
+      } else {
         // TODO Bulk fullspeed can only be 8, 16, 32, 64
         TU_ASSERT(max_packet_size <= 64);
       }
-    break;
+      break;
 
-    case TUSB_XFER_INTERRUPT:
-    {
+    case TUSB_XFER_INTERRUPT: {
       uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64);
       TU_ASSERT(max_packet_size <= spec_size);
+      break;
     }
-    break;
 
-    default: return false;
+    default:
+      return false;
   }
 
   return true;
 }
 
-void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id)
-{
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len,
+                         uint8_t driver_id) {
   uint8_t const* p_desc = (uint8_t const*) desc_itf;
   uint8_t const* desc_end = p_desc + desc_len;
 
-  while( p_desc < desc_end )
-  {
-    if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-    {
+  while (p_desc < desc_end) {
+    if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) {
       uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
-
       TU_LOG(2, "  Bind EP %02x to driver id %u\r\n", ep_addr, driver_id);
       ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
     }
-
     p_desc = tu_desc_next(p_desc);
   }
 }
 
-uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
-{
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) {
   uint8_t const* p_desc = (uint8_t const*) desc_itf;
   uint16_t len = 0;
 
-  while (itf_count--)
-  {
+  while (itf_count--) {
     // Next on interface desc
     len += tu_desc_len(desc_itf);
     p_desc = tu_desc_next(p_desc);
 
-    while (len < max_len)
-    {
+    while (len < max_len) {
       // return on IAD regardless of itf count
-      if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
-
-      if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
-           ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 )
-      {
+      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) {
+        return len;
+      }
+      if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
+          ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0) {
         break;
       }
 
@@ -239,8 +219,7 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
 //--------------------------------------------------------------------+
 
 bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
-                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize)
-{
+                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) {
   osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex);
   (void) new_mutex;
   (void) is_tx;
@@ -256,91 +235,72 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-bool stream_claim(tu_edpt_stream_t* s)
-{
-  if (s->is_host)
-  {
+bool stream_claim(tu_edpt_stream_t* s) {
+  if (s->is_host) {
     #if CFG_TUH_ENABLED
     return usbh_edpt_claim(s->daddr, s->ep_addr);
     #endif
-  }else
-  {
+  } else {
     #if CFG_TUD_ENABLED
     return usbd_edpt_claim(s->rhport, s->ep_addr);
     #endif
   }
-
   return false;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-bool stream_xfer(tu_edpt_stream_t* s, uint16_t count)
-{
-  if (s->is_host)
-  {
+bool stream_xfer(tu_edpt_stream_t* s, uint16_t count) {
+  if (s->is_host) {
     #if CFG_TUH_ENABLED
     return usbh_edpt_xfer(s->daddr, s->ep_addr, count ? s->ep_buf : NULL, count);
     #endif
-  }else
-  {
+  } else {
     #if CFG_TUD_ENABLED
     return usbd_edpt_xfer(s->rhport, s->ep_addr, count ? s->ep_buf : NULL, count);
     #endif
   }
-
   return false;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-bool stream_release(tu_edpt_stream_t* s)
-{
-  if (s->is_host)
-  {
+bool stream_release(tu_edpt_stream_t* s) {
+  if (s->is_host) {
     #if CFG_TUH_ENABLED
     return usbh_edpt_release(s->daddr, s->ep_addr);
     #endif
-  }else
-  {
+  } else {
     #if CFG_TUD_ENABLED
     return usbd_edpt_release(s->rhport, s->ep_addr);
     #endif
   }
-
   return false;
 }
 
 //--------------------------------------------------------------------+
 // Stream Write
 //--------------------------------------------------------------------+
-
-bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes)
-{
+bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes) {
   // ZLP condition: no pending data, last transferred bytes is multiple of packet size
-  TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) );
-
-  TU_VERIFY( stream_claim(s) );
-  TU_ASSERT( stream_xfer(s, 0) );
-
+  TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize - 1))));
+  TU_VERIFY(stream_claim(s));
+  TU_ASSERT(stream_xfer(s, 0));
   return true;
 }
 
-uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
-{
+uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s) {
   // skip if no data
-  TU_VERIFY( tu_fifo_count(&s->ff), 0 );
+  TU_VERIFY(tu_fifo_count(&s->ff), 0);
 
   // Claim the endpoint
-  TU_VERIFY( stream_claim(s), 0 );
+  TU_VERIFY(stream_claim(s), 0);
 
   // Pull data from FIFO -> EP buf
   uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
 
-  if ( count )
-  {
-    TU_ASSERT( stream_xfer(s, count), 0 );
+  if (count) {
+    TU_ASSERT(stream_xfer(s, count), 0);
     return count;
-  }else
-  {
+  } else {
     // Release endpoint since we don't make any transfer
     // Note: data is dropped if terminal is not connected
     stream_release(s);
@@ -348,16 +308,13 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
   }
 }
 
-uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize)
-{
+uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const* buffer, uint32_t bufsize) {
   TU_VERIFY(bufsize); // TODO support ZLP
-
   uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
 
   // flush if fifo has more than packet size or
   // in rare case: fifo depth is configured too small (which never reach packet size)
-  if ( (tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize) )
-  {
+  if ((tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize)) {
     tu_edpt_stream_write_xfer(s);
   }
 
@@ -367,9 +324,7 @@ uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t
 //--------------------------------------------------------------------+
 // Stream Read
 //--------------------------------------------------------------------+
-
-uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
-{
+uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s) {
   uint16_t available = tu_fifo_remaining(&s->ff);
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
@@ -384,25 +339,21 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
   // get available again since fifo can be changed before endpoint is claimed
   available = tu_fifo_remaining(&s->ff);
 
-  if ( available >= s->ep_packetsize )
-  {
+  if (available >= s->ep_packetsize) {
     // multiple of packet size limit by ep bufsize
-    uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1));
+    uint16_t count = (uint16_t) (available & ~(s->ep_packetsize - 1));
     count = tu_min16(count, s->ep_bufsize);
 
-    TU_ASSERT( stream_xfer(s, count), 0 );
-
+    TU_ASSERT(stream_xfer(s, count), 0);
     return count;
-  }else
-  {
+  } else {
     // Release endpoint since we don't make any transfer
     stream_release(s);
     return 0;
   }
 }
 
-uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize)
-{
+uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize) {
   uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize);
   tu_edpt_stream_read_xfer(s);
   return num_read;
@@ -416,42 +367,35 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize
 #include <ctype.h>
 
 #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL || CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
-
-char const* const tu_str_speed[] = { "Full", "Low", "High" };
-char const* const tu_str_std_request[] =
-{
-  "Get Status"        ,
-  "Clear Feature"     ,
-  "Reserved"          ,
-  "Set Feature"       ,
-  "Reserved"          ,
-  "Set Address"       ,
-  "Get Descriptor"    ,
-  "Set Descriptor"    ,
-  "Get Configuration" ,
-  "Set Configuration" ,
-  "Get Interface"     ,
-  "Set Interface"     ,
-  "Synch Frame"
+char const* const tu_str_speed[] = {"Full", "Low", "High"};
+char const* const tu_str_std_request[] = {
+    "Get Status",
+    "Clear Feature",
+    "Reserved",
+    "Set Feature",
+    "Reserved",
+    "Set Address",
+    "Get Descriptor",
+    "Set Descriptor",
+    "Get Configuration",
+    "Set Configuration",
+    "Get Interface",
+    "Set Interface",
+    "Synch Frame"
 };
 
 char const* const tu_str_xfer_result[] = {
     "OK", "FAILED", "STALLED", "TIMEOUT"
 };
-
 #endif
 
-static void dump_str_line(uint8_t const* buf, uint16_t count)
-{
+static void dump_str_line(uint8_t const* buf, uint16_t count) {
   tu_printf("  |");
-
   // each line is 16 bytes
-  for(uint16_t i=0; i<count; i++)
-  {
+  for (uint16_t i = 0; i < count; i++) {
     const char ch = buf[i];
     tu_printf("%c", isprint(ch) ? ch : '.');
   }
-
   tu_printf("|\r\n");
 }
 
@@ -460,39 +404,27 @@ static void dump_str_line(uint8_t const* buf, uint16_t count)
  *  - count : number of item
  *  - indent: prefix spaces on every line
  */
-void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
-{
+void tu_print_mem(void const* buf, uint32_t count, uint8_t indent) {
   uint8_t const size = 1; // fixed 1 byte for now
-
-  if ( !buf || !count )
-  {
+  if (!buf || !count) {
     tu_printf("NULL\r\n");
     return;
   }
 
-  uint8_t const *buf8 = (uint8_t const *) buf;
-
+  uint8_t const* buf8 = (uint8_t const*) buf;
   char format[] = "%00X";
-  format[2] += (uint8_t) (2*size); // 1 byte = 2 hex digits
+  format[2] += (uint8_t) (2 * size); // 1 byte = 2 hex digits
+  const uint8_t item_per_line = 16 / size;
 
-  const uint8_t item_per_line  = 16 / size;
+  for (unsigned int i = 0; i < count; i++) {
+    unsigned int value = 0;
 
-  for(unsigned int i=0; i<count; i++)
-  {
-    unsigned int value=0;
-
-    if ( i%item_per_line == 0 )
-    {
+    if (i % item_per_line == 0) {
       // Print Ascii
-      if ( i != 0 )
-      {
-        dump_str_line(buf8-16, 16);
-      }
-
-      for(uint8_t s=0; s < indent; s++) tu_printf(" ");
-
+      if (i != 0) dump_str_line(buf8 - 16, 16);
+      for (uint8_t s = 0; s < indent; s++) tu_printf(" ");
       // print offset or absolute address
-      tu_printf("%04X: ", 16*i/item_per_line);
+      tu_printf("%04X: ", 16 * i / item_per_line);
     }
 
     tu_memcpy_s(&value, sizeof(value), buf8, size);
@@ -503,19 +435,16 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
   }
 
   // fill up last row to 16 for printing ascii
-  const uint32_t remain = count%16;
-  uint8_t nback = (uint8_t)(remain ? remain : 16);
-
-  if ( remain )
-  {
-    for(uint32_t i=0; i< 16-remain; i++)
-    {
+  const uint32_t remain = count % 16;
+  uint8_t nback = (uint8_t) (remain ? remain : 16);
+  if (remain) {
+    for (uint32_t i = 0; i < 16 - remain; i++) {
       tu_printf(" ");
-      for(int j=0; j<2*size; j++) tu_printf(" ");
+      for (int j = 0; j < 2 * size; j++) tu_printf(" ");
     }
   }
 
-  dump_str_line(buf8-nback, nback);
+  dump_str_line(buf8 - nback, nback);
 }
 
 #endif
-- 
cgit v1.3.1


From 5774ac98864880fdc7c1d6a8b9c7e160ac0dfba8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Mar 2024 12:53:31 +0700
Subject: add tu_edpt_stream_deinit()

---
 src/common/tusb_private.h | 19 +++++++++----------
 src/tusb.c                | 11 ++++++++++-
 2 files changed, 19 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index db1ba974d..373a50256 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -60,7 +60,7 @@ typedef struct {
   tu_fifo_t ff;
 
   // mutex: read if ep rx, write if e tx
-  OSAL_MUTEX_DEF(ff_mutex);
+  OSAL_MUTEX_DEF(ff_mutexdef);
 
 }tu_edpt_stream_t;
 
@@ -87,15 +87,17 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
 // Endpoint Stream
 //--------------------------------------------------------------------+
 
-// Init an stream, should only be called once
+// Init an endpoint stream
 bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
                          void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize);
 
+// Deinit an endpoint stream
+bool tu_edpt_stream_deinit(tu_edpt_stream_t* s);
+
 // Open an stream for an endpoint
 // hwid is either device address (host mode) or rhport (device mode)
 TU_ATTR_ALWAYS_INLINE static inline
-void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t const *desc_ep)
-{
+void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t const *desc_ep) {
   tu_fifo_clear(&s->ff);
   s->hwid = hwid;
   s->ep_addr = desc_ep->bEndpointAddress;
@@ -103,16 +105,14 @@ void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void tu_edpt_stream_close(tu_edpt_stream_t* s)
-{
+void tu_edpt_stream_close(tu_edpt_stream_t* s) {
   s->hwid = 0;
   s->ep_addr = 0;
 }
 
 // Clear fifo
 TU_ATTR_ALWAYS_INLINE static inline
-bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
-{
+bool tu_edpt_stream_clear(tu_edpt_stream_t* s) {
   return tu_fifo_clear(&s->ff);
 }
 
@@ -131,8 +131,7 @@ bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferr
 
 // Get the number of bytes available for writing
 TU_ATTR_ALWAYS_INLINE static inline
-uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s)
-{
+uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s) {
   return (uint32_t) tu_fifo_remaining(&s->ff);
 }
 
diff --git a/src/tusb.c b/src/tusb.c
index 2256dc3b9..074dcce96 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -220,7 +220,7 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
 
 bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
                          void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize) {
-  osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex);
+  osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutexdef);
   (void) new_mutex;
   (void) is_tx;
 
@@ -234,6 +234,15 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove
   return true;
 }
 
+bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) {
+  (void) s;
+  #if OSAL_MUTEX_REQUIRED
+  if (s->ff->mutex_wr) osal_mutex_delete(s->ff->mutex_wr);
+  if (s->ff->mutex_rd) osal_mutex_delete(s->ff->mutex_rd);
+  #endif
+  return true;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline
 bool stream_claim(tu_edpt_stream_t* s) {
   if (s->is_host) {
-- 
cgit v1.3.1


From 31f68495cf66706926c408ad15ea90a646c62198 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Mar 2024 16:10:26 +0700
Subject: update osal API

add osal_semaphore_delete(), osal_mutex_delete(), osal_queue_delete()
---
 src/osal/osal.h          |   3 ++
 src/osal/osal_freertos.h |  19 ++++++++-
 src/osal/osal_mynewt.h   |  61 +++++++++++++--------------
 src/osal/osal_none.h     |  16 ++++++++
 src/osal/osal_pico.h     | 105 +++++++++++++++++++----------------------------
 src/osal/osal_rtthread.h |   6 +--
 src/osal/osal_rtx4.h     |  61 ++++++++++++++-------------
 src/tusb.c               |   4 +-
 8 files changed, 147 insertions(+), 128 deletions(-)

(limited to 'src')

diff --git a/src/osal/osal.h b/src/osal/osal.h
index f092e8ffb..8f45ea5c1 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -74,15 +74,18 @@ typedef void (*osal_task_func_t)( void * );
 // Should be implemented as static inline function in osal_port.h header
 /*
    osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
+   bool osal_semaphore_delete(osal_semaphore_t semd_hdl);
    bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
    bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
    void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
 
    osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
+   bool osal_mutex_delete(osal_mutex_t mutex_hdl)
    bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
    bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
 
    osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
+   bool osal_queue_delete(osal_queue_t qhdl);
    bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec);
    bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
    bool osal_queue_empty(osal_queue_t qhdl);
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 501e0bddd..f1f05f353 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_FREERTOS_H_
-#define _TUSB_OSAL_FREERTOS_H_
+#ifndef TUSB_OSAL_FREERTOS_H_
+#define TUSB_OSAL_FREERTOS_H_
 
 // FreeRTOS Headers
 #include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
@@ -114,6 +114,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_
 #endif
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  vSemaphoreDelete(semd_hdl);
+  return true;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   if ( !in_isr ) {
     return xSemaphoreGive(sem_hdl) != 0;
@@ -153,6 +158,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de
 #endif
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  vSemaphoreDelete(mutex_hdl);
+  return true;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
@@ -181,6 +191,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
   return q;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  vQueueDelete(qhdl);
+  return true;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   return xQueueReceive(qhdl, data, _osal_ms2tick(msec));
 }
diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h
index b8ea2087c..16def0d2a 100644
--- a/src/osal/osal_mynewt.h
+++ b/src/osal/osal_mynewt.h
@@ -36,8 +36,7 @@
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   os_time_delay( os_time_ms_to_ticks32(msec) );
 }
 
@@ -47,25 +46,26 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 typedef struct os_sem  osal_semaphore_def_t;
 typedef struct os_sem* osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
   return (os_sem_init(semdef, 0) == OS_OK) ? (osal_semaphore_t) semdef : NULL;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   (void) in_isr;
   return os_sem_release(sem_hdl) == OS_OK;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
   return os_sem_pend(sem_hdl, ticks) == OS_OK;
 }
 
-static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
-{
+static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
   // TODO implement later
 }
 
@@ -75,19 +75,21 @@ static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
 typedef struct os_mutex osal_mutex_def_t;
 typedef struct os_mutex* osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   return (os_mutex_init(mdef) == OS_OK) ? (osal_mutex_t) mdef : NULL;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
   return os_mutex_pend(mutex_hdl, ticks) == OS_OK;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return os_mutex_release(mutex_hdl) == OS_OK;
 }
 
@@ -101,8 +103,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
   static struct os_event _name##_##evbuf[_depth];\
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf =  _name##_##evbuf};\
 
-typedef struct
-{
+typedef struct {
   uint16_t depth;
   uint16_t item_sz;
   void*    buf;
@@ -116,17 +117,20 @@ typedef struct
 
 typedef osal_queue_def_t* osal_queue_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
-  if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usbd queue") ) return NULL;
-  if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usbd evqueue") ) return NULL;
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
+  if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usb queue") ) return NULL;
+  if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usb evqueue") ) return NULL;
 
   os_eventq_init(&qdef->evq);
   return (osal_queue_t) qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   (void) msec; // os_eventq_get() does not take timeout, always behave as msec = WAIT_FOREVER
 
   struct os_event* ev;
@@ -139,8 +143,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
   return true;
 }
 
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) {
   (void) in_isr;
 
   // get a block from mem pool for data
@@ -150,8 +153,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
 
   // get a block from event pool to put into queue
   struct os_event* ev = (struct os_event*) os_memblock_get(&qhdl->epool);
-  if (!ev)
-  {
+  if (!ev) {
     os_memblock_put(&qhdl->mpool, ptr);
     return false;
   }
@@ -163,8 +165,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   return STAILQ_EMPTY(&qhdl->evq.evq_list);
 }
 
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index a07d39828..c954fcfe8 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -54,6 +54,12 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_
   return semdef;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   (void) in_isr;
   sem_hdl->count++;
@@ -90,6 +96,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de
   return mdef;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
@@ -143,6 +154,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
   return (osal_queue_t) qdef;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true; // nothing to do
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   (void) msec; // not used, always behave as msec = 0
 
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index e6efa0968..00c589ef9 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_PICO_H_
-#define _TUSB_OSAL_PICO_H_
+#ifndef TUSB_OSAL_PICO_H_
+#define TUSB_OSAL_PICO_H_
 
 #include "pico/time.h"
 #include "pico/sem.h"
@@ -33,42 +33,42 @@
 #include "pico/critical_section.h"
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   sleep_ms(msec);
 }
 
 //--------------------------------------------------------------------+
 // Binary Semaphore API
 //--------------------------------------------------------------------+
-typedef struct semaphore osal_semaphore_def_t, *osal_semaphore_t;
+typedef struct semaphore osal_semaphore_def_t, * osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) {
   sem_init(semdef, 0, 255);
   return semdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   (void) in_isr;
   sem_release(sem_hdl);
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   return sem_acquire_timeout_ms(sem_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) {
   sem_reset(sem_hdl, 0);
 }
 
@@ -76,21 +76,23 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t s
 // MUTEX API
 // Within tinyusb, mutex is never used in ISR context
 //--------------------------------------------------------------------+
-typedef struct mutex osal_mutex_def_t, *osal_mutex_t;
+typedef struct mutex osal_mutex_def_t, * osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   mutex_init(mdef);
   return mdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   return mutex_enter_timeout_ms(mutex_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   mutex_exit(mutex_hdl);
   return true;
 }
@@ -100,75 +102,54 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 //--------------------------------------------------------------------+
 #include "common/tusb_fifo.h"
 
-typedef struct
-{
-    tu_fifo_t ff;
-    struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section
+typedef struct {
+  tu_fifo_t ff;
+  struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section
 } osal_queue_def_t;
 
 typedef osal_queue_def_t* osal_queue_t;
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)       \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)    \
   uint8_t _name##_buf[_depth*sizeof(_type)];              \
   osal_queue_def_t _name = {                              \
     .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
   }
 
-// lock queue by disable USB interrupt
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl)
-{
-  critical_section_enter_blocking(&qhdl->critsec);
-}
-
-// unlock queue
-TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl)
-{
-  critical_section_exit(&qhdl->critsec);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   critical_section_init(&qdef->critsec);
   tu_fifo_clear(&qdef->ff);
   return (osal_queue_t) qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
-  (void) msec; // not used, always behave as msec = 0
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  osal_queue_def_t* qdef = (osal_queue_def_t*) qhdl;
+  critical_section_deinit(&qdef->critsec);
+  return true;
+}
 
-  // TODO: revisit... docs say that mutexes are never used from IRQ context,
-  //  however osal_queue_recieve may be. therefore my assumption is that
-  //  the fifo mutex is not populated for queues used from an IRQ context
-  //assert(!qhdl->ff.mutex);
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
+  (void) msec; // not used, always behave as msec = 0
 
-  _osal_q_lock(qhdl);
+  critical_section_enter_blocking(&qhdl->critsec);
   bool success = tu_fifo_read(&qhdl->ff, data);
-  _osal_q_unlock(qhdl);
+  critical_section_exit(&qhdl->critsec);
 
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
-  // TODO: revisit... docs say that mutexes are never used from IRQ context,
-  //  however osal_queue_recieve may be. therefore my assumption is that
-  //  the fifo mutex is not populated for queues used from an IRQ context
-  //assert(!qhdl->ff.mutex);
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) {
   (void) in_isr;
 
-  _osal_q_lock(qhdl);
+  critical_section_enter_blocking(&qhdl->critsec);
   bool success = tu_fifo_write(&qhdl->ff, data);
-  _osal_q_unlock(qhdl);
+  critical_section_exit(&qhdl->critsec);
 
   TU_ASSERT(success);
-
   return success;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   // TODO: revisit; whether this is true or not currently, tu_fifo_empty is a single
   //  volatile read.
 
@@ -178,7 +159,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
 }
 
 #ifdef __cplusplus
- }
+}
 #endif
 
-#endif /* _TUSB_OSAL_PICO_H_ */
+#endif
diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index d03b53bee..a8423086f 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -25,8 +25,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_RTTHREAD_H_
-#define _TUSB_OSAL_RTTHREAD_H_
+#ifndef TUSB_OSAL_RTTHREAD_H_
+#define TUSB_OSAL_RTTHREAD_H_
 
 // RT-Thread Headers
 #include "rtthread.h"
@@ -133,4 +133,4 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
 }
 #endif
 
-#endif /* _TUSB_OSAL_RTTHREAD_H_ */
+#endif
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index e443135e0..35909e4d6 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -25,8 +25,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_OSAL_RTX4_H_
-#define _TUSB_OSAL_RTX4_H_
+#ifndef TUSB_OSAL_RTX4_H_
+#define TUSB_OSAL_RTX4_H_
 
 #include <rtl.h>
 
@@ -37,8 +37,7 @@ extern "C" {
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   uint16_t hi = msec >> 16;
   uint16_t lo = msec;
   while (hi--) {
@@ -48,12 +47,13 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) {
-  if (msec == OSAL_TIMEOUT_WAIT_FOREVER)
+  if (msec == OSAL_TIMEOUT_WAIT_FOREVER) {
     return 0xFFFF;
-  else if (msec >= 0xFFFE)
+  } else if (msec >= 0xFFFE) {
     return 0xFFFE;
-  else
+  } else {
     return msec;
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -67,6 +67,11 @@ TU_ATTR_ALWAYS_INLINE static inline OS_ID osal_semaphore_create(osal_semaphore_d
   return semdef;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  (void) semd_hdl;
+  return true; // nothing to do
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   if ( !in_isr ) {
     os_sem_send(sem_hdl);
@@ -90,19 +95,21 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 typedef OS_MUT osal_mutex_def_t;
 typedef OS_ID osal_mutex_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) {
   os_mut_init(mdef);
   return mdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  (void) mutex_hdl;
+  return true; // nothing to do
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) {
   return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return os_mut_release(mutex_hdl) == OS_R_OK;
 }
 
@@ -116,9 +123,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
   _declare_box(_name##__pool, sizeof(_type), _depth); \
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox };
 
-
-typedef struct
-{
+typedef struct {
   uint16_t depth;
   uint16_t item_sz;
   U32* pool;
@@ -127,15 +132,13 @@ typedef struct
 
 typedef osal_queue_def_t* osal_queue_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4);
   _init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz);
   return qdef;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   void* buf;
   os_mbx_wait(qhdl->mbox, &buf, msec2wait(msec));
   memcpy(data, buf, qhdl->item_sz);
@@ -143,23 +146,23 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  (void) qhdl;
+  return true; // nothing to do ?
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) {
   void* buf = _alloc_box(qhdl->pool);
   memcpy(buf, data, qhdl->item_sz);
-  if ( !in_isr )
-  {
+  if ( !in_isr ) {
     os_mbx_send(qhdl->mbox, buf, 0xFFFF);
-  }
-  else
-  {
+  } else {
     isr_mbx_send(qhdl->mbox, buf);
   }
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   return os_mbx_check(qhdl->mbox) == qhdl->depth;
 }
 
diff --git a/src/tusb.c b/src/tusb.c
index 074dcce96..0f09acb64 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -237,8 +237,8 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove
 bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) {
   (void) s;
   #if OSAL_MUTEX_REQUIRED
-  if (s->ff->mutex_wr) osal_mutex_delete(s->ff->mutex_wr);
-  if (s->ff->mutex_rd) osal_mutex_delete(s->ff->mutex_rd);
+  if (s->ff.mutex_wr) osal_mutex_delete(s->ff.mutex_wr);
+  if (s->ff.mutex_rd) osal_mutex_delete(s->ff.mutex_rd);
   #endif
   return true;
 }
-- 
cgit v1.3.1


From e84c9f3e221092687808f175e1e19732a10fea72 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Mar 2024 16:12:57 +0700
Subject: implement tuh_init()

change usbh driver init() return type from void to bool
---
 src/class/cdc/cdc_host.c | 12 +++++--
 src/class/cdc/cdc_host.h |  2 +-
 src/class/hid/hid_host.c |  4 ++-
 src/class/hid/hid_host.h |  2 +-
 src/class/msc/msc_host.c |  5 +--
 src/class/msc/msc_host.h |  2 +-
 src/host/hub.c           |  3 +-
 src/host/hub.h           | 12 +++----
 src/host/usbh.c          | 85 ++++++++++++++++++++++++++++++------------------
 src/host/usbh_pvt.h      |  2 +-
 10 files changed, 79 insertions(+), 50 deletions(-)

(limited to 'src')

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 14f380b40..5bdd41f1f 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -621,12 +621,11 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 // CLASS-USBH API
 //--------------------------------------------------------------------+
 
-void cdch_init(void) {
+bool cdch_init(void) {
+  TU_LOG_DRV("sizeof(cdch_interface_t) = %u\r\n", sizeof(cdch_interface_t));
   tu_memclr(cdch_data, sizeof(cdch_data));
-
   for (size_t i = 0; i < CFG_TUH_CDC; i++) {
     cdch_interface_t* p_cdc = &cdch_data[i];
-
     tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
                         p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
                         p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
@@ -635,9 +634,16 @@ void cdch_init(void) {
                         p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
                         p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
   }
+
+  return true;
 }
 
 bool cdch_deinit(void) {
+  for (size_t i = 0; i < CFG_TUH_CDC; i++) {
+    cdch_interface_t* p_cdc = &cdch_data[i];
+    tu_edpt_stream_deinit(&p_cdc->stream.tx);
+    tu_edpt_stream_deinit(&p_cdc->stream.rx);
+  }
   return true;
 }
 
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 7530b1e9d..b63dd1530 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -192,7 +192,7 @@ TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx);
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void cdch_init       (void);
+bool cdch_init       (void);
 bool cdch_deinit     (void);
 bool cdch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 bool cdch_set_config (uint8_t dev_addr, uint8_t itf_num);
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 16e2d3c2c..efc54656e 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -372,8 +372,10 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo
 //--------------------------------------------------------------------+
 // USBH API
 //--------------------------------------------------------------------+
-void hidh_init(void) {
+bool hidh_init(void) {
+  TU_LOG_DRV("sizeof(hidh_interface_t) = %u\r\n", sizeof(hidh_interface_t));
   tu_memclr(_hidh_itf, sizeof(_hidh_itf));
+  return true;
 }
 
 bool hidh_deinit(void) {
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 9ea222b3d..0902bf1af 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -163,7 +163,7 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void hidh_init(void);
+bool hidh_init(void);
 bool hidh_deinit(void);
 bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len);
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num);
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 61ecb8e4e..ce6e7fb2d 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -284,15 +284,16 @@ bool tuh_msc_reset(uint8_t dev_addr) {
 //--------------------------------------------------------------------+
 // CLASS-USBH API
 //--------------------------------------------------------------------+
-void msch_init(void) {
+bool msch_init(void) {
+  TU_LOG_DRV("sizeof(msch_interface_t) = %u\r\n", sizeof(msch_interface_t));
   tu_memclr(_msch_itf, sizeof(_msch_itf));
+  return true;
 }
 
 bool msch_deinit(void) {
   return true;
 }
 
-
 void msch_close(uint8_t dev_addr) {
   TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,);
   msch_interface_t* p_msc = get_itf(dev_addr);
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 5bf2e62e3..9fda566d8 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -113,7 +113,7 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 
-void msch_init       (void);
+bool msch_init       (void);
 bool msch_deinit     (void);
 bool msch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
 bool msch_set_config (uint8_t dev_addr, uint8_t itf_num);
diff --git a/src/host/hub.c b/src/host/hub.c
index 0853ff27a..e97014443 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -182,8 +182,9 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
 //--------------------------------------------------------------------+
 // CLASS-USBH API (don't require to verify parameters)
 //--------------------------------------------------------------------+
-void hub_init(void) {
+bool hub_init(void) {
   tu_memclr(hub_data, sizeof(hub_data));
+  return true;
 }
 
 bool hub_deinit(void) {
diff --git a/src/host/hub.h b/src/host/hub.h
index c3f4a3612..385efe6b2 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -187,16 +187,14 @@ bool hub_port_get_status    (uint8_t hub_addr, uint8_t hub_port, void* resp,
 bool hub_edpt_status_xfer(uint8_t dev_addr);
 
 // Reset a port
-static inline bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+TU_ATTR_ALWAYS_INLINE static inline
+bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_data);
 }
 
 // Clear Reset Change
-static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port,
-                                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+TU_ATTR_ALWAYS_INLINE static inline
+bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_data);
 }
 
@@ -204,7 +202,7 @@ static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_por
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void hub_init       (void);
+bool hub_init       (void);
 bool hub_deinit     (void);
 bool hub_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
 bool hub_set_config (uint8_t dev_addr, uint8_t itf_num);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index cf348bbb2..1edc43fd6 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -351,51 +351,55 @@ bool tuh_inited(void) {
 
 bool tuh_init(uint8_t rhport) {
   // skip if already initialized
-  if ( tuh_inited() ) return true;
+  if (tuh_rhport_is_active(rhport)) return true;
 
   TU_LOG_USBH("USBH init on controller %u\r\n", rhport);
-  TU_LOG_INT_USBH(sizeof(usbh_device_t));
-  TU_LOG_INT_USBH(sizeof(hcd_event_t));
-  TU_LOG_INT_USBH(sizeof(_ctrl_xfer));
-  TU_LOG_INT_USBH(sizeof(tuh_xfer_t));
-  TU_LOG_INT_USBH(sizeof(tu_fifo_t));
-  TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t));
 
-  // Event queue
-  _usbh_q = osal_queue_create( &_usbh_qdef );
-  TU_ASSERT(_usbh_q != NULL);
+  // Init host stack if not already
+  if (!tuh_inited()) {
+    TU_LOG_INT_USBH(sizeof(usbh_device_t));
+    TU_LOG_INT_USBH(sizeof(hcd_event_t));
+    TU_LOG_INT_USBH(sizeof(_ctrl_xfer));
+    TU_LOG_INT_USBH(sizeof(tuh_xfer_t));
+    TU_LOG_INT_USBH(sizeof(tu_fifo_t));
+    TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t));
+
+    // Event queue
+    _usbh_q = osal_queue_create(&_usbh_qdef);
+    TU_ASSERT(_usbh_q != NULL);
 
 #if OSAL_MUTEX_REQUIRED
-  // Init mutex
-  _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
-  TU_ASSERT(_usbh_mutex);
+    // Init mutex
+    _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
+    TU_ASSERT(_usbh_mutex);
 #endif
 
-  // Get application driver if available
-  if ( usbh_app_driver_get_cb ) {
-    _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
-  }
+    // Get application driver if available
+    if (usbh_app_driver_get_cb) {
+      _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
+    }
 
-  // Device
-  tu_memclr(&_dev0, sizeof(_dev0));
-  tu_memclr(_usbh_devices, sizeof(_usbh_devices));
-  tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
+    // Device
+    tu_memclr(&_dev0, sizeof(_dev0));
+    tu_memclr(_usbh_devices, sizeof(_usbh_devices));
+    tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
 
-  for(uint8_t i=0; i<TOTAL_DEVICES; i++) {
-    clear_device(&_usbh_devices[i]);
-  }
+    for (uint8_t i = 0; i < TOTAL_DEVICES; i++) {
+      clear_device(&_usbh_devices[i]);
+    }
 
-  // Class drivers
-  for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
-    usbh_class_driver_t const* driver = get_driver(drv_id);
-    if (driver) {
-      TU_LOG_USBH("%s init\r\n", driver->name);
-      driver->init();
+    // Class drivers
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+      usbh_class_driver_t const* driver = get_driver(drv_id);
+      if (driver) {
+        TU_LOG_USBH("%s init\r\n", driver->name);
+        driver->init();
+      }
     }
   }
 
+  // Init host controller
   _usbh_controller = rhport;;
-
   TU_ASSERT(hcd_init(rhport));
   hcd_int_enable(rhport);
 
@@ -405,14 +409,31 @@ bool tuh_init(uint8_t rhport) {
 bool tuh_deinit(uint8_t rhport) {
   if (!tuh_rhport_is_active(rhport)) return true;
 
+  // deinit host controller
   hcd_int_disable(rhport);
   hcd_deinit(rhport);
 
   _usbh_controller = TUSB_INDEX_INVALID_8;
 
-  // no other controller is active, deinit the stack
+  // deinit host stack if no controller is active
   if (!tuh_inited()) {
+    // Class drivers
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+      usbh_class_driver_t const* driver = get_driver(drv_id);
+      if (driver) {
+        TU_LOG_USBH("%s deinit\r\n", driver->name);
+        driver->deinit();
+      }
+    }
+
+    osal_queue_delete(_usbh_q);
+    _usbh_q = NULL;
 
+    #if OSAL_MUTEX_REQUIRED
+    // TODO make sure there is no task waiting on this mutex
+    osal_mutex_delete(_usbh_mutex);
+    _usbh_mutex = NULL;
+    #endif
   }
 
   return true;
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 204315175..95de915e9 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -51,7 +51,7 @@ enum {
 
 typedef struct {
   char const* name;
-  void (* const init       )(void);
+  bool (* const init       )(void);
   bool (* const deinit     )(void);
   bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
   bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
-- 
cgit v1.3.1


From a7a65e5d6d43fbb0c07eb82b3ab9fd8286dd3013 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Mar 2024 18:30:03 +0700
Subject: add delete API for rtthread

---
 src/osal/osal_rtthread.h | 54 +++++++++++++++++++++++++++++-------------------
 1 file changed, 33 insertions(+), 21 deletions(-)

(limited to 'src')

diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index a8423086f..c27814835 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -48,23 +48,27 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
 typedef struct rt_semaphore osal_semaphore_def_t;
 typedef rt_sem_t osal_semaphore_t;
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t
-osal_semaphore_create(osal_semaphore_def_t *semdef) {
-    rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_PRIO);
-    return semdef;
+TU_ATTR_ALWAYS_INLINE static inline
+osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) {
+  rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_PRIO);
+  return semdef;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) {
+  return RT_EOK == rt_sem_detach(semd_hdl);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
-    (void) in_isr;
-    return rt_sem_release(sem_hdl) == RT_EOK;
+  (void) in_isr;
+  return rt_sem_release(sem_hdl) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
-    return rt_sem_take(sem_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
+  return rt_sem_take(sem_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
-    rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, 0);
+  rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, 0);
 }
 
 //--------------------------------------------------------------------+
@@ -74,16 +78,20 @@ typedef struct rt_mutex osal_mutex_def_t;
 typedef rt_mutex_t osal_mutex_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
-    rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_PRIO);
-    return mdef;
+  rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_PRIO);
+  return mdef;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) {
+  return RT_EOK == rt_mutex_detach(mutex_hdl);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
-    return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
+  return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
-    return rt_mutex_release(mutex_hdl) == RT_EOK;
+  return rt_mutex_release(mutex_hdl) == RT_EOK;
 }
 
 //--------------------------------------------------------------------+
@@ -106,27 +114,31 @@ typedef struct {
 typedef rt_mq_t osal_queue_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) {
-    rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz,
-               qdef->item_sz * qdef->depth, RT_IPC_FLAG_PRIO);
-    return &(qdef->sq);
+  rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz,
+             qdef->item_sz * qdef->depth, RT_IPC_FLAG_PRIO);
+  return &(qdef->sq);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) {
+  return RT_EOK == rt_mq_detach(qhdl);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void *data, uint32_t msec) {
-    rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec);
+  rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec);
 #if RT_VERSION_MAJOR >= 5
-    return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) > 0;
+  return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) > 0;
 #else
-    return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK;
+  return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK;
 #endif  /* RT_VERSION_MAJOR >= 5 */
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
-    (void) in_isr;
-    return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK;
+  (void) in_isr;
+  return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
-    return (qhdl->entry) == 0;
+  return (qhdl->entry) == 0;
 }
 
 #ifdef __cplusplus
-- 
cgit v1.3.1


From 0610070d07babf3623016603325afa938d4fc9f7 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 25 Mar 2024 18:44:51 +0700
Subject: Update dcd_stm32_fsdev_pvt_st.h

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index e0df21860..5a129ecf8 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -296,17 +296,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB
 {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
-  volatile uint32_t count = 10;
-  /*
-  WA: few cycles for RX PMA descriptor to update
-  This workaround is ported from stm32h5xx_hal_pcd.h : PCD_GET_EP_RX_CNT H5
-  This code fixes an issue when the code is compiled in GCC with a fast optimization(O2/O3) and device with an high frequency.
-  The function doesn't return the correct value.
-  Issue observed on Windows 10 and stm32h573i_dk and tud_task() scheduled by IT, the device is not migrated the USB device is not visible .
+  /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value.
+     Note: required for G0, U5, H5 etc. 
+  This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough.
+  Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. 
+  Observed on Windows 10 where tud_task() is scheduled by interrupt handler.
   */
-  while (count > 0U)
-  {
-    asm("NOP");
+  volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
+  while (count > 0U) {
     count--;
   }
   return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
-- 
cgit v1.3.1


From 29f016ae15eb94654748bf29b81557f6ab611384 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 25 Mar 2024 18:59:05 +0700
Subject: fix pre-commit

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 5a129ecf8..ade64b4fb 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -297,9 +297,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value.
-     Note: required for G0, U5, H5 etc. 
+     Note: required for G0, U5, H5 etc.
   This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough.
-  Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency. 
+  Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency.
   Observed on Windows 10 where tud_task() is scheduled by interrupt handler.
   */
   volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
-- 
cgit v1.3.1


From fbb20373c1b22c8eb1aed4fa95972c851be819f3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Mar 2024 10:26:42 +0700
Subject: implement hcd_deinit() for max3421

---
 src/portable/analog/max3421/hcd_max3421.c | 35 ++++++++++++++++++++++++-------
 1 file changed, 27 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index cc4799dd6..d70cf7208 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -321,35 +321,35 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
 }
 
 //------------- register write helper -------------//
-static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
   reg_write(rhport, HIRQ_ADDR, data, in_isr);
   // HIRQ write 1 is clear
   _hcd_data.hirq &= (uint8_t) ~data;
 }
 
-static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hien = data;
   reg_write(rhport, HIEN_ADDR, data, in_isr);
 }
 
-static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.mode = data;
   reg_write(rhport, MODE_ADDR, data, in_isr);
 }
 
-static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
   if ( _hcd_data.peraddr == data ) return; // no need to change address
 
   _hcd_data.peraddr = data;
   reg_write(rhport, PERADDR_ADDR, data, in_isr);
 }
 
-static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hxfr = data;
   reg_write(rhport, HXFR_ADDR, data, in_isr);
 }
 
-static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.sndbc = data;
   reg_write(rhport, SNDBC_ADDR, data, in_isr);
 }
@@ -449,7 +449,7 @@ bool hcd_init(uint8_t rhport) {
   // full duplex, interrupt negative edge
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
-  // V1 is 0x01, V2 is 0x12, V3 is 0x13
+  // v1 is 0x01, v2 is 0x12, v3 is 0x13
   uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
   TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
   TU_LOG2_HEX(revision);
@@ -481,6 +481,24 @@ bool hcd_init(uint8_t rhport) {
   return true;
 }
 
+bool hcd_deinit(uint8_t rhport) {
+  (void) rhport;
+
+  // disable interrupt
+  tuh_max3421_int_api(rhport, false);
+
+  // reset max3421
+  reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
+  reg_write(rhport, USBCTL_ADDR, 0, false);
+
+  #if OSAL_MUTEX_REQUIRED
+  osal_mutex_delete(_hcd_data.spi_mutex);
+  _hcd_data.spi_mutex = NULL;
+  #endif
+
+  return true;
+}
+
 // Enable USB interrupt
 // Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
@@ -598,7 +616,8 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   hxfr_write(rhport, hxfr, in_isr);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline
+void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   if (ep->ep_num == 0 ) {
     // setup
     if (ep->is_setup) {
-- 
cgit v1.3.1


From 9fdb1c1684c653426d4f616d788b329ee528110a Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Tue, 26 Mar 2024 08:10:32 +0100
Subject: draft MAX3421E NAK retry handling next frame

---
 src/portable/analog/max3421/hcd_max3421.c | 45 ++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index d70cf7208..d366298ea 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -28,6 +28,8 @@
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
+#define NAK_RETRY_HANDLING 1
+
 #include <stdatomic.h>
 #include "host/hcd.h"
 
@@ -180,6 +182,9 @@ typedef struct {
     uint8_t data_toggle   : 1;
     uint8_t xfer_pending  : 1;
     uint8_t xfer_complete : 1;
+#if NAK_RETRY_HANDLING
+    uint8_t retry_pending : 1;
+#endif
   };
 
   struct TU_ATTR_PACKED {
@@ -593,7 +598,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   }
 
   uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
+//  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
   if (xact_len) {
     fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
   }
@@ -803,6 +808,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
   xfer_result_t xfer_result;
   switch(hresult) {
     case HRSL_SUCCESS:
+//      putchar('S');
       xfer_result = XFER_RESULT_SUCCESS;
       break;
 
@@ -811,6 +817,19 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
       break;
 
     case HRSL_NAK:
+//      putchar('N');
+#if NAK_RETRY_HANDLING
+      ep->retry_pending = 1;
+      ep->xfer_pending = 0;
+      max3421_ep_t * next_ep = find_next_pending_ep(ep);
+      if (next_ep) {
+        // switch to next pending TODO could have issue with double buffered if not clear previously out data
+        xact_inout(rhport, next_ep, true, in_isr);
+      } else {
+        // no more pending
+        atomic_flag_clear(&_hcd_data.busy);
+      }
+#else
       if (ep_num == 0) {
         // NAK on control, retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
@@ -828,6 +847,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
           TU_ASSERT(false,);
         }
       }
+#endif
       return;
 
     case HRSL_BAD_REQ:
@@ -909,6 +929,29 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
+
+#if NAK_RETRY_HANDLING
+    // retry EPs
+    max3421_ep_t * next_ep = NULL;
+    for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+      max3421_ep_t * ep = &_hcd_data.ep[i];
+      // set retryable EPs to pending
+      if (ep->retry_pending) {
+//        putchar('R');
+        ep->xfer_pending = 1;
+        ep->retry_pending = 0;
+        if (next_ep == NULL) {
+          next_ep = &_hcd_data.ep[i];
+        }
+      }
+    }
+    // trigger 1st retryable EP
+    if (next_ep) {
+      if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
+        xact_inout(rhport, next_ep, true, in_isr);
+      }
+    }
+#endif
   }
 
   if (hirq & HIRQ_CONDET_IRQ) {
-- 
cgit v1.3.1


From 307cce92c4f630ab988e6eb1e77685bc1e82d85a Mon Sep 17 00:00:00 2001
From: Camila <s1000325098@senor0lunlx0455.eu.sony.com>
Date: Tue, 26 Mar 2024 18:40:22 +0100
Subject: Improved SDK 3.2.0 compatibility

- Used usbdev_allocreq for compatibility with SDK 3.2.0
- Wrapped previous code in #ifdef for legacy compatibility
---
 src/portable/sony/cxd56/dcd_cxd56.c | 29 ++++++++++-------------------
 1 file changed, 10 insertions(+), 19 deletions(-)

(limited to 'src')

diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index 9a939bc6c..83cd0718c 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -39,25 +39,6 @@
 #define CXD56_SETUP_QUEUE_DEPTH (4)
 #define CXD56_MAX_DATA_OUT_SIZE (64)
 
-/* Allocate/free I/O requests.
- * Should not be called from interrupt processing!
- */
-
-#define EP_ALLOCREQ(ep)            (ep)->ops->allocreq(ep)
-#define EP_FREEREQ(ep,req)         (ep)->ops->freereq(ep,req)
-
-/* Allocate/free an I/O buffer.
- * Should not be called from interrupt processing!
- */
-
-#ifdef CONFIG_USBDEV_DMA
-#  define EP_ALLOCBUFFER(ep,nb)    (ep)->ops->allocbuffer(ep,nb)
-#  define EP_FREEBUFFER(ep,buf)    (ep)->ops->freebuffer(ep,buf)
-#else
-#  define EP_ALLOCBUFFER(ep,nb)    kmm_malloc(nb)
-#  define EP_FREEBUFFER(ep,buf)    kmm_free(buf)
-#endif
-
 OSAL_QUEUE_DEF(usbd_int_set, _setup_queue_def, CXD56_SETUP_QUEUE_DEPTH, struct usb_ctrlreq_s);
 
 struct usbdcd_driver_s
@@ -121,6 +102,7 @@ static int _dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_
   usbdev = dev;
   usbdcd_driver.ep[0] = dev->ep0;
 
+  #ifdef EP_ALLOCREQ
   usbdcd_driver.req[0] = EP_ALLOCREQ(usbdcd_driver.ep[0]);
   if (usbdcd_driver.req[0] != NULL)
   {
@@ -132,6 +114,9 @@ static int _dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_
       usbdcd_driver.req[0] = NULL;
     }
   }
+  #else
+  usbdcd_driver.req[0] = usbdev_allocreq(usbdcd_driver.ep[0],64);
+  #endif
 
   usbdcd_driver.req[0]->callback = usbdcd_ep0incomplete;
 
@@ -314,12 +299,18 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   }
 
   usbdcd_driver.req[epnum] = NULL;
+
+  #ifdef EP_ALLOCREQ
   usbdcd_driver.req[epnum] = EP_ALLOCREQ(usbdcd_driver.ep[epnum]);
   if (usbdcd_driver.req[epnum] != NULL)
   {
     usbdcd_driver.req[epnum]->len = ep_mps;
   }
   else
+  #else
+  usbdcd_driver.req[epnum] = usbdev_allocreq(usbdcd_driver.ep[epnum], ep_mps);
+  if(usbdcd_driver.req[epnum] == NULL)
+  #endif
   {
     return false;
   }
-- 
cgit v1.3.1


From 0da1da942a735bcac7b48786a511a38b02519e88 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Mar 2024 16:32:02 +0700
Subject: enhance hub removal using while loop to unroll recursive instead of
 event queue.

---
 src/host/usbh.c | 117 +++++++++++++++++++++++++++-----------------------------
 1 file changed, 57 insertions(+), 60 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 1edc43fd6..71691fad6 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1138,43 +1138,42 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
   TU_VERIFY(_async_func(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \
   return (uint8_t) result
 
-uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index,
+                                void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get, daddr, type, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_device, daddr, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index,
+                                              void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_configuration, daddr, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index,
+                                           void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, daddr, itf_num, desc_type, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id,
+                                       void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_string, daddr, index, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id,
+                                                    void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, daddr, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id,
+                                               void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_product_string, daddr, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
-{
+uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id,
+                                              void* buffer, uint16_t len) {
   _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len);
 }
 
@@ -1210,57 +1209,55 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) {
 static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
   // TODO mark as disconnected in ISR, also handle dev0
+  uint32_t removing_hubs = 0;
+  do {
+    for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
+      usbh_device_t* dev = &_usbh_devices[dev_id];
+      uint8_t const daddr = dev_id + 1;
+
+      // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
+      if (dev->rhport == rhport && dev->connected &&
+          (hub_addr == 0 || dev->hub_addr == hub_addr) &&
+          (hub_port == 0 || dev->hub_port == hub_port)) {
+        TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
+
+        if (is_hub_addr(daddr)) {
+          TU_LOG_USBH("  is a HUB device %u\r\n", daddr);
+          // marking this hub to run the loop on its children next (unroll recursive)
+          removing_hubs |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX);
+        } else {
+          // Invoke callback before closing driver (maybe call it later ?)
+          if (tuh_umount_cb) tuh_umount_cb(daddr);
+        }
 
-#if 0
-  // index as hub addr, value is hub port (0xFF for invalid)
-  uint8_t removing_hubs[CFG_TUH_HUB];
-  memset(removing_hubs, TUSB_INDEX_INVALID_8, sizeof(removing_hubs));
-
-  removing_hubs[hub_addr-CFG_TUH_DEVICE_MAX] = hub_port;
+        // Close class driver
+        for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+          usbh_class_driver_t const* driver = get_driver(drv_id);
+          if (driver) driver->close(daddr);
+        }
 
-  // consecutive non-removing hub
-  uint8_t nop_count = 0;
-#endif
+        hcd_device_close(rhport, daddr);
+        clear_device(dev);
 
-  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
-    usbh_device_t *dev = &_usbh_devices[dev_id];
-    uint8_t const daddr = dev_id + 1;
-
-    // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
-    if (dev->rhport == rhport && dev->connected &&
-        (hub_addr == 0 || dev->hub_addr == hub_addr) &&
-        (hub_port == 0 || dev->hub_port == hub_port)) {
-      TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
-
-      if (is_hub_addr(daddr)) {
-        TU_LOG_USBH("  is a HUB device %u\r\n", daddr);
-
-        // Submit removed event If the device itself is a hub (un-rolled recursive)
-        // TODO a better to unroll recursrive is using array of removing_hubs and mark it here
-        hcd_event_t event;
-        event.rhport = rhport;
-        event.event_id = HCD_EVENT_DEVICE_REMOVE;
-        event.connection.hub_addr = daddr;
-        event.connection.hub_port = 0;
-
-        hcd_event_handler(&event, false);
-      } else {
-        // Invoke callback before closing driver (maybe call it later ?)
-        if (tuh_umount_cb) tuh_umount_cb(daddr);
+        // abort on-going control xfer on this device if any
+        if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
       }
+    }
 
-      // Close class driver
-      for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
-        usbh_class_driver_t const * driver = get_driver(drv_id);
-        if ( driver ) driver->close(daddr);
-      }
+    if (removing_hubs == 0) break;
+
+    // find the next hub to process
+    for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) {
+      if (tu_bit_test(removing_hubs, h_id)) {
+        removing_hubs &= ~TU_BIT(h_id);
 
-      hcd_device_close(rhport, daddr);
-      clear_device(dev);
-      // abort on-going control xfer if any
-      if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
+        // update hub_addr and hub_port for next loop
+        hub_addr = h_id + 1 + CFG_TUH_DEVICE_MAX;
+        hub_port = 0;
+        break;
+      }
     }
-  }
+  } while(1);
 }
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 3dcb7362aa8f0e710157da4b28be44abb2c26230 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Mar 2024 19:18:20 +0700
Subject: fix build when CFG_TUH_HUB == 0

---
 src/host/usbh.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 71691fad6..f2dc2f7c1 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1219,11 +1219,10 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       if (dev->rhport == rhport && dev->connected &&
           (hub_addr == 0 || dev->hub_addr == hub_addr) &&
           (hub_port == 0 || dev->hub_port == hub_port)) {
-        TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
+        TU_LOG_USBH("[%u:%u:%u] unplugged address = %u\r\n", rhport, hub_addr, hub_port, daddr);
 
         if (is_hub_addr(daddr)) {
           TU_LOG_USBH("  is a HUB device %u\r\n", daddr);
-          // marking this hub to run the loop on its children next (unroll recursive)
           removing_hubs |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX);
         } else {
           // Invoke callback before closing driver (maybe call it later ?)
@@ -1244,9 +1243,11 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       }
     }
 
+    // if removing a hub, we need to remove its downstream devices
+    #if CFG_TUH_HUB
     if (removing_hubs == 0) break;
 
-    // find the next hub to process
+    // find a marked hub to process
     for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) {
       if (tu_bit_test(removing_hubs, h_id)) {
         removing_hubs &= ~TU_BIT(h_id);
@@ -1257,6 +1258,10 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
         break;
       }
     }
+    #else
+    (void) removing_hubs;
+    break;
+    #endif
   } while(1);
 }
 
-- 
cgit v1.3.1


From d50003e33d89740c0993ae236629392df82453c2 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 27 Mar 2024 11:21:13 -0700
Subject: Fake unplug devices when a root hub is deinit

---
 src/host/usbh.c | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index f2dc2f7c1..29c6eb1e9 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -415,6 +415,15 @@ bool tuh_deinit(uint8_t rhport) {
 
   _usbh_controller = TUSB_INDEX_INVALID_8;
 
+  // "unplug" all devices on this rhport
+  for (uint8_t idx = 0; idx < CFG_TUH_DEVICE_MAX + CFG_TUH_HUB; idx++) {
+    usbh_device_t *dev = &_usbh_devices[idx];
+    if (!dev->connected || dev->rhport != rhport) {
+      continue;
+    }
+    process_removing_device(rhport, dev->hub_addr, dev->hub_port);
+  }
+
   // deinit host stack if no controller is active
   if (!tuh_inited()) {
     // Class drivers
-- 
cgit v1.3.1


From ddb1034a9c77d8ef4efccf3df76013f86efe5e09 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Mar 2024 21:45:52 +0700
Subject: use hub_addr=0, hub_port=0 for removing root hub port

---
 src/host/usbh.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 29c6eb1e9..05091736e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -412,17 +412,10 @@ bool tuh_deinit(uint8_t rhport) {
   // deinit host controller
   hcd_int_disable(rhport);
   hcd_deinit(rhport);
-
   _usbh_controller = TUSB_INDEX_INVALID_8;
 
-  // "unplug" all devices on this rhport
-  for (uint8_t idx = 0; idx < CFG_TUH_DEVICE_MAX + CFG_TUH_HUB; idx++) {
-    usbh_device_t *dev = &_usbh_devices[idx];
-    if (!dev->connected || dev->rhport != rhport) {
-      continue;
-    }
-    process_removing_device(rhport, dev->hub_addr, dev->hub_port);
-  }
+  // "unplug" all devices on this rhport (hub_addr = 0, hub_port = 0)
+  process_removing_device(rhport, 0, 0);
 
   // deinit host stack if no controller is active
   if (!tuh_inited()) {
-- 
cgit v1.3.1


From b9400df4c8bd49f1dd1e3047ca2a2c0284fa785e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Mar 2024 11:23:36 +0700
Subject: fix rp2 debug build with level 3

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 08aef9314..b351a9a07 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -113,7 +113,7 @@ static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_en
 static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
   uint32_t remaining_buffers = usb_hw->buf_status;
-  pico_trace("buf_status 0x%08x\n", remaining_buffers);
+  pico_trace("buf_status 0x%08lx\n", remaining_buffers);
 
   // Check EPX first
   uint bit = 0b1;
@@ -325,10 +325,8 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
   ep->wMaxPacketSize = wMaxPacketSize;
   ep->transfer_type = transfer_type;
 
-  pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
-             ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
-  pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
-             ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
+  pico_trace("hw_endpoint_init dev %d ep %02X xfer %d\n", ep->dev_addr, ep->ep_addr, ep->transfer_type);
+  pico_trace("dev %d ep %02X setup buffer @ 0x%p\n", ep->dev_addr, ep->ep_addr, ep->hw_data_buf);
   uint dpram_offset = hw_data_offset(ep->hw_data_buf);
   // Bits 0-5 should be 0
   assert(!(dpram_offset & 0b111111));
@@ -343,7 +341,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
     ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
   }
   *ep->endpoint_control = ep_reg;
-  pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
+  pico_trace("endpoint control (0x%p) <- 0x%lx\n", ep->endpoint_control, ep_reg);
   ep->configured = true;
 
   if ( ep != &epx )
-- 
cgit v1.3.1


From cab11064160deab42af654cd766bbfaca7f688cd Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 21 Nov 2023 18:06:57 +0100
Subject: dwc2: add endpoint allocation support.

---
 src/class/audio/audio_device.c        |   4 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c | 102 ++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 4adc558a6..293defd96 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -96,8 +96,8 @@
   #define  USE_LINEAR_BUFFER     1
 #endif
 
-// Temporarily put the check here for stm32_fsdev
-#ifdef TUP_USBIP_FSDEV
+// Temporarily put the check here
+#if defined(TUP_USBIP_FSDEV) || defined(TUP_USBIP_DWC2)
   #define  USE_ISO_EP_ALLOCATION   1
 #else
   #define  USE_ISO_EP_ALLOCATION   0
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 3f00243e5..b0149a9a9 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -648,6 +648,108 @@ void dcd_edpt_close_all(uint8_t rhport) {
   _allocated_fifo_words_tx = 16;
 }
 
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
+{
+  (void)rhport;
+
+  TU_ASSERT(largest_packet_size <= 1024);
+
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  TU_ASSERT(epnum < ep_count);
+
+  uint16_t const fifo_size = tu_div_ceil(largest_packet_size, 4);
+
+  if (dir == TUSB_DIR_OUT) {
+    // Calculate required size of RX FIFO
+    uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
+
+    // If size_rx needs to be extended check if possible and if so enlarge it
+    if (dwc2->grxfsiz < sz) {
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
+
+      // Enlarge RX FIFO
+      dwc2->grxfsiz = sz;
+    }
+
+  } else
+  {
+    // "USB Data FIFOs" section in reference manual
+    // Peripheral FIFO architecture
+    //
+    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+    // | IN FIFO 0   |
+    // --------------- (320 or 1024) - 16
+    // | IN FIFO 1   |
+    // --------------- (320 or 1024) - 16 - x
+    // |   . . . .   |
+    // --------------- (320 or 1024) - 16 - x - y - ... - z
+    // | IN FIFO MAX |
+    // ---------------
+    // |    FREE     |
+    // --------------- GRXFSIZ
+    // | OUT FIFO    |
+    // | ( Shared )  |
+    // --------------- 0
+    //
+    // In FIFO is allocated by following rules:
+    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
+
+    // Check if free space is available
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
+
+    _allocated_fifo_words_tx += fifo_size;
+
+    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size * 4,
+           _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
+
+    // DIEPTXF starts at FIFO #1.
+    // Both TXFD and TXSA are in unit of 32-bit words.
+    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
+                               (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
+  }
+
+  return true;
+}
+
+bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void)rhport;
+
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
+  xfer->interval = p_endpoint_desc->bInterval;
+
+  if (dir == TUSB_DIR_OUT) {
+    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) |
+                                  (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
+                                  (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+                                  (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+
+    dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
+  } else
+  {
+    dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
+                                 (epnum << DIEPCTL_TXFNUM_Pos) |
+                                 (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
+                                 (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
+                                 (xfer->max_size << DIEPCTL_MPSIZ_Pos);
+
+    dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
+  }
+
+  return true;
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
-- 
cgit v1.3.1


From 4116a962a6c3073e6c617797e3d87643eafc4375 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Thu, 23 Nov 2023 19:20:03 +0100
Subject: Flush FIFO on bus reset.

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index b0149a9a9..a411b54f4 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -139,6 +139,14 @@ static void bus_reset(uint8_t rhport) {
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
+  // flush all TX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
+  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+
+  // flush RX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_RXFFLSH;
+  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+
   // 2. Set up interrupt mask
   dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
   dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-- 
cgit v1.3.1


From 8055bc88d8f606c1f69d669a1c022d1a7bca44a2 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 12 Jan 2024 15:59:51 +0100
Subject: Code refactor.

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 375 ++++++++++++++--------------------
 1 file changed, 157 insertions(+), 218 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index a411b54f4..f302b29b3 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -121,6 +121,155 @@ static void update_grxfsiz(uint8_t rhport) {
   dwc2->grxfsiz = calc_grxfsiz(max_epsize, ep_count);
 }
 
+static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size)
+{
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  TU_ASSERT(epnum < ep_count);
+
+  uint16_t const fifo_size = tu_div_ceil(packet_size, 4);
+
+  if (dir == TUSB_DIR_OUT) {
+    // Calculate required size of RX FIFO
+    uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
+
+    // If size_rx needs to be extended check if possible and if so enlarge it
+    if (dwc2->grxfsiz < sz) {
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
+
+      // Enlarge RX FIFO
+      dwc2->grxfsiz = sz;
+    }
+
+  } else
+  {
+    // "USB Data FIFOs" section in reference manual
+    // Peripheral FIFO architecture
+    //
+    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+    // | IN FIFO 0   |
+    // --------------- (320 or 1024) - 16
+    // | IN FIFO 1   |
+    // --------------- (320 or 1024) - 16 - x
+    // |   . . . .   |
+    // --------------- (320 or 1024) - 16 - x - y - ... - z
+    // | IN FIFO MAX |
+    // ---------------
+    // |    FREE     |
+    // --------------- GRXFSIZ
+    // | OUT FIFO    |
+    // | ( Shared )  |
+    // --------------- 0
+    //
+    // In FIFO is allocated by following rules:
+    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
+
+    // Check if free space is available
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
+
+    _allocated_fifo_words_tx += fifo_size;
+
+    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size * 4,
+           _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
+
+    // DIEPTXF starts at FIFO #1.
+    // Both TXFD and TXSA are in unit of 32-bit words.
+    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
+                               (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
+  }
+
+  return true;
+}
+
+static void edpt_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+
+  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
+  xfer->interval = p_endpoint_desc->bInterval;
+
+  if (dir == TUSB_DIR_OUT) {
+    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) |
+                                  (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
+                                  (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+                                  (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+
+    dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
+  } else
+  {
+    dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
+                                 (epnum << DIEPCTL_TXFNUM_Pos) |
+                                 (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
+                                 (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
+                                 (xfer->max_size << DIEPCTL_MPSIZ_Pos);
+
+    dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
+  }
+}
+
+static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
+  (void) rhport;
+
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  if (dir == TUSB_DIR_IN) {
+    dwc2_epin_t* epin = dwc2->epin;
+
+    // Only disable currently enabled non-control endpoint
+    if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) {
+      epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+    } else {
+      // Stop transmitting packets and NAK IN xfers.
+      epin[epnum].diepctl |= DIEPCTL_SNAK;
+      while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {}
+
+      // Disable the endpoint.
+      epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {}
+
+      epin[epnum].diepint = DIEPINT_EPDISD;
+    }
+
+    // Flush the FIFO, and wait until we have confirmed it cleared.
+    dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
+    while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {}
+  } else {
+    dwc2_epout_t* epout = dwc2->epout;
+
+    // Only disable currently enabled non-control endpoint
+    if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) {
+      epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
+    } else {
+      // Asserting GONAK is required to STALL an OUT endpoint.
+      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
+      // anyway, and it can't be cleared by user code. If this while loop never
+      // finishes, we have bigger problems than just the stack.
+      dwc2->dctl |= DCTL_SGONAK;
+      while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
+
+      // Ditto here- disable the endpoint.
+      epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {}
+
+      epout[epnum].doepint = DOEPINT_EPDISD;
+
+      // Allow other OUT endpoints to keep receiving.
+      dwc2->dctl |= DCTL_CGONAK;
+    }
+  }
+}
+
 // Start of Bus Reset
 static void bus_reset(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
@@ -555,81 +704,9 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
   (void) rhport;
 
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+  TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
 
-  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
-  TU_ASSERT(epnum < ep_count);
-
-  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = tu_edpt_packet_size(desc_edpt);
-  xfer->interval = desc_edpt->bInterval;
-
-  uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4);
-
-  if (dir == TUSB_DIR_OUT) {
-    // Calculate required size of RX FIFO
-    uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
-
-    // If size_rx needs to be extended check if possible and if so enlarge it
-    if (dwc2->grxfsiz < sz) {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
-
-      // Enlarge RX FIFO
-      dwc2->grxfsiz = sz;
-    }
-
-    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) |
-                                  (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
-                                  (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
-                                  (xfer->max_size << DOEPCTL_MPSIZ_Pos);
-
-    dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
-  } else {
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO 0   |
-    // --------------- (320 or 1024) - 16
-    // | IN FIFO 1   |
-    // --------------- (320 or 1024) - 16 - x
-    // |   . . . .   |
-    // --------------- (320 or 1024) - 16 - x - y - ... - z
-    // | IN FIFO MAX |
-    // ---------------
-    // |    FREE     |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // In FIFO is allocated by following rules:
-    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
-    // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
-
-    _allocated_fifo_words_tx += fifo_size;
-
-    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size * 4,
-           _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
-
-    // DIEPTXF starts at FIFO #1.
-    // Both TXFD and TXSA are in unit of 32-bit words.
-    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
-                               (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
-
-    dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
-                                 (epnum << DIEPCTL_TXFNUM_Pos) |
-                                 (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
-                                 (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
-                                 (xfer->max_size << DIEPCTL_MPSIZ_Pos);
-
-    dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
-  }
+  edpt_activate(rhport, desc_edpt);
 
   return true;
 }
@@ -658,102 +735,17 @@ void dcd_edpt_close_all(uint8_t rhport) {
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
 {
-  (void)rhport;
-
-  TU_ASSERT(largest_packet_size <= 1024);
-
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir = tu_edpt_dir(ep_addr);
-
-  TU_ASSERT(epnum < ep_count);
-
-  uint16_t const fifo_size = tu_div_ceil(largest_packet_size, 4);
-
-  if (dir == TUSB_DIR_OUT) {
-    // Calculate required size of RX FIFO
-    uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
-
-    // If size_rx needs to be extended check if possible and if so enlarge it
-    if (dwc2->grxfsiz < sz) {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
-
-      // Enlarge RX FIFO
-      dwc2->grxfsiz = sz;
-    }
-
-  } else
-  {
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO 0   |
-    // --------------- (320 or 1024) - 16
-    // | IN FIFO 1   |
-    // --------------- (320 or 1024) - 16 - x
-    // |   . . . .   |
-    // --------------- (320 or 1024) - 16 - x - y - ... - z
-    // | IN FIFO MAX |
-    // ---------------
-    // |    FREE     |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // In FIFO is allocated by following rules:
-    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
-    // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
-
-    _allocated_fifo_words_tx += fifo_size;
-
-    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size * 4,
-           _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
-
-    // DIEPTXF starts at FIFO #1.
-    // Both TXFD and TXSA are in unit of 32-bit words.
-    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
-                               (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
-  }
+  TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size));
 
   return true;
 }
 
 bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
 {
-  (void)rhport;
-
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
-  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-
-  xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
-  xfer->interval = p_endpoint_desc->bInterval;
+  // Disable EP to clear potential incomplete transfers
+  edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false);
 
-  if (dir == TUSB_DIR_OUT) {
-    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) |
-                                  (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
-                                  (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
-                                  (xfer->max_size << DOEPCTL_MPSIZ_Pos);
-
-    dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
-  } else
-  {
-    dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
-                                 (epnum << DIEPCTL_TXFNUM_Pos) |
-                                 (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
-                                 (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
-                                 (xfer->max_size << DIEPCTL_MPSIZ_Pos);
-
-    dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
-  }
+  edpt_activate(rhport, p_endpoint_desc);
 
   return true;
 }
@@ -815,60 +807,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
   return true;
 }
 
-static void dcd_edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
-  (void) rhport;
-
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir = tu_edpt_dir(ep_addr);
-
-  if (dir == TUSB_DIR_IN) {
-    dwc2_epin_t* epin = dwc2->epin;
-
-    // Only disable currently enabled non-control endpoint
-    if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) {
-      epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
-    } else {
-      // Stop transmitting packets and NAK IN xfers.
-      epin[epnum].diepctl |= DIEPCTL_SNAK;
-      while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {}
-
-      // Disable the endpoint.
-      epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
-      while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {}
-
-      epin[epnum].diepint = DIEPINT_EPDISD;
-    }
 
-    // Flush the FIFO, and wait until we have confirmed it cleared.
-    dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
-    while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {}
-  } else {
-    dwc2_epout_t* epout = dwc2->epout;
-
-    // Only disable currently enabled non-control endpoint
-    if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) {
-      epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
-    } else {
-      // Asserting GONAK is required to STALL an OUT endpoint.
-      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
-      // anyway, and it can't be cleared by user code. If this while loop never
-      // finishes, we have bigger problems than just the stack.
-      dwc2->dctl |= DCTL_SGONAK;
-      while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
-
-      // Ditto here- disable the endpoint.
-      epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
-      while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {}
-
-      epout[epnum].doepint = DOEPINT_EPDISD;
-
-      // Allow other OUT endpoints to keep receiving.
-      dwc2->dctl |= DCTL_CGONAK;
-    }
-  }
-}
 
 /**
  * Close an endpoint.
@@ -879,7 +818,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  dcd_edpt_disable(rhport, ep_addr, false);
+  edpt_disable(rhport, ep_addr, false);
 
   // Update max_size
   xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
@@ -897,7 +836,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
 }
 
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
-  dcd_edpt_disable(rhport, ep_addr, true);
+  edpt_disable(rhport, ep_addr, true);
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
-- 
cgit v1.3.1


From 85420c61c780e260d0afd21de4a39c17ceba5d87 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Mar 2024 13:49:41 +0700
Subject: minor clean up

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 104 ++++++++++++++--------------------
 1 file changed, 41 insertions(+), 63 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index f302b29b3..cf8f3be50 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -102,7 +102,13 @@ static bool _out_ep_closed;                   // Flag to check if RX FIFO size n
 // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
 static bool _sof_en;
 
-// Calculate the RX FIFO size according to recommendations from reference manual
+// Calculate the RX FIFO size according to minimum recommendations from reference manual
+// RxFIFO = (5 * number of control endpoints + 8) +
+//          ((largest USB packet used / 4) + 1 for status information) +
+//          (2 * number of OUT endpoints) + 1 for Global NAK
+// with number of control endpoints = 1 we have
+// RxFIFO = 15 + (largest USB packet used / 4) + 2 * number of OUT endpoints
+// we double the largest USB packet size to be able to hold up to 2 packets
 static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
   return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
 }
@@ -121,11 +127,9 @@ static void update_grxfsiz(uint8_t rhport) {
   dwc2->grxfsiz = calc_grxfsiz(max_epsize, ep_count);
 }
 
-static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size)
-{
+static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
 
@@ -133,6 +137,26 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size)
 
   uint16_t const fifo_size = tu_div_ceil(packet_size, 4);
 
+  // "USB Data FIFOs" section in reference manual
+  // Peripheral FIFO architecture
+  //
+  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+  // | IN FIFO 0   |
+  // --------------- (320 or 1024) - 16
+  // | IN FIFO 1   |
+  // --------------- (320 or 1024) - 16 - x
+  // |   . . . .   |
+  // --------------- (320 or 1024) - 16 - x - y - ... - z
+  // | IN FIFO MAX |
+  // ---------------
+  // |    FREE     |
+  // --------------- GRXFSIZ
+  // | OUT FIFO    |
+  // | ( Shared )  |
+  // --------------- 0
+  //
+  // In FIFO is allocated by following rules:
+  // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
   if (dir == TUSB_DIR_OUT) {
     // Calculate required size of RX FIFO
     uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
@@ -144,35 +168,10 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size)
       // Enlarge RX FIFO
       dwc2->grxfsiz = sz;
     }
-
-  } else
-  {
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO 0   |
-    // --------------- (320 or 1024) - 16
-    // | IN FIFO 1   |
-    // --------------- (320 or 1024) - 16 - x
-    // |   . . . .   |
-    // --------------- (320 or 1024) - 16 - x - y - ... - z
-    // | IN FIFO MAX |
-    // ---------------
-    // |    FREE     |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // In FIFO is allocated by following rules:
-    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
+  } else {
     // Check if free space is available
     TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
-
     _allocated_fifo_words_tx += fifo_size;
-
     TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size * 4,
            _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
 
@@ -185,10 +184,8 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size)
   return true;
 }
 
-static void edpt_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
-{
+static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
   uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
 
@@ -196,21 +193,17 @@ static void edpt_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoi
   xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
   xfer->interval = p_endpoint_desc->bInterval;
 
-  if (dir == TUSB_DIR_OUT) {
-    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) |
-                                  (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
-                                  (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
-                                  (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+  // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints.
+  uint32_t const dxepctl = (1 << DOEPCTL_USBAEP_Pos) |
+                           (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
+                           (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+                           (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
+  if (dir == TUSB_DIR_OUT) {
+    dwc2->epout[epnum].doepctl |= dxepctl;
     dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
-  } else
-  {
-    dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
-                                 (epnum << DIEPCTL_TXFNUM_Pos) |
-                                 (p_endpoint_desc->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
-                                 (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
-                                 (xfer->max_size << DIEPCTL_MPSIZ_Pos);
-
+  } else {
+    dwc2->epin[epnum].diepctl |= dxepctl | (epnum << DIEPCTL_TXFNUM_Pos);
     dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
   }
 }
@@ -219,7 +212,6 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
   (void) rhport;
 
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir = tu_edpt_dir(ep_addr);
 
@@ -426,7 +418,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 /* Controller API
  *------------------------------------------------------------------*/
 #if CFG_TUSB_DEBUG >= DWC2_DEBUG
-
 void print_dwc2_info(dwc2_regs_t* dwc2) {
   // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
   // use dwc2_info.py/md for bit-field value and comparison with other ports
@@ -437,7 +428,6 @@ void print_dwc2_info(dwc2_regs_t* dwc2) {
   }
   TU_LOG(DWC2_DEBUG, "0x%08lX\r\n", p[5]);
 }
-
 #endif
 
 static void reset_core(dwc2_regs_t* dwc2) {
@@ -702,12 +692,8 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
  *------------------------------------------------------------------*/
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
-  (void) rhport;
-
   TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
-
   edpt_activate(rhport, desc_edpt);
-
   return true;
 }
 
@@ -733,15 +719,12 @@ void dcd_edpt_close_all(uint8_t rhport) {
   _allocated_fifo_words_tx = 16;
 }
 
-bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
-{
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
   TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size));
-
   return true;
 }
 
-bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
-{
+bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc) {
   // Disable EP to clear potential incomplete transfers
   edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false);
 
@@ -807,11 +790,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
   return true;
 }
 
-
-
-/**
- * Close an endpoint.
- */
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
-- 
cgit v1.3.1


From 998090d1a7f914c04f0bb3e6ac85634d432d88fc Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Fri, 29 Mar 2024 15:59:11 +0100
Subject: added further debug log outputs

---
 src/portable/analog/max3421/hcd_max3421.c | 32 ++++++++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index d366298ea..93d12fc64 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -29,6 +29,7 @@
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
 #define NAK_RETRY_HANDLING 1
+#define PUTCHAR_LOGS 0 // TODO to be deleted later
 
 #include <stdatomic.h>
 #include "host/hcd.h"
@@ -808,7 +809,11 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
   xfer_result_t xfer_result;
   switch(hresult) {
     case HRSL_SUCCESS:
-//      putchar('S');
+#if PUTCHAR_LOGS // TODO to be deleted later
+      putchar(ep->ep_dir ? 's' : 'S');
+      putchar('0' + ep->daddr);
+//      putchar('0' + ep->ep_num);
+#endif
       xfer_result = XFER_RESULT_SUCCESS;
       break;
 
@@ -817,7 +822,12 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
       break;
 
     case HRSL_NAK:
-//      putchar('N');
+#if PUTCHAR_LOGS // TODO to be deleted later
+      putchar(ep->ep_dir ? 'n' : 'N');
+      putchar('0' + ep->daddr);
+//      putchar('0' + ep->ep_num);
+//      putchar('0' + ep->xfer_attemp);
+#endif
 #if NAK_RETRY_HANDLING
       ep->retry_pending = 1;
       ep->xfer_pending = 0;
@@ -928,6 +938,12 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 //  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
+    LL_GPIO_SetOutputPin ( D2_GPIO_Port, D2_Pin ); // TODO to be deleted later
+#if PUTCHAR_LOGS // TODO to be deleted later
+    putchar(13);
+    putchar(10);
+    putchar('F');
+#endif
     _hcd_data.frame_count++;
 
 #if NAK_RETRY_HANDLING
@@ -937,7 +953,11 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
       max3421_ep_t * ep = &_hcd_data.ep[i];
       // set retryable EPs to pending
       if (ep->retry_pending) {
-//        putchar('R');
+#if PUTCHAR_LOGS // TODO to be deleted later
+        putchar(ep->ep_dir ? 'r' : 'R');
+        putchar('0' + ep->daddr);
+//        putchar('0' + ep->ep_num);
+#endif
         ep->xfer_pending = 1;
         ep->retry_pending = 0;
         if (next_ep == NULL) {
@@ -948,10 +968,16 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     // trigger 1st retryable EP
     if (next_ep) {
       if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
+#if PUTCHAR_LOGS // TODO to be deleted later
+        putchar(next_ep->ep_dir ? 't' : 'T');
+        putchar('0' + next_ep->daddr);
+//        putchar('0' + next_ep->ep_num);
+#endif
         xact_inout(rhport, next_ep, true, in_isr);
       }
     }
 #endif
+    LL_GPIO_SetOutputPin ( D2_GPIO_Port, D2_Pin << 16 );
   }
 
   if (hirq & HIRQ_CONDET_IRQ) {
-- 
cgit v1.3.1


From 818c64efecfb70d8abfee6b90d53f4af8c452dcf Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 30 Mar 2024 14:11:02 +0100
Subject: fixed EP0 control handling

---
 src/portable/analog/max3421/hcd_max3421.c | 32 +++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 93d12fc64..9209865d4 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -828,36 +828,36 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
 //      putchar('0' + ep->ep_num);
 //      putchar('0' + ep->xfer_attemp);
 #endif
-#if NAK_RETRY_HANDLING
-      ep->retry_pending = 1;
-      ep->xfer_pending = 0;
-      max3421_ep_t * next_ep = find_next_pending_ep(ep);
-      if (next_ep) {
-        // switch to next pending TODO could have issue with double buffered if not clear previously out data
-        xact_inout(rhport, next_ep, true, in_isr);
-      } else {
-        // no more pending
-        atomic_flag_clear(&_hcd_data.busy);
-      }
-#else
       if (ep_num == 0) {
         // NAK on control, retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
-      }else {
+      } else {
+      #if NAK_RETRY_HANDLING
+        ep->retry_pending = 1;
+        ep->xfer_pending = 0;
+        max3421_ep_t * next_ep = find_next_pending_ep(ep);
+        if (next_ep) {
+          // switch to next pending TODO could have issue with double buffered if not clear previously out data
+          xact_inout(rhport, next_ep, true, in_isr);
+        } else {
+          // no more pending
+          atomic_flag_clear(&_hcd_data.busy);
+        }
+      #else
         // NAK on non-control, find next pending to switch
         max3421_ep_t *next_ep = find_next_pending_ep(ep);
 
         if (ep == next_ep) {
           // this endpoint is only one pending, retry immediately
           hxfr_write(rhport, _hcd_data.hxfr, in_isr);
-        }else if (next_ep) {
+        } else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
           xact_inout(rhport, next_ep, true, in_isr);
-        }else {
+        } else {
           TU_ASSERT(false,);
         }
+      #endif
       }
-#endif
       return;
 
     case HRSL_BAD_REQ:
-- 
cgit v1.3.1


From 11a54bc8e185c58fa5c72b6913ac07e3a3060be6 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 30 Mar 2024 14:16:13 +0100
Subject: renamed define NAK_RETRY_HANDLING to
 CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME as official option

---
 src/portable/analog/max3421/hcd_max3421.c | 9 +++++----
 src/tusb_option.h                         | 9 +++++++++
 2 files changed, 14 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 9209865d4..09de1bc5a 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -28,7 +28,6 @@
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
-#define NAK_RETRY_HANDLING 1
 #define PUTCHAR_LOGS 0 // TODO to be deleted later
 
 #include <stdatomic.h>
@@ -169,6 +168,8 @@ enum {
   DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
 };
 
+TU_VERIFY_STATIC(CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME >= 0 && CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME <= 1, "unsupported attemp quantity");
+
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
@@ -183,7 +184,7 @@ typedef struct {
     uint8_t data_toggle   : 1;
     uint8_t xfer_pending  : 1;
     uint8_t xfer_complete : 1;
-#if NAK_RETRY_HANDLING
+#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
     uint8_t retry_pending : 1;
 #endif
   };
@@ -832,7 +833,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
         // NAK on control, retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
       } else {
-      #if NAK_RETRY_HANDLING
+      #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
         ep->retry_pending = 1;
         ep->xfer_pending = 0;
         max3421_ep_t * next_ep = find_next_pending_ep(ep);
@@ -946,7 +947,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 #endif
     _hcd_data.frame_count++;
 
-#if NAK_RETRY_HANDLING
+#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
     // retry EPs
     max3421_ep_t * next_ep = NULL;
     for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 22f27e9e1..68eb4882c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -529,6 +529,15 @@
   #define CFG_TUH_MAX3421  0
 #endif
 
+// MAX3421 Host max. transfer attemps per frame (except control and iso)
+// temporary only one attemp (no retry) per frame allowed (more in work)
+// retry quantity = (CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME - 1)
+// 0 = endless retries in current frame. is default to keep compatibility
+#ifndef CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+  #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 0
+#endif
+
+
 //--------------------------------------------------------------------+
 // TypeC Options (Default)
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 009d85722bbfae41f057cfbb69c63716a5fb2c5f Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 30 Mar 2024 15:17:34 +0100
Subject: replaced bits xfer_pending, xfer_complete and retry_pending by common
 4 bits state

---
 src/portable/analog/max3421/hcd_max3421.c | 47 ++++++++++++++++---------------
 1 file changed, 24 insertions(+), 23 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 09de1bc5a..2b3c625dc 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -168,6 +168,15 @@ enum {
   DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
 };
 
+enum {
+  EP_STATE_IDLE = 0,
+  EP_STATE_PENDING,
+#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+  EP_STATE_SUSPENDED,
+#endif
+  EP_STATE_COMPLETE
+};
+
 TU_VERIFY_STATIC(CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME >= 0 && CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME <= 1, "unsupported attemp quantity");
 
 //--------------------------------------------------------------------+
@@ -178,15 +187,11 @@ typedef struct {
   uint8_t daddr;
 
   struct TU_ATTR_PACKED {
-    uint8_t ep_dir        : 1;
-    uint8_t is_iso        : 1;
-    uint8_t is_setup      : 1;
+    uint8_t state         : 4;
+    uint8_t is_setup      : 1; // also bit 4 in HXFR reg (smaller code, no shift necessary)
+    uint8_t ep_dir        : 1; // also bit 5 in HXFR reg (smaller code, no shift necessary)
+    uint8_t is_iso        : 1; // also bit 6 in HXFR reg (smaller code, no shift necessary)
     uint8_t data_toggle   : 1;
-    uint8_t xfer_pending  : 1;
-    uint8_t xfer_complete : 1;
-#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-    uint8_t retry_pending : 1;
-#endif
   };
 
   struct TU_ATTR_PACKED {
@@ -406,7 +411,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->xfer_pending && ep->packet_size) {
+    if (ep->state == EP_STATE_PENDING && ep->packet_size) {
 //      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
@@ -415,7 +420,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // wrap around including current endpoint
   for (size_t i = 0; i <= idx; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->xfer_pending && ep->packet_size) {
+    if (ep->state == EP_STATE_PENDING && ep->packet_size) {
 //      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
@@ -664,8 +669,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
-  ep->xfer_complete = 0;
-  ep->xfer_pending = 1;
+  ep->state = EP_STATE_PENDING;
 
   if ( ep_num == 0 ) {
     ep->is_setup = 0;
@@ -704,8 +708,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->buf = (uint8_t*)(uintptr_t) setup_packet;
   ep->total_len = 8;
   ep->xferred_len = 0;
-  ep->xfer_complete = 0;
-  ep->xfer_pending = 1;
+  ep->state = EP_STATE_PENDING;
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
@@ -783,7 +786,7 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
     ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1u : 0u;
   }
 
-  ep->xfer_pending = 0;
+  ep->state = EP_STATE_IDLE;
   hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, in_isr);
 
   // Find next pending endpoint
@@ -834,8 +837,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
       } else {
       #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-        ep->retry_pending = 1;
-        ep->xfer_pending = 0;
+        ep->state = EP_STATE_SUSPENDED;
         max3421_ep_t * next_ep = find_next_pending_ep(ep);
         if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
@@ -879,11 +881,11 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
   if (ep_dir) {
     // IN transfer: fifo data is already received in RCVDAV IRQ
     if ( hxfr_type & HXFR_HS ) {
-      ep->xfer_complete = 1;
+      ep->state = EP_STATE_COMPLETE;
     }
 
     // short packet or all bytes transferred
-    if ( ep->xfer_complete ) {
+    if (ep->state == EP_STATE_COMPLETE) {
       xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
     }else {
       // more to transfer
@@ -953,14 +955,13 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
       max3421_ep_t * ep = &_hcd_data.ep[i];
       // set retryable EPs to pending
-      if (ep->retry_pending) {
+      if (ep->state == EP_STATE_SUSPENDED) {
 #if PUTCHAR_LOGS // TODO to be deleted later
         putchar(ep->ep_dir ? 'r' : 'R');
         putchar('0' + ep->daddr);
 //        putchar('0' + ep->ep_num);
 #endif
-        ep->xfer_pending = 1;
-        ep->retry_pending = 0;
+        ep->state = EP_STATE_PENDING;
         if (next_ep == NULL) {
           next_ep = &_hcd_data.ep[i];
         }
@@ -1009,7 +1010,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
       }
 
       if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
-        ep->xfer_complete = 1;
+        ep->state = EP_STATE_COMPLETE;
       }
     }
 
-- 
cgit v1.3.1


From 0bb26c97c316cbf3dc0b6e70234c958cf361da73 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 30 Mar 2024 14:49:00 +0100
Subject: removed redundant return true;

---
 src/portable/analog/max3421/hcd_max3421.c | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 2b3c625dc..335d78481 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -679,8 +679,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
     xact_inout(rhport, ep, true, false);
-  } else {
-    return true;
   }
 
   return true;
-- 
cgit v1.3.1


From f3fccaad2657fae7957523aee5ec1698b55470c4 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 30 Mar 2024 14:57:22 +0100
Subject: improved/fixed trigger 1st retryable EP

---
 src/portable/analog/max3421/hcd_max3421.c | 22 +++++++++-------------
 1 file changed, 9 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 335d78481..2dc8f2e18 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -949,7 +949,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 
 #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
     // retry EPs
-    max3421_ep_t * next_ep = NULL;
     for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
       max3421_ep_t * ep = &_hcd_data.ep[i];
       // set retryable EPs to pending
@@ -960,20 +959,17 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 //        putchar('0' + ep->ep_num);
 #endif
         ep->state = EP_STATE_PENDING;
-        if (next_ep == NULL) {
-          next_ep = &_hcd_data.ep[i];
-        }
-      }
-    }
-    // trigger 1st retryable EP
-    if (next_ep) {
-      if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
+        // trigger 1st retryable EP
+        if (ep->packet_size) { // first test packet_size before atomic_flag_test_and_set()
+          if (!atomic_flag_test_and_set(&_hcd_data.busy) ) {
 #if PUTCHAR_LOGS // TODO to be deleted later
-        putchar(next_ep->ep_dir ? 't' : 'T');
-        putchar('0' + next_ep->daddr);
-//        putchar('0' + next_ep->ep_num);
+              putchar(ep->ep_dir ? 't' : 'T');
+              putchar('0' + ep->daddr);
+//              putchar('0' + ep->ep_num);
 #endif
-        xact_inout(rhport, next_ep, true, in_isr);
+            xact_inout(rhport, ep, true, in_isr);
+          }
+        }
       }
     }
 #endif
-- 
cgit v1.3.1


From 79bc09a68ce07224983bf597b29e7fb1084617f3 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sat, 30 Mar 2024 15:15:05 +0100
Subject: improved code readability

---
 src/portable/analog/max3421/hcd_max3421.c | 75 +++++++++++++++----------------
 1 file changed, 35 insertions(+), 40 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 2dc8f2e18..dbdd2d127 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -788,7 +788,7 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
   hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, in_isr);
 
   // Find next pending endpoint
-  max3421_ep_t *next_ep = find_next_pending_ep(ep);
+  max3421_ep_t * next_ep = find_next_pending_ep(ep);
   if (next_ep) {
     xact_inout(rhport, next_ep, true, in_isr);
   }else {
@@ -811,11 +811,11 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
   xfer_result_t xfer_result;
   switch(hresult) {
     case HRSL_SUCCESS:
-#if PUTCHAR_LOGS // TODO to be deleted later
-      putchar(ep->ep_dir ? 's' : 'S');
-      putchar('0' + ep->daddr);
-//      putchar('0' + ep->ep_num);
-#endif
+      #if PUTCHAR_LOGS // TODO to be deleted later
+        putchar(ep->ep_dir ? 's' : 'S');
+        putchar('0' + ep->daddr);
+//        putchar('0' + ep->ep_num);
+      #endif
       xfer_result = XFER_RESULT_SUCCESS;
       break;
 
@@ -824,12 +824,12 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
       break;
 
     case HRSL_NAK:
-#if PUTCHAR_LOGS // TODO to be deleted later
-      putchar(ep->ep_dir ? 'n' : 'N');
-      putchar('0' + ep->daddr);
-//      putchar('0' + ep->ep_num);
-//      putchar('0' + ep->xfer_attemp);
-#endif
+      #if PUTCHAR_LOGS // TODO to be deleted later
+        putchar(ep->ep_dir ? 'n' : 'N');
+        putchar('0' + ep->daddr);
+//        putchar('0' + ep->ep_num);
+        putchar('0' + ep->state);
+      #endif
       if (ep_num == 0) {
         // NAK on control, retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
@@ -917,13 +917,13 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
 void print_hirq(uint8_t hirq) {
   TU_LOG3_HEX(hirq);
 
-  if (hirq & HIRQ_HXFRDN_IRQ) TU_LOG3(" HXFRDN");
-  if (hirq & HIRQ_FRAME_IRQ)  TU_LOG3(" FRAME");
-  if (hirq & HIRQ_CONDET_IRQ) TU_LOG3(" CONDET");
-  if (hirq & HIRQ_SUSDN_IRQ)  TU_LOG3(" SUSDN");
-  if (hirq & HIRQ_SNDBAV_IRQ) TU_LOG3(" SNDBAV");
-  if (hirq & HIRQ_RCVDAV_IRQ) TU_LOG3(" RCVDAV");
-  if (hirq & HIRQ_RWU_IRQ)    TU_LOG3(" RWU");
+  if (hirq & HIRQ_HXFRDN_IRQ)   TU_LOG3(" HXFRDN");
+  if (hirq & HIRQ_FRAME_IRQ)    TU_LOG3(" FRAME");
+  if (hirq & HIRQ_CONDET_IRQ)   TU_LOG3(" CONDET");
+  if (hirq & HIRQ_SUSDN_IRQ)    TU_LOG3(" SUSDN");
+  if (hirq & HIRQ_SNDBAV_IRQ)   TU_LOG3(" SNDBAV");
+  if (hirq & HIRQ_RCVDAV_IRQ)   TU_LOG3(" RCVDAV");
+  if (hirq & HIRQ_RWU_IRQ)      TU_LOG3(" RWU");
   if (hirq & HIRQ_BUSEVENT_IRQ) TU_LOG3(" BUSEVENT");
 
   TU_LOG3("\r\n");
@@ -940,33 +940,28 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 
   if (hirq & HIRQ_FRAME_IRQ) {
     LL_GPIO_SetOutputPin ( D2_GPIO_Port, D2_Pin ); // TODO to be deleted later
-#if PUTCHAR_LOGS // TODO to be deleted later
-    putchar(13);
-    putchar(10);
-    putchar('F');
-#endif
+    #if PUTCHAR_LOGS // TODO to be deleted later
+      putchar(13);
+      putchar(10);
+      putchar('F');
+    #endif
     _hcd_data.frame_count++;
 
-#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-    // retry EPs
-    for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
-      max3421_ep_t * ep = &_hcd_data.ep[i];
-      // set retryable EPs to pending
-      if (ep->state == EP_STATE_SUSPENDED) {
-#if PUTCHAR_LOGS // TODO to be deleted later
-        putchar(ep->ep_dir ? 'r' : 'R');
-        putchar('0' + ep->daddr);
-//        putchar('0' + ep->ep_num);
-#endif
+    #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+      // retry EPs
+      for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+        max3421_ep_t * ep = &_hcd_data.ep[i];
+        // set retryable EPs to pending
+        if (ep->state == EP_STATE_SUSPENDED) {
         ep->state = EP_STATE_PENDING;
         // trigger 1st retryable EP
         if (ep->packet_size) { // first test packet_size before atomic_flag_test_and_set()
           if (!atomic_flag_test_and_set(&_hcd_data.busy) ) {
-#if PUTCHAR_LOGS // TODO to be deleted later
-              putchar(ep->ep_dir ? 't' : 'T');
-              putchar('0' + ep->daddr);
-//              putchar('0' + ep->ep_num);
-#endif
+              #if PUTCHAR_LOGS // TODO to be deleted later
+                putchar(ep->ep_dir ? 't' : 'T');
+                putchar('0' + ep->daddr);
+//                putchar('0' + ep->ep_num);
+              #endif
             xact_inout(rhport, ep, true, in_isr);
           }
         }
-- 
cgit v1.3.1


From fbb2818864d70e7e11879bf1c2daf2c22011f78b Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sun, 31 Mar 2024 09:25:51 +0200
Subject: added multiple attemp counting per frame

---
 src/portable/analog/max3421/hcd_max3421.c | 100 +++++++++++++++++++++---------
 1 file changed, 70 insertions(+), 30 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index dbdd2d127..6a38302b1 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -169,15 +169,33 @@ enum {
 };
 
 enum {
-  EP_STATE_IDLE = 0,
-  EP_STATE_PENDING,
-#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-  EP_STATE_SUSPENDED,
-#endif
-  EP_STATE_COMPLETE
+  EP_STATE_IDLE       = 0,
+  EP_STATE_ATTEMP1    = 1,  // pending 1st attemp
+  #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+    EP_STATE_ATTEMP2  = 2,  // don't change order
+    EP_STATE_ATTEMP3  = 3,  // need to be incrementable
+    EP_STATE_ATTEMP4  = 4,
+    EP_STATE_ATTEMP5  = 5,
+    EP_STATE_ATTEMP6  = 6,
+    EP_STATE_ATTEMP7  = 7,
+    EP_STATE_ATTEMP8  = 8,
+    EP_STATE_ATTEMP9  = 9,
+    EP_STATE_ATTEMP10 = 10,
+    EP_STATE_SUSPENDED,    // keep next behind last attemp
+  #endif
+  EP_STATE_COMPLETE,
+  EP_STATE_QUANTITY        // not used. only to get quantity. keep last
 };
 
-TU_VERIFY_STATIC(CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME >= 0 && CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME <= 1, "unsupported attemp quantity");
+TU_VERIFY_STATIC(EP_STATE_QUANTITY <= 16, "no more than 16 states possible. ep->state has 4 bits");
+
+#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+  #define EP_STATE_ATTEMP_QUANTITY (EP_STATE_SUSPENDED - 1)
+  TU_VERIFY_STATIC(CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME >= 1 &&
+                   CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME <= EP_STATE_ATTEMP_QUANTITY, "unsupported attemp quantity");
+#else
+  #define EP_STATE_ATTEMP_QUANTITY 1
+#endif
 
 //--------------------------------------------------------------------+
 //
@@ -406,12 +424,16 @@ static void free_ep(uint8_t daddr) {
 }
 
 static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
+  // search for next pending endpoint using round-robin scheduling
+  // if no other endpoint is pending and current endpoint is still pending, the current endpoint will be returned
+  // if no other endpoint is pending and current endpoint is not pending, NULL will be returned
+  // TODO maybe priorization control/interrupt/bulk/iso
   size_t const idx = (size_t) (cur_ep - _hcd_data.ep);
 
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->state == EP_STATE_PENDING && ep->packet_size) {
+    if (ep->state >= EP_STATE_ATTEMP1 && ep->state <= EP_STATE_ATTEMP_QUANTITY && ep->packet_size) {
 //      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
@@ -420,7 +442,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // wrap around including current endpoint
   for (size_t i = 0; i <= idx; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->state == EP_STATE_PENDING && ep->packet_size) {
+    if (ep->state >= EP_STATE_ATTEMP1 && ep->state <= EP_STATE_ATTEMP_QUANTITY && ep->packet_size) {
 //      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
@@ -669,7 +691,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
-  ep->state = EP_STATE_PENDING;
+  ep->state = EP_STATE_ATTEMP1;
 
   if ( ep_num == 0 ) {
     ep->is_setup = 0;
@@ -706,7 +728,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->buf = (uint8_t*)(uintptr_t) setup_packet;
   ep->total_len = 8;
   ep->xferred_len = 0;
-  ep->state = EP_STATE_PENDING;
+  ep->state = EP_STATE_ATTEMP1;
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
@@ -824,6 +846,8 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
       break;
 
     case HRSL_NAK:
+      // TODO no retry for iso in current frame
+      // TODO retry limitation over all (not only per frame)
       #if PUTCHAR_LOGS // TODO to be deleted later
         putchar(ep->ep_dir ? 'n' : 'N');
         putchar('0' + ep->daddr);
@@ -831,33 +855,38 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
         putchar('0' + ep->state);
       #endif
       if (ep_num == 0) {
-        // NAK on control, retry immediately
+        // setup/control => retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
-      } else {
       #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+      } else if (ep->state == CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME) {
+        // no more retry this frame if max. attemps are reached => suspend and retry it next frame
         ep->state = EP_STATE_SUSPENDED;
+
         max3421_ep_t * next_ep = find_next_pending_ep(ep);
         if (next_ep) {
-          // switch to next pending TODO could have issue with double buffered if not clear previously out data
+          // switch to next pending endpoint TODO could have issue with double buffered if not clear previously out data
           xact_inout(rhport, next_ep, true, in_isr);
         } else {
-          // no more pending
+          // no more pending => clear busy
           atomic_flag_clear(&_hcd_data.busy);
         }
-      #else
-        // NAK on non-control, find next pending to switch
-        max3421_ep_t *next_ep = find_next_pending_ep(ep);
+      #endif
+      } else {
+        // another attemp
+        #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+          ep->state++;
+        #endif
 
+        max3421_ep_t * next_ep = find_next_pending_ep(ep);
         if (ep == next_ep) {
-          // this endpoint is only one pending, retry immediately
+          // this endpoint is only one pending => retry immediately
           hxfr_write(rhport, _hcd_data.hxfr, in_isr);
         } else if (next_ep) {
-          // switch to next pending TODO could have issue with double buffered if not clear previously out data
+          // switch to next pending endpoint TODO could have issue with double buffered if not clear previously out data
           xact_inout(rhport, next_ep, true, in_isr);
         } else {
           TU_ASSERT(false,);
         }
-      #endif
       }
       return;
 
@@ -948,26 +977,37 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     _hcd_data.frame_count++;
 
     #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-      // retry EPs
+      // endpoints retry or restart attemp next frame
       for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
         max3421_ep_t * ep = &_hcd_data.ep[i];
-        // set retryable EPs to pending
+
+        // retry the endpoints that are suspended (NAK) last frame
         if (ep->state == EP_STATE_SUSPENDED) {
-        ep->state = EP_STATE_PENDING;
-        // trigger 1st retryable EP
-        if (ep->packet_size) { // first test packet_size before atomic_flag_test_and_set()
-          if (!atomic_flag_test_and_set(&_hcd_data.busy) ) {
+          // resume and retry suspended endpoint with attemp 1
+          ep->state = EP_STATE_ATTEMP1;
+
+          if (ep->packet_size) { // first test packet_size before atomic_flag_test_and_set()
+            if (!atomic_flag_test_and_set(&_hcd_data.busy) ) {
+              // trigger endpoint to be retried
               #if PUTCHAR_LOGS // TODO to be deleted later
                 putchar(ep->ep_dir ? 't' : 'T');
                 putchar('0' + ep->daddr);
 //                putchar('0' + ep->ep_num);
               #endif
-            xact_inout(rhport, ep, true, in_isr);
+              xact_inout(rhport, ep, true, in_isr);
+            }
           }
+        } else if (ep->state > EP_STATE_ATTEMP1 && ep->state <= CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME) {
+          // restart all other running/pending endpoints
+          #if PUTCHAR_LOGS // TODO to be deleted later
+            putchar(ep->ep_dir ? 'r' : 'R');
+            putchar('0' + ep->daddr);
+//            putchar('0' + ep->ep_num);
+          #endif
+          ep->state = EP_STATE_ATTEMP1;
         }
       }
-    }
-#endif
+    #endif
     LL_GPIO_SetOutputPin ( D2_GPIO_Port, D2_Pin << 16 );
   }
 
-- 
cgit v1.3.1


From c1a17a7369e326fad83b28d2abdef35d61d1f1ab Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sun, 31 Mar 2024 09:32:41 +0200
Subject: removed debug code

---
 src/portable/analog/max3421/hcd_max3421.c | 30 ------------------------------
 1 file changed, 30 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 6a38302b1..17d144c07 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -28,8 +28,6 @@
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
-#define PUTCHAR_LOGS 0 // TODO to be deleted later
-
 #include <stdatomic.h>
 #include "host/hcd.h"
 
@@ -833,11 +831,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
   xfer_result_t xfer_result;
   switch(hresult) {
     case HRSL_SUCCESS:
-      #if PUTCHAR_LOGS // TODO to be deleted later
-        putchar(ep->ep_dir ? 's' : 'S');
-        putchar('0' + ep->daddr);
-//        putchar('0' + ep->ep_num);
-      #endif
       xfer_result = XFER_RESULT_SUCCESS;
       break;
 
@@ -848,12 +841,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
     case HRSL_NAK:
       // TODO no retry for iso in current frame
       // TODO retry limitation over all (not only per frame)
-      #if PUTCHAR_LOGS // TODO to be deleted later
-        putchar(ep->ep_dir ? 'n' : 'N');
-        putchar('0' + ep->daddr);
-//        putchar('0' + ep->ep_num);
-        putchar('0' + ep->state);
-      #endif
       if (ep_num == 0) {
         // setup/control => retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
@@ -968,12 +955,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 //  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
-    LL_GPIO_SetOutputPin ( D2_GPIO_Port, D2_Pin ); // TODO to be deleted later
-    #if PUTCHAR_LOGS // TODO to be deleted later
-      putchar(13);
-      putchar(10);
-      putchar('F');
-    #endif
     _hcd_data.frame_count++;
 
     #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
@@ -989,26 +970,15 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
           if (ep->packet_size) { // first test packet_size before atomic_flag_test_and_set()
             if (!atomic_flag_test_and_set(&_hcd_data.busy) ) {
               // trigger endpoint to be retried
-              #if PUTCHAR_LOGS // TODO to be deleted later
-                putchar(ep->ep_dir ? 't' : 'T');
-                putchar('0' + ep->daddr);
-//                putchar('0' + ep->ep_num);
-              #endif
               xact_inout(rhport, ep, true, in_isr);
             }
           }
         } else if (ep->state > EP_STATE_ATTEMP1 && ep->state <= CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME) {
           // restart all other running/pending endpoints
-          #if PUTCHAR_LOGS // TODO to be deleted later
-            putchar(ep->ep_dir ? 'r' : 'R');
-            putchar('0' + ep->daddr);
-//            putchar('0' + ep->ep_num);
-          #endif
           ep->state = EP_STATE_ATTEMP1;
         }
       }
     #endif
-    LL_GPIO_SetOutputPin ( D2_GPIO_Port, D2_Pin << 16 );
   }
 
   if (hirq & HIRQ_CONDET_IRQ) {
-- 
cgit v1.3.1


From 8ded6d3d2eeb57dbffe1db9cdacaf3ae7c0159a7 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sun, 31 Mar 2024 09:33:20 +0200
Subject: added some description to tusb_option.h

---
 src/tusb_option.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 68eb4882c..64915cf62 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -530,9 +530,11 @@
 #endif
 
 // MAX3421 Host max. transfer attemps per frame (except control and iso)
-// temporary only one attemp (no retry) per frame allowed (more in work)
 // retry quantity = (CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME - 1)
-// 0 = endless retries in current frame. is default to keep compatibility
+// 0 = endless retries. is default to keep compatibility
+//     => this may overload MCU with permanently repeating NAK interrupts
+//     => possible increased USB traffic, increased latencies, reduced data throughput
+// a usual attemp quantity is 3 (reference: the book "USB Complete" by Jan Axelson)
 #ifndef CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
   #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 0
 #endif
-- 
cgit v1.3.1


From fe304576d0875646a07ab56493f27a7a249ded35 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sun, 31 Mar 2024 09:35:38 +0200
Subject: reactivated TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);

---
 src/portable/analog/max3421/hcd_max3421.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 17d144c07..84ea39d20 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -625,7 +625,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   }
 
   uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-//  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
+  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
   if (xact_len) {
     fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
   }
-- 
cgit v1.3.1


From b644e4d95582748dfc9ab947bbb32fd994f34448 Mon Sep 17 00:00:00 2001
From: IngHK <github@hkue.de>
Date: Sun, 31 Mar 2024 09:58:59 +0200
Subject: fixed spelling

---
 examples/host/bare_api/src/tusb_config.h           |  2 +-
 examples/host/cdc_msc_hid/src/tusb_config.h        |  2 +-
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    |  2 +-
 examples/host/hid_controller/src/tusb_config.h     |  2 +-
 examples/host/msc_file_explorer/src/tusb_config.h  |  2 +-
 src/portable/analog/max3421/hcd_max3421.c          | 68 +++++++++++-----------
 src/tusb_option.h                                  |  8 +--
 7 files changed, 43 insertions(+), 43 deletions(-)

(limited to 'src')

diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index 8bdcb4fba..d8e81aa82 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -72,7 +72,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 3 // max. transfer attemps per frame
+  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 371ed807e..8a56ebc2b 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -72,7 +72,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 3 // max. transfer attemps per frame
+  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index 621b97865..7705be5c8 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -77,7 +77,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 3 // max. transfer attemps per frame
+  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index 8036e9f66..f087a93cf 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -72,7 +72,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 3 // max. transfer attemps per frame
+  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index 3ac3f3cdf..05b9fa174 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -72,7 +72,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 3 // max. transfer attemps per frame
+  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 84ea39d20..324638cb8 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -167,19 +167,19 @@ enum {
 };
 
 enum {
-  EP_STATE_IDLE       = 0,
-  EP_STATE_ATTEMP1    = 1,  // pending 1st attemp
-  #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-    EP_STATE_ATTEMP2  = 2,  // don't change order
-    EP_STATE_ATTEMP3  = 3,  // need to be incrementable
-    EP_STATE_ATTEMP4  = 4,
-    EP_STATE_ATTEMP5  = 5,
-    EP_STATE_ATTEMP6  = 6,
-    EP_STATE_ATTEMP7  = 7,
-    EP_STATE_ATTEMP8  = 8,
-    EP_STATE_ATTEMP9  = 9,
-    EP_STATE_ATTEMP10 = 10,
-    EP_STATE_SUSPENDED,    // keep next behind last attemp
+  EP_STATE_IDLE        = 0,
+  EP_STATE_ATTEMPT1    = 1, // pending 1st attempt
+  #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
+    EP_STATE_ATTEMPT2  = 2, // don't change order
+    EP_STATE_ATTEMPT3  = 3, // need to be incrementable
+    EP_STATE_ATTEMPT4  = 4,
+    EP_STATE_ATTEMPT5  = 5,
+    EP_STATE_ATTEMPT6  = 6,
+    EP_STATE_ATTEMPT7  = 7,
+    EP_STATE_ATTEMPT8  = 8,
+    EP_STATE_ATTEMPT9  = 9,
+    EP_STATE_ATTEMPT10 = 10,
+    EP_STATE_SUSPENDED,    // keep next behind last attempt
   #endif
   EP_STATE_COMPLETE,
   EP_STATE_QUANTITY        // not used. only to get quantity. keep last
@@ -187,12 +187,12 @@ enum {
 
 TU_VERIFY_STATIC(EP_STATE_QUANTITY <= 16, "no more than 16 states possible. ep->state has 4 bits");
 
-#if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-  #define EP_STATE_ATTEMP_QUANTITY (EP_STATE_SUSPENDED - 1)
-  TU_VERIFY_STATIC(CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME >= 1 &&
-                   CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME <= EP_STATE_ATTEMP_QUANTITY, "unsupported attemp quantity");
+#if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
+  #define EP_STATE_ATTEMPT_QUANTITY (EP_STATE_SUSPENDED - 1)
+  TU_VERIFY_STATIC(CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME >= 1 &&
+                   CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME <= EP_STATE_ATTEMPT_QUANTITY, "unsupported attempt quantity");
 #else
-  #define EP_STATE_ATTEMP_QUANTITY 1
+  #define EP_STATE_ATTEMPT_QUANTITY 1
 #endif
 
 //--------------------------------------------------------------------+
@@ -425,13 +425,13 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // search for next pending endpoint using round-robin scheduling
   // if no other endpoint is pending and current endpoint is still pending, the current endpoint will be returned
   // if no other endpoint is pending and current endpoint is not pending, NULL will be returned
-  // TODO maybe priorization control/interrupt/bulk/iso
+  // TODO maybe prioritisation control/interrupt/bulk/iso
   size_t const idx = (size_t) (cur_ep - _hcd_data.ep);
 
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->state >= EP_STATE_ATTEMP1 && ep->state <= EP_STATE_ATTEMP_QUANTITY && ep->packet_size) {
+    if (ep->state >= EP_STATE_ATTEMPT1 && ep->state <= EP_STATE_ATTEMPT_QUANTITY && ep->packet_size) {
 //      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
@@ -440,7 +440,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // wrap around including current endpoint
   for (size_t i = 0; i <= idx; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->state >= EP_STATE_ATTEMP1 && ep->state <= EP_STATE_ATTEMP_QUANTITY && ep->packet_size) {
+    if (ep->state >= EP_STATE_ATTEMPT1 && ep->state <= EP_STATE_ATTEMPT_QUANTITY && ep->packet_size) {
 //      TU_LOG3("next pending i = %u\r\n", i);
       return ep;
     }
@@ -689,7 +689,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
-  ep->state = EP_STATE_ATTEMP1;
+  ep->state = EP_STATE_ATTEMPT1;
 
   if ( ep_num == 0 ) {
     ep->is_setup = 0;
@@ -726,7 +726,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->buf = (uint8_t*)(uintptr_t) setup_packet;
   ep->total_len = 8;
   ep->xferred_len = 0;
-  ep->state = EP_STATE_ATTEMP1;
+  ep->state = EP_STATE_ATTEMPT1;
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
@@ -844,9 +844,9 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
       if (ep_num == 0) {
         // setup/control => retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
-      #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-      } else if (ep->state == CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME) {
-        // no more retry this frame if max. attemps are reached => suspend and retry it next frame
+      #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
+      } else if (ep->state == CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME) {
+        // no more retry this frame if max. attempts are reached => suspend and retry it next frame
         ep->state = EP_STATE_SUSPENDED;
 
         max3421_ep_t * next_ep = find_next_pending_ep(ep);
@@ -859,8 +859,8 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
         }
       #endif
       } else {
-        // another attemp
-        #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
+        // another attempt
+        #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
           ep->state++;
         #endif
 
@@ -957,15 +957,15 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
 
-    #if CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-      // endpoints retry or restart attemp next frame
+    #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
+      // endpoints retry or restart attempt next frame
       for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
         max3421_ep_t * ep = &_hcd_data.ep[i];
 
         // retry the endpoints that are suspended (NAK) last frame
         if (ep->state == EP_STATE_SUSPENDED) {
-          // resume and retry suspended endpoint with attemp 1
-          ep->state = EP_STATE_ATTEMP1;
+          // resume and retry suspended endpoint with attempt 1
+          ep->state = EP_STATE_ATTEMPT1;
 
           if (ep->packet_size) { // first test packet_size before atomic_flag_test_and_set()
             if (!atomic_flag_test_and_set(&_hcd_data.busy) ) {
@@ -973,9 +973,9 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
               xact_inout(rhport, ep, true, in_isr);
             }
           }
-        } else if (ep->state > EP_STATE_ATTEMP1 && ep->state <= CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME) {
+        } else if (ep->state > EP_STATE_ATTEMPT1 && ep->state <= CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME) {
           // restart all other running/pending endpoints
-          ep->state = EP_STATE_ATTEMP1;
+          ep->state = EP_STATE_ATTEMPT1;
         }
       }
     #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 64915cf62..18cc8a82c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -529,14 +529,14 @@
   #define CFG_TUH_MAX3421  0
 #endif
 
-// MAX3421 Host max. transfer attemps per frame (except control and iso)
+// MAX3421 Host max. transfer attempts per frame (except control and iso)
 // retry quantity = (CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME - 1)
 // 0 = endless retries. is default to keep compatibility
 //     => this may overload MCU with permanently repeating NAK interrupts
 //     => possible increased USB traffic, increased latencies, reduced data throughput
-// a usual attemp quantity is 3 (reference: the book "USB Complete" by Jan Axelson)
-#ifndef CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME
-  #define CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME 0
+// a usual attempt quantity is 3 (reference: the book "USB Complete" by Jan Axelson)
+#ifndef CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
+  #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 0
 #endif
 
 
-- 
cgit v1.3.1


From 2012a0d369badbc671ac061184ddc3f5961e985e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Mar 2024 15:48:26 +0700
Subject: fix hid close not clear data

---
 src/class/hid/hid_host.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index efc54656e..621fb2a55 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -410,8 +410,7 @@ void hidh_close(uint8_t daddr) {
     if (p_hid->daddr == daddr) {
       TU_LOG_DRV("  HIDh close addr = %u index = %u\r\n", daddr, i);
       if (tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
-      p_hid->daddr = 0;
-      p_hid->mounted = false;
+      tu_memclr(p_hid, sizeof(hidh_interface_t));
     }
   }
 }
-- 
cgit v1.3.1


From ac4e649e56b7ace537670d1cc261a64a4e650d02 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Mar 2024 18:41:59 +0700
Subject: code format

---
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h        | 176 +++++++++------------
 1 file changed, 71 insertions(+), 105 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index ade64b4fb..15de95d23 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -1,30 +1,32 @@
-/**
-  * Copyright(c) 2016 STMicroelectronics
-  * Copyright(c) N Conrad
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  */
+/*
+ * Copyright(c) 2016 STMicroelectronics
+ * Copyright(c) N Conrad
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
 
 // This file contains source copied from ST's HAL, and thus should have their copyright statement.
 
@@ -138,7 +140,6 @@
   #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
   #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
 
-
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   #include "stm32wbxx.h"
   #define FSDEV_PMA_SIZE (1024u)
@@ -182,27 +183,23 @@ typedef uint16_t fsdev_bus_t;
 // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
 static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
-{
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) {
   size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
   total_word_offset *= FSDEV_PMA_STRIDE;
   return &(pma[total_word_offset]);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
   return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
   return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
 }
 #endif
 
 /* Aligned buffer size according to hardware */
-TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) {
   /* The STM32 full speed USB peripheral supports only a limited set of
    * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
   uint16_t blocksize = (size > 62) ? 32 : 2;
@@ -213,9 +210,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si
   return numblocks * blocksize;
 }
 
-/* SetENDPOINT */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
@@ -226,7 +221,6 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, ui
 #endif
 }
 
-/* GetENDPOINT */
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
@@ -237,8 +231,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx
   return *reg;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= (uint32_t)USB_EP_T_MASK;
   regVal |= wType;
@@ -246,20 +239,19 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint
   pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EP_T_FIELD;
   return regVal;
 }
+
 /**
   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
   * @param  USBx USB peripheral instance register address.
   * @param  bEpIdx Endpoint Number.
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal &= ~USB_EP_CTR_RX;
@@ -267,22 +259,21 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx,
   pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal &= ~USB_EP_CTR_TX;
   regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0)
   pcd_set_endpoint(USBx, bEpIdx,regVal);
 }
+
 /**
   * @brief  gets counter of the tx buffer.
   * @param  USBx USB peripheral instance register address.
   * @param  bEpIdx Endpoint Number.
   * @retval Counter value
   */
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
@@ -292,8 +283,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value.
@@ -320,8 +310,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB
   * @param  bAddr Address.
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t bAddr)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t bAddr) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal |= bAddr;
@@ -329,8 +318,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,
   pcd_set_endpoint(USBx, bEpIdx,regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   return pma32[2*bEpIdx] & 0x0000FFFFu ;
@@ -339,8 +327,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef *
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
@@ -349,8 +336,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef *
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
@@ -359,8 +345,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USB
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
@@ -369,8 +354,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USB
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
@@ -380,8 +364,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, u
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
@@ -391,8 +374,8 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, u
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t blocksize, uint32_t numblocks)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx,
+                                                                      uint32_t blocksize, uint32_t numblocks) {
   /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
@@ -403,8 +386,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDe
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) {
   wCount = pcd_aligned_buffer_size(wCount);
 
   /* We assume that the buffer size is already aligned to hardware requirements. */
@@ -418,13 +400,11 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx,
   pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
   pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
   pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount);
 }
 
@@ -435,8 +415,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USB
   * @param  wState new state
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPTX_DTOGMASK;
 
@@ -453,7 +432,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx
 
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
   pcd_set_endpoint(USBx, bEpIdx, regVal);
-} /* pcd_set_ep_tx_status */
+}
 
 /**
   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
@@ -463,31 +442,27 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx
   * @retval None
   */
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPRX_DTOGMASK;
 
   /* toggle first bit ? */
-  if((USB_EPRX_DTOG1 & wState)!= 0U)
-  {
+  if((USB_EPRX_DTOG1 & wState)!= 0U) {
     regVal ^= USB_EPRX_DTOG1;
   }
   /* toggle second bit ? */
-  if((USB_EPRX_DTOG2 & wState)!= 0U)
-  {
+  if((USB_EPRX_DTOG2 & wState)!= 0U) {
     regVal ^= USB_EPRX_DTOG2;
   }
 
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
   pcd_set_endpoint(USBx, bEpIdx, regVal);
-} /* pcd_set_ep_rx_status */
+}
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   return (regVal & USB_EPRX_STAT) >> (12u);
-} /* pcd_get_ep_rx_status */
+}
 
 
 /**
@@ -496,16 +471,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef *
   * @param  bEpIdx Endpoint Number.
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
   pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
@@ -518,21 +491,16 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32
   * @param  bEpIdx Endpoint Number.
   * @retval None
   */
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  if((regVal & USB_EP_DTOG_RX) != 0)
-  {
+  if((regVal & USB_EP_DTOG_RX) != 0) {
     pcd_rx_dtog(USBx,bEpIdx);
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  if((regVal & USB_EP_DTOG_TX) != 0)
-  {
+  if((regVal & USB_EP_DTOG_TX) != 0) {
     pcd_tx_dtog(USBx,bEpIdx);
   }
 }
@@ -543,17 +511,15 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,
   * @param  bEpIdx Endpoint Number.
   * @retval None
   */
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpIdx)
-{
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal |= USB_EP_KIND;
   regVal &= USB_EPREG_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
   pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPKIND_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-- 
cgit v1.3.1


From 27afa568445d193a075c6ca2b7bb1df76039d956 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Mar 2024 18:42:49 +0700
Subject: rename dcd_stm32_fsdev_pvt_st.h to simply dcd_stm32_fsdev.h

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c      |   2 +-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h      | 543 +++++++++++++++++++++
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h        | 543 ---------------------
 3 files changed, 544 insertions(+), 544 deletions(-)
 create mode 100644 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
 delete mode 100644 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 9c37f1f98..5e54d0f56 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -109,7 +109,7 @@
 #ifdef TUP_USBIP_FSDEV_STM32
   // Undefine to reduce the dependence on HAL
   #undef USE_HAL_DRIVER
-  #include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h"
+  #include "portable/st/stm32_fsdev/dcd_stm32_fsdev.h"
 #endif
 
 /*****************************************************
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
new file mode 100644
index 000000000..15de95d23
--- /dev/null
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
@@ -0,0 +1,543 @@
+/*
+ * Copyright(c) 2016 STMicroelectronics
+ * Copyright(c) N Conrad
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright notice,
+ *      this list of conditions and the following disclaimer in the documentation
+ *      and/or other materials provided with the distribution.
+ *   3. Neither the name of STMicroelectronics nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+// This file contains source copied from ST's HAL, and thus should have their copyright statement.
+
+// FSDEV_PMA_SIZE is PMA buffer size in bytes.
+// On 512-byte devices, access with a stride of two words (use every other 16-bit address)
+// On 1024-byte devices, access with a stride of one word (use every 16-bit address)
+
+#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
+#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
+
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0
+  #include "stm32f0xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+  // F0x2 models are crystal-less
+  // All have internal D+ pull-up
+  // 070RB:    2 x 16 bits/word memory     LPM Support, BCD Support
+  // PMA dedicated to USB (no sharing with CAN)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
+  #include "stm32f1xx.h"
+  #define FSDEV_PMA_SIZE (512u)
+  // NO internal Pull-ups
+  //         *B, and *C:    2 x 16 bits/word
+
+  // F1 names this differently from the rest
+  #define USB_CNTR_LPMODE   USB_CNTR_LP_MODE
+
+#elif defined(STM32F302xB) || defined(STM32F302xC) || \
+      defined(STM32F303xB) || defined(STM32F303xC) || \
+      defined(STM32F373xC)
+  #include "stm32f3xx.h"
+  #define FSDEV_PMA_SIZE (512u)
+  // NO internal Pull-ups
+  //         *B, and *C:    1 x 16 bits/word
+  // PMA dedicated to USB (no sharing with CAN)
+
+#elif defined(STM32F302x6) || defined(STM32F302x8) || \
+      defined(STM32F302xD) || defined(STM32F302xE) || \
+      defined(STM32F303xD) || defined(STM32F303xE)
+  #include "stm32f3xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+  // NO internal Pull-ups
+  // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
+  // When CAN clock is enabled, USB can use first 768 bytes ONLY.
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
+  #include "stm32l0xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
+  #include "stm32l1xx.h"
+  #define FSDEV_PMA_SIZE (512u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+  #include "stm32g4xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+  #include "stm32g0xx.h"
+  #define FSDEV_BUS_32BIT
+  #define FSDEV_PMA_SIZE (2048u)
+  #undef USB_PMAADDR
+  #define USB_PMAADDR USB_DRD_PMAADDR
+  #define USB_TypeDef USB_DRD_TypeDef
+  #define EP0R CHEP0R
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB USB_DRD_FS
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
+  #include "stm32h5xx.h"
+  #define FSDEV_BUS_32BIT
+  #define FSDEV_PMA_SIZE (2048u)
+  #undef USB_PMAADDR
+  #define USB_PMAADDR USB_DRD_PMAADDR
+  #define USB_TypeDef USB_DRD_TypeDef
+  #define EP0R CHEP0R
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB USB_DRD_FS
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+  #include "stm32wbxx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+  /* ST provided header has incorrect value */
+  #undef USB_PMAADDR
+  #define USB_PMAADDR USB1_PMAADDR
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
+  #include "stm32l4xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+  #include "stm32l5xx.h"
+  #define FSDEV_PMA_SIZE (1024u)
+
+  #ifndef USB_PMAADDR
+    #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
+  #endif
+
+#else
+  #error You are using an untested or unimplemented STM32 variant. Please update the driver.
+  // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
+#endif
+
+// For purposes of accessing the packet
+#if ((FSDEV_PMA_SIZE) == 512u)
+  #define FSDEV_PMA_STRIDE  (2u)
+#elif ((FSDEV_PMA_SIZE) == 1024u)
+  #define FSDEV_PMA_STRIDE  (1u)
+#endif
+
+// The fsdev_bus_t type can be used for both register and PMA access necessities
+// For type-safety create a new macro for the volatile address of PMAADDR
+// The compiler should warn us if we cast it to a non-volatile type?
+#ifdef FSDEV_BUS_32BIT
+typedef uint32_t fsdev_bus_t;
+static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR;
+
+#else
+typedef uint16_t fsdev_bus_t;
+// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
+static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
+
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) {
+  size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
+  total_word_offset *= FSDEV_PMA_STRIDE;
+  return &(pma[total_word_offset]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
+  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
+  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
+}
+#endif
+
+/* Aligned buffer size according to hardware */
+TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) {
+  /* The STM32 full speed USB peripheral supports only a limited set of
+   * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
+  uint16_t blocksize = (size > 62) ? 32 : 2;
+
+  // Round up while dividing requested size by blocksize
+  uint16_t numblocks = (size + blocksize - 1) / blocksize ;
+
+  return numblocks * blocksize;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
+  *reg = wRegValue;
+#else
+  __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
+  *reg = (uint16_t)wRegValue;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4);
+#else
+  __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
+#endif
+  return *reg;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= (uint32_t)USB_EP_T_MASK;
+  regVal |= wType;
+  regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EP_T_FIELD;
+  return regVal;
+}
+
+/**
+  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @retval None
+  */
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPREG_MASK;
+  regVal &= ~USB_EP_CTR_RX;
+  regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0)
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPREG_MASK;
+  regVal &= ~USB_EP_CTR_TX;
+  regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0)
+  pcd_set_endpoint(USBx, bEpIdx,regVal);
+}
+
+/**
+  * @brief  gets counter of the tx buffer.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @retval Counter value
+  */
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
+#else
+  __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
+  return *regPtr & 0x3ffU;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value.
+     Note: required for G0, U5, H5 etc.
+  This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough.
+  Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency.
+  Observed on Windows 10 where tud_task() is scheduled by interrupt handler.
+  */
+  volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
+  while (count > 0U) {
+    count--;
+  }
+  return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
+#else
+  __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
+  return *regPtr & 0x3ffU;
+#endif
+}
+
+/**
+  * @brief  Sets address in an endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @param  bAddr Address.
+  * @retval None
+  */
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t bAddr) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPREG_MASK;
+  regVal |= bAddr;
+  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
+  pcd_set_endpoint(USBx, bEpIdx,regVal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  return pma32[2*bEpIdx] & 0x0000FFFFu ;
+#else
+  return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
+#else
+  return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
+#else
+  *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
+#else
+  *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr;
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
+#else
+  __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
+  *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
+#else
+  __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
+  *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx,
+                                                                      uint32_t blocksize, uint32_t numblocks) {
+  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
+#ifdef FSDEV_BUS_32BIT
+  (void) USBx;
+  pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26);
+#else
+  __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u);
+  *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
+#endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) {
+  wCount = pcd_aligned_buffer_size(wCount);
+
+  /* We assume that the buffer size is already aligned to hardware requirements. */
+  uint16_t blocksize = (wCount > 62) ? 1 : 0;
+  uint16_t numblocks = wCount / (blocksize ? 32 : 2);
+
+  /* There should be no remainder in the above calculation */
+  TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
+
+  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
+  pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
+  pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
+  pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount);
+}
+
+/**
+  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @param  wState new state
+  * @retval None
+  */
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPTX_DTOGMASK;
+
+  /* toggle first bit ? */
+  if((USB_EPTX_DTOG1 & (wState))!= 0U)
+  {
+    regVal ^= USB_EPTX_DTOG1;
+  }
+  /* toggle second bit ?  */
+  if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
+  {
+    regVal ^= USB_EPTX_DTOG2;
+  }
+
+  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+/**
+  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @param  wState new state
+  * @retval None
+  */
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPRX_DTOGMASK;
+
+  /* toggle first bit ? */
+  if((USB_EPRX_DTOG1 & wState)!= 0U) {
+    regVal ^= USB_EPRX_DTOG1;
+  }
+  /* toggle second bit ? */
+  if((USB_EPRX_DTOG2 & wState)!= 0U) {
+    regVal ^= USB_EPRX_DTOG2;
+  }
+
+  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  return (regVal & USB_EPRX_STAT) >> (12u);
+}
+
+
+/**
+  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @retval None
+  */
+TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPREG_MASK;
+  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPREG_MASK;
+  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+/**
+  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @retval None
+  */
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  if((regVal & USB_EP_DTOG_RX) != 0) {
+    pcd_rx_dtog(USBx,bEpIdx);
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  if((regVal & USB_EP_DTOG_TX) != 0) {
+    pcd_tx_dtog(USBx,bEpIdx);
+  }
+}
+
+/**
+  * @brief  set & clear EP_KIND bit.
+  * @param  USBx USB peripheral instance register address.
+  * @param  bEpIdx Endpoint Number.
+  * @retval None
+  */
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal |= USB_EP_KIND;
+  regVal &= USB_EPREG_MASK;
+  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) {
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
+  regVal &= USB_EPKIND_MASK;
+  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
+}
+
+// This checks if the device has "LPM"
+#if defined(USB_ISTR_L1REQ)
+#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
+#else
+#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
+#endif
+
+#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
+     USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
+
+// Number of endpoints in hardware
+// TODO should use TUP_DCD_ENDPOINT_MAX
+#define STFSDEV_EP_COUNT (8u)
+
+#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
deleted file mode 100644
index 15de95d23..000000000
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * Copyright(c) 2016 STMicroelectronics
- * Copyright(c) N Conrad
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of STMicroelectronics nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-// This file contains source copied from ST's HAL, and thus should have their copyright statement.
-
-// FSDEV_PMA_SIZE is PMA buffer size in bytes.
-// On 512-byte devices, access with a stride of two words (use every other 16-bit address)
-// On 1024-byte devices, access with a stride of one word (use every 16-bit address)
-
-#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
-#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
-
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0
-  #include "stm32f0xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-  // F0x2 models are crystal-less
-  // All have internal D+ pull-up
-  // 070RB:    2 x 16 bits/word memory     LPM Support, BCD Support
-  // PMA dedicated to USB (no sharing with CAN)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
-  #include "stm32f1xx.h"
-  #define FSDEV_PMA_SIZE (512u)
-  // NO internal Pull-ups
-  //         *B, and *C:    2 x 16 bits/word
-
-  // F1 names this differently from the rest
-  #define USB_CNTR_LPMODE   USB_CNTR_LP_MODE
-
-#elif defined(STM32F302xB) || defined(STM32F302xC) || \
-      defined(STM32F303xB) || defined(STM32F303xC) || \
-      defined(STM32F373xC)
-  #include "stm32f3xx.h"
-  #define FSDEV_PMA_SIZE (512u)
-  // NO internal Pull-ups
-  //         *B, and *C:    1 x 16 bits/word
-  // PMA dedicated to USB (no sharing with CAN)
-
-#elif defined(STM32F302x6) || defined(STM32F302x8) || \
-      defined(STM32F302xD) || defined(STM32F302xE) || \
-      defined(STM32F303xD) || defined(STM32F303xE)
-  #include "stm32f3xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-  // NO internal Pull-ups
-  // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
-  // When CAN clock is enabled, USB can use first 768 bytes ONLY.
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L0
-  #include "stm32l0xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
-  #include "stm32l1xx.h"
-  #define FSDEV_PMA_SIZE (512u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
-  #include "stm32g4xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-  #include "stm32g0xx.h"
-  #define FSDEV_BUS_32BIT
-  #define FSDEV_PMA_SIZE (2048u)
-  #undef USB_PMAADDR
-  #define USB_PMAADDR USB_DRD_PMAADDR
-  #define USB_TypeDef USB_DRD_TypeDef
-  #define EP0R CHEP0R
-  #define USB_EP_CTR_RX USB_EP_VTRX
-  #define USB_EP_CTR_TX USB_EP_VTTX
-  #define USB_EP_T_FIELD USB_CHEP_UTYPE
-  #define USB_EPREG_MASK USB_CHEP_REG_MASK
-  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
-  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
-  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
-  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
-  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
-  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
-  #define USB_EPRX_STAT USB_CH_RX_VALID
-  #define USB_EPKIND_MASK USB_EP_KIND_MASK
-  #define USB USB_DRD_FS
-  #define USB_CNTR_FRES USB_CNTR_USBRST
-  #define USB_CNTR_RESUME USB_CNTR_L2RES
-  #define USB_ISTR_EP_ID USB_ISTR_IDN
-  #define USB_EPADDR_FIELD USB_CHEP_ADDR
-  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
-  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
-  #include "stm32h5xx.h"
-  #define FSDEV_BUS_32BIT
-  #define FSDEV_PMA_SIZE (2048u)
-  #undef USB_PMAADDR
-  #define USB_PMAADDR USB_DRD_PMAADDR
-  #define USB_TypeDef USB_DRD_TypeDef
-  #define EP0R CHEP0R
-  #define USB_EP_CTR_RX USB_EP_VTRX
-  #define USB_EP_CTR_TX USB_EP_VTTX
-  #define USB_EP_T_FIELD USB_CHEP_UTYPE
-  #define USB_EPREG_MASK USB_CHEP_REG_MASK
-  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
-  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
-  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
-  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
-  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
-  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
-  #define USB_EPRX_STAT USB_CH_RX_VALID
-  #define USB_EPKIND_MASK USB_EP_KIND_MASK
-  #define USB USB_DRD_FS
-  #define USB_CNTR_FRES USB_CNTR_USBRST
-  #define USB_CNTR_RESUME USB_CNTR_L2RES
-  #define USB_ISTR_EP_ID USB_ISTR_IDN
-  #define USB_EPADDR_FIELD USB_CHEP_ADDR
-  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
-  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
-  #include "stm32wbxx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-  /* ST provided header has incorrect value */
-  #undef USB_PMAADDR
-  #define USB_PMAADDR USB1_PMAADDR
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
-  #include "stm32l4xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-
-#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
-  #include "stm32l5xx.h"
-  #define FSDEV_PMA_SIZE (1024u)
-
-  #ifndef USB_PMAADDR
-    #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
-  #endif
-
-#else
-  #error You are using an untested or unimplemented STM32 variant. Please update the driver.
-  // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
-#endif
-
-// For purposes of accessing the packet
-#if ((FSDEV_PMA_SIZE) == 512u)
-  #define FSDEV_PMA_STRIDE  (2u)
-#elif ((FSDEV_PMA_SIZE) == 1024u)
-  #define FSDEV_PMA_STRIDE  (1u)
-#endif
-
-// The fsdev_bus_t type can be used for both register and PMA access necessities
-// For type-safety create a new macro for the volatile address of PMAADDR
-// The compiler should warn us if we cast it to a non-volatile type?
-#ifdef FSDEV_BUS_32BIT
-typedef uint32_t fsdev_bus_t;
-static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR;
-
-#else
-typedef uint16_t fsdev_bus_t;
-// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
-static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
-
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) {
-  size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
-  total_word_offset *= FSDEV_PMA_STRIDE;
-  return &(pma[total_word_offset]);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
-  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx) {
-  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
-}
-#endif
-
-/* Aligned buffer size according to hardware */
-TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size) {
-  /* The STM32 full speed USB peripheral supports only a limited set of
-   * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
-  uint16_t blocksize = (size > 62) ? 32 : 2;
-
-  // Round up while dividing requested size by blocksize
-  uint16_t numblocks = (size + blocksize - 1) / blocksize ;
-
-  return numblocks * blocksize;
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
-  *reg = wRegValue;
-#else
-  __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
-  *reg = (uint16_t)wRegValue;
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4);
-#else
-  __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
-#endif
-  return *reg;
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= (uint32_t)USB_EP_T_MASK;
-  regVal |= wType;
-  regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EP_T_FIELD;
-  return regVal;
-}
-
-/**
-  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @retval None
-  */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPREG_MASK;
-  regVal &= ~USB_EP_CTR_RX;
-  regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0)
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPREG_MASK;
-  regVal &= ~USB_EP_CTR_TX;
-  regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0)
-  pcd_set_endpoint(USBx, bEpIdx,regVal);
-}
-
-/**
-  * @brief  gets counter of the tx buffer.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @retval Counter value
-  */
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
-#else
-  __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
-  return *regPtr & 0x3ffU;
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value.
-     Note: required for G0, U5, H5 etc.
-  This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough.
-  Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency.
-  Observed on Windows 10 where tud_task() is scheduled by interrupt handler.
-  */
-  volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
-  while (count > 0U) {
-    count--;
-  }
-  return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
-#else
-  __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
-  return *regPtr & 0x3ffU;
-#endif
-}
-
-/**
-  * @brief  Sets address in an endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @param  bAddr Address.
-  * @retval None
-  */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t bAddr) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPREG_MASK;
-  regVal |= bAddr;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpIdx,regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  return pma32[2*bEpIdx] & 0x0000FFFFu ;
-#else
-  return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
-#else
-  return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
-#else
-  *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr;
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
-#else
-  *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr;
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
-#else
-  __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
-  *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
-#else
-  __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
-  *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx,
-                                                                      uint32_t blocksize, uint32_t numblocks) {
-  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
-#ifdef FSDEV_BUS_32BIT
-  (void) USBx;
-  pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26);
-#else
-  __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u);
-  *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
-#endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount) {
-  wCount = pcd_aligned_buffer_size(wCount);
-
-  /* We assume that the buffer size is already aligned to hardware requirements. */
-  uint16_t blocksize = (wCount > 62) ? 1 : 0;
-  uint16_t numblocks = wCount / (blocksize ? 32 : 2);
-
-  /* There should be no remainder in the above calculation */
-  TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
-
-  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
-  pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
-  pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
-  pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount);
-}
-
-/**
-  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPTX_DTOGMASK;
-
-  /* toggle first bit ? */
-  if((USB_EPTX_DTOG1 & (wState))!= 0U)
-  {
-    regVal ^= USB_EPTX_DTOG1;
-  }
-  /* toggle second bit ?  */
-  if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)
-  {
-    regVal ^= USB_EPTX_DTOG2;
-  }
-
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-/**
-  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @param  wState new state
-  * @retval None
-  */
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPRX_DTOGMASK;
-
-  /* toggle first bit ? */
-  if((USB_EPRX_DTOG1 & wState)!= 0U) {
-    regVal ^= USB_EPRX_DTOG1;
-  }
-  /* toggle second bit ? */
-  if((USB_EPRX_DTOG2 & wState)!= 0U) {
-    regVal ^= USB_EPRX_DTOG2;
-  }
-
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  return (regVal & USB_EPRX_STAT) >> (12u);
-}
-
-
-/**
-  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @retval None
-  */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPREG_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPREG_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-/**
-  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @retval None
-  */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  if((regVal & USB_EP_DTOG_RX) != 0) {
-    pcd_rx_dtog(USBx,bEpIdx);
-  }
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  if((regVal & USB_EP_DTOG_TX) != 0) {
-    pcd_tx_dtog(USBx,bEpIdx);
-  }
-}
-
-/**
-  * @brief  set & clear EP_KIND bit.
-  * @param  USBx USB peripheral instance register address.
-  * @param  bEpIdx Endpoint Number.
-  * @retval None
-  */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal |= USB_EP_KIND;
-  regVal &= USB_EPREG_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx) {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
-  regVal &= USB_EPKIND_MASK;
-  regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpIdx, regVal);
-}
-
-// This checks if the device has "LPM"
-#if defined(USB_ISTR_L1REQ)
-#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
-#else
-#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
-#endif
-
-#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
-     USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
-
-// Number of endpoints in hardware
-// TODO should use TUP_DCD_ENDPOINT_MAX
-#define STFSDEV_EP_COUNT (8u)
-
-#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */
-- 
cgit v1.3.1


From fc54ad43b1ac89efa8853d69e836b16ddfe156fa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Mar 2024 21:53:12 +0700
Subject: move walkaround to dcd_ep_ctr_rx_handler(), increase cycle_count from
 10 to 20 (40 cycle)

---
 .idea/runConfigurations/stlink.xml            |  4 +--
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 51 +++++++++++++++++----------
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h | 10 ------
 3 files changed, 34 insertions(+), 31 deletions(-)

(limited to 'src')

diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
index babb8b463..c82f37d59 100644
--- a/.idea/runConfigurations/stlink.xml
+++ b/.idea/runConfigurations/stlink.xml
@@ -1,6 +1,6 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="stm32" PROGRAM_PARAMS="-p 28833 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.1.100.202311100844/tools/bin&quot; --frequency 8000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="stm32h563nucleo" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::28833" executable="/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.1.100.202310302101/tools/bin/ST-LINK_gdbserver" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="stm32" PROGRAM_PARAMS="-p 10458 -cp &quot;/opt/st/stm32cubeide_1.14.0/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.1.100.202311100844/tools/bin&quot; --frequency 8000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_device_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="stm32h563nucleo" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_device_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::10458" executable="/opt/st/stm32cubeide_1.14.0/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.1.100.202310302101/tools/bin/ST-LINK_gdbserver" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
     <method v="2">
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 5e54d0f56..7bf726f3f 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -200,8 +200,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
 // Inline helper
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) {
   uint8_t epnum = tu_edpt_number(ep_addr);
   uint8_t dir = tu_edpt_dir(ep_addr);
   // Fix -Werror=null-dereference
@@ -524,7 +523,7 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
   if((xfer->total_len != xfer->queued_len)) /* TX not complete */
   {
-      dcd_transmit_packet(xfer, EPindex);
+    dcd_transmit_packet(xfer, EPindex);
   }
   else /* TX Complete */
   {
@@ -533,10 +532,29 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
 }
 
 // Handle CTR interrupt for the RX/OUT direction
-//
 // Upon call, (wIstr & USB_ISTR_DIR) == 0U
-static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
-{
+static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
+  #ifdef FSDEV_BUS_32BIT
+  /* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf
+   * From STM32H503 errata 2.15.1: Buffer description table update completes after CTR interrupt triggers
+   * Description:
+   * - During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
+   * have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
+   * Workaround:
+   * - Software should ensure that a small delay is included before accessing the SRAM contents. This delay
+   * should be 800 ns in Full Speed mode and 6.4 μs in Low Speed mode
+   * - Since H5 can run up to 250Mhz -> 1 cycle = 4ns. Per errata, we need to wait 200 cycles. Though executing code
+   * also takes time, so we'll wait 40 cycles (count = 20).
+   * - Since Low Speed mode is not supported/popular, we will ignore it for now.
+   *
+   * Note: this errata also seems to apply to G0, U5, H5 etc.
+   */
+  volatile uint32_t cycle_count = 20; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
+  while (cycle_count > 0U) {
+    cycle_count--; // each count take 2 cycle (1 cycle for sub, 1 cycle for compare/jump)
+  }
+  #endif
+
   uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
   uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
   uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
@@ -545,8 +563,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
 
   // Verify the CTR_RX bit is set. This was in the ST Micro code,
   // but I'm not sure it's actually necessary?
-  if((wEPRegVal & USB_EP_CTR_RX) == 0U)
-  {
+  if((wEPRegVal & USB_EP_CTR_RX) == 0U) {
     return;
   }
 
@@ -633,26 +650,22 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
   // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared)
   if(ep_addr == 0u)
   {
-      // Always be prepared for a status packet...
+    // Always be prepared for a status packet...
     pcd_set_ep_rx_bufsize(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
     pcd_clear_rx_ep_ctr(USB, EPindex);
   }
 }
 
-static void dcd_ep_ctr_handler(void)
-{
+static void dcd_ep_ctr_handler(void) {
   uint32_t wIstr;
 
   /* stay in loop while pending interrupts */
-  while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U)
-  {
-
-    if ((wIstr & USB_ISTR_DIR) == 0U) /* TX/IN */
-    {
+  while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U) {
+    if ((wIstr & USB_ISTR_DIR) == 0U) {
+      /* TX/IN */
       dcd_ep_ctr_tx_handler(wIstr);
-    }
-    else /* RX/OUT*/
-    {
+    } else {
+      /* RX/OUT*/
       dcd_ep_ctr_rx_handler(wIstr);
     }
   }
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
index 15de95d23..5de25765d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
@@ -286,16 +286,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
-  /* WA: few cycles for RX PMA descriptor to update, otherwise doesn't return the correct value.
-     Note: required for G0, U5, H5 etc.
-  This workaround is ported from stm32h5xx_hal_pcd.h and fixes the issue when calling this function fast enough.
-  Reproduced with GCC ast optimization(O2/O3) and stm32h573i_dk with an high frequency.
-  Observed on Windows 10 where tud_task() is scheduled by interrupt handler.
-  */
-  volatile uint32_t count = 10; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
-  while (count > 0U) {
-    count--;
-  }
   return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
 #else
   __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
-- 
cgit v1.3.1


From 943a2a6db335d98843b73246fcce9aead0d38886 Mon Sep 17 00:00:00 2001
From: Wojciech Klimek <wjklimek1@gmail.com>
Date: Sun, 31 Mar 2024 23:11:49 +0200
Subject: Support for STM32H503 MCU

- added support for STM32H503RB on H503RB-NUCLEO board
- modified H5 family.c file to allow portability between H503 and H565/H573
- redefined USB_DRD_BASE to USB_DRD_FS_BASE if STM32H503xx is used
---
 hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake |   8 ++
 hw/bsp/stm32h5/boards/stm32h503nucleo/board.h     | 142 ++++++++++++++++++++++
 hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk    |   7 ++
 hw/bsp/stm32h5/boards/stm32h563nucleo/board.h     |  18 ++-
 hw/bsp/stm32h5/boards/stm32h573i_dk/board.h       |  18 ++-
 hw/bsp/stm32h5/family.c                           |  19 +--
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h     |   5 +
 7 files changed, 199 insertions(+), 18 deletions(-)
 create mode 100644 hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake
 create mode 100644 hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
 create mode 100644 hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk

(limited to 'src')

diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake
new file mode 100644
index 000000000..f0fb1d809
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32h503xx)
+set(JLINK_DEVICE stm32h503rb)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H503xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
new file mode 100644
index 000000000..96c126ab8
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
@@ -0,0 +1,142 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2023, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART3
+#define UART_CLK_EN           __USART3_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF13_USART3
+
+#define UART_TX_PIN           GPIO_PIN_3
+#define UART_RX_PIN           GPIO_PIN_4
+
+// //--------------------------------------------------------------------+
+// // RCC Clock
+// //--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 12;
+  RCC_OscInitStruct.PLL.PLLN = 250;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                                |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                                |RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  // Configure CRS clock source
+  __HAL_RCC_CRS_CLK_ENABLE();
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+  /* Select HSI48 as USB clock source */
+  RCC_PeriphCLKInitTypeDef usb_clk = {0 };
+  usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&usb_clk);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+}
+
+static inline void board_enable_vdd_usb(void)
+{
+  // USB in STM32H503RB does not require enabling VDD
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk
new file mode 100644
index 000000000..cf60098af
--- /dev/null
+++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = stm32h503xx
+
+CFLAGS += \
+	-DSTM32H503xx
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h503rb
diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
index 8e849f5c8..ccbcbd8e2 100644
--- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
+++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
@@ -54,10 +54,21 @@ extern "C" {
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void SystemClock_Config(void) {
+static inline void board_clock_init(void)
+{
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+
   /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
@@ -122,6 +133,11 @@ static inline void SystemClock_Config(void) {
   __HAL_RCC_USB_CLK_ENABLE();
 }
 
+static inline void board_enable_vdd_usb(void)
+{
+  /* Enable VDDUSB to power on USB peripheral */
+  HAL_PWREx_EnableVddUSB();
+}
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
index 674cf8e2a..87bf2ac1a 100644
--- a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
+++ b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
@@ -54,10 +54,20 @@ extern "C" {
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void SystemClock_Config(void) {
+static inline void board_clock_init(void) {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
+    // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+
   /** Configure the main internal regulator output voltage */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 
@@ -108,6 +118,12 @@ static inline void SystemClock_Config(void) {
   __HAL_RCC_USB_CLK_ENABLE();
 }
 
+static inline void board_enable_vdd_usb(void)
+{
+  /* Enable VDDUSB to power on USB peripheral */
+  HAL_PWREx_EnableVddUSB();
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c
index ed1389a12..0ff09a259 100644
--- a/hw/bsp/stm32h5/family.c
+++ b/hw/bsp/stm32h5/family.c
@@ -59,23 +59,10 @@ UART_HandleTypeDef UartHandle;
 
 void board_init(void) {
   HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS
-  SystemClock_Config(); // implemented in board.h
+  board_clock_init(); // implemented in board.h
   SystemCoreClockUpdate();
 
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOG_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-  __HAL_RCC_GPIOI_CLK_ENABLE();
-
-  //__HAL_RCC_SYSCFG_CLK_ENABLE();
-  //__HAL_RCC_PWR_CLK_ENABLE();
-
-      UART_CLK_EN();
+  UART_CLK_EN();
 
   #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -141,7 +128,7 @@ void board_init(void) {
   __HAL_RCC_USB_CLK_ENABLE();
 
   /* Enable VDDUSB */
-  HAL_PWREx_EnableVddUSB();
+  board_enable_vdd_usb();
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
index 5de25765d..8cedee5d1 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
@@ -115,6 +115,11 @@
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
   #include "stm32h5xx.h"
   #define FSDEV_BUS_32BIT
+
+  #ifdef STM32H503xx
+  #define USB_DRD_BASE USB_DRD_FS_BASE
+  #endif
+
   #define FSDEV_PMA_SIZE (2048u)
   #undef USB_PMAADDR
   #define USB_PMAADDR USB_DRD_PMAADDR
-- 
cgit v1.3.1


From 057278c0c6c159880e11f9b16de5735d8fc821ce Mon Sep 17 00:00:00 2001
From: Wojciech Klimek <wjklimek1@gmail.com>
Date: Mon, 1 Apr 2024 14:51:46 +0200
Subject: Support for STM32H503 MCU - review changes

Implemented changes suggested in the review:
- restored original name of SystemClock_Config() function
- some GPIO clocks are only enabled if macros are defined
- moved GPIO clocks init back to family.c
---
 hw/bsp/stm32h5/boards/stm32h503nucleo/board.h | 15 ++++-----------
 hw/bsp/stm32h5/boards/stm32h563nucleo/board.h | 12 +-----------
 hw/bsp/stm32h5/boards/stm32h573i_dk/board.h   | 12 +-----------
 hw/bsp/stm32h5/family.c                       | 19 ++++++++++++++++++-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h |  2 +-
 5 files changed, 25 insertions(+), 35 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
index 96c126ab8..0651b2694 100644
--- a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
+++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h
@@ -51,21 +51,14 @@ extern "C" {
 #define UART_TX_PIN           GPIO_PIN_3
 #define UART_RX_PIN           GPIO_PIN_4
 
-// //--------------------------------------------------------------------+
-// // RCC Clock
-// //--------------------------------------------------------------------+
-static inline void board_clock_init(void)
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void SystemClock_Config(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-    // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-
   /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
index ccbcbd8e2..df249242a 100644
--- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
+++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h
@@ -54,21 +54,11 @@ extern "C" {
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_clock_init(void)
+static inline void SystemClock_Config(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOG_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-  __HAL_RCC_GPIOI_CLK_ENABLE();
-
   /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
diff --git a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
index 87bf2ac1a..c58de13ee 100644
--- a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
+++ b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h
@@ -54,20 +54,10 @@ extern "C" {
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_clock_init(void) {
+static inline void SystemClock_Config(void) {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-    // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOG_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-  __HAL_RCC_GPIOI_CLK_ENABLE();
-
   /** Configure the main internal regulator output voltage */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 
diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c
index 0ff09a259..e4a9666b7 100644
--- a/hw/bsp/stm32h5/family.c
+++ b/hw/bsp/stm32h5/family.c
@@ -59,9 +59,26 @@ UART_HandleTypeDef UartHandle;
 
 void board_init(void) {
   HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS
-  board_clock_init(); // implemented in board.h
+  SystemClock_Config(); // implemented in board.h
   SystemCoreClockUpdate();
 
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  
+  #ifdef __HAL_RCC_GPIOE_CLK_ENABLE
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  #endif
+  #ifdef __HAL_RCC_GPIOG_CLK_ENABLE
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  #endif
+  #ifdef __HAL_RCC_GPIOI_CLK_ENABLE
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  #endif
+
   UART_CLK_EN();
 
   #if CFG_TUSB_OS == OPT_OS_NONE
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
index 8cedee5d1..946ad2c7c 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
@@ -116,7 +116,7 @@
   #include "stm32h5xx.h"
   #define FSDEV_BUS_32BIT
 
-  #ifdef STM32H503xx
+  #if !defined(USB_DRD_BASE) && defined(USB_DRD_FS_BASE)
   #define USB_DRD_BASE USB_DRD_FS_BASE
   #endif
 
-- 
cgit v1.3.1


From 05f9cab1916195ceb55d73efa56d226b2451f5d1 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Mon, 1 Apr 2024 19:48:45 +0200
Subject: UAC2: refactor interrupt endpoint support.

---
 src/class/audio/audio.h        |  25 +++++++++
 src/class/audio/audio_device.c | 114 ++++++++++++++++++-----------------------
 src/class/audio/audio_device.h |  51 +++---------------
 src/device/usbd.h              |  11 ++--
 4 files changed, 88 insertions(+), 113 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index 70d431282..d6f3e22e2 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -924,6 +924,31 @@ typedef struct TU_ATTR_PACKED {
     } subrange[numSubRanges];                   \
 }
 
+// 6.1 Interrupt Data Message Format
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t bInfo;
+  uint8_t bAttribute;
+  union
+  {
+    uint16_t wValue;
+    struct
+    {
+      uint8_t wValue_cn_or_mcn;
+      uint8_t wValue_cs;
+    };
+  };
+  union
+  {
+    uint16_t wIndex;
+    struct
+    {
+      uint8_t wIndex_ep_or_int;
+      uint8_t wIndex_entity_id;
+    };
+  };
+} audio_interrupt_data_t;
+
 /** @} */
 
 #ifdef __cplusplus
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index f4e7de0c8..93e995c56 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -301,8 +301,8 @@ typedef struct
 
 #endif
 
-#if CFG_TUD_AUDIO_INT_EPSIZE_IN
-  uint8_t ep_int;           // Audio control interrupt EP.
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+  uint8_t ep_int;               // Audio control interrupt EP.
 #endif
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
@@ -358,8 +358,8 @@ typedef struct
 #endif
 
   // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
-#if CFG_TUD_AUDIO_INT_EPSIZE_IN
-  CFG_TUSB_MEM_ALIGN uint8_t ep_int_buf[CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE];
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+  CFG_TUSB_MEM_ALIGN uint8_t ep_int_buf[6];
 #endif
 
   // Decoding parameters - parameters are set when alternate AS interface is set by host
@@ -826,26 +826,29 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff(uint8_t func_id, uint8_t ff_idx)
 
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-
 // If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_done_cb() is called in inform user
-uint16_t tud_audio_int_n_write(uint8_t func_id, uint8_t const* buffer, uint16_t len)
+bool tud_audio_int_n_write(uint8_t func_id, const audio_interrupt_data_t * data)
 {
-  TU_VERIFY(_audiod_fct[func_id].ep_int != 0);
-
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
+  TU_VERIFY(_audiod_fct[func_id].ep_int != 0);
+
   // We write directly into the EP's buffer - abort if previous transfer not complete
-  TU_VERIFY(!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int));
+  TU_VERIFY(usbd_edpt_claim(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int));
 
   // Check length
-  TU_VERIFY(tu_memcpy_s(_audiod_fct[func_id].ep_int_buf, CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE,  buffer, len)==0);
-
-  // Schedule transmit
-  TU_VERIFY(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int, _audiod_fct[func_id].ep_int_buf, len));
+  if (tu_memcpy_s(_audiod_fct[func_id].ep_int_buf, sizeof(_audiod_fct[func_id].ep_int_buf),  data, sizeof(audio_interrupt_data_t)) == 0)
+  {
+    // Schedule transmit
+    TU_ASSERT(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int, _audiod_fct[func_id].ep_int_buf, sizeof(_audiod_fct[func_id].ep_int_buf)), 0);
+  } else
+  {
+    // Release endpoint since we don't make any transfer
+    usbd_edpt_release(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int);
+  }
 
   return true;
 }
-
 #endif
 
 // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission.
@@ -1091,48 +1094,6 @@ static inline bool audiod_fb_send(uint8_t rhport, audiod_function_t *audio)
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-static bool set_int_number(audiod_function_t *audio)
-{
-
-  uint8_t const *p_desc = audio->p_desc;
-  // Get pointer at end
-  uint8_t const *p_desc_end = audio->p_desc + audio->desc_length - TUD_AUDIO_DESC_IAD_LEN;
-
-
-  bool found = false;
-  while (!found && p_desc < p_desc_end)
-  {
-    // For each interface/alternate
-    if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE)
-    {
-      uint8_t foundEPs = 0, nEps = ((tusb_desc_interface_t const * )p_desc)->bNumEndpoints;
-      while (!found && foundEPs < nEps && p_desc < p_desc_end)
-      {
-        // For each endpoint
-        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
-        {
-          tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-          uint8_t const ep_addr = desc_ep->bEndpointAddress;
-          // If endpoint is input-direction and interrupt-type
-          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.xfer == 0x03)   // Check if usage is interrupt EP
-          {
-            // Store endpoint number and open endpoint
-            audio->ep_int = ep_addr;
-            TU_ASSERT(usbd_edpt_open(audio->rhport, desc_ep));
-            found = true;
-          }
-          foundEPs += 1;
-        }
-        p_desc = tu_desc_next(p_desc);
-      }
-    }
-    p_desc = tu_desc_next(p_desc);
-  }
-  return found;
-}
-#endif
-
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
@@ -1492,10 +1453,11 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   // Verify version is correct - this check can be omitted
   TU_VERIFY(itf_desc->bInterfaceProtocol == AUDIO_INT_PROTOCOL_CODE_V2);
 
-  // Verify interrupt control EP is enabled if demanded by descriptor - this should be best some static check however - this check can be omitted
-  if (itf_desc->bNumEndpoints == 1) // 0 or 1 EPs are allowed
+  // Verify interrupt control EP is enabled if demanded by descriptor
+  TU_ASSERT(itf_desc->bNumEndpoints <= 1); // 0 or 1 EPs are allowed
+  if (itf_desc->bNumEndpoints == 1)
   {
-    TU_VERIFY(CFG_TUD_AUDIO_INT_EPSIZE_IN > 0);
+    TU_ASSERT(CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP);
   }
 
   // Alternate setting MUST be zero - this check can be omitted
@@ -1639,6 +1601,31 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       }
 #endif // CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
 
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
+      {
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning
+        while (p_desc_end - p_desc > 0)
+        {
+          // For each endpoint
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+          {
+            tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            uint8_t const ep_addr = desc_ep->bEndpointAddress;
+            // If endpoint is input-direction and interrupt-type
+            if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.xfer == TUSB_XFER_INTERRUPT)
+            {
+              // Store endpoint number and open endpoint
+              _audiod_fct[i].ep_int = ep_addr;
+              TU_ASSERT(usbd_edpt_open(_audiod_fct[i].rhport, desc_ep));
+            }
+          }
+          p_desc = tu_desc_next(p_desc);
+        }
+      }
+#endif
+
       break;
     }
   }
@@ -1649,10 +1636,6 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   // This is all we need so far - the EPs are setup by a later set_interface request (as per UAC2 specification)
   uint16_t drv_len = _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;    // - TUD_AUDIO_DESC_IAD_LEN since tinyUSB already handles the IAD descriptor
 
-#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-  TU_ASSERT(set_int_number(&_audiod_fct[i]));
-#endif
-
   return drv_len;
 }
 
@@ -2169,7 +2152,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
   {
     audiod_function_t* audio = &_audiod_fct[func_id];
 
-#if CFG_TUD_AUDIO_INT_EPSIZE_IN
+#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
 
     // Data transmission of control interrupt finished
     if (audio->ep_int == ep_addr)
@@ -2181,7 +2164,8 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
       // I assume here, that things above are handled by PHY
       // All transmission is done - what remains to do is to inform job was completed
 
-      if (tud_audio_int_done_cb) TU_VERIFY(tud_audio_int_done_cb(rhport, (uint16_t) xferred_bytes));
+      if (tud_audio_int_done_cb) tud_audio_int_done_cb(rhport);
+      return true;
     }
 
 #endif
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 70bbd7ff6..040a760d6 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -198,21 +198,7 @@
 
 // Enable/disable interrupt EP (required for notifying host of control changes)
 #ifndef CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-#define CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP                    0                             // Feedback - 0 or 1
-#endif
-
-// Audio interrupt control EP size - disabled if 0
-#ifndef CFG_TUD_AUDIO_INT_EPSIZE_IN
-// Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
-#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-#define CFG_TUD_AUDIO_INT_EPSIZE_IN                     6
-#else
-#define CFG_TUD_AUDIO_INT_EPSIZE_IN                     0
-#endif
-#endif
-
-#ifndef CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE
-#define CFG_TUD_AUDIO_INT_EP_IN_SW_BUFFER_SIZE          6                             // Buffer size of audio control interrupt EP - 6 Bytes according to UAC 2 specification (p. 74)
+#define CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP                   0                             // Feedback - 0 or 1
 #endif
 
 // Use software encoding/decoding
@@ -404,7 +390,7 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_i
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-uint16_t    tud_audio_int_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
+bool    tud_audio_int_n_write                     (uint8_t func_id, const audio_interrupt_data_t * data);
 #endif
 
 
@@ -448,7 +434,7 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff        (uint8_t ff_idx);
 // INT CTR API
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-static inline uint16_t tud_audio_int_write              (uint8_t const* buffer, uint16_t len);
+static inline bool tud_audio_int_write                      (const audio_interrupt_data_t * data);
 #endif
 
 // Buffer control EP data and schedule a transmit
@@ -548,32 +534,7 @@ TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-// UAC2 §6.1 "interrupt data message"
-typedef struct TU_ATTR_PACKED
-{
-  uint8_t bInfo;
-  uint8_t bAttribute;
-  union TU_ATTR_PACKED
-  {
-    uint16_t wValue;
-    struct TU_ATTR_PACKED
-    {
-      uint8_t wValue_cn_or_mcn;
-      uint8_t wValue_cs;
-    };
-  };
-  union TU_ATTR_PACKED
-  {
-    uint16_t wIndex;
-    struct TU_ATTR_PACKED
-    {
-      uint8_t wIndex_ep_or_int;
-      uint8_t wIndex_entity_id;
-    };
-  };
-} audio_status_update_t;
-
-TU_ATTR_WEAK bool tud_audio_int_done_cb(uint8_t rhport, uint16_t n_bytes_copied);
+TU_ATTR_WEAK void tud_audio_int_done_cb(uint8_t rhport);
 #endif
 
 // Invoked when audio set interface request received
@@ -705,9 +666,9 @@ static inline tu_fifo_t* tud_audio_get_tx_support_ff(uint8_t ff_idx)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-static inline uint16_t tud_audio_int_write(uint8_t const* buffer, uint16_t len)
+static inline bool tud_audio_int_write(const audio_interrupt_data_t * data)
 {
-  return tud_audio_int_n_write(0, buffer, len);
+  return tud_audio_int_n_write(0, data);
 }
 #endif
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index cf500143a..2e3987b99 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -393,6 +393,11 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 // For more channels, add definitions here
 
+/* Standard AC Interrupt Endpoint Descriptor(4.8.2.1) */
+#define TUD_AUDIO_DESC_STD_AC_INT_EP_LEN 7
+#define TUD_AUDIO_DESC_STD_AC_INT_EP(_ep, _interval) \
+  TUD_AUDIO_DESC_STD_AC_INT_EP_LEN, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(6), _interval
+
 /* Standard AS Interface Descriptor(4.9.1) */
 #define TUD_AUDIO_DESC_STD_AS_INT_LEN 9
 #define TUD_AUDIO_DESC_STD_AS_INT(_itfnum, _altset, _nEPs, _stridx) \
@@ -468,7 +473,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -517,7 +522,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -565,7 +570,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) ((uint8_t)TUSB_XFER_ISOCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_ASYNCHRONOUS | (uint8_t)TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
-- 
cgit v1.3.1


From 7ca988018ee057a66ab7d5635069fbc695182d2d Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Mon, 1 Apr 2024 19:50:52 +0200
Subject: UAC2: fix mounted condition.

---
 src/class/audio/audio_device.c | 21 ++++-----------------
 1 file changed, 4 insertions(+), 17 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 93e995c56..9a361419b 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -305,6 +305,8 @@ typedef struct
   uint8_t ep_int;               // Audio control interrupt EP.
 #endif
 
+  bool mounted;                 // Device opened
+
   /*------------- From this point, data is not cleared by bus reset -------------*/
 
   uint16_t desc_length;         // Length of audio function descriptor
@@ -486,23 +488,7 @@ bool tud_audio_n_mounted(uint8_t func_id)
   TU_VERIFY(func_id < CFG_TUD_AUDIO);
   audiod_function_t* audio = &_audiod_fct[func_id];
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-  if (audio->ep_out == 0) return false;
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_EP_IN
-  if (audio->ep_in == 0) return false;
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP
-  if (audio->ep_int == 0) return false;
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-  if (audio->ep_fb == 0) return false;
-#endif
-
-  return true;
+  return audio->mounted;
 }
 
 //--------------------------------------------------------------------+
@@ -1626,6 +1612,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       }
 #endif
 
+      _audiod_fct[i].mounted = true;
       break;
     }
   }
-- 
cgit v1.3.1


From bd2210b812cca0f56fc54ab9ebe3e48482baa653 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Apr 2024 12:36:00 +0700
Subject: always limit number of NAK per endpoint per usb frame to save cpu
 usage. Default to 1 NAK per endpoint

---
 examples/host/bare_api/src/tusb_config.h           |   1 -
 examples/host/cdc_msc_hid/src/tusb_config.h        |   1 -
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    |   1 -
 examples/host/hid_controller/src/tusb_config.h     |   1 -
 examples/host/msc_file_explorer/src/tusb_config.h  |   1 -
 src/portable/analog/max3421/hcd_max3421.c          | 144 ++++++++-------------
 6 files changed, 56 insertions(+), 93 deletions(-)

(limited to 'src')

diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index d8e81aa82..432446e94 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -72,7 +72,6 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 8a56ebc2b..a59a0ffb9 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -72,7 +72,6 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index 7705be5c8..35de5ee50 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -77,7 +77,6 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index f087a93cf..3ac591d8f 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -72,7 +72,6 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index 05b9fa174..c798b4383 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -72,7 +72,6 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // #define CFG_TUH_RPI_PIO_USB   1 // use pio-usb as host controller
   // #define CFG_TUH_MAX3421       1 // use max3421 as host controller
-  // #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 3 // max. transfer attempts per frame
 
   // host roothub port is 1 if using either pio-usb or max3421
   #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 324638cb8..3eb3f796f 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -166,35 +166,17 @@ enum {
   DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
 };
 
+enum {
+  MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame
+};
+
 enum {
   EP_STATE_IDLE        = 0,
-  EP_STATE_ATTEMPT1    = 1, // pending 1st attempt
-  #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
-    EP_STATE_ATTEMPT2  = 2, // don't change order
-    EP_STATE_ATTEMPT3  = 3, // need to be incrementable
-    EP_STATE_ATTEMPT4  = 4,
-    EP_STATE_ATTEMPT5  = 5,
-    EP_STATE_ATTEMPT6  = 6,
-    EP_STATE_ATTEMPT7  = 7,
-    EP_STATE_ATTEMPT8  = 8,
-    EP_STATE_ATTEMPT9  = 9,
-    EP_STATE_ATTEMPT10 = 10,
-    EP_STATE_SUSPENDED,    // keep next behind last attempt
-  #endif
   EP_STATE_COMPLETE,
-  EP_STATE_QUANTITY        // not used. only to get quantity. keep last
+  EP_STATE_ATTEMPT_1, // pending 1st attempt
+  EP_STATE_ATTEMPT_MAX = 15
 };
 
-TU_VERIFY_STATIC(EP_STATE_QUANTITY <= 16, "no more than 16 states possible. ep->state has 4 bits");
-
-#if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
-  #define EP_STATE_ATTEMPT_QUANTITY (EP_STATE_SUSPENDED - 1)
-  TU_VERIFY_STATIC(CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME >= 1 &&
-                   CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME <= EP_STATE_ATTEMPT_QUANTITY, "unsupported attempt quantity");
-#else
-  #define EP_STATE_ATTEMPT_QUANTITY 1
-#endif
-
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
@@ -223,6 +205,8 @@ typedef struct {
 TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct");
 
 typedef struct {
+  volatile uint16_t frame_count;
+
   // cached register
   uint8_t sndbc;
   uint8_t hirq;
@@ -232,17 +216,17 @@ typedef struct {
   uint8_t hxfr;
 
   atomic_flag busy; // busy transferring
-  volatile uint16_t frame_count;
-
-  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
 
-  OSAL_MUTEX_DEF(spi_mutexdef);
 #if OSAL_MUTEX_REQUIRED
+  OSAL_MUTEX_DEF(spi_mutexdef);
   osal_mutex_t spi_mutex;
 #endif
+
+  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
 } max3421_data_t;
 
 static max3421_data_t _hcd_data;
+static uint8_t _max_nak = MAX_NAK_DEFAULT; // max NAK before giving up in a usb frame
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E
@@ -332,7 +316,6 @@ static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint
   tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
 
   max3421_spi_unlock(rhport, in_isr);
-
 }
 
 static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
@@ -421,18 +404,22 @@ static void free_ep(uint8_t daddr) {
   }
 }
 
+// Check if endpoint has an queued transfer
+TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) {
+  uint8_t const state = ep->state;
+  return ep->packet_size && state >= EP_STATE_ATTEMPT_1 && state < EP_STATE_ATTEMPT_1 + _max_nak;
+}
+
+// Find the next pending endpoint using round-robin scheduling, starting from next endpoint.
+// return NULL if not found
+// TODO respect interrupt endpoint's interval
 static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
-  // search for next pending endpoint using round-robin scheduling
-  // if no other endpoint is pending and current endpoint is still pending, the current endpoint will be returned
-  // if no other endpoint is pending and current endpoint is not pending, NULL will be returned
-  // TODO maybe prioritisation control/interrupt/bulk/iso
   size_t const idx = (size_t) (cur_ep - _hcd_data.ep);
 
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->state >= EP_STATE_ATTEMPT1 && ep->state <= EP_STATE_ATTEMPT_QUANTITY && ep->packet_size) {
-//      TU_LOG3("next pending i = %u\r\n", i);
+    if (is_ep_pending(ep)) {
       return ep;
     }
   }
@@ -440,8 +427,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // wrap around including current endpoint
   for (size_t i = 0; i <= idx; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->state >= EP_STATE_ATTEMPT1 && ep->state <= EP_STATE_ATTEMPT_QUANTITY && ep->packet_size) {
-//      TU_LOG3("next pending i = %u\r\n", i);
+    if (is_ep_pending(ep)) {
       return ep;
     }
   }
@@ -469,7 +455,9 @@ bool hcd_init(uint8_t rhport) {
   tuh_max3421_int_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
+  TU_LOG2_INT(sizeof(atomic_flag));
   TU_LOG2_INT(sizeof(max3421_data_t));
+  TU_LOG2_INT(offsetof(max3421_data_t, ep));
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
   _hcd_data.peraddr = 0xff; // invalid
@@ -689,7 +677,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
-  ep->state = EP_STATE_ATTEMPT1;
+  ep->state = EP_STATE_ATTEMPT_1;
 
   if ( ep_num == 0 ) {
     ep->is_setup = 0;
@@ -726,7 +714,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->buf = (uint8_t*)(uintptr_t) setup_packet;
   ep->total_len = 8;
   ep->xferred_len = 0;
-  ep->state = EP_STATE_ATTEMPT1;
+  ep->state = EP_STATE_ATTEMPT_1;
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
@@ -839,40 +827,24 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
       break;
 
     case HRSL_NAK:
-      // TODO no retry for iso in current frame
-      // TODO retry limitation over all (not only per frame)
       if (ep_num == 0) {
-        // setup/control => retry immediately
+        // control endpoint -> retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, in_isr);
-      #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
-      } else if (ep->state == CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME) {
-        // no more retry this frame if max. attempts are reached => suspend and retry it next frame
-        ep->state = EP_STATE_SUSPENDED;
-
-        max3421_ep_t * next_ep = find_next_pending_ep(ep);
-        if (next_ep) {
-          // switch to next pending endpoint TODO could have issue with double buffered if not clear previously out data
-          xact_inout(rhport, next_ep, true, in_isr);
-        } else {
-          // no more pending => clear busy
-          atomic_flag_clear(&_hcd_data.busy);
-        }
-      #endif
       } else {
-        // another attempt
-        #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
+        if (ep->state < EP_STATE_ATTEMPT_MAX) {
           ep->state++;
-        #endif
+        }
 
         max3421_ep_t * next_ep = find_next_pending_ep(ep);
         if (ep == next_ep) {
-          // this endpoint is only one pending => retry immediately
+          // this endpoint is only one pending -> retry immediately
           hxfr_write(rhport, _hcd_data.hxfr, in_isr);
         } else if (next_ep) {
           // switch to next pending endpoint TODO could have issue with double buffered if not clear previously out data
           xact_inout(rhport, next_ep, true, in_isr);
         } else {
-          TU_ASSERT(false,);
+          // no more pending in this frame -> clear busy
+          atomic_flag_clear(&_hcd_data.busy);
         }
       }
       return;
@@ -957,28 +929,24 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
 
-    #if CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
-      // endpoints retry or restart attempt next frame
-      for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
-        max3421_ep_t * ep = &_hcd_data.ep[i];
-
-        // retry the endpoints that are suspended (NAK) last frame
-        if (ep->state == EP_STATE_SUSPENDED) {
-          // resume and retry suspended endpoint with attempt 1
-          ep->state = EP_STATE_ATTEMPT1;
-
-          if (ep->packet_size) { // first test packet_size before atomic_flag_test_and_set()
-            if (!atomic_flag_test_and_set(&_hcd_data.busy) ) {
-              // trigger endpoint to be retried
-              xact_inout(rhport, ep, true, in_isr);
-            }
-          }
-        } else if (ep->state > EP_STATE_ATTEMPT1 && ep->state <= CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME) {
-          // restart all other running/pending endpoints
-          ep->state = EP_STATE_ATTEMPT1;
+    max3421_ep_t* ep_retry = NULL;
+
+    // reset all endpoints attempt counter
+    for (size_t i = 0; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+      max3421_ep_t* ep = &_hcd_data.ep[i];
+      if (ep->packet_size && ep->state > EP_STATE_ATTEMPT_1) {
+        ep->state = EP_STATE_ATTEMPT_1;
+
+        if (ep_retry == NULL) {
+          ep_retry = ep;
         }
       }
-    #endif
+    }
+
+    // start usb transfer if not busy
+    if (ep_retry != NULL && !atomic_flag_test_and_set(&_hcd_data.busy)) {
+      xact_inout(rhport, ep_retry, true, in_isr);
+    }
   }
 
   if (hirq & HIRQ_CONDET_IRQ) {
@@ -987,17 +955,17 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 
   // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
   // not call this handler again. So we need to loop until all IRQ are cleared
-  while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) {
-    if ( hirq & HIRQ_RCVDAV_IRQ ) {
+  while (hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ)) {
+    if (hirq & HIRQ_RCVDAV_IRQ) {
       uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
-      max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
+      max3421_ep_t* ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
       uint8_t xact_len = 0;
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
-      while ( hirq & HIRQ_RCVDAV_IRQ ) {
+      while (hirq & HIRQ_RCVDAV_IRQ) {
         uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
         xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
-        if ( xact_len ) {
+        if (xact_len) {
           fifo_read(rhport, ep->buf, xact_len, in_isr);
           ep->buf += xact_len;
           ep->xferred_len += xact_len;
@@ -1008,12 +976,12 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
         hirq = reg_read(rhport, HIRQ_ADDR, in_isr);
       }
 
-      if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+      if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
         ep->state = EP_STATE_COMPLETE;
       }
     }
 
-    if ( hirq & HIRQ_HXFRDN_IRQ ) {
+    if (hirq & HIRQ_HXFRDN_IRQ) {
       hirq_write(rhport, HIRQ_HXFRDN_IRQ, in_isr);
       handle_xfer_done(rhport, in_isr);
     }
-- 
cgit v1.3.1


From e802fe0677c901a444e7c9b5d67be2a1f400adee Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Apr 2024 14:28:41 +0700
Subject: refactor: add hxfr per endpoint

---
 src/portable/analog/max3421/hcd_max3421.c | 100 +++++++++++++++---------------
 src/tusb_option.h                         |  13 +---
 2 files changed, 52 insertions(+), 61 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 3eb3f796f..1b182e551 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -184,17 +184,21 @@ enum {
 typedef struct {
   uint8_t daddr;
 
-  struct TU_ATTR_PACKED {
-    uint8_t state         : 4;
-    uint8_t is_setup      : 1; // also bit 4 in HXFR reg (smaller code, no shift necessary)
-    uint8_t ep_dir        : 1; // also bit 5 in HXFR reg (smaller code, no shift necessary)
-    uint8_t is_iso        : 1; // also bit 6 in HXFR reg (smaller code, no shift necessary)
-    uint8_t data_toggle   : 1;
+  union { ;
+    struct TU_ATTR_PACKED {
+      uint8_t ep_num   : 4;
+      uint8_t is_setup : 1;
+      uint8_t is_out   : 1;
+      uint8_t is_iso   : 1;
+    }hxfr_bm;
+
+    uint8_t hxfr;
   };
 
   struct TU_ATTR_PACKED {
-    uint8_t ep_num : 4;
-    uint16_t packet_size : 12;
+    uint8_t state        : 4;
+    uint8_t data_toggle  : 1;
+    uint16_t packet_size : 11;
   };
 
   uint16_t total_len;
@@ -370,10 +374,11 @@ TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t dat
 //--------------------------------------------------------------------+
 
 static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  uint8_t const is_out = 1-ep_dir;
   for(size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    // for control endpoint, skip direction check
-    if (daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) {
+    // control endpoint is bi-direction (skip check)
+    if (daddr == ep->daddr && ep_num == ep->hxfr_bm.ep_num && (ep_num == 0 || is_out == ep->hxfr_bm.is_out)) {
       return ep;
     }
   }
@@ -577,7 +582,6 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
 // Open an endpoint
 bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc) {
   (void) rhport;
-  (void) daddr;
 
   uint8_t const ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
   tusb_dir_t const ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
@@ -589,12 +593,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
     ep = allocate_ep();
     TU_ASSERT(ep);
     ep->daddr = daddr;
-    ep->ep_num = (uint8_t) (ep_num & 0x0f);
-    ep->ep_dir = (ep_dir == TUSB_DIR_IN) ? 1 : 0;
-  }
-
-  if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) {
-    ep->is_iso = 1;
+    ep->hxfr_bm.ep_num = (uint8_t) (ep_num & 0x0f);
+    ep->hxfr_bm.is_out = (ep_dir == TUSB_DIR_OUT) ? 1 : 0;
+    ep->hxfr_bm.is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0;
   }
 
   ep->packet_size = (uint16_t) (tu_edpt_packet_size(ep_desc) & 0x7ff);
@@ -602,7 +603,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
   return true;
 }
 
-void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 12: Programming BULK-OUT Transfers
   // TODO double buffered
   if (switch_ep) {
@@ -618,12 +619,10 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
   }
   sndbc_write(rhport, xact_len, in_isr);
-
-  uint8_t const hxfr = (uint8_t ) (ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0));
-  hxfr_write(rhport, hxfr, in_isr);
+  hxfr_write(rhport, ep->hxfr, in_isr);
 }
 
-void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+static void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 13: Programming BULK-IN Transfers
   if (switch_ep) {
     peraddr_write(rhport, ep->daddr, in_isr);
@@ -632,34 +631,36 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  uint8_t const hxfr = (uint8_t) (ep->ep_num | (ep->is_iso ? HXFR_ISO : 0));
-  hxfr_write(rhport, hxfr, in_isr);
+  hxfr_write(rhport, ep->hxfr, in_isr);
+}
+
+static void xact_setup(uint8_t rhport, max3421_ep_t *ep, bool in_isr) {
+  peraddr_write(rhport, ep->daddr, in_isr);
+  fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr);
+  hxfr_write(rhport, HXFR_SETUP, in_isr);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline
-void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
-  if (ep->ep_num == 0 ) {
+static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  if (ep->hxfr_bm.ep_num == 0 ) {
     // setup
-    if (ep->is_setup) {
-      peraddr_write(rhport, ep->daddr, in_isr);
-      fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr);
-      hxfr_write(rhport, HXFR_SETUP, in_isr);
+    if (ep->hxfr_bm.is_setup) {
+      xact_setup(rhport, ep, in_isr);
       return;
     }
 
     // status
     if (ep->buf == NULL || ep->total_len == 0) {
-      uint8_t const hxfr = HXFR_HS | (ep->ep_dir ? 0 : HXFR_OUT_NIN);
+      uint8_t const hxfr = HXFR_HS | (ep->hxfr_bm.is_out ? HXFR_OUT_NIN : 0);
       peraddr_write(rhport, ep->daddr, in_isr);
       hxfr_write(rhport, hxfr, in_isr);
       return;
     }
   }
 
-  if (ep->ep_dir) {
-    xact_in(rhport, ep, switch_ep, in_isr);
-  }else {
+  if (ep->hxfr_bm.is_out) {
     xact_out(rhport, ep, switch_ep, in_isr);
+  }else {
+    xact_in(rhport, ep, switch_ep, in_isr);
   }
 }
 
@@ -672,21 +673,21 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   TU_VERIFY(ep);
 
   // control transfer can switch direction
-  ep->ep_dir = ep_dir ? 1u : 0u;
+  ep->hxfr_bm.is_out = ep_dir ? 0u : 1u;
 
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
   ep->state = EP_STATE_ATTEMPT_1;
 
-  if ( ep_num == 0 ) {
-    ep->is_setup = 0;
+  if (ep_num == 0) {
+    ep->hxfr_bm.is_setup = 0;
     ep->data_toggle = 1;
   }
 
   // carry out transfer if not busy
-  if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
-    xact_inout(rhport, ep, true, false);
+  if (!atomic_flag_test_and_set(&_hcd_data.busy)) {
+    xact_generic(rhport, ep, true, false);
   }
 
   return true;
@@ -709,16 +710,16 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
   TU_ASSERT(ep);
 
-  ep->ep_dir = 0;
-  ep->is_setup = 1;
+  ep->hxfr_bm.is_out = 1;
+  ep->hxfr_bm.is_setup = 1;
   ep->buf = (uint8_t*)(uintptr_t) setup_packet;
   ep->total_len = 8;
   ep->xferred_len = 0;
   ep->state = EP_STATE_ATTEMPT_1;
 
   // carry out transfer if not busy
-  if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
-    xact_inout(rhport, ep, true, false);
+  if (!atomic_flag_test_and_set(&_hcd_data.busy)) {
+    xact_setup(rhport, ep, false);
   }
 
   return true;
@@ -783,10 +784,11 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
 }
 
 static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl, bool in_isr) {
-  uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
+  uint8_t const ep_dir = 1-ep->hxfr_bm.is_out;
+  uint8_t const ep_addr = tu_edpt_addr(ep->hxfr_bm.ep_num, ep_dir);
 
   // save data toggle
-  if (ep->ep_dir) {
+  if (ep_dir) {
     ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1u : 0u;
   }else {
     ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1u : 0u;
@@ -798,7 +800,7 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
   // Find next pending endpoint
   max3421_ep_t * next_ep = find_next_pending_ep(ep);
   if (next_ep) {
-    xact_inout(rhport, next_ep, true, in_isr);
+    xact_generic(rhport, next_ep, true, in_isr);
   }else {
     // no more pending
     atomic_flag_clear(&_hcd_data.busy);
@@ -841,7 +843,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
           hxfr_write(rhport, _hcd_data.hxfr, in_isr);
         } else if (next_ep) {
           // switch to next pending endpoint TODO could have issue with double buffered if not clear previously out data
-          xact_inout(rhport, next_ep, true, in_isr);
+          xact_generic(rhport, next_ep, true, in_isr);
         } else {
           // no more pending in this frame -> clear busy
           atomic_flag_clear(&_hcd_data.busy);
@@ -945,7 +947,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
 
     // start usb transfer if not busy
     if (ep_retry != NULL && !atomic_flag_test_and_set(&_hcd_data.busy)) {
-      xact_inout(rhport, ep_retry, true, in_isr);
+      xact_generic(rhport, ep_retry, true, in_isr);
     }
   }
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 18cc8a82c..f90fb7026 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -34,7 +34,7 @@
 #define TUSB_VERSION_MAJOR     0
 #define TUSB_VERSION_MINOR     16
 #define TUSB_VERSION_REVISION  0
-#define TUSB_VERSION_BUILD     1
+#define TUSB_VERSION_BUILD     2
 
 #define TUSB_VERSION_NUMBER    (TUSB_VERSION_MAJOR << 24 | TUSB_VERSION_MINOR << 16 | TUSB_VERSION_REVISION << 8 | TUSB_VERSION_BUILD)
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
@@ -529,17 +529,6 @@
   #define CFG_TUH_MAX3421  0
 #endif
 
-// MAX3421 Host max. transfer attempts per frame (except control and iso)
-// retry quantity = (CFG_TUH_MAX3421_MAX_ATTEMPS_PER_FRAME - 1)
-// 0 = endless retries. is default to keep compatibility
-//     => this may overload MCU with permanently repeating NAK interrupts
-//     => possible increased USB traffic, increased latencies, reduced data throughput
-// a usual attempt quantity is 3 (reference: the book "USB Complete" by Jan Axelson)
-#ifndef CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME
-  #define CFG_TUH_MAX3421_MAX_ATTEMPTS_PER_FRAME 0
-#endif
-
-
 //--------------------------------------------------------------------+
 // TypeC Options (Default)
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 7d3d60f96de3f6e15291c9302463c294e2dc98de Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Apr 2024 16:38:40 +0700
Subject: add hcd_configure() to change max NAK dynamically

---
 src/host/hcd.h                            |  2 +-
 src/host/usbh.c                           | 13 ++++++++-----
 src/host/usbh.h                           | 14 ++++++++++++--
 src/portable/analog/max3421/hcd_max3421.c | 17 +++++++++++------
 src/tusb_option.h                         |  1 -
 5 files changed, 32 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/host/hcd.h b/src/host/hcd.h
index d5804c608..5547c7cc5 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -125,7 +125,7 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
 //--------------------------------------------------------------------+
 
 // optional hcd configuration, called by tuh_configure()
-bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_ATTR_WEAK;
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
 
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 05091736e..aa0603d47 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -52,6 +52,13 @@ TU_ATTR_WEAK bool hcd_deinit(uint8_t rhport) {
   return false;
 }
 
+TU_ATTR_WEAK bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+  return false;
+}
+
 TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
   (void) rhport;
   (void) eventid;
@@ -332,11 +339,7 @@ bool tuh_rhport_reset_bus(uint8_t rhport, bool active) {
 //--------------------------------------------------------------------+
 
 bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
-  if ( hcd_configure ) {
-    return hcd_configure(rhport, cfg_id, cfg_param);
-  } else {
-    return false;
-  }
+  return hcd_configure(rhport, cfg_id, cfg_param);
 }
 
 static void clear_device(usbh_device_t* dev) {
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 0e31e80a7..57362c778 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -73,11 +73,21 @@ typedef struct {
   tusb_desc_interface_t desc;
 } tuh_itf_info_t;
 
-// ConfigID for tuh_config()
+// ConfigID for tuh_configure()
 enum {
-  TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 << 8 // cfg_param: pio_usb_configuration_t
+  TUH_CFGID_INVALID = 0,
+  TUH_CFGID_RPI_PIO_USB_CONFIGURATION = 100, // cfg_param: pio_usb_configuration_t
+  TUH_CFGID_MAX3421 = 200,
 };
 
+typedef union {
+  // For TUH_CFGID_RPI_PIO_USB_CONFIGURATION use pio_usb_configuration_t
+
+  struct {
+    uint8_t max_nak;
+  } max3421;
+} tuh_configure_param_t;
+
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK
 //--------------------------------------------------------------------+
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 1b182e551..12d80e0b5 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -30,6 +30,7 @@
 
 #include <stdatomic.h>
 #include "host/hcd.h"
+#include "host/usbh.h"
 
 //--------------------------------------------------------------------+
 //
@@ -230,7 +231,9 @@ typedef struct {
 } max3421_data_t;
 
 static max3421_data_t _hcd_data;
-static uint8_t _max_nak = MAX_NAK_DEFAULT; // max NAK before giving up in a usb frame
+
+// max NAK before giving up in a frame. 0 means infinite NAKs
+static uint8_t _max_nak = MAX_NAK_DEFAULT;
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E
@@ -409,10 +412,11 @@ static void free_ep(uint8_t daddr) {
   }
 }
 
-// Check if endpoint has an queued transfer
+// Check if endpoint has an queued transfer and not reach max NAK
 TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) {
   uint8_t const state = ep->state;
-  return ep->packet_size && state >= EP_STATE_ATTEMPT_1 && state < EP_STATE_ATTEMPT_1 + _max_nak;
+  return ep->packet_size && (state >= EP_STATE_ATTEMPT_1) &&
+         (_max_nak == 0 || state < EP_STATE_ATTEMPT_1 + _max_nak);
 }
 
 // Find the next pending endpoint using round-robin scheduling, starting from next endpoint.
@@ -447,10 +451,11 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
 // optional hcd configuration, called by tuh_configure()
 bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   (void) rhport;
-  (void) cfg_id;
-  (void) cfg_param;
+  TU_VERIFY(cfg_id == TUH_CFGID_MAX3421);
 
-  return false;
+  tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
+  _max_nak = cfg->max3421.max_nak;
+  return true;
 }
 
 // Initialize controller to host mode
diff --git a/src/tusb_option.h b/src/tusb_option.h
index f90fb7026..812074c44 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -144,7 +144,6 @@
 #define OPT_MCU_RX72N            1402 ///< Renesas RX72N
 #define OPT_MCU_RAXXX            1403 ///< Renesas RAxxx families
 
-
 // Mind Motion
 #define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327
 
-- 
cgit v1.3.1


From 172c9f70c74c541892006ff2bbfea818f40a235a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Apr 2024 16:55:49 +0700
Subject: clean up

---
 src/portable/analog/max3421/hcd_max3421.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 12d80e0b5..61a7e2703 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -173,8 +173,8 @@ enum {
 
 enum {
   EP_STATE_IDLE        = 0,
-  EP_STATE_COMPLETE,
-  EP_STATE_ATTEMPT_1, // pending 1st attempt
+  EP_STATE_COMPLETE    = 1,
+  EP_STATE_ATTEMPT_1   = 2, // pending 1st attempt
   EP_STATE_ATTEMPT_MAX = 15
 };
 
@@ -465,7 +465,6 @@ bool hcd_init(uint8_t rhport) {
   tuh_max3421_int_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
-  TU_LOG2_INT(sizeof(atomic_flag));
   TU_LOG2_INT(sizeof(max3421_data_t));
   TU_LOG2_INT(offsetof(max3421_data_t, ep));
 
@@ -873,7 +872,9 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) {
 
   if (ep_dir) {
     // IN transfer: fifo data is already received in RCVDAV IRQ
-    if ( hxfr_type & HXFR_HS ) {
+
+    // mark control handshake as complete
+    if (hxfr_type & HXFR_HS) {
       ep->state = EP_STATE_COMPLETE;
     }
 
-- 
cgit v1.3.1


From 8936096846f3b4e0f6d2193b5f8be74a94d003f9 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Tue, 2 Apr 2024 19:56:39 +0700
Subject: max3421 limit max nak

---
 src/portable/analog/max3421/hcd_max3421.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 61a7e2703..9e363506c 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -454,7 +454,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   TU_VERIFY(cfg_id == TUH_CFGID_MAX3421);
 
   tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
-  _max_nak = cfg->max3421.max_nak;
+  _max_nak = tu_max8(cfg->max3421.max_nak, EP_STATE_ATTEMPT_MAX-EP_STATE_ATTEMPT_1);
   return true;
 }
 
-- 
cgit v1.3.1


From 9fb1fb90447fbbfdc3ca33c39cbd75bb807a7907 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Tue, 2 Apr 2024 20:39:06 +0700
Subject: correct max nak

---
 src/portable/analog/max3421/hcd_max3421.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 9e363506c..fa6d45d3e 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -454,7 +454,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   TU_VERIFY(cfg_id == TUH_CFGID_MAX3421);
 
   tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
-  _max_nak = tu_max8(cfg->max3421.max_nak, EP_STATE_ATTEMPT_MAX-EP_STATE_ATTEMPT_1);
+  _max_nak = tu_min8(cfg->max3421.max_nak, EP_STATE_ATTEMPT_MAX-EP_STATE_ATTEMPT_1);
   return true;
 }
 
-- 
cgit v1.3.1


From f8dc3b97beae611c0a68ab50b960dd1922a66f5d Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Tue, 2 Apr 2024 22:47:50 +0700
Subject: check cfg_param pointer

---
 src/portable/analog/max3421/hcd_max3421.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index fa6d45d3e..242c65501 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -451,7 +451,7 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
 // optional hcd configuration, called by tuh_configure()
 bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   (void) rhport;
-  TU_VERIFY(cfg_id == TUH_CFGID_MAX3421);
+  TU_VERIFY(cfg_id == TUH_CFGID_MAX3421 && cfg_param != NULL);
 
   tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
   _max_nak = tu_min8(cfg->max3421.max_nak, EP_STATE_ATTEMPT_MAX-EP_STATE_ATTEMPT_1);
-- 
cgit v1.3.1


From db28437218244ae9a1e16d87964edd51f78f54bd Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 2 Apr 2024 14:17:24 +0200
Subject: Move endpoint alloc define to tusb_mcu.h

---
 src/class/audio/audio_device.c | 19 ++++++-------------
 src/common/tusb_mcu.h          |  4 ++++
 2 files changed, 10 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9a361419b..2af3da324 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -96,13 +96,6 @@
   #define  USE_LINEAR_BUFFER     1
 #endif
 
-// Temporarily put the check here
-#if defined(TUP_USBIP_FSDEV) || defined(TUP_USBIP_DWC2)
-  #define  USE_ISO_EP_ALLOCATION   1
-#else
-  #define  USE_ISO_EP_ALLOCATION   0
-#endif
-
 // Declaration of buffers
 
 // Check for maximum supported numbers
@@ -1476,7 +1469,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 #endif
       }
 
-#if USE_ISO_EP_ALLOCATION
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
       {
   #if CFG_TUD_AUDIO_ENABLE_EP_IN
         uint8_t  ep_in = 0;
@@ -1552,7 +1545,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
         }
   #endif
       }
-#endif // USE_ISO_EP_ALLOCATION
+#endif // TUP_DCD_EDPT_ISO_ALLOC
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
       {
@@ -1674,7 +1667,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   if (audio->ep_in_as_intf_num == itf)
   {
     audio->ep_in_as_intf_num = 0;
-  #if !USE_ISO_EP_ALLOCATION
+  #ifndef TUP_DCD_EDPT_ISO_ALLOC
     usbd_edpt_close(rhport, audio->ep_in);
   #endif
 
@@ -1705,7 +1698,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   if (audio->ep_out_as_intf_num == itf)
   {
     audio->ep_out_as_intf_num = 0;
-  #if !USE_ISO_EP_ALLOCATION
+  #ifndef TUP_DCD_EDPT_ISO_ALLOC
     usbd_edpt_close(rhport, audio->ep_out);
   #endif
 
@@ -1726,7 +1719,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
     // Close corresponding feedback EP
   #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-    #if !USE_ISO_EP_ALLOCATION
+    #ifndef TUP_DCD_EDPT_ISO_ALLOC
     usbd_edpt_close(rhport, audio->ep_fb);
     #endif
     audio->ep_fb = 0;
@@ -1758,7 +1751,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
         if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
         {
           tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-#if USE_ISO_EP_ALLOCATION
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
           TU_ASSERT(usbd_edpt_iso_activate(rhport, desc_ep));
 #else
           TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 308ee713c..1ee20ba07 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -434,4 +434,8 @@
   #define TU_ATTR_FAST_FUNC
 #endif
 
+#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV)
+  #define TUP_DCD_EDPT_ISO_ALLOC
+#endif
+
 #endif
-- 
cgit v1.3.1


From 2e4d4e4a017202e4aef2a8f3027a29da0f47cd32 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 2 Apr 2024 15:29:16 +0200
Subject: Add endpoint ISO allocation to video class.

---
 src/class/video/video_device.c | 47 ++++++++++++++++++++++++++++++++----------
 1 file changed, 36 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 5306356ba..648c8c3c8 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -759,10 +759,15 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
     if (!ofs_ep) break;
-    uint8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
-    usbd_edpt_close(rhport, ep_adr);
-    stm->desc.ep[i] = 0;
-    TU_LOG_DRV("    close EP%02x\r\n", ep_adr);
+    tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)(desc + ofs_ep);
+    /* Only ISO endpoints needs to be closed */
+    if(ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+#ifndef TUP_DCD_EDPT_ISO_ALLOC
+      usbd_edpt_close(rhport, ep->bEndpointAddress);
+#endif
+      stm->desc.ep[i] = 0;
+      TU_LOG_DRV("    close EP%02x\r\n", ep->bEndpointAddress);
+    }
   }
 
   /* clear transfer management information */
@@ -788,16 +793,18 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     TU_ASSERT(cur < end);
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
     uint_fast32_t max_size = stm->max_payload_transfer_size;
-    if (altnum) {
-      if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
-          (tu_edpt_packet_size(ep) < max_size)) {
-        /* FS must be less than or equal to max packet size */
-        return false;
-      }
+    if (altnum && (TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer)) {
+      /* FS must be less than or equal to max packet size */
+      TU_VERIFY (tu_edpt_packet_size(ep) >= max_size);
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+      usbd_edpt_iso_activate(rhport, ep);
+#else
+      TU_ASSERT(usbd_edpt_open(rhport, ep));
+#endif
     } else {
       TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer);
+      TU_ASSERT(usbd_edpt_open(rhport, ep));
     }
-    TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
     TU_LOG_DRV("    open EP%02x\r\n", _desc_ep_addr(cur));
   }
@@ -1283,6 +1290,24 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     cur = _next_desc_itf(cur, end);
     stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
     stm->state = VS_STATE_PROBING;
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+    /* Allocate ISO endpoints */
+    uint16_t ep_size = 0;
+    uint16_t ep_addr = 0;
+    uint8_t const *p_desc = (uint8_t const*)itf_desc + stm->desc.beg;
+    uint8_t const *p_desc_end = (uint8_t const*)itf_desc + stm->desc.end;
+    while (p_desc < p_desc_end) {
+      if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) {
+        tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+        if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+              ep_addr = desc_ep->bEndpointAddress;
+              ep_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_size);
+        }
+      }
+      p_desc = tu_desc_next(p_desc);
+    }
+    if(ep_addr > 0 && ep_size > 0) usbd_edpt_iso_alloc(rhport, ep_addr, ep_size);
+#endif
     if (0 == stm_idx && 1 == bInCollection) {
       /* If there is only one streaming interface and no alternate settings,
        * host may not issue set_interface so open the streaming interface here. */
-- 
cgit v1.3.1


From 11722cc53393dff71a97b45e63309cb98c463b4b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 3 Apr 2024 23:08:15 +0700
Subject: add note for sdk v2 and v3, also add check if allocreq failed

---
 src/portable/sony/cxd56/dcd_cxd56.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index 83cd0718c..41814370e 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -103,19 +103,23 @@ static int _dcd_bind(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev_
   usbdcd_driver.ep[0] = dev->ep0;
 
   #ifdef EP_ALLOCREQ
+  // SDK v2
   usbdcd_driver.req[0] = EP_ALLOCREQ(usbdcd_driver.ep[0]);
-  if (usbdcd_driver.req[0] != NULL)
-  {
+  if (usbdcd_driver.req[0] != NULL) {
     usbdcd_driver.req[0]->len = 64;
     usbdcd_driver.req[0]->buf = EP_ALLOCBUFFER(usbdcd_driver.ep[0], 64);
-    if (!usbdcd_driver.req[0]->buf)
-    {
+    if (!usbdcd_driver.req[0]->buf) {
       EP_FREEREQ(usbdcd_driver.ep[0], usbdcd_driver.req[0]);
       usbdcd_driver.req[0] = NULL;
+      return ENOMEM;
     }
   }
   #else
-  usbdcd_driver.req[0] = usbdev_allocreq(usbdcd_driver.ep[0],64);
+  // SDK v3
+  usbdcd_driver.req[0] = usbdev_allocreq(usbdcd_driver.ep[0], 64);
+  if (usbdcd_driver.req[0] == NULL) {
+    return ENOMEM;
+  }
   #endif
 
   usbdcd_driver.req[0]->callback = usbdcd_ep0incomplete;
@@ -301,17 +305,17 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   usbdcd_driver.req[epnum] = NULL;
 
   #ifdef EP_ALLOCREQ
+  // sdk v2
   usbdcd_driver.req[epnum] = EP_ALLOCREQ(usbdcd_driver.ep[epnum]);
-  if (usbdcd_driver.req[epnum] != NULL)
-  {
+  if (usbdcd_driver.req[epnum] != NULL) {
     usbdcd_driver.req[epnum]->len = ep_mps;
   }
-  else
   #else
+  // sdk v3
   usbdcd_driver.req[epnum] = usbdev_allocreq(usbdcd_driver.ep[epnum], ep_mps);
-  if(usbdcd_driver.req[epnum] == NULL)
   #endif
-  {
+
+  if(usbdcd_driver.req[epnum] == NULL) {
     return false;
   }
 
-- 
cgit v1.3.1


From 7910cc298187327e05c43770b58eac528a4fecfa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Apr 2024 10:55:14 +0700
Subject: fix build with rp2040 + max3421

- forward MAX3421_HOST=1 from makefile to cmake
- add feather_rp2040_max3421 board to run with ci for rp2040 + max3421
---
 examples/build_system/make/make.mk                      |  1 +
 hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake |  4 ++++
 src/portable/analog/max3421/hcd_max3421.c               | 13 ++++++-------
 3 files changed, 11 insertions(+), 7 deletions(-)
 create mode 100644 hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake

(limited to 'src')

diff --git a/examples/build_system/make/make.mk b/examples/build_system/make/make.mk
index e1113aa52..772befca4 100644
--- a/examples/build_system/make/make.mk
+++ b/examples/build_system/make/make.mk
@@ -113,6 +113,7 @@ CFLAGS += -DBOARD_$(BOARD_UPPER)
 ifeq (${MAX3421_HOST},1)
   SRC_C += src/portable/analog/max3421/hcd_max3421.c
   CFLAGS += -DCFG_TUH_MAX3421=1
+  CMAKE_DEFSYM +=	-DMAX3421_HOST=1
 endif
 
 # Log level is mapped to TUSB DEBUG option
diff --git a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake
new file mode 100644
index 000000000..b8e5890f3
--- /dev/null
+++ b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake
@@ -0,0 +1,4 @@
+set(PICO_BOARD adafruit_feather_rp2040)
+
+# Enable MAX3421E USB Host
+set(MAX3421_HOST 1)
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 242c65501..76c1a150b 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -676,19 +676,18 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
   TU_VERIFY(ep);
 
-  // control transfer can switch direction
-  ep->hxfr_bm.is_out = ep_dir ? 0u : 1u;
+  if (ep_num == 0) {
+    // control transfer can switch direction
+    ep->hxfr_bm.is_out = ep_dir ? 0 : 1;
+    ep->hxfr_bm.is_setup = 0;
+    ep->data_toggle = 1;
+  }
 
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
   ep->state = EP_STATE_ATTEMPT_1;
 
-  if (ep_num == 0) {
-    ep->hxfr_bm.is_setup = 0;
-    ep->data_toggle = 1;
-  }
-
   // carry out transfer if not busy
   if (!atomic_flag_test_and_set(&_hcd_data.busy)) {
     xact_generic(rhport, ep, true, false);
-- 
cgit v1.3.1


From 93fb3b00debc613f631cb6ec848bfcb9231a325c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Apr 2024 12:51:07 +0700
Subject: fix build with gcc 11

---
 src/portable/analog/max3421/hcd_max3421.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 76c1a150b..059f674cd 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -654,7 +654,7 @@ static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool
 
     // status
     if (ep->buf == NULL || ep->total_len == 0) {
-      uint8_t const hxfr = HXFR_HS | (ep->hxfr_bm.is_out ? HXFR_OUT_NIN : 0);
+      uint8_t const hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN));
       peraddr_write(rhport, ep->daddr, in_isr);
       hxfr_write(rhport, hxfr, in_isr);
       return;
-- 
cgit v1.3.1


From 802ad885ab041ecf855c1c08d97dfc45359fd1b0 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Thu, 4 Apr 2024 17:15:38 +0700
Subject: minor update

---
 src/device/usbd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 28eb9aa6e..72fde1b97 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1233,7 +1233,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   TU_LOG_USBD("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
 #if CFG_TUD_LOG_LEVEL >= 3
-  if(tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
+  if(dir == TUSB_DIR_IN) {
     TU_LOG_MEM(CFG_TUD_LOG_LEVEL, buffer, total_bytes, 2);
   }
 #endif
-- 
cgit v1.3.1


From caf2c5e0b75b72c0b0357ca364a76d70b5846bde Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Apr 2024 17:04:33 +0700
Subject: reverted un-related file changes

---
 examples/device/cdc_msc_freertos/src/main.c        | 51 ++++++++++++----------
 hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk |  3 --
 hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk   |  3 --
 hw/bsp/nrf/boards/pca10095/board.h                 |  4 +-
 hw/bsp/nrf/boards/pca10095/board.mk                |  3 ++
 hw/bsp/nrf/family.c                                |  1 +
 src/class/msc/msc_device.c                         |  2 +-
 src/class/video/video.h                            |  6 ++-
 src/common/tusb_debug.h                            |  3 +-
 src/common/tusb_fifo.c                             |  1 +
 src/host/usbh_pvt.h                                |  6 ++-
 src/portable/nordic/nrf5x/dcd_nrf5x.c              |  8 +++-
 src/portable/ohci/ohci.h                           |  2 +-
 13 files changed, 54 insertions(+), 39 deletions(-)

(limited to 'src')

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 1dadc4513..e94e8eaec 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -52,7 +52,8 @@
   #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
-#define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
+#define CDC_STACK_SIZE      configMINIMAL_STACK_SIZE
+#define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPES
@@ -69,21 +70,22 @@ enum {
   BLINK_SUSPENDED = 2500,
 };
 
-// static timer & task
+// static task
 #if configSUPPORT_STATIC_ALLOCATION
-StaticTimer_t blinky_tmdef;
+StackType_t blinky_stack[BLINKY_STACK_SIZE];
+StaticTask_t blinky_taskdef;
 
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
-StackType_t  cdc_stack[CDC_STACK_SZIE];
+StackType_t  cdc_stack[CDC_STACK_SIZE];
 StaticTask_t cdc_taskdef;
 #endif
 
-TimerHandle_t blinky_tm;
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-static void led_blinky_cb(TimerHandle_t xTimer);
 static void usb_device_task(void *param);
+void led_blinking_task(void* param);
 void cdc_task(void *params);
 
 //--------------------------------------------------------------------+
@@ -94,22 +96,20 @@ int main(void) {
   board_init();
 
 #if configSUPPORT_STATIC_ALLOCATION
-  // soft timer for blinky
-  blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
+  // blinky task
+  xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef);
 
   // Create a task for tinyusb device stack
   xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
 
   // Create CDC task
-  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef);
 #else
-  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL);
   xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
   xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
 #endif
 
-  xTimerStart(blinky_tm, 0);
-
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
@@ -154,12 +154,12 @@ static void usb_device_task(void *param) {
 
 // Invoked when device is mounted
 void tud_mount_cb(void) {
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
 void tud_umount_cb(void) {
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+  blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
@@ -167,16 +167,12 @@ void tud_umount_cb(void) {
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
 void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
+  blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
 void tud_resume_cb(void) {
-  if (tud_mounted()) {
-    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
-  } else {
-    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
-  }
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
@@ -235,10 +231,17 @@ void tud_cdc_rx_cb(uint8_t itf) {
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-static void led_blinky_cb(TimerHandle_t xTimer) {
-  (void) xTimer;
+void led_blinking_task(void* param) {
+  (void) param;
+  static uint32_t start_ms = 0;
   static bool led_state = false;
 
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+  while (1) {
+    // Blink every interval ms
+    vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
+    start_ms += blink_interval_ms;
+
+    board_led_write(led_state);
+    led_state = 1 - led_state; // toggle
+  }
 }
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
index f69700139..c4dc65b63 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
@@ -8,9 +8,6 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
 
-SRC_C += \
-	$(MCU_DIR)/project_template/clock_config.c \
-
 # For flash-jlink target
 JLINK_DEVICE = K32L2A41xxxxA
 
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
index 82456b721..9cf36c500 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
@@ -8,9 +8,6 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
 
-SRC_C += \
-	$(MCU_DIR)/project_template/clock_config.c \
-
 # For flash-jlink target
 JLINK_DEVICE = K32L2B31xxxxA
 
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
index 2a46e5422..846c2ee5b 100644
--- a/hw/bsp/nrf/boards/pca10095/board.h
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -42,8 +42,8 @@
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
-#define UART_RX_PIN           32
-#define UART_TX_PIN           33
+#define UART_RX_PIN           22
+#define UART_TX_PIN           20
 
 // SPI for USB host shield
 // Pin is correct but not working probably due to signal incompatible (1.8V 3v3) with MAC3421E !?
diff --git a/hw/bsp/nrf/boards/pca10095/board.mk b/hw/bsp/nrf/boards/pca10095/board.mk
index 9c4edbafc..20580d619 100644
--- a/hw/bsp/nrf/boards/pca10095/board.mk
+++ b/hw/bsp/nrf/boards/pca10095/board.mk
@@ -2,6 +2,9 @@ CPU_CORE = cortex-m33
 MCU_VARIANT = nrf5340_application
 CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
 
+# enable max3421 host driver for this board
+MAX3421_HOST = 1
+
 LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf5340_xxaa_application.ld
 
 SRC_C += hw/mcu/nordic/nrfx/drivers/src/nrfx_usbreg.c
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index d6bb2d868..71c651f5f 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -76,6 +76,7 @@ enum {
   #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
   #define VBUSDETECT_Msk USBREG_USBREGSTATUS_VBUSDETECT_Msk
   #define OUTPUTRDY_Msk USBREG_USBREGSTATUS_OUTPUTRDY_Msk
+  #define GPIOTE_IRQn GPIOTE1_IRQn
 #else
   #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_RC
   #define VBUSDETECT_Msk POWER_USBREGSTATUS_VBUSDETECT_Msk
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 2589dcd2c..c145d86a6 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -203,7 +203,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL
 
 TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
 {
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 3b511af96..b8a9b6369 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -369,6 +369,8 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bCopyProtect;
 } tusb_desc_video_format_uncompressed_t;
 
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_uncompressed_t) == 27, "size is not correct");
+
 // Uncompressed payload specs: 3.1.2 frame descriptor
 #define tusb_desc_video_frame_uncompressed_nint_t(_nint) \
   struct TU_ATTR_PACKED { \
@@ -382,7 +384,7 @@ typedef struct TU_ATTR_PACKED {
     uint32_t dwMinBitRate; \
     uint32_t dwMaxBitRate; \
     uint32_t dwMaxVideoFrameBufferSize; /* deprecated in 1.5 */ \
-    uint32_t dwDefaultFrameInterval; \
+    uint32_t dwDefaultFrameInterval; /* 100ns unit */\
     uint8_t  bFrameIntervalType; \
     uint32_t dwFrameInterval[_nint]; \
   }
@@ -414,6 +416,8 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bCopyProtect;
 } tusb_desc_video_format_mjpeg_t;
 
+TU_VERIFY_STATIC(sizeof(tusb_desc_video_format_mjpeg_t) == 11, "size is not correct");
+
 // MJPEG payload specs: 3.1.2 frame descriptor (same as uncompressed)
 typedef tusb_desc_video_frame_uncompressed_t tusb_desc_video_frame_mjpeg_t;
 typedef tusb_desc_video_frame_uncompressed_1int_t tusb_desc_video_frame_mjpeg_1int_t;
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 0f4dc93f3..2e9f1d9cd 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -60,6 +60,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
 
 static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
   for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
+  tu_printf("\r\n");
 }
 
 // Log with Level
@@ -76,7 +77,7 @@ static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_BUF(_x, _n)   tu_print_buf((uint8_t const*)(_x), _n)
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = 0x%lX\r\n", (unsigned long) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index d6c3db4ce..76696396b 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -224,6 +224,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
       }
       break;
+    default: break;
   }
 }
 
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 46d13a907..95de915e9 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -35,7 +35,11 @@
  extern "C" {
 #endif
 
-#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_USBH(...)      TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_MEM_USBH(...)  TU_LOG_MEM(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_BUF_USBH(...)  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_INT_USBH(...)  TU_LOG_INT(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+#define TU_LOG_HEX_USBH(...)  TU_LOG_HEX(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
 
 enum {
   USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index cf9e5923b..80a285ef0 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -653,7 +653,11 @@ void dcd_int_handler(uint8_t rhport)
     if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
     {
       iso_enabled = true;
-      xact_out_dma(EP_ISO_NUM);
+      // Transfer from endpoint to RAM only if data is not corrupted
+      if ((int_status & USBD_INTEN_USBEVENT_Msk) == 0 ||
+          (NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_ISOOUTCRC_Msk) == 0) {
+        xact_out_dma(EP_ISO_NUM);
+      }
     }
 
     // ISOIN: Notify client that data was transferred
@@ -683,7 +687,7 @@ void dcd_int_handler(uint8_t rhport)
   {
     TU_LOG(3, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
 
-    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk };
+    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk };
     uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
     NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt
 
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 4feefd771..94bad5df7 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -83,7 +83,7 @@ typedef struct TU_ATTR_ALIGNED(16)
   volatile uint32_t condition_code : 4;
 
 	// Word 1
-	volatile uint8_t* current_buffer_pointer;
+	uint8_t* volatile current_buffer_pointer;
 
 	// Word 2 : next TD
 	volatile uint32_t next;
-- 
cgit v1.3.1


From 5ce458588498090204cdc7c3977c0fd48e00d710 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Apr 2024 17:14:51 +0700
Subject: fix pre-commit format

---
 examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk | 2 +-
 hw/bsp/mcx/boards/frdmmcxa153/board.mk                  | 2 +-
 hw/bsp/mcx/boards/frdmmcxa153/clock_config.h            | 2 +-
 hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c                 | 2 +-
 hw/bsp/mcx/family.c                                     | 2 +-
 hw/bsp/mcx/family.cmake                                 | 6 +++---
 hw/bsp/mcx/family.mk                                    | 4 ++--
 src/portable/chipidea/ci_fs/ci_fs_mcx.h                 | 2 +-
 8 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk b/examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk
index f74f46d54..c65f24376 100644
--- a/examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk
+++ b/examples/build_system/make/cpu/cortex-m33-nodsp-nofp.mk
@@ -13,4 +13,4 @@ else ifeq ($(TOOLCHAIN),iar)
 
 endif
 
-FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
\ No newline at end of file
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/board.mk b/hw/bsp/mcx/boards/frdmmcxa153/board.mk
index a70a7dcef..cf6d9c0eb 100644
--- a/hw/bsp/mcx/boards/frdmmcxa153/board.mk
+++ b/hw/bsp/mcx/boards/frdmmcxa153/board.mk
@@ -6,7 +6,7 @@ CPU_CORE ?= cortex-m33-nodsp-nofp
 CFLAGS += \
 	-DCPU_MCXA153VLH \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
- 
+
 JLINK_DEVICE = MCXA153
 PYOCD_TARGET = MCXA153
 
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/clock_config.h b/hw/bsp/mcx/boards/frdmmcxa153/clock_config.h
index 079d0d312..aae811052 100644
--- a/hw/bsp/mcx/boards/frdmmcxa153/clock_config.h
+++ b/hw/bsp/mcx/boards/frdmmcxa153/clock_config.h
@@ -4,7 +4,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
- 
+
 /***********************************************************************************************************************
  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
diff --git a/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c
index b0e6de560..cc8f56e63 100644
--- a/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c
+++ b/hw/bsp/mcx/boards/frdmmcxa153/pin_mux.c
@@ -4,7 +4,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
- 
+
 /***********************************************************************************************************************
  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 74b84773d..96ae2fde3 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -151,7 +151,7 @@ void board_init(void)
   CLOCK_EnableClock(kCLOCK_Usb0Ram);
   CLOCK_EnableClock(kCLOCK_Usb0Fs);
   CLOCK_EnableUsbfsClock();
-  
+
 #endif
 
 #if PORT_SUPPORT_DEVICE(1) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 078d13b9f..78490ec57 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -27,13 +27,13 @@ function(add_board_target BOARD_TARGET)
       ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
       ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
       ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
-      
+
       # mcu
       ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
       ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
       ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
       )
-    
+
       if (${FAMILY_MCUS} STREQUAL "MCXN9")
         target_sources(${BOARD_TARGET} PRIVATE
           ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
@@ -105,7 +105,7 @@ function(family_configure_example TARGET RTOS)
   elseif(${FAMILY_MCUS} STREQUAL "MCXA15")
     family_add_tinyusb(${TARGET} OPT_MCU_MCXA15 ${RTOS})
   endif()
-  
+
   target_sources(${TARGET}-tinyusb PUBLIC
     # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
     ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 59170271c..3ee0efaf6 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -38,7 +38,7 @@ SRC_C += \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
-	
+
 
 # fsl_lpflexcomm just needed for MCXN9
 ifeq ($(MCU_VARIANT), MCXN947)
@@ -54,7 +54,7 @@ ifeq ($(MCU_VARIANT), MCXA153)
 
 endif
 
-	
+
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcx.h b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
index bf88df0f4..3f2b13323 100644
--- a/src/portable/chipidea/ci_fs/ci_fs_mcx.h
+++ b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
@@ -36,7 +36,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_MCXA15
 	#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
 	#define USB0_IRQN 				USB0_IRQn
-	
+
 #else
   #error "MCU is not supported"
 #endif
-- 
cgit v1.3.1


From c97c3418c741a26666942e184ca514f5dbdafcfa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Apr 2024 20:31:55 +0700
Subject: minor update bsp

---
 examples/build_system/cmake/cpu/cortex-m23.cmake   |  4 +-
 .../cmake/cpu/cortex-m33-nodsp-nofp.cmake          |  2 +-
 examples/build_system/cmake/cpu/cortex-m33.cmake   |  2 +-
 hw/bsp/mcx/boards/frdm_mcxa153/board.cmake         |  3 -
 hw/bsp/mcx/boards/frdm_mcxa153/board.h             | 20 +++--
 hw/bsp/mcx/boards/frdm_mcxa153/board.mk            |  2 +-
 hw/bsp/mcx/boards/frdm_mcxn947/board.cmake         |  3 -
 hw/bsp/mcx/boards/frdm_mcxn947/board.mk            |  2 +-
 hw/bsp/mcx/boards/mcxn947brk/board.cmake           |  3 -
 hw/bsp/mcx/boards/mcxn947brk/board.mk              |  2 +-
 hw/bsp/mcx/family.c                                | 92 ++++++++++------------
 hw/bsp/mcx/family.cmake                            | 10 +++
 hw/bsp/mcx/family.mk                               | 15 +---
 src/portable/chipidea/ci_fs/ci_fs_mcx.h            | 20 +++--
 src/portable/chipidea/ci_fs/dcd_ci_fs.c            |  2 +-
 15 files changed, 81 insertions(+), 101 deletions(-)

(limited to 'src')

diff --git a/examples/build_system/cmake/cpu/cortex-m23.cmake b/examples/build_system/cmake/cpu/cortex-m23.cmake
index 3093dc99a..c7ce1d242 100644
--- a/examples/build_system/cmake/cpu/cortex-m23.cmake
+++ b/examples/build_system/cmake/cpu/cortex-m23.cmake
@@ -5,13 +5,13 @@ if (TOOLCHAIN STREQUAL "gcc")
     -mfloat-abi=soft
     )
 
-  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+  set(FREERTOS_PORT GCC_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
 
 elseif (TOOLCHAIN STREQUAL "iar")
   set(TOOLCHAIN_COMMON_FLAGS
     --cpu cortex-m23
     )
 
-  set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "")
+  set(FREERTOS_PORT IAR_ARM_CM23_NTZ_NONSECURE CACHE INTERNAL "")
 
 endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake b/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
index 7946affbe..01e6b979a 100644
--- a/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
+++ b/examples/build_system/cmake/cpu/cortex-m33-nodsp-nofp.cmake
@@ -12,6 +12,6 @@ elseif (TOOLCHAIN STREQUAL "iar")
     --cpu cortex-m33+nodsp
     )
 
-  set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+  set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
 
 endif ()
diff --git a/examples/build_system/cmake/cpu/cortex-m33.cmake b/examples/build_system/cmake/cpu/cortex-m33.cmake
index 7ebaf1748..94c29099d 100644
--- a/examples/build_system/cmake/cpu/cortex-m33.cmake
+++ b/examples/build_system/cmake/cpu/cortex-m33.cmake
@@ -14,6 +14,6 @@ elseif (TOOLCHAIN STREQUAL "iar")
     --fpu VFPv5-SP
     )
 
-  set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+  set(FREERTOS_PORT IAR_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
 
 endif ()
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
index acde3f46f..6a9a20e21 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT MCXA153)
 set(MCU_CORE MCXA153)
 
-set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
-
 set(JLINK_DEVICE MCXA153_M33)
 set(PYOCD_TARGET MCXA153)
 set(NXPLINK_DEVICE MCXA153:MCXA153)
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
index 02a452da5..e207d89d9 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.h
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h
@@ -28,7 +28,7 @@
 #define BOARD_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 // LED
@@ -38,29 +38,27 @@
 #define LED_STATE_ON          0
 
 // ISP button (Dummy, use unused pin
- #define BUTTON_GPIO           GPIO3
- #define BUTTON_CLK            kCLOCK_GateGPIO3
- #define BUTTON_PIN            29 //sw2
- #define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO           GPIO3
+#define BUTTON_CLK            kCLOCK_GateGPIO3
+#define BUTTON_PIN            29 //sw2
+#define BUTTON_STATE_ACTIVE   0
 
 // UART
 #define UART_DEV              LPUART0
 
 static inline void board_uart_init_clock(void) {
-
   /* attach 12 MHz clock to LPUART0 (debug console) */
-    CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
-    CLOCK_AttachClk(kFRO12M_to_LPUART0);
+  CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+  CLOCK_AttachClk(kFRO12M_to_LPUART0);
 
-    RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
 }
 
-
 // XTAL
 #define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif
diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
index cf6d9c0eb..af8416d8e 100644
--- a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
+++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk
@@ -2,7 +2,7 @@ MCU_VARIANT = MCXA153
 MCU_CORE = MCXA153
 PORT = 0
 
-CPU_CORE ?= cortex-m33-nodsp-nofp
+CPU_CORE = cortex-m33-nodsp-nofp
 CFLAGS += \
 	-DCPU_MCXA153VLH \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXA15 \
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
index a08d248f5..8c3280743 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT MCXN947)
 set(MCU_CORE MCXN947_cm33_core0)
 
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
-
 set(JLINK_DEVICE MCXN947_M33_0)
 set(PYOCD_TARGET MCXN947)
 set(NXPLINK_DEVICE MCXN947:MCXN947)
diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
index d90780996..22fefd79b 100644
--- a/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
+++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.mk
@@ -2,7 +2,7 @@ MCU_VARIANT = MCXN947
 MCU_CORE = MCXN947_cm33_core0
 PORT ?= 1
 
-CPU_CORE ?= cortex-m33
+CPU_CORE = cortex-m33
 CFLAGS += \
 	-DCPU_MCXN947VDF_cm33_core0 \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
index a08d248f5..8c3280743 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -1,9 +1,6 @@
 set(MCU_VARIANT MCXN947)
 set(MCU_CORE MCXN947_cm33_core0)
 
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
-
 set(JLINK_DEVICE MCXN947_M33_0)
 set(PYOCD_TARGET MCXN947)
 set(NXPLINK_DEVICE MCXN947:MCXN947)
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
index d90780996..22fefd79b 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.mk
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -2,7 +2,7 @@ MCU_VARIANT = MCXN947
 MCU_CORE = MCXN947_cm33_core0
 PORT ?= 1
 
-CPU_CORE ?= cortex-m33
+CPU_CORE = cortex-m33
 CFLAGS += \
 	-DCPU_MCXN947VDF_cm33_core0 \
 	-DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 96ae2fde3..cc675a49d 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -33,6 +33,10 @@
 #include "pin_mux.h"
 #include "clock_config.h"
 
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
 #ifdef BOARD_TUD_RHPORT
   #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
 #else
@@ -45,54 +49,50 @@
   #define PORT_SUPPORT_HOST(_n)    0
 #endif
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
 
 #if CFG_TUSB_MCU == OPT_MCU_MCXN9
-void USB0_FS_IRQHandler(void)
-{
+void USB0_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB1_HS_IRQHandler(void)
-{
+void USB1_HS_IRQHandler(void) {
   tud_int_handler(1);
 }
 
 #elif CFG_TUSB_MCU == OPT_MCU_MCXA15
-void USB0_IRQHandler(void)
-{
+
+void USB0_IRQHandler(void) {
   tud_int_handler(0);
 }
+
 #endif
 
 
-void board_init(void)
-{
+void board_init(void) {
   BOARD_InitPins();
   BOARD_InitBootClocks();
   CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
 
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  #if CFG_TUSB_MCU == OPT_MCU_MCXN9
+  NVIC_SetPriority(USB0_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #else
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
 #endif
 
   // LED
   CLOCK_EnableClock(LED_CLK);
-  gpio_pin_config_t led_config = {
-      kGPIO_DigitalOutput,
-      0,
-  };
-  GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
+  gpio_pin_config_t led_config = {kGPIO_DigitalOutput, 0};
+  GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
   board_led_write(0);
 
 #ifdef NEOPIXEL_PIN
@@ -110,7 +110,7 @@ void board_init(void)
   // Button
 #ifdef BUTTON_GPIO
   CLOCK_EnableClock(BUTTON_CLK);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
   GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
 #endif
 
@@ -125,33 +125,26 @@ void board_init(void)
   lpuart_config_t uart_config;
   LPUART_GetDefaultConfig(&uart_config);
   uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
   LPUART_Init(UART_DEV, &uart_config, 12000000u);
 #endif
 
   // USB VBUS
   /* PORT0 PIN22 configured as USB0_VBUS */
 
-
-  /* MCXA15 USB configurations */
-#if PORT_SUPPORT_DEVICE(0) && (CFG_TUSB_MCU == OPT_MCU_MCXA15)
-
-  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
-  CLOCK_EnableUsbfsClock();
-
-#endif
-
-
-  /* MCXN9 USB configurations */
-#if PORT_SUPPORT_DEVICE(0) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
+#if PORT_SUPPORT_DEVICE(0)
   // Port0 is Full Speed
 
+  #if CFG_TUSB_MCU == OPT_MCU_MCXA15
+  RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
+  #elif CFG_TUSB_MCU == OPT_MCU_MCXN9
   CLOCK_AttachClk(kCLK_48M_to_USB0);
   CLOCK_EnableClock(kCLOCK_Usb0Ram);
   CLOCK_EnableClock(kCLOCK_Usb0Fs);
-  CLOCK_EnableUsbfsClock();
+  #endif
 
+  CLOCK_EnableUsbfsClock();
 #endif
 
 #if PORT_SUPPORT_DEVICE(1) && (CFG_TUSB_MCU == OPT_MCU_MCXN9)
@@ -213,9 +206,8 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 
 #ifdef NEOPIXEL_PIN
   if (state) {
@@ -229,23 +221,21 @@ void board_led_write(bool state)
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
 #ifdef BUTTON_GPIO
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
 #endif
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const* buf, int len) {
 #ifdef UART_DEV
-  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+  LPUART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
   return len;
 #else
   (void) buf; (void) len;
@@ -255,13 +245,13 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 78490ec57..c8591b569 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -11,6 +11,16 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 # toolchain set up
+if (MCU_VARIANT STREQUAL "MCXA153")
+  set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor")
+  set(FAMILY_MCUS MCXA15 CACHE INTERNAL "")
+elseif (MCU_VARIANT STREQUAL "MCXN947")
+  set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+  set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
+else()
+  message(FATAL_ERROR "MCU_VARIANT not supported")
+endif()
+
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 #------------------------------------
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 3ee0efaf6..58149fb8d 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -39,23 +39,16 @@ SRC_C += \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
 
-
-# fsl_lpflexcomm just needed for MCXN9
+# fsl_lpflexcomm for MCXN9
 ifeq ($(MCU_VARIANT), MCXN947)
-	SRC_C += \
-		$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
-
+	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c
 endif
 
-# fsl_spc just needed for MCXNA15
+# fsl_spc for MCXNA15
 ifeq ($(MCU_VARIANT), MCXA153)
-	SRC_C += \
-		$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c  \
-
+	SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c
 endif
 
-
-
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcx.h b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
index 3f2b13323..4b93a03a7 100644
--- a/src/portable/chipidea/ci_fs/ci_fs_mcx.h
+++ b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
@@ -30,29 +30,27 @@
 #include "fsl_device_registers.h"
 
 #if CFG_TUSB_MCU == OPT_MCU_MCXN9
-	#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USBFS0_BASE)
-	#define USB0_IRQN 				USB0_FS_IRQn
+  #define CI_FS_REG(_port)  ((ci_fs_regs_t*) USBFS0_BASE)
+  #define CIFS_IRQN 				USB0_FS_IRQn
 
 #elif CFG_TUSB_MCU == OPT_MCU_MCXA15
-	#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
-	#define USB0_IRQN 				USB0_IRQn
+  #define CI_FS_REG(_port)  ((ci_fs_regs_t*) USB0_BASE)
+  #define CIFS_IRQN         USB0_IRQn
 
 #else
   #error "MCU is not supported"
 #endif
 
-#define CI_REG                  CI_FS_REG(0)
+#define CI_REG              CI_FS_REG(0)
 
-void dcd_int_enable(uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   (void) rhport;
-  NVIC_EnableIRQ(USB0_IRQN);
+  NVIC_EnableIRQ(CIFS_IRQN);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   (void) rhport;
-  NVIC_DisableIRQ(USB0_IRQN);
+  NVIC_DisableIRQ(CIFS_IRQN);
 }
 
 #endif
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index a68ecf8c9..02f813ab5 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -295,7 +295,7 @@ void dcd_init(uint8_t rhport)
   CI_REG->INT_EN = USB_INTEN_USBRSTEN_MASK;
 
   dcd_connect(rhport);
-  // NVIC_ClearPendingIRQ(USB0_IRQn);
+  // NVIC_ClearPendingIRQ(CIFS_IRQN);
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-- 
cgit v1.3.1


From e160366a1e3fc26242daf0e31c0d0fafcc51b83c Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 5 Apr 2024 19:12:28 +0200
Subject: dwc2: remove fifo free code.

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 43 -----------------------------------
 1 file changed, 43 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index cf8f3be50..8b13b0753 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -97,7 +97,6 @@ static uint16_t ep0_pending[2];               // Index determines direction as t
 
 // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
 static uint16_t _allocated_fifo_words_tx;     // TX FIFO size in words (IN EPs)
-static bool _out_ep_closed;                   // Flag to check if RX FIFO size needs an update (reduce its size)
 
 // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
 static bool _sof_en;
@@ -113,20 +112,6 @@ static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
   return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
 }
 
-static void update_grxfsiz(uint8_t rhport) {
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-
-  // Determine largest EP size for RX FIFO
-  uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
-    max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
-  }
-
-  // Update size of RX FIFO
-  dwc2->grxfsiz = calc_grxfsiz(max_epsize, ep_count);
-}
-
 static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
@@ -268,7 +253,6 @@ static void bus_reset(uint8_t rhport) {
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   tu_memclr(xfer_status, sizeof(xfer_status));
-  _out_ep_closed = false;
 
   _sof_en = false;
 
@@ -791,26 +775,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
 }
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir = tu_edpt_dir(ep_addr);
-
   edpt_disable(rhport, ep_addr, false);
-
-  // Update max_size
-  xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
-
-  if (dir == TUSB_DIR_IN) {
-    uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
-
-    // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx,);
-    _allocated_fifo_words_tx -= fifo_size;
-  } else {
-    _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
-  }
 }
 
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
@@ -1181,14 +1146,6 @@ void dcd_int_handler(uint8_t rhport) {
       handle_rxflvl_irq(rhport);
     } while (dwc2->gotgint & GINTSTS_RXFLVL);
 
-    // Manage RX FIFO size
-    if (_out_ep_closed) {
-      update_grxfsiz(rhport);
-
-      // Disable flag
-      _out_ep_closed = false;
-    }
-
     dwc2->gintmsk |= GINTMSK_RXFLVLM;
   }
 
-- 
cgit v1.3.1


From e642066562f96e7e4790b709635d32d4c8450861 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 6 Apr 2024 19:02:50 +0200
Subject: Move TUP_DCD_EDPT_ISO_ALLOC outside usbd_edpt_close() loop.

---
 src/class/video/video_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 648c8c3c8..891ece721 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -755,6 +755,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   TU_LOG_DRV("    reopen VS %d\r\n", altnum);
   uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
+#ifndef TUP_DCD_EDPT_ISO_ALLOC
   /* Close endpoints of previous settings. */
   for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
@@ -762,13 +763,12 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)(desc + ofs_ep);
     /* Only ISO endpoints needs to be closed */
     if(ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
-#ifndef TUP_DCD_EDPT_ISO_ALLOC
       usbd_edpt_close(rhport, ep->bEndpointAddress);
-#endif
       stm->desc.ep[i] = 0;
       TU_LOG_DRV("    close EP%02x\r\n", ep->bEndpointAddress);
     }
   }
+#endif
 
   /* clear transfer management information */
   stm->buffer  = NULL;
-- 
cgit v1.3.1


From cbbfbbb57ea8b4ea97ce4f2e2d157da9c25019fe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Apr 2024 13:16:08 +0700
Subject: add cpuctl and pinctl to tuh_configure() option for max3421

---
 .github/workflows/build_iar.yml           |  1 +
 src/host/usbh.h                           | 10 +++++++---
 src/portable/analog/max3421/hcd_max3421.c | 18 +++++++++++-------
 3 files changed, 19 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index a0a022ecc..499349904 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -28,6 +28,7 @@ concurrency:
 
 jobs:
   cmake:
+    if: github.repository_owner == 'hathach'
     runs-on: [self-hosted, Linux, X64, hifiphile]
     strategy:
       fail-fast: false
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 57362c778..359684169 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -80,12 +80,16 @@ enum {
   TUH_CFGID_MAX3421 = 200,
 };
 
+typedef struct {
+  uint8_t max_nak; // max NAK per endpoint per frame
+  uint8_t cpuctl; // R16: CPU Control Register
+  uint8_t pinctl; // R17: Pin Control Register. FDUPSPI bit is ignored
+} tuh_configure_max3421_t;
+
 typedef union {
   // For TUH_CFGID_RPI_PIO_USB_CONFIGURATION use pio_usb_configuration_t
 
-  struct {
-    uint8_t max_nak;
-  } max3421;
+  tuh_configure_max3421_t max3421;
 } tuh_configure_param_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 059f674cd..39afb7505 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -233,7 +233,11 @@ typedef struct {
 static max3421_data_t _hcd_data;
 
 // max NAK before giving up in a frame. 0 means infinite NAKs
-static uint8_t _max_nak = MAX_NAK_DEFAULT;
+static tuh_configure_max3421_t _tuh_cfg = {
+    .max_nak = MAX_NAK_DEFAULT,
+    .cpuctl = 0, // default: INT pulse width = 10.6 us
+    .pinctl = 0, // default: negative edge interrupt
+};
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E
@@ -416,7 +420,7 @@ static void free_ep(uint8_t daddr) {
 TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) {
   uint8_t const state = ep->state;
   return ep->packet_size && (state >= EP_STATE_ATTEMPT_1) &&
-         (_max_nak == 0 || state < EP_STATE_ATTEMPT_1 + _max_nak);
+         (_tuh_cfg.max_nak == 0 || state < EP_STATE_ATTEMPT_1 + _tuh_cfg.max_nak);
 }
 
 // Find the next pending endpoint using round-robin scheduling, starting from next endpoint.
@@ -454,7 +458,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   TU_VERIFY(cfg_id == TUH_CFGID_MAX3421 && cfg_param != NULL);
 
   tuh_configure_param_t const* cfg = (tuh_configure_param_t const*) cfg_param;
-  _max_nak = tu_min8(cfg->max3421.max_nak, EP_STATE_ATTEMPT_MAX-EP_STATE_ATTEMPT_1);
+  _tuh_cfg = cfg->max3421;
   return true;
 }
 
@@ -476,7 +480,7 @@ bool hcd_init(uint8_t rhport) {
 #endif
 
   // full duplex, interrupt negative edge
-  reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
+  reg_write(rhport, PINCTL_ADDR, _tuh_cfg.pinctl | PINCTL_FDUPSPI, false);
 
   // v1 is 0x01, v2 is 0x12, v3 is 0x13
   uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
@@ -505,7 +509,7 @@ bool hcd_init(uint8_t rhport) {
   tuh_max3421_int_api(rhport, true);
 
   // Enable Interrupt pin
-  reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
+  reg_write(rhport, CPUCTL_ADDR, _tuh_cfg.cpuctl | CPUCTL_IE, false);
 
   return true;
 }
@@ -516,9 +520,9 @@ bool hcd_deinit(uint8_t rhport) {
   // disable interrupt
   tuh_max3421_int_api(rhport, false);
 
-  // reset max3421
+  // reset max3421 and power down
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
-  reg_write(rhport, USBCTL_ADDR, 0, false);
+  reg_write(rhport, USBCTL_ADDR, USBCTL_PWRDOWN, false);
 
   #if OSAL_MUTEX_REQUIRED
   osal_mutex_delete(_hcd_data.spi_mutex);
-- 
cgit v1.3.1


From 47c12a07f2edf927eaa685ee8c32b222271d770f Mon Sep 17 00:00:00 2001
From: "Felix \"xq\" Queißner" <xq@random-projects.net>
Date: Mon, 2 Jan 2023 17:09:45 +0100
Subject: Implements tuh_deinit() and tud_deinit() to uninitialize host/device
 mode.

---
 src/device/dcd.h                             |  3 +++
 src/device/usbd.h                            |  5 ++++-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 12 ++++++++++++
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  8 ++++++++
 4 files changed, 27 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 69c26bcf4..21f404e4f 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -122,6 +122,9 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
 // Initialize controller to device mode
 void dcd_init(uint8_t rhport);
 
+// Deinitialize controller, unset device mode.
+void dcd_deinit(uint8_t rhport);
+
 // Interrupt Handler
 void dcd_int_handler(uint8_t rhport);
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 2e3987b99..a9350192b 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -37,9 +37,12 @@ extern "C" {
 // Application API
 //--------------------------------------------------------------------+
 
-// Init device stack
+// Init device stack on roothub port
 bool tud_init (uint8_t rhport);
 
+// Deinit device stack on roothub port
+void tud_deinit(uint8_t rhport);
+
 // Check if device stack is already initialized
 bool tud_inited(void);
 
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 5c564cb1c..ccc7ee102 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -407,6 +407,18 @@ void dcd_init(uint8_t rhport) {
   dcd_connect(rhport);
 }
 
+void dcd_deinit(uint8_t rhport) {
+  assert(rhport == 0);
+
+  dcd_disconnect(rhport);
+  reset_non_control_endpoints();
+  irq_remove_handler(USBCTRL_IRQ, dcd_rp2040_irq);
+
+  // reset usb hardware into initial state
+  reset_block(RESETS_RESET_USBCTRL_BITS);
+  unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+}
+
 void dcd_int_enable(__unused uint8_t rhport) {
   assert(rhport == 0);
   irq_set_enabled(USBCTRL_IRQ, true);
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index b351a9a07..762753a25 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -409,6 +409,14 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
+void hcd_deinit(uint8_t rhport) {
+  (void) rhport;
+
+  irq_remove_handler(USBCTRL_IRQ, hcd_rp2040_irq);
+  reset_block(RESETS_RESET_USBCTRL_BITS);
+  unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+}
+
 void hcd_port_reset(uint8_t rhport)
 {
   (void) rhport;
-- 
cgit v1.3.1


From c3c06484560d0102366a3a1b1101c35301009f97 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Apr 2024 22:07:56 +0700
Subject: add class driver deinit

---
 src/class/audio/audio_device.c               |   4 +
 src/class/audio/audio_device.h               |   1 +
 src/class/bth/bth_device.c                   |   7 +-
 src/class/bth/bth_device.h                   |   1 +
 src/class/cdc/cdc_device.c                   |  32 ++++-
 src/class/cdc/cdc_device.h                   |   1 +
 src/class/dfu/dfu_device.c                   |   7 +-
 src/class/dfu/dfu_device.h                   |   1 +
 src/class/dfu/dfu_rt_device.c                |   7 +-
 src/class/dfu/dfu_rt_device.h                |   1 +
 src/class/hid/hid_device.c                   |   7 +-
 src/class/hid/hid_device.h                   |   1 +
 src/class/midi/midi_device.c                 |  36 ++++-
 src/class/midi/midi_device.h                 |   1 +
 src/class/msc/msc_device.c                   |   8 +-
 src/class/msc/msc_device.h                   |   1 +
 src/class/net/ecm_rndis_device.c             |   7 +-
 src/class/net/ncm_device.c                   |   4 +
 src/class/net/net_device.h                   |   1 +
 src/class/usbtmc/usbtmc_device.c             |   5 +
 src/class/usbtmc/usbtmc_device.h             |   3 +-
 src/class/vendor/vendor_device.c             |  38 ++++-
 src/class/vendor/vendor_device.h             |   1 +
 src/class/video/video_device.c               |   4 +
 src/class/video/video_device.h               |   1 +
 src/device/dcd.h                             |   2 +-
 src/device/usbd.c                            | 204 +++++++++++++++++----------
 src/device/usbd.h                            |   2 +-
 src/device/usbd_pvt.h                        |   4 +-
 src/host/usbh.c                              |   2 +-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c |   5 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |   4 +-
 src/tusb_option.h                            |   2 +-
 33 files changed, 292 insertions(+), 113 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9a361419b..7077d66f8 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1396,6 +1396,10 @@ void audiod_init(void)
   }
 }
 
+bool audiod_deinit(void) {
+  return false; // TODO not implemented yet
+}
+
 void audiod_reset(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 040a760d6..b16514fd4 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -685,6 +685,7 @@ static inline bool tud_audio_fb_set(uint32_t feedback)
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     audiod_init           (void);
+bool     audiod_deinit         (void);
 void     audiod_reset          (uint8_t rhport);
 uint16_t audiod_open           (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index f145e2ead..cbf6e1332 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -91,11 +91,14 @@ bool tud_bt_acl_data_send(void *event, uint16_t event_len)
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void btd_init(void)
-{
+void btd_init(void) {
   tu_memclr(&_btd_itf, sizeof(_btd_itf));
 }
 
+bool btd_deinit(void) {
+  return true;
+}
+
 void btd_reset(uint8_t rhport)
 {
   (void)rhport;
diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h
index e782c532b..4f6350839 100755
--- a/src/class/bth/bth_device.h
+++ b/src/class/bth/bth_device.h
@@ -104,6 +104,7 @@ bool tud_bt_acl_data_send(void *acl_data, uint16_t data_len);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     btd_init            (void);
+bool     btd_deinit          (void);
 void     btd_reset           (uint8_t rhport);
 uint16_t btd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     btd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const *request);
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index c26264e60..7ef0530ec 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -253,11 +253,39 @@ void cdcd_init(void)
     // In this way, the most current data is prioritized.
     tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
 
-    tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, osal_mutex_create(&p_cdc->rx_ff_mutex));
-    tu_fifo_config_mutex(&p_cdc->tx_ff, osal_mutex_create(&p_cdc->tx_ff_mutex), NULL);
+    #if OSAL_MUTEX_REQUIRED
+    osal_mutex_t mutex_rd = osal_mutex_create(&p_cdc->rx_ff_mutex);
+    osal_mutex_t mutex_wr = osal_mutex_create(&p_cdc->tx_ff_mutex);
+    TU_ASSERT(mutex_rd != NULL && mutex_wr != NULL, );
+
+    tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, mutex_rd);
+    tu_fifo_config_mutex(&p_cdc->tx_ff, mutex_wr, NULL);
+    #endif
   }
 }
 
+bool cdcd_deinit(void) {
+  #if OSAL_MUTEX_REQUIRED
+  for(uint8_t i=0; i<CFG_TUD_CDC; i++) {
+    cdcd_interface_t* p_cdc = &_cdcd_itf[i];
+    osal_mutex_t mutex_rd = p_cdc->rx_ff.mutex_rd;
+    osal_mutex_t mutex_wr = p_cdc->tx_ff.mutex_wr;
+
+    if (mutex_rd) {
+      osal_mutex_delete(mutex_rd);
+      tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, NULL);
+    }
+
+    if (mutex_wr) {
+      osal_mutex_delete(mutex_wr);
+      tu_fifo_config_mutex(&p_cdc->tx_ff, NULL, NULL);
+    }
+  }
+  #endif
+
+  return true;
+}
+
 void cdcd_reset(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index a6e07aa5c..20e908451 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -247,6 +247,7 @@ static inline bool tud_cdc_write_clear(void)
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
 void     cdcd_init            (void);
+bool     cdcd_deinit          (void);
 void     cdcd_reset           (uint8_t rhport);
 uint16_t cdcd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     cdcd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 3e7c13dea..71e7ac2b3 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -160,11 +160,14 @@ void dfu_moded_reset(uint8_t rhport)
   reset_state();
 }
 
-void dfu_moded_init(void)
-{
+void dfu_moded_init(void) {
   dfu_moded_reset(0);
 }
 
+bool dfu_moded_deinit(void) {
+  return true;
+}
+
 uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
 {
   (void) rhport;
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index fecf8596f..00c22ea8b 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -86,6 +86,7 @@ TU_ATTR_WEAK void tud_dfu_abort_cb(uint8_t alt);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     dfu_moded_init(void);
+bool     dfu_moded_deinit(void);
 void     dfu_moded_reset(uint8_t rhport);
 uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c
index a940d8d62..3b801b787 100644
--- a/src/class/dfu/dfu_rt_device.c
+++ b/src/class/dfu/dfu_rt_device.c
@@ -51,8 +51,11 @@
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void dfu_rtd_init(void)
-{
+void dfu_rtd_init(void) {
+}
+
+bool dfu_rtd_deinit(void) {
+  return true;
 }
 
 void dfu_rtd_reset(uint8_t rhport)
diff --git a/src/class/dfu/dfu_rt_device.h b/src/class/dfu/dfu_rt_device.h
index babaa8214..67eb26d95 100644
--- a/src/class/dfu/dfu_rt_device.h
+++ b/src/class/dfu/dfu_rt_device.h
@@ -43,6 +43,7 @@ void tud_dfu_runtime_reboot_to_dfu_cb(void);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     dfu_rtd_init(void);
+bool     dfu_rtd_deinit(void);
 void     dfu_rtd_reset(uint8_t rhport);
 uint16_t dfu_rtd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 5637ea6b4..e8eda1400 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -166,11 +166,14 @@ bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
 //--------------------------------------------------------------------+
 // USBD-CLASS API
 //--------------------------------------------------------------------+
-void hidd_init(void)
-{
+void hidd_init(void) {
   hidd_reset(0);
 }
 
+bool hidd_deinit(void) {
+  return true;
+}
+
 void hidd_reset(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 17b24def1..53ecf9c06 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -406,6 +406,7 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     hidd_init            (void);
+bool     hidd_deinit          (void);
 void     hidd_reset           (uint8_t rhport);
 uint16_t hidd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 052372a93..42905ab0d 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -373,12 +373,10 @@ bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void midid_init(void)
-{
+void midid_init(void) {
   tu_memclr(_midid_itf, sizeof(_midid_itf));
 
-  for(uint8_t i=0; i<CFG_TUD_MIDI; i++)
-  {
+  for (uint8_t i = 0; i < CFG_TUD_MIDI; i++) {
     midid_interface_t* midi = &_midid_itf[i];
 
     // config fifo
@@ -386,12 +384,38 @@ void midid_init(void)
     tu_fifo_config(&midi->tx_ff, midi->tx_ff_buf, CFG_TUD_MIDI_TX_BUFSIZE, 1, false); // OBVS.
 
     #if CFG_FIFO_MUTEX
-    tu_fifo_config_mutex(&midi->rx_ff, NULL, osal_mutex_create(&midi->rx_ff_mutex));
-    tu_fifo_config_mutex(&midi->tx_ff, osal_mutex_create(&midi->tx_ff_mutex), NULL);
+    osal_mutex_t mutex_rd = osal_mutex_create(&midi->rx_ff_mutex);
+    osal_mutex_t mutex_wr = osal_mutex_create(&midi->tx_ff_mutex);
+    TU_ASSERT(mutex_wr != NULL && mutex_wr != NULL, );
+
+    tu_fifo_config_mutex(&midi->rx_ff, NULL, mutex_rd);
+    tu_fifo_config_mutex(&midi->tx_ff, mutex_wr, NULL);
     #endif
   }
 }
 
+bool midid_deinit(void) {
+  #if CFG_FIFO_MUTEX
+  for(uint8_t i=0; i<CFG_TUD_MIDI; i++) {
+    midid_interface_t* midi = &_midid_itf[i];
+    osal_mutex_t mutex_rd = midi->rx_ff.mutex_rd;
+    osal_mutex_t mutex_wr = midi->tx_ff.mutex_wr;
+
+    if (mutex_rd) {
+      osal_mutex_delete(mutex_rd);
+      tu_fifo_config_mutex(&midi->rx_ff, NULL, NULL);
+    }
+
+    if (mutex_wr) {
+      osal_mutex_delete(mutex_wr);
+      tu_fifo_config_mutex(&midi->tx_ff, NULL, NULL);
+    }
+  }
+  #endif
+
+  return true;
+}
+
 void midid_reset(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index 1c6f996be..3e89cc0a3 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -158,6 +158,7 @@ static inline bool tud_midi_packet_write (uint8_t const packet[4])
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     midid_init            (void);
+bool     midid_deinit          (void);
 void     midid_reset           (uint8_t rhport);
 uint16_t midid_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     midid_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index c145d86a6..588fcaaca 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -251,11 +251,15 @@ static inline void set_sense_medium_not_present(uint8_t lun)
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void mscd_init(void)
-{
+void mscd_init(void) {
   tu_memclr(&_mscd_itf, sizeof(mscd_interface_t));
 }
 
+bool mscd_deinit(void) {
+  // nothing to do
+  return true;
+}
+
 void mscd_reset(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h
index 72f95be06..4247a40bd 100644
--- a/src/class/msc/msc_device.h
+++ b/src/class/msc/msc_device.h
@@ -150,6 +150,7 @@ TU_ATTR_WEAK bool tud_msc_is_writable_cb(uint8_t lun);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     mscd_init            (void);
+bool     mscd_deinit          (void);
 void     mscd_reset           (uint8_t rhport);
 uint16_t mscd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     mscd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * p_request);
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index 762425732..f7a5fd225 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -132,11 +132,14 @@ void netd_report(uint8_t *buf, uint16_t len)
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void netd_init(void)
-{
+void netd_init(void) {
   tu_memclr(&_netd_itf, sizeof(_netd_itf));
 }
 
+bool netd_deinit(void) {
+  return true;
+}
+
 void netd_reset(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 226c42c4e..f84bd9f73 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -260,6 +260,10 @@ void netd_init(void)
   ncm_prepare_for_tx();
 }
 
+bool netd_deinit(void) {
+  return true;
+}
+
 void netd_reset(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 399916355..da1a7b1e8 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -105,6 +105,7 @@ void tud_network_link_state_cb(bool state);
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
 void     netd_init            (void);
+bool     netd_deinit          (void);
 void     netd_reset           (uint8_t rhport);
 uint16_t netd_open            (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 573654d58..972a450e6 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -260,6 +260,11 @@ void usbtmcd_init_cb(void)
   usbtmcLock = osal_mutex_create(&usbtmcLockBuffer);
 }
 
+bool usbtmcd_deinit(void) {
+  osal_mutex_delete(usbtmcLock);
+  return true;
+}
+
 uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
 {
   (void)rhport;
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index c1298ddb8..3299a36eb 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -98,11 +98,12 @@ bool tud_usbtmc_start_bus_read(void);
 
 /* "callbacks" from USB device core */
 
+void     usbtmcd_init_cb(void);
+bool     usbtmcd_deinit(void);
 uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 void     usbtmcd_reset_cb(uint8_t rhport);
 bool     usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 bool     usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
-void     usbtmcd_init_cb(void);
 
 /************************************************************
  * USBTMC Descriptor Templates
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index a68cb2156..e87ce3997 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -169,21 +169,47 @@ uint32_t tud_vendor_n_write_available (uint8_t itf)
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void vendord_init(void)
-{
+void vendord_init(void) {
   tu_memclr(_vendord_itf, sizeof(_vendord_itf));
 
-  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++)
-  {
+  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
     vendord_interface_t* p_itf = &_vendord_itf[i];
 
     // config fifo
     tu_fifo_config(&p_itf->rx_ff, p_itf->rx_ff_buf, CFG_TUD_VENDOR_RX_BUFSIZE, 1, false);
     tu_fifo_config(&p_itf->tx_ff, p_itf->tx_ff_buf, CFG_TUD_VENDOR_TX_BUFSIZE, 1, false);
 
-    tu_fifo_config_mutex(&p_itf->rx_ff, NULL, osal_mutex_create(&p_itf->rx_ff_mutex));
-    tu_fifo_config_mutex(&p_itf->tx_ff, osal_mutex_create(&p_itf->tx_ff_mutex), NULL);
+    #if OSAL_MUTEX_REQUIRED
+    osal_mutex_t mutex_rd = osal_mutex_create(&p_itf->rx_ff_mutex);
+    osal_mutex_t mutex_wr = osal_mutex_create(&p_itf->tx_ff_mutex);
+    TU_ASSERT(mutex_rd && mutex_wr,);
+
+    tu_fifo_config_mutex(&p_itf->rx_ff, NULL, mutex_rd);
+    tu_fifo_config_mutex(&p_itf->tx_ff, mutex_wr, NULL);
+    #endif
+  }
+}
+
+bool vendord_deinit(void) {
+  #if OSAL_MUTEX_REQUIRED
+  for(uint8_t i=0; i<CFG_TUD_VENDOR; i++) {
+    vendord_interface_t* p_itf = &_vendord_itf[i];
+    osal_mutex_t mutex_rd = p_itf->rx_ff.mutex_rd;
+    osal_mutex_t mutex_wr = p_itf->tx_ff.mutex_wr;
+
+    if (mutex_rd) {
+      osal_mutex_delete(mutex_rd);
+      tu_fifo_config_mutex(&p_itf->rx_ff, NULL, NULL);
+    }
+
+    if (mutex_wr) {
+      osal_mutex_delete(mutex_wr);
+      tu_fifo_config_mutex(&p_itf->tx_ff, NULL, NULL);
+    }
   }
+  #endif
+
+  return true;
 }
 
 void vendord_reset(uint8_t rhport)
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index d239406b4..cd69ec7c6 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -139,6 +139,7 @@ static inline uint32_t tud_vendor_write_available (void)
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 void     vendord_init(void);
+bool     vendord_deinit(void);
 void     vendord_reset(uint8_t rhport);
 uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 5306356ba..c30690232 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -1229,6 +1229,10 @@ void videod_init(void) {
   }
 }
 
+bool videod_deinit(void) {
+  return true;
+}
+
 void videod_reset(uint8_t rhport) {
   (void) rhport;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) {
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index ee2fcb9d5..92930c013 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -85,6 +85,7 @@ TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
 void     videod_init           (void);
+bool     videod_deinit         (void);
 void     videod_reset          (uint8_t rhport);
 uint16_t videod_open           (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 21f404e4f..d4f105aa3 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -123,7 +123,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W
 void dcd_init(uint8_t rhport);
 
 // Deinitialize controller, unset device mode.
-void dcd_deinit(uint8_t rhport);
+bool dcd_deinit(uint8_t rhport);
 
 // Interrupt Handler
 void dcd_int_handler(uint8_t rhport);
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 8f98862c6..439e071ff 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -43,8 +43,13 @@
 #endif
 
 //--------------------------------------------------------------------+
-// Callback weak stubs (called if application does not provide)
+// Weak stubs: invoked if no strong implementation is available
 //--------------------------------------------------------------------+
+TU_ATTR_WEAK bool dcd_deinit(uint8_t rhport) {
+  (void) rhport;
+  return false;
+}
+
 TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
   (void)rhport;
   (void)eventid;
@@ -85,17 +90,18 @@ tu_static usbd_device_t _usbd_dev;
 // Class Driver
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
-  #define DRIVER_NAME(_name)    .name = _name,
+  #define DRIVER_NAME(_name)  _name
 #else
-  #define DRIVER_NAME(_name)
+  #define DRIVER_NAME(_name)  NULL
 #endif
 
 // Built-in class drivers
 tu_static usbd_class_driver_t const _usbd_driver[] = {
     #if CFG_TUD_CDC
     {
-        DRIVER_NAME("CDC")
+        .name             = DRIVER_NAME("CDC"),
         .init             = cdcd_init,
+        .deinit           = cdcd_deinit,
         .reset            = cdcd_reset,
         .open             = cdcd_open,
         .control_xfer_cb  = cdcd_control_xfer_cb,
@@ -106,8 +112,9 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_MSC
     {
-        DRIVER_NAME("MSC")
+        .name             = DRIVER_NAME("MSC"),
         .init             = mscd_init,
+        .deinit           = NULL,
         .reset            = mscd_reset,
         .open             = mscd_open,
         .control_xfer_cb  = mscd_control_xfer_cb,
@@ -118,121 +125,131 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_HID
     {
-      DRIVER_NAME("HID")
-      .init             = hidd_init,
-      .reset            = hidd_reset,
-      .open             = hidd_open,
-      .control_xfer_cb  = hidd_control_xfer_cb,
-      .xfer_cb          = hidd_xfer_cb,
-      .sof              = NULL
+        .name             = DRIVER_NAME("HID"),
+        .init             = hidd_init,
+        .deinit           = hidd_deinit,
+        .reset            = hidd_reset,
+        .open             = hidd_open,
+        .control_xfer_cb  = hidd_control_xfer_cb,
+        .xfer_cb          = hidd_xfer_cb,
+        .sof              = NULL
     },
     #endif
 
     #if CFG_TUD_AUDIO
     {
-      DRIVER_NAME("AUDIO")
-      .init             = audiod_init,
-      .reset            = audiod_reset,
-      .open             = audiod_open,
-      .control_xfer_cb  = audiod_control_xfer_cb,
-      .xfer_cb          = audiod_xfer_cb,
-      .sof              = audiod_sof_isr
+        .name             = DRIVER_NAME("AUDIO"),
+        .init             = audiod_init,
+        .deinit           = audiod_deinit,
+        .reset            = audiod_reset,
+        .open             = audiod_open,
+        .control_xfer_cb  = audiod_control_xfer_cb,
+        .xfer_cb          = audiod_xfer_cb,
+        .sof              = audiod_sof_isr
     },
     #endif
 
     #if CFG_TUD_VIDEO
     {
-      DRIVER_NAME("VIDEO")
-      .init             = videod_init,
-      .reset            = videod_reset,
-      .open             = videod_open,
-      .control_xfer_cb  = videod_control_xfer_cb,
-      .xfer_cb          = videod_xfer_cb,
-      .sof              = NULL
+        .name             = DRIVER_NAME("VIDEO"),
+        .init             = videod_init,
+        .deinit           = videod_deinit,
+        .reset            = videod_reset,
+        .open             = videod_open,
+        .control_xfer_cb  = videod_control_xfer_cb,
+        .xfer_cb          = videod_xfer_cb,
+        .sof              = NULL
     },
     #endif
 
     #if CFG_TUD_MIDI
     {
-      DRIVER_NAME("MIDI")
-      .init             = midid_init,
-      .open             = midid_open,
-      .reset            = midid_reset,
-      .control_xfer_cb  = midid_control_xfer_cb,
-      .xfer_cb          = midid_xfer_cb,
-      .sof              = NULL
+        .name             = DRIVER_NAME("MIDI"),
+        .init             = midid_init,
+        .deinit           = midid_deinit,
+        .open             = midid_open,
+        .reset            = midid_reset,
+        .control_xfer_cb  = midid_control_xfer_cb,
+        .xfer_cb          = midid_xfer_cb,
+        .sof              = NULL
     },
     #endif
 
     #if CFG_TUD_VENDOR
     {
-      DRIVER_NAME("VENDOR")
-      .init             = vendord_init,
-      .reset            = vendord_reset,
-      .open             = vendord_open,
-      .control_xfer_cb  = tud_vendor_control_xfer_cb,
-      .xfer_cb          = vendord_xfer_cb,
-      .sof              = NULL
+        .name             = DRIVER_NAME("VENDOR"),
+        .init             = vendord_init,
+        .deinit           = vendord_deinit,
+        .reset            = vendord_reset,
+        .open             = vendord_open,
+        .control_xfer_cb  = tud_vendor_control_xfer_cb,
+        .xfer_cb          = vendord_xfer_cb,
+        .sof              = NULL
     },
     #endif
 
     #if CFG_TUD_USBTMC
     {
-      DRIVER_NAME("TMC")
-      .init             = usbtmcd_init_cb,
-      .reset            = usbtmcd_reset_cb,
-      .open             = usbtmcd_open_cb,
-      .control_xfer_cb  = usbtmcd_control_xfer_cb,
-      .xfer_cb          = usbtmcd_xfer_cb,
-      .sof              = NULL
+        .name             = DRIVER_NAME("TMC"),
+        .init             = usbtmcd_init_cb,
+        .deinit           = usbtmcd_deinit,
+        .reset            = usbtmcd_reset_cb,
+        .open             = usbtmcd_open_cb,
+        .control_xfer_cb  = usbtmcd_control_xfer_cb,
+        .xfer_cb          = usbtmcd_xfer_cb,
+        .sof              = NULL
     },
     #endif
 
     #if CFG_TUD_DFU_RUNTIME
     {
-      DRIVER_NAME("DFU-RUNTIME")
-      .init             = dfu_rtd_init,
-      .reset            = dfu_rtd_reset,
-      .open             = dfu_rtd_open,
-      .control_xfer_cb  = dfu_rtd_control_xfer_cb,
-      .xfer_cb          = NULL,
-      .sof              = NULL
+        .name             = DRIVER_NAME("DFU-RUNTIME"),
+        .init             = dfu_rtd_init,
+        .deinit           = dfu_rtd_deinit,
+        .reset            = dfu_rtd_reset,
+        .open             = dfu_rtd_open,
+        .control_xfer_cb  = dfu_rtd_control_xfer_cb,
+        .xfer_cb          = NULL,
+        .sof              = NULL
     },
     #endif
 
     #if CFG_TUD_DFU
     {
-      DRIVER_NAME("DFU")
-      .init             = dfu_moded_init,
-      .reset            = dfu_moded_reset,
-      .open             = dfu_moded_open,
-      .control_xfer_cb  = dfu_moded_control_xfer_cb,
-      .xfer_cb          = NULL,
-      .sof              = NULL
+        .name             = DRIVER_NAME("DFU"),
+        .init             = dfu_moded_init,
+        .deinit           = dfu_moded_deinit,
+        .reset            = dfu_moded_reset,
+        .open             = dfu_moded_open,
+        .control_xfer_cb  = dfu_moded_control_xfer_cb,
+        .xfer_cb          = NULL,
+        .sof              = NULL
     },
     #endif
 
     #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
     {
-      DRIVER_NAME("NET")
-      .init             = netd_init,
-      .reset            = netd_reset,
-      .open             = netd_open,
-      .control_xfer_cb  = netd_control_xfer_cb,
-      .xfer_cb          = netd_xfer_cb,
-      .sof                  = NULL,
+        .name             = DRIVER_NAME("NET"),
+        .init             = netd_init,
+        .deinit           = netd_deinit,
+        .reset            = netd_reset,
+        .open             = netd_open,
+        .control_xfer_cb  = netd_control_xfer_cb,
+        .xfer_cb          = netd_xfer_cb,
+        .sof                  = NULL,
     },
     #endif
 
     #if CFG_TUD_BTH
     {
-      DRIVER_NAME("BTH")
-      .init             = btd_init,
-      .reset            = btd_reset,
-      .open             = btd_open,
-      .control_xfer_cb  = btd_control_xfer_cb,
-      .xfer_cb          = btd_xfer_cb,
-      .sof              = NULL
+        .name             = DRIVER_NAME("BTH"),
+        .init             = btd_init,
+        .deinit           = btd_deinit,
+        .reset            = btd_reset,
+        .open             = btd_open,
+        .control_xfer_cb  = btd_control_xfer_cb,
+        .xfer_cb          = btd_xfer_cb,
+        .sof              = NULL
     },
     #endif
 };
@@ -402,7 +419,7 @@ bool tud_init(uint8_t rhport) {
   // Init class drivers
   for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
     usbd_class_driver_t const* driver = get_driver(i);
-    TU_ASSERT(driver);
+    TU_ASSERT(driver && driver->init);
     TU_LOG_USBD("%s init\r\n", driver->name);
     driver->init();
   }
@@ -416,6 +433,41 @@ bool tud_init(uint8_t rhport) {
   return true;
 }
 
+bool tud_deinit(uint8_t rhport) {
+  // skip if not initialized
+  if (!tud_inited()) return true;
+
+  TU_LOG_USBD("USBD deinit on controller %u\r\n", rhport);
+
+  // Deinit device controller driver
+  dcd_int_disable(rhport);
+  dcd_disconnect(rhport);
+  dcd_deinit(rhport);
+
+  // Deinit class drivers
+  for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
+    usbd_class_driver_t const* driver = get_driver(i);
+    if(driver && driver->deinit) {
+      TU_LOG_USBD("%s deinit\r\n", driver->name);
+      driver->deinit();
+    }
+  }
+
+  // Deinit device queue & task
+  osal_queue_delete(_usbd_q);
+  _usbd_q = NULL;
+
+#if OSAL_MUTEX_REQUIRED
+  // TODO make sure there is no task waiting on this mutex
+  osal_mutex_delete(_usbd_mutex);
+  _usbd_mutex = NULL;
+#endif
+
+  _usbd_rhport = RHPORT_INVALID;
+
+  return true;
+}
+
 static void configuration_reset(uint8_t rhport) {
   for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) {
     usbd_class_driver_t const* driver = get_driver(i);
diff --git a/src/device/usbd.h b/src/device/usbd.h
index a9350192b..0197628e2 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -41,7 +41,7 @@ extern "C" {
 bool tud_init (uint8_t rhport);
 
 // Deinit device stack on roothub port
-void tud_deinit(uint8_t rhport);
+bool tud_deinit(uint8_t rhport);
 
 // Check if device stack is already initialized
 bool tud_inited(void);
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 9039bc9d6..5ae96e589 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -40,11 +40,9 @@
 //--------------------------------------------------------------------+
 
 typedef struct {
-  #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   char const* name;
-  #endif
-
   void     (* init             ) (void);
+  bool     (* deinit           ) (void);
   void     (* reset            ) (uint8_t rhport);
   uint16_t (* open             ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
   bool     (* control_xfer_cb  ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index aa0603d47..6a5491998 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -425,7 +425,7 @@ bool tuh_deinit(uint8_t rhport) {
     // Class drivers
     for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
       usbh_class_driver_t const* driver = get_driver(drv_id);
-      if (driver) {
+      if (driver && driver->deinit) {
         TU_LOG_USBH("%s deinit\r\n", driver->name);
         driver->deinit();
       }
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index ccc7ee102..a2b3375a3 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -407,16 +407,17 @@ void dcd_init(uint8_t rhport) {
   dcd_connect(rhport);
 }
 
-void dcd_deinit(uint8_t rhport) {
+bool dcd_deinit(uint8_t rhport) {
   assert(rhport == 0);
 
-  dcd_disconnect(rhport);
   reset_non_control_endpoints();
   irq_remove_handler(USBCTRL_IRQ, dcd_rp2040_irq);
 
   // reset usb hardware into initial state
   reset_block(RESETS_RESET_USBCTRL_BITS);
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+
+  return true;
 }
 
 void dcd_int_enable(__unused uint8_t rhport) {
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 762753a25..222dbbbf0 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -409,12 +409,14 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
-void hcd_deinit(uint8_t rhport) {
+bool hcd_deinit(uint8_t rhport) {
   (void) rhport;
 
   irq_remove_handler(USBCTRL_IRQ, hcd_rp2040_irq);
   reset_block(RESETS_RESET_USBCTRL_BITS);
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+
+  return true;
 }
 
 void hcd_port_reset(uint8_t rhport)
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 2921d3ae0..cbcb69edd 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -34,7 +34,7 @@
 #define TUSB_VERSION_MAJOR     0
 #define TUSB_VERSION_MINOR     16
 #define TUSB_VERSION_REVISION  0
-#define TUSB_VERSION_BUILD     2
+#define TUSB_VERSION_BUILD     3
 
 #define TUSB_VERSION_NUMBER    (TUSB_VERSION_MAJOR << 24 | TUSB_VERSION_MINOR << 16 | TUSB_VERSION_REVISION << 8 | TUSB_VERSION_BUILD)
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
-- 
cgit v1.3.1


From 366564e952b974a49a5b8da7f1d4c729bd37219d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Apr 2024 22:13:05 +0700
Subject: fix missing if mutex required

---
 src/class/usbtmc/usbtmc_device.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src')

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 972a450e6..286cbe108 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -261,7 +261,9 @@ void usbtmcd_init_cb(void)
 }
 
 bool usbtmcd_deinit(void) {
+  #if OSAL_MUTEX_REQUIRED
   osal_mutex_delete(usbtmcLock);
+  #endif
   return true;
 }
 
-- 
cgit v1.3.1


From 4bc6a5feb74e073824cf404916442311b7040c47 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Apr 2024 22:22:00 +0700
Subject: fix unused warning

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index a2b3375a3..bc0deee32 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -408,7 +408,7 @@ void dcd_init(uint8_t rhport) {
 }
 
 bool dcd_deinit(uint8_t rhport) {
-  assert(rhport == 0);
+  (void) rhport;
 
   reset_non_control_endpoints();
   irq_remove_handler(USBCTRL_IRQ, dcd_rp2040_irq);
-- 
cgit v1.3.1


From be25a3fc20339c27803e68cb1363f89ffe7a7c67 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Apr 2024 22:56:22 +0700
Subject: revert usbd driver name change to be backward compatible

---
 src/device/usbd.c     | 28 ++++++++++++++--------------
 src/device/usbd_pvt.h |  3 +++
 2 files changed, 17 insertions(+), 14 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 439e071ff..96982c30b 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -90,16 +90,16 @@ tu_static usbd_device_t _usbd_dev;
 // Class Driver
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
-  #define DRIVER_NAME(_name)  _name
+  #define DRIVER_NAME(_name)    .name = _name,
 #else
-  #define DRIVER_NAME(_name)  NULL
+  #define DRIVER_NAME(_name)
 #endif
 
 // Built-in class drivers
 tu_static usbd_class_driver_t const _usbd_driver[] = {
     #if CFG_TUD_CDC
     {
-        .name             = DRIVER_NAME("CDC"),
+        DRIVER_NAME("CDC")
         .init             = cdcd_init,
         .deinit           = cdcd_deinit,
         .reset            = cdcd_reset,
@@ -112,7 +112,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_MSC
     {
-        .name             = DRIVER_NAME("MSC"),
+        DRIVER_NAME("MSC")
         .init             = mscd_init,
         .deinit           = NULL,
         .reset            = mscd_reset,
@@ -125,7 +125,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_HID
     {
-        .name             = DRIVER_NAME("HID"),
+        DRIVER_NAME("HID")
         .init             = hidd_init,
         .deinit           = hidd_deinit,
         .reset            = hidd_reset,
@@ -138,7 +138,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_AUDIO
     {
-        .name             = DRIVER_NAME("AUDIO"),
+        DRIVER_NAME("AUDIO")
         .init             = audiod_init,
         .deinit           = audiod_deinit,
         .reset            = audiod_reset,
@@ -151,7 +151,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_VIDEO
     {
-        .name             = DRIVER_NAME("VIDEO"),
+        DRIVER_NAME("VIDEO")
         .init             = videod_init,
         .deinit           = videod_deinit,
         .reset            = videod_reset,
@@ -164,7 +164,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_MIDI
     {
-        .name             = DRIVER_NAME("MIDI"),
+        DRIVER_NAME("MIDI")
         .init             = midid_init,
         .deinit           = midid_deinit,
         .open             = midid_open,
@@ -177,7 +177,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_VENDOR
     {
-        .name             = DRIVER_NAME("VENDOR"),
+        DRIVER_NAME("VENDOR")
         .init             = vendord_init,
         .deinit           = vendord_deinit,
         .reset            = vendord_reset,
@@ -190,7 +190,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_USBTMC
     {
-        .name             = DRIVER_NAME("TMC"),
+        DRIVER_NAME("TMC")
         .init             = usbtmcd_init_cb,
         .deinit           = usbtmcd_deinit,
         .reset            = usbtmcd_reset_cb,
@@ -203,7 +203,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_DFU_RUNTIME
     {
-        .name             = DRIVER_NAME("DFU-RUNTIME"),
+        DRIVER_NAME("DFU-RUNTIME")
         .init             = dfu_rtd_init,
         .deinit           = dfu_rtd_deinit,
         .reset            = dfu_rtd_reset,
@@ -216,7 +216,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_DFU
     {
-        .name             = DRIVER_NAME("DFU"),
+        DRIVER_NAME("DFU")
         .init             = dfu_moded_init,
         .deinit           = dfu_moded_deinit,
         .reset            = dfu_moded_reset,
@@ -229,7 +229,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
     {
-        .name             = DRIVER_NAME("NET"),
+        DRIVER_NAME("NET")
         .init             = netd_init,
         .deinit           = netd_deinit,
         .reset            = netd_reset,
@@ -242,7 +242,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = {
 
     #if CFG_TUD_BTH
     {
-        .name             = DRIVER_NAME("BTH"),
+        DRIVER_NAME("BTH")
         .init             = btd_init,
         .deinit           = btd_deinit,
         .reset            = btd_reset,
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 5ae96e589..47752f32c 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -40,7 +40,10 @@
 //--------------------------------------------------------------------+
 
 typedef struct {
+  #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   char const* name;
+  #endif
+
   void     (* init             ) (void);
   bool     (* deinit           ) (void);
   void     (* reset            ) (uint8_t rhport);
-- 
cgit v1.3.1


From 5c7876d4444de25942778728d377ec77f74a75dd Mon Sep 17 00:00:00 2001
From: Matthias Schär <matthias.schaer@jennyscience.ch>
Date: Thu, 28 Jul 2022 13:01:36 +0200
Subject: Fixed behavior of the PRCR register. Previous write protection will
 be recovered.

---
 .idea/cmake.xml                                            | 2 +-
 examples/device/cdc_msc_freertos/src/freertos_hook.c       | 3 ++-
 examples/device/hid_composite_freertos/src/freertos_hook.c | 3 ++-
 src/common/tusb_compiler.h                                 | 2 +-
 4 files changed, 6 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index ebc6a0570..e4a08eaa6 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -75,7 +75,7 @@
       <configuration PROFILE_NAME="stm32u575nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575nucleo -DLOG=3" />
       <configuration PROFILE_NAME="stm32u5a5nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u5a5nucleo -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra2a1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra2a1_ek -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ra4m1" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
diff --git a/examples/device/cdc_msc_freertos/src/freertos_hook.c b/examples/device/cdc_msc_freertos/src/freertos_hook.c
index ab885947c..3cd27e08c 100644
--- a/examples/device/cdc_msc_freertos/src/freertos_hook.c
+++ b/examples/device/cdc_msc_freertos/src/freertos_hook.c
@@ -99,9 +99,10 @@ void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, Stack
 void vApplicationSetupTimerInterrupt(void)
 {
   /* Enable CMT0 */
+  unsigned short oldPRCR = SYSTEM.PRCR.WORD;
   SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
   MSTP(CMT0)       = 0;
-  SYSTEM.PRCR.WORD = (0xA5u<<8);
+  SYSTEM.PRCR.WORD = oldPRCR;
 
   CMT0.CMCNT      = 0;
   CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
diff --git a/examples/device/hid_composite_freertos/src/freertos_hook.c b/examples/device/hid_composite_freertos/src/freertos_hook.c
index ab885947c..3cd27e08c 100644
--- a/examples/device/hid_composite_freertos/src/freertos_hook.c
+++ b/examples/device/hid_composite_freertos/src/freertos_hook.c
@@ -99,9 +99,10 @@ void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, Stack
 void vApplicationSetupTimerInterrupt(void)
 {
   /* Enable CMT0 */
+  unsigned short oldPRCR = SYSTEM.PRCR.WORD;
   SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
   MSTP(CMT0)       = 0;
-  SYSTEM.PRCR.WORD = (0xA5u<<8);
+  SYSTEM.PRCR.WORD = oldPRCR;
 
   CMT0.CMCNT      = 0;
   CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 6f07bdd53..86d150c68 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -56,7 +56,7 @@
 #elif defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
   #define TU_VERIFY_STATIC   _Static_assert
 #elif defined(__CCRX__)
-  #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0];
+  #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT3(Line, __LINE__, _TU_COUNTER_)[(const_expr) ? 1 : 0];
 #else
   #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) }
 #endif
-- 
cgit v1.3.1


From b0568e32a5d3ad427d296e0d3bcb1020d54d25a3 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 10:47:06 +0200
Subject: Fix tud_video_n_streaming check

---
 src/class/video/video_device.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index d0a88eb17..4218835aa 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -763,8 +763,8 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)(desc + ofs_ep);
     /* Only ISO endpoints needs to be closed */
     if(ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
-      usbd_edpt_close(rhport, ep->bEndpointAddress);
       stm->desc.ep[i] = 0;
+      usbd_edpt_close(rhport, ep->bEndpointAddress);
       TU_LOG_DRV("    close EP%02x\r\n", ep->bEndpointAddress);
     }
   }
@@ -1186,6 +1186,16 @@ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
   if (!stm || !stm->desc.ep[0]) return false;
   if (stm->state == VS_STATE_PROBING) return false;
+
+#ifdef TUP_DCD_EDPT_ISO_ALLOC
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
+  uint_fast16_t ofs_ep = stm->desc.ep[0];
+  tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)(desc + ofs_ep);
+  if (ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) {
+    if (stm->state == VS_STATE_COMMITTED) return false;
+  }
+#endif
+
   return true;
 }
 
-- 
cgit v1.3.1


From 6c2f71ad19bbe9e3d346b5631ede9557b4252088 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 9 Apr 2024 17:12:15 +0700
Subject: make veryfi static in ccrx consistent with the rest

---
 src/common/tusb_compiler.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 86d150c68..0d5570b1c 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -56,7 +56,7 @@
 #elif defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
   #define TU_VERIFY_STATIC   _Static_assert
 #elif defined(__CCRX__)
-  #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT3(Line, __LINE__, _TU_COUNTER_)[(const_expr) ? 1 : 0];
+  #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(_verify_static_, _TU_COUNTER_)[(const_expr) ? 1 : 0];
 #else
   #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) }
 #endif
-- 
cgit v1.3.1


From 00db4227451b223c939f7a84e93199a73519d04a Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 5 Apr 2024 13:12:24 +0200
Subject: Cleanup ep/pma free, ISO ep should use alloc/activate.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 99 +++------------------------
 1 file changed, 8 insertions(+), 91 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 7bf726f3f..41b5acbc6 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -183,12 +183,9 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
 static void dcd_ep_ctr_handler(void);
 
 // PMA allocation/access
-static uint8_t open_ep_count;
 static uint16_t ep_buf_ptr; ///< Points to first free memory location
 static void dcd_pma_alloc_reset(void);
 static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length);
-static void dcd_pma_free(uint8_t ep_addr);
-static void dcd_ep_free(uint8_t ep_addr);
 static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes);
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes);
@@ -765,7 +762,6 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 
 static void dcd_pma_alloc_reset(void)
 {
-  open_ep_count = 0;
   ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
   //TU_LOG2("dcd_pma_alloc_reset()\r\n");
   for(uint32_t i=0; i<MAX_EP_COUNT; i++)
@@ -805,8 +801,6 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
   length = (length + 1) & ~0x01;
 #endif
 
-  open_ep_count++;
-
   uint16_t addr = ep_buf_ptr;
   ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
 
@@ -820,33 +814,6 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
   return addr;
 }
 
-/***
- * Free a block of PMA space
- */
-static void dcd_pma_free(uint8_t ep_addr)
-{
-  // Presently, this should never be called for EP0 IN/OUT
-  TU_ASSERT(open_ep_count > 2, /**/);
-  TU_ASSERT(xfer_ctl_ptr(ep_addr)->max_packet_size != 0, /**/);
-  open_ep_count--;
-
-  // If count is 2, only EP0 should be open, so allocations can be mostly reset.
-
-  if(open_ep_count == 2)
-  {
-    ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT + 2*CFG_TUD_ENDPOINT0_SIZE; // 8 bytes per endpoint (two TX and two RX words, each), and EP0
-
-    // Skip EP0
-    for(uint32_t i=1; i<MAX_EP_COUNT; i++)
-    {
-      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_alloc_size = 0U;
-      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_alloc_size = 0U;
-      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_ptr = 0U;
-      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_ptr = 0U;
-    }
-  }
-}
-
 /***
  * Allocate hardware endpoint
  */
@@ -892,34 +859,6 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
   TU_ASSERT(0);
 }
 
-/***
- * Free hardware endpoint
- */
-static void dcd_ep_free(uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
-  {
-    // Check if EP number & dir are the same
-    if(ep_alloc_status[i].ep_num == epnum &&
-       ep_alloc_status[i].allocated[dir] == dir)
-    {
-      ep_alloc_status[i].allocated[dir] = false;
-      // Reset entry if ISO endpoint or both direction are free
-      if(ep_alloc_status[i].ep_type == TUSB_XFER_ISOCHRONOUS ||
-         !ep_alloc_status[i].allocated[dir ^ 1])
-      {
-        ep_alloc_status[i].ep_num = 0xFF;
-        ep_alloc_status[i].ep_type = 0xFF;
-
-        return;
-      }
-    }
-  }
-}
-
 // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
 // so I'm using the #define from HAL here, instead.
 
@@ -934,16 +873,16 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   uint32_t wType;
 
   TU_ASSERT(ep_idx < STFSDEV_EP_COUNT);
-  TU_ASSERT(buffer_size <= 1024);
+  TU_ASSERT(buffer_size <= 64);
+
+  // ISO endpoint should use alloc / active functions
+  TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
   // Set type
   switch(p_endpoint_desc->bmAttributes.xfer) {
   case TUSB_XFER_CONTROL:
     wType = USB_EP_CONTROL;
     break;
-  case TUSB_XFER_ISOCHRONOUS:
-    wType = USB_EP_ISOCHRONOUS;
-    break;
   case TUSB_XFER_BULK:
     wType = USB_EP_CONTROL;
     break;
@@ -958,45 +897,27 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
 
   pcd_set_eptype(USB, ep_idx, wType);
   pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
-  // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
-  // or being double-buffered (bulk endpoints)
-  pcd_clear_ep_kind(USB,0);
 
   /* Create a packet memory buffer area. For isochronous endpoints,
    * use the same buffer as the double buffer, essentially disabling double buffering */
   pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size);
 
-  if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) )
+  if(dir == TUSB_DIR_IN)
   {
     pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size);
+    pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
     pcd_clear_tx_dtog(USB, ep_idx);
   }
 
-  if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) )
+  if(dir == TUSB_DIR_OUT)
   {
     pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size);
+    pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
     pcd_clear_rx_dtog(USB, ep_idx);
   }
 
-  /* Enable endpoint */
-  if (dir == TUSB_DIR_IN)
-  {
-    if(wType == USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
-    } else {
-      pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
-    }
-  } else
-  {
-    if(wType == USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
-    } else {
-      pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
-    }
-  }
-
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx = ep_idx;
 
@@ -1032,10 +953,6 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
   {
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
   }
-
-  dcd_ep_free(ep_addr);
-
-  dcd_pma_free(ep_addr);
 }
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
-- 
cgit v1.3.1


From bf3e9b865302c90bc175e2ed28d64de9dc7bf8c9 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 13:31:23 +0200
Subject: Refactor edpt_xfer(), support double buffering in dcd_pma_alloc().

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 114 +++++++++-----------------
 1 file changed, 37 insertions(+), 77 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 41b5acbc6..f380355ae 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -151,9 +151,7 @@ typedef struct
   tu_fifo_t * ff;
   uint16_t total_len;
   uint16_t queued_len;
-  uint16_t pma_ptr;
   uint16_t max_packet_size;
-  uint16_t pma_alloc_size;
   uint8_t ep_idx; // index for USB_EPnR register
 } xfer_ctl_t;
 
@@ -180,12 +178,12 @@ static uint8_t remoteWakeCountdown; // When wake is requested
 // into the stack.
 static void dcd_handle_bus_reset(void);
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
+static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr);
 static void dcd_ep_ctr_handler(void);
 
 // PMA allocation/access
 static uint16_t ep_buf_ptr; ///< Points to first free memory location
-static void dcd_pma_alloc_reset(void);
-static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length);
+static uint32_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length, bool dbuf);
 static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes);
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes);
@@ -491,7 +489,9 @@ static void dcd_handle_bus_reset(void)
     ep_alloc_status[i].allocated[1] = false;
   }
 
-  dcd_pma_alloc_reset();
+  // Reset PMA allocation
+  ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT;
+
   dcd_edpt_open (0, &ep0OUT_desc);
   dcd_edpt_open (0, &ep0IN_desc);
 
@@ -760,40 +760,15 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
   }
 }
 
-static void dcd_pma_alloc_reset(void)
-{
-  ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
-  //TU_LOG2("dcd_pma_alloc_reset()\r\n");
-  for(uint32_t i=0; i<MAX_EP_COUNT; i++)
-  {
-    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_alloc_size = 0U;
-    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_alloc_size = 0U;
-    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_ptr = 0U;
-    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_ptr = 0U;
-  }
-}
-
 /***
  * Allocate a section of PMA
- *
- * If the EP number has already been allocated, and the new allocation
- * is larger than the old allocation, then this will fail with a TU_ASSERT.
- * (This is done to simplify the code. More complicated algorithms could be used)
- *
+ * In case of double buffering, high 16bit is the address of 2nd buffer
  * During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
  */
-static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
+static uint32_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length, bool dbuf)
 {
   xfer_ctl_t* epXferCtl = xfer_ctl_ptr(ep_addr);
 
-  if(epXferCtl->pma_alloc_size != 0U)
-  {
-    //TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr);
-    // Previously allocated
-    TU_ASSERT(length <= epXferCtl->pma_alloc_size, 0xFFFF);  // Verify no larger than previous alloc
-    return epXferCtl->pma_ptr;
-  }
-
   // Ensure allocated buffer is aligned
 #ifdef FSDEV_BUS_32BIT
   length = (length + 3) & ~0x03;
@@ -801,15 +776,16 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
   length = (length + 1) & ~0x01;
 #endif
 
-  uint16_t addr = ep_buf_ptr;
+  uint32_t addr = ep_buf_ptr;
   ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
 
-  // Verify no overflow
-  TU_ASSERT(ep_buf_ptr <= FSDEV_PMA_SIZE, 0xFFFF);
+  if(dbuf) {
+    addr |= ((uint32_t)ep_buf_ptr) << 16;
+    ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
+  }
 
-  epXferCtl->pma_ptr = addr;
-  epXferCtl->pma_alloc_size = length;
-  //TU_LOG1("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr);
+  // Verify packet buffer is not overflowed
+  TU_ASSERT(ep_buf_ptr <= FSDEV_PMA_SIZE, 0xFFFF);
 
   return addr;
 }
@@ -898,9 +874,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   pcd_set_eptype(USB, ep_idx, wType);
   pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
 
-  /* Create a packet memory buffer area. For isochronous endpoints,
-   * use the same buffer as the double buffer, essentially disabling double buffering */
-  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size);
+  /* Create a packet memory buffer area. */
+  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size, false);
 
   if(dir == TUSB_DIR_IN)
   {
@@ -966,7 +941,7 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
 
   /* Create a packet memory buffer area. For isochronous endpoints,
    * use the same buffer as the double buffer, essentially disabling double buffering */
-  uint16_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size);
+  uint16_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size, false);
 
   xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
 
@@ -1036,7 +1011,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
 
   /* Write into correct register when ISOCHRONOUS (double buffered) */
-  if ( (ep_reg & USB_EP_DTOG_TX) && ( (ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) ) {
+  if ((ep_reg & USB_EP_DTOG_TX) && ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
     pcd_set_ep_rx_cnt(USB, ep_ix, len);
   } else {
     pcd_set_ep_tx_cnt(USB, ep_ix, len);
@@ -1045,7 +1020,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
 }
 
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
@@ -1053,26 +1028,18 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   uint8_t const ep_idx = xfer->ep_idx;
   uint8_t const dir    = tu_edpt_dir(ep_addr);
 
-  xfer->buffer = buffer;
-  xfer->ff     = NULL;
-  xfer->total_len = total_bytes;
-  xfer->queued_len = 0;
-
   if ( dir == TUSB_DIR_OUT )
   {
     // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
     // buffer for the control endpoint.
-    if (ep_idx == 0 && buffer == NULL)
+    if (ep_idx == 0 && xfer->buffer == NULL)
     {
-        xfer->buffer = (uint8_t*)_setup_packet;
+      xfer->buffer = (uint8_t*)_setup_packet;
     }
 
-    if(total_bytes > xfer->max_packet_size)
-    {
-      pcd_set_ep_rx_bufsize(USB,ep_idx,xfer->max_packet_size);
-    } else {
-      pcd_set_ep_rx_bufsize(USB,ep_idx,total_bytes);
-    }
+    uint32_t bufsize = xfer->total_len > xfer->max_packet_size ? xfer->max_packet_size : xfer->total_len;
+    pcd_set_ep_rx_bufsize(USB, ep_idx, bufsize);
+
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID);
   }
   else // IN
@@ -1082,34 +1049,27 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   return true;
 }
 
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
-  (void) rhport;
-
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
-  uint8_t const epnum = xfer->ep_idx;
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
 
+  xfer->buffer = buffer;
+  xfer->ff     = NULL;
+  xfer->total_len = total_bytes;
+  xfer->queued_len = 0;
+
+  return edpt_xfer(rhport, ep_addr);
+}
+
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
   xfer->buffer = NULL;
   xfer->ff     = ff;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
-  if ( dir == TUSB_DIR_OUT )
-  {
-    if(total_bytes > xfer->max_packet_size)
-    {
-      pcd_set_ep_rx_bufsize(USB,epnum,xfer->max_packet_size);
-    } else {
-      pcd_set_ep_rx_bufsize(USB,epnum,total_bytes);
-    }
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
-  }
-  else // IN
-  {
-    dcd_transmit_packet(xfer,epnum);
-  }
-  return true;
+  return edpt_xfer(rhport, ep_addr);
 }
 
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-- 
cgit v1.3.1


From 41fb2b69f72207d069ebbce50a0457c4c5cdfb35 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 16:20:18 +0200
Subject: Rework macro according to ST driver.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
index 946ad2c7c..7992f34a1 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.h
@@ -298,6 +298,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USB
 #endif
 }
 
+#define pcd_get_ep_dbuf0_cnt pcd_get_ep_tx_cnt
+#define pcd_get_ep_dbuf1_cnt pcd_get_ep_rx_cnt
+
 /**
   * @brief  Sets address in an endpoint register.
   * @param  USBx USB peripheral instance register address.
@@ -331,6 +334,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef *
 #endif
 }
 
+#define pcd_get_ep_dbuf0_address pcd_get_ep_tx_address
+#define pcd_get_ep_dbuf1_address pcd_get_ep_rx_address
+
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
@@ -349,6 +355,9 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USB
 #endif
 }
 
+#define pcd_set_ep_dbuf0_address pcd_set_ep_tx_address
+#define pcd_set_ep_dbuf1_address pcd_set_ep_rx_address
+
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
@@ -359,7 +368,9 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, u
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
+#define pcd_set_ep_tx_dbuf0_cnt pcd_set_ep_tx_cnt
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_dbuf1_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
 #ifdef FSDEV_BUS_32BIT
   (void) USBx;
   pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
@@ -395,14 +406,16 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx,
   pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_dbuf0_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
   pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount) {
   pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount);
 }
 
+#define pcd_set_ep_rx_dbuf1_cnt pcd_set_ep_rx_cnt
+
 /**
   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
   * @param  USBx USB peripheral instance register address.
-- 
cgit v1.3.1


From 973d29acd095662a3a5f1dfb8d57a3ad8092f89b Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 16:24:54 +0200
Subject: Rework ISO double buffering.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 115 ++++++++++++++------------
 1 file changed, 62 insertions(+), 53 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index f380355ae..4844c916d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -586,26 +586,31 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
   }
   else
   {
+    // Clear RX CTR interrupt flag
+    if(ep_addr != 0u) {
+      pcd_clear_rx_ep_ctr(USB, EPindex);
+    }
+
     uint32_t count;
+    uint16_t addr;
     /* Read from correct register when ISOCHRONOUS (double buffered) */
-    if ( (wEPRegVal & USB_EP_DTOG_RX) && ( (wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) ) {
-      count = pcd_get_ep_tx_cnt(USB, EPindex);
+    if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
+      if (wEPRegVal & USB_EP_DTOG_RX) {
+        count = pcd_get_ep_dbuf0_cnt(USB, EPindex);
+        addr = pcd_get_ep_dbuf0_address(USB, EPindex);
+      } else {
+        count = pcd_get_ep_dbuf1_cnt(USB, EPindex);
+        addr = pcd_get_ep_dbuf1_address(USB, EPindex);
+      }
     } else {
       count = pcd_get_ep_rx_cnt(USB, EPindex);
+      addr = pcd_get_ep_rx_address(USB, EPindex);
     }
 
     TU_ASSERT(count <= xfer->max_packet_size, /**/);
 
-    // Clear RX CTR interrupt flag
-    if(ep_addr != 0u)
-    {
-      pcd_clear_rx_ep_ctr(USB, EPindex);
-    }
-
     if (count != 0U)
     {
-      uint16_t addr = pcd_get_ep_rx_address(USB, EPindex);
-
       if (xfer->ff)
       {
         dcd_read_packet_memory_ff(xfer->ff, addr, count);
@@ -627,16 +632,15 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
     }
     else
     {
-      uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
-      if(remaining >= xfer->max_packet_size) {
-        pcd_set_ep_rx_bufsize(USB, EPindex,xfer->max_packet_size);
-      } else {
-        pcd_set_ep_rx_bufsize(USB, EPindex,remaining);
-      }
-
+      /* Set endpoint active again for receiving more data.
+       * Note that isochronous endpoints stay active always */
       if (!((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
-        /* Set endpoint active again for receiving more data.
-         * Note that isochronous endpoints stay active always */
+        uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
+        if(remaining >= xfer->max_packet_size) {
+          pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size);
+        } else {
+          pcd_set_ep_rx_cnt(USB, EPindex,remaining);
+        }
         pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
       }
     }
@@ -648,7 +652,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
   if(ep_addr == 0u)
   {
     // Always be prepared for a status packet...
-    pcd_set_ep_rx_bufsize(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
+    pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
     pcd_clear_rx_ep_ctr(USB, EPindex);
   }
 }
@@ -838,7 +842,7 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
 // so I'm using the #define from HAL here, instead.
 
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void)rhport;
   uint8_t const ep_idx = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
@@ -880,7 +884,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   if(dir == TUSB_DIR_IN)
   {
     pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
-    pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size);
     pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
     pcd_clear_tx_dtog(USB, ep_idx);
   }
@@ -888,7 +891,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   if(dir == TUSB_DIR_OUT)
   {
     pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
-    pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size);
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
     pcd_clear_rx_dtog(USB, ep_idx);
   }
@@ -912,7 +914,7 @@ void dcd_edpt_close_all (uint8_t rhport)
  *
  * This also clears transfers in progress, should there be any.
  */
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
@@ -939,16 +941,15 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
   uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
   const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
 
-  /* Create a packet memory buffer area. For isochronous endpoints,
-   * use the same buffer as the double buffer, essentially disabling double buffering */
-  uint16_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size, false);
+  /* Create a packet memory buffer area. Enable double buffering */
+  uint32_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size, true);
 
   xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
 
   pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
 
-  pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
-  pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
+  pcd_set_ep_tx_address(USB, ep_idx, pma_addr & 0xFFFF);
+  pcd_set_ep_rx_address(USB, ep_idx, pma_addr >> 16);
 
   return true;
 }
@@ -961,26 +962,20 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
   const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
 
-  /* Disable endpoint */
-  if(dir == TUSB_DIR_IN)
-  {
-    pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
-  }
-  else
-  {
-    pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
-  }
+  pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
+  pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
 
   pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
-  // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
-  // or being double-buffered (bulk endpoints)
-  pcd_clear_ep_kind(USB,0);
 
-  pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size);
-  pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size);
   pcd_clear_tx_dtog(USB, ep_idx);
   pcd_clear_rx_dtog(USB, ep_idx);
 
+  if(dir == TUSB_DIR_IN) {
+    pcd_rx_dtog(USB, ep_idx);
+  } else {
+    pcd_tx_dtog(USB, ep_idx);
+  }
+
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
 
   return true;
@@ -998,7 +993,21 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   }
 
   uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix);
-  uint16_t addr_ptr = pcd_get_ep_tx_address(USB, ep_ix);
+  uint16_t addr_ptr;
+
+
+  if ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
+    if (ep_reg & USB_EP_DTOG_TX) {
+      addr_ptr = pcd_get_ep_dbuf1_address(USB, ep_ix);
+      pcd_set_ep_tx_dbuf1_cnt(USB, ep_ix, len);
+    } else {
+      addr_ptr = pcd_get_ep_dbuf0_address(USB, ep_ix);
+      pcd_set_ep_tx_dbuf0_cnt(USB, ep_ix, len);
+    }
+  } else {
+    addr_ptr = pcd_get_ep_tx_address(USB, ep_ix);
+    pcd_set_ep_tx_cnt(USB, ep_ix, len);
+  }
 
   if (xfer->ff)
   {
@@ -1010,13 +1019,6 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   }
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
 
-  /* Write into correct register when ISOCHRONOUS (double buffered) */
-  if ((ep_reg & USB_EP_DTOG_TX) && ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
-    pcd_set_ep_rx_cnt(USB, ep_ix, len);
-  } else {
-    pcd_set_ep_tx_cnt(USB, ep_ix, len);
-  }
-
   pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
 }
 
@@ -1037,8 +1039,15 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
       xfer->buffer = (uint8_t*)_setup_packet;
     }
 
-    uint32_t bufsize = xfer->total_len > xfer->max_packet_size ? xfer->max_packet_size : xfer->total_len;
-    pcd_set_ep_rx_bufsize(USB, ep_idx, bufsize);
+    uint32_t cnt = xfer->total_len > xfer->max_packet_size ? xfer->max_packet_size : xfer->total_len;
+    uint16_t ep_reg = pcd_get_endpoint(USB, ep_idx);
+
+    if ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_rx_dbuf0_cnt(USB, ep_idx, cnt);
+      pcd_set_ep_rx_dbuf1_cnt(USB, ep_idx, cnt);
+    } else {
+      pcd_set_ep_rx_cnt(USB, ep_idx, cnt);
+    }
 
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID);
   }
-- 
cgit v1.3.1


From 472996e2bfbd14341e99aa58e9f0c24e69a5043e Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 16:29:08 +0200
Subject: Ignore spurious RX interrupt.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 4844c916d..a6d92c7c0 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -153,6 +153,7 @@ typedef struct
   uint16_t queued_len;
   uint16_t max_packet_size;
   uint8_t ep_idx; // index for USB_EPnR register
+  bool in_complete; // Workaround for ISO IN EP doesn't have interrupt mask
 } xfer_ctl_t;
 
 // EP allocator
@@ -518,6 +519,19 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
   pcd_clear_tx_ep_ctr(USB, EPindex);
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+
+  /* Ignore spurious int */
+  if(xfer->in_complete) return;
+  xfer->in_complete = true;
+
+  if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
+    if (wEPRegVal & USB_EP_DTOG_TX) {
+      pcd_set_ep_tx_dbuf0_cnt(USB, EPindex, 0);
+    } else {
+      pcd_set_ep_tx_dbuf1_cnt(USB, EPindex, 0);
+    }
+  }
+
   if((xfer->total_len != xfer->queued_len)) /* TX not complete */
   {
     dcd_transmit_packet(xfer, EPindex);
@@ -1019,7 +1033,10 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   }
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
 
+  dcd_int_disable(0);
   pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
+  xfer->in_complete = false;
+  dcd_int_enable(0);
 }
 
 static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
-- 
cgit v1.3.1


From c0824472e8741ba67b660f34f27b5b4fcfe6c295 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 22:15:18 +0200
Subject: Enable double buffer only for PMA > 1024b

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index a6d92c7c0..d85adfe95 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -950,20 +950,26 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
 {
   (void)rhport;
 
-  TU_ASSERT(largest_packet_size <= 1024);
+  TU_ASSERT(largest_packet_size < 1024);
 
   uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
   const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
 
-  /* Create a packet memory buffer area. Enable double buffering */
+  /* Create a packet memory buffer area. Enable double buffering for devices with 2048 bytes PMA,
+     for smaller devices double buffering occupy too much space. */
+#if FSDEV_PMA_SIZE > 1024u
   uint32_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size, true);
-
-  xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
+  uint16_t pma_addr2 = pma_addr >> 16;
+#else
+  uint32_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size, true);
+  uint16_t pma_addr2 = pma_addr;
+#endif
+  pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
+  pcd_set_ep_rx_address(USB, ep_idx, pma_addr2);
 
   pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
 
-  pcd_set_ep_tx_address(USB, ep_idx, pma_addr & 0xFFFF);
-  pcd_set_ep_rx_address(USB, ep_idx, pma_addr >> 16);
+  xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
 
   return true;
 }
-- 
cgit v1.3.1


From 146c3c69450924d64795bd3d627ad1affaed5af7 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 22:59:48 +0200
Subject: Cleanup.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index d85adfe95..b89961d7d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -184,7 +184,7 @@ static void dcd_ep_ctr_handler(void);
 
 // PMA allocation/access
 static uint16_t ep_buf_ptr; ///< Points to first free memory location
-static uint32_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length, bool dbuf);
+static uint32_t dcd_pma_alloc(uint16_t length, bool dbuf);
 static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes);
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes);
@@ -649,14 +649,12 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
       /* Set endpoint active again for receiving more data.
        * Note that isochronous endpoints stay active always */
       if (!((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
-        uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
-        if(remaining >= xfer->max_packet_size) {
-          pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size);
-        } else {
-          pcd_set_ep_rx_cnt(USB, EPindex,remaining);
-        }
-        pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
+        uint16_t remaining = xfer->total_len - xfer->queued_len;
+        uint16_t cnt = remaining >= xfer->max_packet_size ? xfer->max_packet_size : remaining;
+        pcd_set_ep_rx_cnt(USB, EPindex, cnt);
+        pcd_set_ep_rx_cnt(USB, EPindex,remaining);
       }
+      pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
     }
   }
 
@@ -783,10 +781,8 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
  * In case of double buffering, high 16bit is the address of 2nd buffer
  * During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
  */
-static uint32_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length, bool dbuf)
+static uint32_t dcd_pma_alloc(uint16_t length, bool dbuf)
 {
-  xfer_ctl_t* epXferCtl = xfer_ctl_ptr(ep_addr);
-
   // Ensure allocated buffer is aligned
 #ifdef FSDEV_BUS_32BIT
   length = (length + 3) & ~0x03;
@@ -893,7 +889,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
 
   /* Create a packet memory buffer area. */
-  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size, false);
+  pma_addr = dcd_pma_alloc(buffer_size, false);
 
   if(dir == TUSB_DIR_IN)
   {
@@ -958,10 +954,10 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
   /* Create a packet memory buffer area. Enable double buffering for devices with 2048 bytes PMA,
      for smaller devices double buffering occupy too much space. */
 #if FSDEV_PMA_SIZE > 1024u
-  uint32_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size, true);
+  uint32_t pma_addr = dcd_pma_alloc(buffer_size, true);
   uint16_t pma_addr2 = pma_addr >> 16;
 #else
-  uint32_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size, true);
+  uint32_t pma_addr = dcd_pma_alloc(buffer_size, true);
   uint16_t pma_addr2 = pma_addr;
 #endif
   pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
@@ -980,7 +976,6 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
   uint8_t const ep_idx = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx;
   uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
-  const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
 
   pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
   pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
@@ -1015,7 +1010,6 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix);
   uint16_t addr_ptr;
 
-
   if ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
     if (ep_reg & USB_EP_DTOG_TX) {
       addr_ptr = pcd_get_ep_dbuf1_address(USB, ep_ix);
-- 
cgit v1.3.1


From 402b084646b6d9c7c6520def6de343b7b7fdab07 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 9 Apr 2024 23:00:29 +0200
Subject: Format doc.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 603 +++++++++++---------------
 1 file changed, 260 insertions(+), 343 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index b89961d7d..c11a8c625 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -107,9 +107,9 @@
 #include "device/dcd.h"
 
 #ifdef TUP_USBIP_FSDEV_STM32
-  // Undefine to reduce the dependence on HAL
-  #undef USE_HAL_DRIVER
-  #include "portable/st/stm32_fsdev/dcd_stm32_fsdev.h"
+// Undefine to reduce the dependence on HAL
+#undef USE_HAL_DRIVER
+#include "portable/st/stm32_fsdev/dcd_stm32_fsdev.h"
 #endif
 
 /*****************************************************
@@ -119,17 +119,17 @@
 // HW supports max of 8 bidirectional endpoints, but this can be reduced to save RAM
 // (8u here would mean 8 IN and 8 OUT)
 #ifndef MAX_EP_COUNT
-#  define MAX_EP_COUNT 8U
+#define MAX_EP_COUNT 8U
 #endif
 
 // If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
 // Both of these MUST be a multiple of 2, and are in byte units.
 #ifndef DCD_STM32_BTABLE_BASE
-#  define DCD_STM32_BTABLE_BASE 0U
+#define DCD_STM32_BTABLE_BASE 0U
 #endif
 
 #ifndef DCD_STM32_BTABLE_SIZE
-#  define DCD_STM32_BTABLE_SIZE (FSDEV_PMA_SIZE - DCD_STM32_BTABLE_BASE)
+#define DCD_STM32_BTABLE_SIZE (FSDEV_PMA_SIZE - DCD_STM32_BTABLE_BASE)
 #endif
 
 /***************************************************
@@ -145,20 +145,18 @@ TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligne
 //--------------------------------------------------------------------+
 
 // One of these for every EP IN & OUT, uses a bit of RAM....
-typedef struct
-{
-  uint8_t * buffer;
-  tu_fifo_t * ff;
+typedef struct {
+  uint8_t *buffer;
+  tu_fifo_t *ff;
   uint16_t total_len;
   uint16_t queued_len;
   uint16_t max_packet_size;
-  uint8_t ep_idx; // index for USB_EPnR register
+  uint8_t ep_idx;   // index for USB_EPnR register
   bool in_complete; // Workaround for ISO IN EP doesn't have interrupt mask
 } xfer_ctl_t;
 
 // EP allocator
-typedef struct
-{
+typedef struct {
   uint8_t ep_num;
   uint8_t ep_type;
   bool allocated[2];
@@ -178,7 +176,7 @@ static uint8_t remoteWakeCountdown; // When wake is requested
 
 // into the stack.
 static void dcd_handle_bus_reset(void);
-static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
+static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix);
 static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr);
 static void dcd_ep_ctr_handler(void);
 
@@ -189,14 +187,15 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes);
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes);
 
-static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes);
-static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes);
+static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes);
+static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes);
 
 //--------------------------------------------------------------------+
 // Inline helper
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) {
+TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint32_t ep_addr)
+{
   uint8_t epnum = tu_edpt_number(ep_addr);
   uint8_t dir = tu_edpt_dir(ep_addr);
   // Fix -Werror=null-dereference
@@ -209,7 +208,7 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr) {
 // Controller API
 //--------------------------------------------------------------------+
 
-void dcd_init (uint8_t rhport)
+void dcd_init(uint8_t rhport)
 {
   /* Clocks should already be enabled */
   /* Use __HAL_RCC_USB_CLK_ENABLE(); to enable the clocks before calling this function */
@@ -217,13 +216,13 @@ void dcd_init (uint8_t rhport)
   /* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL.
    * Here, the RM is followed. */
 
-  for(uint32_t i = 0; i<200; i++) // should be a few us
+  for (uint32_t i = 0; i < 200; i++) // should be a few us
   {
     asm("NOP");
   }
   // Perform USB peripheral reset
   USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
-  for(uint32_t i = 0; i<200; i++) // should be a few us
+  for (uint32_t i = 0; i < 200; i++) // should be a few us
   {
     asm("NOP");
   }
@@ -231,29 +230,29 @@ void dcd_init (uint8_t rhport)
   USB->CNTR &= ~USB_CNTR_PDWN;
 
   // Wait startup time, for F042 and F070, this is <= 1 us.
-  for(uint32_t i = 0; i<200; i++) // should be a few us
+  for (uint32_t i = 0; i < 200; i++) // should be a few us
   {
     asm("NOP");
   }
   USB->CNTR = 0; // Enable USB
 
-#if !defined(STM32G0) && !defined(STM32H5)  // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
+#if !defined(STM32G0) && !defined(STM32H5) // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
   USB->BTABLE = DCD_STM32_BTABLE_BASE;
 #endif
   USB->ISTR = 0; // Clear pending interrupts
 
   // Reset endpoints to disabled
-  for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
-  {
+  for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) {
     // This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
-    pcd_set_endpoint(USB,i,0u);
+    pcd_set_endpoint(USB, i, 0u);
   }
 
   USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
   dcd_handle_bus_reset();
 
   // Enable pull-up if supported
-  if ( dcd_connect ) dcd_connect(rhport);
+  if (dcd_connect)
+    dcd_connect(rhport);
 }
 
 // Define only on MCU with internal pull-up. BSP can define on MCU without internal PU.
@@ -262,14 +261,14 @@ void dcd_init (uint8_t rhport)
 // Disable internal D+ PU
 void dcd_disconnect(uint8_t rhport)
 {
-  (void) rhport;
+  (void)rhport;
   USB->BCDR &= ~(USB_BCDR_DPPU);
 }
 
 // Enable internal D+ PU
 void dcd_connect(uint8_t rhport)
 {
-  (void) rhport;
+  (void)rhport;
   USB->BCDR |= USB_BCDR_DPPU;
 }
 
@@ -277,60 +276,54 @@ void dcd_connect(uint8_t rhport)
 // Disable internal D+ PU
 void dcd_disconnect(uint8_t rhport)
 {
-  (void) rhport;
+  (void)rhport;
   SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU);
 }
 
 // Enable internal D+ PU
 void dcd_connect(uint8_t rhport)
 {
-  (void) rhport;
+  (void)rhport;
   SYSCFG->PMC |= SYSCFG_PMC_USB_PU;
 }
 #endif
 
 void dcd_sof_enable(uint8_t rhport, bool en)
 {
-  (void) rhport;
-  (void) en;
+  (void)rhport;
+  (void)en;
 
-  if (en)
-  {
+  if (en) {
     USB->CNTR |= USB_CNTR_SOFM;
-  }
-  else
-  {
+  } else {
     USB->CNTR &= ~USB_CNTR_SOFM;
   }
 }
 
 // Enable device interrupt
-void dcd_int_enable (uint8_t rhport)
+void dcd_int_enable(uint8_t rhport)
 {
   (void)rhport;
   // Member here forces write to RAM before allowing ISR to execute
   __DSB();
   __ISB();
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L4
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || CFG_TUSB_MCU == OPT_MCU_STM32L4
   NVIC_EnableIRQ(USB_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1
   NVIC_EnableIRQ(USB_LP_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-  // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
-  // shared USB/CAN IRQs to separate CAN and USB IRQs.
-  // This dynamically checks if this remap is active to enable the right IRQs.
-  #ifdef SYSCFG_CFGR1_USB_IT_RMP
-  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP)
-  {
+// Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
+// shared USB/CAN IRQs to separate CAN and USB IRQs.
+// This dynamically checks if this remap is active to enable the right IRQs.
+#ifdef SYSCFG_CFGR1_USB_IT_RMP
+  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
     NVIC_EnableIRQ(USB_HP_IRQn);
     NVIC_EnableIRQ(USB_LP_IRQn);
     NVIC_EnableIRQ(USBWakeUp_RMP_IRQn);
-  }
-  else
-  #endif
+  } else
+#endif
   {
     NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
     NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
@@ -347,14 +340,14 @@ void dcd_int_enable (uint8_t rhport)
   NVIC_EnableIRQ(USBWakeUp_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-  #ifdef STM32G0B0xx
-    NVIC_EnableIRQ(USB_IRQn);
-  #else
-    NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
-  #endif
+#ifdef STM32G0B0xx
+  NVIC_EnableIRQ(USB_IRQn);
+#else
+  NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
+#endif
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
-    NVIC_EnableIRQ(USB_DRD_FS_IRQn);
+  NVIC_EnableIRQ(USB_DRD_FS_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_EnableIRQ(USB_HP_IRQn);
@@ -364,7 +357,7 @@ void dcd_int_enable (uint8_t rhport)
   NVIC_EnableIRQ(USB_FS_IRQn);
 
 #else
-  #error Unknown arch in USB driver
+#error Unknown arch in USB driver
 #endif
 }
 
@@ -373,24 +366,21 @@ void dcd_int_disable(uint8_t rhport)
 {
   (void)rhport;
 
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L4
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || CFG_TUSB_MCU == OPT_MCU_STM32L4
   NVIC_DisableIRQ(USB_IRQn);
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1
   NVIC_DisableIRQ(USB_LP_IRQn);
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F3
-  // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
-  // shared USB/CAN IRQs to separate CAN and USB IRQs.
-  // This dynamically checks if this remap is active to disable the right IRQs.
-  #ifdef SYSCFG_CFGR1_USB_IT_RMP
-  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP)
-  {
+// Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
+// shared USB/CAN IRQs to separate CAN and USB IRQs.
+// This dynamically checks if this remap is active to disable the right IRQs.
+#ifdef SYSCFG_CFGR1_USB_IT_RMP
+  if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) {
     NVIC_DisableIRQ(USB_HP_IRQn);
     NVIC_DisableIRQ(USB_LP_IRQn);
     NVIC_DisableIRQ(USBWakeUp_RMP_IRQn);
-  }
-  else
-  #endif
+  } else
+#endif
   {
     NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn);
     NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
@@ -407,14 +397,14 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USBWakeUp_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-  #ifdef STM32G0B0xx
-    NVIC_DisableIRQ(USB_IRQn);
-  #else
-    NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
-  #endif
+#ifdef STM32G0B0xx
+  NVIC_DisableIRQ(USB_IRQn);
+#else
+  NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
+#endif
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H5
-    NVIC_DisableIRQ(USB_DRD_FS_IRQn);
+  NVIC_DisableIRQ(USB_DRD_FS_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_DisableIRQ(USB_HP_IRQn);
@@ -424,7 +414,7 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_FS_IRQn);
 
 #else
-  #error Unknown arch in USB driver
+#error Unknown arch in USB driver
 #endif
 
   // CMSIS has a membar after disabling interrupts
@@ -433,8 +423,8 @@ void dcd_int_disable(uint8_t rhport)
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-  (void) rhport;
-  (void) dev_addr;
+  (void)rhport;
+  (void)dev_addr;
 
   // Respond with status
   dcd_edpt_xfer(rhport, TUSB_DIR_IN_MASK | 0x00, NULL, 0);
@@ -445,43 +435,36 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
-  (void) rhport;
+  (void)rhport;
 
   USB->CNTR |= USB_CNTR_RESUME;
   remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
 }
 
-static const tusb_desc_endpoint_t ep0OUT_desc =
-{
-  .bLength          = sizeof(tusb_desc_endpoint_t),
-  .bDescriptorType  = TUSB_DESC_ENDPOINT,
+static const tusb_desc_endpoint_t ep0OUT_desc = {.bLength = sizeof(tusb_desc_endpoint_t),
+                                                 .bDescriptorType = TUSB_DESC_ENDPOINT,
 
-  .bEndpointAddress = 0x00,
-  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
-  .bInterval        = 0
-};
+                                                 .bEndpointAddress = 0x00,
+                                                 .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
+                                                 .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
+                                                 .bInterval = 0};
 
-static const tusb_desc_endpoint_t ep0IN_desc =
-{
-  .bLength          = sizeof(tusb_desc_endpoint_t),
-  .bDescriptorType  = TUSB_DESC_ENDPOINT,
+static const tusb_desc_endpoint_t ep0IN_desc = {.bLength = sizeof(tusb_desc_endpoint_t),
+                                                .bDescriptorType = TUSB_DESC_ENDPOINT,
 
-  .bEndpointAddress = 0x80,
-  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
-  .bInterval        = 0
-};
+                                                .bEndpointAddress = 0x80,
+                                                .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
+                                                .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
+                                                .bInterval = 0};
 
 static void dcd_handle_bus_reset(void)
 {
   //__IO uint16_t * const epreg = &(EPREG(0));
   USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
 
-  for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
-  {
+  for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) {
     // Clear all EPREG (or maybe this is automatic? I'm not sure)
-    pcd_set_endpoint(USB,i,0u);
+    pcd_set_endpoint(USB, i, 0u);
 
     // Clear EP allocation status
     ep_alloc_status[i].ep_num = 0xFF;
@@ -491,10 +474,10 @@ static void dcd_handle_bus_reset(void)
   }
 
   // Reset PMA allocation
-  ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT;
+  ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT;
 
-  dcd_edpt_open (0, &ep0OUT_desc);
-  dcd_edpt_open (0, &ep0IN_desc);
+  dcd_edpt_open(0, &ep0OUT_desc);
+  dcd_edpt_open(0, &ep0IN_desc);
 
   USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
 }
@@ -510,18 +493,18 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
 
   // Verify the CTR_TX bit is set. This was in the ST Micro code,
   // but I'm not sure it's actually necessary?
-  if((wEPRegVal & USB_EP_CTR_TX) == 0U)
-  {
+  if ((wEPRegVal & USB_EP_CTR_TX) == 0U) {
     return;
   }
 
   /* clear int flag */
   pcd_clear_tx_ep_ctr(USB, EPindex);
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
 
   /* Ignore spurious int */
-  if(xfer->in_complete) return;
+  if (xfer->in_complete)
+    return;
   xfer->in_complete = true;
 
   if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
@@ -532,11 +515,10 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
     }
   }
 
-  if((xfer->total_len != xfer->queued_len)) /* TX not complete */
+  if ((xfer->total_len != xfer->queued_len)) /* TX not complete */
   {
     dcd_transmit_packet(xfer, EPindex);
-  }
-  else /* TX Complete */
+  } else /* TX Complete */
   {
     dcd_event_xfer_complete(0, ep_addr, xfer->total_len, XFER_RESULT_SUCCESS, true);
   }
@@ -544,8 +526,9 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
 
 // Handle CTR interrupt for the RX/OUT direction
 // Upon call, (wIstr & USB_ISTR_DIR) == 0U
-static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
-  #ifdef FSDEV_BUS_32BIT
+static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
+{
+#ifdef FSDEV_BUS_32BIT
   /* https://www.st.com/resource/en/errata_sheet/es0561-stm32h503cbebkbrb-device-errata-stmicroelectronics.pdf
    * From STM32H503 errata 2.15.1: Buffer description table update completes after CTR interrupt triggers
    * Description:
@@ -564,7 +547,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
   while (cycle_count > 0U) {
     cycle_count--; // each count take 2 cycle (1 cycle for sub, 1 cycle for compare/jump)
   }
-  #endif
+#endif
 
   uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
   uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
@@ -574,34 +557,32 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
 
   // Verify the CTR_RX bit is set. This was in the ST Micro code,
   // but I'm not sure it's actually necessary?
-  if((wEPRegVal & USB_EP_CTR_RX) == 0U) {
+  if ((wEPRegVal & USB_EP_CTR_RX) == 0U) {
     return;
   }
 
-  if((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
+  if ((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
   {
     uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex);
     /* Get SETUP Packet*/
-    if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
+    if (count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
     {
       // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
-      pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
-      pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
+      pcd_set_ep_rx_status(USB, 0u, USB_EP_RX_NAK);
+      pcd_set_ep_tx_status(USB, 0u, USB_EP_TX_NAK);
 #ifdef FSDEV_BUS_32BIT
-      dcd_event_setup_received(0, (uint8_t*)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true);
+      dcd_event_setup_received(0, (uint8_t *)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true);
 #else
       // The setup_received function uses memcpy, so this must first copy the setup data into
       // user memory, to allow for the 32-bit access that memcpy performs.
       uint8_t userMemBuf[8];
-      dcd_read_packet_memory(userMemBuf, pcd_get_ep_rx_address(USB,EPindex), 8);
-      dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
+      dcd_read_packet_memory(userMemBuf, pcd_get_ep_rx_address(USB, EPindex), 8);
+      dcd_event_setup_received(0, (uint8_t *)userMemBuf, true);
 #endif
     }
-  }
-  else
-  {
+  } else {
     // Clear RX CTR interrupt flag
-    if(ep_addr != 0u) {
+    if (ep_addr != 0u) {
       pcd_clear_rx_ep_ctr(USB, EPindex);
     }
 
@@ -623,36 +604,29 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
 
     TU_ASSERT(count <= xfer->max_packet_size, /**/);
 
-    if (count != 0U)
-    {
-      if (xfer->ff)
-      {
+    if (count != 0U) {
+      if (xfer->ff) {
         dcd_read_packet_memory_ff(xfer->ff, addr, count);
-      }
-      else
-      {
+      } else {
         dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), addr, count);
       }
 
       xfer->queued_len = (uint16_t)(xfer->queued_len + count);
     }
 
-    if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
-    {
+    if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
       /* RX COMPLETE */
       dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
       // Though the host could still send, we don't know.
       // Does the bulk pipe need to be reset to valid to allow for a ZLP?
-    }
-    else
-    {
+    } else {
       /* Set endpoint active again for receiving more data.
        * Note that isochronous endpoints stay active always */
       if (!((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
         uint16_t remaining = xfer->total_len - xfer->queued_len;
         uint16_t cnt = remaining >= xfer->max_packet_size ? xfer->max_packet_size : remaining;
         pcd_set_ep_rx_cnt(USB, EPindex, cnt);
-        pcd_set_ep_rx_cnt(USB, EPindex,remaining);
+        pcd_set_ep_rx_cnt(USB, EPindex, remaining);
       }
       pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
     }
@@ -661,15 +635,15 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
   // For EP0, prepare to receive another SETUP packet.
   // Clear CTR last so that a new packet does not overwrite the packing being read.
   // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared)
-  if(ep_addr == 0u)
-  {
+  if (ep_addr == 0u) {
     // Always be prepared for a status packet...
     pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
     pcd_clear_rx_ep_ctr(USB, EPindex);
   }
 }
 
-static void dcd_ep_ctr_handler(void) {
+static void dcd_ep_ctr_handler(void)
+{
   uint32_t wIstr;
 
   /* stay in loop while pending interrupts */
@@ -684,26 +658,27 @@ static void dcd_ep_ctr_handler(void) {
   }
 }
 
-void dcd_int_handler(uint8_t rhport) {
+void dcd_int_handler(uint8_t rhport)
+{
 
-  (void) rhport;
+  (void)rhport;
 
   uint32_t int_status = USB->ISTR;
-  //const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP
-  //    | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF;
-  // unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ )
+  // const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP
+  //     | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF;
+  //  unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ )
 
   // The ST driver loops here on the CTR bit, but that loop has been moved into the
   // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't
   // be triggered repeatedly.
 
   /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
-  if(int_status & USB_ISTR_SOF) {
+  if (int_status & USB_ISTR_SOF) {
     USB->ISTR = (fsdev_bus_t)~USB_ISTR_SOF;
     dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
   }
 
-  if(int_status & USB_ISTR_RESET) {
+  if (int_status & USB_ISTR_RESET) {
     // USBRST is start of reset.
     USB->ISTR = (fsdev_bus_t)~USB_ISTR_RESET;
     dcd_handle_bus_reset();
@@ -711,15 +686,13 @@ void dcd_int_handler(uint8_t rhport) {
     return; // Don't do the rest of the things here; perhaps they've been cleared?
   }
 
-  if (int_status & USB_ISTR_CTR)
-  {
+  if (int_status & USB_ISTR_CTR) {
     /* servicing of the endpoint correct transfer interrupt */
     /* clear of the CTR flag into the sub */
     dcd_ep_ctr_handler();
   }
 
-  if (int_status & USB_ISTR_WKUP)
-  {
+  if (int_status & USB_ISTR_WKUP) {
     USB->CNTR &= ~USB_CNTR_LPMODE;
     USB->CNTR &= ~USB_CNTR_FSUSP;
 
@@ -727,8 +700,7 @@ void dcd_int_handler(uint8_t rhport) {
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
 
-  if (int_status & USB_ISTR_SUSP)
-  {
+  if (int_status & USB_ISTR_SUSP) {
     /* Suspend is asserted for both suspend and unplug events. without Vbus monitoring,
      * these events cannot be differentiated, so we only trigger suspend. */
 
@@ -741,13 +713,11 @@ void dcd_int_handler(uint8_t rhport) {
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 
-  if(int_status & USB_ISTR_ESOF) {
-    if(remoteWakeCountdown == 1u)
-    {
+  if (int_status & USB_ISTR_ESOF) {
+    if (remoteWakeCountdown == 1u) {
       USB->CNTR &= ~USB_CNTR_RESUME;
     }
-    if(remoteWakeCountdown > 0u)
-    {
+    if (remoteWakeCountdown > 0u) {
       remoteWakeCountdown--;
     }
     USB->ISTR = (fsdev_bus_t)~USB_ISTR_ESOF;
@@ -760,15 +730,12 @@ void dcd_int_handler(uint8_t rhport) {
 
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
-void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request)
 {
-  (void) rhport;
+  (void)rhport;
 
-  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
-      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-      request->bRequest == TUSB_REQ_SET_ADDRESS )
-  {
-    uint8_t const dev_addr = (uint8_t) request->wValue;
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_ADDRESS) {
+    uint8_t const dev_addr = (uint8_t)request->wValue;
 
     // Setting new address after the whole request is complete
     USB->DADDR &= ~USB_DADDR_ADD;
@@ -793,7 +760,7 @@ static uint32_t dcd_pma_alloc(uint16_t length, bool dbuf)
   uint32_t addr = ep_buf_ptr;
   ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
 
-  if(dbuf) {
+  if (dbuf) {
     addr |= ((uint32_t)ep_buf_ptr) << 16;
     ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
   }
@@ -810,31 +777,21 @@ static uint32_t dcd_pma_alloc(uint16_t length, bool dbuf)
 static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
-  {
+  for (uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) {
     // Check if already allocated
-    if(ep_alloc_status[i].allocated[dir] &&
-       ep_alloc_status[i].ep_type == ep_type &&
-       ep_alloc_status[i].ep_num == epnum)
-    {
+    if (ep_alloc_status[i].allocated[dir] && ep_alloc_status[i].ep_type == ep_type && ep_alloc_status[i].ep_num == epnum) {
       return i;
     }
 
     // If EP of current direction is not allocated
     // Except for ISO endpoint, both direction should be free
-    if(!ep_alloc_status[i].allocated[dir] &&
-       (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1]))
-    {
+    if (!ep_alloc_status[i].allocated[dir] && (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) {
       // Check if EP number is the same
-      if(ep_alloc_status[i].ep_num == 0xFF ||
-         ep_alloc_status[i].ep_num == epnum)
-      {
+      if (ep_alloc_status[i].ep_num == 0xFF || ep_alloc_status[i].ep_num == epnum) {
         // One EP pair has to be the same type
-        if(ep_alloc_status[i].ep_type == 0xFF ||
-           ep_alloc_status[i].ep_type == ep_type)
-        {
+        if (ep_alloc_status[i].ep_type == 0xFF || ep_alloc_status[i].ep_type == ep_type) {
           ep_alloc_status[i].ep_num = epnum;
           ep_alloc_status[i].ep_type = ep_type;
           ep_alloc_status[i].allocated[dir] = true;
@@ -852,11 +809,11 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
 // so I'm using the #define from HAL here, instead.
 
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
 {
   (void)rhport;
   uint8_t const ep_idx = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
-  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
   const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
   uint16_t pma_addr;
@@ -869,7 +826,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
   // Set type
-  switch(p_endpoint_desc->bmAttributes.xfer) {
+  switch (p_endpoint_desc->bmAttributes.xfer) {
   case TUSB_XFER_CONTROL:
     wType = USB_EP_CONTROL;
     break;
@@ -891,15 +848,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   /* Create a packet memory buffer area. */
   pma_addr = dcd_pma_alloc(buffer_size, false);
 
-  if(dir == TUSB_DIR_IN)
-  {
+  if (dir == TUSB_DIR_IN) {
     pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
     pcd_clear_tx_dtog(USB, ep_idx);
   }
 
-  if(dir == TUSB_DIR_OUT)
-  {
+  if (dir == TUSB_DIR_OUT) {
     pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
     pcd_clear_rx_dtog(USB, ep_idx);
@@ -911,9 +866,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
+void dcd_edpt_close_all(uint8_t rhport)
 {
-  (void) rhport;
+  (void)rhport;
   // TODO implement dcd_edpt_close_all()
 }
 
@@ -928,16 +883,13 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
   uint8_t const ep_idx = xfer->ep_idx;
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if(dir == TUSB_DIR_IN)
-  {
+  if (dir == TUSB_DIR_IN) {
     pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
-  }
-  else
-  {
+  } else {
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
   }
 }
@@ -970,11 +922,11 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
   return true;
 }
 
-bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
+bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
 {
   (void)rhport;
   uint8_t const ep_idx = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx;
-  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
 
   pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
@@ -985,7 +937,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
   pcd_clear_tx_dtog(USB, ep_idx);
   pcd_clear_rx_dtog(USB, ep_idx);
 
-  if(dir == TUSB_DIR_IN) {
+  if (dir == TUSB_DIR_IN) {
     pcd_rx_dtog(USB, ep_idx);
   } else {
     pcd_tx_dtog(USB, ep_idx);
@@ -998,11 +950,11 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
 
 // Currently, single-buffered, and only 64 bytes at a time (max)
 
-static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
+static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix)
 {
   uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
 
-  if(len > xfer->max_packet_size) // max packet size for FS transfer
+  if (len > xfer->max_packet_size) // max packet size for FS transfer
   {
     len = xfer->max_packet_size;
   }
@@ -1023,12 +975,9 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
     pcd_set_ep_tx_cnt(USB, ep_ix, len);
   }
 
-  if (xfer->ff)
-  {
+  if (xfer->ff) {
     dcd_write_packet_memory_ff(xfer->ff, addr_ptr, len);
-  }
-  else
-  {
+  } else {
     dcd_write_packet_memory(addr_ptr, &(xfer->buffer[xfer->queued_len]), len);
   }
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
@@ -1041,19 +990,17 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
 
 static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
 {
-  (void) rhport;
+  (void)rhport;
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
   uint8_t const ep_idx = xfer->ep_idx;
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if ( dir == TUSB_DIR_OUT )
-  {
+  if (dir == TUSB_DIR_OUT) {
     // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
     // buffer for the control endpoint.
-    if (ep_idx == 0 && xfer->buffer == NULL)
-    {
-      xfer->buffer = (uint8_t*)_setup_packet;
+    if (ep_idx == 0 && xfer->buffer == NULL) {
+      xfer->buffer = (uint8_t *)_setup_packet;
     }
 
     uint32_t cnt = xfer->total_len > xfer->max_packet_size ? xfer->max_packet_size : xfer->total_len;
@@ -1067,75 +1014,68 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
     }
 
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID);
-  }
-  else // IN
+  } else // IN
   {
-    dcd_transmit_packet(xfer,ep_idx);
+    dcd_transmit_packet(xfer, ep_idx);
   }
   return true;
 }
 
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
-  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
 
   xfer->buffer = buffer;
-  xfer->ff     = NULL;
+  xfer->ff = NULL;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
   return edpt_xfer(rhport, ep_addr);
 }
 
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes)
 {
-  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
   xfer->buffer = NULL;
-  xfer->ff     = ff;
+  xfer->ff = ff;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
   return edpt_xfer(rhport, ep_addr);
 }
 
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
   uint8_t const ep_idx = xfer->ep_idx;
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if (dir == TUSB_DIR_IN)
-  { // IN
+  if (dir == TUSB_DIR_IN) { // IN
     pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_STALL);
-  }
-  else
-  { // OUT
+  } else { // OUT
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_STALL);
   }
 }
 
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
   uint8_t const ep_idx = xfer->ep_idx;
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if (dir == TUSB_DIR_IN)
-  { // IN
-    if (pcd_get_eptype(USB, ep_idx) !=  USB_EP_ISOCHRONOUS) {
+  if (dir == TUSB_DIR_IN) { // IN
+    if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) {
       pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
     }
 
     /* Reset to DATA0 if clearing stall condition. */
     pcd_clear_tx_dtog(USB, ep_idx);
-  }
-  else
-  { // OUT
-    if (pcd_get_eptype(USB, ep_idx) !=  USB_EP_ISOCHRONOUS) {
+  } else { // OUT
+    if (pcd_get_eptype(USB, ep_idx) != USB_EP_ISOCHRONOUS) {
       pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
     }
     /* Reset to DATA0 if clearing stall condition. */
@@ -1146,8 +1086,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 #ifdef FSDEV_BUS_32BIT
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
 {
-  const uint8_t* srcVal = src;
-  volatile uint32_t* dst32 = (volatile uint32_t*)(USB_PMAADDR + dst);
+  const uint8_t *srcVal = src;
+  volatile uint32_t *dst32 = (volatile uint32_t *)(USB_PMAADDR + dst);
 
   for (uint32_t n = wNBytes / 4; n > 0; --n) {
     *dst32++ = tu_unaligned_read32(srcVal);
@@ -1155,18 +1095,15 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
   }
 
   wNBytes = wNBytes & 0x03;
-  if (wNBytes)
-  {
+  if (wNBytes) {
     uint32_t wrVal = *srcVal;
     wNBytes--;
 
-    if (wNBytes)
-    {
+    if (wNBytes) {
       wrVal |= *++srcVal << 8;
       wNBytes--;
 
-      if (wNBytes)
-      {
+      if (wNBytes) {
         wrVal |= *++srcVal << 16;
       }
     }
@@ -1179,20 +1116,20 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
 #else
 // Packet buffer access can only be 8- or 16-bit.
 /**
-  * @brief Copy a buffer from user memory area to packet memory area (PMA).
-  *        This uses byte-access for user memory (so support non-aligned buffers)
-  *        and 16-bit access for packet memory.
-  * @param   dst, byte address in PMA; must be 16-bit aligned
-  * @param   src pointer to user memory area.
-  * @param   wPMABufAddr address into PMA.
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
+ * @brief Copy a buffer from user memory area to packet memory area (PMA).
+ *        This uses byte-access for user memory (so support non-aligned buffers)
+ *        and 16-bit access for packet memory.
+ * @param   dst, byte address in PMA; must be 16-bit aligned
+ * @param   src pointer to user memory area.
+ * @param   wPMABufAddr address into PMA.
+ * @param   wNBytes no. of bytes to be copied.
+ * @retval None
+ */
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
 {
   uint32_t n = (uint32_t)wNBytes >> 1U;
   uint16_t temp1, temp2;
-  const uint8_t * srcVal;
+  const uint8_t *srcVal;
 
   // The GCC optimizer will combine access to 32-bit sizes if we let it. Force
   // it volatile so that it won't do that.
@@ -1201,18 +1138,16 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
   srcVal = src;
   pdwVal = &pma[FSDEV_PMA_STRIDE * (dst >> 1)];
 
-  while (n--)
-  {
+  while (n--) {
     temp1 = (uint16_t)*srcVal;
     srcVal++;
-    temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U)) ;
+    temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U));
     *pdwVal = temp2;
     pdwVal += FSDEV_PMA_STRIDE;
     srcVal++;
   }
 
-  if (wNBytes)
-  {
+  if (wNBytes) {
     temp1 = *srcVal;
     *pdwVal = temp1;
   }
@@ -1222,42 +1157,39 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, ui
 #endif
 
 /**
-  * @brief Copy from FIFO to packet memory area (PMA).
-  *        Uses byte-access of system memory and 16-bit access of packet memory
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes)
+ * @brief Copy from FIFO to packet memory area (PMA).
+ *        Uses byte-access of system memory and 16-bit access of packet memory
+ * @param   wNBytes no. of bytes to be copied.
+ * @retval None
+ */
+static bool dcd_write_packet_memory_ff(tu_fifo_t *ff, uint16_t dst, uint16_t wNBytes)
 {
   // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
   tu_fifo_buffer_info_t info;
   tu_fifo_get_read_info(ff, &info);
 
-  uint16_t cnt_lin =  TU_MIN(wNBytes, info.len_lin);
+  uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin);
   uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
 
   // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
   // last lin byte will be combined with wrapped part
   // To ensure PMA is always access aligned (dst aligned to 16 or 32 bit)
 #ifdef FSDEV_BUS_32BIT
-  if((cnt_lin & 0x03) && cnt_wrap)
-  {
+  if ((cnt_lin & 0x03) && cnt_wrap) {
     // Copy first linear part
-    dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin &~0x03);
-    dst += cnt_lin &~0x03;
+    dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin & ~0x03);
+    dst += cnt_lin & ~0x03;
 
     // Copy last linear bytes & first wrapped bytes to buffer
     uint32_t i;
     uint8_t tmp[4];
-    for (i = 0; i < (cnt_lin & 0x03); i++)
-    {
-      tmp[i] = ((uint8_t*)info.ptr_lin)[(cnt_lin &~0x03) + i];
+    for (i = 0; i < (cnt_lin & 0x03); i++) {
+      tmp[i] = ((uint8_t *)info.ptr_lin)[(cnt_lin & ~0x03) + i];
     }
     uint32_t wCnt = cnt_wrap;
-    for (; i < 4 && wCnt > 0; i++, wCnt--)
-    {
-      tmp[i] = *(uint8_t*)info.ptr_wrap;
-      info.ptr_wrap = (uint8_t*)info.ptr_wrap + 1;
+    for (; i < 4 && wCnt > 0; i++, wCnt--) {
+      tmp[i] = *(uint8_t *)info.ptr_wrap;
+      info.ptr_wrap = (uint8_t *)info.ptr_wrap + 1;
     }
 
     // Write unaligned buffer
@@ -1266,32 +1198,29 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
 
     // Copy rest of wrapped byte
     if (wCnt)
-        dcd_write_packet_memory(dst, info.ptr_wrap, wCnt);
+      dcd_write_packet_memory(dst, info.ptr_wrap, wCnt);
   }
 #else
-  if((cnt_lin & 0x01) && cnt_wrap)
-  {
+  if ((cnt_lin & 0x01) && cnt_wrap) {
     // Copy first linear part
-    dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin &~0x01);
-    dst += cnt_lin &~0x01;
+    dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin & ~0x01);
+    dst += cnt_lin & ~0x01;
 
     // Copy last linear byte & first wrapped byte
-    uint16_t tmp = ((uint8_t*)info.ptr_lin)[cnt_lin - 1] | ((uint16_t)(((uint8_t*)info.ptr_wrap)[0]) << 8U);
+    uint16_t tmp = ((uint8_t *)info.ptr_lin)[cnt_lin - 1] | ((uint16_t)(((uint8_t *)info.ptr_wrap)[0]) << 8U);
     dcd_write_packet_memory(dst, &tmp, 2);
     dst += 2;
 
     // Copy rest of wrapped byte
-    dcd_write_packet_memory(dst, ((uint8_t*)info.ptr_wrap) + 1, cnt_wrap - 1);
+    dcd_write_packet_memory(dst, ((uint8_t *)info.ptr_wrap) + 1, cnt_wrap - 1);
   }
 #endif
-  else
-  {
+  else {
     // Copy linear part
     dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin);
     dst += info.len_lin;
 
-    if(info.len_wrap)
-    {
+    if (info.len_wrap) {
       // Copy wrapped byte
       dcd_write_packet_memory(dst, info.ptr_wrap, cnt_wrap);
     }
@@ -1305,8 +1234,8 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
 #ifdef FSDEV_BUS_32BIT
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
 {
-  uint8_t* dstVal = dst;
-  volatile uint32_t* src32 = (volatile uint32_t*)(USB_PMAADDR + src);
+  uint8_t *dstVal = dst;
+  volatile uint32_t *src32 = (volatile uint32_t *)(USB_PMAADDR + src);
 
   for (uint32_t n = wNBytes / 4; n > 0; --n) {
     tu_unaligned_write32(dstVal, *src32++);
@@ -1314,20 +1243,17 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
   }
 
   wNBytes = wNBytes & 0x03;
-  if (wNBytes)
-  {
+  if (wNBytes) {
     uint32_t rdVal = *src32;
 
     *dstVal = tu_u32_byte0(rdVal);
     wNBytes--;
 
-    if (wNBytes)
-    {
+    if (wNBytes) {
       *++dstVal = tu_u32_byte1(rdVal);
       wNBytes--;
 
-      if (wNBytes)
-      {
+      if (wNBytes) {
         *++dstVal = tu_u32_byte2(rdVal);
       }
     }
@@ -1337,11 +1263,11 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
 }
 #else
 /**
-  * @brief Copy a buffer from packet memory area (PMA) to user memory area.
-  *        Uses byte-access of system memory and 16-bit access of packet memory
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
+ * @brief Copy a buffer from packet memory area (PMA) to user memory area.
+ *        Uses byte-access of system memory and 16-bit access of packet memory
+ * @param   wNBytes no. of bytes to be copied.
+ * @retval None
+ */
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
 {
   uint32_t n = (uint32_t)wNBytes >> 1U;
@@ -1351,18 +1277,16 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
   uint32_t temp;
 
   pdwVal = &pma[FSDEV_PMA_STRIDE * (src >> 1)];
-  uint8_t *dstVal = (uint8_t*)dst;
+  uint8_t *dstVal = (uint8_t *)dst;
 
-  while (n--)
-  {
+  while (n--) {
     temp = *pdwVal;
     pdwVal += FSDEV_PMA_STRIDE;
     *dstVal++ = ((temp >> 0) & 0xFF);
     *dstVal++ = ((temp >> 8) & 0xFF);
   }
 
-  if (wNBytes & 0x01)
-  {
+  if (wNBytes & 0x01) {
     temp = *pdwVal;
     pdwVal += FSDEV_PMA_STRIDE;
     *dstVal++ = ((temp >> 0) & 0xFF);
@@ -1372,31 +1296,29 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t
 #endif
 
 /**
-  * @brief Copy a buffer from user packet memory area (PMA) to FIFO.
-  *        Uses byte-access of system memory and 16-bit access of packet memory
-  * @param   wNBytes no. of bytes to be copied.
-  * @retval None
-  */
-static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes)
+ * @brief Copy a buffer from user packet memory area (PMA) to FIFO.
+ *        Uses byte-access of system memory and 16-bit access of packet memory
+ * @param   wNBytes no. of bytes to be copied.
+ * @retval None
+ */
+static bool dcd_read_packet_memory_ff(tu_fifo_t *ff, uint16_t src, uint16_t wNBytes)
 {
   // Since we copy into a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
   // Check for first linear part
   tu_fifo_buffer_info_t info;
-  tu_fifo_get_write_info(ff, &info);  // We want to read from the FIFO
+  tu_fifo_get_write_info(ff, &info); // We want to read from the FIFO
 
-  uint16_t cnt_lin =  TU_MIN(wNBytes, info.len_lin);
+  uint16_t cnt_lin = TU_MIN(wNBytes, info.len_lin);
   uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
 
-
   // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
   // last lin byte will be combined with wrapped part
   // To ensure PMA is always access aligned (src aligned to 16 or 32 bit)
 #ifdef FSDEV_BUS_32BIT
-  if((cnt_lin & 0x03) && cnt_wrap)
-  {
+  if ((cnt_lin & 0x03) && cnt_wrap) {
     // Copy first linear part
-    dcd_read_packet_memory(info.ptr_lin, src, cnt_lin &~0x03);
-    src += cnt_lin &~0x03;
+    dcd_read_packet_memory(info.ptr_lin, src, cnt_lin & ~0x03);
+    src += cnt_lin & ~0x03;
 
     // Copy last linear bytes & first wrapped bytes
     uint8_t tmp[4];
@@ -1404,15 +1326,13 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
     src += 4;
 
     uint32_t i;
-    for (i = 0; i < (cnt_lin & 0x03); i++)
-    {
-      ((uint8_t*)info.ptr_lin)[(cnt_lin &~0x03) + i] = tmp[i];
+    for (i = 0; i < (cnt_lin & 0x03); i++) {
+      ((uint8_t *)info.ptr_lin)[(cnt_lin & ~0x03) + i] = tmp[i];
     }
     uint32_t wCnt = cnt_wrap;
-    for (; i < 4 && wCnt > 0; i++, wCnt--)
-    {
-      *(uint8_t*)info.ptr_wrap = tmp[i];
-      info.ptr_wrap = (uint8_t*)info.ptr_wrap + 1;
+    for (; i < 4 && wCnt > 0; i++, wCnt--) {
+      *(uint8_t *)info.ptr_wrap = tmp[i];
+      info.ptr_wrap = (uint8_t *)info.ptr_wrap + 1;
     }
 
     // Copy rest of wrapped byte
@@ -1420,32 +1340,29 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
       dcd_read_packet_memory(info.ptr_wrap, src, wCnt);
   }
 #else
-  if((cnt_lin & 0x01) && cnt_wrap)
-  {
+  if ((cnt_lin & 0x01) && cnt_wrap) {
     // Copy first linear part
-    dcd_read_packet_memory(info.ptr_lin, src, cnt_lin &~0x01);
-    src += cnt_lin &~0x01;
+    dcd_read_packet_memory(info.ptr_lin, src, cnt_lin & ~0x01);
+    src += cnt_lin & ~0x01;
 
     // Copy last linear byte & first wrapped byte
     uint8_t tmp[2];
     dcd_read_packet_memory(tmp, src, 2);
     src += 2;
 
-    ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = tmp[0];
-    ((uint8_t*)info.ptr_wrap)[0] = tmp[1];
+    ((uint8_t *)info.ptr_lin)[cnt_lin - 1] = tmp[0];
+    ((uint8_t *)info.ptr_wrap)[0] = tmp[1];
 
     // Copy rest of wrapped byte
-    dcd_read_packet_memory(((uint8_t*)info.ptr_wrap) + 1, src, cnt_wrap - 1);
+    dcd_read_packet_memory(((uint8_t *)info.ptr_wrap) + 1, src, cnt_wrap - 1);
   }
 #endif
-  else
-  {
+  else {
     // Copy linear part
     dcd_read_packet_memory(info.ptr_lin, src, cnt_lin);
     src += cnt_lin;
 
-    if(info.len_wrap)
-    {
+    if (info.len_wrap) {
       // Copy wrapped byte
       dcd_read_packet_memory(info.ptr_wrap, src, cnt_wrap);
     }
-- 
cgit v1.3.1


From 724ef1af8d948dc65815b48564b351eeeb270f77 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 Apr 2024 09:58:43 +0700
Subject: set txfifo empty level to complete and change back fifo tx to normal
 size

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 69d96aff0..d01d9645b 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -154,9 +154,11 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
       dwc2->grxfsiz = sz;
     }
   } else {
-    // The fifo-empty interrupt fires when the interrupt is half empty. In order
+    // Note if The TXFELVL is configured as half empty. In order
     // to be able to write a packet at that point, the fifo must be twice the max_size.
-    fifo_size = fifo_size * 2;
+    if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
+      fifo_size *= 2;
+    }
 
     // Check if free space is available
     TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
@@ -596,13 +598,13 @@ void dcd_init(uint8_t rhport) {
   int_mask = dwc2->gotgint;
   dwc2->gotgint |= int_mask;
 
-  // Configure TX FIFO to set the TX FIFO empty interrupt when half-empty
-  dwc2->gahbcfg &= ~GAHBCFG_TXFELVL;
-
   // Required as part of core initialization.
   dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM |
                   GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
 
+  // Configure TX FIFO empty level for interrupt. Default is complete empty
+  dwc2->gahbcfg |= GAHBCFG_TXFELVL;
+
   // Enable global interrupt
   dwc2->gahbcfg |= GAHBCFG_GINT;
 
-- 
cgit v1.3.1


From 1e41b9725a946eb6bbbd5cc96b804dbca0bcf7fa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 Apr 2024 10:13:36 +0700
Subject: remove the usage of TU_BIT() and TU_GENMASK() from tusb_types.h

---
 src/common/tusb_types.h | 31 ++++++++++---------------------
 1 file changed, 10 insertions(+), 21 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 2c5dce723..b571f9b72 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -24,12 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-/** \ingroup group_usb_definitions
- *  \defgroup USBDef_Type USB Types
- *  @{ */
-
-#ifndef _TUSB_TYPES_H_
-#define _TUSB_TYPES_H_
+#ifndef TUSB_TYPES_H_
+#define TUSB_TYPES_H_
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -212,8 +208,8 @@ typedef enum {
 } device_capability_type_t;
 
 enum {
-  TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5),
-  TUSB_DESC_CONFIG_ATT_SELF_POWERED  = TU_BIT(6),
+  TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = 1u << 5,
+  TUSB_DESC_CONFIG_ATT_SELF_POWERED  = 1u << 6,
 };
 
 #define TUSB_DESC_CONFIG_POWER_MA(x)  ((x)/2)
@@ -274,11 +270,11 @@ TU_ATTR_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes.
   uint8_t  bDescriptorType    ; ///< DEVICE Descriptor Type.
-  uint16_t bcdUSB             ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant.
+  uint16_t bcdUSB             ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H).
 
-  uint8_t  bDeviceClass       ; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific.
-  uint8_t  bDeviceSubClass    ; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF.
-  uint8_t  bDeviceProtocol    ; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis.
+  uint8_t  bDeviceClass       ; ///< Class code (assigned by the USB-IF).
+  uint8_t  bDeviceSubClass    ; ///< Subclass code (assigned by the USB-IF).
+  uint8_t  bDeviceProtocol    ; ///< Protocol code (assigned by the USB-IF).
   uint8_t  bMaxPacketSize0    ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64.
 
   uint16_t idVendor           ; ///< Vendor ID (assigned by the USB-IF).
@@ -493,15 +489,10 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t di
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) {
-  return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
+  return tu_le16toh(desc_ep->wMaxPacketSize) & 0x7FF;
 }
 
 #if CFG_TUSB_DEBUG
-TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir) {
-  tu_static const char *str[] = {"out", "in"};
-  return str[dir];
-}
-
 TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) {
   tu_static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
@@ -541,6 +532,4 @@ uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t b
  }
 #endif
 
-#endif /* _TUSB_TYPES_H_ */
-
-/** @} */
+#endif // TUSB_TYPES_H_
-- 
cgit v1.3.1


From 804a73a454f382ef7dd5377e6a564f516196fa5d Mon Sep 17 00:00:00 2001
From: Luke A <arntsonl@gmail.com>
Date: Mon, 14 Aug 2023 21:58:20 -0400
Subject: Adding tuh_hid_get_report(...) to hid_host.h

This allows USB host functionality to call HID_REQ_CONTROL_GET_REPORT on the IN Endpoint, and read the report buffer in the callback.
---
 src/class/hid/hid_host.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
 src/class/hid/hid_host.h |  8 ++++++++
 2 files changed, 52 insertions(+)

(limited to 'src')

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 621fb2a55..115a8a4df 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -222,6 +222,50 @@ bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol) {
   return _hidh_set_protocol(daddr, p_hid->itf_num, protocol, set_protocol_complete, 0);
 }
 
+static void get_report_complete(tuh_xfer_t* xfer) {
+  TU_LOG_DRV("HID Get Report complete\r\n");
+
+  if (tuh_hid_get_report_complete_cb) {
+    uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+    uint8_t const idx = tuh_hid_itf_get_index(xfer->daddr, itf_num);
+
+    uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
+    uint8_t const report_id = tu_u16_low(xfer->setup->wValue);
+
+    tuh_hid_get_report_complete_cb(xfer->daddr, idx, report_id, report_type,
+                                   (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
+  }
+}
+
+bool tuh_hid_get_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len) {
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+  TU_LOG_DRV("HID Get Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
+
+  tusb_control_request_t const request = {
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
+      },
+      .bRequest = HID_REQ_CONTROL_GET_REPORT,
+      .wValue   = tu_htole16(tu_u16(report_type, report_id)),
+      .wIndex   = tu_htole16((uint16_t) p_hid->itf_num),
+      .wLength  = len
+  };
+
+  tuh_xfer_t xfer = {
+      .daddr       = daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = report,
+      .complete_cb = get_report_complete,
+      .user_data   = 0
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
 static void set_report_complete(tuh_xfer_t* xfer) {
   TU_LOG_DRV("HID Set Report complete\r\n");
 
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 0902bf1af..9681c704b 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -105,6 +105,10 @@ void tuh_hid_set_default_protocol(uint8_t protocol);
 // This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE)
 bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol);
 
+// Get Report using control endpoint
+// report_type is either Input, Output or Feature, (value from hid_report_type_t)
+bool tuh_hid_get_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
+
 // Set Report using control endpoint
 // report_type is either Input, Output or Feature, (value from hid_report_type_t)
 bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type,
@@ -153,6 +157,10 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* re
 // Invoked when sent report to device successfully via interrupt endpoint
 TU_ATTR_WEAK void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report, uint16_t len);
 
+// Invoked when Get Report to device via either control endpoint
+// len = 0 indicate there is error in the transfer e.g stalled response
+TU_ATTR_WEAK void tuh_hid_get_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len);
+
 // Invoked when Sent Report to device via either control endpoint
 // len = 0 indicate there is error in the transfer e.g stalled response
 TU_ATTR_WEAK void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len);
-- 
cgit v1.3.1


From a173e6ed138cc6f696ab219913c7cf8107c2e9ed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 Apr 2024 17:02:35 +0700
Subject: revert pr2245

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 9 ---------
 1 file changed, 9 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 24edc30e7..3ec1b70b5 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -266,14 +266,6 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void
   tu_fifo_advance_write_pointer(f, count);
 }
 
-
-static bool wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) {
-  TU_ASSERT(num);
-  while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {}
-  return true;
-}
-
-
 //--------------------------------------------------------------------+
 // Pipe Transfer
 //--------------------------------------------------------------------+
@@ -347,7 +339,6 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
   const unsigned rem  = pipe->remaining;
 
   if (!rem) {
-    wait_pipe_fifo_empty(rusb, num);
     pipe->buf = NULL;
     return true;
   }
-- 
cgit v1.3.1


From fb69d80e70c5a3d89606bb503622837fdf8fae4a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 Apr 2024 18:26:56 +0700
Subject: use for loop instead of__builtin_ctz() which is not portable (e.g
 with ccrx)

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 52 ++++++++++++++--------------------
 1 file changed, 22 insertions(+), 30 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 3ec1b70b5..0d53b7a7b 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -89,39 +89,39 @@ static dcd_data_t _dcd;
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-// Transfer conditions specifiable for each pipe:
+// Transfer conditions specifiable for each pipe for most MCUs
 // - Pipe 0: Control transfer with 64-byte single buffer
-// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
-//   to 2 KB and optional double buffer
-// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and
-//   optional double buffer
-// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer
+// - Pipes 1 and 2: Bulk or ISO
+// - Pipes 3 to 5: Bulk
+// - Pipes 6 to 9: Interrupt
+//
+// Note: for small mcu such as
+// - RA2A1: only pipe 4-7 are available, and no support for ISO
+
 enum {
-  PIPE_1ST_BULK = 3,
-  PIPE_1ST_INTERRUPT = 6,
+  PIPE_LAST_ISO = 2,
+  PIPE_LAST_BULK = 5,
+  PIPE_LAST_INTERRUPT = 9,
   PIPE_COUNT = 10,
 };
 
-static unsigned find_pipe(unsigned xfer)
-{
-  switch (xfer) {
+static unsigned find_pipe(unsigned xfer_type) {
+  switch (xfer_type) {
     case TUSB_XFER_ISOCHRONOUS:
-      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+      for (int i = PIPE_LAST_ISO; i > 0; i--) {
         if (0 == _dcd.pipe[i].ep) return i;
       }
       break;
 
     case TUSB_XFER_BULK:
-      for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) {
-        if (0 == _dcd.pipe[i].ep) return i;
-      }
-      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+      // find backward since only pipe 1, 2 support ISO
+      for (int i = PIPE_LAST_BULK; i > 0; i--) {
         if (0 == _dcd.pipe[i].ep) return i;
       }
       break;
 
     case TUSB_XFER_INTERRUPT:
-      for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) {
+      for(int i = PIPE_LAST_INTERRUPT; i > PIPE_LAST_BULK; i--) {
         if (0 == _dcd.pipe[i].ep) return i;
       }
       break;
@@ -1025,20 +1025,12 @@ void dcd_int_handler(uint8_t rhport)
     unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     rusb->BRDYSTS = ~s;
-    while (s) {
-#if defined(__CCRX__)
-      static const int Mod37BitPosition[] = {
-        -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
-        7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
-        20, 8, 19, 18
-      };
 
-      const unsigned num = Mod37BitPosition[(-s & s) % 37];
-#else
-      const unsigned num = __builtin_ctz(s);
-#endif
-      process_pipe_brdy(rhport, num);
-      s &= ~TU_BIT(num);
+    for (unsigned pipe = 0; pipe < PIPE_COUNT; ++pipe) {
+      if (tu_bit_test(s, pipe)) {
+        process_pipe_brdy(rhport, pipe);
+        s = tu_bit_clear(s, pipe);
+      }
     }
   }
 }
-- 
cgit v1.3.1


From 241e436d19d5ee400decc0d6a56ed4ab2a21fa46 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 Apr 2024 19:17:23 +0700
Subject: support ra2a1 pipe numbering, fix ra2a1 ek led/button. Though usb not
 enumerated yet, probably due to bsp/clock setup

---
 hw/bsp/ra/boards/ra2a1_ek/board.h      |  4 +-
 hw/bsp/ra/family.c                     |  3 ++
 hw/bsp/ra/vector_data.h                |  3 ++
 src/portable/renesas/rusb2/dcd_rusb2.c | 80 +++++++++++++++-------------------
 4 files changed, 42 insertions(+), 48 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.h b/hw/bsp/ra/boards/ra2a1_ek/board.h
index c132387bc..1c2b666d2 100644
--- a/hw/bsp/ra/boards/ra2a1_ek/board.h
+++ b/hw/bsp/ra/boards/ra2a1_ek/board.h
@@ -31,10 +31,10 @@
 extern "C" {
 #endif
 
-#define LED1          BSP_IO_PORT_01_PIN_06
+#define LED1          BSP_IO_PORT_02_PIN_05
 #define LED_STATE_ON  1
 
-#define SW1                   BSP_IO_PORT_01_PIN_05
+#define SW1                   BSP_IO_PORT_02_PIN_06
 #define BUTTON_STATE_ACTIVE   0
 
 static const ioport_pin_cfg_t board_pin_cfg[] = {
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 16332be17..db8988a36 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -64,8 +64,11 @@ BSP_DONT_REMOVE BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS)
 const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = {
     [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
     [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
+
+#ifndef BSP_MCU_GROUP_RA2A1
     [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
     [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+#endif
 
 #ifdef BOARD_HAS_USB_HIGHSPEED
     [4] = usbhs_interrupt_handler, /* USBHS INT (USBHS interrupt) */
diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h
index ca667faa3..2b3b7d837 100644
--- a/hw/bsp/ra/vector_data.h
+++ b/hw/bsp/ra/vector_data.h
@@ -9,8 +9,11 @@ extern "C" {
 /* ISR prototypes */
 void usbfs_interrupt_handler(void);
 void usbfs_resume_handler(void);
+
+#ifndef BSP_MCU_GROUP_RA2A1
 void usbfs_d0fifo_handler(void);
 void usbfs_d1fifo_handler(void);
+#endif
 
 #ifdef BOARD_HAS_USB_HIGHSPEED
 void usbhs_interrupt_handler(void);
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 0d53b7a7b..0fcf1b688 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -89,6 +89,10 @@ static dcd_data_t _dcd;
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
+enum {
+  PIPE_COUNT = 10,
+};
+
 // Transfer conditions specifiable for each pipe for most MCUs
 // - Pipe 0: Control transfer with 64-byte single buffer
 // - Pipes 1 and 2: Bulk or ISO
@@ -97,44 +101,33 @@ static dcd_data_t _dcd;
 //
 // Note: for small mcu such as
 // - RA2A1: only pipe 4-7 are available, and no support for ISO
-
-enum {
-  PIPE_LAST_ISO = 2,
-  PIPE_LAST_BULK = 5,
-  PIPE_LAST_INTERRUPT = 9,
-  PIPE_COUNT = 10,
-};
-
 static unsigned find_pipe(unsigned xfer_type) {
-  switch (xfer_type) {
-    case TUSB_XFER_ISOCHRONOUS:
-      for (int i = PIPE_LAST_ISO; i > 0; i--) {
-        if (0 == _dcd.pipe[i].ep) return i;
-      }
-      break;
-
-    case TUSB_XFER_BULK:
-      // find backward since only pipe 1, 2 support ISO
-      for (int i = PIPE_LAST_BULK; i > 0; i--) {
-        if (0 == _dcd.pipe[i].ep) return i;
-      }
-      break;
-
-    case TUSB_XFER_INTERRUPT:
-      for(int i = PIPE_LAST_INTERRUPT; i > PIPE_LAST_BULK; i--) {
-        if (0 == _dcd.pipe[i].ep) return i;
-      }
-      break;
+  #if defined(BSP_MCU_GROUP_RA2A1)
+  const uint8_t pipe_idx_arr[4][2] = {
+      { 0, 0 }, // Control
+      { 0, 0 }, // Isochronous not supported
+      { 4, 5 }, // Bulk
+      { 6, 7 }, // Interrupt
+  };
+  #else
+  const uint8_t pipe_idx_arr[4][2] = {
+      { 0, 0 }, // Control
+      { 1, 2 }, // Isochronous
+      { 1, 5 }, // Bulk
+      { 6, 9 }, // Interrupt
+  };
+  #endif
 
-    default:
-      /* No support for control transfer */
-      break;
+  // find backward since only pipe 1, 2 support ISO
+  const uint8_t* idx = pipe_idx_arr[xfer_type];
+  for (int i = idx[1]; i >= idx[0]; i--) {
+    if (0 == _dcd.pipe[i].ep) return i;
   }
+
   return 0;
 }
 
-static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
-{
+static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num) {
   if (num) {
     return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
   } else {
@@ -142,8 +135,7 @@ static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
   }
 }
 
-static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
-{
+static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num) {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
     tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
@@ -151,8 +143,7 @@ static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
   return tre;
 }
 
-static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
-{
+static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr) {
   rusb2_reg_t *rusb = RUSB2_REG(rhport);
   const unsigned epn = tu_edpt_number(ep_addr);
 
@@ -165,19 +156,16 @@ static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
   }
 }
 
-static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb)
-{
+static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb) {
   return rusb->DCPMAXP_b.MXPS;
 }
 
-static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num)
-{
+static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num) {
   rusb->PIPESEL = num;
   return rusb->PIPEMAXP;
 }
 
-static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
-{
+static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num) {
   while ( rusb->D0FIFOSEL_b.CURPIPE != num ) {}
   while ( !rusb->D0FIFOCTR_b.FRDY ) {}
 }
@@ -1026,10 +1014,10 @@ void dcd_int_handler(uint8_t rhport)
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     rusb->BRDYSTS = ~s;
 
-    for (unsigned pipe = 0; pipe < PIPE_COUNT; ++pipe) {
-      if (tu_bit_test(s, pipe)) {
-        process_pipe_brdy(rhport, pipe);
-        s = tu_bit_clear(s, pipe);
+    for (unsigned p = 0; p < PIPE_COUNT; ++p) {
+      if (tu_bit_test(s, p)) {
+        process_pipe_brdy(rhport, p);
+        s = tu_bit_clear(s, p);
       }
     }
   }
-- 
cgit v1.3.1


From daf1c7303ce390407ab876a5230bc2520cbfd573 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 Apr 2024 20:09:11 +0700
Subject: fix mask typo for brdysts when using pipe9

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 37 +++++++++++++---------------------
 1 file changed, 14 insertions(+), 23 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 0fcf1b688..a65d056cf 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -57,29 +57,22 @@
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
+enum {
+  PIPE_COUNT = 10,
+};
 
-/* Start of definition of packed structs (used by the CCRX toolchain) */
-TU_ATTR_PACKED_BEGIN
-TU_ATTR_BIT_FIELD_ORDER_BEGIN
-
-typedef struct TU_ATTR_PACKED
-{
+typedef struct {
   void      *buf;      /* the start address of a transfer data buffer */
   uint16_t  length;    /* the number of bytes in the buffer */
   uint16_t  remaining; /* the number of bytes remaining in the buffer */
-  struct {
-    uint32_t ep  : 8;  /* an assigned endpoint address */
-    uint32_t ff  : 1;  /* `buf` is TU_FUFO or POD */
-    uint32_t     : 0;
-  };
-} pipe_state_t;
 
-TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
-TU_ATTR_BIT_FIELD_ORDER_END
+  uint8_t ep; /* an assigned endpoint address */
+  uint8_t ff; /* `buf` is TU_FUFO or POD */
+} pipe_state_t;
 
 typedef struct
 {
-  pipe_state_t pipe[10];
+  pipe_state_t pipe[PIPE_COUNT];
   uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
 } dcd_data_t;
 
@@ -89,9 +82,6 @@ static dcd_data_t _dcd;
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-enum {
-  PIPE_COUNT = 10,
-};
 
 // Transfer conditions specifiable for each pipe for most MCUs
 // - Pipe 0: Control transfer with 64-byte single buffer
@@ -119,8 +109,10 @@ static unsigned find_pipe(unsigned xfer_type) {
   #endif
 
   // find backward since only pipe 1, 2 support ISO
-  const uint8_t* idx = pipe_idx_arr[xfer_type];
-  for (int i = idx[1]; i >= idx[0]; i--) {
+  const uint8_t idx_first = pipe_idx_arr[xfer_type][0];
+  const uint8_t idx_last  = pipe_idx_arr[xfer_type][1];
+
+  for (int i = idx_last; i >= idx_first; i--) {
     if (0 == _dcd.pipe[i].ep) return i;
   }
 
@@ -823,7 +815,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   }
 
   rusb->PIPECFG = cfg;
-  rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  rusb->BRDYSTS = 0x3FFu ^ TU_BIT(num);
   rusb->BRDYENB |= TU_BIT(num);
 
   if (dir || (xfer != TUSB_XFER_BULK)) {
@@ -1010,14 +1002,13 @@ void dcd_int_handler(uint8_t rhport)
   // Buffer ready
   if ( is0 & RUSB2_INTSTS0_BRDY_Msk ) {
     const unsigned m = rusb->BRDYENB;
-    unsigned s = rusb->BRDYSTS & m;
+    const unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     rusb->BRDYSTS = ~s;
 
     for (unsigned p = 0; p < PIPE_COUNT; ++p) {
       if (tu_bit_test(s, p)) {
         process_pipe_brdy(rhport, p);
-        s = tu_bit_clear(s, p);
       }
     }
   }
-- 
cgit v1.3.1


From 03cfe90f3ef44c2f4e46509701dfbad5af9991e5 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Wed, 10 Apr 2024 22:21:53 +0200
Subject: flush fifo in dcd_edpt_close_all()

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 33 +++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index d01d9645b..40e59136d 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -101,6 +101,19 @@ static uint16_t _allocated_fifo_words_tx;     // TX FIFO size in words (IN EPs)
 // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
 static bool _sof_en;
 
+static inline void fifo_flush(uint8_t rhport)
+{
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+  // flush all TX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
+  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+
+  // flush RX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_RXFFLSH;
+  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+}
+
 // Calculate the RX FIFO size according to minimum recommendations from reference manual
 // RxFIFO = (5 * number of control endpoints + 8) +
 //          ((largest USB packet used / 4) + 1 for status information) +
@@ -270,13 +283,7 @@ static void bus_reset(uint8_t rhport) {
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
-  // flush all TX fifo and wait for it cleared
-  dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
-  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
-
-  // flush RX fifo and wait for it cleared
-  dwc2->grstctl = GRSTCTL_RXFFLSH;
-  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+  fifo_flush(rhport);
 
   // 2. Set up interrupt mask
   dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
@@ -584,13 +591,7 @@ void dcd_init(uint8_t rhport) {
   // (non zero-length packet), send STALL back and discard.
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
-  // flush all TX fifo and wait for it cleared
-  dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
-  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
-
-  // flush RX fifo and wait for it cleared
-  dwc2->grstctl = GRSTCTL_RXFFLSH;
-  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+  fifo_flush(rhport);
 
   // Clear all interrupts
   uint32_t int_mask = dwc2->gintsts;
@@ -708,8 +709,12 @@ void dcd_edpt_close_all(uint8_t rhport) {
     xfer_status[n][TUSB_DIR_IN].max_size = 0;
   }
 
+  // reset allocated fifo OUT
+  dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
   // reset allocated fifo IN
   _allocated_fifo_words_tx = 16;
+
+  fifo_flush(rhport);
 }
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
-- 
cgit v1.3.1


From 79cbe93fcff83a5764acd2427af410b896434d5f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 Apr 2024 11:02:54 +0700
Subject: separate flush tx/rx fifo

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 36 +++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 40e59136d..830a1ccd0 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -101,19 +101,6 @@ static uint16_t _allocated_fifo_words_tx;     // TX FIFO size in words (IN EPs)
 // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
 static bool _sof_en;
 
-static inline void fifo_flush(uint8_t rhport)
-{
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
-  // flush all TX fifo and wait for it cleared
-  dwc2->grstctl = GRSTCTL_TXFFLSH | (0x10u << GRSTCTL_TXFNUM_Pos);
-  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
-
-  // flush RX fifo and wait for it cleared
-  dwc2->grstctl = GRSTCTL_RXFFLSH;
-  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
-}
-
 // Calculate the RX FIFO size according to minimum recommendations from reference manual
 // RxFIFO = (5 * number of control endpoints + 8) +
 //          ((largest USB packet used / 4) + 1 for status information) +
@@ -125,6 +112,17 @@ static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
   return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
+  // flush TX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos);
+  while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
+}
+TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_rx(dwc2_regs_t* dwc2) {
+  // flush RX fifo and wait for it cleared
+  dwc2->grstctl = GRSTCTL_RXFFLSH;
+  while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
+}
+
 static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
@@ -238,8 +236,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
-    while ((dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0) {}
+    fifo_flush_tx(dwc2, epnum);
   } else {
     dwc2_epout_t* epout = dwc2->epout;
 
@@ -283,7 +280,8 @@ static void bus_reset(uint8_t rhport) {
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
-  fifo_flush(rhport);
+  fifo_flush_tx(dwc2, 0x10); // all tx fifo
+  fifo_flush_rx(dwc2);
 
   // 2. Set up interrupt mask
   dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
@@ -591,7 +589,8 @@ void dcd_init(uint8_t rhport) {
   // (non zero-length packet), send STALL back and discard.
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
-  fifo_flush(rhport);
+  fifo_flush_tx(dwc2, 0x10); // all tx fifo
+  fifo_flush_rx(dwc2);
 
   // Clear all interrupts
   uint32_t int_mask = dwc2->gintsts;
@@ -714,7 +713,8 @@ void dcd_edpt_close_all(uint8_t rhport) {
   // reset allocated fifo IN
   _allocated_fifo_words_tx = 16;
 
-  fifo_flush(rhport);
+  fifo_flush_tx(dwc2, 0x10); // all tx fifo
+  fifo_flush_rx(dwc2);
 }
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
-- 
cgit v1.3.1


From b992b6d7a6f90cd96f7d53383755dc17e393f00e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 Apr 2024 12:06:13 +0700
Subject: apply find_pipe() and forloop for hcd

---
 src/portable/renesas/rusb2/dcd_rusb2.c |  1 -
 src/portable/renesas/rusb2/hcd_rusb2.c | 75 +++++++++++++---------------------
 2 files changed, 29 insertions(+), 47 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index a65d056cf..f9523191a 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -1005,7 +1005,6 @@ void dcd_int_handler(uint8_t rhport)
     const unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     rusb->BRDYSTS = ~s;
-
     for (unsigned p = 0; p < PIPE_COUNT; ++p) {
       if (tu_bit_test(s, p)) {
         process_pipe_brdy(rhport, p);
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index bf95be707..1356b696f 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -45,6 +45,9 @@
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
+enum {
+  PIPE_COUNT = 10,
+};
 
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
@@ -75,7 +78,7 @@ TU_ATTR_BIT_FIELD_ORDER_END
 typedef struct
 {
   bool         need_reset; /* The device has not been reset after connection. */
-  pipe_state_t pipe[10];
+  pipe_state_t pipe[PIPE_COUNT];
   uint8_t ep[4][2][15];   /* a lookup table for a pipe index from an endpoint address */
   uint8_t      ctl_mps[5]; /* EP0 max packet size for each device */
 } hcd_data_t;
@@ -86,46 +89,30 @@ typedef struct
 static hcd_data_t _hcd;
 
 // TODO merged with DCD
-// Transfer conditions specifiable for each pipe:
+// Transfer conditions specifiable for each pipe for most MCUs
 // - Pipe 0: Control transfer with 64-byte single buffer
-// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
-//   to 2 KB and optional double buffer
-// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and
-//   optional double buffer
-// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer
-enum {
-  PIPE_1ST_BULK = 3,
-  PIPE_1ST_INTERRUPT = 6,
-  PIPE_COUNT = 10,
-};
-
-static unsigned find_pipe(unsigned xfer) {
-  switch ( xfer ) {
-    case TUSB_XFER_ISOCHRONOUS:
-      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
-        if ( 0 == _hcd.pipe[i].ep ) return i;
-      }
-      break;
-
-    case TUSB_XFER_BULK:
-      for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) {
-        if ( 0 == _hcd.pipe[i].ep ) return i;
-      }
-      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
-        if ( 0 == _hcd.pipe[i].ep ) return i;
-      }
-      break;
+// - Pipes 1 and 2: Bulk or ISO
+// - Pipes 3 to 5: Bulk
+// - Pipes 6 to 9: Interrupt
+//
+// Note: for small mcu such as
+// - RA2A1: only pipe 4-7 are available, and no support for ISO
+static unsigned find_pipe(unsigned xfer_type) {
+  const uint8_t pipe_idx_arr[4][2] = {
+      { 0, 0 }, // Control
+      { 1, 2 }, // Isochronous
+      { 1, 5 }, // Bulk
+      { 6, 9 }, // Interrupt
+  };
 
-    case TUSB_XFER_INTERRUPT:
-      for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) {
-        if ( 0 == _hcd.pipe[i].ep ) return i;
-      }
-      break;
+  // find backward since only pipe 1, 2 support ISO
+  const uint8_t idx_first = pipe_idx_arr[xfer_type][0];
+  const uint8_t idx_last  = pipe_idx_arr[xfer_type][1];
 
-    default:
-      /* No support for control transfer */
-      break;
+  for (int i = idx_last; i >= idx_first; i--) {
+    if (0 == _hcd.pipe[i].ep) return i;
   }
+
   return 0;
 }
 
@@ -718,7 +705,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   }
 
   rusb->PIPECFG = cfg;
-  rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  rusb->BRDYSTS = 0x3FFu ^ TU_BIT(num);
   rusb->NRDYENB |= TU_BIT(num);
   rusb->BRDYENB |= TU_BIT(num);
 
@@ -846,14 +833,10 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     rusb->BRDYSTS = ~s;
-    while (s) {
-#if defined(__CCRX__)
-      const unsigned num = Mod37BitPosition[(-s & s) % 37];
-#else
-      const unsigned num = __builtin_ctz(s);
-#endif
-      process_pipe_brdy(rhport, num);
-      s &= ~TU_BIT(num);
+    for (unsigned p = 0; p < PIPE_COUNT; ++p) {
+      if (tu_bit_test(s, p)) {
+        process_pipe_brdy(rhport, p);
+      }
     }
   }
 }
-- 
cgit v1.3.1


From 535571c3d278efbbeebdc531c36ce1f492ea4d05 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 Apr 2024 19:25:02 +0700
Subject: - remove redundant call of pcd_set_ep_rx_cnt() - minor code format

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 155 +++++++++++++-------------
 1 file changed, 75 insertions(+), 80 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index c11a8c625..56c9bc84b 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -216,22 +216,19 @@ void dcd_init(uint8_t rhport)
   /* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL.
    * Here, the RM is followed. */
 
-  for (uint32_t i = 0; i < 200; i++) // should be a few us
-  {
+  for (uint32_t i = 0; i < 200; i++) { // should be a few us
     asm("NOP");
   }
   // Perform USB peripheral reset
   USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
-  for (uint32_t i = 0; i < 200; i++) // should be a few us
-  {
+  for (uint32_t i = 0; i < 200; i++) { // should be a few us
     asm("NOP");
   }
 
   USB->CNTR &= ~USB_CNTR_PDWN;
 
   // Wait startup time, for F042 and F070, this is <= 1 us.
-  for (uint32_t i = 0; i < 200; i++) // should be a few us
-  {
+  for (uint32_t i = 0; i < 200; i++) { // should be a few us
     asm("NOP");
   }
   USB->CNTR = 0; // Enable USB
@@ -251,8 +248,9 @@ void dcd_init(uint8_t rhport)
   dcd_handle_bus_reset();
 
   // Enable pull-up if supported
-  if (dcd_connect)
+  if (dcd_connect) {
     dcd_connect(rhport);
+  }
 }
 
 // Define only on MCU with internal pull-up. BSP can define on MCU without internal PU.
@@ -441,21 +439,23 @@ void dcd_remote_wakeup(uint8_t rhport)
   remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
 }
 
-static const tusb_desc_endpoint_t ep0OUT_desc = {.bLength = sizeof(tusb_desc_endpoint_t),
-                                                 .bDescriptorType = TUSB_DESC_ENDPOINT,
-
-                                                 .bEndpointAddress = 0x00,
-                                                 .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
-                                                 .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
-                                                 .bInterval = 0};
-
-static const tusb_desc_endpoint_t ep0IN_desc = {.bLength = sizeof(tusb_desc_endpoint_t),
-                                                .bDescriptorType = TUSB_DESC_ENDPOINT,
-
-                                                .bEndpointAddress = 0x80,
-                                                .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
-                                                .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
-                                                .bInterval = 0};
+static const tusb_desc_endpoint_t ep0OUT_desc = {
+    .bLength = sizeof(tusb_desc_endpoint_t),
+    .bDescriptorType = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0x00,
+    .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
+    .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
+    .bInterval = 0
+};
+
+static const tusb_desc_endpoint_t ep0IN_desc = {
+    .bLength = sizeof(tusb_desc_endpoint_t),
+    .bDescriptorType = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0x80,
+    .bmAttributes = {.xfer = TUSB_XFER_CONTROL},
+    .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
+    .bInterval = 0
+};
 
 static void dcd_handle_bus_reset(void)
 {
@@ -503,8 +503,9 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
   xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
 
   /* Ignore spurious int */
-  if (xfer->in_complete)
+  if (xfer->in_complete) {
     return;
+  }
   xfer->in_complete = true;
 
   if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
@@ -515,11 +516,9 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
     }
   }
 
-  if ((xfer->total_len != xfer->queued_len)) /* TX not complete */
-  {
+  if ((xfer->total_len != xfer->queued_len)) {
     dcd_transmit_packet(xfer, EPindex);
-  } else /* TX Complete */
-  {
+  } else {
     dcd_event_xfer_complete(0, ep_addr, xfer->total_len, XFER_RESULT_SUCCESS, true);
   }
 }
@@ -561,12 +560,11 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
     return;
   }
 
-  if ((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
-  {
+  if ((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) {
+    /* Setup packet */
     uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex);
-    /* Get SETUP Packet*/
-    if (count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
-    {
+    // Setup packet should always be 8 bytes. If not, ignore it, and try again.
+    if (count == 8) {
       // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
       pcd_set_ep_rx_status(USB, 0u, USB_EP_RX_NAK);
       pcd_set_ep_tx_status(USB, 0u, USB_EP_TX_NAK);
@@ -615,16 +613,14 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
     }
 
     if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
-      /* RX COMPLETE */
+      // all bytes received or short packet
       dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-      // Though the host could still send, we don't know.
-      // Does the bulk pipe need to be reset to valid to allow for a ZLP?
     } else {
       /* Set endpoint active again for receiving more data.
        * Note that isochronous endpoints stay active always */
-      if (!((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
+      if ((wEPRegVal & USB_EP_TYPE_MASK) != USB_EP_ISOCHRONOUS) {
         uint16_t remaining = xfer->total_len - xfer->queued_len;
-        uint16_t cnt = remaining >= xfer->max_packet_size ? xfer->max_packet_size : remaining;
+        uint16_t cnt = tu_min16(remaining, xfer->max_packet_size);
         pcd_set_ep_rx_cnt(USB, EPindex, cnt);
         pcd_set_ep_rx_cnt(USB, EPindex, remaining);
       }
@@ -734,7 +730,9 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *req
 {
   (void)rhport;
 
-  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_ADDRESS) {
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS) {
     uint8_t const dev_addr = (uint8_t)request->wValue;
 
     // Setting new address after the whole request is complete
@@ -781,13 +779,16 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 
   for (uint8_t i = 0; i < STFSDEV_EP_COUNT; i++) {
     // Check if already allocated
-    if (ep_alloc_status[i].allocated[dir] && ep_alloc_status[i].ep_type == ep_type && ep_alloc_status[i].ep_num == epnum) {
+    if (ep_alloc_status[i].allocated[dir] &&
+        ep_alloc_status[i].ep_type == ep_type &&
+        ep_alloc_status[i].ep_num == epnum) {
       return i;
     }
 
     // If EP of current direction is not allocated
     // Except for ISO endpoint, both direction should be free
-    if (!ep_alloc_status[i].allocated[dir] && (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) {
+    if (!ep_alloc_status[i].allocated[dir] &&
+        (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) {
       // Check if EP number is the same
       if (ep_alloc_status[i].ep_num == 0xFF || ep_alloc_status[i].ep_num == epnum) {
         // One EP pair has to be the same type
@@ -812,8 +813,9 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
 {
   (void)rhport;
-  uint8_t const ep_idx = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
-  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_addr = p_endpoint_desc->bEndpointAddress;
+  uint8_t const ep_idx = dcd_ep_alloc(ep_addr, p_endpoint_desc->bmAttributes.xfer);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
   const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
   uint16_t pma_addr;
@@ -822,28 +824,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   TU_ASSERT(ep_idx < STFSDEV_EP_COUNT);
   TU_ASSERT(buffer_size <= 64);
 
-  // ISO endpoint should use alloc / active functions
-  TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-
   // Set type
   switch (p_endpoint_desc->bmAttributes.xfer) {
-  case TUSB_XFER_CONTROL:
-    wType = USB_EP_CONTROL;
-    break;
-  case TUSB_XFER_BULK:
-    wType = USB_EP_CONTROL;
-    break;
-
-  case TUSB_XFER_INTERRUPT:
-    wType = USB_EP_INTERRUPT;
-    break;
-
-  default:
-    TU_ASSERT(false);
+    case TUSB_XFER_CONTROL:
+      wType = USB_EP_CONTROL;
+      break;
+    case TUSB_XFER_BULK:
+      wType = USB_EP_CONTROL;
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      wType = USB_EP_INTERRUPT;
+      break;
+
+    default:
+      // Note: ISO endpoint should use alloc / active functions
+      TU_ASSERT(false);
   }
 
   pcd_set_eptype(USB, ep_idx, wType);
-  pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
+  pcd_set_ep_address(USB, ep_idx, tu_edpt_number(ep_addr));
 
   /* Create a packet memory buffer area. */
   pma_addr = dcd_pma_alloc(buffer_size, false);
@@ -852,16 +852,14 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
     pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
     pcd_clear_tx_dtog(USB, ep_idx);
-  }
-
-  if (dir == TUSB_DIR_OUT) {
+  } else {
     pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
     pcd_clear_rx_dtog(USB, ep_idx);
   }
 
-  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
-  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx = ep_idx;
+  xfer_ctl_ptr(ep_addr)->max_packet_size = packet_size;
+  xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
 
   return true;
 }
@@ -898,8 +896,6 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
 {
   (void)rhport;
 
-  TU_ASSERT(largest_packet_size < 1024);
-
   uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
   const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
 
@@ -925,14 +921,15 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
 bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
 {
   (void)rhport;
-  uint8_t const ep_idx = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx;
-  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_addr = p_endpoint_desc->bEndpointAddress;
+  uint8_t const ep_idx = xfer_ctl_ptr(ep_addr)->ep_idx;
+  uint8_t const dir = tu_edpt_dir(ep_addr);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
 
   pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
   pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
 
-  pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
+  pcd_set_ep_address(USB, ep_idx, tu_edpt_number(ep_addr));
 
   pcd_clear_tx_dtog(USB, ep_idx);
   pcd_clear_rx_dtog(USB, ep_idx);
@@ -943,7 +940,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoin
     pcd_tx_dtog(USB, ep_idx);
   }
 
-  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
+  xfer_ctl_ptr(ep_addr)->max_packet_size = packet_size;
 
   return true;
 }
@@ -953,9 +950,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoin
 static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix)
 {
   uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
-
-  if (len > xfer->max_packet_size) // max packet size for FS transfer
-  {
+  if (len > xfer->max_packet_size) {
     len = xfer->max_packet_size;
   }
 
@@ -996,14 +991,16 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
   uint8_t const ep_idx = xfer->ep_idx;
   uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if (dir == TUSB_DIR_OUT) {
+  if (dir == TUSB_DIR_IN) {
+    dcd_transmit_packet(xfer, ep_idx);
+  } else {
     // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
     // buffer for the control endpoint.
     if (ep_idx == 0 && xfer->buffer == NULL) {
       xfer->buffer = (uint8_t *)_setup_packet;
     }
 
-    uint32_t cnt = xfer->total_len > xfer->max_packet_size ? xfer->max_packet_size : xfer->total_len;
+    uint32_t cnt = (uint32_t ) tu_min16(xfer->total_len, xfer->max_packet_size);
     uint16_t ep_reg = pcd_get_endpoint(USB, ep_idx);
 
     if ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
@@ -1014,10 +1011,8 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr)
     }
 
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID);
-  } else // IN
-  {
-    dcd_transmit_packet(xfer, ep_idx);
   }
+
   return true;
 }
 
@@ -1052,9 +1047,9 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   uint8_t const ep_idx = xfer->ep_idx;
   uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if (dir == TUSB_DIR_IN) { // IN
+  if (dir == TUSB_DIR_IN) {
     pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_STALL);
-  } else { // OUT
+  } else {
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_STALL);
   }
 }
-- 
cgit v1.3.1


From 0f775630c7468b804fad7e3350b37430b6fb0a2d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 Apr 2024 20:53:44 +0700
Subject: rename, invert logic for iso_in_sending. Also limit its usage to ISO
 endpoint

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 56c9bc84b..493e634c7 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -152,7 +152,7 @@ typedef struct {
   uint16_t queued_len;
   uint16_t max_packet_size;
   uint8_t ep_idx;   // index for USB_EPnR register
-  bool in_complete; // Workaround for ISO IN EP doesn't have interrupt mask
+  bool iso_in_sending; // Workaround for ISO IN EP doesn't have interrupt mask
 } xfer_ctl_t;
 
 // EP allocator
@@ -502,13 +502,15 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
 
   xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
 
-  /* Ignore spurious int */
-  if (xfer->in_complete) {
-    return;
-  }
-  xfer->in_complete = true;
-
   if ((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
+    // Ignore spurious interrupts that we don't schedule
+    // host can send IN token while there is no data to send, since ISO does not have NAK
+    // this will result to zero length packet --> trigger interrupt (which cannot be masked)
+    if (!xfer->iso_in_sending) {
+      return;
+    }
+    xfer->iso_in_sending = false;
+
     if (wEPRegVal & USB_EP_DTOG_TX) {
       pcd_set_ep_tx_dbuf0_cnt(USB, EPindex, 0);
     } else {
@@ -955,9 +957,10 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix)
   }
 
   uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix);
+  bool const is_iso = (ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS;
   uint16_t addr_ptr;
 
-  if ((ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) {
+  if (is_iso) {
     if (ep_reg & USB_EP_DTOG_TX) {
       addr_ptr = pcd_get_ep_dbuf1_address(USB, ep_ix);
       pcd_set_ep_tx_dbuf1_cnt(USB, ep_ix, len);
@@ -979,7 +982,9 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix)
 
   dcd_int_disable(0);
   pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
-  xfer->in_complete = false;
+  if (is_iso) {
+    xfer->iso_in_sending = true;
+  }
   dcd_int_enable(0);
 }
 
-- 
cgit v1.3.1


From 0ce2452a088bd7f1397a8f55d736e4e0100cb32f Mon Sep 17 00:00:00 2001
From: Clifroy Henry <clhenry@users.noreply.github.com>
Date: Fri, 30 Dec 2022 19:21:53 -0500
Subject: Add non-bus-powered MSP430 re-enumeration support.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 80 ++++++++++++++++++++++++++---
 1 file changed, 74 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index b4dfda575..60aa23b98 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -131,11 +131,17 @@ void dcd_init (uint8_t rhport)
 
   USBVECINT = 0;
 
-  // Enable reset and wait for it before continuing.
-  USBIE |= RSTRIE;
-
-  // Enable pullup.
-  USBCNF |= PUR_EN;
+  if(USBPWRCTL & USBBGVBV)  // Bus power detected?
+  {
+    USBPWRCTL |= VBOFFIE;   // Enable bus-power-removed interrupt.
+    USBIE |= RSTRIE;        // Enable reset and wait for it before continuing.
+    USBCNF |= PUR_EN;       // Enable pullup.
+  }
+  else
+  {
+    USBPWRCTL |= VBONIE;    // Enable bus-power-applied interrupt.
+    USBCNF &= ~USB_EN;      // Disable USB module until bus power is detected.
+  }
 
   USBKEYPID = 0;
 }
@@ -618,6 +624,48 @@ static void handle_setup_packet(void)
   dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true);
 }
 
+static void handle_bus_power_event(void *param)
+{
+  (void) param;
+
+  osal_task_delay(2);                 // Bus power settling delay.
+
+  USBKEYPID = USBKEY;
+
+  if(USBPWRCTL & USBBGVBV)            // Event caused by application of bus power.
+  {
+    USBPWRCTL |= VBOFFIE;             // Enable bus-power-removed interrupt.
+    USBPLLDIVB = USBPLLDIVB;          // For some reason the PLL will *NOT* lock unless the divider
+                                      // register is re-written. The assumption here is that this
+                                      // register was already properly configured during board-level
+                                      // initialization.
+    USBPLLCTL |= (UPLLEN | UPFDEN);   // Enable the PLL.
+
+    uint16_t attempts = 0;
+
+    do                                // Poll the PLL to check for a successful lock.
+    {
+      USBPLLIR = 0;
+      osal_task_delay(1);
+      attempts++;
+    } while ((attempts < 10) && (USBPLLIR != 0));
+
+    if(!USBPLLIR)                     // A successful lock is indicated by all PLL-related interrupt
+    {                                 // flags being cleared.
+      dcd_init(0);                    // Re-initialize the USB module. 
+    }
+  }
+  else                                // Event caused by removal of bus power.
+  {
+    USBPWRCTL |= VBONIE;              // Enable bus-power-applied interrupt.
+    USBPLLCTL &= ~(UPLLEN | UPFDEN);  // Disable the PLL.
+    USBCNF = 0;                       // Disable the USB module.
+    dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, false);
+  }
+
+  USBKEYPID = 0;
+}
+
 void dcd_int_handler(uint8_t rhport)
 {
   (void) rhport;
@@ -646,11 +694,32 @@ void dcd_int_handler(uint8_t rhport)
 
   switch(curr_vector)
   {
+    case USBVECINT_NONE:
+      break;
+
     case USBVECINT_RSTR:
       bus_reset();
       dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
       break;
 
+    case USBVECINT_PWR_VBUSOn:
+    case USBVECINT_PWR_VBUSOff:
+      USBKEYPID = USBKEY;
+      // Prevent (possibly) unstable power from generating spurious interrupts.
+      USBPWRCTL &= ~(VBONIE | VBOFFIE);
+      USBKEYPID = 0;
+
+      {
+        dcd_event_t event;
+
+        event.rhport = 0;
+        event.event_id = USBD_EVENT_FUNC_CALL;
+        event.func_call.func = handle_bus_power_event;
+
+        dcd_event_handler(&event, true);
+      }
+      break;
+
     // Clear the (hardware-enforced) NAK on EP 0 after a SETUP packet
     // is received. At this point, even though the hardware is no longer
     // forcing NAKs, the EP0 NAK bits should still be set to avoid
@@ -710,7 +779,6 @@ void dcd_int_handler(uint8_t rhport)
 
     default:
       while(true);
-      break;
   }
 
 }
-- 
cgit v1.3.1


From 87905d30ab8c94999bd69d0ae32f91ebdfef39d3 Mon Sep 17 00:00:00 2001
From: Clifroy Henry <clhenry@users.noreply.github.com>
Date: Tue, 3 Jan 2023 10:33:49 -0500
Subject: Increase bus powe stabilization delay.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index 60aa23b98..c1bef86fa 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -628,7 +628,7 @@ static void handle_bus_power_event(void *param)
 {
   (void) param;
 
-  osal_task_delay(2);                 // Bus power settling delay.
+  osal_task_delay(5);                 // Bus power settling delay.
 
   USBKEYPID = USBKEY;
 
-- 
cgit v1.3.1


From 5a9b3eab6f3aa5e9fc71b902bfdbfef1acb29b44 Mon Sep 17 00:00:00 2001
From: Clifroy Henry <clhenry@users.noreply.github.com>
Date: Tue, 3 Jan 2023 11:58:22 -0500
Subject: Resolve erroneous data on enumeration.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index c1bef86fa..46b7d6458 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -616,11 +616,20 @@ static void handle_setup_packet(void)
     _setup_packet[i] = setup_buf[i];
   }
 
-  // Clearing SETUPIFG by reading USBVECINT does not set NAK, so now that we
-  // have a SETUP packet, force NAKs until tinyusb can handle the SETUP
-  // packet and prepare for a new xfer.
+  // Force NAKs until tinyusb can handle the SETUP packet and prepare
+  // for a new xfer.
   USBIEPCNT_0 |= NAK;
   USBOEPCNT_0 |= NAK;
+
+  // Clear SETUPIFG to avoid handling in the USBVECINT switch statement.
+  // When handled there the NAKs applied to the endpoints above are
+  // cleared by hardware and the host will receive stale/duplicate data.
+  //
+  // Excerpt from MSP430x5xx and MSP430x6xx Family User's Guide:
+  //
+  // "...the SETUPIFG is cleared upon reading USBIV. In addition, the NAK on
+  // input endpoint 0 and output endpoint 0 is also cleared."
+  USBIFG &= ~SETUPIFG;
   dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true);
 }
 
-- 
cgit v1.3.1


From b8b22b929e1bbbbae7c7337972129ae6f7192bc6 Mon Sep 17 00:00:00 2001
From: Clifroy Henry <clhenry@users.noreply.github.com>
Date: Tue, 3 Jan 2023 15:56:14 -0500
Subject: Allow re-enumeration on host power cycle.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index 46b7d6458..a0d9b3ea5 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -94,7 +94,12 @@ static void bus_reset(void)
   USBOEPCNT_0 &= ~NAK;
   USBIEPCNT_0 &= ~NAK;
 
-  USBCTL |= FEN; // Enable responding to packets.
+  // Disable (subsequent) bus reset events from causing a functional
+  // reset of the USB module.
+  USBCTL &= ~FRSTE;
+
+  // Enable responding to packets.
+  USBCTL |= FEN;
 
   // Dedicated buffers in hardware for SETUP and EP0, no setup needed.
   // Now safe to respond to SETUP packets.
@@ -334,6 +339,10 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   if(epnum == 0)
   {
+    // Enables a bus reset to cause a functional reset of the USB
+    // module.
+    USBCTL |= FRSTE;
+
     if(dir == TUSB_DIR_OUT)
     {
       // Interrupt will notify us when data was received.
-- 
cgit v1.3.1


From a3286932add7c8142b94160522f19e5544e27c0a Mon Sep 17 00:00:00 2001
From: Clifroy Henry <clhenry@users.noreply.github.com>
Date: Sat, 8 Jul 2023 17:21:19 -0400
Subject: Correctly implementing recommended workarounds for erratas USB4 and
 USB10.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 40 ++++++++++++++++++++++-------
 1 file changed, 31 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index a0d9b3ea5..25c2fb301 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -94,10 +94,6 @@ static void bus_reset(void)
   USBOEPCNT_0 &= ~NAK;
   USBIEPCNT_0 &= ~NAK;
 
-  // Disable (subsequent) bus reset events from causing a functional
-  // reset of the USB module.
-  USBCTL &= ~FRSTE;
-
   // Enable responding to packets.
   USBCTL |= FEN;
 
@@ -108,6 +104,28 @@ static void bus_reset(void)
   USBKEYPID = 0;
 }
 
+// Controls reset behavior of the USB module on receipt of a bus reset event.
+// - enable: When true, bus reset events will cause a reset the USB module.
+static void enable_functional_reset(const bool enable)
+{
+  // Check whether or not the USB configuration registers were
+  // locked prior to this function being called so that, if
+  // necessary, the lock state can be restored on exit.
+  bool unlocked = (USBKEYPID == 0xA528) ? true : false;
+
+  if(!unlocked) USBKEYPID = USBKEY;
+
+  if(enable)
+  {
+    USBCTL |= FRSTE;
+  }
+  else
+  {
+    USBCTL &= ~FRSTE;
+  }
+
+  if(!unlocked) USBKEYPID = 0;
+}
 
 /*------------------------------------------------------------------*/
 /* Controller API
@@ -339,10 +357,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   if(epnum == 0)
   {
-    // Enables a bus reset to cause a functional reset of the USB
-    // module.
-    USBCTL |= FRSTE;
-
     if(dir == TUSB_DIR_OUT)
     {
       // Interrupt will notify us when data was received.
@@ -638,7 +652,11 @@ static void handle_setup_packet(void)
   //
   // "...the SETUPIFG is cleared upon reading USBIV. In addition, the NAK on
   // input endpoint 0 and output endpoint 0 is also cleared."
+  USBIEPCNF_0 &= ~UBME; // Errata USB10 workaround.
+  USBOEPCNF_0 &= ~UBME; // Errata USB10 workaround.
   USBIFG &= ~SETUPIFG;
+  USBIEPCNF_0 |= UBME;  // Errata USB10 workaround.
+  USBOEPCNF_0 |= UBME;  // Errata USB10 workaround.
   dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true);
 }
 
@@ -661,7 +679,7 @@ static void handle_bus_power_event(void *param)
 
     uint16_t attempts = 0;
 
-    do                                // Poll the PLL to check for a successful lock.
+    do                                // Poll the PLL, checking for a successful lock.
     {
       USBPLLIR = 0;
       osal_task_delay(1);
@@ -694,6 +712,7 @@ void dcd_int_handler(uint8_t rhport)
 
   if(setup_status)
   {
+    enable_functional_reset(true);
     handle_setup_packet();
   }
 
@@ -716,6 +735,7 @@ void dcd_int_handler(uint8_t rhport)
       break;
 
     case USBVECINT_RSTR:
+      enable_functional_reset(false); // Errata USB4 workaround.
       bus_reset();
       dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
       break;
@@ -762,10 +782,12 @@ void dcd_int_handler(uint8_t rhport)
       break;
 
     case USBVECINT_INPUT_ENDPOINT0:
+      enable_functional_reset(true);
       transmit_packet(0);
       break;
 
     case USBVECINT_OUTPUT_ENDPOINT0:
+      enable_functional_reset(true);
       receive_packet(0);
       break;
 
-- 
cgit v1.3.1


From 5d3b0896e1eeb1bd45bcb4f2031c7a571f1a16cb Mon Sep 17 00:00:00 2001
From: Clifroy Henry <clhenry@users.noreply.github.com>
Date: Sat, 8 Jul 2023 17:36:08 -0400
Subject: Removed trailing whitespace.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index 25c2fb301..870cd725d 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -688,7 +688,7 @@ static void handle_bus_power_event(void *param)
 
     if(!USBPLLIR)                     // A successful lock is indicated by all PLL-related interrupt
     {                                 // flags being cleared.
-      dcd_init(0);                    // Re-initialize the USB module. 
+      dcd_init(0);                    // Re-initialize the USB module.
     }
   }
   else                                // Event caused by removal of bus power.
-- 
cgit v1.3.1


From dfef0bc81b1677c2d6bbd148b8a0cea4b64aacec Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Thu, 11 Apr 2024 22:00:25 +0200
Subject: Cleanup

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 5 -----
 1 file changed, 5 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 493e634c7..c38247c38 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -459,13 +459,9 @@ static const tusb_desc_endpoint_t ep0IN_desc = {
 
 static void dcd_handle_bus_reset(void)
 {
-  //__IO uint16_t * const epreg = &(EPREG(0));
   USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
 
   for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) {
-    // Clear all EPREG (or maybe this is automatic? I'm not sure)
-    pcd_set_endpoint(USB, i, 0u);
-
     // Clear EP allocation status
     ep_alloc_status[i].ep_num = 0xFF;
     ep_alloc_status[i].ep_type = 0xFF;
@@ -624,7 +620,6 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
         uint16_t remaining = xfer->total_len - xfer->queued_len;
         uint16_t cnt = tu_min16(remaining, xfer->max_packet_size);
         pcd_set_ep_rx_cnt(USB, EPindex, cnt);
-        pcd_set_ep_rx_cnt(USB, EPindex, remaining);
       }
       pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
     }
-- 
cgit v1.3.1


From 049ceda315cb581eba27c31952f82353bb881520 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Thu, 11 Apr 2024 22:02:44 +0200
Subject: Implement dcd_edpt_close_all()

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index c38247c38..cd6142d3a 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -864,7 +864,19 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
 void dcd_edpt_close_all(uint8_t rhport)
 {
   (void)rhport;
-  // TODO implement dcd_edpt_close_all()
+
+  for (uint32_t i = 1; i < STFSDEV_EP_COUNT; i++) {
+    // Reset endpoint
+    pcd_set_endpoint(USB, i, 0);
+    // Clear EP allocation status
+    ep_alloc_status[i].ep_num = 0xFF;
+    ep_alloc_status[i].ep_type = 0xFF;
+    ep_alloc_status[i].allocated[0] = false;
+    ep_alloc_status[i].allocated[1] = false;
+  }
+
+  // Reset PMA allocation
+  ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT + 2 * CFG_TUD_ENDPOINT0_SIZE;
 }
 
 /**
-- 
cgit v1.3.1


From bf649988ef8ffd39435dddc747f953faf78db471 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Apr 2024 12:06:13 +0700
Subject: add blocking delay for msp430 with max 25mhz

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  4 +-
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c   | 59 ++++++++++++++-------------
 2 files changed, 33 insertions(+), 30 deletions(-)

(limited to 'src')

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 7bf726f3f..bb96b4937 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -544,14 +544,14 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) {
    * - Software should ensure that a small delay is included before accessing the SRAM contents. This delay
    * should be 800 ns in Full Speed mode and 6.4 μs in Low Speed mode
    * - Since H5 can run up to 250Mhz -> 1 cycle = 4ns. Per errata, we need to wait 200 cycles. Though executing code
-   * also takes time, so we'll wait 40 cycles (count = 20).
+   * also takes time, so we'll wait 60 cycles (count = 20).
    * - Since Low Speed mode is not supported/popular, we will ignore it for now.
    *
    * Note: this errata also seems to apply to G0, U5, H5 etc.
    */
   volatile uint32_t cycle_count = 20; // defined as PCD_RX_PMA_CNT in stm32 hal_driver
   while (cycle_count > 0U) {
-    cycle_count--; // each count take 2 cycle (1 cycle for sub, 1 cycle for compare/jump)
+    cycle_count--; // each count take 3 cycles (1 for sub, jump, and compare)
   }
   #endif
 
diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index 870cd725d..8005f5f7b 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -154,14 +154,11 @@ void dcd_init (uint8_t rhport)
 
   USBVECINT = 0;
 
-  if(USBPWRCTL & USBBGVBV)  // Bus power detected?
-  {
+  if(USBPWRCTL & USBBGVBV) {// Bus power detected?
     USBPWRCTL |= VBOFFIE;   // Enable bus-power-removed interrupt.
     USBIE |= RSTRIE;        // Enable reset and wait for it before continuing.
     USBCNF |= PUR_EN;       // Enable pullup.
-  }
-  else
-  {
+  } else {
     USBPWRCTL |= VBONIE;    // Enable bus-power-applied interrupt.
     USBCNF &= ~USB_EN;      // Disable USB module until bus power is detected.
   }
@@ -639,8 +636,7 @@ static void handle_setup_packet(void)
     _setup_packet[i] = setup_buf[i];
   }
 
-  // Force NAKs until tinyusb can handle the SETUP packet and prepare
-  // for a new xfer.
+  // Force NAKs until tinyusb can handle the SETUP packet and prepare for a new xfer.
   USBIEPCNT_0 |= NAK;
   USBOEPCNT_0 |= NAK;
 
@@ -660,16 +656,28 @@ static void handle_setup_packet(void)
   dcd_event_setup_received(0, (uint8_t*) &_setup_packet[0], true);
 }
 
-static void handle_bus_power_event(void *param)
-{
+#if CFG_TUSB_OS == OPT_OS_NONE
+TU_ATTR_ALWAYS_INLINE static inline void tu_delay(uint32_t ms) {
+  // msp430 can run up to 25Mhz -> 40ns per cycle. 1 ms = 25000 cycles
+  // each loop need 4 cycle: 1 sub, 1 cmp, 1 jump, 1 nop
+  volatile uint32_t cycles = (25000 * ms) >> 2;
+  while (cycles > 0) {
+    cycles--;
+    asm("nop");
+  }
+}
+#else
+#define tu_delay(ms) osal_task_delay(ms)
+#endif
+
+static void handle_bus_power_event(void *param) {
   (void) param;
 
-  osal_task_delay(5);                 // Bus power settling delay.
+  tu_delay(5);                 // Bus power settling delay.
 
   USBKEYPID = USBKEY;
 
-  if(USBPWRCTL & USBBGVBV)            // Event caused by application of bus power.
-  {
+  if(USBPWRCTL & USBBGVBV) {          // Event caused by application of bus power.
     USBPWRCTL |= VBOFFIE;             // Enable bus-power-removed interrupt.
     USBPLLDIVB = USBPLLDIVB;          // For some reason the PLL will *NOT* lock unless the divider
                                       // register is re-written. The assumption here is that this
@@ -678,21 +686,17 @@ static void handle_bus_power_event(void *param)
     USBPLLCTL |= (UPLLEN | UPFDEN);   // Enable the PLL.
 
     uint16_t attempts = 0;
-
-    do                                // Poll the PLL, checking for a successful lock.
-    {
+    do {                              // Poll the PLL, checking for a successful lock.
       USBPLLIR = 0;
-      osal_task_delay(1);
+      tu_delay(1);
       attempts++;
     } while ((attempts < 10) && (USBPLLIR != 0));
 
-    if(!USBPLLIR)                     // A successful lock is indicated by all PLL-related interrupt
-    {                                 // flags being cleared.
+    // A successful lock is indicated by all PLL-related interrupt flags being cleared.
+    if(!USBPLLIR) {
       dcd_init(0);                    // Re-initialize the USB module.
     }
-  }
-  else                                // Event caused by removal of bus power.
-  {
+  } else {                            // Event caused by removal of bus power.
     USBPWRCTL |= VBONIE;              // Enable bus-power-applied interrupt.
     USBPLLCTL &= ~(UPLLEN | UPFDEN);  // Disable the PLL.
     USBCNF = 0;                       // Disable the USB module.
@@ -741,20 +745,19 @@ void dcd_int_handler(uint8_t rhport)
       break;
 
     case USBVECINT_PWR_VBUSOn:
-    case USBVECINT_PWR_VBUSOff:
+    case USBVECINT_PWR_VBUSOff: {
       USBKEYPID = USBKEY;
       // Prevent (possibly) unstable power from generating spurious interrupts.
       USBPWRCTL &= ~(VBONIE | VBOFFIE);
       USBKEYPID = 0;
 
-      {
-        dcd_event_t event;
+      dcd_event_t event;
 
-        event.rhport = 0;
-        event.event_id = USBD_EVENT_FUNC_CALL;
-        event.func_call.func = handle_bus_power_event;
+      event.rhport = 0;
+      event.event_id = USBD_EVENT_FUNC_CALL;
+      event.func_call.func = handle_bus_power_event;
 
-        dcd_event_handler(&event, true);
+      dcd_event_handler(&event, true);
       }
       break;
 
-- 
cgit v1.3.1


From 6328301bb652458ad752b05129e1944404adc7ca Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Apr 2024 23:56:55 +0700
Subject: revert to use __builtin_ctz() for optimized time

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 22 +++++++++++++++++-----
 src/portable/renesas/rusb2/hcd_rusb2.c | 30 +++++++++++++++---------------
 2 files changed, 32 insertions(+), 20 deletions(-)

(limited to 'src')

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index f9523191a..50400d1f5 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -915,6 +915,18 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 // ISR
 //--------------------------------------------------------------------+
+
+#if defined(__CCRX__)
+TU_ATTR_ALWAYS_INLINE static inline unsigned __builtin_ctz(unsigned int value) {
+  unsigned int count = 0;
+  while ((value & 1) == 0) {
+    value >>= 1;
+    count++;
+  }
+  return count;
+}
+#endif
+
 void dcd_int_handler(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
@@ -1002,13 +1014,13 @@ void dcd_int_handler(uint8_t rhport)
   // Buffer ready
   if ( is0 & RUSB2_INTSTS0_BRDY_Msk ) {
     const unsigned m = rusb->BRDYENB;
-    const unsigned s = rusb->BRDYSTS & m;
+    unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     rusb->BRDYSTS = ~s;
-    for (unsigned p = 0; p < PIPE_COUNT; ++p) {
-      if (tu_bit_test(s, p)) {
-        process_pipe_brdy(rhport, p);
-      }
+    while (s) {
+      const unsigned num = __builtin_ctz(s);
+      process_pipe_brdy(rhport, num);
+      s &= ~TU_BIT(num);
     }
   }
 }
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 1356b696f..f140da690 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -758,6 +758,17 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 //--------------------------------------------------------------------+
 // ISR
 //--------------------------------------------------------------------+
+#if defined(__CCRX__)
+TU_ATTR_ALWAYS_INLINE static inline unsigned __builtin_ctz(unsigned int value) {
+  unsigned int count = 0;
+  while ((value & 1) == 0) {
+    value >>= 1;
+    count++;
+  }
+  return count;
+}
+#endif
+
 void hcd_int_handler(uint8_t rhport, bool in_isr) {
   (void) in_isr;
 
@@ -807,23 +818,12 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     }
   }
 
-#if defined(__CCRX__)
-  static const int Mod37BitPosition[] = {
-    -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
-    7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
-    20, 8, 19, 18};
-#endif
-
   if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
     const unsigned m = rusb->NRDYENB;
     unsigned s = rusb->NRDYSTS & m;
     rusb->NRDYSTS = ~s;
     while (s) {
-#if defined(__CCRX__)
-      const unsigned num = Mod37BitPosition[(-s & s) % 37];
-#else
       const unsigned num = __builtin_ctz(s);
-#endif
       process_pipe_nrdy(rhport, num);
       s &= ~TU_BIT(num);
     }
@@ -833,10 +833,10 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) {
     unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     rusb->BRDYSTS = ~s;
-    for (unsigned p = 0; p < PIPE_COUNT; ++p) {
-      if (tu_bit_test(s, p)) {
-        process_pipe_brdy(rhport, p);
-      }
+    while (s) {
+      const unsigned num = __builtin_ctz(s);
+      process_pipe_brdy(rhport, num);
+      s &= ~TU_BIT(num);
     }
   }
 }
-- 
cgit v1.3.1


From 9588c3fac9e6625e73357f6edddd12f6d11cbd7d Mon Sep 17 00:00:00 2001
From: NConrad <pigrew@gmail.com>
Date: Tue, 28 Jun 2022 23:26:54 -0400
Subject: USBD: When SET_FEATURE(ENDPOINT_HALT), the DTOG must be reset.

---
 src/device/usbd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 96982c30b..034a9ae09 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -636,7 +636,7 @@ static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * dri
 }
 
 // This handles the actual request and its response.
-// return false will cause its caller to stall control endpoint
+// Returns false if unable to complete the request, causing caller to stall control endpoints.
 static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request) {
   usbd_control_set_complete_callback(NULL);
   TU_ASSERT(p_request->bmRequestType_bit.type < TUSB_REQ_TYPE_INVALID);
-- 
cgit v1.3.1


From 5dabef79eeb7d6ca271b2a09abddb700bc59ca03 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Apr 2024 10:27:16 +0700
Subject: don't check local endpoint stalled status, just carry the request for
 host.

---
 src/device/usbd.c | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 034a9ae09..109c3462d 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1306,12 +1306,10 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // only stalled if currently cleared
-  if (!_usbd_dev.ep_status[epnum][dir].stalled) {
-    TU_LOG_USBD("    Stall EP %02X\r\n", ep_addr);
-    dcd_edpt_stall(rhport, ep_addr);
-    _usbd_dev.ep_status[epnum][dir].stalled = 1;
-    _usbd_dev.ep_status[epnum][dir].busy = 1;
-  }
+  TU_LOG_USBD("    Stall EP %02X\r\n", ep_addr);
+  dcd_edpt_stall(rhport, ep_addr);
+  _usbd_dev.ep_status[epnum][dir].stalled = 1;
+  _usbd_dev.ep_status[epnum][dir].busy = 1;
 }
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
@@ -1321,12 +1319,10 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   uint8_t const dir = tu_edpt_dir(ep_addr);
 
   // only clear if currently stalled
-  if (_usbd_dev.ep_status[epnum][dir].stalled) {
-    TU_LOG_USBD("    Clear Stall EP %02X\r\n", ep_addr);
-    dcd_edpt_clear_stall(rhport, ep_addr);
-    _usbd_dev.ep_status[epnum][dir].stalled = 0;
-    _usbd_dev.ep_status[epnum][dir].busy = 0;
-  }
+  TU_LOG_USBD("    Clear Stall EP %02X\r\n", ep_addr);
+  dcd_edpt_clear_stall(rhport, ep_addr);
+  _usbd_dev.ep_status[epnum][dir].stalled = 0;
+  _usbd_dev.ep_status[epnum][dir].busy = 0;
 }
 
 bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) {
-- 
cgit v1.3.1


From 189080b684b298e0b3e7df6528f24a43c646ab8c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Apr 2024 10:40:24 +0700
Subject: add TU_ASSERT() to check for adding new usb event

---
 src/device/usbd.c    | 4 ++--
 src/host/usbh.c      | 4 ++--
 src/osal/osal_none.h | 1 -
 src/osal/osal_pico.h | 1 -
 4 files changed, 4 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 96982c30b..76b7b3ee5 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -296,9 +296,9 @@ tu_static osal_queue_t _usbd_q;
 #endif
 
 TU_ATTR_ALWAYS_INLINE static inline bool queue_event(dcd_event_t const * event, bool in_isr) {
-  bool ret = osal_queue_send(_usbd_q, event, in_isr);
+  TU_ASSERT(osal_queue_send(_usbd_q, event, in_isr));
   tud_event_hook_cb(event->rhport, event->event_id, in_isr);
-  return ret;
+  return true;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 6a5491998..f8fddf394 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -288,9 +288,9 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec) {
 #endif
 
 TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) {
-  bool ret = osal_queue_send(_usbh_q, event, in_isr);
+  TU_ASSERT(osal_queue_send(_usbh_q, event, in_isr));
   tuh_event_hook_cb(event->rhport, event->event_id, in_isr);
-  return ret;
+  return true;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index c954fcfe8..c93f7a86c 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -180,7 +180,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
     _osal_q_unlock(qhdl);
   }
 
-  TU_ASSERT(success);
   return success;
 }
 
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 00c589ef9..315de0950 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -145,7 +145,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
   bool success = tu_fifo_write(&qhdl->ff, data);
   critical_section_exit(&qhdl->critsec);
 
-  TU_ASSERT(success);
   return success;
 }
 
-- 
cgit v1.3.1


From e1c3b5aeab46de79b08b0655e8ece2c37a0f1a92 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Apr 2024 10:57:54 +0700
Subject: minor update to sof

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 830a1ccd0..a824226c7 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -1136,16 +1136,14 @@ void dcd_int_handler(uint8_t rhport) {
 
   if(int_status & GINTSTS_SOF) {
     dwc2->gintsts = GINTSTS_SOF;
+    const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos;
 
-    if (_sof_en) {
-      uint32_t frame = (dwc2->dsts & (DSTS_FNSOF)) >> 8;
-      dcd_event_sof(rhport, frame, true);
-    } else {
-      // Disable SOF interrupt if SOF was not explicitly enabled. SOF was used for remote wakeup detection
+    // Disable SOF interrupt if SOF was not explicitly enabled since SOF was used for remote wakeup detection
+    if (!_sof_en) {
       dwc2->gintmsk &= ~GINTMSK_SOFM;
     }
 
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+    dcd_event_sof(rhport, frame, true);
   }
 
   // RxFIFO non-empty interrupt handling.
-- 
cgit v1.3.1


From 1b0ec6b1bd3135209451fab7909130a7b12c23f8 Mon Sep 17 00:00:00 2001
From: Hardy Griech <reinhard.griech@endress.com>
Date: Fri, 22 Sep 2023 18:26:36 +0200
Subject: make it compile also with old Nordic SDK

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 71 +++++++++++++++++++++++++++--------
 1 file changed, 55 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 80a285ef0..e831a09de 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -40,7 +40,6 @@
 
 #include "nrf.h"
 #include "nrf_clock.h"
-#include "nrf_power.h"
 #include "nrfx_usbd_errata.h"
 
 #ifdef __GNUC__
@@ -57,6 +56,13 @@
 #include "mcu/mcu.h"
 #endif
 
+#if 1000*MDK_MAJOR_VERSION + MDK_MINOR_VERSION <= 8040
+// Nordic actually has generated a mess here: nrfx==1.9.0 has MDK 8.40.3 while nrfx==2.0.0 has MDK 8.29.0
+// Unfortunately there are API differences between nrfx<2.0.0 and nrfx>=2.0.0.  Hoping that everyone uses
+// nRF Connect SDK keeps the libraries up to date.
+#define OLD_NORDIC_SDK
+#endif
+
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
@@ -110,21 +116,6 @@ static struct
 /* Control / Bulk / Interrupt (CBI) Transfer
  *------------------------------------------------------------------*/
 
-// NVIC_GetEnableIRQ is only available in CMSIS v5
-#ifndef NVIC_GetEnableIRQ
-static inline uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif
-
 // check if we are in ISR
 TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
 {
@@ -253,13 +244,27 @@ void dcd_init (uint8_t rhport)
 void dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
+#ifdef SOFTDEVICE_PRESENT
+  if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
+  {
+    NVIC_EnableIRQ(USBD_IRQn);
+  }
+#else
   NVIC_EnableIRQ(USBD_IRQn);
+#endif
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
   (void) rhport;
+#ifdef SOFTDEVICE_PRESENT
+  if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
+  {
+    NVIC_DisableIRQ(USBD_IRQn);
+  }
+#else
   NVIC_DisableIRQ(USBD_IRQn);
+#endif
 }
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
@@ -916,7 +921,11 @@ static bool hfclk_running(void)
   }
 #endif
 
+#ifdef OLD_NORDIC_SDK
+  return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+#else
   return nrf_clock_hf_is_running(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+#endif
 }
 
 static void hfclk_enable(void)
@@ -937,9 +946,14 @@ static void hfclk_enable(void)
   }
 #endif
 
+#ifdef OLD_NORDIC_SDK
+  nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
+  nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART);
+#else
   nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
 #endif
+#endif
 }
 
 static void hfclk_disable(void)
@@ -957,8 +971,12 @@ static void hfclk_disable(void)
   }
 #endif
 
+#ifdef OLD_NORDIC_SDK
+  nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
+#else
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
 #endif
+#endif
 }
 
 // Power & Clock Peripheral on nRF5x to manage USB
@@ -1100,13 +1118,27 @@ void tusb_hal_nrf_power_event (uint32_t event)
       NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk;
 
       // Enable interrupt, priorities should be set by application
+#ifdef SOFTDEVICE_PRESENT
+      if (sd_nvic_ClearPendingIRQ(USBD_IRQn) != NRF_SUCCESS)
+      {
+        NVIC_ClearPendingIRQ(USBD_IRQn);
+      }
+#else
       NVIC_ClearPendingIRQ(USBD_IRQn);
+#endif
       // Don't enable USBD interrupt yet, if dcd_init() did not finish yet
       // Interrupt will be enabled by tud_init(), when USB stack is ready
       // to handle interrupts.
       if (tud_inited())
       {
+#ifdef SOFTDEVICE_PRESENT
+        if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
+        {
+          NVIC_EnableIRQ(USBD_IRQn);
+        }
+#else
         NVIC_EnableIRQ(USBD_IRQn);
+#endif
       }
 
       // Wait for HFCLK
@@ -1127,7 +1159,14 @@ void tusb_hal_nrf_power_event (uint32_t event)
         __ISB(); __DSB(); // for sync
 
         // Disable Interrupt
+#ifdef SOFTDEVICE_PRESENT
+        if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
+        {
+          NVIC_DisableIRQ(USBD_IRQn);
+        }
+#else
         NVIC_DisableIRQ(USBD_IRQn);
+#endif
 
         // disable all interrupt
         NRF_USBD->INTENCLR = NRF_USBD->INTEN;
-- 
cgit v1.3.1


From 2567fe3fd8b69e896b1d29de36d295ee007e5c91 Mon Sep 17 00:00:00 2001
From: Hardy Griech <reinhard.griech@endress.com>
Date: Fri, 22 Sep 2023 18:39:00 +0200
Subject: softdevice nvic calls only if old SDK

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index e831a09de..0e645ec46 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -244,7 +244,7 @@ void dcd_init (uint8_t rhport)
 void dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
-#ifdef SOFTDEVICE_PRESENT
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
   if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
   {
     NVIC_EnableIRQ(USBD_IRQn);
@@ -257,7 +257,7 @@ void dcd_int_enable(uint8_t rhport)
 void dcd_int_disable(uint8_t rhport)
 {
   (void) rhport;
-#ifdef SOFTDEVICE_PRESENT
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
   if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
   {
     NVIC_DisableIRQ(USBD_IRQn);
@@ -1118,7 +1118,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
       NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk;
 
       // Enable interrupt, priorities should be set by application
-#ifdef SOFTDEVICE_PRESENT
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
       if (sd_nvic_ClearPendingIRQ(USBD_IRQn) != NRF_SUCCESS)
       {
         NVIC_ClearPendingIRQ(USBD_IRQn);
@@ -1131,7 +1131,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
       // to handle interrupts.
       if (tud_inited())
       {
-#ifdef SOFTDEVICE_PRESENT
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
         if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
         {
           NVIC_EnableIRQ(USBD_IRQn);
@@ -1159,7 +1159,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
         __ISB(); __DSB(); // for sync
 
         // Disable Interrupt
-#ifdef SOFTDEVICE_PRESENT
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
         if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
         {
           NVIC_DisableIRQ(USBD_IRQn);
-- 
cgit v1.3.1


From c535a4d42be742f235126fa679bf65a6751360cc Mon Sep 17 00:00:00 2001
From: Hardy Griech <reinhard.griech@endress.com>
Date: Sat, 25 Nov 2023 14:49:49 +0100
Subject: catch all nrfx versions with an old API

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 40 +++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 13 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 0e645ec46..f5eea1310 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -56,11 +56,25 @@
 #include "mcu/mcu.h"
 #endif
 
-#if 1000*MDK_MAJOR_VERSION + MDK_MINOR_VERSION <= 8040
-// Nordic actually has generated a mess here: nrfx==1.9.0 has MDK 8.40.3 while nrfx==2.0.0 has MDK 8.29.0
-// Unfortunately there are API differences between nrfx<2.0.0 and nrfx>=2.0.0.  Hoping that everyone uses
-// nRF Connect SDK keeps the libraries up to date.
-#define OLD_NORDIC_SDK
+// Unfortunately there are API differences between nrfx<2.0.0 and nrfx>=2.0.0
+// Nordic actually has generated a mess here: nrfx==1.9.0 has MDK 8.40.3 while nrfx==2.0.0 has MDK 8.29.0.
+// See the below statement to catch all nrfx versions with an old API.
+#define _MDK_VERSION 10000*MDK_MAJOR_VERSION + 100*MDK_MINOR_VERSION + MDK_MICRO_VERSION
+#if _MDK_VERSION <= 82701
+    // nrfx <= 1.8.1
+    #define NORDIC_SDK_OLD_API
+#elif  _MDK_VERSION == 83201
+    // nrfx 1.8.2 / 1.8.4
+    #define NORDIC_SDK_OLD_API
+#elif  _MDK_VERSION == 83203
+    // nrfx 1.8.5
+    #define NORDIC_SDK_OLD_API
+#elif  _MDK_VERSION == 83500
+    // nrfx 1.8.6
+    #define NORDIC_SDK_OLD_API
+#elif _MDK_VERSION == 84003
+    // nrfx 1.9.0
+    #define NORDIC_SDK_OLD_API
 #endif
 
 /*------------------------------------------------------------------*/
@@ -244,7 +258,7 @@ void dcd_init (uint8_t rhport)
 void dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
   if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
   {
     NVIC_EnableIRQ(USBD_IRQn);
@@ -257,7 +271,7 @@ void dcd_int_enable(uint8_t rhport)
 void dcd_int_disable(uint8_t rhport)
 {
   (void) rhport;
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
   if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
   {
     NVIC_DisableIRQ(USBD_IRQn);
@@ -921,7 +935,7 @@ static bool hfclk_running(void)
   }
 #endif
 
-#ifdef OLD_NORDIC_SDK
+#ifdef NORDIC_SDK_OLD_API
   return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY);
 #else
   return nrf_clock_hf_is_running(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
@@ -946,7 +960,7 @@ static void hfclk_enable(void)
   }
 #endif
 
-#ifdef OLD_NORDIC_SDK
+#ifdef NORDIC_SDK_OLD_API
   nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
   nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART);
 #else
@@ -971,7 +985,7 @@ static void hfclk_disable(void)
   }
 #endif
 
-#ifdef OLD_NORDIC_SDK
+#ifdef NORDIC_SDK_OLD_API
   nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
 #else
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
@@ -1118,7 +1132,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
       NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk;
 
       // Enable interrupt, priorities should be set by application
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
       if (sd_nvic_ClearPendingIRQ(USBD_IRQn) != NRF_SUCCESS)
       {
         NVIC_ClearPendingIRQ(USBD_IRQn);
@@ -1131,7 +1145,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
       // to handle interrupts.
       if (tud_inited())
       {
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
         if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
         {
           NVIC_EnableIRQ(USBD_IRQn);
@@ -1159,7 +1173,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
         __ISB(); __DSB(); // for sync
 
         // Disable Interrupt
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(OLD_NORDIC_SDK)
+#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
         if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
         {
           NVIC_DisableIRQ(USBD_IRQn);
-- 
cgit v1.3.1


From 37a05e02647a188f562e763ab24cdbd9f48cf434 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Apr 2024 11:23:38 +0700
Subject: revert nvic changes

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 36 +----------------------------------
 1 file changed, 1 insertion(+), 35 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index f5eea1310..5f2de6446 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -258,27 +258,13 @@ void dcd_init (uint8_t rhport)
 void dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
-  if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
-  {
-    NVIC_EnableIRQ(USBD_IRQn);
-  }
-#else
   NVIC_EnableIRQ(USBD_IRQn);
-#endif
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
   (void) rhport;
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
-  if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
-  {
-    NVIC_DisableIRQ(USBD_IRQn);
-  }
-#else
   NVIC_DisableIRQ(USBD_IRQn);
-#endif
 }
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
@@ -1132,27 +1118,14 @@ void tusb_hal_nrf_power_event (uint32_t event)
       NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk;
 
       // Enable interrupt, priorities should be set by application
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
-      if (sd_nvic_ClearPendingIRQ(USBD_IRQn) != NRF_SUCCESS)
-      {
-        NVIC_ClearPendingIRQ(USBD_IRQn);
-      }
-#else
       NVIC_ClearPendingIRQ(USBD_IRQn);
-#endif
+
       // Don't enable USBD interrupt yet, if dcd_init() did not finish yet
       // Interrupt will be enabled by tud_init(), when USB stack is ready
       // to handle interrupts.
       if (tud_inited())
       {
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
-        if (sd_nvic_EnableIRQ(USBD_IRQn) != NRF_SUCCESS)
-        {
-          NVIC_EnableIRQ(USBD_IRQn);
-        }
-#else
         NVIC_EnableIRQ(USBD_IRQn);
-#endif
       }
 
       // Wait for HFCLK
@@ -1173,14 +1146,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
         __ISB(); __DSB(); // for sync
 
         // Disable Interrupt
-#if defined(SOFTDEVICE_PRESENT)  &&  defined(NORDIC_SDK_OLD_API)
-        if (sd_nvic_DisableIRQ(USBD_IRQn) != NRF_SUCCESS)
-        {
-          NVIC_DisableIRQ(USBD_IRQn);
-        }
-#else
         NVIC_DisableIRQ(USBD_IRQn);
-#endif
 
         // disable all interrupt
         NRF_USBD->INTENCLR = NRF_USBD->INTEN;
-- 
cgit v1.3.1


From d82ee79bd0a834a83694c91ce9cff67575283846 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Apr 2024 11:55:03 +0700
Subject: - in case of mdk conflict to use nrfx v2 - allow to force nrfx
 version with CFG_TUD_NRF_NRFX_VERSION=1

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 43 +++++++++++++++++------------------
 1 file changed, 21 insertions(+), 22 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 5f2de6446..df5f275db 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -56,25 +56,24 @@
 #include "mcu/mcu.h"
 #endif
 
-// Unfortunately there are API differences between nrfx<2.0.0 and nrfx>=2.0.0
-// Nordic actually has generated a mess here: nrfx==1.9.0 has MDK 8.40.3 while nrfx==2.0.0 has MDK 8.29.0.
-// See the below statement to catch all nrfx versions with an old API.
-#define _MDK_VERSION 10000*MDK_MAJOR_VERSION + 100*MDK_MINOR_VERSION + MDK_MICRO_VERSION
-#if _MDK_VERSION <= 82701
-    // nrfx <= 1.8.1
-    #define NORDIC_SDK_OLD_API
-#elif  _MDK_VERSION == 83201
-    // nrfx 1.8.2 / 1.8.4
-    #define NORDIC_SDK_OLD_API
-#elif  _MDK_VERSION == 83203
-    // nrfx 1.8.5
-    #define NORDIC_SDK_OLD_API
-#elif  _MDK_VERSION == 83500
-    // nrfx 1.8.6
-    #define NORDIC_SDK_OLD_API
-#elif _MDK_VERSION == 84003
-    // nrfx 1.9.0
-    #define NORDIC_SDK_OLD_API
+/* Try to detect nrfx version if not configured with CFG_TUD_NRF_NRFX_VERSION
+ * nrfx v1 and v2 are concurrently developed. There is no NRFX_VERSION only MDK VERSION which is as follows:
+ * - v2.6.0: 8.44.1, v2.5.0: 8.40.2, v2.4.0: 8.37.0, v2.3.0: 8.35.0, v2.2.0: 8.32.1, v2.1.0: 8.30.2, v2.0.0: 8.29.0
+ * - v1.9.0: 8.40.3, v1.8.6: 8.35.0 (conflict with v2.3.0), v1.8.5: 8.32.3, v1.8.4: 8.32.1 (conflict with v2.2.0),
+ *   v1.8.2: 8.32.1 (conflict with v2.2.0), v1.8.1: 8.27.1
+ * Therefore the check for v1 would be:
+ * - MDK < 8.29.0 (v2.0), MDK == 8.32.3, 8.40.3
+ * - in case of conflict User of those version must upgrade to other 1.x version or set CFG_TUD_NRF_NRFX_VERSION
+*/
+#ifndef CFG_TUD_NRF_NRFX_VERSION
+  #define _MDK_VERSION  (10000*MDK_MAJOR_VERSION + 100*MDK_MINOR_VERSION + MDK_MICRO_VERSION)
+
+  #if _MDK_VERSION < 82900 || _MDK_VERSION == 83203 || _MDK_VERSION == 84003
+    // nrfx <= 1.8.1, or 1.8.5 or 1.9.0
+    #define CFG_TUD_NRF_NRFX_VERSION 1
+  #else
+    #define CFG_TUD_NRF_NRFX_VERSION 2
+  #endif
 #endif
 
 /*------------------------------------------------------------------*/
@@ -921,7 +920,7 @@ static bool hfclk_running(void)
   }
 #endif
 
-#ifdef NORDIC_SDK_OLD_API
+#if CFG_TUD_NRF_NRFX_VERSION == 1
   return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY);
 #else
   return nrf_clock_hf_is_running(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
@@ -946,7 +945,7 @@ static void hfclk_enable(void)
   }
 #endif
 
-#ifdef NORDIC_SDK_OLD_API
+#if CFG_TUD_NRF_NRFX_VERSION == 1
   nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
   nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART);
 #else
@@ -971,7 +970,7 @@ static void hfclk_disable(void)
   }
 #endif
 
-#ifdef NORDIC_SDK_OLD_API
+#if CFG_TUD_NRF_NRFX_VERSION == 1
   nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
 #else
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
-- 
cgit v1.3.1


From bf29417e5fc1cd157e77510d23b05cf51cae2b34 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 Apr 2024 12:59:28 +0700
Subject: code format

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 545 ++++++++++++++--------------------
 1 file changed, 216 insertions(+), 329 deletions(-)

(limited to 'src')

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index df5f275db..38d37bfc6 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -79,25 +79,22 @@
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
-enum
-{
+enum {
   // Max allowed by USB specs
-  MAX_PACKET_SIZE   = 64,
+  MAX_PACKET_SIZE = 64,
 
   // Mask of all END event (IN & OUT) for all endpoints. ENDEPIN0-7, ENDEPOUT0-7, ENDISOIN, ENDISOOUT
   EDPT_END_ALL_MASK = (0xff << USBD_INTEN_ENDEPIN0_Pos) | (0xff << USBD_INTEN_ENDEPOUT0_Pos) |
                       USBD_INTENCLR_ENDISOIN_Msk | USBD_INTEN_ENDISOOUT_Msk
 };
 
-enum
-{
-  EP_ISO_NUM   = 8, // Endpoint number is fixed (8) for ISOOUT and ISOIN
+enum {
+  EP_ISO_NUM = 8, // Endpoint number is fixed (8) for ISOOUT and ISOIN
   EP_CBI_COUNT = 8  // Control Bulk Interrupt endpoints count
 };
 
 // Transfer Descriptor
-typedef struct
-{
+typedef struct {
   uint8_t* buffer;
   uint16_t total_len;
   volatile uint16_t actual_len;
@@ -115,98 +112,83 @@ typedef struct
 } xfer_td_t;
 
 // Data for managing dcd
-static struct
-{
+static struct {
   // All 8 endpoints including control IN & OUT (offset 1)
   // +1 for ISO endpoints
   xfer_td_t xfer[EP_CBI_COUNT + 1][2];
 
   // nRF can only carry one DMA at a time, this is used to guard the access to EasyDMA
   atomic_bool dma_running;
-}_dcd;
+} _dcd;
 
 /*------------------------------------------------------------------*/
 /* Control / Bulk / Interrupt (CBI) Transfer
  *------------------------------------------------------------------*/
 
 // check if we are in ISR
-TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void) {
   return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) ? true : false;
 }
 
 // helper to start DMA
-static void start_dma(volatile uint32_t* reg_startep)
-{
+static void start_dma(volatile uint32_t* reg_startep) {
   (*reg_startep) = 1;
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 
   // TASKS_EP0STATUS, TASKS_EP0RCVOUT seem to need EasyDMA to be available
   // However these don't trigger any DMA transfer and got ENDED event subsequently
   // Therefore dma_pending is corrected right away
-  if ( (reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT) )
-  {
+  if ((reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT)) {
     atomic_flag_clear(&_dcd.dma_running);
   }
 }
 
-static void edpt_dma_start(volatile uint32_t* reg_startep)
-{
-  if ( atomic_flag_test_and_set(&_dcd.dma_running) )
-  {
+static void edpt_dma_start(volatile uint32_t* reg_startep) {
+  if (atomic_flag_test_and_set(&_dcd.dma_running)) {
     usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
-  }else
-  {
+  } else {
     start_dma(reg_startep);
   }
 }
 
 // DMA is complete
-static void edpt_dma_end(void)
-{
-  TU_ASSERT(_dcd.dma_running, );
+static void edpt_dma_end(void) {
+  TU_ASSERT(_dcd.dma_running,);
   atomic_flag_clear(&_dcd.dma_running);
 }
 
 // helper getting td
-static inline xfer_td_t* get_td(uint8_t epnum, uint8_t dir)
-{
+static inline xfer_td_t* get_td(uint8_t epnum, uint8_t dir) {
   return &_dcd.xfer[epnum][dir];
 }
 
 static void xact_out_dma(uint8_t epnum);
+
 // Function wraps xact_out_dma which wants uint8_t while usbd_defer_func wants void (*)(void *)
-static void xact_out_dma_wrapper(void *epnum)
-{
-  xact_out_dma((uint8_t)((uintptr_t)epnum));
+static void xact_out_dma_wrapper(void* epnum) {
+  xact_out_dma((uint8_t) ((uintptr_t) epnum));
 }
 
 // Start DMA to move data from Endpoint -> RAM
-static void xact_out_dma(uint8_t epnum)
-{
+static void xact_out_dma(uint8_t epnum) {
   xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
   uint32_t xact_len;
 
   // DMA can't be active during read of SIZE.EPOUT or SIZE.ISOOUT, so try to lock,
   // If already running defer call regardless if it was called from ISR or task,
-  if ( atomic_flag_test_and_set(&_dcd.dma_running) )
-  {
-    usbd_defer_func((osal_task_func_t)xact_out_dma_wrapper, (void *)(uint32_t)epnum, is_in_isr());
+  if (atomic_flag_test_and_set(&_dcd.dma_running)) {
+    usbd_defer_func((osal_task_func_t) xact_out_dma_wrapper, (void*) (uint32_t) epnum, is_in_isr());
     return;
   }
-  if (epnum == EP_ISO_NUM)
-  {
+  if (epnum == EP_ISO_NUM) {
     xact_len = NRF_USBD->SIZE.ISOOUT;
     // If ZERO bit is set, ignore ISOOUT length
-    if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk)
-    {
+    if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk) {
       xact_len = 0;
       atomic_flag_clear(&_dcd.dma_running);
-    }
-    else
-    {
-      if (xfer->started)
-      {
+    } else {
+      if (xfer->started) {
         // Trigger DMA move data from Endpoint -> SRAM
         NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer;
         NRF_USBD->ISOOUT.MAXCNT = xact_len;
@@ -216,9 +198,7 @@ static void xact_out_dma(uint8_t epnum)
         atomic_flag_clear(&_dcd.dma_running);
       }
     }
-  }
-  else
-  {
+  } else {
     // limit xact len to remaining length
     xact_len = tu_min16((uint16_t) NRF_USBD->SIZE.EPOUT[epnum], xfer->total_len - xfer->actual_len);
 
@@ -232,14 +212,13 @@ static void xact_out_dma(uint8_t epnum)
 
 // Prepare for a CBI transaction IN, call at the start
 // it start DMA to transfer data from RAM -> Endpoint
-static void xact_in_dma(uint8_t epnum)
-{
+static void xact_in_dma(uint8_t epnum) {
   xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
 
   // Each transaction is up to Max Packet Size
   uint16_t const xact_len = tu_min16(xfer->total_len - xfer->actual_len, xfer->mps);
 
-  NRF_USBD->EPIN[epnum].PTR    = (uint32_t) xfer->buffer;
+  NRF_USBD->EPIN[epnum].PTR = (uint32_t) xfer->buffer;
   NRF_USBD->EPIN[epnum].MAXCNT = xact_len;
 
   edpt_dma_start(&NRF_USBD->TASKS_STARTEPIN[epnum]);
@@ -248,26 +227,22 @@ static void xact_in_dma(uint8_t epnum)
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
-void dcd_init (uint8_t rhport)
-{
+void dcd_init(uint8_t rhport) {
   TU_LOG2("dcd init\r\n");
   (void) rhport;
 }
 
-void dcd_int_enable(uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   (void) rhport;
   NVIC_EnableIRQ(USBD_IRQn);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   (void) rhport;
   NVIC_DisableIRQ(USBD_IRQn);
 }
 
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
   (void) rhport;
   (void) dev_addr;
   // Set Address is automatically update by hw controller, nothing to do
@@ -282,8 +257,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   NRF_USBD->INTENSET = USBD_INTEN_USBEVENT_Msk;
 }
 
-void dcd_remote_wakeup(uint8_t rhport)
-{
+void dcd_remote_wakeup(uint8_t rhport) {
   (void) rhport;
 
   // Bring controller out of low power mode
@@ -292,8 +266,7 @@ void dcd_remote_wakeup(uint8_t rhport)
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport)
-{
+void dcd_disconnect(uint8_t rhport) {
   (void) rhport;
   NRF_USBD->USBPULLUP = 0;
 
@@ -303,14 +276,12 @@ void dcd_disconnect(uint8_t rhport)
 }
 
 // connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport)
-{
+void dcd_connect(uint8_t rhport) {
   (void) rhport;
   NRF_USBD->USBPULLUP = 1;
 }
 
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
+void dcd_sof_enable(uint8_t rhport, bool en) {
   (void) rhport;
   (void) en;
 
@@ -320,39 +291,32 @@ void dcd_sof_enable(uint8_t rhport, bool en)
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
   (void) rhport;
 
   uint8_t const ep_addr = desc_edpt->bEndpointAddress;
-  uint8_t const epnum   = tu_edpt_number(ep_addr);
-  uint8_t const dir     = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   _dcd.xfer[epnum][dir].mps = tu_edpt_packet_size(desc_edpt);
 
-  if (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS)
-  {
-    if (dir == TUSB_DIR_OUT)
-    {
+  if (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) {
+    if (dir == TUSB_DIR_OUT) {
       NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + epnum);
       NRF_USBD->EPOUTEN |= TU_BIT(epnum);
 
       // Write any value to SIZE register will allow nRF to ACK/accept data
       NRF_USBD->SIZE.EPOUT[epnum] = 0;
-    }else
-    {
+    } else {
       NRF_USBD->INTENSET = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum);
-      NRF_USBD->EPINEN  |= TU_BIT(epnum);
+      NRF_USBD->EPINEN |= TU_BIT(epnum);
     }
     // clear stall and reset DataToggle
     NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
     NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
-  }
-  else
-  {
+  } else {
     TU_ASSERT(epnum == EP_ISO_NUM);
-    if (dir == TUSB_DIR_OUT)
-    {
+    if (dir == TUSB_DIR_OUT) {
       // SPLIT ISO buffer when ISO IN endpoint is already opened.
       if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps) NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
 
@@ -365,9 +329,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       // Enable SOF and ISOOUT interrupts, and ISOOUT endpoint.
       NRF_USBD->INTENSET = USBD_INTENSET_ENDISOOUT_Msk | USBD_INTENSET_SOF_Msk;
       NRF_USBD->EPOUTEN |= USBD_EPOUTEN_ISOOUT_Msk;
-    }
-    else
-    {
+    } else {
       NRF_USBD->EVENTS_ENDISOIN = 0;
 
       // SPLIT ISO buffer when ISO OUT endpoint is already opened.
@@ -378,39 +340,38 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
       // Enable SOF and ISOIN interrupts, and ISOIN endpoint.
       NRF_USBD->INTENSET = USBD_INTENSET_ENDISOIN_Msk | USBD_INTENSET_SOF_Msk;
-      NRF_USBD->EPINEN  |= USBD_EPINEN_ISOIN_Msk;
+      NRF_USBD->EPINEN |= USBD_EPINEN_ISOIN_Msk;
     }
   }
 
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 
   return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
-{
+void dcd_edpt_close_all(uint8_t rhport) {
   // disable interrupt to prevent race condition
   dcd_int_disable(rhport);
 
   // disable all non-control (bulk + interrupt) endpoints
-  for ( uint8_t ep = 1; ep < EP_CBI_COUNT; ep++ )
-  {
+  for (uint8_t ep = 1; ep < EP_CBI_COUNT; ep++) {
     NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + ep) | TU_BIT(USBD_INTEN_ENDEPIN0_Pos + ep);
 
     NRF_USBD->TASKS_STARTEPIN[ep] = 0;
     NRF_USBD->TASKS_STARTEPOUT[ep] = 0;
 
-    tu_memclr(_dcd.xfer[ep], 2*sizeof(xfer_td_t));
+    tu_memclr(_dcd.xfer[ep], 2 * sizeof(xfer_td_t));
   }
 
   // disable both ISO
   NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk | USBD_INTENCLR_ENDISOOUT_Msk | USBD_INTENCLR_ENDISOIN_Msk;
   NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_OneDir;
 
-  NRF_USBD->TASKS_STARTISOIN  = 0;
+  NRF_USBD->TASKS_STARTISOIN = 0;
   NRF_USBD->TASKS_STARTISOOUT = 0;
 
-  tu_memclr(_dcd.xfer[EP_ISO_NUM], 2*sizeof(xfer_td_t));
+  tu_memclr(_dcd.xfer[EP_ISO_NUM], 2 * sizeof(xfer_td_t));
 
   // de-activate all non-control
   NRF_USBD->EPOUTEN = 1UL;
@@ -419,107 +380,89 @@ void dcd_edpt_close_all (uint8_t rhport)
   dcd_int_enable(rhport);
 }
 
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if (epnum != EP_ISO_NUM)
-  {
+  if (epnum != EP_ISO_NUM) {
     // CBI
-    if (dir == TUSB_DIR_OUT)
-    {
+    if (dir == TUSB_DIR_OUT) {
       NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + epnum);
       NRF_USBD->EPOUTEN &= ~TU_BIT(epnum);
-    }
-    else
-    {
+    } else {
       NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPIN0_Pos + epnum);
       NRF_USBD->EPINEN &= ~TU_BIT(epnum);
     }
-  }
-  else
-  {
+  } else {
     _dcd.xfer[EP_ISO_NUM][dir].mps = 0;
     // ISO
-    if (dir == TUSB_DIR_OUT)
-    {
+    if (dir == TUSB_DIR_OUT) {
       NRF_USBD->INTENCLR = USBD_INTENCLR_ENDISOOUT_Msk;
       NRF_USBD->EPOUTEN &= ~USBD_EPOUTEN_ISOOUT_Msk;
       NRF_USBD->EVENTS_ENDISOOUT = 0;
-    }
-    else
-    {
+    } else {
       NRF_USBD->INTENCLR = USBD_INTENCLR_ENDISOIN_Msk;
       NRF_USBD->EPINEN &= ~USBD_EPINEN_ISOIN_Msk;
     }
     // One of the ISO endpoints closed, no need to split buffers any more.
     NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_OneDir;
     // When both ISO endpoint are close there is no need for SOF any more.
-    if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps + _dcd.xfer[EP_ISO_NUM][TUSB_DIR_OUT].mps == 0) NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
+    if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps + _dcd.xfer[EP_ISO_NUM][TUSB_DIR_OUT].mps == 0)
+      NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
   }
   _dcd.xfer[epnum][dir].started = false;
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 }
 
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   xfer_td_t* xfer = get_td(epnum, dir);
 
   TU_ASSERT(!xfer->started);
-  xfer->buffer     = buffer;
-  xfer->total_len  = total_bytes;
+  xfer->buffer = buffer;
+  xfer->total_len = total_bytes;
   xfer->actual_len = 0;
 
   // Control endpoint with zero-length packet and opposite direction to 1st request byte --> status stage
   bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
 
-  if ( control_status )
-  {
+  if (control_status) {
     // Status Phase also requires EasyDMA has to be available as well !!!!
     edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
 
     // The nRF doesn't interrupt on status transmit so we queue up a success response.
     dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr());
-  }
-  else if ( dir == TUSB_DIR_OUT )
-  {
+  } else if (dir == TUSB_DIR_OUT) {
     xfer->started = true;
-    if ( epnum == 0 )
-    {
+    if (epnum == 0) {
       // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
       edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
-    }else
-    {
+    } else {
       // started just set, it could start DMA transfer if interrupt was trigger after this line
       // code only needs to start transfer (from Endpoint to RAM) when data_received was set
       // before started was set. If started is NOT set but data_received is, it means that
       // current transfer was already finished and next data is already present in endpoint and
       // can be consumed by future transfer
-      __ISB(); __DSB();
-      if ( xfer->data_received && xfer->started )
-      {
+      __ISB();
+      __DSB();
+      if (xfer->data_received && xfer->started) {
         // Data is already received previously
         // start DMA to copy to SRAM
         xfer->data_received = false;
         xact_out_dma(epnum);
-      }
-      else
-      {
+      } else {
         // nRF auto accept next Bulk/Interrupt OUT packet
         // nothing to do
       }
     }
-  }
-  else
-  {
+  } else {
     // Start DMA to copy data from RAM -> Endpoint
     xact_in_dma(epnum);
   }
@@ -527,42 +470,37 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   return true;
 }
 
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
   xfer_td_t* xfer = get_td(epnum, dir);
 
-  if ( epnum == 0 )
-  {
+  if (epnum == 0) {
     NRF_USBD->TASKS_EP0STALL = 1;
-  }else if (epnum != EP_ISO_NUM)
-  {
+  } else if (epnum != EP_ISO_NUM) {
     NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | ep_addr;
 
     // Note: nRF can auto ACK packet OUT before get stalled.
     // There maybe data in endpoint fifo already, we need to pull it out
-    if ( (dir == TUSB_DIR_OUT) && xfer->data_received )
-    {
+    if ((dir == TUSB_DIR_OUT) && xfer->data_received) {
       xfer->data_received = false;
       xact_out_dma(epnum);
     }
   }
 
-  __ISB(); __DSB();
+  __ISB();
+  __DSB();
 }
 
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-  if ( epnum != 0 && epnum != EP_ISO_NUM )
-  {
+  if (epnum != 0 && epnum != EP_ISO_NUM) {
     // reset data toggle to DATA0
     // First write this register with VALUE=Nop to select the endpoint, then either read it to get the status from
     // VALUE, or write it again with VALUE=Data0 or Data1
@@ -575,26 +513,25 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
     // Write any value to SIZE register will allow nRF to ACK/accept data
     if (dir == TUSB_DIR_OUT) NRF_USBD->SIZE.EPOUT[epnum] = 0;
 
-    __ISB(); __DSB();
+    __ISB();
+    __DSB();
   }
 }
 
 /*------------------------------------------------------------------*/
 /* Interrupt Handler
  *------------------------------------------------------------------*/
-void bus_reset(void)
-{
+void bus_reset(void) {
   // 6.35.6 USB controller automatically disabled all endpoints (except control)
   NRF_USBD->EPOUTEN = 1UL;
   NRF_USBD->EPINEN = 1UL;
 
-  for(int i=0; i<8; i++)
-  {
+  for (int i = 0; i < 8; i++) {
     NRF_USBD->TASKS_STARTEPIN[i] = 0;
     NRF_USBD->TASKS_STARTEPOUT[i] = 0;
   }
 
-  NRF_USBD->TASKS_STARTISOIN  = 0;
+  NRF_USBD->TASKS_STARTISOIN = 0;
   NRF_USBD->TASKS_STARTISOOUT = 0;
 
   // Clear USB Event Interrupt
@@ -604,43 +541,40 @@ void bus_reset(void)
   // Reset interrupt
   NRF_USBD->INTENCLR = NRF_USBD->INTEN;
   NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
-          USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk;
+                       USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk |
+                       USBD_INTEN_ENDEPOUT0_Msk;
 
   tu_varclr(&_dcd);
   _dcd.xfer[0][TUSB_DIR_IN].mps = MAX_PACKET_SIZE;
   _dcd.xfer[0][TUSB_DIR_OUT].mps = MAX_PACKET_SIZE;
 }
 
-void dcd_int_handler(uint8_t rhport)
-{
+void dcd_int_handler(uint8_t rhport) {
   (void) rhport;
 
-  uint32_t const inten  = NRF_USBD->INTEN;
+  uint32_t const inten = NRF_USBD->INTEN;
   uint32_t int_status = 0;
 
   volatile uint32_t* regevt = &NRF_USBD->EVENTS_USBRESET;
 
-  for(uint8_t i=0; i<USBD_INTEN_EPDATA_Pos+1; i++)
-  {
-    if ( tu_bit_test(inten, i) && regevt[i]  )
-    {
+  for (uint8_t i = 0; i < USBD_INTEN_EPDATA_Pos + 1; i++) {
+    if (tu_bit_test(inten, i) && regevt[i]) {
       int_status |= TU_BIT(i);
 
       // event clear
       regevt[i] = 0;
-      __ISB(); __DSB();
+      __ISB();
+      __DSB();
     }
   }
 
-  if ( int_status & USBD_INTEN_USBRESET_Msk )
-  {
+  if (int_status & USBD_INTEN_USBRESET_Msk) {
     bus_reset();
     dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
   }
 
   // ISOIN: Data was moved to endpoint buffer, client will be notified in SOF
-  if ( int_status & USBD_INTEN_ENDISOIN_Msk )
-  {
+  if (int_status & USBD_INTEN_ENDISOIN_Msk) {
     xfer_td_t* xfer = get_td(EP_ISO_NUM, TUSB_DIR_IN);
 
     xfer->actual_len = NRF_USBD->ISOIN.AMOUNT;
@@ -649,13 +583,11 @@ void dcd_int_handler(uint8_t rhport)
     xfer->iso_in_transfer_ready = true;
   }
 
-  if ( int_status & USBD_INTEN_SOF_Msk )
-  {
+  if (int_status & USBD_INTEN_SOF_Msk) {
     bool iso_enabled = false;
 
     // ISOOUT: Transfer data gathered in previous frame from buffer to RAM
-    if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
-    {
+    if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk) {
       iso_enabled = true;
       // Transfer from endpoint to RAM only if data is not corrupted
       if ((int_status & USBD_INTEN_USBEVENT_Msk) == 0 ||
@@ -665,20 +597,17 @@ void dcd_int_handler(uint8_t rhport)
     }
 
     // ISOIN: Notify client that data was transferred
-    if (NRF_USBD->EPINEN & USBD_EPINEN_ISOIN_Msk)
-    {
+    if (NRF_USBD->EPINEN & USBD_EPINEN_ISOIN_Msk) {
       iso_enabled = true;
 
       xfer_td_t* xfer = get_td(EP_ISO_NUM, TUSB_DIR_IN);
-      if ( xfer->iso_in_transfer_ready )
-      {
+      if (xfer->iso_in_transfer_ready) {
         xfer->iso_in_transfer_ready = false;
         dcd_event_xfer_complete(0, EP_ISO_NUM | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
       }
     }
 
-    if ( !iso_enabled )
-    {
+    if (!iso_enabled) {
       // ISO endpoint is not used, SOF is only enabled one-time for remote wakeup
       // so we disable it now
       NRF_USBD->INTENCLR = USBD_INTENSET_SOF_Msk;
@@ -687,16 +616,17 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
 
-  if ( int_status & USBD_INTEN_USBEVENT_Msk )
-  {
+  if (int_status & USBD_INTEN_USBEVENT_Msk) {
     TU_LOG(3, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
 
-    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk | USBD_EVENTCAUSE_ISOOUTCRC_Msk };
+    enum {
+      EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk |
+                       USBD_EVENTCAUSE_ISOOUTCRC_Msk
+    };
     uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
     NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt
 
-    if ( evt_cause & USBD_EVENTCAUSE_SUSPEND_Msk )
-    {
+    if (evt_cause & USBD_EVENTCAUSE_SUSPEND_Msk) {
       // Put controller into low power mode
       // Leave HFXO disable to application, since it may be used by other peripherals
       NRF_USBD->LOWPOWER = 1;
@@ -704,8 +634,7 @@ void dcd_int_handler(uint8_t rhport)
       dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
     }
 
-    if ( evt_cause & USBD_EVENTCAUSE_USBWUALLOWED_Msk )
-    {
+    if (evt_cause & USBD_EVENTCAUSE_USBWUALLOWED_Msk) {
       // USB is out of low power mode, and wakeup is allowed
       // Initiate RESUME signal
       NRF_USBD->DPDMVALUE = USBD_DPDMVALUE_STATE_Resume;
@@ -717,34 +646,29 @@ void dcd_int_handler(uint8_t rhport)
       NRF_USBD->INTENSET = USBD_INTENSET_SOF_Msk;
     }
 
-    if ( evt_cause & USBD_EVENTCAUSE_RESUME_Msk )
-    {
+    if (evt_cause & USBD_EVENTCAUSE_RESUME_Msk) {
       dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
     }
   }
 
   // Setup tokens are specific to the Control endpoint.
-  if ( int_status & USBD_INTEN_EP0SETUP_Msk )
-  {
-    uint8_t const setup[8] =
-    {
-      NRF_USBD->BMREQUESTTYPE , NRF_USBD->BREQUEST, NRF_USBD->WVALUEL , NRF_USBD->WVALUEH,
-      NRF_USBD->WINDEXL       , NRF_USBD->WINDEXH , NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
+  if (int_status & USBD_INTEN_EP0SETUP_Msk) {
+    uint8_t const setup[8] = {
+        NRF_USBD->BMREQUESTTYPE, NRF_USBD->BREQUEST, NRF_USBD->WVALUEL, NRF_USBD->WVALUEH,
+        NRF_USBD->WINDEXL, NRF_USBD->WINDEXH, NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
     };
 
     // nrf5x hw auto handle set address, there is no need to inform usb stack
-    tusb_control_request_t const * request = (tusb_control_request_t const *) setup;
+    tusb_control_request_t const* request = (tusb_control_request_t const*) setup;
 
-    if ( !(TUSB_REQ_RCPT_DEVICE   == request->bmRequestType_bit.recipient &&
-           TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type &&
-           TUSB_REQ_SET_ADDRESS   == request->bRequest) )
-    {
+    if (!(TUSB_REQ_RCPT_DEVICE == request->bmRequestType_bit.recipient &&
+          TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type &&
+          TUSB_REQ_SET_ADDRESS == request->bRequest)) {
       dcd_event_setup_received(0, setup, true);
     }
   }
 
-  if ( int_status & EDPT_END_ALL_MASK )
-  {
+  if (int_status & EDPT_END_ALL_MASK) {
     // DMA complete move data from SRAM <-> Endpoint
     // Must before endpoint transfer handling
     edpt_dma_end();
@@ -786,30 +710,24 @@ void dcd_int_handler(uint8_t rhport)
    * len if Host decides to sent fewer bytes, it this case transaction is also
    * complete and next transfer is not initiated here like for CBI.
    */
-  for(uint8_t epnum=0; epnum<EP_CBI_COUNT+1; epnum++)
-  {
-    if ( tu_bit_test(int_status, USBD_INTEN_ENDEPOUT0_Pos+epnum))
-    {
+  for (uint8_t epnum = 0; epnum < EP_CBI_COUNT + 1; epnum++) {
+    if (tu_bit_test(int_status, USBD_INTEN_ENDEPOUT0_Pos + epnum)) {
       xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
       uint16_t const xact_len = NRF_USBD->EPOUT[epnum].AMOUNT;
 
-      xfer->buffer     += xact_len;
+      xfer->buffer += xact_len;
       xfer->actual_len += xact_len;
 
       // Transfer complete if transaction len < Max Packet Size or total len is transferred
-      if ( (epnum != EP_ISO_NUM) && (xact_len == xfer->mps) && (xfer->actual_len < xfer->total_len) )
-      {
-        if ( epnum == 0 )
-        {
+      if ((epnum != EP_ISO_NUM) && (xact_len == xfer->mps) && (xfer->actual_len < xfer->total_len)) {
+        if (epnum == 0) {
           // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
           edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
-        }else
-        {
+        } else {
           // nRF auto accept next Bulk/Interrupt OUT packet
           // nothing to do
         }
-      }else
-      {
+      } else {
         TU_ASSERT(xfer->started,);
         xfer->total_len = xfer->actual_len;
         xfer->started = false;
@@ -823,11 +741,11 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   // Endpoint <-> Host ( In & OUT )
-  if ( int_status & (USBD_INTEN_EPDATA_Msk | USBD_INTEN_EP0DATADONE_Msk) )
-  {
+  if (int_status & (USBD_INTEN_EPDATA_Msk | USBD_INTEN_EP0DATADONE_Msk)) {
     uint32_t data_status = NRF_USBD->EPDATASTATUS;
     NRF_USBD->EPDATASTATUS = data_status;
-    __ISB(); __DSB();
+    __ISB();
+    __DSB();
 
     // EP0DATADONE is set with either Control Out on IN Data
     // Since EPDATASTATUS cannot be used to determine whether it is control OUT or IN.
@@ -836,22 +754,18 @@ void dcd_int_handler(uint8_t rhport)
     bool const is_control_out = (int_status & USBD_INTEN_EP0DATADONE_Msk) && !(NRF_USBD->BMREQUESTTYPE & TUSB_DIR_IN_MASK);
 
     // CBI In: Endpoint -> Host (transaction complete)
-    for(uint8_t epnum=0; epnum<EP_CBI_COUNT; epnum++)
-    {
-      if ( tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in) )
-      {
+    for (uint8_t epnum = 0; epnum < EP_CBI_COUNT; epnum++) {
+      if (tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in)) {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
         uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT;
 
-        xfer->buffer     += xact_len;
+        xfer->buffer += xact_len;
         xfer->actual_len += xact_len;
 
-        if ( xfer->actual_len < xfer->total_len )
-        {
+        if (xfer->actual_len < xfer->total_len) {
           // Start DMA to copy next data packet
           xact_in_dma(epnum);
-        } else
-        {
+        } else {
           // CBI IN complete
           dcd_event_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
         }
@@ -859,17 +773,13 @@ void dcd_int_handler(uint8_t rhport)
     }
 
     // CBI OUT: Host -> Endpoint
-    for(uint8_t epnum=0; epnum<EP_CBI_COUNT; epnum++)
-    {
-      if ( tu_bit_test(data_status, 16+epnum) || (epnum == 0 && is_control_out) )
-      {
+    for (uint8_t epnum = 0; epnum < EP_CBI_COUNT; epnum++) {
+      if (tu_bit_test(data_status, 16 + epnum) || (epnum == 0 && is_control_out)) {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
 
-        if ( xfer->started && xfer->actual_len < xfer->total_len )
-        {
+        if (xfer->started && xfer->actual_len < xfer->total_len) {
           xact_out_dma(epnum);
-        }else
-        {
+        } else {
           // Data overflow !!! Nah, nRF will auto accept next Bulk/Interrupt OUT packet
           // Mark this endpoint with data received
           xfer->data_received = true;
@@ -893,27 +803,22 @@ void dcd_int_handler(uint8_t rhport)
   #define SD_MAGIC_NUMBER   0x51B1E5DB
 #endif
 
-static inline bool is_sd_existed(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_sd_existed(void) {
   return *((uint32_t*)(SOFTDEVICE_INFO_STRUCT_ADDRESS+4)) == SD_MAGIC_NUMBER;
 }
 
 // check if SD is existed and enabled
-static inline bool is_sd_enabled(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool is_sd_enabled(void) {
   if ( !is_sd_existed() ) return false;
-
   uint8_t sd_en = false;
   (void) sd_softdevice_is_enabled(&sd_en);
   return sd_en;
 }
 #endif
 
-static bool hfclk_running(void)
-{
+static bool hfclk_running(void) {
 #ifdef SOFTDEVICE_PRESENT
-  if ( is_sd_enabled() )
-  {
+  if ( is_sd_enabled() ) {
     uint32_t is_running = 0;
     (void) sd_clock_hfclk_is_running(&is_running);
     return (is_running ? true : false);
@@ -927,19 +832,17 @@ static bool hfclk_running(void)
 #endif
 }
 
-static void hfclk_enable(void)
-{
+static void hfclk_enable(void) {
 #if CFG_TUSB_OS == OPT_OS_MYNEWT
   usb_clock_request();
   return;
 #else
 
   // already running, nothing to do
-  if ( hfclk_running() ) return;
+  if (hfclk_running()) return;
 
 #ifdef SOFTDEVICE_PRESENT
-  if ( is_sd_enabled() )
-  {
+  if ( is_sd_enabled() ) {
     (void)sd_clock_hfclk_request();
     return;
   }
@@ -955,16 +858,14 @@ static void hfclk_enable(void)
 #endif
 }
 
-static void hfclk_disable(void)
-{
+static void hfclk_disable(void) {
 #if CFG_TUSB_OS == OPT_OS_MYNEWT
   usb_clock_release();
   return;
 #else
 
 #ifdef SOFTDEVICE_PRESENT
-  if ( is_sd_enabled() )
-  {
+  if ( is_sd_enabled() ) {
     (void)sd_clock_hfclk_release();
     return;
   }
@@ -988,8 +889,7 @@ static void hfclk_disable(void)
 // Therefore this function must be called to handle USB power event by
 // - nrfx_power_usbevt_init() : if Softdevice is not used or enabled
 // - SoftDevice SOC event : if SD is used and enabled
-void tusb_hal_nrf_power_event (uint32_t event)
-{
+void tusb_hal_nrf_power_event(uint32_t event) {
   // Value is chosen to be as same as NRFX_POWER_USB_EVT_* in nrfx_power.h
   enum {
     USB_EVT_DETECTED = 0,
@@ -998,50 +898,41 @@ void tusb_hal_nrf_power_event (uint32_t event)
   };
 
 #if CFG_TUSB_DEBUG >= 2
-  const char* const power_evt_str[] = { "Detected", "Removed", "Ready" };
+  const char* const power_evt_str[] = {"Detected", "Removed", "Ready"};
   TU_LOG(2, "Power USB event: %s\r\n", power_evt_str[event]);
 #endif
 
-  switch ( event )
-  {
+  switch (event) {
     case USB_EVT_DETECTED:
-      if ( !NRF_USBD->ENABLE )
-      {
+      if (!NRF_USBD->ENABLE) {
         // Prepare for receiving READY event: disable interrupt since we will blocking wait
         NRF_USBD->INTENCLR = USBD_INTEN_USBEVENT_Msk;
         NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
 #ifdef NRF52_SERIES // NRF53 does not need this errata
         // ERRATA 171, 187, 166
-        if ( nrfx_usbd_errata_187() )
-        {
+        if (nrfx_usbd_errata_187()) {
           // CRITICAL_REGION_ENTER();
-          if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-          {
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-            *((volatile uint32_t *) (0x4006ED14)) = 0x00000003;
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          }
-          else
-          {
-            *((volatile uint32_t *) (0x4006ED14)) = 0x00000003;
+          if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+            *((volatile uint32_t*) (0x4006ED14)) = 0x00000003;
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          } else {
+            *((volatile uint32_t*) (0x4006ED14)) = 0x00000003;
           }
           // CRITICAL_REGION_EXIT();
         }
 
-        if ( nrfx_usbd_errata_171() )
-        {
+        if (nrfx_usbd_errata_171()) {
           // CRITICAL_REGION_ENTER();
-          if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-          {
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-            *((volatile uint32_t *) (0x4006EC14)) = 0x000000C0;
-            *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          }
-          else
-          {
-            *((volatile uint32_t *) (0x4006EC14)) = 0x000000C0;
+          if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+            *((volatile uint32_t*) (0x4006EC14)) = 0x000000C0;
+            *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          } else {
+            *((volatile uint32_t*) (0x4006EC14)) = 0x000000C0;
           }
           // CRITICAL_REGION_EXIT();
         }
@@ -1049,64 +940,58 @@ void tusb_hal_nrf_power_event (uint32_t event)
 
         // Enable the peripheral (will cause Ready event)
         NRF_USBD->ENABLE = 1;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
         // Enable HFCLK
         hfclk_enable();
       }
-    break;
+      break;
 
     case USB_EVT_READY:
       // Skip if pull-up is enabled and HCLK is already running.
       // Application probably call this more than necessary.
-      if ( NRF_USBD->USBPULLUP && hfclk_running() ) break;
+      if (NRF_USBD->USBPULLUP && hfclk_running()) break;
 
       // Waiting for USBD peripheral enabled
-      while ( !(USBD_EVENTCAUSE_READY_Msk & NRF_USBD->EVENTCAUSE) ) { }
+      while (!(USBD_EVENTCAUSE_READY_Msk & NRF_USBD->EVENTCAUSE)) {}
 
       NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
-      __ISB(); __DSB(); // for sync
+      __ISB();
+      __DSB(); // for sync
 
 #ifdef NRF52_SERIES
-      if ( nrfx_usbd_errata_171() )
-      {
+      if (nrfx_usbd_errata_171()) {
         // CRITICAL_REGION_ENTER();
-        if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-        {
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          *((volatile uint32_t *) (0x4006EC14)) = 0x00000000;
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-        }
-        else
-        {
-          *((volatile uint32_t *) (0x4006EC14)) = 0x00000000;
+        if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          *((volatile uint32_t*) (0x4006EC14)) = 0x00000000;
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+        } else {
+          *((volatile uint32_t*) (0x4006EC14)) = 0x00000000;
         }
 
         // CRITICAL_REGION_EXIT();
       }
 
-      if ( nrfx_usbd_errata_187() )
-      {
+      if (nrfx_usbd_errata_187()) {
         // CRITICAL_REGION_ENTER();
-        if ( *((volatile uint32_t *) (0x4006EC00)) == 0x00000000 )
-        {
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-          *((volatile uint32_t *) (0x4006ED14)) = 0x00000000;
-          *((volatile uint32_t *) (0x4006EC00)) = 0x00009375;
-        }
-        else
-        {
-          *((volatile uint32_t *) (0x4006ED14)) = 0x00000000;
+        if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) {
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+          *((volatile uint32_t*) (0x4006ED14)) = 0x00000000;
+          *((volatile uint32_t*) (0x4006EC00)) = 0x00009375;
+        } else {
+          *((volatile uint32_t*) (0x4006ED14)) = 0x00000000;
         }
         // CRITICAL_REGION_EXIT();
       }
 
-      if ( nrfx_usbd_errata_166() )
-      {
-        *((volatile uint32_t *) (NRF_USBD_BASE + 0x800)) = 0x7E3;
-        *((volatile uint32_t *) (NRF_USBD_BASE + 0x804)) = 0x40;
+      if (nrfx_usbd_errata_166()) {
+        *((volatile uint32_t*) (NRF_USBD_BASE + 0x800)) = 0x7E3;
+        *((volatile uint32_t*) (NRF_USBD_BASE + 0x804)) = 0x40;
 
-        __ISB(); __DSB();
+        __ISB();
+        __DSB();
       }
 #endif
 
@@ -1122,27 +1007,27 @@ void tusb_hal_nrf_power_event (uint32_t event)
       // Don't enable USBD interrupt yet, if dcd_init() did not finish yet
       // Interrupt will be enabled by tud_init(), when USB stack is ready
       // to handle interrupts.
-      if (tud_inited())
-      {
+      if (tud_inited()) {
         NVIC_EnableIRQ(USBD_IRQn);
       }
 
       // Wait for HFCLK
-      while ( !hfclk_running() ) { }
+      while (!hfclk_running()) {}
 
       // Enable pull up
       NRF_USBD->USBPULLUP = 1;
-      __ISB(); __DSB(); // for sync
-    break;
+      __ISB();
+      __DSB(); // for sync
+      break;
 
     case USB_EVT_REMOVED:
-      if ( NRF_USBD->ENABLE )
-      {
+      if (NRF_USBD->ENABLE) {
         // Abort all transfers
 
         // Disable pull up
         NRF_USBD->USBPULLUP = 0;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
         // Disable Interrupt
         NVIC_DisableIRQ(USBD_IRQn);
@@ -1151,15 +1036,17 @@ void tusb_hal_nrf_power_event (uint32_t event)
         NRF_USBD->INTENCLR = NRF_USBD->INTEN;
 
         NRF_USBD->ENABLE = 0;
-        __ISB(); __DSB(); // for sync
+        __ISB();
+        __DSB(); // for sync
 
         hfclk_disable();
 
         dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, is_in_isr());
       }
-    break;
+      break;
 
-    default: break;
+    default:
+      break;
   }
 }
 
-- 
cgit v1.3.1


From 3442a87d5b52112a8bc4672322d488703e4ee23e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Apr 2024 20:06:13 +0700
Subject: - clang h743 build and run cdc_msc ok - switch unit test back to gcc,
 since path to clang conflict on local setup (x86 and arm)

---
 examples/build_system/cmake/cpu/cortex-m7.cmake    |  1 -
 examples/build_system/cmake/toolchain/common.cmake |  2 +-
 hw/bsp/board.c                                     | 19 +++++++++++++++++++
 hw/bsp/stm32h7/family.cmake                        |  7 +++----
 src/common/tusb_common.h                           |  1 +
 src/portable/synopsys/dwc2/dcd_dwc2.c              |  6 +++---
 test/unit-test/project.yml                         | 12 ++++++------
 7 files changed, 33 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/examples/build_system/cmake/cpu/cortex-m7.cmake b/examples/build_system/cmake/cpu/cortex-m7.cmake
index f7684af84..b0f84b76b 100644
--- a/examples/build_system/cmake/cpu/cortex-m7.cmake
+++ b/examples/build_system/cmake/cpu/cortex-m7.cmake
@@ -18,7 +18,6 @@ elseif (TOOLCHAIN STREQUAL "clang")
   set(TOOLCHAIN_COMMON_FLAGS
     --target=arm-none-eabi
     -mcpu=cortex-m7
-    -mfloat-abi=hard
     -mfpu=fpv5-d16
     )
   set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
diff --git a/examples/build_system/cmake/toolchain/common.cmake b/examples/build_system/cmake/toolchain/common.cmake
index 6c6d54c74..bbd670b65 100644
--- a/examples/build_system/cmake/toolchain/common.cmake
+++ b/examples/build_system/cmake/toolchain/common.cmake
@@ -45,7 +45,7 @@ elseif (TOOLCHAIN STREQUAL "clang")
   list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
     -Wl,--print-memory-usage
     -Wl,--gc-sections
-    -Wl,--cref
+    #-Wl,--cref
     )
 endif ()
 
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 23b4b6628..996ac9263 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -108,6 +108,25 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
 //  st->st_mode = S_IFCHR;
 //}
 
+// Clang use picolibc
+#if defined(__clang__)
+static int cl_putc(char c, FILE *f) {
+  (void) f;
+  return sys_write(0, &c, 1);
+}
+
+static int cl_getc(FILE* f) {
+  (void) f;
+  char c;
+  return sys_read(0, &c, 1) > 0 ? c : -1;
+}
+
+static FILE __stdio = FDEV_SETUP_STREAM(cl_putc, cl_getc, NULL, _FDEV_SETUP_RW);
+FILE *const stdin = &__stdio;
+__strong_reference(stdin, stdout);
+__strong_reference(stdin, stderr);
+#endif
+
 int board_getchar(void) {
   char c;
   return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index d852ce21c..ab9ba3fbb 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -56,10 +56,8 @@ function(add_board_target BOARD_TARGET)
       ${ST_CMSIS}/Include
       ${ST_HAL_DRIVER}/Inc
       )
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      )
+    #target_compile_options(${BOARD_TARGET} PUBLIC)
+    #target_compile_definitions(${BOARD_TARGET} PUBLIC)
 
     update_board(${BOARD_TARGET})
 
@@ -75,6 +73,7 @@ function(add_board_target BOARD_TARGET)
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
       target_link_options(${BOARD_TARGET} PUBLIC
+        #-ldummyhost
         "LINKER:--script=${LD_FILE_GNU}"
         )
     endif ()
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 1f08ce4ed..0d4082c03 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -65,6 +65,7 @@
 // Standard Headers
 #include <stdbool.h>
 #include <stdint.h>
+#include <inttypes.h>
 #include <stddef.h>
 #include <string.h>
 #include <stdio.h>
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index a824226c7..f17d30f06 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -174,7 +174,7 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
     // Check if free space is available
     TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
     _allocated_fifo_words_tx += fifo_size;
-    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size * 4,
+    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %" PRIu32, fifo_size * 4,
            _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
 
     // DIEPTXF starts at FIFO #1.
@@ -419,9 +419,9 @@ void print_dwc2_info(dwc2_regs_t* dwc2) {
   volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
   TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
   for (size_t i = 0; i < 5; i++) {
-    TU_LOG(DWC2_DEBUG, "0x%08lX, ", p[i]);
+    TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 ", ", p[i]);
   }
-  TU_LOG(DWC2_DEBUG, "0x%08lX\r\n", p[5]);
+  TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 "\r\n", p[5]);
 }
 #endif
 
diff --git a/test/unit-test/project.yml b/test/unit-test/project.yml
index 82528f68c..7fbbabfe6 100644
--- a/test/unit-test/project.yml
+++ b/test/unit-test/project.yml
@@ -81,20 +81,20 @@
 
 :tools:
   :test_compiler:
-     :executable: clang
-     :name: 'clang compiler'
+     :executable: gcc
+     :name: 'gcc compiler'
      :arguments:
         - -I"$": COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE               #expands to -I search paths
         - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR   #expands to -I search paths
         - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR  #expands to all -D defined symbols
-        - -fsanitize=address
+        #- -fsanitize=address
         - -c ${1}                       #source code input file (Ruby method call param list sub)
         - -o ${2}                       #object file output (Ruby method call param list sub)
   :test_linker:
-     :executable: clang
-     :name: 'clang linker'
+     :executable: gcc
+     :name: 'gcc linker'
      :arguments:
-        - -fsanitize=address
+        #- -fsanitize=address
         - ${1}               #list of object files to link (Ruby method call param list sub)
         - -o ${2}            #executable file output (Ruby method call param list sub)
 
-- 
cgit v1.3.1


From 9d1d171b0c54f179b07c4abd3f776da1e512e2fc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Apr 2024 23:08:27 +0700
Subject: - update nrfx to v3.4.0 - compile nrf with __STARTUP_CLEAR_BSS and
 link flag -nostartfiles

---
 hw/bsp/nrf/boards/pca10056/board.cmake |  1 -
 hw/bsp/nrf/family.c                    | 46 +++++++++++++++++++++++++++++++---
 hw/bsp/nrf/family.cmake                | 13 ++++++----
 hw/bsp/nrf/linker/nrf52840_xxaa.ld     | 26 +++++++++++++++++++
 src/portable/nordic/nrf5x/dcd_nrf5x.c  |  3 ++-
 tools/get_deps.py                      |  2 +-
 6 files changed, 79 insertions(+), 12 deletions(-)
 create mode 100644 hw/bsp/nrf/linker/nrf52840_xxaa.ld

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
index 693d7beed..cc370aac8 100644
--- a/hw/bsp/nrf/boards/pca10056/board.cmake
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -1,5 +1,4 @@
 set(MCU_VARIANT nrf52840)
-set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
 endfunction()
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 71c651f5f..897d27c59 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -33,6 +33,7 @@
 #pragma GCC diagnostic ignored "-Wcast-qual"
 #pragma GCC diagnostic ignored "-Wcast-align"
 #pragma GCC diagnostic ignored "-Wunused-parameter"
+#pragma GCC diagnostic ignored "-Wunused-variable"
 #pragma GCC diagnostic ignored "-Wundef"
 #pragma GCC diagnostic ignored "-Wredundant-decls"
 #endif
@@ -54,6 +55,14 @@
 #endif
 
 
+// There is API changes between nrfx v2 and v3
+#if 85301 >= (10000*MDK_MAJOR_VERSION + 100*MDK_MINOR_VERSION + MDK_MICRO_VERSION)
+  // note MDK 8.53.1 is also used by nrfx v3.0.0, just skip this version and use later 3.x
+  #define NRFX_VER 2
+#else
+  #define NRFX_VER 3
+#endif
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -100,11 +109,19 @@ static void max3421_init(void);
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 #endif
 
-
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
 void board_init(void) {
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
@@ -124,6 +141,7 @@ void board_init(void) {
   SysTick_Config(SystemCoreClock / 1000);
 
   // UART
+  #if NRFX_VER == 2
   nrfx_uarte_config_t uart_cfg = {
       .pseltxd   = UART_TX_PIN,
       .pselrxd   = UART_RX_PIN,
@@ -137,6 +155,21 @@ void board_init(void) {
           .parity    = NRF_UARTE_PARITY_EXCLUDED,
       }
   };
+  #elif NRFX_VER == 3
+  nrfx_uarte_config_t uart_cfg = {
+      .txd_pin   = UART_TX_PIN,
+      .rxd_pin   = UART_RX_PIN,
+      .rts_pin   = NRF_UARTE_PSEL_DISCONNECTED,
+      .cts_pin   = NRF_UARTE_PSEL_DISCONNECTED,
+      .p_context = NULL,
+      .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
+      .interrupt_priority = 7,
+      .config = {
+          .hwfc      = NRF_UARTE_HWFC_DISABLED,
+          .parity    = NRF_UARTE_PARITY_EXCLUDED,
+      }
+  };
+  #endif
 
   nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler);
 
@@ -224,11 +257,17 @@ int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
-//  return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
+//  nrfx_err_t err = nrfx_uarte_rx(&_uart_id, buf, (size_t) len);
+//  return NRFX_SUCCESS == err ? len : 0;
 }
 
 int board_uart_write(void const* buf, int len) {
-  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
+  nrfx_err_t err = nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len
+                                 #if NRFX_VER == 3
+                                 ,0
+                                 #endif
+                                );
+  return (NRFX_SUCCESS == err) ? len : 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -241,7 +280,6 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
-
 #endif
 
 #ifdef SOFTDEVICE_PRESENT
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 60dcdf753..c038a2035 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -31,14 +31,13 @@ set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
     if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
-      set(LD_FILE_GNU ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld)
-      set(LD_FILE_Clang ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/clang/${MCU_VARIANT}_xxaa.ld)
+      set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_xxaa.ld)
+      set(LD_FILE_Clang ${LD_FILE_GNU})
     endif ()
 
     if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
       set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S)
       set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-      #set(STARTUP_FILE_Clang ${NRFX_DIR}/mdk/arm_startup_${MCU_VARIANT}.s)
     endif ()
 
     add_library(${BOARD_TARGET} STATIC
@@ -48,9 +47,13 @@ function(add_board_target BOARD_TARGET)
       ${NRFX_DIR}/drivers/src/nrfx_spim.c
       ${NRFX_DIR}/drivers/src/nrfx_uarte.c
       ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c
+      ${NRFX_DIR}/soc/nrfx_atomic.c
       ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC CONFIG_GPIO_AS_PINRESET)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      __STARTUP_CLEAR_BSS
+      CONFIG_GPIO_AS_PINRESET
+      )
 
     if (MCU_VARIANT STREQUAL "nrf52840")
       target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52840_XXAA)
@@ -82,12 +85,12 @@ function(add_board_target BOARD_TARGET)
         "LINKER:--script=${LD_FILE_GNU}"
         -L${NRFX_DIR}/mdk
         --specs=nosys.specs --specs=nano.specs
+        -nostartfiles
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
       target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--script=${LD_FILE_Clang}"
         -L${NRFX_DIR}/mdk
-        -lcrt0
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
       target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/nrf/linker/nrf52840_xxaa.ld b/hw/bsp/nrf/linker/nrf52840_xxaa.ld
new file mode 100644
index 000000000..8768fe072
--- /dev/null
+++ b/hw/bsp/nrf/linker/nrf52840_xxaa.ld
@@ -0,0 +1,26 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000
+  EXTFLASH (rx) : ORIGIN = 0x12000000, LENGTH = 0x8000000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+  CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x40000
+}
+
+
+INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+/*__tbss_start__ = __tbss_start;*/
+/*__tbss_end__ = __tbss_end;*/
+/*__sbss_start__ = __sbss_start;*/
+/*__sbss_end__ = __sbss_end;*/
+
+/* picolibc crt0 */
+/*__data_source = __copy_table_start__;*/
+/*__tls_base = __tdata_start;*/
+/*PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );*/
+/*PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );*/
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 38d37bfc6..d31925806 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -58,7 +58,8 @@
 
 /* Try to detect nrfx version if not configured with CFG_TUD_NRF_NRFX_VERSION
  * nrfx v1 and v2 are concurrently developed. There is no NRFX_VERSION only MDK VERSION which is as follows:
- * - v2.6.0: 8.44.1, v2.5.0: 8.40.2, v2.4.0: 8.37.0, v2.3.0: 8.35.0, v2.2.0: 8.32.1, v2.1.0: 8.30.2, v2.0.0: 8.29.0
+ * - v3.0.0: 8.53.1 (conflict with v2.11.0), v3.1.0: 8.55.0 ...
+ * - v2.11.0: 8.53.1, v2.6.0: 8.44.1, v2.5.0: 8.40.2, v2.4.0: 8.37.0, v2.3.0: 8.35.0, v2.2.0: 8.32.1, v2.1.0: 8.30.2, v2.0.0: 8.29.0
  * - v1.9.0: 8.40.3, v1.8.6: 8.35.0 (conflict with v2.3.0), v1.8.5: 8.32.3, v1.8.4: 8.32.1 (conflict with v2.2.0),
  *   v1.8.2: 8.32.1 (conflict with v2.2.0), v1.8.1: 8.27.1
  * Therefore the check for v1 would be:
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 85c8c2126..cfa60002a 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -42,7 +42,7 @@ deps_optional = {
                                   '0b79559eb411149d36e073c1635c620e576308d4',
                                   'mm32'],
     'hw/mcu/nordic/nrfx': ['https://github.com/NordicSemiconductor/nrfx.git',
-                           '2527e3c8449cfd38aee41598e8af8492f410ed15',
+                           '7c47cc0a56ce44658e6da2458e86cd8783ccc4a2',
                            'nrf'],
     'hw/mcu/nuvoton': ['https://github.com/majbthrd/nuc_driver.git',
                        '2204191ec76283371419fbcec207da02e1bc22fa',
-- 
cgit v1.3.1


From 2e383bf90173aa8fa7b4da8a6cded5527907c465 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 22 Apr 2024 12:12:56 +0700
Subject: dcd nrf change atoimc_bool to atomic_flag

---
 hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake | 1 -
 hw/bsp/nrf/family.cmake                                | 4 ++--
 hw/bsp/nrf/linker/nrf52840_s140_v6.ld                  | 2 +-
 hw/bsp/nrf/linker/nrf52840_xxaa.ld                     | 8 +-------
 hw/bsp/samd51/family.c                                 | 5 +++++
 src/portable/nordic/nrf5x/dcd_nrf5x.c                  | 5 ++---
 6 files changed, 11 insertions(+), 14 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
index 726438d05..6ff1a7b59 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -1,6 +1,5 @@
 set(MCU_VARIANT nrf52840)
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
-#set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 # enable max3421 host driver for this board
 set(MAX3421_HOST 1)
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index c038a2035..52a6fc196 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -30,10 +30,10 @@ set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
-    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    if (NOT DEFINED LD_FILE_GNU)
       set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_xxaa.ld)
-      set(LD_FILE_Clang ${LD_FILE_GNU})
     endif ()
+    set(LD_FILE_Clang ${LD_FILE_GNU})
 
     if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
       set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S)
diff --git a/hw/bsp/nrf/linker/nrf52840_s140_v6.ld b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
index e27fa1c91..7cc94a405 100644
--- a/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
@@ -1,7 +1,7 @@
 /* Linker script to configure memory regions. */
 
 SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
 
 MEMORY
 {
diff --git a/hw/bsp/nrf/linker/nrf52840_xxaa.ld b/hw/bsp/nrf/linker/nrf52840_xxaa.ld
index 8768fe072..377c248bb 100644
--- a/hw/bsp/nrf/linker/nrf52840_xxaa.ld
+++ b/hw/bsp/nrf/linker/nrf52840_xxaa.ld
@@ -1,6 +1,7 @@
 /* Linker script to configure memory regions. */
 
 SEARCH_DIR(.)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
 
 MEMORY
 {
@@ -10,7 +11,6 @@ MEMORY
   CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x40000
 }
 
-
 INCLUDE "nrf_common.ld"
 
 /* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
@@ -18,9 +18,3 @@ INCLUDE "nrf_common.ld"
 /*__tbss_end__ = __tbss_end;*/
 /*__sbss_start__ = __sbss_start;*/
 /*__sbss_end__ = __sbss_end;*/
-
-/* picolibc crt0 */
-/*__data_source = __copy_table_start__;*/
-/*__tls_base = __tdata_start;*/
-/*PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );*/
-/*PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );*/
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 170c88191..d56d9f695 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -388,3 +388,8 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx
 }
 
 #endif
+
+void HardFault_Handler(void) {
+  __BKPT(0);
+  while (1);
+}
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index d31925806..56e7f39a0 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -119,7 +119,7 @@ static struct {
   xfer_td_t xfer[EP_CBI_COUNT + 1][2];
 
   // nRF can only carry one DMA at a time, this is used to guard the access to EasyDMA
-  atomic_bool dma_running;
+  atomic_flag dma_running;
 } _dcd;
 
 /*------------------------------------------------------------------*/
@@ -155,7 +155,6 @@ static void edpt_dma_start(volatile uint32_t* reg_startep) {
 
 // DMA is complete
 static void edpt_dma_end(void) {
-  TU_ASSERT(_dcd.dma_running,);
   atomic_flag_clear(&_dcd.dma_running);
 }
 
@@ -618,7 +617,7 @@ void dcd_int_handler(uint8_t rhport) {
   }
 
   if (int_status & USBD_INTEN_USBEVENT_Msk) {
-    TU_LOG(3, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
+    TU_LOG(3, "EVENTCAUSE = 0x%04" PRIX32 "\r\n", NRF_USBD->EVENTCAUSE);
 
     enum {
       EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk |
-- 
cgit v1.3.1


From 62331f02070bdb1bec2890885008e9f88b06bdb6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 22 Apr 2024 15:55:50 +0700
Subject: fix nrfx v3 spim freq when init fix clang build with nrf

---
 examples/host/cdc_msc_hid/src/msc_app.c         |  4 ++--
 hw/bsp/nrf/boards/pca10059/pca10059.ld          |  8 +++++++-
 hw/bsp/nrf/boards/pca10095/board.cmake          |  1 -
 hw/bsp/nrf/boards/pca10100/board.cmake          |  1 -
 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake |  1 -
 hw/bsp/nrf/family.c                             |  6 ++++--
 hw/bsp/nrf/family.cmake                         | 18 +++++++++---------
 hw/bsp/nrf/linker/nrf52833_xxaa.ld              | 20 ++++++++++++++++++++
 hw/bsp/nrf/linker/nrf5340_xxaa_application.ld   | 21 +++++++++++++++++++++
 src/class/cdc/cdc_host.c                        |  4 ++--
 src/host/usbh.c                                 |  2 +-
 11 files changed, 66 insertions(+), 20 deletions(-)
 create mode 100644 hw/bsp/nrf/linker/nrf52833_xxaa.ld
 create mode 100644 hw/bsp/nrf/linker/nrf5340_xxaa_application.ld

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c
index e9c9676b8..1d7e18e6e 100644
--- a/examples/host/cdc_msc_hid/src/msc_app.c
+++ b/examples/host/cdc_msc_hid/src/msc_app.c
@@ -48,8 +48,8 @@ bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_da
   uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
   uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
 
-  printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
-  printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024*1024)/block_size));
+  printf("Block Count = %" PRIu32 ", Block Size: %" PRIu32 "\r\n", block_count, block_size);
 
   return true;
 }
diff --git a/hw/bsp/nrf/boards/pca10059/pca10059.ld b/hw/bsp/nrf/boards/pca10059/pca10059.ld
index 510bfdd8c..adc80f3c4 100644
--- a/hw/bsp/nrf/boards/pca10059/pca10059.ld
+++ b/hw/bsp/nrf/boards/pca10059/pca10059.ld
@@ -1,7 +1,7 @@
 /* Linker script to configure memory regions. */
 
 SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
 
 MEMORY
 {
@@ -11,3 +11,9 @@ MEMORY
 
 
 INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index ca5399a3a..95dd30969 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -1,5 +1,4 @@
 set(MCU_VARIANT nrf5340_application)
-set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
 
 function(update_board TARGET)
   target_sources(${TARGET} PRIVATE
diff --git a/hw/bsp/nrf/boards/pca10100/board.cmake b/hw/bsp/nrf/boards/pca10100/board.cmake
index c30026815..a925dae80 100644
--- a/hw/bsp/nrf/boards/pca10100/board.cmake
+++ b/hw/bsp/nrf/boards/pca10100/board.cmake
@@ -1,5 +1,4 @@
 set(MCU_VARIANT nrf52833)
-set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52833_xxaa.ld)
 
 function(update_board TARGET)
 endfunction()
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
index 693d7beed..cc370aac8 100644
--- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
+++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
@@ -1,5 +1,4 @@
 set(MCU_VARIANT nrf52840)
-set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
 endfunction()
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index deae64f05..aff851ddc 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -356,20 +356,22 @@ static void max3421_init(void) {
       .miso_pin       = MAX3421_MISO_PIN,
   #if NRFX_VER <= 2
       .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
+      .frequency      = NRF_SPIM_FREQ_4M,
   #else
       .ss_pin         = NRF_SPIM_PIN_NOT_CONNECTED,
+      .frequency      = 4000000u,
   #endif
       .ss_active_high = false,
       .irq_priority   = 3,
       .orc            = 0xFF,
       // default setting 4 Mhz, Mode 0, MSB first
-      .frequency      = NRF_SPIM_FREQ_4M,
       .mode           = NRF_SPIM_MODE_0,
       .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
+      .miso_pull      = NRF_GPIO_PIN_NOPULL,
   };
 
   // no handler --> blocking
-  nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+  TU_ASSERT(NRFX_SUCCESS == nrfx_spim_init(&_spi, &cfg, NULL, NULL), );
 
   // max3421e interrupt pin
   #if NRFX_VER <= 2
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 52a6fc196..56ff62bc4 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -30,8 +30,14 @@ set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
+    if (MCU_VARIANT STREQUAL "nrf5340_application")
+      set(MCU_VARIANT_XXAA "nrf5340_xxaa_application")
+    else ()
+      set(MCU_VARIANT_XXAA "${MCU_VARIANT}_xxaa")
+    endif ()
+
     if (NOT DEFINED LD_FILE_GNU)
-      set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_xxaa.ld)
+      set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT_XXAA}.ld)
     endif ()
     set(LD_FILE_Clang ${LD_FILE_GNU})
 
@@ -50,19 +56,13 @@ function(add_board_target BOARD_TARGET)
       ${NRFX_DIR}/soc/nrfx_atomic.c
       ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
+    string(TOUPPER "${MCU_VARIANT_XXAA}" MCU_VARIANT_XXAA_UPPER)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
       __STARTUP_CLEAR_BSS
       CONFIG_GPIO_AS_PINRESET
+      ${MCU_VARIANT_XXAA_UPPER}
       )
 
-    if (MCU_VARIANT STREQUAL "nrf52840")
-      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52840_XXAA)
-    elseif (MCU_VARIANT STREQUAL "nrf52833")
-      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52833_XXAA)
-    elseif (MCU_VARIANT STREQUAL "nrf5340_application")
-      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF5340_XXAA NRF5340_XXAA_APPLICATION)
-    endif ()
-
     if (TRACE_ETM STREQUAL "1")
       # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace
       target_compile_definitions(${BOARD_TARGET} PUBLIC ENABLE_TRACE)
diff --git a/hw/bsp/nrf/linker/nrf52833_xxaa.ld b/hw/bsp/nrf/linker/nrf52833_xxaa.ld
new file mode 100644
index 000000000..ae4d0e5b3
--- /dev/null
+++ b/hw/bsp/nrf/linker/nrf52833_xxaa.ld
@@ -0,0 +1,20 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000
+  CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x20000
+}
+
+
+INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/hw/bsp/nrf/linker/nrf5340_xxaa_application.ld b/hw/bsp/nrf/linker/nrf5340_xxaa_application.ld
new file mode 100644
index 000000000..31762d0b2
--- /dev/null
+++ b/hw/bsp/nrf/linker/nrf5340_xxaa_application.ld
@@ -0,0 +1,21 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+/*GROUP(-lgcc -lc) not compatible with clang*/
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000
+  EXTFLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x8000000
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
+  RAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x3F000
+}
+
+
+INCLUDE "nrf_common.ld"
+
+/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
+__tbss_start__ = __tbss_start;
+__tbss_end__ = __tbss_end;
+__sbss_start__ = __sbss_start;
+__sbss_end__ = __sbss_end;
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 5bdd41f1f..133a10f6e 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1079,7 +1079,7 @@ static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) {
 
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
-  TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
+  TU_LOG_DRV("CDC FTDI Set BaudRate = %" PRIu32 ", divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
   p_cdc->requested_line_coding.bit_rate = baudrate;
@@ -1222,7 +1222,7 @@ static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t co
 }
 
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate);
+  TU_LOG_DRV("CDC CP210x Set BaudRate = %" PRIu32 "\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
diff --git a/src/host/usbh.c b/src/host/usbh.c
index f8fddf394..7a47f5056 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -704,7 +704,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %" PRIu32 "\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     TU_LOG_BUF_USBH(request, 8);
 
     // terminate transfer if any stage failed
-- 
cgit v1.3.1


From c097c85dcf8e0ef3ea052c146c5f514101827251 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 22 Apr 2024 16:17:22 +0700
Subject: fix print lu format warnings with clang

---
 examples/device/audio_test_multi_rate/src/main.c |  2 +-
 examples/device/cdc_uac2/src/uac2_app.c          |  4 ++--
 examples/device/uac2_headset/src/main.c          |  4 ++--
 examples/host/bare_api/src/main.c                |  2 +-
 examples/host/cdc_msc_hid_freertos/src/cdc_app.c |  4 ++--
 examples/host/cdc_msc_hid_freertos/src/msc_app.c |  4 ++--
 examples/host/msc_file_explorer/src/msc_app.c    |  6 +++---
 src/CMakeLists.txt                               |  2 +-
 src/class/cdc/cdc_device.c                       | 13 ++++++-------
 src/class/usbtmc/usbtmc_device.c                 |  2 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c            |  2 +-
 tools/get_deps.py                                |  3 ++-
 12 files changed, 24 insertions(+), 24 deletions(-)

(limited to 'src')

diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 3e7f40dac..2ff7f10bd 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -272,7 +272,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
 
         sampFreq = (uint32_t)((audio_control_cur_4_t *)pBuff)->bCur;
 
-        TU_LOG2("Clock set current freq: %lu\r\n", sampFreq);
+        TU_LOG2("Clock set current freq: %" PRIu32 "\r\n", sampFreq);
 
         return true;
       break;
diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c
index 98659ea68..c57d98a1a 100644
--- a/examples/device/cdc_uac2/src/uac2_app.c
+++ b/examples/device/cdc_uac2/src/uac2_app.c
@@ -69,7 +69,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
   {
     if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
-      TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
+      TU_LOG1("Clock get current freq %" PRIu32 "\r\n", current_sample_rate);
 
       audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
@@ -118,7 +118,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
 
     current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
 
-    TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
+    TU_LOG1("Clock set current freq: %" PRIu32 "\r\n", current_sample_rate);
 
     return true;
   }
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index fbd7ffe22..0ea6e7025 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -157,7 +157,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
   {
     if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
-      TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
+      TU_LOG1("Clock get current freq %" PRIu32 "\r\n", current_sample_rate);
 
       audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
@@ -206,7 +206,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
 
     current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
 
-    TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
+    TU_LOG1("Clock set current freq: %" PRIu32 "\r\n", current_sample_rate);
 
     return true;
   }
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 14725996d..940840a30 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -420,5 +420,5 @@ static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
     _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 
-    printf((char*)temp_buf);
+    printf("%s", (char*)temp_buf);
 }
diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
index 6ff513be1..7d246af67 100644
--- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -117,7 +117,7 @@ void tuh_cdc_rx_cb(uint8_t idx) {
   uint32_t count = tuh_cdc_read(idx, buf, bufsize);
   buf[count] = 0;
 
-  printf((char *) buf);
+  printf("%s", (char *) buf);
 }
 
 void tuh_cdc_mount_cb(uint8_t idx) {
@@ -131,7 +131,7 @@ void tuh_cdc_mount_cb(uint8_t idx) {
   // otherwise you need to call tuh_cdc_set_line_coding() first
   cdc_line_coding_t line_coding = { 0 };
   if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
-    printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
+    printf("  Baudrate: %" PRIu32 ", Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
     printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
   }
 #endif
diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
index ee02ba917..9ffd5d965 100644
--- a/examples/host/cdc_msc_hid_freertos/src/msc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
@@ -47,8 +47,8 @@ bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_dat
   uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
   uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
 
-  printf("Disk Size: %lu MB\r\n", block_count / ((1024 * 1024) / block_size));
-  printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024 * 1024) / block_size));
+  printf("Block Count = %" PRIu32 ", Block Size: %" PRIu32 "\r\n", block_count, block_size);
 
   return true;
 }
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index ecea614a2..f323e30f0 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -114,7 +114,7 @@ bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_da
   uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
   uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
 
-  printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
+  printf("Disk Size: %" PRIu32 " MB\r\n", block_count / ((1024*1024)/block_size));
   // printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
 
   // For simplicity: we only mount 1 LUN per device
@@ -541,10 +541,10 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
         printf("%-40s", fno.fname);
         if (fno.fsize < 1024)
         {
-          printf("%lu B\r\n", fno.fsize);
+          printf("%" PRIu32 " B\r\n", fno.fsize);
         }else
         {
-          printf("%lu KB\r\n", fno.fsize / 1024);
+          printf("%" PRIu32 " KB\r\n", fno.fsize / 1024);
         }
       }
     }
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 076e1e1eb..272962332 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -41,7 +41,7 @@ function(add_tinyusb TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../lib/networking
     )
 
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
     target_compile_options(${TARGET} PRIVATE
       -Wall
       -Wextra
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 7ef0530ec..2e0a0c30d 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -43,10 +43,7 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-enum
-{
-  BULK_PACKET_SIZE = (TUD_OPT_HIGH_SPEED ? 512 : 64)
-};
+#define BULK_PACKET_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 typedef struct
 {
@@ -176,9 +173,11 @@ uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
   uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
 
   // flush if queue more than packet size
-  // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
-  if ( (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE) || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) )
-  {
+  if ( tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE
+       #if CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
+       || tu_fifo_full(&p_cdc->tx_ff) // check full if fifo size is less than packet size
+       #endif
+      ) {
     tud_cdc_n_write_flush(itf);
   }
 
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 286cbe108..f6cddfbd7 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -360,7 +360,7 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 // processing a command (such as a clear). Returns true if it was
 // in the NAK state and successfully transitioned to the ACK wait
 // state.
-bool tud_usbtmc_start_bus_read()
+bool tud_usbtmc_start_bus_read(void)
 {
   usbtmcd_state_enum oldState = usbtmc_state.state;
   switch(oldState)
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 56e7f39a0..2fe721d6b 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -147,7 +147,7 @@ static void start_dma(volatile uint32_t* reg_startep) {
 
 static void edpt_dma_start(volatile uint32_t* reg_startep) {
   if (atomic_flag_test_and_set(&_dcd.dma_running)) {
-    usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
+    usbd_defer_func((osal_task_func_t)(uintptr_t ) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
   } else {
     start_dma(reg_startep);
   }
diff --git a/tools/get_deps.py b/tools/get_deps.py
index cfa60002a..e08246178 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -177,7 +177,8 @@ deps_optional = {
                     '20285262657d1b482d132d20d755c8c330d55c1f',
                     'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
                     'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5'
-                    'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
+                    'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'
+                    'sam3x samd11 samd21 samd51 same5x same7x saml2x samg'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
                          'e73e04ca63495672d955f9268e003cffe168fcd8',
                          'lpc55'],
-- 
cgit v1.3.1


From db30eee0fcacda2b2f3f208ddf5ab9be723129d8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 22 Apr 2024 18:08:41 +0700
Subject: clang tested with mcb1800, add heap to lpc18 linker

---
 examples/host/msc_file_explorer/src/main.c     | 17 +++++-------
 examples/host/msc_file_explorer/src/msc_app.c  |  1 -
 hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld | 34 ++++++++++++++++-------
 hw/bsp/lpc18/boards/mcb1800/lpc1857.ld         | 37 ++++++++++++++++++--------
 hw/bsp/lpc18/family.cmake                      |  8 +++---
 hw/bsp/nrf/family.cmake                        |  3 +--
 src/portable/ehci/ehci.c                       |  2 +-
 7 files changed, 64 insertions(+), 38 deletions(-)

(limited to 'src')

diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index 73f3e9eb5..f6b6810f5 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -72,8 +72,7 @@ extern bool msc_app_init(void);
 extern void msc_app_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   printf("TinyUSB Host MassStorage Explorer Example\r\n");
@@ -87,8 +86,7 @@ int main(void)
 
   msc_app_init();
 
-  while (1)
-  {
+  while (1) {
     // tinyusb host task
     tuh_task();
 
@@ -103,28 +101,25 @@ int main(void)
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
 
-void tuh_mount_cb(uint8_t dev_addr)
-{
+void tuh_mount_cb(uint8_t dev_addr) {
   (void) dev_addr;
 }
 
-void tuh_umount_cb(uint8_t dev_addr)
-{
+void tuh_umount_cb(uint8_t dev_addr) {
   (void) dev_addr;
 }
 
 //--------------------------------------------------------------------+
 // Blinking Task
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   const uint32_t interval_ms = 1000;
   static uint32_t start_ms = 0;
 
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  if (board_millis() - start_ms < interval_ms) return; // not enough time
   start_ms += interval_ms;
 
   board_led_write(led_state);
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index f323e30f0..ddd39c674 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -95,7 +95,6 @@ void msc_app_task(void)
 //
 //--------------------------------------------------------------------+
 
-
 bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
   msc_cbw_t const* cbw = cb_data->cbw;
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
index f1a3add8f..8562a6e71 100644
--- a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
@@ -311,6 +311,20 @@ SECTIONS
         PROVIDE(end = .);
     } > RamLoc40 AT> RamLoc40 /* > RamLoc32 AT> RamLoc32 */
 
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc40
+
     /* NOINIT section for RamLoc40 */
     .noinit_RAM2 (NOLOAD) : ALIGN(4)
     {
@@ -383,15 +397,17 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 -
-                                         (_vStackTop
-                                         + (ResetISR + 1)
-                                         + (NMI_Handler + 1)
-                                         + (HardFault_Handler + 1)
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
+/*    PROVIDE(__valid_user_code_checksum = 0 -*/
+/*                                         (_vStackTop*/
+/*                                         + (ResetISR + 1)*/
+/*                                         + (NMI_Handler + 1)*/
+/*                                         + (HardFault_Handler + 1)*/
+/*                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
+/*                                         ) );*/
 
     /* Provide basic symbols giving location and size of main text
      * block, including initial values of RW data sections. Note that
diff --git a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
index 837dec364..02ea1088e 100644
--- a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
+++ b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
@@ -255,7 +255,6 @@ SECTIONS
         *(COMMON)
         . = ALIGN(4) ;
         _ebss = .;
-        PROVIDE(end = .);
     } > RamLoc40 /* RamLoc32 */
 
     /* NOINIT section for RamLoc40 */
@@ -266,6 +265,20 @@ SECTIONS
        . = ALIGN(4) ;
     } > RamLoc40
 
+    .heap (NOLOAD): {
+        __heap_start = .;
+        __HeapBase = .;
+        __heap_base = .;
+        __end = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        PROVIDE(__end__ = .);
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+        __heap_limit = .;
+        __heap_end = .;
+    } > RamLoc40
+
     /* NOINIT section for RamAHB32 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
     {
@@ -298,19 +311,21 @@ SECTIONS
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
-    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 -
-                                         (_vStackTop
-                                         + (ResetISR + 1)
-                                         + (NMI_Handler + 1)
-                                         + (HardFault_Handler + 1)
-                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
-                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
-                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
-                                         ) );
+    /* This cause issue with clang linker, so it is disabled */
+    /* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
+/*    PROVIDE(__valid_user_code_checksum = 0 -*/
+/*                                         (_vStackTop*/
+/*                                         + (ResetISR + 1)*/
+/*                                         + (NMI_Handler + 1)*/
+/*                                         + (HardFault_Handler + 1)*/
+/*                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
+/*                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
+/*                                         ) );*/
 
     /* Provide basic symbols giving location and size of main text
      * block, including initial values of RW data sections. Note that
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 78f4c510b..bf8efabba 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -47,9 +47,11 @@ function(add_board_target BOARD_TARGET)
     if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
       target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
       target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 56ff62bc4..1d6702720 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -39,7 +39,6 @@ function(add_board_target BOARD_TARGET)
     if (NOT DEFINED LD_FILE_GNU)
       set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT_XXAA}.ld)
     endif ()
-    set(LD_FILE_Clang ${LD_FILE_GNU})
 
     if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
       set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S)
@@ -89,7 +88,7 @@ function(add_board_target BOARD_TARGET)
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
       target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_Clang}"
+        "LINKER:--script=${LD_FILE_GNU}"
         -L${NRFX_DIR}/mdk
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index e145cbb1b..01bbf62bf 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -92,7 +92,7 @@ CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= (EHCI_DBG + 1)
+#if 0 && CFG_TUSB_DEBUG >= (EHCI_DBG + 1)
 static inline void print_portsc(ehci_registers_t* regs) {
   TU_LOG_HEX(EHCI_DBG, regs->portsc);
   TU_LOG(EHCI_DBG, "  Connect Status : %u\r\n", regs->portsc_bm.current_connect_status);
-- 
cgit v1.3.1


From 3fd82cfe225cb05c106eccac830bbcf19206bdb1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Apr 2024 10:57:45 +0700
Subject: clang work with lpc55

---
 examples/device/msc_dual_lun/src/main.c      | 25 ++++------
 hw/bsp/family_support.cmake                  |  2 +-
 hw/bsp/lpc55/family.c                        | 66 +++++++++++++++-----------
 hw/bsp/lpc55/family.cmake                    | 69 +++++++++++++---------------
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c |  2 +-
 5 files changed, 83 insertions(+), 81 deletions(-)

(limited to 'src')

diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index de402d3da..aabd0bf8a 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -39,7 +39,7 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -50,8 +50,7 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 void led_blinking_task(void);
 
 /*------------- MAIN -------------*/
-int main(void)
-{
+int main(void) {
   board_init();
 
   // init device stack on configured roothub port
@@ -61,8 +60,7 @@ int main(void)
     board_init_after_tusb();
   }
 
-  while (1)
-  {
+  while (1) {
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
@@ -73,42 +71,37 @@ int main(void)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   blink_interval_ms = BLINK_MOUNTED;
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   blink_interval_ms = BLINK_NOT_MOUNTED;
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   blink_interval_ms = BLINK_SUSPENDED;
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
+void tud_resume_cb(void) {
   blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
+void led_blinking_task(void) {
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
   // Blink every interval ms
-  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
 
   board_led_write(led_state);
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index d86ecc0a2..5f0653646 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -239,7 +239,7 @@ function(family_configure_common TARGET RTOS)
       if (NOT TARGET segger_rtt)
         add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
         target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
-        #target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
+#        target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
       endif()
       target_link_libraries(${TARGET} PUBLIC segger_rtt)
     endif ()
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index 0fd85988a..cfd5b7032 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -72,13 +72,11 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB1_IRQHandler(void)
-{
+void USB1_IRQHandler(void) {
   tud_int_handler(1);
 }
 
@@ -92,8 +90,7 @@ settings:
 sources:
 - {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
 ******************************************************************/
-void BootClockFROHF96M(void)
-{
+void BootClockFROHF96M(void) {
   /*!< Set up the clock sources */
   /*!< Set up FRO */
   POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on  */
@@ -116,8 +113,7 @@ void BootClockFROHF96M(void)
   SystemCoreClock = 96000000U;
 }
 
-void board_init(void)
-{
+void board_init(void) {
   // Enable IOCON clock
   CLOCK_EnableClock(kCLOCK_Iocon);
 
@@ -138,7 +134,7 @@ void board_init(void)
 
   // LED
   IOCON_PinMuxSet(IOCON, LED_PORT, LED_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 1};
+  gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 1};
   GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
 
   board_led_write(0);
@@ -157,7 +153,7 @@ void board_init(void)
 
   // Button
   IOCON_PinMuxSet(IOCON, BUTTON_PORT, BUTTON_PIN, IOCON_PIO_DIG_FUNC0_EN);
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
   GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
 
 #ifdef UART_DEV
@@ -170,8 +166,8 @@ void board_init(void)
   usart_config_t uart_config;
   USART_GetDefaultConfig(&uart_config);
   uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
-  uart_config.enableTx     = true;
-  uart_config.enableRx     = true;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
   USART_Init(UART_DEV, &uart_config, 12000000);
 #endif
 
@@ -250,9 +246,8 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 
 #ifdef NEOPIXEL_PIN
   if (state) {
@@ -266,33 +261,50 @@ void board_led_write(bool state)
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // active low
   return BUTTON_STATE_ACTIVE == GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+int board_uart_write(void const* buf, int len) {
+  USART_WriteBlocking(UART_DEV, (uint8_t const*) buf, len);
   return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
+
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 75dabfe5a..21c57fc1f 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -1,9 +1,5 @@
 include_guard()
 
-if (NOT BOARD)
-  message(FATAL_ERROR "BOARD not specified")
-endif ()
-
 set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
@@ -30,9 +26,20 @@ set(HOST_PORT $<NOT:${PORT}>)
 function(add_board_target BOARD_TARGET)
   if (TARGET ${BOARD_TARGET})
     return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
   endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
 
   add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     # driver
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/common/fsl_common_arm.c
@@ -44,12 +51,27 @@ function(add_board_target BOARD_TARGET)
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
     )
-
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
     CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
     BOARD_TUD_RHPORT=${PORT}
     BOARD_TUH_RHPORT=${HOST_PORT}
+    __STARTUP_CLEAR_BSS
     )
+
   # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
   if (PORT EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
@@ -65,42 +87,17 @@ function(add_board_target BOARD_TARGET)
       )
   endif ()
 
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${TOP}/lib/sct_neopixel
-    # driver
-    ${SDK_DIR}/drivers/common
-    ${SDK_DIR}/drivers/flexcomm
-    ${SDK_DIR}/drivers/lpc_iocon
-    ${SDK_DIR}/drivers/lpc_gpio
-    ${SDK_DIR}/drivers/lpuart
-    ${SDK_DIR}/drivers/sctimer
-    # mcu
-    ${CMSIS_DIR}/CMSIS/Core/Include
-    ${SDK_DIR}/devices/${MCU_VARIANT}
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-    )
-
   update_board(${BOARD_TARGET})
 
-  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
-    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
-  endif ()
-
-  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
-    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
-  endif ()
-
-  target_sources(${BOARD_TARGET} PUBLIC
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     target_link_options(${BOARD_TARGET} PUBLIC
-      # linker file
       "LINKER:--script=${LD_FILE_GNU}"
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
       )
   elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
     target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index f4ed09d83..022904a3a 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -239,7 +239,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(ep_cmd_sts_t* ep_cs, bool is_
   return is_highspeed ? (ep_cs[0].cmd_sts.type && !ep_cs[0].cmd_sts.rf_tv) : ep_cs->cmd_sts.type;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool ep_is_bulk(ep_cmd_sts_t* ep_cs) {
+TU_ATTR_ALWAYS_INLINE TU_ATTR_UNUSED static inline bool ep_is_bulk(ep_cmd_sts_t* ep_cs) {
   return (ep_cs[0].cmd_sts.type == 0) && (ep_cs[0].cmd_sts.rf_tv == 0);
 }
 
-- 
cgit v1.3.1


From 0f3d6c61b563f8776d6e9f90a8b459a513f79fc1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Apr 2024 12:04:08 +0700
Subject: port clang stm32: f1, f2, f3

---
 .github/workflows/build_arm.yml                    |   1 -
 .github/workflows/cmake_arm.yml                    |   4 +
 hw/bsp/stm32f1/family.cmake                        |  26 +-
 hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake  |  10 +
 hw/bsp/stm32f2/boards/stm32f207nucleo/board.h      |  57 ++++
 .../boards/stm32f207nucleo/stm32f207nucleo.c       | 214 ------------
 hw/bsp/stm32f2/family.c                            | 150 +++++++++
 hw/bsp/stm32f2/family.cmake                        | 112 +++++++
 hw/bsp/stm32f3/boards/stm32f303disco/board.cmake   |  10 +
 hw/bsp/stm32f3/boards/stm32f303disco/board.h       |  61 ++++
 .../stm32f3/boards/stm32f303disco/stm32f303disco.c | 216 -------------
 .../boards/stm32f303disco/stm32f3xx_hal_conf.h     | 357 ---------------------
 hw/bsp/stm32f3/family.c                            | 152 +++++++++
 hw/bsp/stm32f3/family.cmake                        | 110 +++++++
 hw/bsp/stm32f3/stm32f3xx_hal_conf.h                | 357 +++++++++++++++++++++
 src/portable/synopsys/dwc2/dcd_dwc2.c              |   8 +-
 16 files changed, 1043 insertions(+), 802 deletions(-)
 create mode 100644 hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake
 create mode 100644 hw/bsp/stm32f2/boards/stm32f207nucleo/board.h
 delete mode 100644 hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
 create mode 100644 hw/bsp/stm32f2/family.c
 create mode 100644 hw/bsp/stm32f2/family.cmake
 create mode 100644 hw/bsp/stm32f3/boards/stm32f303disco/board.cmake
 create mode 100644 hw/bsp/stm32f3/boards/stm32f303disco/board.h
 delete mode 100644 hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
 delete mode 100644 hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
 create mode 100644 hw/bsp/stm32f3/family.c
 create mode 100644 hw/bsp/stm32f3/family.cmake
 create mode 100644 hw/bsp/stm32f3/stm32f3xx_hal_conf.h

(limited to 'src')

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 9f3270c91..12e6615ea 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -41,7 +41,6 @@ jobs:
         - 'lpc51'
         - 'mm32 msp432e4'
         - 'samd11 same5x saml2x'
-        - 'stm32f2 stm32f3'
         - 'stm32l0 stm32wb'
         - 'tm4c123 xmc4000'
     steps:
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index bc2a98b59..8eb1e3f74 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -49,6 +49,8 @@ jobs:
           - 'samd51'
           - 'stm32f0'
           - 'stm32f1'
+          - 'stm32f2'
+          - 'stm32f3'
           - 'stm32f4'
           - 'stm32f7'
           - 'stm32g0'
@@ -135,6 +137,8 @@ jobs:
           - 'samd51'
           - 'stm32f0'
           - 'stm32f1'
+          - 'stm32f2'
+          - 'stm32f3'
           - 'stm32f4'
           - 'stm32f7'
           - 'stm32g0'
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
index 6657c85ce..cf7e8e9b1 100644
--- a/hw/bsp/stm32f1/family.cmake
+++ b/hw/bsp/stm32f1/family.cmake
@@ -1,9 +1,5 @@
 include_guard()
 
-if (NOT BOARD)
-  message(FATAL_ERROR "BOARD not specified")
-endif ()
-
 set(ST_FAMILY f1)
 set(ST_PREFIX stm32${ST_FAMILY}xx)
 
@@ -29,8 +25,14 @@ function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
     # Startup & Linker script
     set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
     set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
+    set(LD_FILE_Clang ${LD_FILE_GNU})
+    if (NOT DEFINED LD_FILE_IAR)
+      set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+    endif ()
+
     add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
@@ -47,10 +49,8 @@ function(add_board_target BOARD_TARGET)
       ${ST_CMSIS}/Include
       ${ST_HAL_DRIVER}/Inc
       )
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      )
+    #target_compile_options(${BOARD_TARGET} PUBLIC)
+    #target_compile_definitions(${BOARD_TARGET} PUBLIC)
 
     update_board(${BOARD_TARGET})
 
@@ -58,9 +58,11 @@ function(add_board_target BOARD_TARGET)
       target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--script=${LD_FILE_GNU}"
         -nostartfiles
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_Clang}"
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
       target_link_options(${BOARD_TARGET} PUBLIC
@@ -106,5 +108,5 @@ function(family_configure_example TARGET RTOS)
 
   # Flashing
   family_flash_stlink(${TARGET})
-  #family_flash_jlink(${TARGET})
+  family_flash_jlink(${TARGET})
 endfunction()
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake
new file mode 100644
index 000000000..8f78e6295
--- /dev/null
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f207xx)
+set(JLINK_DEVICE stm32f207zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F207ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F207xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h
new file mode 100644
index 000000000..3301ede27
--- /dev/null
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h
@@ -0,0 +1,57 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (HSE)
+  *            SYSCLK(Hz)                     = 120000000
+  *            HCLK(Hz)                       = 120000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 4
+  *            APB2 Prescaler                 = 2
+  *            HSE Frequency(Hz)              = 8000000
+  *            PLL_M                          = HSE_VALUE/1000000
+  *            PLL_N                          = 240
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 5
+  *            VDD(V)                         = 3.3
+  *            Flash Latency(WS)              = 3
+  * @param  None
+  * @retval None
+  */
+static inline void SystemClock_Config(void) {
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000;
+  RCC_OscInitStruct.PLL.PLLN = 240;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 5;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+     clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+}
+
+#endif
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
deleted file mode 100644
index dfbe7b743..000000000
--- a/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-
-#include "stm32f2xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-
-  __HAL_RCC_GPIOB_CLK_ENABLE();  // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE();  // Button
-}
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 120000000
-  *            HCLK(Hz)                       = 120000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 4
-  *            APB2 Prescaler                 = 2
-  *            HSE Frequency(Hz)              = 8000000
-  *            PLL_M                          = HSE_VALUE/1000000
-  *            PLL_N                          = 240
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 5
-  *            VDD(V)                         = 3.3
-  *            Flash Latency(WS)              = 3
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
-  RCC_OscInitStruct.PLL.PLLN = 240;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 5;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-     clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
-}
-
-void board_init(void)
-{
-  SystemClock_Config();
-
-  #if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-  #endif
-
-
-  all_rcc_clk_enable();
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure ID pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Enable USB FS Clocks */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  HAL_IncTick();
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  __asm("BKPT #0\n");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/stm32f2/family.c b/hw/bsp/stm32f2/family.c
new file mode 100644
index 000000000..8b1c56423
--- /dev/null
+++ b/hw/bsp/stm32f2/family.c
@@ -0,0 +1,150 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32f2xx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+// enable all LED, Button, Uart, USB clock
+static void all_rcc_clk_enable(void) {
+  __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-
+  __HAL_RCC_GPIOB_CLK_ENABLE();  // LED
+  __HAL_RCC_GPIOC_CLK_ENABLE();  // Button
+}
+
+void board_init(void) {
+  SystemClock_Config();
+
+  #if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+  #endif
+
+  all_rcc_clk_enable();
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  /* Configure DM DP Pins */
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Configure VBUS Pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Configure ID pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Enable USB FS Clocks */
+  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+}
diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake
new file mode 100644
index 000000000..862680bce
--- /dev/null
+++ b/hw/bsp/stm32f2/family.cmake
@@ -0,0 +1,112 @@
+include_guard()
+
+set(ST_FAMILY f2)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F2 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+    set(LD_FILE_Clang ${LD_FILE_GNU})
+    if (NOT DEFINED LD_FILE_IAR)
+      set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+    endif ()
+
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    #target_compile_options(${BOARD_TARGET} PUBLIC)
+    #target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_Clang}"
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F2 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.cmake b/hw/bsp/stm32f3/boards/stm32f303disco/board.cmake
new file mode 100644
index 000000000..7e02a7910
--- /dev/null
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f303xc)
+set(JLINK_DEVICE stm32f303vc)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F303VCTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F303xC
+    )
+endfunction()
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.h b/hw/bsp/stm32f3/boards/stm32f303disco/board.h
new file mode 100644
index 000000000..706149b49
--- /dev/null
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.h
@@ -0,0 +1,61 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              GPIOE
+#define LED_PIN               GPIO_PIN_9
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   1
+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (HSE)
+  *            SYSCLK(Hz)                     = 72000000
+  *            HCLK(Hz)                       = 72000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 2
+  *            APB2 Prescaler                 = 1
+  *            HSE Frequency(Hz)              = 8000000
+  *            HSE PREDIV                     = 1
+  *            PLLMUL                         = RCC_PLL_MUL9 (9)
+  *            Flash Latency(WS)              = 2
+  * @param  None
+  * @retval None
+  */
+static inline void SystemClock_Config(void) {
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Configures the USB clock */
+  HAL_RCCEx_GetPeriphCLKConfig(&RCC_PeriphClkInit);
+  RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+  clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  /* Enable Power Clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+}
+
+#endif
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
deleted file mode 100644
index d6a39a8e2..000000000
--- a/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include "stm32f3xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-// USB defaults to using interrupts 19, 20 and 42, however, this BSP sets the
-// SYSCFG_CFGR1.USB_IT_RMP bit remapping interrupts to 74, 75 and 76.
-
-// FIXME: Do all three need to be handled, or just the LP one?
-// USB high-priority interrupt (Channel 74): Triggered only by a correct
-// transfer event for isochronous and double-buffer bulk transfer to reach
-// the highest possible transfer rate.
-void USB_HP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// USB low-priority interrupt (Channel 75): Triggered by all USB events
-// (Correct transfer, USB reset, etc.). The firmware has to check the
-// interrupt source before serving the interrupt.
-void USB_LP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// USB wakeup interrupt (Channel 76): Triggered by the wakeup event from the USB
-// Suspend mode.
-void USBWakeUp_RMP_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define LED_PORT              GPIOE
-#define LED_PIN               GPIO_PIN_9
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 72000000
-  *            HCLK(Hz)                       = 72000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 2
-  *            APB2 Prescaler                 = 1
-  *            HSE Frequency(Hz)              = 8000000
-  *            HSE PREDIV                     = 1
-  *            PLLMUL                         = RCC_PLL_MUL9 (9)
-  *            Flash Latency(WS)              = 2
-  * @param  None
-  * @retval None
-  */
-static void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef  RCC_PeriphClkInit;
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Configures the USB clock */
-  HAL_RCCEx_GetPeriphCLKConfig(&RCC_PeriphClkInit);
-  RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
-  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-  clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  /* Enable Power Clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-}
-
-void board_init(void)
-{
-  SystemClock_Config();
-
-  #if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-  #endif
-
-  // Remap the USB interrupts
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-  __HAL_REMAPINTERRUPT_USB_ENABLE();
-
-  // LED
-  __HAL_RCC_GPIOE_CLK_ENABLE();
-  GPIO_InitTypeDef  GPIO_InitStruct;
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // Button
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  /* Configure USB DM and DP pins */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF14_USB;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable USB clock
-  __HAL_RCC_USB_CLK_ENABLE();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  HAL_IncTick();
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
deleted file mode 100644
index 82d3765af..000000000
--- a/hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f3xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_CONF_H
-#define __STM32F3xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_EXTI_MODULE_ENABLED */
-/* #define HAL_HRTIM_MODULE_ENABLED */
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_PWR_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SDADC_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-/* #define HAL_TSC_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-/**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
-  *        Timeout value
-  */
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
-  *        Timeout value
-  */
-#if !defined  (HSI_STARTUP_TIMEOUT)
- #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (40000U)
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  *        - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
-  *        - External clock not generated on EVAL 373
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    (8000000U) /*!< Value of the External oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)   /*!< tick interrupt priority (lowest by default) */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     0U
-#define  DATA_CACHE_ENABLE            0U
-#define  USE_SPI_CRC                  1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS        0U /* COMP register callback disabled      */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SDADC_REGISTER_CALLBACKS       0U /* SDADC register callback disabled     */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS       0U /* HRTIM register callback disabled     */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS       0U /* OPAMP register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_TSC_REGISTER_CALLBACKS         0U /* TSC register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/*#define USE_FULL_ASSERT    1U*/
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f3xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f3xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f3xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f3xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f3xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f3xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f3xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
- #include "stm32f3xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f3xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32f3xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f3xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f3xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f3xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f3xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f3xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f3xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
- #include "stm32f3xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f3xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f3xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f3xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f3xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32f3xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f3xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f3xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f3xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SDADC_MODULE_ENABLED
- #include "stm32f3xx_hal_sdadc.h"
-#endif /* HAL_SDADC_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f3xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f3xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f3xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f3xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32f3xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f3xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f3xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f3xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F3xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f3/family.c b/hw/bsp/stm32f3/family.c
new file mode 100644
index 000000000..7c194a694
--- /dev/null
+++ b/hw/bsp/stm32f3/family.c
@@ -0,0 +1,152 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32f3xx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+// USB defaults to using interrupts 19, 20 and 42, however, this BSP sets the
+// SYSCFG_CFGR1.USB_IT_RMP bit remapping interrupts to 74, 75 and 76.
+
+// FIXME: Do all three need to be handled, or just the LP one?
+// USB high-priority interrupt (Channel 74): Triggered only by a correct
+// transfer event for isochronous and double-buffer bulk transfer to reach
+// the highest possible transfer rate.
+void USB_HP_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+// USB low-priority interrupt (Channel 75): Triggered by all USB events
+// (Correct transfer, USB reset, etc.). The firmware has to check the
+// interrupt source before serving the interrupt.
+void USB_LP_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+// USB wakeup interrupt (Channel 76): Triggered by the wakeup event from the USB
+// Suspend mode.
+void USBWakeUp_RMP_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+
+void board_init(void) {
+  SystemClock_Config();
+
+  #if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+  #endif
+
+  // Remap the USB interrupts
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_REMAPINTERRUPT_USB_ENABLE();
+
+  // LED
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  GPIO_InitTypeDef GPIO_InitStruct;
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  // Button
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  /* Configure USB DM and DP pins */
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF14_USB;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // Enable USB clock
+  __HAL_RCC_USB_CLK_ENABLE();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  HAL_IncTick();
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
+
+void HardFault_Handler(void) {
+  asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void) {
+
+}
diff --git a/hw/bsp/stm32f3/family.cmake b/hw/bsp/stm32f3/family.cmake
new file mode 100644
index 000000000..0a28e480b
--- /dev/null
+++ b/hw/bsp/stm32f3/family.cmake
@@ -0,0 +1,110 @@
+include_guard()
+
+set(ST_FAMILY f3)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F3 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+    set(LD_FILE_Clang ${LD_FILE_GNU})
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    #target_compile_options(${BOARD_TARGET} PUBLIC)
+    #target_compile_definitions(${BOARD_TARGET} PUBLIC)
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_Clang}"
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F3 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f3/stm32f3xx_hal_conf.h b/hw/bsp/stm32f3/stm32f3xx_hal_conf.h
new file mode 100644
index 000000000..82d3765af
--- /dev/null
+++ b/hw/bsp/stm32f3/stm32f3xx_hal_conf.h
@@ -0,0 +1,357 @@
+/**
+  ******************************************************************************
+  * @file    stm32f3xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_HAL_CONF_H
+#define __STM32F3xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED */
+/* #define HAL_CAN_MODULE_ENABLED */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_COMP_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_EXTI_MODULE_ENABLED */
+/* #define HAL_HRTIM_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_OPAMP_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_PWR_MODULE_ENABLED */
+#define HAL_RCC_MODULE_ENABLED
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SDADC_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+/* #define HAL_TIM_MODULE_ENABLED */
+/* #define HAL_TSC_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+  *        Timeout value
+  */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+  *        Timeout value
+  */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+ #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (40000U)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Time out for LSE start up value in ms.
+  */
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  *        - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
+  *        - External clock not generated on EVAL 373
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    (8000000U) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)   /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     0U
+#define  DATA_CACHE_ENABLE            0U
+#define  USE_SPI_CRC                  1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS        0U /* COMP register callback disabled      */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SDADC_REGISTER_CALLBACKS       0U /* SDADC register callback disabled     */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS       0U /* HRTIM register callback disabled     */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS       0U /* OPAMP register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_TSC_REGISTER_CALLBACKS         0U /* TSC register callback disabled       */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/*#define USE_FULL_ASSERT    1U*/
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f3xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f3xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f3xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f3xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f3xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #include "stm32f3xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f3xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f3xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f3xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f3xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f3xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f3xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f3xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f3xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f3xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f3xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+ #include "stm32f3xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f3xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f3xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f3xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SDADC_MODULE_ENABLED
+ #include "stm32f3xx_hal_sdadc.h"
+#endif /* HAL_SDADC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f3xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f3xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f3xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f3xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32f3xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f3xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f3xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f3xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index f17d30f06..c2c09a1fc 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -440,11 +440,15 @@ static void reset_core(dwc2_regs_t* dwc2) {
 }
 
 static bool phy_hs_supported(dwc2_regs_t* dwc2) {
-  // note: esp32 incorrect report its hs_phy_type as utmi
+  (void) dwc2;
+
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  // note: esp32 incorrect report its hs_phy_type as utmi
+  return false;
+#elif !TUD_OPT_HIGH_SPEED
   return false;
 #else
-  return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+  return dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
 #endif
 }
 
-- 
cgit v1.3.1


From 7a3e730dedad4d75f901d3c5ac393e001de69157 Mon Sep 17 00:00:00 2001
From: tyustli <43946994+tyustli@users.noreply.github.com>
Date: Wed, 24 Apr 2024 21:44:03 +0800
Subject: Remove redundant header file includes for the hid class

---
 src/tusb.h | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src')

diff --git a/src/tusb.h b/src/tusb.h
index c9d56d3c3..4f69a1414 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -38,8 +38,6 @@
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
 
-#include "class/hid/hid.h"
-
 //------------- TypeC -------------//
 #if CFG_TUC_ENABLED
   #include "typec/usbc.h"
-- 
cgit v1.3.1


From 5f473d51cf04a7bfeca71bce09a9b3a4c2b2a7d1 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Thu, 18 Apr 2024 20:00:45 +0200
Subject: Fix IAR breakpoint test.

---
 src/common/tusb_verify.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 8aa66b4df..71406dacf 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -76,7 +76,8 @@
 #endif
 
 // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
+    defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
   #define TU_BREAKPOINT() do                                                                                \
   {                                                                                                         \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
-- 
cgit v1.3.1


From 13bde7af403c4f6f3ff6381e23202fc433bffdb2 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 23 Apr 2024 21:36:05 +0200
Subject: uac2: return on clear_feature.

---
 src/class/audio/audio_device.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9050b462a..9ba38a20c 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2015,7 +2015,10 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const
       case TUSB_REQ_SET_INTERFACE:
         return audiod_set_interface(rhport, p_request);
 
-        // Unknown/Unsupported request
+      case TUSB_REQ_CLEAR_FEATURE:
+        return true;
+
+      // Unknown/Unsupported request
       default: TU_BREAKPOINT(); return false;
     }
   }
-- 
cgit v1.3.1


From c2f836279e88d15c2dd818f44f3c563071f36bca Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 23 Apr 2024 21:43:59 +0200
Subject: Disable EPs correctly to clear incomplete transfer.

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c2c09a1fc..692096fc8 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -202,10 +202,10 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
                            (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
   if (dir == TUSB_DIR_OUT) {
-    dwc2->epout[epnum].doepctl |= dxepctl;
+    dwc2->epout[epnum].doepctl = dxepctl;
     dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
   } else {
-    dwc2->epin[epnum].diepctl |= dxepctl | (epnum << DIEPCTL_TXFNUM_Pos);
+    dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos);
     dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
   }
 }
@@ -280,10 +280,17 @@ static void bus_reset(uint8_t rhport) {
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
+  // 2. Disable all IN endpoints
+  for (uint8_t n = 0; n < ep_count; n++) {
+    if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
+      dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+    }
+  }
+
   fifo_flush_tx(dwc2, 0x10); // all tx fifo
   fifo_flush_rx(dwc2);
 
-  // 2. Set up interrupt mask
+  // 3. Set up interrupt mask
   dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
   dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
   dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
@@ -704,11 +711,15 @@ void dcd_edpt_close_all(uint8_t rhport) {
 
   for (uint8_t n = 1; n < ep_count; n++) {
     // disable OUT endpoint
-    dwc2->epout[n].doepctl = 0;
+    if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) {
+      dwc2->epout[n].doepctl |= DOEPCTL_SNAK | DOEPCTL_EPDIS;
+    }
     xfer_status[n][TUSB_DIR_OUT].max_size = 0;
 
     // disable IN endpoint
-    dwc2->epin[n].diepctl = 0;
+    if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
+      dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+    }
     xfer_status[n][TUSB_DIR_IN].max_size = 0;
   }
 
-- 
cgit v1.3.1


From 2e995d7cf4b2971e3ca7167a097b99832c8d61ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 Apr 2024 20:23:40 +0700
Subject: adding support for esp32 for use with max3421e host

---
 examples/device/board_test/src/tusb_config.h       |  2 +-
 examples/device/cdc_msc_freertos/src/main.c        |  6 +--
 examples/device/cdc_msc_freertos/src/tusb_config.h |  2 +-
 examples/device/hid_composite_freertos/src/main.c  |  6 +--
 .../hid_composite_freertos/src/tusb_config.h       |  2 +-
 examples/device/video_capture/src/main.c           |  4 +-
 examples/device/video_capture/src/tusb_config.h    |  2 +-
 examples/device/video_capture_2ch/src/main.c       |  4 +-
 .../device/video_capture_2ch/src/tusb_config.h     |  2 +-
 examples/host/cdc_msc_hid_freertos/src/cdc_app.c   |  2 +-
 examples/host/cdc_msc_hid_freertos/src/main.c      |  6 +--
 .../host/cdc_msc_hid_freertos/src/tusb_config.h    |  2 +-
 hw/bsp/board_api.h                                 |  2 +-
 .../boards/adafruit_feather_esp32_v2/board.cmake   |  2 +
 .../boards/adafruit_feather_esp32_v2/board.h       | 53 ++++++++++++++++++++++
 hw/bsp/espressif/boards/family.c                   | 19 ++++----
 .../components/tinyusb_src/CMakeLists.txt          | 12 +----
 hw/bsp/espressif/family.cmake                      |  6 +--
 src/common/tusb_mcu.h                              |  5 +-
 src/portable/analog/max3421/hcd_max3421.c          |  2 +-
 src/tusb_option.h                                  |  2 +
 21 files changed, 94 insertions(+), 49 deletions(-)
 create mode 100644 hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
 create mode 100644 hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h

(limited to 'src')

diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h
index 1a27cc87f..36eafe807 100644
--- a/examples/device/board_test/src/tusb_config.h
+++ b/examples/device/board_test/src/tusb_config.h
@@ -49,7 +49,7 @@
 #endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index e94e8eaec..607d40270 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -30,7 +30,7 @@
 #include "bsp/board_api.h"
 #include "tusb.h"
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -111,14 +111,14 @@ int main(void) {
 #endif
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if !TUP_MCU_ESPRESSIF
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 void app_main(void) {
   main();
 }
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index 91efe7d40..e743c9148 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -59,7 +59,7 @@
 #endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index ff2cb635e..2bd545bc2 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -31,7 +31,7 @@
 #include "tusb.h"
 #include "usb_descriptors.h"
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -113,14 +113,14 @@ int main(void)
   xTimerStart(blinky_tm, 0);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if !TUP_MCU_ESPRESSIF
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 void app_main(void)
 {
   main();
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 3ba9bf311..0689e0f23 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -59,7 +59,7 @@
 #endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 2a2b0961f..ddb51e03a 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -288,7 +288,7 @@ void led_blinking_task(void* param) {
 #define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
 #define VIDEO_STACK_SIZE    (configMINIMAL_STACK_SIZE*4)
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
   #define USBD_STACK_SIZE     4096
   int main(void);
   void app_main(void) {
@@ -344,7 +344,7 @@ void freertos_init_task(void) {
   #endif
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-  #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  #if !TUP_MCU_ESPRESSIF
   vTaskStartScheduler();
   #endif
 }
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index bdfc37d87..21483a2da 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -58,7 +58,7 @@
 #endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c
index eb1cf2580..e8c2ec6b0 100644
--- a/examples/device/video_capture_2ch/src/main.c
+++ b/examples/device/video_capture_2ch/src/main.c
@@ -296,7 +296,7 @@ void led_blinking_task(void* param) {
 #define BLINKY_STACK_SIZE   configMINIMAL_STACK_SIZE
 #define VIDEO_STACK_SIZE    (configMINIMAL_STACK_SIZE*4)
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
   #define USBD_STACK_SIZE     4096
   int main(void);
   void app_main(void) {
@@ -352,7 +352,7 @@ void freertos_init_task(void) {
   #endif
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-  #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  #if !TUP_MCU_ESPRESSIF
   vTaskStartScheduler();
   #endif
 }
diff --git a/examples/device/video_capture_2ch/src/tusb_config.h b/examples/device/video_capture_2ch/src/tusb_config.h
index fe66d63b5..43c7dfc90 100644
--- a/examples/device/video_capture_2ch/src/tusb_config.h
+++ b/examples/device/video_capture_2ch/src/tusb_config.h
@@ -58,7 +58,7 @@
 #endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
index 7d246af67..f3495ab28 100644
--- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -27,7 +27,7 @@
 #include "tusb.h"
 #include "bsp/board_api.h"
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 // ESP-IDF need "freertos/" prefix in include path.
 // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index 069cbdc90..a6cb4d460 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -30,7 +30,7 @@
 #include "bsp/board_api.h"
 #include "tusb.h"
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -107,14 +107,14 @@ int main(void) {
   xTimerStart(blinky_tm, 0);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if !TUP_MCU_ESPRESSIF
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 void app_main(void) {
   main();
 }
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
index 35de5ee50..0aab2cd2f 100644
--- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -44,7 +44,7 @@
 #endif
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
 #define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index f21a32371..eee9ed9c5 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -39,7 +39,7 @@ extern "C" {
 #include "tusb.h"
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if TUP_MCU_ESPRESSIF
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
new file mode 100644
index 000000000..18c956714
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32")
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h
new file mode 100644
index 000000000..0c53df06b
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          0
+#define NEOPIXEL_POWER_PIN    2
+#define NEOPIXEL_POWER_STATE  1
+
+#define BUTTON_PIN            38
+#define BUTTON_STATE_ACTIVE   0
+
+// SPI for USB host shield
+#define MAX3421_SPI_HOST SPI3_HOST
+#define MAX3421_SCK_PIN  5
+#define MAX3421_MOSI_PIN 19
+#define MAX3421_MISO_PIN 21
+#define MAX3421_CS_PIN   33
+#define MAX3421_INTR_PIN 15
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 5599d1504..02e478a0c 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -30,8 +30,12 @@
 #include "esp_rom_gpio.h"
 #include "esp_mac.h"
 #include "hal/gpio_ll.h"
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 #include "hal/usb_hal.h"
 #include "soc/usb_periph.h"
+static void configure_pins(usb_hal_context_t* usb);
+#endif
 
 #include "driver/gpio.h"
 #include "driver/uart.h"
@@ -56,7 +60,6 @@ static led_strip_handle_t led_strip;
 static void max3421_init(void);
 #endif
 
-static void configure_pins(usb_hal_context_t* usb);
 
 //--------------------------------------------------------------------+
 // Implementation
@@ -100,7 +103,6 @@ void board_init(void) {
   };
 
   ESP_ERROR_CHECK(led_strip_new_rmt_device(&strip_config, &rmt_config, &led_strip));
-
   led_strip_clear(led_strip); // off
 #endif
 
@@ -109,6 +111,7 @@ void board_init(void) {
   gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
   gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
 
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   // USB Controller Hal init
   periph_module_reset(PERIPH_USB_MODULE);
   periph_module_enable(PERIPH_USB_MODULE);
@@ -118,12 +121,14 @@ void board_init(void) {
   };
   usb_hal_init(&hal);
   configure_pins(&hal);
+#endif
 
 #if CFG_TUH_ENABLED && CFG_TUH_MAX3421
   max3421_init();
 #endif
 }
 
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 static void configure_pins(usb_hal_context_t* usb) {
   /* usb_periph_iopins currently configures USB_OTG as USB Device.
    * Introduce additional parameters in usb_hal_context_t when adding support
@@ -153,6 +158,7 @@ static void configure_pins(usb_hal_context_t* usb) {
     gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
   }
 }
+#endif
 
 //--------------------------------------------------------------------+
 // Board porting API
@@ -208,15 +214,12 @@ SemaphoreHandle_t max3421_intr_sem;
 
 static void IRAM_ATTR max3421_isr_handler(void* arg) {
   (void) arg; // arg is gpio num
-  gpio_set_level(13, 1);
 
   BaseType_t xHigherPriorityTaskWoken = pdFALSE;
   xSemaphoreGiveFromISR(max3421_intr_sem, &xHigherPriorityTaskWoken);
   if (xHigherPriorityTaskWoken) {
     portYIELD_FROM_ISR();
   }
-
-  gpio_set_level(13, 0);
 }
 
 static void max3421_intr_task(void* param) {
@@ -250,16 +253,12 @@ static void max3421_init(void) {
 
   spi_device_interface_config_t max3421_cfg = {
       .mode = 0,
-      .clock_speed_hz = 26000000,
+      .clock_speed_hz = 20000000, // S2/S3 can work with 26 Mhz, but esp32 seems only work up to 20 Mhz
       .spics_io_num = -1, // manual control CS
       .queue_size = 1
   };
   ESP_ERROR_CHECK(spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi));
 
-  // debug
-  gpio_set_direction(13, GPIO_MODE_OUTPUT);
-  gpio_set_level(13, 0);
-
   // Interrupt pin
   max3421_intr_sem = xSemaphoreCreateBinary();
   xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES - 2, NULL);
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index abe276910..8bdb3802e 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -5,17 +5,7 @@ set(includes_public)
 set(compile_options)
 set(tusb_src "${CMAKE_CURRENT_SOURCE_DIR}/../../../../../src")
 
-if(target STREQUAL "esp32s3")
-  set(tusb_mcu "OPT_MCU_ESP32S3")
-elseif(target STREQUAL "esp32s2")
-  set(tusb_mcu "OPT_MCU_ESP32S2")
-else()
-  # CONFIG_TINYUSB dependency has been guaranteed by Kconfig logic,
-  # So it's not possible that cmake goes here
-  message(FATAL_ERROR "TinyUSB is not support on ${target}.")
-  return()
-endif()
-
+string(TOUPPER OPT_MCU_${target} tusb_mcu)
 list(APPEND compile_definitions
   CFG_TUSB_MCU=${tusb_mcu}
   CFG_TUSB_OS=OPT_OS_FREERTOS
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
index 92a9bcb04..eb97401c3 100644
--- a/hw/bsp/espressif/family.cmake
+++ b/hw/bsp/espressif/family.cmake
@@ -3,11 +3,7 @@ cmake_minimum_required(VERSION 3.5)
 # Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
 include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
 
-if(IDF_TARGET STREQUAL "esp32s2")
-  set(FAMILY_MCUS ESP32S2)
-elseif(IDF_TARGET STREQUAL "esp32s3")
-  set(FAMILY_MCUS ESP32S3)
-endif()
+string(TOUPPER ${IDF_TARGET} FAMILY_MCUS)
 
 # Add example src and bsp directories
 set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 0ae2573cd..2c4d7461d 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -329,6 +329,9 @@
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    6
 
+#elif TU_CHECK_MCU(OPT_MCU_ESP32) && (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421))
+  #error "MCUs are only supported with CFG_TUH_MAX3421 enabled"
+
 //--------------------------------------------------------------------+
 // Dialog
 //--------------------------------------------------------------------+
@@ -426,7 +429,7 @@
 #define TUP_MCU_MULTIPLE_CORE 0
 #endif
 
-#ifndef TUP_DCD_ENDPOINT_MAX
+#if CFG_TUD_ENABLED && !defined(TUP_DCD_ENDPOINT_MAX)
   #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define TUP_DCD_ENDPOINT_MAX    8
 #endif
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 39afb7505..053169bf2 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -484,8 +484,8 @@ bool hcd_init(uint8_t rhport) {
 
   // v1 is 0x01, v2 is 0x12, v3 is 0x13
   uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
-  TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
   TU_LOG2_HEX(revision);
+  TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
 
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cbcb69edd..25412d432 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -119,6 +119,8 @@
 // Espressif
 #define OPT_MCU_ESP32S2           900 ///< Espressif ESP32-S2
 #define OPT_MCU_ESP32S3           901 ///< Espressif ESP32-S3
+#define OPT_MCU_ESP32             902 ///< Espressif ESP32 (for host max3421e)
+#define TUP_MCU_ESPRESSIF         (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU
 
 // Dialog
 #define OPT_MCU_DA1469X          1000 ///< Dialog Semiconductor DA1469x
-- 
cgit v1.3.1


From 03ccc8d8dfe21fc158fc5eb8a4f3f90f425f8a3b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 Apr 2024 20:41:44 +0700
Subject: revert a change in tusb_mcu

---
 src/common/tusb_mcu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 2c4d7461d..00526bdba 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -429,7 +429,7 @@
 #define TUP_MCU_MULTIPLE_CORE 0
 #endif
 
-#if CFG_TUD_ENABLED && !defined(TUP_DCD_ENDPOINT_MAX)
+#if !defined(TUP_DCD_ENDPOINT_MAX)
   #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define TUP_DCD_ENDPOINT_MAX    8
 #endif
-- 
cgit v1.3.1


From 223ce56625474764dc00229c44731858abcf4f29 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 Apr 2024 00:10:57 +0700
Subject: - add esp32 c3, c6 mcu option - skip breakpoint for espressif riscv

---
 examples/host/cdc_msc_hid_freertos/src/main.c | 5 ++++-
 src/common/tusb_mcu.h                         | 4 ++--
 src/common/tusb_verify.h                      | 2 +-
 src/portable/analog/max3421/hcd_max3421.c     | 2 ++
 src/tusb_option.h                             | 2 ++
 5 files changed, 11 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index a6cb4d460..fa799aede 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -126,7 +126,10 @@ static void usb_host_task(void *param) {
   (void) param;
 
   // init host stack on configured roothub port
-  tuh_init(BOARD_TUH_RHPORT);
+  if (!tuh_init(BOARD_TUH_RHPORT)) {
+    printf("Failed to init USB Host Stack\r\n");
+    vTaskSuspend(NULL);
+  }
 
   if (board_init_after_tusb) {
     board_init_after_tusb();
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 00526bdba..5a567f2d5 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -429,8 +429,8 @@
 #define TUP_MCU_MULTIPLE_CORE 0
 #endif
 
-#if !defined(TUP_DCD_ENDPOINT_MAX)
-  #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
+#if !defined(TUP_DCD_ENDPOINT_MAX) && defined(CFG_TUD_ENABLED) && CFG_TUD_ENABLED
+#warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define TUP_DCD_ENDPOINT_MAX    8
 #endif
 
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 71406dacf..0a9549c99 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -84,7 +84,7 @@
     if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */            \
   } while(0)
 
-#elif defined(__riscv)
+#elif defined(__riscv) && !TUP_MCU_ESPRESSIF
   #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
 
 #elif defined(_mips)
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 053169bf2..4dc93d2d8 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -479,6 +479,8 @@ bool hcd_init(uint8_t rhport) {
   _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
 #endif
 
+  // NOTE: driver does not seem to work without nRST pin signal
+
   // full duplex, interrupt negative edge
   reg_write(rhport, PINCTL_ADDR, _tuh_cfg.pinctl | PINCTL_FDUPSPI, false);
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 25412d432..3ead20ee7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -120,6 +120,8 @@
 #define OPT_MCU_ESP32S2           900 ///< Espressif ESP32-S2
 #define OPT_MCU_ESP32S3           901 ///< Espressif ESP32-S3
 #define OPT_MCU_ESP32             902 ///< Espressif ESP32 (for host max3421e)
+#define OPT_MCU_ESP32C3           903 ///< Espressif ESP32-C3
+#define OPT_MCU_ESP32C6           904 ///< Espressif ESP32-C6
 #define TUP_MCU_ESPRESSIF         (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU
 
 // Dialog
-- 
cgit v1.3.1


From 7fb8d3341ce2feb46b0bce0bef069d31cf080168 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 26 Apr 2024 13:40:13 +0200
Subject: use separate buffer for ctrl transfer.

---
 src/class/hid/hid_device.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index ba77d3c5f..a5c709d4c 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -52,7 +52,7 @@ typedef struct
 
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE];
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t set_report_buf[CFG_TUD_HID_EP_BUFSIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE];
 
   // TODO save hid descriptor since host can specifically request this after enumeration
   // Note: HID descriptor may be not available from application after enumeration
@@ -296,7 +296,7 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           uint8_t const report_type = tu_u16_high(request->wValue);
           uint8_t const report_id   = tu_u16_low(request->wValue);
 
-          uint8_t* report_buf = p_hid->epin_buf;
+          uint8_t* report_buf = p_hid->ctrl_buf;
           uint16_t req_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
 
           uint16_t xferlen = 0;
@@ -313,22 +313,22 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           xferlen += tud_hid_get_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, req_len);
           TU_ASSERT( xferlen > 0 );
 
-          tud_control_xfer(rhport, request, p_hid->epin_buf, xferlen);
+          tud_control_xfer(rhport, request, p_hid->ctrl_buf, xferlen);
         }
       break;
 
       case  HID_REQ_CONTROL_SET_REPORT:
         if ( stage == CONTROL_STAGE_SETUP )
         {
-          TU_VERIFY(request->wLength <= sizeof(p_hid->set_report_buf));
-          tud_control_xfer(rhport, request, p_hid->set_report_buf, request->wLength);
+          TU_VERIFY(request->wLength <= sizeof(p_hid->ctrl_buf));
+          tud_control_xfer(rhport, request, p_hid->ctrl_buf, request->wLength);
         }
         else if ( stage == CONTROL_STAGE_ACK )
         {
           uint8_t const report_type = tu_u16_high(request->wValue);
           uint8_t const report_id   = tu_u16_low(request->wValue);
 
-          uint8_t const* report_buf = p_hid->set_report_buf;
+          uint8_t const* report_buf = p_hid->ctrl_buf;
           uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
 
           // If host request a specific Report ID, extract report ID in buffer before invoking callback
-- 
cgit v1.3.1


From 1661acf82f8e01392de0c18c3472d016679c707d Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 26 Apr 2024 13:42:20 +0200
Subject: Add missing alignment.

---
 src/class/hid/hid_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index a5c709d4c..c66a4597e 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -46,9 +46,9 @@ typedef struct
   uint8_t ep_out;        // optional Out endpoint
   uint8_t itf_protocol;  // Boot mouse or keyboard
 
-  uint8_t protocol_mode; // Boot (0) or Report protocol (1)
-  uint8_t idle_rate;     // up to application to handle idle rate
   uint16_t report_desc_len;
+  CFG_TUSB_MEM_ALIGN uint8_t protocol_mode; // Boot (0) or Report protocol (1)
+  CFG_TUSB_MEM_ALIGN uint8_t idle_rate;     // up to application to handle idle rate
 
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE];
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE];
-- 
cgit v1.3.1


From 4af67dd0078009c1378612440afd5806e84a81c7 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 26 Apr 2024 17:45:14 +0200
Subject: Simplify transfer failure cb.

---
 .clang-format              | 6 ++++++
 src/class/hid/hid_device.c | 6 ++++--
 src/class/hid/hid_device.h | 3 +--
 3 files changed, 11 insertions(+), 4 deletions(-)
 create mode 100644 .clang-format

(limited to 'src')

diff --git a/.clang-format b/.clang-format
new file mode 100644
index 000000000..4369c29fe
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,6 @@
+---
+BreakBeforeBraces: Linux
+ColumnLimit: '200'
+ReflowComments: 'true'
+
+...
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 564ad12f6..637bc7f61 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -381,6 +381,8 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
 
 bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
+  (void) result;
+
   uint8_t instance = 0;
   hidd_interface_t * p_hid = _hidd_itf;
 
@@ -396,9 +398,9 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   if (XFER_RESULT_SUCCESS != result)
   {
     // Inform application about the issue
-    if (tud_hid_report_issue_cb)
+    if (tud_hid_report_fail_cb)
     {
-      tud_hid_report_issue_cb(instance, ep_addr, result, (uint16_t) xferred_bytes);
+      tud_hid_report_fail_cb(instance, ep_addr, (uint16_t) xferred_bytes);
     }
 
     // Allow a new transfer to be received if issue happened on an OUT endpoint
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index a934753eb..9206d67f8 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -119,7 +119,7 @@ TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
 TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
 
 // Invoked when a transfer wasn't successful
-TU_ATTR_WEAK void tud_hid_report_issue_cb(uint8_t instance, uint8_t ep_addr, xfer_result_t result, uint16_t len);
+TU_ATTR_WEAK void tud_hid_report_fail_cb(uint8_t instance, uint8_t ep_addr, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Inline Functions
@@ -413,7 +413,6 @@ uint16_t hidd_open            (uint8_t rhport, tusb_desc_interface_t const * itf
 bool     hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 bool     hidd_xfer_cb         (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
 
-void test(void);
 
 #ifdef __cplusplus
  }
-- 
cgit v1.3.1


From 24339dbcce5c5374e0abedf605471753484e4a56 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 26 Apr 2024 18:01:02 +0200
Subject: Code format.

---
 src/class/hid/hid_device.c | 355 +++++++++++++++++++--------------------------
 1 file changed, 153 insertions(+), 202 deletions(-)

(limited to 'src')

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 45c10862b..ada01582e 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -39,12 +39,11 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_in;
-  uint8_t ep_out;        // optional Out endpoint
-  uint8_t itf_protocol;  // Boot mouse or keyboard
+  uint8_t ep_out;       // optional Out endpoint
+  uint8_t itf_protocol; // Boot mouse or keyboard
 
   uint16_t report_desc_len;
   CFG_TUSB_MEM_ALIGN uint8_t protocol_mode; // Boot (0) or Report protocol (1)
@@ -56,7 +55,7 @@ typedef struct
 
   // TODO save hid descriptor since host can specifically request this after enumeration
   // Note: HID descriptor may be not available from application after enumeration
-  tusb_hid_descriptor_hid_t const * hid_descriptor;
+  tusb_hid_descriptor_hid_t const *hid_descriptor;
 } hidd_interface_t;
 
 CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID];
@@ -64,12 +63,12 @@ CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID];
 /*------------- Helpers -------------*/
 static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
 {
-	for (uint8_t i=0; i < CFG_TUD_HID; i++ )
-	{
-		if ( itf_num == _hidd_itf[i].itf_num ) return i;
-	}
+  for (uint8_t i = 0; i < CFG_TUD_HID; i++) {
+    if (itf_num == _hidd_itf[i].itf_num)
+      return i;
+  }
 
-	return 0xFF;
+  return 0xFF;
 }
 
 //--------------------------------------------------------------------+
@@ -82,37 +81,29 @@ bool tud_hid_n_ready(uint8_t instance)
   return tud_ready() && (ep_in != 0) && !usbd_edpt_busy(rhport, ep_in);
 }
 
-bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint16_t len)
+bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const *report, uint16_t len)
 {
   uint8_t const rhport = 0;
-  hidd_interface_t * p_hid = &_hidd_itf[instance];
+  hidd_interface_t *p_hid = &_hidd_itf[instance];
 
   // claim endpoint
-  TU_VERIFY( usbd_edpt_claim(rhport, p_hid->ep_in) );
+  TU_VERIFY(usbd_edpt_claim(rhport, p_hid->ep_in));
 
   // prepare data
-  if (report_id)
-  {
+  if (report_id) {
     p_hid->epin_buf[0] = report_id;
-    TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len));
+    TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf + 1, CFG_TUD_HID_EP_BUFSIZE - 1, report, len));
     len++;
-  }else
-  {
+  } else {
     TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len));
   }
 
   return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len);
 }
 
-uint8_t tud_hid_n_interface_protocol(uint8_t instance)
-{
-  return _hidd_itf[instance].itf_protocol;
-}
+uint8_t tud_hid_n_interface_protocol(uint8_t instance) { return _hidd_itf[instance].itf_protocol; }
 
-uint8_t tud_hid_n_get_protocol(uint8_t instance)
-{
-  return _hidd_itf[instance].protocol_mode;
-}
+uint8_t tud_hid_n_get_protocol(uint8_t instance) { return _hidd_itf[instance].protocol_mode; }
 
 bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modifier, uint8_t keycode[6])
 {
@@ -121,27 +112,23 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
   report.modifier = modifier;
   report.reserved = 0;
 
-  if ( keycode )
-  {
+  if (keycode) {
     memcpy(report.keycode, keycode, sizeof(report.keycode));
-  }else
-  {
+  } else {
     tu_memclr(report.keycode, 6);
   }
 
   return tud_hid_n_report(instance, report_id, &report, sizeof(report));
 }
 
-bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id,
-                            uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal)
+bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal)
 {
-  hid_mouse_report_t report =
-  {
+  hid_mouse_report_t report = {
     .buttons = buttons,
-    .x       = x,
-    .y       = y,
-    .wheel   = vertical,
-    .pan     = horizontal
+    .x = x,
+    .y = y,
+    .wheel = vertical,
+    .pan = horizontal
   };
 
   return tud_hid_n_report(instance, report_id, &report, sizeof(report));
@@ -149,29 +136,27 @@ bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id,
 
 bool tud_hid_n_abs_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int16_t x, int16_t y, int8_t vertical, int8_t horizontal)
 {
-  hid_abs_mouse_report_t report =
-  {
+  hid_abs_mouse_report_t report = {
     .buttons = buttons,
-    .x       = x,
-    .y       = y,
-    .wheel   = vertical,
-    .pan     = horizontal
+    .x = x,
+    .y = y,
+    .wheel = vertical,
+    .pan = horizontal
   };
   return tud_hid_n_report(instance, report_id, &report, sizeof(report));
 }
 
-bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
-                              int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
-  hid_gamepad_report_t report =
-  {
-    .x       = x,
-    .y       = y,
-    .z       = z,
-    .rz      = rz,
-    .rx      = rx,
-    .ry      = ry,
-    .hat     = hat,
-    .buttons = buttons,
+bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons)
+{
+  hid_gamepad_report_t report = {
+      .x = x,
+      .y = y,
+      .z = z,
+      .rz = rz,
+      .rx = rx,
+      .ry = ry,
+      .hat = hat,
+      .buttons = buttons,
   };
 
   return tud_hid_n_report(instance, report_id, &report, sizeof(report));
@@ -180,67 +165,64 @@ bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
 //--------------------------------------------------------------------+
 // USBD-CLASS API
 //--------------------------------------------------------------------+
-void hidd_init(void) {
+void hidd_init(void)
+{
   hidd_reset(0);
 }
 
-bool hidd_deinit(void) {
+bool hidd_deinit(void)
+{
   return true;
 }
 
 void hidd_reset(uint8_t rhport)
 {
-  (void) rhport;
+  (void)rhport;
   tu_memclr(_hidd_itf, sizeof(_hidd_itf));
 }
 
-uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
- {
+uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
+{
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0);
 
   // len = interface + hid + n*endpoints
-  uint16_t const drv_len =
-      (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
-                                       desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
+  uint16_t const drv_len = (uint16_t)(sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(max_len >= drv_len, 0);
 
   // Find available interface
-  hidd_interface_t * p_hid = NULL;
+  hidd_interface_t *p_hid = NULL;
   uint8_t hid_id;
-  for(hid_id=0; hid_id<CFG_TUD_HID; hid_id++)
-  {
-    if ( _hidd_itf[hid_id].ep_in == 0 )
-    {
+  for (hid_id = 0; hid_id < CFG_TUD_HID; hid_id++) {
+    if (_hidd_itf[hid_id].ep_in == 0) {
       p_hid = &_hidd_itf[hid_id];
       break;
     }
   }
   TU_ASSERT(p_hid, 0);
 
-  uint8_t const *p_desc = (uint8_t const *) desc_itf;
+  uint8_t const *p_desc = (uint8_t const *)desc_itf;
 
   //------------- HID descriptor -------------//
   p_desc = tu_desc_next(p_desc);
   TU_ASSERT(HID_DESC_TYPE_HID == tu_desc_type(p_desc), 0);
-  p_hid->hid_descriptor = (tusb_hid_descriptor_hid_t const *) p_desc;
+  p_hid->hid_descriptor = (tusb_hid_descriptor_hid_t const *)p_desc;
 
   //------------- Endpoint Descriptor -------------//
   p_desc = tu_desc_next(p_desc);
   TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_INTERRUPT, &p_hid->ep_out, &p_hid->ep_in), 0);
 
-  if ( desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT ) p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
+  if (desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT)
+    p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
 
   p_hid->protocol_mode = HID_PROTOCOL_REPORT; // Per Specs: default is report mode
-  p_hid->itf_num       = desc_itf->bInterfaceNumber;
+  p_hid->itf_num = desc_itf->bInterfaceNumber;
 
   // Use offsetof to avoid pointer to the odd/misaligned address
-  p_hid->report_desc_len = tu_unaligned_read16((uint8_t const*) p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength));
+  p_hid->report_desc_len = tu_unaligned_read16((uint8_t const *)p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength));
 
   // Prepare for output endpoint
-  if (p_hid->ep_out)
-  {
-    if ( !usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)) )
-    {
+  if (p_hid->ep_out) {
+    if (!usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf))) {
       TU_LOG_FAILED();
       TU_BREAKPOINT();
     }
@@ -252,144 +234,120 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
+bool hidd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request)
 {
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
 
-  uint8_t const hid_itf = get_index_by_itfnum((uint8_t) request->wIndex);
+  uint8_t const hid_itf = get_index_by_itfnum((uint8_t)request->wIndex);
   TU_VERIFY(hid_itf < CFG_TUD_HID);
 
-  hidd_interface_t* p_hid = &_hidd_itf[hid_itf];
+  hidd_interface_t *p_hid = &_hidd_itf[hid_itf];
 
-  if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD)
-  {
+  if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
     //------------- STD Request -------------//
-    if ( stage == CONTROL_STAGE_SETUP )
-    {
-      uint8_t const desc_type  = tu_u16_high(request->wValue);
-      //uint8_t const desc_index = tu_u16_low (request->wValue);
+    if (stage == CONTROL_STAGE_SETUP) {
+      uint8_t const desc_type = tu_u16_high(request->wValue);
+      // uint8_t const desc_index = tu_u16_low (request->wValue);
 
-      if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID)
-      {
+      if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID) {
         TU_VERIFY(p_hid->hid_descriptor);
-        TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
-      }
-      else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT)
-      {
-        uint8_t const * desc_report = tud_hid_descriptor_report_cb(hid_itf);
-        tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_report, p_hid->report_desc_len);
-      }
-      else
-      {
+        TU_VERIFY(tud_control_xfer(rhport, request, (void *)(uintptr_t)p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
+      } else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT) {
+        uint8_t const *desc_report = tud_hid_descriptor_report_cb(hid_itf);
+        tud_control_xfer(rhport, request, (void *)(uintptr_t)desc_report, p_hid->report_desc_len);
+      } else {
         return false; // stall unsupported request
       }
     }
-  }
-  else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
-  {
+  } else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS) {
     //------------- Class Specific Request -------------//
-    switch( request->bRequest )
-    {
-      case HID_REQ_CONTROL_GET_REPORT:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          uint8_t const report_type = tu_u16_high(request->wValue);
-          uint8_t const report_id   = tu_u16_low(request->wValue);
+    switch (request->bRequest) {
+    case HID_REQ_CONTROL_GET_REPORT:
+      if (stage == CONTROL_STAGE_SETUP) {
+        uint8_t const report_type = tu_u16_high(request->wValue);
+        uint8_t const report_id = tu_u16_low(request->wValue);
 
-          uint8_t* report_buf = p_hid->ctrl_buf;
-          uint16_t req_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
+        uint8_t *report_buf = p_hid->ctrl_buf;
+        uint16_t req_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
 
-          uint16_t xferlen = 0;
+        uint16_t xferlen = 0;
 
-          // If host request a specific Report ID, add ID to as 1 byte of response
-          if ( (report_id != HID_REPORT_TYPE_INVALID) && (req_len > 1) )
-          {
-            *report_buf++ = report_id;
-            req_len--;
+        // If host request a specific Report ID, add ID to as 1 byte of response
+        if ((report_id != HID_REPORT_TYPE_INVALID) && (req_len > 1)) {
+          *report_buf++ = report_id;
+          req_len--;
 
-            xferlen++;
-          }
+          xferlen++;
+        }
 
-          xferlen += tud_hid_get_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, req_len);
-          TU_ASSERT( xferlen > 0 );
+        xferlen += tud_hid_get_report_cb(hid_itf, report_id, (hid_report_type_t)report_type, report_buf, req_len);
+        TU_ASSERT(xferlen > 0);
 
-          tud_control_xfer(rhport, request, p_hid->ctrl_buf, xferlen);
-        }
+        tud_control_xfer(rhport, request, p_hid->ctrl_buf, xferlen);
+      }
       break;
 
-      case  HID_REQ_CONTROL_SET_REPORT:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          TU_VERIFY(request->wLength <= sizeof(p_hid->ctrl_buf));
-          tud_control_xfer(rhport, request, p_hid->ctrl_buf, request->wLength);
-        }
-        else if ( stage == CONTROL_STAGE_ACK )
-        {
-          uint8_t const report_type = tu_u16_high(request->wValue);
-          uint8_t const report_id   = tu_u16_low(request->wValue);
-
-          uint8_t const* report_buf = p_hid->ctrl_buf;
-          uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
-
-          // If host request a specific Report ID, extract report ID in buffer before invoking callback
-          if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0]) )
-          {
-            report_buf++;
-            report_len--;
-          }
-
-          tud_hid_set_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, report_len);
+    case HID_REQ_CONTROL_SET_REPORT:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_VERIFY(request->wLength <= sizeof(p_hid->ctrl_buf));
+        tud_control_xfer(rhport, request, p_hid->ctrl_buf, request->wLength);
+      } else if (stage == CONTROL_STAGE_ACK) {
+        uint8_t const report_type = tu_u16_high(request->wValue);
+        uint8_t const report_id = tu_u16_low(request->wValue);
+
+        uint8_t const *report_buf = p_hid->ctrl_buf;
+        uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
+
+        // If host request a specific Report ID, extract report ID in buffer before invoking callback
+        if ((report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0])) {
+          report_buf++;
+          report_len--;
         }
+
+        tud_hid_set_report_cb(hid_itf, report_id, (hid_report_type_t)report_type, report_buf, report_len);
+      }
       break;
 
-      case HID_REQ_CONTROL_SET_IDLE:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          p_hid->idle_rate = tu_u16_high(request->wValue);
-          if ( tud_hid_set_idle_cb )
-          {
-            // stall request if callback return false
-            TU_VERIFY( tud_hid_set_idle_cb( hid_itf, p_hid->idle_rate) );
-          }
-
-          tud_control_status(rhport, request);
+    case HID_REQ_CONTROL_SET_IDLE:
+      if (stage == CONTROL_STAGE_SETUP) {
+        p_hid->idle_rate = tu_u16_high(request->wValue);
+        if (tud_hid_set_idle_cb) {
+          // stall request if callback return false
+          TU_VERIFY(tud_hid_set_idle_cb(hid_itf, p_hid->idle_rate));
         }
+
+        tud_control_status(rhport, request);
+      }
       break;
 
-      case HID_REQ_CONTROL_GET_IDLE:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          // TODO idle rate of report
-          tud_control_xfer(rhport, request, &p_hid->idle_rate, 1);
-        }
+    case HID_REQ_CONTROL_GET_IDLE:
+      if (stage == CONTROL_STAGE_SETUP) {
+        // TODO idle rate of report
+        tud_control_xfer(rhport, request, &p_hid->idle_rate, 1);
+      }
       break;
 
-      case HID_REQ_CONTROL_GET_PROTOCOL:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          tud_control_xfer(rhport, request, &p_hid->protocol_mode, 1);
-        }
+    case HID_REQ_CONTROL_GET_PROTOCOL:
+      if (stage == CONTROL_STAGE_SETUP) {
+        tud_control_xfer(rhport, request, &p_hid->protocol_mode, 1);
+      }
       break;
 
-      case HID_REQ_CONTROL_SET_PROTOCOL:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          tud_control_status(rhport, request);
-        }
-        else if ( stage == CONTROL_STAGE_ACK )
-        {
-          p_hid->protocol_mode = (uint8_t) request->wValue;
-          if (tud_hid_set_protocol_cb)
-          {
-            tud_hid_set_protocol_cb(hid_itf, p_hid->protocol_mode);
-          }
+    case HID_REQ_CONTROL_SET_PROTOCOL:
+      if (stage == CONTROL_STAGE_SETUP) {
+        tud_control_status(rhport, request);
+      } else if (stage == CONTROL_STAGE_ACK) {
+        p_hid->protocol_mode = (uint8_t)request->wValue;
+        if (tud_hid_set_protocol_cb) {
+          tud_hid_set_protocol_cb(hid_itf, p_hid->protocol_mode);
         }
+      }
       break;
 
-      default: return false; // stall unsupported request
+    default:
+      return false; // stall unsupported request
     }
-  }else
-  {
+  } else {
     return false; // stall unsupported request
   }
 
@@ -398,31 +356,27 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
 
 bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
-  (void) result;
+  (void)result;
 
   uint8_t instance = 0;
-  hidd_interface_t * p_hid = _hidd_itf;
+  hidd_interface_t *p_hid = _hidd_itf;
 
   // Identify which interface to use
-  for (instance = 0; instance < CFG_TUD_HID; instance++)
-  {
+  for (instance = 0; instance < CFG_TUD_HID; instance++) {
     p_hid = &_hidd_itf[instance];
-    if ( (ep_addr == p_hid->ep_out) || (ep_addr == p_hid->ep_in) ) break;
+    if ((ep_addr == p_hid->ep_out) || (ep_addr == p_hid->ep_in))
+      break;
   }
   TU_ASSERT(instance < CFG_TUD_HID);
 
   // Check if there was a problem
-  if (XFER_RESULT_SUCCESS != result)
-  {
-    // Inform application about the issue
-    if (tud_hid_report_fail_cb)
-    {
-      tud_hid_report_fail_cb(instance, ep_addr, (uint16_t) xferred_bytes);
+  if (XFER_RESULT_SUCCESS != result) { // Inform application about the issue
+    if (tud_hid_report_fail_cb) {
+      tud_hid_report_fail_cb(instance, ep_addr, (uint16_t)xferred_bytes);
     }
 
     // Allow a new transfer to be received if issue happened on an OUT endpoint
-    if (ep_addr == p_hid->ep_out)
-    {
+    if (ep_addr == p_hid->ep_out) {
       // Prepare the OUT endpoint to be able to receive a new transfer
       TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)));
     }
@@ -431,17 +385,14 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   }
 
   // Sent report successfully
-  if (ep_addr == p_hid->ep_in)
-  {
-    if (tud_hid_report_complete_cb)
-    {
-      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t) xferred_bytes);
+  if (ep_addr == p_hid->ep_in) {
+    if (tud_hid_report_complete_cb) {
+      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t)xferred_bytes);
     }
   }
   // Received report successfully
-  else if (ep_addr == p_hid->ep_out)
-  {
-    tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_OUTPUT, p_hid->epout_buf, (uint16_t) xferred_bytes);
+  else if (ep_addr == p_hid->ep_out) {
+    tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_OUTPUT, p_hid->epout_buf, (uint16_t)xferred_bytes);
     TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)));
   }
 
-- 
cgit v1.3.1


From 98e85a296deb89dbcc05033bda26e3c9581d535b Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 27 Apr 2024 17:09:05 +0200
Subject: bulk_in: copy buffer to ensure alignment correctness.

---
 src/class/usbtmc/usbtmc_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 4092c37ea..81e969732 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -552,9 +552,10 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     case STATE_TX_INITIATED:
       if(usbtmc_state.transfer_size_remaining >= sizeof(usbtmc_state.ep_bulk_in_buf))
       {
-        // FIXME! This removes const below!
+        // Copy buffer to ensure alignment correctness
+        memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf));
         TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
-            (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf)));
+            usbtmc_state.ep_bulk_in_buf, sizeof(usbtmc_state.ep_bulk_in_buf)));
         usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf);
         usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf);
         usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf);
-- 
cgit v1.3.1


From fdb431b5c70ff605eebda8988e1728e7118b4ab4 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 27 Apr 2024 17:12:00 +0200
Subject: Buffer int msg to ensure alignment and placement correctness.

---
 src/class/usbtmc/usbtmc_device.c | 18 +++++++++++++-----
 src/class/usbtmc/usbtmc_device.h | 17 ++++++-----------
 2 files changed, 19 insertions(+), 16 deletions(-)

(limited to 'src')

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 81e969732..59d9b184e 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -86,6 +86,11 @@ tu_static char logMsg[150];
 // imposes a minimum buffer size of 32 bytes.
 #define USBTMCD_BUFFER_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
+// Interrupt endpoint buffer size, default to 2 bytes as USB488 specification.
+#ifndef CFG_TUD_USBTMC_INT_EP_SIZE
+#define CFG_TUD_USBTMC_INT_EP_SIZE 2
+#endif
+
 /*
  * The state machine does not allow simultaneous reading and writing. This is
  * consistent with USBTMC.
@@ -124,13 +129,15 @@ typedef struct
   uint8_t ep_bulk_in;
   uint8_t ep_bulk_out;
   uint8_t ep_int_in;
+  uint32_t ep_bulk_in_wMaxPacketSize;
+  uint32_t ep_bulk_out_wMaxPacketSize;
   // IN buffer is only used for first packet, not the remainder
   // in order to deal with prepending header
   CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_in_buf[USBTMCD_BUFFER_SIZE];
-  uint32_t ep_bulk_in_wMaxPacketSize;
   // OUT buffer receives one packet at a time
   CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_out_buf[USBTMCD_BUFFER_SIZE];
-  uint32_t ep_bulk_out_wMaxPacketSize;
+  // Buffer int msg to ensure alignment and placement correctness
+  CFG_TUSB_MEM_ALIGN uint8_t ep_int_in_buf[CFG_TUD_USBTMC_INT_EP_SIZE];
 
   uint32_t transfer_size_remaining; // also used for requested length for bulk IN.
   uint32_t transfer_size_sent;      // To keep track of data bytes that have been queued in FIFO (not header bytes)
@@ -243,12 +250,13 @@ bool tud_usbtmc_transmit_dev_msg_data(
 bool tud_usbtmc_transmit_notification_data(const void * data, size_t len)
 {
 #ifndef NDEBUG
-  TU_ASSERT(len >= 1);
+  TU_ASSERT(len > 0);
   TU_ASSERT(usbtmc_state.ep_int_in != 0);
 #endif
-  if (usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in)) return false;
+  TU_VERIFY(usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in));
 
-  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, (void *)(uintptr_t) data, len));
+  TU_VERIFY(tu_memcpy_s(usbtmc_state.ep_int_in_buf, sizeof(usbtmc_state.ep_int_in_buf), data, len) == 0);
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, usbtmc_state.ep_int_in_buf, len));
   return true;
 }
 
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index 2f3c91dbd..af7ea6ec9 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -86,21 +86,16 @@ TU_ATTR_WEAK bool tud_usbtmc_msg_trigger_cb(usbtmc_msg_generic_t* msg);
 //TU_ATTR_WEAK bool tud_usbtmc_app_go_to_local_cb();
 #endif
 
-/*******************************************
- * Called from app
- *
- * We keep a reference to the buffer, so it MUST not change until the app is
- * notified that the transfer is complete.
- ******************************************/
-
+// Called from app
+//
+// We keep a reference to the buffer, so it MUST not change until the app is
+// notified that the transfer is complete.
 bool tud_usbtmc_transmit_dev_msg_data(
     const void * data, size_t len,
     bool endOfMessage, bool usingTermChar);
 
-// Buffers a notification to be sent to the host. The buffer must be
-// valid until the tud_usbtmc_notification_complete_cb callback. The
-// data starts with the bNotify1 field, see the USBTMC Specification,
-// Table 13.
+// Buffers a notification to be sent to the host. The data starts
+// with the bNotify1 field, see the USBTMC Specification, Table 13.
 //
 // If the previous notification data has not yet been sent, this
 // returns false.
-- 
cgit v1.3.1


From bd033a2d531d09478ddd947121e12aa6ece86d56 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 27 Apr 2024 17:24:19 +0200
Subject: Fix CI.

---
 src/class/usbtmc/usbtmc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 59d9b184e..f80abdaf3 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -256,7 +256,7 @@ bool tud_usbtmc_transmit_notification_data(const void * data, size_t len)
   TU_VERIFY(usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in));
 
   TU_VERIFY(tu_memcpy_s(usbtmc_state.ep_int_in_buf, sizeof(usbtmc_state.ep_int_in_buf), data, len) == 0);
-  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, usbtmc_state.ep_int_in_buf, len));
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, usbtmc_state.ep_int_in_buf, (uint16_t)len));
   return true;
 }
 
-- 
cgit v1.3.1


From 327e3ec4bd1908e57e2ecd90738f01fc04a17ba1 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 28 Apr 2024 21:59:54 +0200
Subject: Stall unsupported class request.

---
 src/class/net/ncm_device.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 14ace9d8e..829161865 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -947,7 +947,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     }
 
     switch (request->bmRequestType_bit.type) {
-        case TUSB_REQ_TYPE_STANDARD:
+        case TUSB_REQ_TYPE_STANDARD: {
             switch (request->bRequest) {
                 case TUSB_REQ_GET_INTERFACE: {
                     TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
@@ -975,14 +975,15 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
                 default:
                     return false;
             }
-            break;
+        }
+        break;
 
-        case TUSB_REQ_TYPE_CLASS:
+        case TUSB_REQ_TYPE_CLASS: {
             TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
-
+            switch (request->bRequest) {
             TU_LOG3("  TUSB_REQ_TYPE_CLASS: %d\n", request->bRequest);
 
-            if (request->bRequest == NCM_GET_NTB_PARAMETERS) {
+            case NCM_GET_NTB_PARAMETERS: {
                 // transfer NTB parameters to host.
                 // TODO can one assume, that tud_control_xfer() succeeds?
                 TU_LOG3("    NCM_GET_NTB_PARAMETERS\n");
@@ -990,6 +991,13 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
             }
             break;
 
+                // unsupported request
+            default:
+                return false ;
+
+            }
+        }
+        break;
             // unsupported request
         default:
             return false ;
-- 
cgit v1.3.1


From c303b5d81d3dd9d5dc9f831af704e6d40366d7cf Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Mon, 29 Apr 2024 22:35:55 +0200
Subject: Guard const addr fifo functions with TUP_MEM_CONST_ADDR.

---
 src/common/tusb_fifo.c | 31 +++++++++++++++++++++++++++++--
 src/common/tusb_fifo.h |  4 ++++
 src/common/tusb_mcu.h  |  4 ++++
 3 files changed, 37 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 76696396b..8a0fd4417 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -62,7 +62,9 @@ TU_ATTR_ALWAYS_INLINE static inline void _ff_unlock(osal_mutex_t mutex)
 typedef enum
 {
   TU_FIFO_COPY_INC,            ///< Copy from/to an increasing source/destination address - default mode
+#ifdef TUP_MEM_CONST_ADDR
   TU_FIFO_COPY_CST_FULL_WORDS, ///< Copy from/to a constant source/destination address - required for e.g. STM32 to write into USB hardware FIFO
+#endif
 } tu_fifo_copy_mode_t;
 
 bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable)
@@ -92,6 +94,7 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
 // Pull & Push
 //--------------------------------------------------------------------+
 
+#ifdef TUP_MEM_CONST_ADDR
 // Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address
 // Code adapted from dcd_synopsys.c
 // TODO generalize with configurable 1 byte or 4 byte each read
@@ -140,6 +143,7 @@ static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t
     *reg_tx = tmp32;
   }
 }
+#endif
 
 // send one item to fifo WITHOUT updating write pointer
 static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel)
@@ -179,7 +183,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         memcpy(f->buffer, ((uint8_t const*) app_buf) + lin_bytes, wrap_bytes);
       }
       break;
-
+#ifdef TUP_MEM_CONST_ADDR
     case TU_FIFO_COPY_CST_FULL_WORDS:
       // Intended for hardware buffers from which it can be read word by word only
       if(n <= lin_count)
@@ -224,6 +228,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
       }
       break;
+#endif
     default: break;
   }
 }
@@ -265,7 +270,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rd_ptr,
         memcpy((uint8_t*) app_buf + lin_bytes, f->buffer, wrap_bytes);
       }
     break;
-
+#ifdef TUP_MEM_CONST_ADDR
     case TU_FIFO_COPY_CST_FULL_WORDS:
       if ( n <= lin_count )
       {
@@ -310,6 +315,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rd_ptr,
         // Read data wrapped part
         if (wrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, wrap_bytes);
       }
+#endif
     break;
 
     default: break;
@@ -727,10 +733,29 @@ uint16_t tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n)
   return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_INC);
 }
 
+#ifdef TUP_MEM_CONST_ADDR
+/******************************************************************************/
+/*!
+    @brief This function will read n elements from the array index specified by
+    the read pointer and increment the read index.
+    This function checks for an overflow and corrects read pointer if required.
+    The dest address will not be incremented which is useful for writing to registers.
+
+    @param[in]  f
+                Pointer to the FIFO buffer to manipulate
+    @param[in]  buffer
+                The pointer to data location
+    @param[in]  n
+                Number of element that buffer can afford
+
+    @returns number of items read from the FIFO
+ */
+/******************************************************************************/
 uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint16_t n)
 {
   return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_CST_FULL_WORDS);
 }
+#endif
 
 /******************************************************************************/
 /*!
@@ -839,6 +864,7 @@ uint16_t tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n)
   return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_INC);
 }
 
+#ifdef TUP_MEM_CONST_ADDR
 /******************************************************************************/
 /*!
     @brief This function will write n elements into the array index specified by
@@ -858,6 +884,7 @@ uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t* f, const void * data,
 {
   return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_CST_FULL_WORDS);
 }
+#endif
 
 /******************************************************************************/
 /*!
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 2d9f5e667..e50d9afd4 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -156,11 +156,15 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
 
 bool     tu_fifo_write                  (tu_fifo_t* f, void const * p_data);
 uint16_t tu_fifo_write_n                (tu_fifo_t* f, void const * p_data, uint16_t n);
+#ifdef TUP_MEM_CONST_ADDR
 uint16_t tu_fifo_write_n_const_addr_full_words    (tu_fifo_t* f, const void * data, uint16_t n);
+#endif
 
 bool     tu_fifo_read                   (tu_fifo_t* f, void * p_buffer);
 uint16_t tu_fifo_read_n                 (tu_fifo_t* f, void * p_buffer, uint16_t n);
+#ifdef TUP_MEM_CONST_ADDR
 uint16_t tu_fifo_read_n_const_addr_full_words     (tu_fifo_t* f, void * buffer, uint16_t n);
+#endif
 
 bool     tu_fifo_peek                   (tu_fifo_t* f, void * p_buffer);
 uint16_t tu_fifo_peek_n                 (tu_fifo_t* f, void * p_buffer, uint16_t n);
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 5a567f2d5..c69bc9995 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -448,4 +448,8 @@
   #define TUP_DCD_EDPT_ISO_ALLOC
 #endif
 
+#if defined(TUP_USBIP_DWC2)
+  #define TUP_MEM_CONST_ADDR
+#endif
+
 #endif
-- 
cgit v1.3.1


From 35e7fddc733c9abb7a6d6aae21994ca8bf053581 Mon Sep 17 00:00:00 2001
From: Trevor <4226647+trejan@users.noreply.github.com>
Date: Tue, 30 Apr 2024 16:53:25 +0100
Subject: Add missing capability bit for CDC ACM serial break support

The send break capability bit is needed for serial break support with Linux and possibly MacOS hosts. [A recent Linux kernel patch made it check the ACM capability bits before sending a serial break](https://github.com/raspberrypi/linux/commit/19e321c3eedd4c681a49f532a196bead5d57205e).
---
 src/device/usbd.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.h b/src/device/usbd.h
index 0197628e2..f36734040 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -221,8 +221,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120),\
   /* CDC Call */\
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1),\
-  /* CDC ACM: support line request */\
-  4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 2,\
+  /* CDC ACM: support line request + send break */\
+  4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 6,\
   /* CDC Union */\
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
   /* Endpoint Notification */\
-- 
cgit v1.3.1


From ea3f1d39e8bfc82facc7b3e503d7c71f9119de2b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 May 2024 13:29:29 +0700
Subject: add cmake for pi zero (renamed from pi zero_w), build but the flash
 size seem wrong (only 24 bytes for text)

---
 .clang-format                                      |   6 --
 examples/build_system/cmake/cpu/arm1176jzf-s.cmake |  19 ++++
 examples/build_system/make/cpu/arm1176.mk          |   9 --
 examples/build_system/make/cpu/arm1176jzf-s.mk     |   9 ++
 .../boards/raspberrypi_zero/board.cmake            |   8 ++
 .../broadcom_32bit/boards/raspberrypi_zero/board.h |  38 ++++++++
 .../boards/raspberrypi_zero/board.mk               |   5 +
 .../boards/raspberrypi_zero_w/board.h              |  38 --------
 .../boards/raspberrypi_zero_w/board.mk             |   5 -
 hw/bsp/broadcom_32bit/family.c                     |  11 +++
 hw/bsp/broadcom_32bit/family.cmake                 | 107 +++++++++++++++++++++
 hw/bsp/broadcom_32bit/family.mk                    |   5 +-
 src/common/tusb_fifo.h                             |  12 +--
 src/common/tusb_mcu.h                              |   2 +-
 src/common/tusb_verify.h                           |   3 +-
 15 files changed, 206 insertions(+), 71 deletions(-)
 delete mode 100644 .clang-format
 create mode 100644 examples/build_system/cmake/cpu/arm1176jzf-s.cmake
 delete mode 100644 examples/build_system/make/cpu/arm1176.mk
 create mode 100644 examples/build_system/make/cpu/arm1176jzf-s.mk
 create mode 100644 hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake
 create mode 100644 hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
 create mode 100644 hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
 delete mode 100644 hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
 delete mode 100644 hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
 create mode 100644 hw/bsp/broadcom_32bit/family.cmake

(limited to 'src')

diff --git a/.clang-format b/.clang-format
deleted file mode 100644
index 4369c29fe..000000000
--- a/.clang-format
+++ /dev/null
@@ -1,6 +0,0 @@
----
-BreakBeforeBraces: Linux
-ColumnLimit: '200'
-ReflowComments: 'true'
-
-...
diff --git a/examples/build_system/cmake/cpu/arm1176jzf-s.cmake b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
new file mode 100644
index 000000000..11bb52f30
--- /dev/null
+++ b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
@@ -0,0 +1,19 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mcpu=arm1176jzf-s
+  )
+  # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=arm1176jzf-s
+    -mfpu=none
+    -mfloat-abi=soft
+  )
+  #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/make/cpu/arm1176.mk b/examples/build_system/make/cpu/arm1176.mk
deleted file mode 100644
index 022ccf7ad..000000000
--- a/examples/build_system/make/cpu/arm1176.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-ifeq ($(TOOLCHAIN),gcc)
-  CFLAGS += \
-    -mcpu=arm1176jzf-s \
-
-else ifeq ($(TOOLCHAIN),iar)
-	#CFLAGS += --cpu cortex-a53
-	#ASFLAGS += --cpu cortex-a53
-
-endif
diff --git a/examples/build_system/make/cpu/arm1176jzf-s.mk b/examples/build_system/make/cpu/arm1176jzf-s.mk
new file mode 100644
index 000000000..022ccf7ad
--- /dev/null
+++ b/examples/build_system/make/cpu/arm1176jzf-s.mk
@@ -0,0 +1,9 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=arm1176jzf-s \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake
new file mode 100644
index 000000000..2b8cc19e0
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake
@@ -0,0 +1,8 @@
+set(CMAKE_SYSTEM_PROCESSOR arm1176jzf-s CACHE INTERNAL "System Processor")
+#set(SUFFIX "")
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    BCM_VERSION=2835
+    )
+endfunction()
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
new file mode 100644
index 000000000..84a106346
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h
@@ -0,0 +1,38 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
new file mode 100644
index 000000000..7a248ed24
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.mk
@@ -0,0 +1,5 @@
+CPU_CORE = arm1176jzf-s
+CFLAGS += -DBCM_VERSION=2835 \
+          -DCFG_TUSB_MCU=OPT_MCU_BCM2835
+
+SUFFIX =
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
deleted file mode 100644
index 84a106346..000000000
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
deleted file mode 100644
index 052033230..000000000
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-CPU_CORE = arm1176
-CFLAGS += -DBCM_VERSION=2835 \
-          -DCFG_TUSB_MCU=OPT_MCU_BCM2835
-
-SUFFIX =
diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c
index 664b4dcaf..626565e34 100644
--- a/hw/bsp/broadcom_32bit/family.c
+++ b/hw/bsp/broadcom_32bit/family.c
@@ -27,6 +27,13 @@
 #include "bsp/board_api.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
 #include "broadcom/cpu.h"
 #include "broadcom/gpio.h"
 #include "broadcom/interrupts.h"
@@ -34,6 +41,10 @@
 #include "broadcom/caches.h"
 #include "broadcom/vcmailbox.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 // LED
 #define LED_PIN               18
 #define LED_STATE_ON          1
diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake
new file mode 100644
index 000000000..223c85e48
--- /dev/null
+++ b/hw/bsp/broadcom_32bit/family.cmake
@@ -0,0 +1,107 @@
+include_guard()
+
+set(MCU_DIR ${TOP}/hw/mcu/broadcom)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS BCM2835 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${MCU_DIR}/broadcom/link.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${MCU_DIR}/broadcom/boot.s)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${MCU_DIR}/broadcom/gen/interrupt_handlers.c
+    ${MCU_DIR}/broadcom/gpio.c
+    ${MCU_DIR}/broadcom/interrupts.c
+    ${MCU_DIR}/broadcom/mmu.c
+    ${MCU_DIR}/broadcom/caches.c
+    ${MCU_DIR}/broadcom/vcmailbox.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    -O0
+    -ffreestanding
+    -mgeneral-regs-only
+    -fno-exceptions
+    -std=c17
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${MCU_DIR}
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostdlib -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_BCM2835 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk
index cf68e21ee..e15bd93f7 100644
--- a/hw/bsp/broadcom_32bit/family.mk
+++ b/hw/bsp/broadcom_32bit/family.mk
@@ -1,5 +1,4 @@
 MCU_DIR = hw/mcu/broadcom
-DEPS_SUBMODULES += $(MCU_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -27,15 +26,13 @@ SRC_C += \
 	$(MCU_DIR)/broadcom/caches.c \
 	$(MCU_DIR)/broadcom/vcmailbox.c
 
-SKIP_NANOLIB = 1
-
 LD_FILE = $(MCU_DIR)/broadcom/link$(SUFFIX).ld
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR)
 
-SRC_S += $(MCU_DIR)/broadcom/boot$(SUFFIX).S
+SRC_S += $(MCU_DIR)/broadcom/boot$(SUFFIX).s
 
 $(BUILD)/kernel$(SUFFIX).img: $(BUILD)/$(PROJECT).elf
 	$(OBJCOPY) -O binary $^ $@
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 2d9f5e667..0de576601 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -145,13 +145,13 @@ bool tu_fifo_clear(tu_fifo_t *f);
 bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
 
 #if OSAL_MUTEX_REQUIRED
-  TU_ATTR_ALWAYS_INLINE static inline
-  void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) {
-    f->mutex_wr = wr_mutex;
-    f->mutex_rd = rd_mutex;
-  }
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex) {
+  f->mutex_wr = wr_mutex;
+  f->mutex_rd = rd_mutex;
+}
 #else
-  #define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
+#define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
 #endif
 
 bool     tu_fifo_write                  (tu_fifo_t* f, void const * p_data);
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 5a567f2d5..8d58be2a1 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -430,7 +430,7 @@
 #endif
 
 #if !defined(TUP_DCD_ENDPOINT_MAX) && defined(CFG_TUD_ENABLED) && CFG_TUD_ENABLED
-#warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
+  #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define TUP_DCD_ENDPOINT_MAX    8
 #endif
 
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 0a9549c99..dde0550d3 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -78,8 +78,7 @@
 // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
 #if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
     defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
-  #define TU_BREAKPOINT() do                                                                                \
-  {                                                                                                         \
+  #define TU_BREAKPOINT() do {                                                                              \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
     if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */            \
   } while(0)
-- 
cgit v1.3.1


From c717e52ab2453f7672b16f2d63cd70558950ef33 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 May 2024 17:54:44 +0700
Subject: add cmake for lpc11

---
 .../device/audio_4_channel_mic_freertos/skip.txt   |   1 +
 .../kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h  |   2 +-
 hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h       | 178 ++++++++++++++++++
 hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake    |  19 ++
 hw/bsp/lpc11/boards/lpcxpresso11u37/board.h        |  98 ++++++++++
 .../lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c | 208 ---------------------
 hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake    |  12 ++
 hw/bsp/lpc11/boards/lpcxpresso11u68/board.h        |  27 +++
 hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk       |   1 -
 .../lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c | 135 -------------
 hw/bsp/lpc11/family.c                              | 120 ++++++++++++
 hw/bsp/lpc11/family.cmake                          | 104 +++++++++++
 hw/bsp/lpc11/family.mk                             |   5 +-
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c       |  10 +
 14 files changed, 572 insertions(+), 348 deletions(-)
 create mode 100644 hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake
 create mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u37/board.h
 delete mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
 create mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake
 create mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u68/board.h
 delete mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
 create mode 100644 hw/bsp/lpc11/family.c
 create mode 100644 hw/bsp/lpc11/family.cmake

(limited to 'src')

diff --git a/examples/device/audio_4_channel_mic_freertos/skip.txt b/examples/device/audio_4_channel_mic_freertos/skip.txt
index eb434c23b..21683518c 100644
--- a/examples/device/audio_4_channel_mic_freertos/skip.txt
+++ b/examples/device/audio_4_channel_mic_freertos/skip.txt
@@ -10,5 +10,6 @@ mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
 mcu:RAXXX
 mcu:STM32L0
+board:lpcxpresso11u37
 family:broadcom_32bit
 family:broadcom_64bit
diff --git a/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h
index 133728596..e6604d360 100644
--- a/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h
@@ -147,7 +147,7 @@
 //--------------------------------------------------------------------+
 
 // For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
-#define configPRIO_BITS       4
+#define configPRIO_BITS       2
 
 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */
 #define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
diff --git a/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..27b2d76f5
--- /dev/null
+++ b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,178 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #ifdef __GNUC__
+    #pragma GCC diagnostic push
+    #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #endif
+
+  #include "chip.h"
+
+  #ifdef __GNUC__
+    #pragma GCC diagnostic pop
+  #endif
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake
new file mode 100644
index 000000000..12f75cd08
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.cmake
@@ -0,0 +1,19 @@
+set(LPC_FAMILY 11xx)
+set(JLINK_DEVICE LPC11U37/401)
+set(PYOCD_TARGET lpc11u37)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc11u37.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+  target_sources(${TARGET} PRIVATE
+    ${SDK_DIR}/src/gpio_${LPC_FAMILY}_1.c
+    ${SDK_DIR}/src/sysctl_${LPC_FAMILY}.c
+    )
+  target_compile_options(${TARGET} PRIVATE
+    -Wno-error=unused-parameter
+    )
+endfunction()
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h
new file mode 100644
index 000000000..930462f28
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h
@@ -0,0 +1,98 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              1
+#define LED_PIN               24
+#define LED_STATE_ON          0
+
+// Wake up Switch
+#define BUTTON_PORT           0
+#define BUTTON_PIN            16
+#define BUTTON_STATE_ACTIVE   0
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t ExtRateIn = 0;
+
+/* Pin muxing table, only items that need changing from their default pin
+   state are in this table. Not every pin is mapped. */
+/* IOCON pin definitions for pin muxing */
+typedef struct {
+  uint32_t port : 8;			/* Pin port */
+  uint32_t pin : 8;			/* Pin number */
+  uint32_t modefunc : 16;		/* Function and mode */
+} PINMUX_GRP_T;
+
+static const PINMUX_GRP_T pinmuxing[] = {
+    {0,  3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
+    {0,  6, (IOCON_FUNC1 | IOCON_MODE_INACT)},		/* PIO0_6 used for USB_CONNECT */
+
+    {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
+    {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
+};
+
+/* Setup system clocking */
+static inline void Chip_SetupXtalClocking(void) {
+  volatile int i;
+
+  /* Powerup main oscillator */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
+
+  /* Wait 200us for OSC to be stablized, no status
+     indication, dummy wait. */
+  for (i = 0; i < 0x100; i++) {}
+
+  /* Set system PLL input to main oscillator */
+  Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
+
+  /* Power down PLL to change the PLL divider ratio */
+  Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+  /* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
+     MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
+     FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
+     FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
+  Chip_Clock_SetupSystemPLL(3, 1);
+
+  /* Powerup system PLL */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
+
+  /* Wait for PLL to lock */
+  while (!Chip_Clock_IsSystemPLLLocked()) {}
+
+  /* Set system clock divider to 1 */
+  Chip_Clock_SetSysClockDiv(1);
+
+  /* Setup FLASH access to 3 clocks */
+  Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
+
+  /* Set main clock source to the system PLL. This will drive 48MHz
+     for the main clock and 48MHz for the system clock */
+  Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
+
+  /* Set USB PLL input to main oscillator */
+  Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
+  /* Setup USB PLL  (FCLKIN = 12MHz) * 4 = 48MHz
+     MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
+     FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
+     FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
+  Chip_Clock_SetupUSBPLL(3, 1);
+
+  /* Powerup USB PLL */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
+
+  /* Wait for PLL to lock */
+  while (!Chip_Clock_IsUSBPLLLocked()) {}
+}
+
+static inline void Chip_USB_Init(void) {
+  /* enable USB main clock */
+  Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
+  /* Enable AHB clock to the USB block and USB RAM. */
+  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
+  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USBRAM);
+  /* power UP USB Phy */
+  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
+}
+
+#endif
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
deleted file mode 100644
index 900c57936..000000000
--- a/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "bsp/board_api.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//---------------------------------------------------------------- ----+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              1
-#define LED_PIN               24
-#define LED_STATE_ON          0
-
-// Wake up Switch
-#define BUTTON_PORT           0
-#define BUTTON_PIN            16
-#define BUTTON_STATE_ACTIVE   0
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t ExtRateIn = 0;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. Not every pin is mapped. */
-/* IOCON pin definitions for pin muxing */
-typedef struct {
-	uint32_t port : 8;			/* Pin port */
-	uint32_t pin : 8;			/* Pin number */
-	uint32_t modefunc : 16;		/* Function and mode */
-} PINMUX_GRP_T;
-
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0,  3, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
-  {0,  6, (IOCON_FUNC1 | IOCON_MODE_INACT)},		/* PIO0_6 used for USB_CONNECT */
-
-  {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
-  {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
-};
-
-/* Setup system clocking */
-static void SystemSetupClocking(void)
-{
-	volatile int i;
-
-	/* Powerup main oscillator */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
-
-	/* Wait 200us for OSC to be stablized, no status
-	   indication, dummy wait. */
-	for (i = 0; i < 0x100; i++) {}
-
-	/* Set system PLL input to main oscillator */
-	Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
-
-	/* Power down PLL to change the PLL divider ratio */
-	Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
-
-	/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
-	   MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
-	   FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
-	   FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
-	Chip_Clock_SetupSystemPLL(3, 1);
-
-	/* Powerup system PLL */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
-
-	/* Wait for PLL to lock */
-	while (!Chip_Clock_IsSystemPLLLocked()) {}
-
-	/* Set system clock divider to 1 */
-	Chip_Clock_SetSysClockDiv(1);
-
-	/* Setup FLASH access to 3 clocks */
-	Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
-
-	/* Set main clock source to the system PLL. This will drive 48MHz
-	   for the main clock and 48MHz for the system clock */
-	Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
-
-	/* Set USB PLL input to main oscillator */
-	Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
-	/* Setup USB PLL  (FCLKIN = 12MHz) * 4 = 48MHz
-	   MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
-	   FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
-	   FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
-	Chip_Clock_SetupUSBPLL(3, 1);
-
-	/* Powerup USB PLL */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
-
-	/* Wait for PLL to lock */
-	while (!Chip_Clock_IsUSBPLLLocked()) {}
-}
-
-// Invoked by startup code
-void SystemInit(void)
-{
-  SystemSetupClocking();
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_RAM1);
-
-  /* Enable IOCON clock */
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  for (uint32_t i = 0; i < (sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); i++)
-  {
-		Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].port, pinmuxing[i].pin, pinmuxing[i].modefunc);
-	}
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-  // USB: Setup PLL clock, and power
-	/* enable USB main clock */
-	Chip_Clock_SetUSBClockSource(SYSCTL_USBCLKSRC_PLLOUT, 1);
-	/* Enable AHB clock to the USB block and USB RAM. */
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USB);
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_USBRAM);
-	/* power UP USB Phy */
-	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPAD_PD);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake
new file mode 100644
index 000000000..b7393cb2f
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.cmake
@@ -0,0 +1,12 @@
+set(LPC_FAMILY 11u6x)
+set(JLINK_DEVICE LPC11U68)
+set(PYOCD_TARGET LPC11U68)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc11u68.ld)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${SDK_DIR}/src/gpio_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/syscon_${LPC_FAMILY}.c
+    )
+endfunction()
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h
new file mode 100644
index 000000000..a12fcbef1
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h
@@ -0,0 +1,27 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+#define LED_PORT              2
+#define LED_PIN               17
+#define LED_STATE_ON          0
+
+// Wake up Switch
+#define BUTTON_PORT           0
+#define BUTTON_PIN            16
+#define BUTTON_STATE_ACTIVE   0
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t RTCOscRateIn = 32768;
+
+/* Pin muxing table, only items that need changing from their default pin
+   state are in this table. Not every pin is mapped. */
+static const PINMUX_GRP_T pinmuxing[] = {
+    {0, 3,  (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
+    {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
+    {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
+    {2, 0,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALIN
+    {2, 1,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALOUT
+};
+
+#endif
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
index fbe97b853..cf095c347 100644
--- a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
@@ -5,7 +5,6 @@ CFLAGS += \
   -DCORE_M0PLUS \
   -D__VTOR_PRESENT=0 \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/lpc11u68.ld
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
deleted file mode 100644
index df895804d..000000000
--- a/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "chip.h"
-#include "bsp/board_api.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT              2
-#define LED_PIN               17
-#define LED_STATE_ON          0
-
-// Wake up Switch
-#define BUTTON_PORT           0
-#define BUTTON_PIN            16
-#define BUTTON_STATE_ACTIVE   0
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing table, only items that need changing from their default pin
-   state are in this table. Not every pin is mapped. */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  {0, 3,  (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // USB VBUS
-  {0, 18, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 RX
-  {0, 19, (IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGMODE_EN)}, // UART0 TX
-  {2, 0,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALIN
-  {2, 1,  (IOCON_FUNC1 | IOCON_MODE_INACT)}, // XTALOUT
-};
-
-// Invoked by startup code
-void SystemInit(void)
-{
-  /* Enable IOCON clock */
-  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
-  Chip_SetupXtalClocking();
-}
-
-void board_init(void)
-{
-  SystemCoreClockUpdate();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  Chip_GPIO_Init(LPC_GPIO);
-
-  // LED
-  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
-
-  // Button
-  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-
-  // USB: Setup PLL clock, and power
-  Chip_USB_Init();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c
new file mode 100644
index 000000000..bff7110b8
--- /dev/null
+++ b/hw/bsp/lpc11/family.c
@@ -0,0 +1,120 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include "chip.h"
+
+#ifdef __GNUC__
+  #pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+// Invoked by startup code
+void SystemInit(void) {
+  /* Enable IOCON clock */
+  Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
+  for (uint32_t i = 0; i < (sizeof(pinmuxing) / sizeof(PINMUX_GRP_T)); i++) {
+    Chip_IOCON_PinMuxSet(LPC_IOCON, pinmuxing[i].port, pinmuxing[i].pin, pinmuxing[i].modefunc);
+  }
+  Chip_SetupXtalClocking();
+}
+
+void board_init(void) {
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  Chip_GPIO_Init(LPC_GPIO);
+
+  // LED
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO, LED_PORT, LED_PIN);
+
+  // Button
+  Chip_GPIO_SetPinDIRInput(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
+
+  // USB: Setup PLL clock, and power
+  Chip_USB_Init();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake
new file mode 100644
index 000000000..f17a48dd7
--- /dev/null
+++ b/hw/bsp/lpc11/family.cmake
@@ -0,0 +1,104 @@
+include_guard()
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+if (LPC_FAMILY STREQUAL 11xx)
+  set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx)
+else()
+  set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc${LPC_FAMILY}/lpc_chip_${LPC_FAMILY})
+endif()
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC11UXX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc${LPC_FAMILY}.c
+    ${SDK_DIR}/src/chip_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/clock_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/iocon_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysinit_${LPC_FAMILY}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    __VTOR_PRESENT=0
+    CORE_M0
+    CORE_M0PLUS
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC11UXX ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc11/family.mk b/hw/bsp/lpc11/family.mk
index ce07ff450..09713fd55 100644
--- a/hw/bsp/lpc11/family.mk
+++ b/hw/bsp/lpc11/family.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc$(MCU)/lpc_chip_$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m0plus
@@ -34,7 +32,8 @@ SRC_C += \
 endif
 
 INC += \
-	$(TOP)/$(MCU_DIR)/inc
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)/inc \
 
 # For flash-jlink target
 JLINK_DEVICE = LPC11U68
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 022904a3a..6bb440743 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -42,7 +42,17 @@
 
 #if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
   // LPCOpen
+  #ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #endif
+
   #include "chip.h"
+
+  #ifdef __GNUC__
+  #pragma GCC diagnostic pop
+  #endif
+
 #else
   // SDK
   #include "fsl_device_registers.h"
-- 
cgit v1.3.1


From 2213fe40e57d54f28df54d3b48305eceaa89b03d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 May 2024 18:24:47 +0700
Subject: add cmake for lpc15

---
 hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h   | 179 +++++++++++++++++++++++++
 hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake |  11 ++
 hw/bsp/lpc15/family.c                          |  11 ++
 hw/bsp/lpc15/family.cmake                      | 104 ++++++++++++++
 hw/bsp/lpc15/family.mk                         |   2 +-
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c   |   1 +
 6 files changed, 307 insertions(+), 1 deletion(-)
 create mode 100644 hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake
 create mode 100644 hw/bsp/lpc15/family.cmake

(limited to 'src')

diff --git a/hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..33bc22b37
--- /dev/null
+++ b/hw/bsp/lpc15/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,179 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #pragma GCC diagnostic ignored "-Wstrict-prototypes"
+  #endif
+
+  #include "chip.h"
+
+  #ifdef __GNUC__
+  #pragma GCC diagnostic pop
+  #endif
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake b/hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake
new file mode 100644
index 000000000..1e893b554
--- /dev/null
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.cmake
@@ -0,0 +1,11 @@
+set(JLINK_DEVICE lpc1549)
+set(PYOCD_TARGET lpc1549)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1549.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c
index cd5c9ab15..b9ce39648 100644
--- a/hw/bsp/lpc15/family.c
+++ b/hw/bsp/lpc15/family.c
@@ -24,7 +24,18 @@
  * This file is part of the TinyUSB stack.
  */
 
+#ifdef __GNUC__
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wstrict-prototypes"
+  #pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "chip.h"
+
+#ifdef __GNUC__
+  #pragma GCC diagnostic pop
+#endif
+
 #include "bsp/board_api.h"
 #include "board.h"
 
diff --git a/hw/bsp/lpc15/family.cmake b/hw/bsp/lpc15/family.cmake
new file mode 100644
index 000000000..61b47d852
--- /dev/null
+++ b/hw/bsp/lpc15/family.cmake
@@ -0,0 +1,104 @@
+include_guard()
+
+set(LPC_FAMILY 15xx)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc${LPC_FAMILY}/lpc_chip_${LPC_FAMILY})
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC15XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc${LPC_FAMILY}.c
+    ${SDK_DIR}/src/chip_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/clock_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/gpio_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/iocon_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/swm_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysctl_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/sysinit_${LPC_FAMILY}.c
+    ${SDK_DIR}/src/uart_${LPC_FAMILY}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    #__VTOR_PRESENT=0
+    CORE_M3
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC15XX ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index 28ab1db7b..b83e008e8 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -28,8 +28,8 @@ SRC_C += \
 	$(MCU_DIR)/src/iocon_15xx.c \
 	$(MCU_DIR)/src/swm_15xx.c \
 	$(MCU_DIR)/src/sysctl_15xx.c \
+	$(MCU_DIR)/src/sysinit_15xx.c \
 	$(MCU_DIR)/src/uart_15xx.c \
-	$(MCU_DIR)/src/sysinit_15xx.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 6bb440743..cc18cf59b 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -45,6 +45,7 @@
   #ifdef __GNUC__
   #pragma GCC diagnostic push
   #pragma GCC diagnostic ignored "-Wunused-parameter"
+  #pragma GCC diagnostic ignored "-Wstrict-prototypes"
   #endif
 
   #include "chip.h"
-- 
cgit v1.3.1


From 68a4d0c8db0beec4fee22dab003f1e5ec39da310 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 May 2024 20:43:27 +0700
Subject: add cmake to lpc51

---
 hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h       | 169 +++++++++++++++++++
 hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake    |  13 ++
 hw/bsp/lpc51/boards/lpcxpresso51u68/board.h        |  57 +++++++
 .../lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c | 179 ---------------------
 hw/bsp/lpc51/family.c                              | 141 ++++++++++++++++
 hw/bsp/lpc51/family.cmake                          | 123 ++++++++++++++
 hw/bsp/lpc51/family.mk                             |  11 +-
 src/tusb_option.h                                  |   3 +-
 8 files changed, 512 insertions(+), 184 deletions(-)
 create mode 100644 hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
 create mode 100644 hw/bsp/lpc51/boards/lpcxpresso51u68/board.h
 delete mode 100644 hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
 create mode 100644 hw/bsp/lpc51/family.c
 create mode 100644 hw/bsp/lpc51/family.cmake

(limited to 'src')

diff --git a/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e6604d360
--- /dev/null
+++ b/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,169 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
new file mode 100644
index 000000000..1f549bf50
--- /dev/null
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT LPC51U68)
+
+set(JLINK_DEVICE LPC51U68)
+set(PYOCD_TARGET LPC51U68)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC51U68JBD64
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h
new file mode 100644
index 000000000..0a3b37fda
--- /dev/null
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h
@@ -0,0 +1,57 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+#define LED_PORT      0
+#define LED_PIN       29
+#define LED_STATE_ON  0
+
+// WAKE button
+#define BUTTON_PORT   0
+#define BUTTON_PIN    24
+
+// IOCON pin mux
+#define IOCON_PIO_DIGITAL_EN          0x80u   /*!< Enables digital function */
+#define IOCON_PIO_FUNC1               0x01u   /*!< Selects pin function 1 */
+#define IOCON_PIO_FUNC7               0x07u   /*!< Selects pin function 7 */
+#define IOCON_PIO_INPFILT_OFF       0x0100u   /*!< Input filter disabled */
+#define IOCON_PIO_INV_DI              0x00u   /*!< Input function is not inverted */
+#define IOCON_PIO_MODE_INACT          0x00u   /*!< No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI        0x00u   /*!< Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD       0x00u   /*!< Standard mode, output slew rate control is enabled */
+
+/****************************************************************
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: SYSTICK_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+******************************************************************/
+static inline void BootClockFROHF96M(void) {
+  /*!< Set up the clock sources */
+  /*!< Set up FRO */
+  POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+
+  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+  /*!< Set up dividers */
+  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
+  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true);  /*!< Reset SYSTICKCLKDIV divider counter and halt it */
+  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
+
+  /*!< Set up clock selectors - Attach clocks to the peripheries */
+  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+  /*!< Set SystemCoreClock variable. */
+  SystemCoreClock = 96000000U;
+}
+
+#endif
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c b/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
deleted file mode 100644
index 579c9c9ed..000000000
--- a/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018, hathach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "bsp/board_api.h"
-#include "fsl_device_registers.h"
-#include "fsl_gpio.h"
-#include "fsl_power.h"
-#include "fsl_iocon.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-#define LED_PORT      0
-#define LED_PIN       29
-#define LED_STATE_ON  0
-
-// WAKE button
-#define BUTTON_PORT   0
-#define BUTTON_PIN    24
-
-// IOCON pin mux
-#define IOCON_PIO_DIGITAL_EN          0x80u   /*!< Enables digital function */
-#define IOCON_PIO_FUNC1               0x01u   /*!< Selects pin function 1 */
-#define IOCON_PIO_FUNC7               0x07u   /*!< Selects pin function 7 */
-#define IOCON_PIO_INPFILT_OFF       0x0100u   /*!< Input filter disabled */
-#define IOCON_PIO_INV_DI              0x00u   /*!< Input function is not inverted */
-#define IOCON_PIO_MODE_INACT          0x00u   /*!< No addition pin function */
-#define IOCON_PIO_OPENDRAIN_DI        0x00u   /*!< Open drain is disabled */
-#define IOCON_PIO_SLEW_STANDARD       0x00u   /*!< Standard mode, output slew rate control is enabled */
-
-/****************************************************************
-name: BOARD_BootClockFROHF96M
-outputs:
-- {id: SYSTICK_clock.outFreq, value: 96 MHz}
-- {id: System_clock.outFreq, value: 96 MHz}
-settings:
-- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
-sources:
-- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
-******************************************************************/
-void BootClockFROHF96M(void)
-{
-  /*!< Set up the clock sources */
-  /*!< Set up FRO */
-  POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
-  CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
-                                             accidentally being below the voltage for current speed */
-  POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
-  CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
-
-  CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
-
-  /*!< Set up dividers */
-  CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);     /*!< Set AHBCLKDIV divider to value 1 */
-  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true);  /*!< Reset SYSTICKCLKDIV divider counter and halt it */
-  CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */
-
-  /*!< Set up clock selectors - Attach clocks to the peripheries */
-  CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
-  /*!< Set SystemCoreClock variable. */
-  SystemCoreClock = 96000000U;
-}
-
-void board_init(void)
-{
-  // Enable IOCON clock
-  CLOCK_EnableClock(kCLOCK_Iocon);
-
-  // Enable GPIO0 clock
-  CLOCK_EnableClock(kCLOCK_Gpio0);
-
-  // Init 96 MHz clock
-  BootClockFROHF96M();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  GPIO_PortInit(GPIO, LED_PORT);
-  GPIO_PortInit(GPIO, BUTTON_PORT);
-
-  // LED
-  gpio_pin_config_t const led_config = { kGPIO_DigitalOutput, 0};
-  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
-
-  // Button
-  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
-  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
-
-  // USB
-  const uint32_t port1_pin6_config = (
-    IOCON_PIO_FUNC7       | /* Pin is configured as USB0_VBUS */
-    IOCON_PIO_MODE_INACT  | /* No addition pin function */
-    IOCON_PIO_INV_DI      | /* Input function is not inverted */
-    IOCON_PIO_DIGITAL_EN  | /* Enables digital function */
-    IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
-    IOCON_PIO_OPENDRAIN_DI  /* Open drain is disabled */
-  );
-  IOCON_PinMuxSet(IOCON, 1, 6, port1_pin6_config); /* PORT1 PIN6 (coords: 26) is configured as USB0_VBUS */
-
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB Phy */
-  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  // active low
-  return 1-GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/hw/bsp/lpc51/family.c b/hw/bsp/lpc51/family.c
new file mode 100644
index 000000000..a0667a741
--- /dev/null
+++ b/hw/bsp/lpc51/family.c
@@ -0,0 +1,141 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_power.h"
+#include "fsl_iocon.h"
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void) {
+  tud_int_handler(0);
+}
+
+void board_init(void) {
+  // Enable IOCON clock
+  CLOCK_EnableClock(kCLOCK_Iocon);
+
+  // Enable GPIO0 clock
+  CLOCK_EnableClock(kCLOCK_Gpio0);
+
+  // Init 96 MHz clock
+  BootClockFROHF96M();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  GPIO_PortInit(GPIO, LED_PORT);
+  GPIO_PortInit(GPIO, BUTTON_PORT);
+
+  // LED
+  gpio_pin_config_t const led_config = {kGPIO_DigitalOutput, 0};
+  GPIO_PinInit(GPIO, LED_PORT, LED_PIN, &led_config);
+  board_led_write(true);
+
+  // Button
+  gpio_pin_config_t const button_config = {kGPIO_DigitalInput, 0};
+  GPIO_PinInit(GPIO, BUTTON_PORT, BUTTON_PIN, &button_config);
+
+  // USB
+  const uint32_t port1_pin6_config = (
+      IOCON_PIO_FUNC7       | /* Pin is configured as USB0_VBUS */
+      IOCON_PIO_MODE_INACT  | /* No addition pin function */
+      IOCON_PIO_INV_DI      | /* Input function is not inverted */
+      IOCON_PIO_DIGITAL_EN  | /* Enables digital function */
+      IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
+      IOCON_PIO_OPENDRAIN_DI  /* Open drain is disabled */
+  );
+  IOCON_PinMuxSet(IOCON, 1, 6, port1_pin6_config); /* PORT1 PIN6 (coords: 26) is configured as USB0_VBUS */
+
+  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*Turn on USB Phy */
+  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_PinWrite(GPIO, LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  // active low
+  return 1 - GPIO_PinRead(GPIO, BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
+
+#ifndef __ICCARM__
+// Implement _start() since we use linker flag '-nostartfiles'.
+// Requires defined __STARTUP_CLEAR_BSS,
+extern int main(void);
+
+TU_ATTR_UNUSED void _start(void) {
+  // called by startup code
+  main();
+  while (1) {}
+}
+
+#ifdef __clang__
+void	_exit (int __status) {
+  while (1) {}
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake
new file mode 100644
index 000000000..dd0ef6d1b
--- /dev/null
+++ b/hw/bsp/lpc51/family.cmake
@@ -0,0 +1,123 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC51 CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}_flash.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    # driver
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    __STARTUP_CLEAR_BSS
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      --specs=nosys.specs --specs=nano.specs
+      -nostartfiles
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_Clang}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC51 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk
index c8ee29dbc..b41b5438e 100644
--- a/hw/bsp/lpc51/family.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -1,19 +1,21 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
-MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
+  -D__STARTUP_CLEAR_BSS \
   -DCFG_TUSB_MCU=OPT_MCU_LPC51UXX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
 
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+  -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
 
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/$(MCU)_flash.ld
@@ -29,7 +31,8 @@ SRC_C += \
 	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
 
 INC += \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+  $(TOP)/$(BOARD_PATH) \
+  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3ead20ee7..8d5527936 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -55,7 +55,8 @@
 #define OPT_MCU_LPC18XX             6 ///< NXP LPC18xx
 #define OPT_MCU_LPC40XX             7 ///< NXP LPC40xx
 #define OPT_MCU_LPC43XX             8 ///< NXP LPC43xx
-#define OPT_MCU_LPC51UXX            9 ///< NXP LPC51U6x
+#define OPT_MCU_LPC51               9 ///< NXP LPC51
+#define OPT_MCU_LPC51UXX            OPT_MCU_LPC51 ///< NXP LPC51
 #define OPT_MCU_LPC54              10 ///< NXP LPC54
 #define OPT_MCU_LPC55              11 ///< NXP LPC55
 // legacy naming
-- 
cgit v1.3.1


From c020a0190d5f22c0f761ce0a5ec4a6e35e4d0662 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 4 May 2024 12:36:40 +0700
Subject: add cmake for f1c100s

---
 examples/build_system/cmake/cpu/arm1176jzf-s.cmake |   2 +
 examples/build_system/cmake/cpu/arm926ej-s.cmake   |  21 ++++
 examples/build_system/make/cpu/arm926ej-s.mk       |   9 ++
 hw/bsp/f1c100s/board.h                             |   1 -
 hw/bsp/f1c100s/board.mk                            |  52 ---------
 hw/bsp/f1c100s/boards/f1c100s/board.cmake          |   3 +
 hw/bsp/f1c100s/boards/f1c100s/board.h              |   6 +
 hw/bsp/f1c100s/boards/f1c100s/board.mk             |   1 +
 hw/bsp/f1c100s/f1c100s.c                           | 130 ---------------------
 hw/bsp/f1c100s/family.c                            | 126 ++++++++++++++++++++
 hw/bsp/f1c100s/family.cmake                        | 114 ++++++++++++++++++
 hw/bsp/f1c100s/family.mk                           |  58 +++++++++
 src/portable/sunxi/dcd_sunxi_musb.c                |  14 ++-
 13 files changed, 348 insertions(+), 189 deletions(-)
 create mode 100644 examples/build_system/cmake/cpu/arm926ej-s.cmake
 create mode 100644 examples/build_system/make/cpu/arm926ej-s.mk
 delete mode 100644 hw/bsp/f1c100s/board.h
 delete mode 100644 hw/bsp/f1c100s/board.mk
 create mode 100644 hw/bsp/f1c100s/boards/f1c100s/board.cmake
 create mode 100644 hw/bsp/f1c100s/boards/f1c100s/board.h
 create mode 100644 hw/bsp/f1c100s/boards/f1c100s/board.mk
 delete mode 100644 hw/bsp/f1c100s/f1c100s.c
 create mode 100644 hw/bsp/f1c100s/family.c
 create mode 100644 hw/bsp/f1c100s/family.cmake
 create mode 100644 hw/bsp/f1c100s/family.mk

(limited to 'src')

diff --git a/examples/build_system/cmake/cpu/arm1176jzf-s.cmake b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
index 11bb52f30..8029e3987 100644
--- a/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
+++ b/examples/build_system/cmake/cpu/arm1176jzf-s.cmake
@@ -1,6 +1,7 @@
 if (TOOLCHAIN STREQUAL "gcc")
   set(TOOLCHAIN_COMMON_FLAGS
     -mcpu=arm1176jzf-s
+    -ffreestanding
   )
   # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
 
@@ -10,6 +11,7 @@ elseif (TOOLCHAIN STREQUAL "clang")
     -mcpu=arm1176jzf-s
     -mfpu=none
     -mfloat-abi=soft
+    -ffreestanding
   )
   #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
 
diff --git a/examples/build_system/cmake/cpu/arm926ej-s.cmake b/examples/build_system/cmake/cpu/arm926ej-s.cmake
new file mode 100644
index 000000000..c19b9f8a8
--- /dev/null
+++ b/examples/build_system/cmake/cpu/arm926ej-s.cmake
@@ -0,0 +1,21 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mcpu=arm926ej-s
+    -ffreestanding
+    )
+  # set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --target=arm-none-eabi
+    -mcpu=arm926ej-s
+    -mfpu=none
+    -mfloat-abi=soft
+    -ffreestanding
+    )
+  #set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  message(FATAL_ERROR "IAR not supported")
+
+endif ()
diff --git a/examples/build_system/make/cpu/arm926ej-s.mk b/examples/build_system/make/cpu/arm926ej-s.mk
new file mode 100644
index 000000000..5b84f514f
--- /dev/null
+++ b/examples/build_system/make/cpu/arm926ej-s.mk
@@ -0,0 +1,9 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=arm926ej-s \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
diff --git a/hw/bsp/f1c100s/board.h b/hw/bsp/f1c100s/board.h
deleted file mode 100644
index 0ef9a1700..000000000
--- a/hw/bsp/f1c100s/board.h
+++ /dev/null
@@ -1 +0,0 @@
-// Nothing valuable here
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
deleted file mode 100644
index 3596e5414..000000000
--- a/hw/bsp/f1c100s/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-MCU_DIR = hw/mcu/allwinner/f1c100s
-DEPS_SUBMODULES += hw/mcu/allwinner
-DEFINES += -D__ARM32_ARCH__=5 -D__ARM926EJS__
-
-CFLAGS += \
-  -ffreestanding \
-  -std=gnu99 \
-  -march=armv5te \
-  -mtune=arm926ej-s \
-  -mfloat-abi=soft \
-  -marm \
-  -mno-thumb-interwork \
-  -Wno-unused-parameter \
-  -Wno-float-equal \
-  -DCFG_TUSB_MCU=OPT_MCU_F1C100S \
-  -Wno-error=cast-align \
-  -Wno-error=address-of-packed-member \
-  $(DEFINES)
-
-LD_FILE = hw/mcu/allwinner/f1c100s/f1c100s.ld
-# TODO may skip nanolib
-LDFLAGS += -nostdlib -lgcc -specs=nosys.specs -specs=nano.specs
-
-SRC_C += \
-	src/portable/sunxi/dcd_sunxi_musb.c \
-	$(MCU_DIR)/machine/sys-uart.c \
-	$(MCU_DIR)/machine/exception.c \
-	$(MCU_DIR)/machine/sys-clock.c \
-	$(MCU_DIR)/machine/sys-copyself.c \
-	$(MCU_DIR)/machine/sys-dram.c \
-	$(MCU_DIR)/machine/sys-mmu.c \
-	$(MCU_DIR)/machine/sys-spi-flash.c \
-	$(MCU_DIR)/machine/f1c100s-intc.c \
-	$(MCU_DIR)/lib/malloc.c \
-	$(MCU_DIR)/lib/printf.c
-
-SRC_S += \
-  $(MCU_DIR)/machine/start.S \
-	$(MCU_DIR)/lib/memcpy.S \
-	$(MCU_DIR)/lib/memset.S
-
-INC += \
-	$(TOP)/$(MCU_DIR)/include \
-	$(TOP)/$(BOARD_PATH)
-
-# flash target using xfel
-flash: flash-xfel
-
-exec: $(BUILD)/$(PROJECT).bin
-	xfel ddr
-	xfel write 0x80000000 $<
-	xfel exec 0x80000000
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.cmake b/hw/bsp/f1c100s/boards/f1c100s/board.cmake
new file mode 100644
index 000000000..98ed56c57
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.cmake
@@ -0,0 +1,3 @@
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.h b/hw/bsp/f1c100s/boards/f1c100s/board.h
new file mode 100644
index 000000000..3b56a3a57
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.h
@@ -0,0 +1,6 @@
+#ifndef BOARD_H
+#define BOARD_H
+
+// Nothing valuable here
+
+#endif
diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.mk b/hw/bsp/f1c100s/boards/f1c100s/board.mk
new file mode 100644
index 000000000..be830bd8c
--- /dev/null
+++ b/hw/bsp/f1c100s/boards/f1c100s/board.mk
@@ -0,0 +1 @@
+# nothing to do
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/f1c100s.c
deleted file mode 100644
index 272b756f2..000000000
--- a/hw/bsp/f1c100s/f1c100s.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include <stdint.h>
-#include <malloc.h>
-#include <irqflags.h>
-#include <f1c100s-irq.h>
-#include "bsp/board_api.h"
-#include "board.h"
-
-extern void sys_uart_putc(char c);
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-static void timer_init(void);
-
-void board_init(void)
-{
-  arch_local_irq_disable();
-	do_init_mem_pool();
-  f1c100s_intc_init();
-  timer_init();
-  printf("Timer INIT done\n");
-  arch_local_irq_enable();
-}
-
-// No LED, no button
-void board_led_write(bool state)
-{
-
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  int txsize = len;
-  while (txsize--) {
-    sys_uart_putc(*(uint8_t const*)buf);
-    buf++;
-  }
-  return len;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-
-static void timer_handler(void)
-{
-  volatile uint32_t *temp_addr = (uint32_t *)(0x01C20C00 + 0x04);
-
-  /* clear timer */
-  *temp_addr |= 0x01;
-
-  system_ticks++;
-}
-
-static void timer_init(void) {
-  uint32_t temp;
-  volatile uint32_t *temp_addr;
-
-  /* reload value */
-  temp = 12000000 / 1000;
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x14);
-  *temp_addr = temp;
-
-  /* continuous | /2 | 24Mhz |  reload*/
-  temp = (0x00 << 7) | (0x01 << 4) | (0x01 << 2) | (0x00 << 1);
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
-  *temp_addr &= 0xffffff00;
-  *temp_addr |= temp;
-
-  /* open timer irq */
-  temp = 0x01 << 0;
-  temp_addr = (uint32_t *)(0x01C20C00);
-  *temp_addr |= temp;
-
-  /* set init value */
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x18);
-  *temp_addr = 0;
-
-  /* begin run timer */
-  temp = 0x01 << 0;
-  temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
-  *temp_addr |= temp;
-
-  f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
-  f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
-}
-#else
-static void timer_init(void) { }
-#endif
diff --git a/hw/bsp/f1c100s/family.c b/hw/bsp/f1c100s/family.c
new file mode 100644
index 000000000..6df4a0ed8
--- /dev/null
+++ b/hw/bsp/f1c100s/family.c
@@ -0,0 +1,126 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+#include <malloc.h>
+#include <irqflags.h>
+#include <f1c100s-irq.h>
+#include "bsp/board_api.h"
+#include "board.h"
+
+extern void sys_uart_putc(char c);
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+static void timer_init(void);
+
+void board_init(void) {
+  arch_local_irq_disable();
+  do_init_mem_pool();
+  f1c100s_intc_init();
+  timer_init();
+  printf("Timer INIT done\n");
+  arch_local_irq_enable();
+}
+
+// No LED, no button
+void board_led_write(bool state) {
+  (void) state;
+}
+
+uint32_t board_button_read(void) {
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  int txsize = len;
+  while (txsize--) {
+    sys_uart_putc(*(uint8_t const*) buf);
+    buf++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+static void timer_handler(void) {
+  volatile uint32_t* temp_addr = (uint32_t*) (0x01C20C00 + 0x04);
+
+  /* clear timer */
+  *temp_addr |= 0x01;
+
+  system_ticks++;
+}
+
+static void timer_init(void) {
+  uint32_t temp;
+  volatile uint32_t* temp_addr;
+
+  /* reload value */
+  temp = 12000000 / 1000;
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x14);
+  *temp_addr = temp;
+
+  /* continuous | /2 | 24Mhz |  reload*/
+  temp = (0x00 << 7) | (0x01 << 4) | (0x01 << 2) | (0x00 << 1);
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x10);
+  *temp_addr &= 0xffffff00;
+  *temp_addr |= temp;
+
+  /* open timer irq */
+  temp = 0x01 << 0;
+  temp_addr = (uint32_t*) (0x01C20C00);
+  *temp_addr |= temp;
+
+  /* set init value */
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x18);
+  *temp_addr = 0;
+
+  /* begin run timer */
+  temp = 0x01 << 0;
+  temp_addr = (uint32_t*) (0x01C20C00 + 0x10);
+  *temp_addr |= temp;
+
+  f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
+  f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
+}
+
+#else
+static void timer_init(void) { }
+#endif
diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake
new file mode 100644
index 000000000..0903a0143
--- /dev/null
+++ b/hw/bsp/f1c100s/family.cmake
@@ -0,0 +1,114 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/allwinner/f1c100s)
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR arm926ej-s CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS F1C100S CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/f1c100s.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/machine/start.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/lib/malloc.c
+    ${SDK_DIR}/lib/printf.c
+    ${SDK_DIR}/lib/memcpy.S
+    ${SDK_DIR}/lib/memset.S
+    ${SDK_DIR}/machine/sys-uart.c
+    ${SDK_DIR}/machine/exception.c
+    ${SDK_DIR}/machine/sys-clock.c
+    ${SDK_DIR}/machine/sys-copyself.c
+    ${SDK_DIR}/machine/sys-dram.c
+    ${SDK_DIR}/machine/sys-mmu.c
+    ${SDK_DIR}/machine/sys-spi-flash.c
+    ${SDK_DIR}/machine/f1c100s-intc.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __ARM32_ARCH__=5
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/include
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -lgcc
+      --specs=nosys.specs --specs=nano.specs
+      "LINKER:--defsym=__bss_end__=__bss_end"
+      "LINKER:--defsym=__bss_start__=__bss_start"
+      "LINKER:--defsym=end=__bss_end"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_F1C100S ${RTOS})
+  target_sources(${TARGET}-tinyusb PRIVATE
+    ${TOP}/src/portable/sunxi/dcd_sunxi_musb.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/f1c100s/family.mk b/hw/bsp/f1c100s/family.mk
new file mode 100644
index 000000000..be416e72e
--- /dev/null
+++ b/hw/bsp/f1c100s/family.mk
@@ -0,0 +1,58 @@
+SDK_DIR = hw/mcu/allwinner/f1c100s
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= arm926ej-s
+
+#CFLAGS += \
+#  -march=armv5te \
+#  -mtune=arm926ej-s \
+#  -mfloat-abi=soft \
+#  -marm \
+
+CFLAGS += \
+  -ffreestanding \
+  -std=gnu99 \
+  -mno-thumb-interwork \
+  -D__ARM32_ARCH__=5 \
+  -D__ARM926EJS__ \
+  -Wno-float-equal \
+  -Wno-unused-parameter \
+  -DCFG_TUSB_MCU=OPT_MCU_F1C100S \
+  -Wno-error=array-bounds \
+
+LD_FILE = ${SDK_DIR}/f1c100s.ld
+
+# TODO may skip nanolib
+LDFLAGS += \
+  -nostdlib -lgcc \
+  --specs=nosys.specs --specs=nano.specs \
+
+SRC_C += \
+	src/portable/sunxi/dcd_sunxi_musb.c \
+	${SDK_DIR}/machine/sys-uart.c \
+	${SDK_DIR}/machine/exception.c \
+	${SDK_DIR}/machine/sys-clock.c \
+	${SDK_DIR}/machine/sys-copyself.c \
+	${SDK_DIR}/machine/sys-dram.c \
+	${SDK_DIR}/machine/sys-mmu.c \
+	${SDK_DIR}/machine/sys-spi-flash.c \
+	${SDK_DIR}/machine/f1c100s-intc.c \
+	${SDK_DIR}/lib/malloc.c \
+	${SDK_DIR}/lib/printf.c
+
+SRC_S += \
+  ${SDK_DIR}/machine/start.S \
+	${SDK_DIR}/lib/memcpy.S \
+	${SDK_DIR}/lib/memset.S
+
+INC += \
+	$(TOP)/${SDK_DIR}/include \
+	$(TOP)/$(BOARD_PATH)
+
+# flash target using xfel
+flash: flash-xfel
+
+exec: $(BUILD)/$(PROJECT).bin
+	xfel ddr
+	xfel write 0x80000000 $<
+	xfel exec 0x80000000
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 6cc1975a8..6f36ad441 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -35,7 +35,9 @@
 #include <f1c100s-irq.h>
 #include <device/dcd.h>
 #include "musb_def.h"
-#include "bsp/board.h"
+
+//#include "bsp/board_api.h"
+extern uint32_t board_millis(void); // TODO remove
 
 typedef uint32_t u32;
 typedef uint16_t u16;
@@ -58,7 +60,7 @@ typedef struct TU_ATTR_PACKED
 
 typedef struct
 {
-  tusb_control_request_t setup_packet;
+  CFG_TUD_MEM_ALIGN tusb_control_request_t setup_packet;
   uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
   int8_t       status_out;
   pipe_state_t pipe0;
@@ -350,7 +352,7 @@ static void USBC_INT_DisableRxEp(u8 ep_index)
  * INTERNAL FUNCTION DECLARATION
  *------------------------------------------------------------------*/
 
-static dcd_data_t _dcd;
+CFG_TUD_MEM_ALIGN static dcd_data_t _dcd;
 
 static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
 {
@@ -560,7 +562,7 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
 
 static void process_setup_packet(uint8_t rhport)
 {
-  uint32_t *p = (uint32_t*)&_dcd.setup_packet;
+  uint32_t *p = (uint32_t*)(uintptr_t) &_dcd.setup_packet;
   p[0]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
   p[1]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
 
@@ -594,7 +596,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
   if (len) {
     volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
-      pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t *)(uintptr_t) buf, addr, len, TUSB_DIR_IN);
     } else {
       pipe_write_packet(buf, addr, len);
       pipe->buf       = buf + len;
@@ -622,7 +624,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
   if (len) {
     volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
-      pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t *)(uintptr_t )buf, addr, len, TUSB_DIR_OUT);
     } else {
       pipe_read_packet(buf, addr, len);
       pipe->buf       = buf + len;
-- 
cgit v1.3.1


From ea55537fb2a42e112c8d4f714c71c51b2faa88d6 Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Sun, 5 May 2024 20:33:01 +0200
Subject: minor changes due to CR with  HiFiPhile

---
 src/class/net/ncm.h        | 50 ++++++++++++++++++++++++++--------------------
 src/class/net/ncm_device.c |  6 +++---
 2 files changed, 31 insertions(+), 25 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h
index c768192a5..cf4daf96c 100644
--- a/src/class/net/ncm.h
+++ b/src/class/net/ncm.h
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright (c) 2024, Hardy Griech
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -29,42 +30,47 @@
 #define _TUSB_NCM_H_
 
 #include "common/tusb_common.h"
-
+#include "lwipopts.h"
 
 #ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
-    /// must be >> MTU
-    #define CFG_TUD_NCM_IN_NTB_MAX_SIZE        3200
+    #define CFG_TUD_NCM_IN_NTB_MAX_SIZE             (2 * TCP_MSS + 100)
 #endif
 #ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
-    /// must be >> MTU
-    #define CFG_TUD_NCM_OUT_NTB_MAX_SIZE       3200
+    #define CFG_TUD_NCM_OUT_NTB_MAX_SIZE            (2 * TCP_MSS + 100)
 #endif
 
 #ifndef CFG_TUD_NCM_OUT_NTB_N
-    /// number of ntb buffers for reception side
-    /// 1  - good performance
-    /// 2  - up to 30% more performance with iperf with small packets
-    /// >2 - no performance gain
-    #define CFG_TUD_NCM_OUT_NTB_N              2
+    /// number of NTB buffers for reception side
+    ///    1  - good performance
+    ///    2  - up to 30% more performance with iperf with small packets
+    ///    >2 - no performance gain
+    /// -> for performance optimizations this parameter could be increased with the cost of additional RAM requirements
+    #define CFG_TUD_NCM_OUT_NTB_N                   1
 #endif
 
 #ifndef CFG_TUD_NCM_IN_NTB_N
-    /// number of ntb buffers for transmission side
-    /// 1 - good performance but SystemView shows lost events (on load test)
-    /// 2 - up to 50% more performance with iperf with small packets, "tud_network_can_xmit: request blocked"
-    ///     happens from time to time with SystemView
-    /// 3 - "tud_network_can_xmit: request blocked" never happens
-    /// >2 - no performance gain
-    #define CFG_TUD_NCM_IN_NTB_N               3
+    /// number of NTB buffers for transmission side
+    ///    1 - good performance but SystemView shows lost events (on load test)
+    ///    2 - up to 50% more performance with iperf with small packets, "tud_network_can_xmit: request blocked"
+    ///        happens from time to time with SystemView
+    ///    3 - "tud_network_can_xmit: request blocked" never happens
+    ///    >2 - no performance gain
+    /// -> for performance optimizations this parameter could be increased with the cost of additional RAM requirements
+    #define CFG_TUD_NCM_IN_NTB_N                    1
+#endif
+
+#ifndef CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB
+    /// this is for the transmission side for allocation of \a ndp16_datagram_t
+    #define CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB    8
 #endif
 
-#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
-    /// this is for the transmission size for allocation of \a ndp16_datagram_t
-    #define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB  8
+#ifndef CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB
+    /// this tells the host how many datagrams it is allowed to put into an NTB
+    #define CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB   6
 #endif
 
 #ifndef CFG_TUD_NCM_ALIGNMENT
-    #define CFG_TUD_NCM_ALIGNMENT              4
+    #define CFG_TUD_NCM_ALIGNMENT                   4
 #endif
 #if (CFG_TUD_NCM_ALIGNMENT != 4)
     #error "CFG_TUD_NCM_ALIGNMENT must be 4, otherwise the headers and start of datagrams have to be aligned (which they are currently not)"
@@ -136,7 +142,7 @@ typedef union TU_ATTR_PACKED {
     struct {
         nth16_t          nth;
         ndp16_t          ndp;
-        ndp16_datagram_t ndp_datagram[CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1];
+        ndp16_datagram_t ndp_datagram[CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB + 1];
     };
     uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
 } xmit_ntb_t;
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 829161865..40f70dc3f 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -1,8 +1,8 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2023 Hardy Griech
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2024 Hardy Griech
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -126,7 +126,7 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par
         .wNdbOutDivisor          = 4,
         .wNdbOutPayloadRemainder = 0,
         .wNdbOutAlignment        = CFG_TUD_NCM_ALIGNMENT,
-        .wNtbOutMaxDatagrams     = 6                                     // 0=no limit
+        .wNtbOutMaxDatagrams     = CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB,
 };
 
 //-----------------------------------------------------------------------------
@@ -371,7 +371,7 @@ static bool xmit_requested_datagram_fits_into_current_ntb(uint16_t datagram_size
     if (ncm_interface.xmit_glue_ntb == NULL) {
         return false;
     }
-    if (ncm_interface.xmit_glue_ntb_datagram_ndx >= CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB) {
+    if (ncm_interface.xmit_glue_ntb_datagram_ndx >= CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB) {
         return false;
     }
     if (ncm_interface.xmit_glue_ntb->nth.wBlockLength + datagram_size + XMIT_ALIGN_OFFSET(datagram_size) > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-- 
cgit v1.3.1


From cc70958c16f4b88c0e48590d32189c870091547e Mon Sep 17 00:00:00 2001
From: Hardy Griech <ntbox@gmx.net>
Date: Sun, 5 May 2024 21:18:57 +0200
Subject: mostly comments

---
 src/class/net/ncm_device.c | 56 +++++++++++++++++++++++++++++-----------------
 1 file changed, 35 insertions(+), 21 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 40f70dc3f..05cebf94e 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -79,7 +79,7 @@ typedef struct {
     uint8_t     rhport;                            //!< storage of \a rhport because some callbacks are done without it
 
     // recv handling
-    CFG_TUSB_MEM_ALIGN recv_ntb_t  recv_ntb[RECV_NTB_N]; //!< actual recv NTBs
+    CFG_TUSB_MEM_ALIGN recv_ntb_t  recv_ntb[RECV_NTB_N];              //!< actual recv NTBs
     recv_ntb_t *recv_free_ntb[RECV_NTB_N];         //!< free list of recv NTBs
     recv_ntb_t *recv_ready_ntb[RECV_NTB_N];        //!< NTBs waiting for transmission to glue logic
     recv_ntb_t *recv_tinyusb_ntb;                  //!< buffer for the running transfer TinyUSB -> driver
@@ -87,7 +87,7 @@ typedef struct {
     uint16_t               recv_glue_ntb_datagram_ndx;        //!< index into \a recv_glue_ntb_datagram
 
     // xmit handling
-    CFG_TUSB_MEM_ALIGN xmit_ntb_t  xmit_ntb[XMIT_NTB_N]; //!< actual xmit NTBs
+    CFG_TUSB_MEM_ALIGN xmit_ntb_t  xmit_ntb[XMIT_NTB_N];              //!< actual xmit NTBs
     xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N];         //!< free list of xmit NTBs
     xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N];        //!< NTBs waiting for transmission to TinyUSB
     xmit_ntb_t *xmit_tinyusb_ntb;                  //!< buffer for the running transfer driver -> TinyUSB
@@ -129,6 +129,18 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par
         .wNtbOutMaxDatagrams     = CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB,
 };
 
+// Some confusing remarks about wNtbOutMaxDatagrams...
+//      ==1 -> SystemView packets/s goes up to 2000 and events are lost during startup
+//      ==0 -> SystemView runs fine, iperf shows in wireshark a lot of error
+//      ==6 -> SystemView runs fine, iperf also
+//      >6  -> iperf starts to show errors
+//      -> 6 seems to be the best value.  Why?  Don't know, perhaps only on my system?
+//      switch \a TU_LOG2 on to see interesting values for this.
+//
+//      iperf:    for MSS in 100 200 400 800 1200 1450 1500; do iperf -c 192.168.14.1 -e -i 1 -M $MSS -l 8192 -P 1; sleep 2; done
+//      sysview:  SYSTICKS_PER_SEC=35000, IDLE_US=1000, PRINT_MOD=1000
+//
+
 //-----------------------------------------------------------------------------
 //
 // everything about notifications
@@ -340,7 +352,7 @@ static void xmit_start_if_possible(uint8_t rhport)
         ncm_interface.xmit_glue_ntb = NULL;
     }
 
-#ifdef DEBUG_OUT_ENABLED
+#if CFG_TUSB_DEBUG >= 3
     {
         uint16_t len = ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength;
         TU_LOG3(" %d\n", len);
@@ -708,7 +720,7 @@ bool tud_network_can_xmit(uint16_t size)
         return true;
     }
     xmit_start_if_possible(ncm_interface.rhport);
-    TU_LOG2("tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
+    TU_LOG2("(II) tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
     return false;
 }   // tud_network_can_xmit
 
@@ -796,10 +808,18 @@ void netd_init(void)
     }
 }   // netd_init
 
-bool netd_deinit(void) {
-  return true;
+
+
+bool netd_deinit(void)
+/**
+ * Deinit driver
+ */
+{
+    return true;
 }
 
+
+
 void netd_reset(uint8_t rhport)
 /**
  * Resets the port.
@@ -947,12 +967,14 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     }
 
     switch (request->bmRequestType_bit.type) {
-        case TUSB_REQ_TYPE_STANDARD: {
+        case TUSB_REQ_TYPE_STANDARD:
+            TU_LOG3("  TUSB_REQ_TYPE_STANDARD: %d\n", request->bRequest);
+
             switch (request->bRequest) {
                 case TUSB_REQ_GET_INTERFACE: {
                     TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
 
-                    TU_LOG3("  TUSB_REQ_GET_INTERFACE - %d\n", ncm_interface.itf_data_alt);
+                    TU_LOG3("    TUSB_REQ_GET_INTERFACE - %d\n", ncm_interface.itf_data_alt);
                     tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
                 }
                 break;
@@ -961,7 +983,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
                     TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex  &&  request->wValue < 2, false);
 
                     ncm_interface.itf_data_alt = (uint8_t)request->wValue;
-                    TU_LOG3("  TUSB_REQ_SET_INTERFACE - %d %d %d\n", ncm_interface.itf_data_alt, request->wIndex, ncm_interface.itf_num);
+                    TU_LOG3("    TUSB_REQ_SET_INTERFACE - %d %d %d\n", ncm_interface.itf_data_alt, request->wIndex, ncm_interface.itf_num);
 
                     if (ncm_interface.itf_data_alt == 1) {
                         tud_network_recv_renew_r(rhport);
@@ -975,15 +997,14 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
                 default:
                     return false;
             }
-        }
-        break;
+            break;
 
-        case TUSB_REQ_TYPE_CLASS: {
+        case TUSB_REQ_TYPE_CLASS:
             TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
-            switch (request->bRequest) {
+
             TU_LOG3("  TUSB_REQ_TYPE_CLASS: %d\n", request->bRequest);
 
-            case NCM_GET_NTB_PARAMETERS: {
+            if (request->bRequest == NCM_GET_NTB_PARAMETERS) {
                 // transfer NTB parameters to host.
                 // TODO can one assume, that tud_control_xfer() succeeds?
                 TU_LOG3("    NCM_GET_NTB_PARAMETERS\n");
@@ -991,13 +1012,6 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
             }
             break;
 
-                // unsupported request
-            default:
-                return false ;
-
-            }
-        }
-        break;
             // unsupported request
         default:
             return false ;
-- 
cgit v1.3.1


From a9f1c62dffc2cb0229767959173f78eec9931db0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 May 2024 17:28:48 +0700
Subject: temp fix for mm32 redundant-decls of SystemCoreClock

---
 hw/bsp/mm32/family.c                             | 24 ++++++++++++++++--------
 src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 11 +++++++++++
 2 files changed, 27 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/hw/bsp/mm32/family.c b/hw/bsp/mm32/family.c
index f22fd90a1..f0fd6d334 100644
--- a/hw/bsp/mm32/family.c
+++ b/hw/bsp/mm32/family.c
@@ -30,6 +30,21 @@
 #include "bsp/board_api.h"
 #include "board.h"
 
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#ifdef __GNUC__ // caused by extra declaration of SystemCoreClock in freeRTOSConfig.h
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
+extern u32 SystemCoreClock;
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -46,19 +61,12 @@ void USB_DeviceClockInit(void) {
   /* Enable USB clock */
   RCC->AHB2ENR |= 0x1 << 7;
 }
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-extern u32 SystemCoreClock;
 
 void board_init(void) {
 //   usb clock
   USB_DeviceClockInit();
 
-  if (SysTick_Config(SystemCoreClock / 1000)) {
-    while (1);
-  }
+  SysTick_Config(SystemCoreClock / 1000);
   NVIC_SetPriority(SysTick_IRQn, 0x0);
 
   RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index c3d0c7297..d5c0daaeb 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -283,7 +283,18 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   /* Response with status first before changing device address */
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
+
+#ifdef __GNUC__ // caused by extra declaration of SystemCoreClock in freeRTOSConfig.h
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
 extern u32 SystemCoreClock;
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
-- 
cgit v1.3.1


From 91d69fa942c8a450c9816595f0d19138964533ef Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 7 May 2024 00:10:26 +0200
Subject: Reformat NCM class.

---
 src/class/net/ncm.h        |  141 +++--
 src/class/net/ncm_device.c | 1270 ++++++++++++++++++++------------------------
 2 files changed, 640 insertions(+), 771 deletions(-)

(limited to 'src')

diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h
index cf4daf96c..1b987fca0 100644
--- a/src/class/net/ncm.h
+++ b/src/class/net/ncm.h
@@ -25,58 +25,59 @@
  * This file is part of the TinyUSB stack.
  */
 
-
 #ifndef _TUSB_NCM_H_
 #define _TUSB_NCM_H_
 
 #include "common/tusb_common.h"
-#include "lwipopts.h"
 
-#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
-    #define CFG_TUD_NCM_IN_NTB_MAX_SIZE             (2 * TCP_MSS + 100)
-#endif
+// NTB buffers size for reception side, must be >> MTU to avoid TCP retransmission (driver issue ?)
+// Linux use 2048 as minimal size
 #ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
-    #define CFG_TUD_NCM_OUT_NTB_MAX_SIZE            (2 * TCP_MSS + 100)
+  #define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
+#endif
+
+// NTB buffers size for reception side, must be > MTU
+// Linux use 2048 as minimal size
+#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
+  #define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
 #endif
 
+// Number of NTB buffers for reception side
+// Depending on the configuration, this parameter could be increased with the cost of additional RAM requirements
+// On Full-Speed (RP2040) :
+//    1  - good performance
+//    2  - up to 30% more performance with iperf with small packets
+//    >2 - no performance gain
+// On High-Speed (STM32F7) :
+//    No performance gain
 #ifndef CFG_TUD_NCM_OUT_NTB_N
-    /// number of NTB buffers for reception side
-    ///    1  - good performance
-    ///    2  - up to 30% more performance with iperf with small packets
-    ///    >2 - no performance gain
-    /// -> for performance optimizations this parameter could be increased with the cost of additional RAM requirements
-    #define CFG_TUD_NCM_OUT_NTB_N                   1
+  #define CFG_TUD_NCM_OUT_NTB_N 1
 #endif
 
+// Number of NTB buffers for transmission side
+// Depending on the configuration, this parameter could be increased with the cost of additional RAM requirements
+// On Full-Speed (RP2040) :
+//    1 - good performance but SystemView shows lost events (on load test)
+//    2 - up to 50% more performance with iperf with small packets, "tud_network_can_xmit: request blocked"
+//        happens from time to time with SystemView
+//    3 - "tud_network_can_xmit: request blocked" never happens
+//    >3 - no performance gain
+// On High-Speed (STM32F7) :
+//    No performance gain
 #ifndef CFG_TUD_NCM_IN_NTB_N
-    /// number of NTB buffers for transmission side
-    ///    1 - good performance but SystemView shows lost events (on load test)
-    ///    2 - up to 50% more performance with iperf with small packets, "tud_network_can_xmit: request blocked"
-    ///        happens from time to time with SystemView
-    ///    3 - "tud_network_can_xmit: request blocked" never happens
-    ///    >2 - no performance gain
-    /// -> for performance optimizations this parameter could be increased with the cost of additional RAM requirements
-    #define CFG_TUD_NCM_IN_NTB_N                    1
+  #define CFG_TUD_NCM_IN_NTB_N 1
 #endif
 
+// How many datagrams it is allowed to put into an NTB for transmission side
 #ifndef CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB
-    /// this is for the transmission side for allocation of \a ndp16_datagram_t
-    #define CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB    8
+  #define CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB 8
 #endif
 
+// This tells the host how many datagrams it is allowed to put into an NTB
 #ifndef CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB
-    /// this tells the host how many datagrams it is allowed to put into an NTB
-    #define CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB   6
+  #define CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB 6
 #endif
 
-#ifndef CFG_TUD_NCM_ALIGNMENT
-    #define CFG_TUD_NCM_ALIGNMENT                   4
-#endif
-#if (CFG_TUD_NCM_ALIGNMENT != 4)
-    #error "CFG_TUD_NCM_ALIGNMENT must be 4, otherwise the headers and start of datagrams have to be aligned (which they are currently not)"
-#endif
-
-
 // Table 6.2 Class-Specific Request Codes for Network Control Model subclass
 typedef enum
 {
@@ -98,67 +99,65 @@ typedef enum
   NCM_SET_CRC_MODE                                 = 0x8A,
 } ncm_request_code_t;
 
-
-#define NTH16_SIGNATURE      0x484D434E
+#define NTH16_SIGNATURE 0x484D434E
 #define NDP16_SIGNATURE_NCM0 0x304D434E
 #define NDP16_SIGNATURE_NCM1 0x314D434E
 
 typedef struct TU_ATTR_PACKED {
-    uint16_t wLength;
-    uint16_t bmNtbFormatsSupported;
-    uint32_t dwNtbInMaxSize;
-    uint16_t wNdbInDivisor;
-    uint16_t wNdbInPayloadRemainder;
-    uint16_t wNdbInAlignment;
-    uint16_t wReserved;
-    uint32_t dwNtbOutMaxSize;
-    uint16_t wNdbOutDivisor;
-    uint16_t wNdbOutPayloadRemainder;
-    uint16_t wNdbOutAlignment;
-    uint16_t wNtbOutMaxDatagrams;
+  uint16_t wLength;
+  uint16_t bmNtbFormatsSupported;
+  uint32_t dwNtbInMaxSize;
+  uint16_t wNdbInDivisor;
+  uint16_t wNdbInPayloadRemainder;
+  uint16_t wNdbInAlignment;
+  uint16_t wReserved;
+  uint32_t dwNtbOutMaxSize;
+  uint16_t wNdbOutDivisor;
+  uint16_t wNdbOutPayloadRemainder;
+  uint16_t wNdbOutAlignment;
+  uint16_t wNtbOutMaxDatagrams;
 } ntb_parameters_t;
 
 typedef struct TU_ATTR_PACKED {
-    uint32_t dwSignature;
-    uint16_t wHeaderLength;
-    uint16_t wSequence;
-    uint16_t wBlockLength;
-    uint16_t wNdpIndex;
+  uint32_t dwSignature;
+  uint16_t wHeaderLength;
+  uint16_t wSequence;
+  uint16_t wBlockLength;
+  uint16_t wNdpIndex;
 } nth16_t;
 
 typedef struct TU_ATTR_PACKED {
-    uint16_t wDatagramIndex;
-    uint16_t wDatagramLength;
+  uint16_t wDatagramIndex;
+  uint16_t wDatagramLength;
 } ndp16_datagram_t;
 
 typedef struct TU_ATTR_PACKED {
-    uint32_t dwSignature;
-    uint16_t wLength;
-    uint16_t wNextNdpIndex;
-    //ndp16_datagram_t datagram[];
+  uint32_t dwSignature;
+  uint16_t wLength;
+  uint16_t wNextNdpIndex;
+  //ndp16_datagram_t datagram[];
 } ndp16_t;
 
 typedef union TU_ATTR_PACKED {
-    struct {
-        nth16_t          nth;
-        ndp16_t          ndp;
-        ndp16_datagram_t ndp_datagram[CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB + 1];
-    };
-    uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
+  struct {
+    nth16_t nth;
+    ndp16_t ndp;
+    ndp16_datagram_t ndp_datagram[CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB + 1];
+  };
+  uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
 } xmit_ntb_t;
 
 typedef union TU_ATTR_PACKED {
-    struct {
-        nth16_t nth;
-        // only the header is at a guaranteed position
-    };
-    uint8_t data[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+  struct {
+    nth16_t nth;
+    // only the header is at a guaranteed position
+  };
+  uint8_t data[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
 } recv_ntb_t;
 
 struct ncm_notify_t {
-    tusb_control_request_t header;
-    uint32_t               downlink, uplink;
+  tusb_control_request_t header;
+  uint32_t downlink, uplink;
 };
 
-
 #endif
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 05cebf94e..4b237e4cf 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -46,7 +46,7 @@
 
 #include "tusb_option.h"
 
-#if defined(ECLIPSE_GUI) || ( CFG_TUD_ENABLED && CFG_TUD_NCM )
+#if (CFG_TUD_ENABLED && CFG_TUD_NCM)
 
 #include <stdbool.h>
 #include <stdint.h>
@@ -55,59 +55,65 @@
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
 
-#include "net_device.h"
 #include "ncm.h"
+#include "net_device.h"
+
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_NCM_LOG_LEVEL
+  #define CFG_TUD_NCM_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
 
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_NCM_LOG_LEVEL, __VA_ARGS__)
 
+// Alignment must be 4
+#define TUD_NCM_ALIGNMENT   4
 // calculate alignment of xmit datagrams within an NTB
-#define XMIT_ALIGN_OFFSET(x)   ((CFG_TUD_NCM_ALIGNMENT - ((x) & (CFG_TUD_NCM_ALIGNMENT - 1))) & (CFG_TUD_NCM_ALIGNMENT - 1))
+#define XMIT_ALIGN_OFFSET(x) ((TUD_NCM_ALIGNMENT - ((x) & (TUD_NCM_ALIGNMENT - 1))) & (TUD_NCM_ALIGNMENT - 1))
 
 //-----------------------------------------------------------------------------
 //
 // Module global things
 //
-#define XMIT_NTB_N         CFG_TUD_NCM_IN_NTB_N
-#define RECV_NTB_N         CFG_TUD_NCM_OUT_NTB_N
+#define XMIT_NTB_N CFG_TUD_NCM_IN_NTB_N
+#define RECV_NTB_N CFG_TUD_NCM_OUT_NTB_N
 
 typedef struct {
-    // general
-    uint8_t     ep_in;                             //!< endpoint for outgoing datagrams (naming is a little bit confusing)
-    uint8_t     ep_out;                            //!< endpoint for incoming datagrams (naming is a little bit confusing)
-    uint8_t     ep_notif;                          //!< endpoint for notifications
-    uint8_t     itf_num;                           //!< interface number
-    uint8_t     itf_data_alt;                      //!< ==0 -> no endpoints, i.e. no network traffic, ==1 -> normal operation with two endpoints (spec, chapter 5.3)
-    uint8_t     rhport;                            //!< storage of \a rhport because some callbacks are done without it
-
-    // recv handling
-    CFG_TUSB_MEM_ALIGN recv_ntb_t  recv_ntb[RECV_NTB_N];              //!< actual recv NTBs
-    recv_ntb_t *recv_free_ntb[RECV_NTB_N];         //!< free list of recv NTBs
-    recv_ntb_t *recv_ready_ntb[RECV_NTB_N];        //!< NTBs waiting for transmission to glue logic
-    recv_ntb_t *recv_tinyusb_ntb;                  //!< buffer for the running transfer TinyUSB -> driver
-    recv_ntb_t *recv_glue_ntb;                     //!< buffer for the running transfer driver -> glue logic
-    uint16_t               recv_glue_ntb_datagram_ndx;        //!< index into \a recv_glue_ntb_datagram
-
-    // xmit handling
-    CFG_TUSB_MEM_ALIGN xmit_ntb_t  xmit_ntb[XMIT_NTB_N];              //!< actual xmit NTBs
-    xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N];         //!< free list of xmit NTBs
-    xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N];        //!< NTBs waiting for transmission to TinyUSB
-    xmit_ntb_t *xmit_tinyusb_ntb;                  //!< buffer for the running transfer driver -> TinyUSB
-    xmit_ntb_t *xmit_glue_ntb;                     //!< buffer for the running transfer glue logic -> driver
-    uint16_t    xmit_sequence;                     //!< NTB sequence counter
-    uint16_t    xmit_glue_ntb_datagram_ndx;        //!< index into \a xmit_glue_ntb_datagram
-
-    // notification handling
-    enum {
-        NOTIFICATION_SPEED,
-        NOTIFICATION_CONNECTED,
-        NOTIFICATION_DONE
-    } notification_xmit_state;                     //!< state of notification transmission
-    bool        notification_xmit_is_running;      //!< notification is currently transmitted
+  // general
+  uint8_t ep_in;        // endpoint for outgoing datagrams (naming is a little bit confusing)
+  uint8_t ep_out;       // endpoint for incoming datagrams (naming is a little bit confusing)
+  uint8_t ep_notif;     // endpoint for notifications
+  uint8_t itf_num;      // interface number
+  uint8_t itf_data_alt; // ==0 -> no endpoints, i.e. no network traffic, ==1 -> normal operation with two endpoints (spec, chapter 5.3)
+  uint8_t rhport;       // storage of \a rhport because some callbacks are done without it
+
+  // recv handling
+  CFG_TUSB_MEM_ALIGN recv_ntb_t recv_ntb[RECV_NTB_N];   // actual recv NTBs
+  recv_ntb_t *recv_free_ntb[RECV_NTB_N];                // free list of recv NTBs
+  recv_ntb_t *recv_ready_ntb[RECV_NTB_N];               // NTBs waiting for transmission to glue logic
+  recv_ntb_t *recv_tinyusb_ntb;                         // buffer for the running transfer TinyUSB -> driver
+  recv_ntb_t *recv_glue_ntb;                            // buffer for the running transfer driver -> glue logic
+  uint16_t recv_glue_ntb_datagram_ndx;                  // index into \a recv_glue_ntb_datagram
+
+  // xmit handling
+  CFG_TUSB_MEM_ALIGN xmit_ntb_t xmit_ntb[XMIT_NTB_N];   // actual xmit NTBs
+  xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N];                // free list of xmit NTBs
+  xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N];               // NTBs waiting for transmission to TinyUSB
+  xmit_ntb_t *xmit_tinyusb_ntb;                         // buffer for the running transfer driver -> TinyUSB
+  xmit_ntb_t *xmit_glue_ntb;                            // buffer for the running transfer glue logic -> driver
+  uint16_t xmit_sequence;                               // NTB sequence counter
+  uint16_t xmit_glue_ntb_datagram_ndx;                  // index into \a xmit_glue_ntb_datagram
+
+  // notification handling
+  enum {
+    NOTIFICATION_SPEED,
+    NOTIFICATION_CONNECTED,
+    NOTIFICATION_DONE
+  } notification_xmit_state;            // state of notification transmission
+  bool notification_xmit_is_running;    // notification is currently transmitted
 } ncm_interface_t;
 
-
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static ncm_interface_t ncm_interface;
 
-
 /**
  * This is the NTB parameter structure
  *
@@ -115,18 +121,18 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static ncm_interface_t ncm_interface;
  *     We are lucky, that byte order is correct
  */
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
-        .wLength                 = sizeof(ntb_parameters_t),
-        .bmNtbFormatsSupported   = 0x01,                                 // 16-bit NTB supported
-        .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
-        .wNdbInDivisor           = 4,
-        .wNdbInPayloadRemainder  = 0,
-        .wNdbInAlignment         = CFG_TUD_NCM_ALIGNMENT,
-        .wReserved               = 0,
-        .dwNtbOutMaxSize         = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
-        .wNdbOutDivisor          = 4,
-        .wNdbOutPayloadRemainder = 0,
-        .wNdbOutAlignment        = CFG_TUD_NCM_ALIGNMENT,
-        .wNtbOutMaxDatagrams     = CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB,
+  .wLength                  = sizeof(ntb_parameters_t),
+  .bmNtbFormatsSupported    = 0x01,// 16-bit NTB supported
+  .dwNtbInMaxSize           = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
+  .wNdbInDivisor            = 1,
+  .wNdbInPayloadRemainder   = 0,
+  .wNdbInAlignment          = TUD_NCM_ALIGNMENT,
+  .wReserved                = 0,
+  .dwNtbOutMaxSize          = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
+  .wNdbOutDivisor           = 1,
+  .wNdbOutPayloadRemainder  = 0,
+  .wNdbOutAlignment         = TUD_NCM_ALIGNMENT,
+  .wNtbOutMaxDatagrams      = CFG_TUD_NCM_OUT_MAX_DATAGRAMS_PER_NTB,
 };
 
 // Some confusing remarks about wNtbOutMaxDatagrams...
@@ -135,7 +141,6 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par
 //      ==6 -> SystemView runs fine, iperf also
 //      >6  -> iperf starts to show errors
 //      -> 6 seems to be the best value.  Why?  Don't know, perhaps only on my system?
-//      switch \a TU_LOG2 on to see interesting values for this.
 //
 //      iperf:    for MSS in 100 200 400 800 1200 1450 1500; do iperf -c 192.168.14.1 -e -i 1 -M $MSS -l 8192 -P 1; sleep 2; done
 //      sysview:  SYSTICKS_PER_SEC=35000, IDLE_US=1000, PRINT_MOD=1000
@@ -146,151 +151,128 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par
 // everything about notifications
 //
 tu_static struct ncm_notify_t ncm_notify_connected = {
-        .header = {
-                .bmRequestType_bit = {
-                        .recipient = TUSB_REQ_RCPT_INTERFACE,
-                        .type      = TUSB_REQ_TYPE_CLASS,
-                        .direction = TUSB_DIR_IN
-                },
-                .bRequest = CDC_NOTIF_NETWORK_CONNECTION,
-                .wValue   = 1 /* Connected */,
-                .wLength  = 0,
-        },
+    .header = {
+        .bmRequestType_bit = {
+            .recipient = TUSB_REQ_RCPT_INTERFACE,
+            .type = TUSB_REQ_TYPE_CLASS,
+            .direction = TUSB_DIR_IN},
+        .bRequest = CDC_NOTIF_NETWORK_CONNECTION,
+        .wValue = 1 /* Connected */,
+        .wLength = 0,
+    },
 };
 
 tu_static struct ncm_notify_t ncm_notify_speed_change = {
-        .header = {
-                .bmRequestType_bit = {
-                        .recipient = TUSB_REQ_RCPT_INTERFACE,
-                        .type      = TUSB_REQ_TYPE_CLASS,
-                        .direction = TUSB_DIR_IN
-                },
-                .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
-                .wLength  = 8,
-        },
-        .downlink = 12000000,
-        .uplink   = 12000000,
+    .header = {
+        .bmRequestType_bit = {
+            .recipient = TUSB_REQ_RCPT_INTERFACE,
+            .type = TUSB_REQ_TYPE_CLASS,
+            .direction = TUSB_DIR_IN},
+        .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
+        .wLength = 8,
+    },
+    .downlink = TUD_OPT_HIGH_SPEED ? 480000000 : 12000000,
+    .uplink = TUD_OPT_HIGH_SPEED ? 480000000 : 12000000,
 };
 
-
-
-static void notification_xmit(uint8_t rhport, bool force_next)
 /**
  * Transmit next notification to the host (if appropriate).
  * Notifications are transferred to the host once during connection setup.
  */
-{
-    TU_LOG3("notification_xmit(%d, %d) - %d %d\n", force_next, rhport, ncm_interface.notification_xmit_state, ncm_interface.notification_xmit_is_running);
-
-    if ( !force_next  &&  ncm_interface.notification_xmit_is_running) {
-        return;
-    }
-
-    if (ncm_interface.notification_xmit_state == NOTIFICATION_SPEED) {
-        TU_LOG3("  NOTIFICATION_SPEED\n");
-        ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
-        usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t*) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
-        ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED;
-        ncm_interface.notification_xmit_is_running = true;
-    }
-    else if (ncm_interface.notification_xmit_state == NOTIFICATION_CONNECTED) {
-        TU_LOG3("  NOTIFICATION_CONNECTED\n");
-        ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
-        usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t*) &ncm_notify_connected, sizeof(ncm_notify_connected));
-        ncm_interface.notification_xmit_state = NOTIFICATION_DONE;
-        ncm_interface.notification_xmit_is_running = true;
-    }
-    else {
-        TU_LOG3("  NOTIFICATION_FINISHED\n");
-    }
-}   // notification_xmit
-
+static void notification_xmit(uint8_t rhport, bool force_next) {
+  TU_LOG_DRV("notification_xmit(%d, %d) - %d %d\n", force_next, rhport, ncm_interface.notification_xmit_state, ncm_interface.notification_xmit_is_running);
+
+  if (!force_next && ncm_interface.notification_xmit_is_running) {
+    return;
+  }
+
+  if (ncm_interface.notification_xmit_state == NOTIFICATION_SPEED) {
+    TU_LOG_DRV("  NOTIFICATION_SPEED\n");
+    ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
+    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
+    ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED;
+    ncm_interface.notification_xmit_is_running = true;
+  } else if (ncm_interface.notification_xmit_state == NOTIFICATION_CONNECTED) {
+    TU_LOG_DRV("  NOTIFICATION_CONNECTED\n");
+    ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
+    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
+    ncm_interface.notification_xmit_state = NOTIFICATION_DONE;
+    ncm_interface.notification_xmit_is_running = true;
+  } else {
+    TU_LOG_DRV("  NOTIFICATION_FINISHED\n");
+  }
+} // notification_xmit
 
 //-----------------------------------------------------------------------------
 //
 // everything about packet transmission (driver -> TinyUSB)
 //
 
-
-static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb)
 /**
  * Put NTB into the transmitter free list.
  */
-{
-    TU_LOG3("xmit_put_ntb_into_free_list() - %p\n", ncm_interface.xmit_tinyusb_ntb);
+static void xmit_put_ntb_into_free_list(xmit_ntb_t *free_ntb) {
+  TU_LOG_DRV("xmit_put_ntb_into_free_list() - %p\n", ncm_interface.xmit_tinyusb_ntb);
 
-    if (free_ntb == NULL) {
-        // can happen due to ZLPs
-        return;
-    }
+  if (free_ntb == NULL) { // can happen due to ZLPs
+    return;
+  }
 
-    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
-        if (ncm_interface.xmit_free_ntb[i] == NULL) {
-            ncm_interface.xmit_free_ntb[i] = free_ntb;
-            return;
-        }
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    if (ncm_interface.xmit_free_ntb[i] == NULL) {
+      ncm_interface.xmit_free_ntb[i] = free_ntb;
+      return;
     }
-    TU_LOG1("(EE) xmit_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
-}   // xmit_put_ntb_into_free_list
-
-
+  }
+  TU_LOG_DRV("(EE) xmit_put_ntb_into_free_list - no entry in free list\n");// this should not happen
+} // xmit_put_ntb_into_free_list
 
-static xmit_ntb_t *xmit_get_free_ntb(void)
 /**
  * Get an NTB from the free list
  */
-{
-    TU_LOG3("xmit_get_free_ntb()\n");
-
-    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
-        if (ncm_interface.xmit_free_ntb[i] != NULL) {
-            xmit_ntb_t *free = ncm_interface.xmit_free_ntb[i];
-            ncm_interface.xmit_free_ntb[i] = NULL;
-            return free;
-        }
-    }
-    return NULL;
-}   // xmit_get_free_ntb
-
+static xmit_ntb_t *xmit_get_free_ntb(void) {
+  TU_LOG_DRV("xmit_get_free_ntb()\n");
 
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    if (ncm_interface.xmit_free_ntb[i] != NULL) {
+      xmit_ntb_t *free = ncm_interface.xmit_free_ntb[i];
+      ncm_interface.xmit_free_ntb[i] = NULL;
+      return free;
+    }
+  }
+  return NULL;
+} // xmit_get_free_ntb
 
-static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb)
 /**
  * Put a filled NTB into the ready list
  */
-{
-    TU_LOG2("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
+static void xmit_put_ntb_into_ready_list(xmit_ntb_t *ready_ntb) {
+  TU_LOG_DRV("xmit_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
 
-    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
-        if (ncm_interface.xmit_ready_ntb[i] == NULL) {
-            ncm_interface.xmit_ready_ntb[i] = ready_ntb;
-            return;
-        }
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    if (ncm_interface.xmit_ready_ntb[i] == NULL) {
+      ncm_interface.xmit_ready_ntb[i] = ready_ntb;
+      return;
     }
-    TU_LOG1("(EE) xmit_put_ntb_into_ready_list: ready list full\n");  // this should not happen
-}   // xmit_put_ntb_into_ready_list
+  }
+  TU_LOG_DRV("(EE) xmit_put_ntb_into_ready_list: ready list full\n");// this should not happen
+} // xmit_put_ntb_into_ready_list
 
-
-
-static xmit_ntb_t *xmit_get_next_ready_ntb(void)
 /**
  * Get the next NTB from the ready list (and remove it from the list).
  * If the ready list is empty, return NULL.
  */
-{
-    xmit_ntb_t *r = NULL;
-
-    r = ncm_interface.xmit_ready_ntb[0];
-    memmove(ncm_interface.xmit_ready_ntb + 0, ncm_interface.xmit_ready_ntb + 1, sizeof(ncm_interface.xmit_ready_ntb) - sizeof(ncm_interface.xmit_ready_ntb[0]));
-    ncm_interface.xmit_ready_ntb[XMIT_NTB_N - 1] = NULL;
+static xmit_ntb_t *xmit_get_next_ready_ntb(void) {
+  xmit_ntb_t *r = NULL;
 
-    TU_LOG3("recv_get_next_ready_ntb: %p\n", r);
-    return r;
-}   // xmit_get_next_ready_ntb
+  r = ncm_interface.xmit_ready_ntb[0];
+  memmove(ncm_interface.xmit_ready_ntb + 0, ncm_interface.xmit_ready_ntb + 1, sizeof(ncm_interface.xmit_ready_ntb) - sizeof(ncm_interface.xmit_ready_ntb[0]));
+  ncm_interface.xmit_ready_ntb[XMIT_NTB_N - 1] = NULL;
 
+  TU_LOG_DRV("recv_get_next_ready_ntb: %p\n", r);
+  return r;
+} // xmit_get_next_ready_ntb
 
-
-static bool xmit_insert_required_zlp(uint8_t rhport, uint32_t xferred_bytes)
 /**
  * Transmit a ZLP if required
  *
@@ -302,252 +284,221 @@ static bool xmit_insert_required_zlp(uint8_t rhport, uint32_t xferred_bytes)
  * \pre
  *    This must be called from netd_xfer_cb() so that ep_in is ready
  */
-{
-    TU_LOG3("xmit_insert_required_zlp(%d,%d)\n", rhport, xferred_bytes);
-
-    if (xferred_bytes == 0  ||  xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE != 0) {
-        return false;
-    }
+static bool xmit_insert_required_zlp(uint8_t rhport, uint32_t xferred_bytes) {
+  TU_LOG_DRV("xmit_insert_required_zlp(%d,%d)\n", rhport, xferred_bytes);
 
-    TU_ASSERT(ncm_interface.itf_data_alt == 1, false);
-    TU_ASSERT( !usbd_edpt_busy(rhport, ncm_interface.ep_in), false);
-
-    TU_LOG2("xmit_insert_required_zlp! (%u)\n", (unsigned)xferred_bytes);
+  if (xferred_bytes == 0 || xferred_bytes % CFG_TUD_NET_ENDPOINT_SIZE != 0) {
+    return false;
+  }
 
-    // start transmission of the ZLP
-    usbd_edpt_xfer(rhport, ncm_interface.ep_in, NULL, 0);
+  TU_ASSERT(ncm_interface.itf_data_alt == 1, false);
+  TU_ASSERT(!usbd_edpt_busy(rhport, ncm_interface.ep_in), false);
 
-    return true;
-}   // xmit_insert_required_zlp
+  TU_LOG_DRV("xmit_insert_required_zlp! (%u)\n", (unsigned) xferred_bytes);
 
+  // start transmission of the ZLP
+  usbd_edpt_xfer(rhport, ncm_interface.ep_in, NULL, 0);
 
+  return true;
+} // xmit_insert_required_zlp
 
-static void xmit_start_if_possible(uint8_t rhport)
 /**
  * Start transmission if it there is a waiting packet and if can be done from interface side.
  */
-{
-    TU_LOG3("xmit_start_if_possible()\n");
-
-    if (ncm_interface.xmit_tinyusb_ntb != NULL) {
-        TU_LOG3("  !xmit_start_if_possible 1\n");
-        return;
-    }
-    if (ncm_interface.itf_data_alt != 1) {
-        TU_LOG1("(EE) !xmit_start_if_possible 2\n");
-        return;
-    }
-    if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
-        TU_LOG2("  !xmit_start_if_possible 3\n");
-        return;
-    }
+static void xmit_start_if_possible(uint8_t rhport) {
+  TU_LOG_DRV("xmit_start_if_possible()\n");
+
+  if (ncm_interface.xmit_tinyusb_ntb != NULL) {
+    TU_LOG_DRV("  !xmit_start_if_possible 1\n");
+    return;
+  }
+  if (ncm_interface.itf_data_alt != 1) {
+    TU_LOG_DRV("(EE) !xmit_start_if_possible 2\n");
+    return;
+  }
+  if (usbd_edpt_busy(rhport, ncm_interface.ep_in)) {
+    TU_LOG_DRV("  !xmit_start_if_possible 3\n");
+    return;
+  }
+
+  ncm_interface.xmit_tinyusb_ntb = xmit_get_next_ready_ntb();
+  if (ncm_interface.xmit_tinyusb_ntb == NULL) {
+    if (ncm_interface.xmit_glue_ntb == NULL || ncm_interface.xmit_glue_ntb_datagram_ndx == 0) {
+      // -> really nothing is waiting
+      return;
+    }
+    ncm_interface.xmit_tinyusb_ntb = ncm_interface.xmit_glue_ntb;
+    ncm_interface.xmit_glue_ntb = NULL;
+  }
+
+  #if CFG_TUD_NCM_LOG_LEVEL >= 3
+  {
+    uint16_t len = ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength;
+    TU_LOG_BUF(3, ncm_interface.xmit_tinyusb_ntb->data[i], len);
+  }
+  #endif
+
+  if (ncm_interface.xmit_glue_ntb_datagram_ndx != 1) {
+    TU_LOG_DRV(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength, ncm_interface.xmit_glue_ntb_datagram_ndx);
+  }
+
+  // Kick off an endpoint transfer
+  usbd_edpt_xfer(0, ncm_interface.ep_in, ncm_interface.xmit_tinyusb_ntb->data, ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength);
+} // xmit_start_if_possible
 
-    ncm_interface.xmit_tinyusb_ntb = xmit_get_next_ready_ntb();
-    if (ncm_interface.xmit_tinyusb_ntb == NULL) {
-        if (ncm_interface.xmit_glue_ntb == NULL  ||  ncm_interface.xmit_glue_ntb_datagram_ndx == 0) {
-            // -> really nothing is waiting
-            return;
-        }
-        ncm_interface.xmit_tinyusb_ntb = ncm_interface.xmit_glue_ntb;
-        ncm_interface.xmit_glue_ntb = NULL;
-    }
-
-#if CFG_TUSB_DEBUG >= 3
-    {
-        uint16_t len = ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength;
-        TU_LOG3(" %d\n", len);
-        for (int i = 0;  i < len;  ++i) {
-            TU_LOG3(" %02x", ncm_interface.xmit_tinyusb_ntb->data[i]);
-        }
-        TU_LOG3("\n");
-    }
-#endif
-
-    if (ncm_interface.xmit_glue_ntb_datagram_ndx != 1) {
-        TU_LOG3(">> %d %d\n", ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength, ncm_interface.xmit_glue_ntb_datagram_ndx);
-    }
-
-    // Kick off an endpoint transfer
-    usbd_edpt_xfer(0, ncm_interface.ep_in, ncm_interface.xmit_tinyusb_ntb->data, ncm_interface.xmit_tinyusb_ntb->nth.wBlockLength);
-}   // xmit_start_if_possible
-
-
-
-static bool xmit_requested_datagram_fits_into_current_ntb(uint16_t datagram_size)
 /**
  * check if a new datagram fits into the current NTB
  */
-{
-    TU_LOG3("xmit_requested_datagram_fits_into_current_ntb(%d) - %p %p\n", datagram_size, ncm_interface.xmit_tinyusb_ntb, ncm_interface.xmit_glue_ntb);
-
-    if (ncm_interface.xmit_glue_ntb == NULL) {
-        return false;
-    }
-    if (ncm_interface.xmit_glue_ntb_datagram_ndx >= CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB) {
-        return false;
-    }
-    if (ncm_interface.xmit_glue_ntb->nth.wBlockLength + datagram_size + XMIT_ALIGN_OFFSET(datagram_size) > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        return false;
-    }
-    return true;
-}   // xmit_requested_datagram_fits_into_current_ntb
-
+static bool xmit_requested_datagram_fits_into_current_ntb(uint16_t datagram_size) {
+  TU_LOG_DRV("xmit_requested_datagram_fits_into_current_ntb(%d) - %p %p\n", datagram_size, ncm_interface.xmit_tinyusb_ntb, ncm_interface.xmit_glue_ntb);
 
+  if (ncm_interface.xmit_glue_ntb == NULL) {
+    return false;
+  }
+  if (ncm_interface.xmit_glue_ntb_datagram_ndx >= CFG_TUD_NCM_IN_MAX_DATAGRAMS_PER_NTB) {
+    return false;
+  }
+  if (ncm_interface.xmit_glue_ntb->nth.wBlockLength + datagram_size + XMIT_ALIGN_OFFSET(datagram_size) > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+    return false;
+  }
+  return true;
+} // xmit_requested_datagram_fits_into_current_ntb
 
-static bool xmit_setup_next_glue_ntb(void)
 /**
  * Setup an NTB for the glue logic
  */
-{
-    TU_LOG3("xmit_setup_next_glue_ntb - %p\n", ncm_interface.xmit_glue_ntb);
+static bool xmit_setup_next_glue_ntb(void) {
+  TU_LOG_DRV("xmit_setup_next_glue_ntb - %p\n", ncm_interface.xmit_glue_ntb);
 
-    if (ncm_interface.xmit_glue_ntb != NULL) {
-        // put NTB into waiting list (the new datagram did not fit in)
-        xmit_put_ntb_into_ready_list(ncm_interface.xmit_glue_ntb);
-    }
+  if (ncm_interface.xmit_glue_ntb != NULL) {
+    // put NTB into waiting list (the new datagram did not fit in)
+    xmit_put_ntb_into_ready_list(ncm_interface.xmit_glue_ntb);
+  }
 
-    ncm_interface.xmit_glue_ntb = xmit_get_free_ntb();              // get next buffer (if any)
-    if (ncm_interface.xmit_glue_ntb == NULL) {
-        TU_LOG3("  xmit_setup_next_glue_ntb - nothing free\n");   // should happen rarely
-        return false;
-    }
-
-    ncm_interface.xmit_glue_ntb_datagram_ndx = 0;
+  ncm_interface.xmit_glue_ntb = xmit_get_free_ntb();// get next buffer (if any)
+  if (ncm_interface.xmit_glue_ntb == NULL) {
+    TU_LOG_DRV("  xmit_setup_next_glue_ntb - nothing free\n");// should happen rarely
+    return false;
+  }
 
-    xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
+  ncm_interface.xmit_glue_ntb_datagram_ndx = 0;
 
-    // Fill in NTB header
-    ntb->nth.dwSignature   = NTH16_SIGNATURE;
-    ntb->nth.wHeaderLength = sizeof(ntb->nth);
-    ntb->nth.wSequence     = ncm_interface.xmit_sequence++;
-    ntb->nth.wBlockLength  = sizeof(ntb->nth) + sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
-    ntb->nth.wNdpIndex     = sizeof(ntb->nth);
+  xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
 
-    // Fill in NDP16 header and terminator
-    ntb->ndp.dwSignature   = NDP16_SIGNATURE_NCM0;
-    ntb->ndp.wLength       = sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
-    ntb->ndp.wNextNdpIndex = 0;
+  // Fill in NTB header
+  ntb->nth.dwSignature = NTH16_SIGNATURE;
+  ntb->nth.wHeaderLength = sizeof(ntb->nth);
+  ntb->nth.wSequence = ncm_interface.xmit_sequence++;
+  ntb->nth.wBlockLength = sizeof(ntb->nth) + sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+  ntb->nth.wNdpIndex = sizeof(ntb->nth);
 
-    memset(ntb->ndp_datagram, 0, sizeof(ntb->ndp_datagram));
-    return true;
-}   // xmit_setup_next_glue_ntb
+  // Fill in NDP16 header and terminator
+  ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
+  ntb->ndp.wLength = sizeof(ntb->ndp) + sizeof(ntb->ndp_datagram);
+  ntb->ndp.wNextNdpIndex = 0;
 
+  memset(ntb->ndp_datagram, 0, sizeof(ntb->ndp_datagram));
+  return true;
+} // xmit_setup_next_glue_ntb
 
 //-----------------------------------------------------------------------------
 //
 // all the recv_*() stuff (TinyUSB -> driver -> glue logic)
 //
 
-
-static recv_ntb_t *recv_get_free_ntb(void)
 /**
  * Return pointer to an available receive buffer or NULL.
  * Returned buffer (if any) has the size \a CFG_TUD_NCM_OUT_NTB_MAX_SIZE.
  */
-{
-    TU_LOG3("recv_get_free_ntb()\n");
-
-    for (int i = 0;  i < RECV_NTB_N;  ++i) {
-        if (ncm_interface.recv_free_ntb[i] != NULL) {
-            recv_ntb_t *free = ncm_interface.recv_free_ntb[i];
-            ncm_interface.recv_free_ntb[i] = NULL;
-            return free;
-        }
-    }
-    return NULL;
-}   // recv_get_free_ntb
-
+static recv_ntb_t *recv_get_free_ntb(void) {
+  TU_LOG_DRV("recv_get_free_ntb()\n");
 
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    if (ncm_interface.recv_free_ntb[i] != NULL) {
+      recv_ntb_t *free = ncm_interface.recv_free_ntb[i];
+      ncm_interface.recv_free_ntb[i] = NULL;
+      return free;
+    }
+  }
+  return NULL;
+} // recv_get_free_ntb
 
-static recv_ntb_t *recv_get_next_ready_ntb(void)
 /**
  * Get the next NTB from the ready list (and remove it from the list).
  * If the ready list is empty, return NULL.
  */
-{
-    recv_ntb_t *r = NULL;
+static recv_ntb_t *recv_get_next_ready_ntb(void) {
+  recv_ntb_t *r = NULL;
 
-    r = ncm_interface.recv_ready_ntb[0];
-    memmove(ncm_interface.recv_ready_ntb + 0, ncm_interface.recv_ready_ntb + 1, sizeof(ncm_interface.recv_ready_ntb) - sizeof(ncm_interface.recv_ready_ntb[0]));
-    ncm_interface.recv_ready_ntb[RECV_NTB_N - 1] = NULL;
+  r = ncm_interface.recv_ready_ntb[0];
+  memmove(ncm_interface.recv_ready_ntb + 0, ncm_interface.recv_ready_ntb + 1, sizeof(ncm_interface.recv_ready_ntb) - sizeof(ncm_interface.recv_ready_ntb[0]));
+  ncm_interface.recv_ready_ntb[RECV_NTB_N - 1] = NULL;
 
-    TU_LOG3("recv_get_next_ready_ntb: %p\n", r);
-    return r;
-}   // recv_get_next_ready_ntb
+  TU_LOG_DRV("recv_get_next_ready_ntb: %p\n", r);
+  return r;
+} // recv_get_next_ready_ntb
 
-
-
-static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb)
 /**
  * Put NTB into the receiver free list.
  */
-{
-    TU_LOG3("recv_put_ntb_into_free_list(%p)\n", free_ntb);
+static void recv_put_ntb_into_free_list(recv_ntb_t *free_ntb) {
+  TU_LOG_DRV("recv_put_ntb_into_free_list(%p)\n", free_ntb);
 
-    for (int i = 0;  i < RECV_NTB_N;  ++i) {
-        if (ncm_interface.recv_free_ntb[i] == NULL) {
-            ncm_interface.recv_free_ntb[i] = free_ntb;
-            return;
-        }
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    if (ncm_interface.recv_free_ntb[i] == NULL) {
+      ncm_interface.recv_free_ntb[i] = free_ntb;
+      return;
     }
-    TU_LOG1("(EE) recv_put_ntb_into_free_list - no entry in free list\n");  // this should not happen
-}   // recv_put_ntb_into_free_list
+  }
+  TU_LOG_DRV("(EE) recv_put_ntb_into_free_list - no entry in free list\n");// this should not happen
+} // recv_put_ntb_into_free_list
 
-
-
-static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb)
 /**
  * \a ready_ntb holds a validated NTB,
  * put this buffer into the waiting list.
  */
-{
-    TU_LOG3("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
+static void recv_put_ntb_into_ready_list(recv_ntb_t *ready_ntb) {
+  TU_LOG_DRV("recv_put_ntb_into_ready_list(%p) %d\n", ready_ntb, ready_ntb->nth.wBlockLength);
 
-    for (int i = 0;  i < RECV_NTB_N;  ++i) {
-        if (ncm_interface.recv_ready_ntb[i] == NULL) {
-            ncm_interface.recv_ready_ntb[i] = ready_ntb;
-            return;
-        }
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    if (ncm_interface.recv_ready_ntb[i] == NULL) {
+      ncm_interface.recv_ready_ntb[i] = ready_ntb;
+      return;
     }
-    TU_LOG1("(EE) recv_put_ntb_into_ready_list: ready list full\n");  // this should not happen
-}   // recv_put_ntb_into_ready_list
-
-
+  }
+  TU_LOG_DRV("(EE) recv_put_ntb_into_ready_list: ready list full\n");// this should not happen
+} // recv_put_ntb_into_ready_list
 
-static void recv_try_to_start_new_reception(uint8_t rhport)
 /**
  * If possible, start a new reception TinyUSB -> driver.
  */
-{
-    TU_LOG3("recv_try_to_start_new_reception(%d)\n", rhport);
-
-    if (ncm_interface.itf_data_alt != 1) {
-        return;
-    }
-    if (ncm_interface.recv_tinyusb_ntb != NULL) {
-        return;
-    }
-    if (usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
-        return;
-    }
-
-    ncm_interface.recv_tinyusb_ntb = recv_get_free_ntb();
-    if (ncm_interface.recv_tinyusb_ntb == NULL) {
-        return;
-    }
-
-    // initiate transfer
-    TU_LOG3("  start reception\n");
-    bool r = usbd_edpt_xfer(rhport, ncm_interface.ep_out, ncm_interface.recv_tinyusb_ntb->data, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
-    if ( !r) {
-        recv_put_ntb_into_free_list(ncm_interface.recv_tinyusb_ntb);
-        ncm_interface.recv_tinyusb_ntb = NULL;
-    }
-}   // recv_try_to_start_new_reception
-
-
+static void recv_try_to_start_new_reception(uint8_t rhport) {
+  TU_LOG_DRV("recv_try_to_start_new_reception(%d)\n", rhport);
+
+  if (ncm_interface.itf_data_alt != 1) {
+    return;
+  }
+  if (ncm_interface.recv_tinyusb_ntb != NULL) {
+    return;
+  }
+  if (usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
+    return;
+  }
+
+  ncm_interface.recv_tinyusb_ntb = recv_get_free_ntb();
+  if (ncm_interface.recv_tinyusb_ntb == NULL) {
+    return;
+  }
+
+  // initiate transfer
+  TU_LOG_DRV("  start reception\n");
+  bool r = usbd_edpt_xfer(rhport, ncm_interface.ep_out, ncm_interface.recv_tinyusb_ntb->data, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+  if (!r) {
+    recv_put_ntb_into_free_list(ncm_interface.recv_tinyusb_ntb);
+    ncm_interface.recv_tinyusb_ntb = NULL;
+  }
+} // recv_try_to_start_new_reception
 
-static bool recv_validate_datagram(const recv_ntb_t *ntb, uint32_t len)
 /**
  * Validate incoming datagram.
  * \return true if valid
@@ -555,287 +506,243 @@ static bool recv_validate_datagram(const recv_ntb_t *ntb, uint32_t len)
  * \note
  *    \a ndp16->wNextNdpIndex != 0 is not supported
  */
-{
-    const nth16_t *nth16 = &(ntb->nth);
-
-    TU_LOG3("recv_validate_datagram(%p, %d)\n", ntb, (int)len);
-
-    //
-    // check header
-    //
-    if (nth16->wHeaderLength != sizeof(nth16_t))
-    {
-        TU_LOG1("(EE) ill nth16 length: %d\n", nth16->wHeaderLength);
-        return false;
-    }
-    if (nth16->dwSignature != NTH16_SIGNATURE) {
-        TU_LOG1("(EE) ill signature: 0x%08x\n", (unsigned)nth16->dwSignature);
-        return false;
-    }
-    if (len < sizeof(nth16_t) + sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
-        TU_LOG1("(EE) ill min len: %d\n", len);
-        return false;
-    }
-    if (nth16->wBlockLength > len) {
-        TU_LOG1("(EE) ill block length: %d > %d\n", nth16->wBlockLength, len);
-        return false;
-    }
-    if (nth16->wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        TU_LOG1("(EE) ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
-        return false;
-    }
-    if (nth16->wNdpIndex < sizeof(nth16)  ||  nth16->wNdpIndex > len - (sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t))) {
-        TU_LOG1("(EE) ill position of first ndp: %d (%d)\n", nth16->wNdpIndex, len);
-        return false;
-    }
+static bool recv_validate_datagram(const recv_ntb_t *ntb, uint32_t len) {
+  const nth16_t *nth16 = &(ntb->nth);
 
-    //
-    // check (first) NDP(16)
-    //
-    const ndp16_t *ndp16 = (const ndp16_t *)(ntb->data + nth16->wNdpIndex);
+  TU_LOG_DRV("recv_validate_datagram(%p, %d)\n", ntb, (int) len);
 
-    if (ndp16->wLength < sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)) {
-        TU_LOG1("(EE) ill ndp16 length: %d\n", ndp16->wLength);
-        return false;
-    }
-    if (ndp16->dwSignature != NDP16_SIGNATURE_NCM0  &&  ndp16->dwSignature != NDP16_SIGNATURE_NCM1) {
-        TU_LOG1("(EE) ill signature: 0x%08x\n", (unsigned)ndp16->dwSignature);
-        return false;
-    }
-    if (ndp16->wNextNdpIndex != 0) {
-        TU_LOG1("(EE) cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
-        return false;
-    }
+  // check header
+  if (nth16->wHeaderLength != sizeof(nth16_t)) {
+    TU_LOG_DRV("(EE) ill nth16 length: %d\n", nth16->wHeaderLength);
+    return false;
+  }
+  if (nth16->dwSignature != NTH16_SIGNATURE) {
+    TU_LOG_DRV("(EE) ill signature: 0x%08x\n", (unsigned) nth16->dwSignature);
+    return false;
+  }
+  if (len < sizeof(nth16_t) + sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)) {
+    TU_LOG_DRV("(EE) ill min len: %d\n", len);
+    return false;
+  }
+  if (nth16->wBlockLength > len) {
+    TU_LOG_DRV("(EE) ill block length: %d > %d\n", nth16->wBlockLength, len);
+    return false;
+  }
+  if (nth16->wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+    TU_LOG_DRV("(EE) ill block length2: %d > %d\n", nth16->wBlockLength, CFG_TUD_NCM_OUT_NTB_MAX_SIZE);
+    return false;
+  }
+  if (nth16->wNdpIndex < sizeof(nth16) || nth16->wNdpIndex > len - (sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t))) {
+    TU_LOG_DRV("(EE) ill position of first ndp: %d (%d)\n", nth16->wNdpIndex, len);
+    return false;
+  }
 
-    const ndp16_datagram_t *ndp16_datagram = (const ndp16_datagram_t *)(ntb->data + nth16->wNdpIndex + sizeof(ndp16_t));
-    int ndx = 0;
-    uint16_t max_ndx = (uint16_t)((ndp16->wLength - sizeof(ndp16_t)) / sizeof(ndp16_datagram_t));
+  // check (first) NDP(16)
+  const ndp16_t *ndp16 = (const ndp16_t *) (ntb->data + nth16->wNdpIndex);
 
-    if (max_ndx > 2) {
-        // number of datagrams in NTB > 1
-        TU_LOG2("<< %d (%d)\n", max_ndx - 1, ntb->nth.wBlockLength);
-    }
-    if (ndp16_datagram[max_ndx-1].wDatagramIndex != 0  ||  ndp16_datagram[max_ndx-1].wDatagramLength != 0) {
-        TU_LOG2("  max_ndx != 0\n");
-        return false;
-    }
-    while (ndp16_datagram[ndx].wDatagramIndex != 0  &&  ndp16_datagram[ndx].wDatagramLength != 0) {
-        TU_LOG3("  << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
-        if (ndp16_datagram[ndx].wDatagramIndex > len) {
-            TU_LOG1("(EE) ill start of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
-            return false;
-        }
-        if (ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength > len) {
-            TU_LOG1("(EE) ill end of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
-            return false;
-        }
-        ++ndx;
-    }
+  if (ndp16->wLength < sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)) {
+    TU_LOG_DRV("(EE) ill ndp16 length: %d\n", ndp16->wLength);
+    return false;
+  }
+  if (ndp16->dwSignature != NDP16_SIGNATURE_NCM0 && ndp16->dwSignature != NDP16_SIGNATURE_NCM1) {
+    TU_LOG_DRV("(EE) ill signature: 0x%08x\n", (unsigned) ndp16->dwSignature);
+    return false;
+  }
+  if (ndp16->wNextNdpIndex != 0) {
+    TU_LOG_DRV("(EE) cannot handle wNextNdpIndex!=0 (%d)\n", ndp16->wNextNdpIndex);
+    return false;
+  }
 
-#if CFG_TUSB_DEBUG >= 3
-    for (uint32_t i = 0;  i < len;  ++i) {
-        TU_LOG3(" %02x", ntb->data[i]);
-    }
-    TU_LOG3("\n");
-#endif
+  const ndp16_datagram_t *ndp16_datagram = (const ndp16_datagram_t *) (ntb->data + nth16->wNdpIndex + sizeof(ndp16_t));
+  int ndx = 0;
+  uint16_t max_ndx = (uint16_t) ((ndp16->wLength - sizeof(ndp16_t)) / sizeof(ndp16_datagram_t));
 
-    // -> ntb contains a valid packet structure
-    //    ok... I did not check for garbage within the datagram indices...
-    return true;
-}   // recv_validate_datagram
+  if (max_ndx > 2) { // number of datagrams in NTB > 1
+    TU_LOG_DRV("<< %d (%d)\n", max_ndx - 1, ntb->nth.wBlockLength);
+  }
+  if (ndp16_datagram[max_ndx - 1].wDatagramIndex != 0 || ndp16_datagram[max_ndx - 1].wDatagramLength != 0) {
+    TU_LOG_DRV("  max_ndx != 0\n");
+    return false;
+  }
+  while (ndp16_datagram[ndx].wDatagramIndex != 0 && ndp16_datagram[ndx].wDatagramLength != 0) {
+    TU_LOG_DRV("  << %d %d\n", ndp16_datagram[ndx].wDatagramIndex, ndp16_datagram[ndx].wDatagramLength);
+    if (ndp16_datagram[ndx].wDatagramIndex > len) {
+      TU_LOG_DRV("(EE) ill start of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex, len);
+      return false;
+    }
+    if (ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength > len) {
+      TU_LOG_DRV("(EE) ill end of datagram[%d]: %d (%d)\n", ndx, ndp16_datagram[ndx].wDatagramIndex + ndp16_datagram[ndx].wDatagramLength, len);
+      return false;
+    }
+    ++ndx;
+  }
 
+  #if CFG_TUD_NCM_LOG_LEVEL >= 3
+  TU_LOG_BUF(3, ntb->data[i], len);
+  #endif
 
+  // -> ntb contains a valid packet structure
+  //    ok... I did not check for garbage within the datagram indices...
+  return true;
+} // recv_validate_datagram
 
-static void recv_transfer_datagram_to_glue_logic(void)
 /**
  * Transfer the next (pending) datagram to the glue logic and return receive buffer if empty.
  */
-{
-    TU_LOG3("recv_transfer_datagram_to_glue_logic()\n");
-
-    if (ncm_interface.recv_glue_ntb == NULL) {
-        ncm_interface.recv_glue_ntb = recv_get_next_ready_ntb();
-        TU_LOG3("  new buffer for glue logic: %p\n", ncm_interface.recv_glue_ntb);
-        ncm_interface.recv_glue_ntb_datagram_ndx = 0;
-    }
-
-    if (ncm_interface.recv_glue_ntb != NULL) {
-        const ndp16_datagram_t *ndp16_datagram = (ndp16_datagram_t *)(ncm_interface.recv_glue_ntb->data
-                                                                    + ncm_interface.recv_glue_ntb->nth.wNdpIndex
-                                                                    + sizeof(ndp16_t));
-
-        if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex == 0) {
-            TU_LOG1("(EE) SOMETHING WENT WRONG 1\n");
-        }
-        else if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength == 0) {
-            TU_LOG1("(EE) SOMETHING WENT WRONG 2\n");
-        }
-        else {
-            uint16_t datagramIndex  = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex;
-            uint16_t datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength;
-
-            TU_LOG3("  recv[%d] - %d %d\n", ncm_interface.recv_glue_ntb_datagram_ndx, datagramIndex, datagramLength);
-            if (tud_network_recv_cb(ncm_interface.recv_glue_ntb->data + datagramIndex, datagramLength)) {
-                //
-                // send datagram successfully to glue logic
-                //
-                TU_LOG3("    OK\n");
-                datagramIndex  = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramIndex;
-                datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramLength;
-
-                if (datagramIndex != 0  &&  datagramLength != 0) {
-                    // -> next datagram
-                    ++ncm_interface.recv_glue_ntb_datagram_ndx;
-                }
-                else {
-                    // end of datagrams reached
-                    recv_put_ntb_into_free_list(ncm_interface.recv_glue_ntb);
-                    ncm_interface.recv_glue_ntb = NULL;
-                }
-            }
+static void recv_transfer_datagram_to_glue_logic(void) {
+  TU_LOG_DRV("recv_transfer_datagram_to_glue_logic()\n");
+
+  if (ncm_interface.recv_glue_ntb == NULL) {
+    ncm_interface.recv_glue_ntb = recv_get_next_ready_ntb();
+    TU_LOG_DRV("  new buffer for glue logic: %p\n", ncm_interface.recv_glue_ntb);
+    ncm_interface.recv_glue_ntb_datagram_ndx = 0;
+  }
+
+  if (ncm_interface.recv_glue_ntb != NULL) {
+    const ndp16_datagram_t *ndp16_datagram = (ndp16_datagram_t *) (ncm_interface.recv_glue_ntb->data + ncm_interface.recv_glue_ntb->nth.wNdpIndex + sizeof(ndp16_t));
+
+    if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex == 0) {
+      TU_LOG_DRV("(EE) SOMETHING WENT WRONG 1\n");
+    } else if (ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength == 0) {
+      TU_LOG_DRV("(EE) SOMETHING WENT WRONG 2\n");
+    } else {
+      uint16_t datagramIndex = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramIndex;
+      uint16_t datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx].wDatagramLength;
+
+      TU_LOG_DRV("  recv[%d] - %d %d\n", ncm_interface.recv_glue_ntb_datagram_ndx, datagramIndex, datagramLength);
+      if (tud_network_recv_cb(ncm_interface.recv_glue_ntb->data + datagramIndex, datagramLength)) {
+        // send datagram successfully to glue logic
+        TU_LOG_DRV("    OK\n");
+        datagramIndex = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramIndex;
+        datagramLength = ndp16_datagram[ncm_interface.recv_glue_ntb_datagram_ndx + 1].wDatagramLength;
+
+        if (datagramIndex != 0 && datagramLength != 0) {
+          // -> next datagram
+          ++ncm_interface.recv_glue_ntb_datagram_ndx;
+        } else {
+          // end of datagrams reached
+          recv_put_ntb_into_free_list(ncm_interface.recv_glue_ntb);
+          ncm_interface.recv_glue_ntb = NULL;
         }
+      }
     }
-}   // recv_transfer_datagram_to_glue_logic
-
+  }
+} // recv_transfer_datagram_to_glue_logic
 
 //-----------------------------------------------------------------------------
 //
 // all the tud_network_*() stuff (glue logic -> driver)
 //
 
-
-bool tud_network_can_xmit(uint16_t size)
 /**
  * Check if the glue logic is allowed to call tud_network_xmit().
  * This function also fetches a next buffer if required, so that tud_network_xmit() is ready for copy
  * and transmission operation.
  */
-{
-    TU_LOG3("tud_network_can_xmit(%d)\n", size);
-
-    TU_ASSERT(size <= CFG_TUD_NCM_OUT_NTB_MAX_SIZE - (sizeof(nth16_t) + sizeof(ndp16_t) + 2*sizeof(ndp16_datagram_t)), false);
-
-    if (xmit_requested_datagram_fits_into_current_ntb(size)  ||  xmit_setup_next_glue_ntb()) {
-        // -> everything is fine
-        return true;
-    }
-    xmit_start_if_possible(ncm_interface.rhport);
-    TU_LOG2("(II) tud_network_can_xmit: request blocked\n");     // could happen if all xmit buffers are full (but should happen rarely)
-    return false;
-}   // tud_network_can_xmit
+bool tud_network_can_xmit(uint16_t size) {
+  TU_LOG_DRV("tud_network_can_xmit(%d)\n", size);
 
+  TU_ASSERT(size <= CFG_TUD_NCM_OUT_NTB_MAX_SIZE - (sizeof(nth16_t) + sizeof(ndp16_t) + 2 * sizeof(ndp16_datagram_t)), false);
 
+  if (xmit_requested_datagram_fits_into_current_ntb(size) || xmit_setup_next_glue_ntb()) {
+    // -> everything is fine
+    return true;
+  }
+  xmit_start_if_possible(ncm_interface.rhport);
+  TU_LOG_DRV("(II) tud_network_can_xmit: request blocked\n");// could happen if all xmit buffers are full (but should happen rarely)
+  return false;
+} // tud_network_can_xmit
 
-void tud_network_xmit(void *ref, uint16_t arg)
 /**
  * Put a datagram into a waiting NTB.
  * If currently no transmission is started, then initiate transmission.
  */
-{
-    TU_LOG3("tud_network_xmit(%p, %d)\n", ref, arg);
-
-    if (ncm_interface.xmit_glue_ntb == NULL) {
-        TU_LOG1("(EE) tud_network_xmit: no buffer\n");             // must not happen (really)
-        return;
-    }
-
-    xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
+void tud_network_xmit(void *ref, uint16_t arg) {
+  TU_LOG_DRV("tud_network_xmit(%p, %d)\n", ref, arg);
 
-    // copy new datagram to the end of the current NTB
-    uint16_t size = tud_network_xmit_cb(ntb->data + ntb->nth.wBlockLength, ref, arg);
+  if (ncm_interface.xmit_glue_ntb == NULL) {
+    TU_LOG_DRV("(EE) tud_network_xmit: no buffer\n");// must not happen (really)
+    return;
+  }
 
-    // correct NTB internals
-    ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramIndex  = ntb->nth.wBlockLength;
-    ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramLength = size;
-    ncm_interface.xmit_glue_ntb_datagram_ndx += 1;
+  xmit_ntb_t *ntb = ncm_interface.xmit_glue_ntb;
 
-    ntb->nth.wBlockLength += (uint16_t)(size + XMIT_ALIGN_OFFSET(size));
+  // copy new datagram to the end of the current NTB
+  uint16_t size = tud_network_xmit_cb(ntb->data + ntb->nth.wBlockLength, ref, arg);
 
-    if (ntb->nth.wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
-        TU_LOG1("(EE) tud_network_xmit: buffer overflow\n");       // must not happen (really)
-        return;
-    }
+  // correct NTB internals
+  ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramIndex = ntb->nth.wBlockLength;
+  ntb->ndp_datagram[ncm_interface.xmit_glue_ntb_datagram_ndx].wDatagramLength = size;
+  ncm_interface.xmit_glue_ntb_datagram_ndx += 1;
 
-    xmit_start_if_possible(ncm_interface.rhport);
-}   // tud_network_xmit
+  ntb->nth.wBlockLength += (uint16_t) (size + XMIT_ALIGN_OFFSET(size));
 
+  if (ntb->nth.wBlockLength > CFG_TUD_NCM_OUT_NTB_MAX_SIZE) {
+    TU_LOG_DRV("(EE) tud_network_xmit: buffer overflow\n"); // must not happen (really)
+    return;
+  }
 
+  xmit_start_if_possible(ncm_interface.rhport);
+} // tud_network_xmit
 
-void tud_network_recv_renew(void)
 /**
  * Keep the receive logic busy and transfer pending packets to the glue logic.
  */
-{
-    TU_LOG3("tud_network_recv_renew()\n");
+void tud_network_recv_renew(void) {
+  TU_LOG_DRV("tud_network_recv_renew()\n");
 
-    recv_transfer_datagram_to_glue_logic();
-    recv_try_to_start_new_reception(ncm_interface.rhport);
-}   // tud_network_recv_renew
+  recv_transfer_datagram_to_glue_logic();
+  recv_try_to_start_new_reception(ncm_interface.rhport);
+} // tud_network_recv_renew
 
-
-
-void tud_network_recv_renew_r(uint8_t rhport)
 /**
  * Same as tud_network_recv_renew() but knows \a rhport
  */
-{
-    TU_LOG3("tud_network_recv_renew_r(%d)\n", rhport);
-
-    ncm_interface.rhport = rhport;
-    tud_network_recv_renew();
-}   // tud_network_recv_renew
+void tud_network_recv_renew_r(uint8_t rhport) {
+  TU_LOG_DRV("tud_network_recv_renew_r(%d)\n", rhport);
 
+  ncm_interface.rhport = rhport;
+  tud_network_recv_renew();
+} // tud_network_recv_renew
 
 //-----------------------------------------------------------------------------
 //
 // all the netd_*() stuff (interface TinyUSB -> driver)
 //
-void netd_init(void)
 /**
  * Initialize the driver data structures.
  * Might be called several times.
  */
-{
-    TU_LOG3("netd_init()\n");
+void netd_init(void) {
+  TU_LOG_DRV("netd_init()\n");
 
-    memset( &ncm_interface, 0, sizeof(ncm_interface));
-
-    for (int i = 0;  i < XMIT_NTB_N;  ++i) {
-        ncm_interface.xmit_free_ntb[i] = ncm_interface.xmit_ntb + i;
-    }
-    for (int i = 0;  i < RECV_NTB_N;  ++i) {
-        ncm_interface.recv_free_ntb[i] = ncm_interface.recv_ntb + i;
-    }
-}   // netd_init
+  memset(&ncm_interface, 0, sizeof(ncm_interface));
 
+  for (int i = 0; i < XMIT_NTB_N; ++i) {
+    ncm_interface.xmit_free_ntb[i] = ncm_interface.xmit_ntb + i;
+  }
+  for (int i = 0; i < RECV_NTB_N; ++i) {
+    ncm_interface.recv_free_ntb[i] = ncm_interface.recv_ntb + i;
+  }
+} // netd_init
 
-
-bool netd_deinit(void)
 /**
  * Deinit driver
  */
-{
-    return true;
+bool netd_deinit(void) {
+  return true;
 }
 
-
-
-void netd_reset(uint8_t rhport)
 /**
  * Resets the port.
  * In this driver this is the same as netd_init()
  */
-{
-    (void)rhport;
-
-    TU_LOG3("netd_reset(%d)\n", rhport);
+void netd_reset(uint8_t rhport) {
+  (void) rhport;
 
-    netd_init();
-}   // netd_reset
+  netd_init();
+} // netd_reset
 
-
-
-uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 /**
  * Open the USB interface.
  * - parse the USB descriptor \a TUD_CDC_NCM_DESCRIPTOR for itfnum and endpoints
@@ -850,174 +757,137 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16
  * - \a ep_notif, \a ep_in and \a ep_out are set
  * - USB interface is open
  */
-{
-    TU_LOG3("netd_open(%d,%p,%d)\n", rhport, itf_desc, max_len);
-
-    TU_ASSERT(ncm_interface.ep_notif == 0, 0);           // assure that the interface is only opened once
+uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  TU_ASSERT(ncm_interface.ep_notif == 0, 0);// assure that the interface is only opened once
 
-    ncm_interface.itf_num = itf_desc->bInterfaceNumber;  // management interface
+  ncm_interface.itf_num = itf_desc->bInterfaceNumber;// management interface
 
-    //
-    // skip the two first entries and the following TUSB_DESC_CS_INTERFACE entries
-    //
-    uint16_t drv_len = sizeof(tusb_desc_interface_t);
-    uint8_t const *p_desc = tu_desc_next(itf_desc);
-    while (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE  &&  drv_len <= max_len) {
-        drv_len += tu_desc_len(p_desc);
-        p_desc = tu_desc_next(p_desc);
-    }
-
-    //
-    // get notification endpoint
-    //
-    TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
-    TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const* ) p_desc), 0);
-    ncm_interface.ep_notif = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
+  // skip the two first entries and the following TUSB_DESC_CS_INTERFACE entries
+  uint16_t drv_len = sizeof(tusb_desc_interface_t);
+  uint8_t const *p_desc = tu_desc_next(itf_desc);
+  while (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && drv_len <= max_len) {
     drv_len += tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
+  }
 
-    //
-    // skip the following TUSB_DESC_INTERFACE entries (which must be TUSB_CLASS_CDC_DATA)
-    //
-    while (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE  &&  drv_len <= max_len) {
-        tusb_desc_interface_t const *data_itf_desc = (tusb_desc_interface_t const*)p_desc;
-        TU_ASSERT(data_itf_desc->bInterfaceClass == TUSB_CLASS_CDC_DATA, 0);
+  // get notification endpoint
+  TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+  TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0);
+  ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+  drv_len += tu_desc_len(p_desc);
+  p_desc = tu_desc_next(p_desc);
 
-        drv_len += tu_desc_len(p_desc);
-        p_desc = tu_desc_next(p_desc);
-    }
+  // skip the following TUSB_DESC_INTERFACE entries (which must be TUSB_CLASS_CDC_DATA)
+  while (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && drv_len <= max_len) {
+    tusb_desc_interface_t const *data_itf_desc = (tusb_desc_interface_t const *) p_desc;
+    TU_ASSERT(data_itf_desc->bInterfaceClass == TUSB_CLASS_CDC_DATA, 0);
 
-    //
-    // a TUSB_DESC_ENDPOINT (actually two) must follow, open these endpoints
-    //
-    TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
-    TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in));
-    drv_len += 2 * sizeof(tusb_desc_endpoint_t);
-
-    return drv_len;
-}   // netd_open
+    drv_len += tu_desc_len(p_desc);
+    p_desc = tu_desc_next(p_desc);
+  }
 
+  // a TUSB_DESC_ENDPOINT (actually two) must follow, open these endpoints
+  TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT, 0);
+  TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in));
+  drv_len += 2 * sizeof(tusb_desc_endpoint_t);
 
+  return drv_len;
+} // netd_open
 
-bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 /**
  * Handle TinyUSB requests to process transfer events.
  */
-{
-    (void)result;
-
-    TU_LOG3("netd_xfer_cb(%d,%d,%d,%u)\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
-
-    if (ep_addr == ncm_interface.ep_out) {
-        //
-        // new NTB received
-        // - make the NTB valid
-        // - if ready transfer datagrams to the glue logic for further processing
-        // - if there is a free receive buffer, initiate reception
-        //
-        TU_LOG3("  EP_OUT %d %d %d %u\n", rhport, ep_addr, result, (unsigned)xferred_bytes);
-        if ( !recv_validate_datagram( ncm_interface.recv_tinyusb_ntb, xferred_bytes)) {
-            // verification failed: ignore NTB and return it to free
-            TU_LOG1("(EE) VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
-        }
-        else {
-            // packet ok -> put it into ready list
-            recv_put_ntb_into_ready_list(ncm_interface.recv_tinyusb_ntb);
-        }
-        ncm_interface.recv_tinyusb_ntb = NULL;
-        tud_network_recv_renew_r(rhport);
-    }
-    else if (ep_addr == ncm_interface.ep_in) {
-        //
-        // transmission of an NTB finished
-        // - free the transmitted NTB buffer
-        // - insert ZLPs when necessary
-        // - if there is another transmit NTB waiting, try to start transmission
-        //
-        TU_LOG3("  EP_IN %d %u\n", ncm_interface.itf_data_alt, (unsigned)xferred_bytes);
-        xmit_put_ntb_into_free_list(ncm_interface.xmit_tinyusb_ntb);
-        ncm_interface.xmit_tinyusb_ntb = NULL;
-        if ( !xmit_insert_required_zlp(rhport, xferred_bytes)) {
-            xmit_start_if_possible(rhport);
-        }
-    }
-    else if (ep_addr == ncm_interface.ep_notif) {
-        //
-        // next transfer on notification channel
-        //
-        TU_LOG3("  EP_NOTIF\n");
-        notification_xmit(rhport, true);
-    }
-
-    return true;
-}   // netd_xfer_cb
-
-
+bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
+  (void) result;
+
+  if (ep_addr == ncm_interface.ep_out) {
+    // new NTB received
+    // - make the NTB valid
+    // - if ready transfer datagrams to the glue logic for further processing
+    // - if there is a free receive buffer, initiate reception
+    if (!recv_validate_datagram(ncm_interface.recv_tinyusb_ntb, xferred_bytes)) {
+      // verification failed: ignore NTB and return it to free
+      TU_LOG_DRV("(EE) VALIDATION FAILED. WHAT CAN WE DO IN THIS CASE?\n");
+    } else {
+      // packet ok -> put it into ready list
+      recv_put_ntb_into_ready_list(ncm_interface.recv_tinyusb_ntb);
+    }
+    ncm_interface.recv_tinyusb_ntb = NULL;
+    tud_network_recv_renew_r(rhport);
+  } else if (ep_addr == ncm_interface.ep_in) {
+    // transmission of an NTB finished
+    // - free the transmitted NTB buffer
+    // - insert ZLPs when necessary
+    // - if there is another transmit NTB waiting, try to start transmission
+    xmit_put_ntb_into_free_list(ncm_interface.xmit_tinyusb_ntb);
+    ncm_interface.xmit_tinyusb_ntb = NULL;
+    if (!xmit_insert_required_zlp(rhport, xferred_bytes)) {
+      xmit_start_if_possible(rhport);
+    }
+  } else if (ep_addr == ncm_interface.ep_notif) {
+    // next transfer on notification channel
+    notification_xmit(rhport, true);
+  }
+
+  return true;
+} // netd_xfer_cb
 
-bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request)
 /**
  * Respond to TinyUSB control requests.
  * At startup transmission of notification packets are done here.
  */
-{
-    TU_LOG3("netd_control_xfer_cb(%d, %d, %p)\n", rhport, stage, request);
+bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
+  if (stage != CONTROL_STAGE_SETUP) {
+    return true;
+  }
 
-    if (stage != CONTROL_STAGE_SETUP) {
-        return true;
-    }
+  switch (request->bmRequestType_bit.type) {
+    case TUSB_REQ_TYPE_STANDARD:
 
-    switch (request->bmRequestType_bit.type) {
-        case TUSB_REQ_TYPE_STANDARD:
-            TU_LOG3("  TUSB_REQ_TYPE_STANDARD: %d\n", request->bRequest);
-
-            switch (request->bRequest) {
-                case TUSB_REQ_GET_INTERFACE: {
-                    TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
-
-                    TU_LOG3("    TUSB_REQ_GET_INTERFACE - %d\n", ncm_interface.itf_data_alt);
-                    tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
-                }
-                break;
-
-                case TUSB_REQ_SET_INTERFACE: {
-                    TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex  &&  request->wValue < 2, false);
-
-                    ncm_interface.itf_data_alt = (uint8_t)request->wValue;
-                    TU_LOG3("    TUSB_REQ_SET_INTERFACE - %d %d %d\n", ncm_interface.itf_data_alt, request->wIndex, ncm_interface.itf_num);
-
-                    if (ncm_interface.itf_data_alt == 1) {
-                        tud_network_recv_renew_r(rhport);
-                        notification_xmit(rhport, false);
-                    }
-                    tud_control_status(rhport, request);
-                }
-                break;
-
-                // unsupported request
-                default:
-                    return false;
-            }
-            break;
-
-        case TUSB_REQ_TYPE_CLASS:
-            TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
-
-            TU_LOG3("  TUSB_REQ_TYPE_CLASS: %d\n", request->bRequest);
-
-            if (request->bRequest == NCM_GET_NTB_PARAMETERS) {
-                // transfer NTB parameters to host.
-                // TODO can one assume, that tud_control_xfer() succeeds?
-                TU_LOG3("    NCM_GET_NTB_PARAMETERS\n");
-                tud_control_xfer(rhport, request, (void*) (uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
-            }
-            break;
-
-            // unsupported request
-        default:
-            return false ;
-    }
+      switch (request->bRequest) {
+        case TUSB_REQ_GET_INTERFACE: {
+          TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex, false);
 
-    return true;
-}   // netd_control_xfer_cb
+          tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
+        } break;
 
-#endif   // ECLIPSE_GUI || ( CFG_TUD_ENABLED && CFG_TUD_NCM )
+        case TUSB_REQ_SET_INTERFACE: {
+          TU_VERIFY(ncm_interface.itf_num + 1 == request->wIndex && request->wValue < 2, false);
+
+          ncm_interface.itf_data_alt = (uint8_t) request->wValue;
+
+          if (ncm_interface.itf_data_alt == 1) {
+            tud_network_recv_renew_r(rhport);
+            notification_xmit(rhport, false);
+          }
+          tud_control_status(rhport, request);
+        } break;
+
+        // unsupported request
+        default:
+          return false;
+      }
+      break;
+
+    case TUSB_REQ_TYPE_CLASS:
+      TU_VERIFY(ncm_interface.itf_num == request->wIndex, false);
+      switch (request->bRequest) {
+        case NCM_GET_NTB_PARAMETERS: {
+          // transfer NTB parameters to host.
+          tud_control_xfer(rhport, request, (void *) (uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
+        } break;
+
+          // unsupported request
+        default:
+          return false;
+      }
+      break;
+      // unsupported request
+    default:
+      return false;
+  }
+
+  return true;
+} // netd_control_xfer_cb
+
+#endif // ( CFG_TUD_ENABLED && CFG_TUD_NCM )
-- 
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