From 6d1ed1ed8658ef20f72c52666d68d88024265e9f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Wed, 22 Jan 2025 22:35:49 +0100 Subject: Update deps. Signed-off-by: HiFiPhile --- tools/get_deps.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index c8459c1f1..0b49dfd72 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -103,6 +103,9 @@ deps_optional = { 'hw/mcu/st/cmsis_device_h7': ['https://github.com/STMicroelectronics/cmsis_device_h7.git', '60dc2c913203dc8629dc233d4384dcc41c91e77f', 'stm32h7'], + 'hw/mcu/st/cmsis_device_h7rs': ['https://github.com/STMicroelectronics/cmsis_device_h7rs.git', + '832649d1fd09bd901e9f68e979522e5c209ebf20', + 'stm32h7rs'], 'hw/mcu/st/cmsis_device_h5': ['https://github.com/STMicroelectronics/cmsis_device_h5.git', 'cd2d1d579743de57b88ccaf61a968b9c05848ffc', 'stm32h5'], @@ -157,6 +160,9 @@ deps_optional = { 'hw/mcu/st/stm32h7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git', 'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04', 'stm32h7'], + 'hw/mcu/st/stm32h7rsxx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7rsxx-hal-driver.git', + '7ca2e07ca21bc66b53654e845b4c85c884343b60', + 'stm32h7rs'], 'hw/mcu/st/stm32h5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git', '2cf77de584196d619cec1b4586c3b9e2820a254e', 'stm32h5'], @@ -198,7 +204,7 @@ deps_optional = { 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' - 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb ' + 'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb ' 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg ' 'tm4c '], 'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git', -- cgit v1.3.1 From e0df20f260a6c5d5e347427e9e57e73f9327f8d0 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Mon, 17 Mar 2025 12:20:49 +0700 Subject: change pio-usb to upstream --- tools/get_deps.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index b82abac4f..3f529bd7e 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -58,8 +58,8 @@ deps_optional = { 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', '144f1eb7ea8c06512e12f12b27383601c0272410', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], - 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', - '9c8df3083b62c0a678f3bd3d8a7e773932622d4b', + 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', + '0ca3657d55ea20e7fa4483bbd21ce951bc1d6fa5', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', -- cgit v1.3.1 From 65e01fff2e7ab5302baa45bdd81a1d774e269452 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 25 Mar 2025 16:15:58 +0700 Subject: add tuh_edpt_close() API, it will abort any pending transfer implement hcd_edpt_close() for pio-usb and max3421e, also move max3421e api into its own header. --- examples/host/bare_api/src/main.c | 254 +++++++++++-------------- src/host/hcd.h | 3 + src/host/usbh.c | 6 + src/host/usbh.h | 7 + src/portable/analog/max3421/hcd_max3421.c | 40 ++-- src/portable/analog/max3421/hcd_max3421.h | 63 ++++++ src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 5 + tools/get_deps.py | 4 +- 8 files changed, 218 insertions(+), 164 deletions(-) create mode 100644 src/portable/analog/max3421/hcd_max3421.h (limited to 'tools') diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index f582f4f5a..0c76ff0c9 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -55,16 +55,15 @@ uint8_t* get_hid_buf(uint8_t daddr); void free_hid_buf(uint8_t daddr); /*------------- MAIN -------------*/ -int main(void) -{ +int main(void) { board_init(); printf("TinyUSB Bare API Example\r\n"); // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .role = TUSB_ROLE_HOST, - .speed = TUSB_SPEED_AUTO + .role = TUSB_ROLE_HOST, + .speed = TUSB_SPEED_AUTO }; tusb_init(BOARD_TUH_RHPORT, &host_init); @@ -72,8 +71,7 @@ int main(void) board_init_after_tusb(); } - while (1) - { + while (1) { // tinyusb host task tuh_task(); led_blinking_task(); @@ -85,8 +83,7 @@ int main(void) /*------------- TinyUSB Callbacks -------------*/ // Invoked when device is mounted (configured) -void tuh_mount_cb (uint8_t daddr) -{ +void tuh_mount_cb(uint8_t daddr) { printf("Device attached, address = %d\r\n", daddr); // Get Device Descriptor @@ -95,8 +92,7 @@ void tuh_mount_cb (uint8_t daddr) } /// Invoked when device is unmounted (bus reset/unplugged) -void tuh_umount_cb(uint8_t daddr) -{ +void tuh_umount_cb(uint8_t daddr) { printf("Device removed, address = %d\r\n", daddr); free_hid_buf(daddr); } @@ -104,11 +100,8 @@ void tuh_umount_cb(uint8_t daddr) //--------------------------------------------------------------------+ // Device Descriptor //--------------------------------------------------------------------+ - -void print_device_descriptor(tuh_xfer_t* xfer) -{ - if ( XFER_RESULT_SUCCESS != xfer->result ) - { +void print_device_descriptor(tuh_xfer_t *xfer) { + if (XFER_RESULT_SUCCESS != xfer->result) { printf("Failed to get device descriptor\r\n"); return; } @@ -131,33 +124,29 @@ void print_device_descriptor(tuh_xfer_t* xfer) // Get String descriptor using Sync API uint16_t temp_buf[128]; - printf(" iManufacturer %u " , desc_device.iManufacturer); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)) ) - { + printf(" iManufacturer %u ", desc_device.iManufacturer); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" iProduct %u " , desc_device.iProduct); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) - { + printf(" iProduct %u ", desc_device.iProduct); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" iSerialNumber %u " , desc_device.iSerialNumber); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) - { + printf(" iSerialNumber %u ", desc_device.iSerialNumber); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" bNumConfigurations %u\r\n" , desc_device.bNumConfigurations); + printf(" bNumConfigurations %u\r\n", desc_device.bNumConfigurations); // Get configuration descriptor with sync API - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf))) - { - parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf))) { + parse_config_descriptor(daddr, (tusb_desc_configuration_t *) temp_buf); } } @@ -171,37 +160,33 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len); // simple configuration parser to open and listen to HID Endpoint IN -void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) -{ - uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); - uint8_t const* p_desc = tu_desc_next(desc_cfg); +void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const *desc_cfg) { + uint8_t const *desc_end = ((uint8_t const *) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); + uint8_t const *p_desc = tu_desc_next(desc_cfg); // parse each interfaces - while( p_desc < desc_end ) - { + while (p_desc < desc_end) { uint8_t assoc_itf_count = 1; // Class will always starts with Interface Association (if any) and then Interface descriptor - if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) - { - tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; + if (TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc)) { + tusb_desc_interface_assoc_t const *desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; assoc_itf_count = desc_iad->bInterfaceCount; - p_desc = tu_desc_next(p_desc); // next to Interface + p_desc = tu_desc_next(p_desc);// next to Interface } // must be interface from now - if( TUSB_DESC_INTERFACE != tu_desc_type(p_desc) ) return; - tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc; + if (TUSB_DESC_INTERFACE != tu_desc_type(p_desc)) { return; } + tusb_desc_interface_t const *desc_itf = (tusb_desc_interface_t const *) p_desc; - uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc)); + uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end - p_desc)); // probably corrupted descriptor - if(drv_len < sizeof(tusb_desc_interface_t)) return; + if (drv_len < sizeof(tusb_desc_interface_t)) { return; } // only open and listen to HID endpoint IN - if (desc_itf->bInterfaceClass == TUSB_CLASS_HID) - { + if (desc_itf->bInterfaceClass == TUSB_CLASS_HID) { open_hid_interface(dev_addr, desc_itf, drv_len); } @@ -210,25 +195,21 @@ void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* } } -uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) -{ - uint8_t const* p_desc = (uint8_t const*) desc_itf; +uint16_t count_interface_total_len(tusb_desc_interface_t const *desc_itf, uint8_t itf_count, uint16_t max_len) { + uint8_t const *p_desc = (uint8_t const *) desc_itf; uint16_t len = 0; - while (itf_count--) - { + while (itf_count--) { // Next on interface desc len += tu_desc_len(desc_itf); p_desc = tu_desc_next(p_desc); - while (len < max_len) - { + while (len < max_len) { // return on IAD regardless of itf count - if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len; + if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) { return len; } - if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && - ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) - { + if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && + ((tusb_desc_interface_t const *) p_desc)->bAlternateSetting == 0) { break; } @@ -246,46 +227,45 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_ void hid_report_received(tuh_xfer_t* xfer); -void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) -{ +void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) { // len = interface + hid + n*endpoints uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t)); // corrupted descriptor - if (max_len < drv_len) return; + if (max_len < drv_len) { return; } uint8_t const *p_desc = (uint8_t const *) desc_itf; // HID descriptor p_desc = tu_desc_next(p_desc); tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc; - if(HID_DESC_TYPE_HID != desc_hid->bDescriptorType) return; + if (HID_DESC_TYPE_HID != desc_hid->bDescriptorType) { return; } // Endpoint descriptor p_desc = tu_desc_next(p_desc); - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; - - for(int i = 0; i < desc_itf->bNumEndpoints; i++) - { - if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) return; - - if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) - { - // skip if failed to open endpoint - if ( ! tuh_edpt_open(daddr, desc_ep) ) return; - - uint8_t* buf = get_hid_buf(daddr); - if (!buf) return; // out of memory - - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = desc_ep->bEndpointAddress, - .buflen = 64, - .buffer = buf, - .complete_cb = hid_report_received, - .user_data = (uintptr_t) buf, // since buffer is not available in callback, use user data to store the buffer + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; + + for (int i = 0; i < desc_itf->bNumEndpoints; i++) { + if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) { return; } + + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { + if (!tuh_edpt_open(daddr, desc_ep)) { + return; // skip if failed to open endpoint + } + + uint8_t *buf = get_hid_buf(daddr); + if (!buf) { + return;// out of memory + } + + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = desc_ep->bEndpointAddress, + .buflen = 64, + .buffer = buf, + .complete_cb = hid_report_received, + .user_data = (uintptr_t) buf,// since buffer is not available in callback, use user data to store the buffer }; // submit transfer for this EP @@ -299,18 +279,17 @@ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, ui } } -void hid_report_received(tuh_xfer_t* xfer) -{ +void hid_report_received(tuh_xfer_t *xfer) { // Note: not all field in xfer is available for use (i.e filled by tinyusb stack) in callback to save sram // For instance, xfer->buffer is NULL. We have used user_data to store buffer when submitted callback - uint8_t* buf = (uint8_t*) xfer->user_data; + uint8_t *buf = (uint8_t *) xfer->user_data; - if (xfer->result == XFER_RESULT_SUCCESS) - { + if (xfer->result == XFER_RESULT_SUCCESS) { printf("[dev %u: ep %02x] HID Report:", xfer->daddr, xfer->ep_addr); - for(uint32_t i=0; iactual_len; i++) - { - if (i%16 == 0) printf("\r\n "); + for (uint32_t i = 0; i < xfer->actual_len; i++) { + if (i % 16 == 0) { + printf("\r\n "); + } printf("%02X ", buf[i]); } printf("\r\n"); @@ -329,12 +308,9 @@ void hid_report_received(tuh_xfer_t* xfer) //--------------------------------------------------------------------+ // get an buffer from pool -uint8_t* get_hid_buf(uint8_t daddr) -{ - for(size_t i=0; i> 6 & 0x1F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F)); - } else { - // TODO: Verify surrogate. - *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F)); - } - // TODO: Handle UTF-16 code points that take two entries. + // TODO: Check for runover. + (void) utf8_len; + // Get the UTF-16 length out of the data itself. + + for (size_t i = 0; i < utf16_len; i++) { + uint16_t chr = utf16[i]; + if (chr < 0x80) { + *utf8++ = chr & 0xffu; + } else if (chr < 0x800) { + *utf8++ = (uint8_t) (0xC0 | (chr >> 6 & 0x1F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F)); + } else { + // TODO: Verify surrogate. + *utf8++ = (uint8_t) (0xE0 | (chr >> 12 & 0x0F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 6 & 0x3F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F)); } + // TODO: Handle UTF-16 code points that take two entries. + } } // Count how many bytes a utf-16-le encoded string will take in utf-8. static int _count_utf8_bytes(const uint16_t *buf, size_t len) { - size_t total_bytes = 0; - for (size_t i = 0; i < len; i++) { - uint16_t chr = buf[i]; - if (chr < 0x80) { - total_bytes += 1; - } else if (chr < 0x800) { - total_bytes += 2; - } else { - total_bytes += 3; - } - // TODO: Handle UTF-16 code points that take two entries. + size_t total_bytes = 0; + for (size_t i = 0; i < len; i++) { + uint16_t chr = buf[i]; + if (chr < 0x80) { + total_bytes += 1; + } else if (chr < 0x800) { + total_bytes += 2; + } else { + total_bytes += 3; } - return (int) total_bytes; + // TODO: Handle UTF-16 code points that take two entries. + } + return (int) total_bytes; } static void print_utf16(uint16_t *temp_buf, size_t buf_len) { - if ((temp_buf[0] & 0xff) == 0) return; // empty - size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); - size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); - _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); - ((uint8_t*) temp_buf)[utf8_len] = '\0'; + if ((temp_buf[0] & 0xff) == 0) return;// empty + size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); + size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); + _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); + ((uint8_t *) temp_buf)[utf8_len] = '\0'; - printf("%s", (char*)temp_buf); + printf("%s", (char *) temp_buf); } diff --git a/src/host/hcd.h b/src/host/hcd.h index 56b6fdb5d..aa9e9cf3b 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -165,6 +165,9 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr); // Open an endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc); +// Close an endpoint +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr); + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); diff --git a/src/host/usbh.c b/src/host/usbh.c index 308916c9b..5925a7be0 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -994,6 +994,12 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) { return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep); } +bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr) { + TU_VERIFY(0 != tu_edpt_number(ep_addr)); // cannot close EP0 + tuh_edpt_abort_xfer(daddr, ep_addr); // abort any pending transfer + return hcd_edpt_close(usbh_get_rhport(daddr), daddr, ep_addr); +} + bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { usbh_device_t* dev = get_device(dev_addr); TU_VERIFY(dev); diff --git a/src/host/usbh.h b/src/host/usbh.h index d95bb9b57..4829a8183 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -33,6 +33,10 @@ #include "common/tusb_common.h" +#if CFG_TUH_MAX3421 +#include "portable/analog/max3421/hcd_max3421.h" +#endif + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -227,6 +231,9 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer); // Open a non-control endpoint bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep); +// Close a non-control endpoint, it will abort any pending transfer +bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr); + // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index c5e924266..3fbf950a4 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -252,28 +252,6 @@ static tuh_configure_max3421_t _tuh_cfg = { .pinctl = 0, // default: negative edge interrupt }; -//--------------------------------------------------------------------+ -// API: SPI transfer with MAX3421E -// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application -// - reg_read(), reg_write(): is implemented by this driver, can be used by application -//--------------------------------------------------------------------+ - -// API to control MAX3421 SPI CS -extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); - -// API to transfer data with MAX3421 SPI -// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only -extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes); - -// API to enable/disable MAX3421 INTR pin interrupt -extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); - -// API to read MAX3421's register. Implemented by TinyUSB -uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); - -// API to write MAX3421's register. Implemented by TinyUSB -bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); - //--------------------------------------------------------------------+ // SPI Commands and Helper //--------------------------------------------------------------------+ @@ -632,6 +610,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e if (daddr == 0 && ep_num == 0) { ep = &_hcd_data.ep[0]; }else { + if (NULL != find_ep_not_addr0(daddr, ep_num, ep_dir)) { + return false; // endpoint already opened + } ep = allocate_ep(); TU_ASSERT(ep); ep->daddr = daddr; @@ -645,6 +626,21 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; + uint8_t const ep_num = tu_edpt_number(ep_addr); + tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr); + max3421_ep_t * ep = find_ep_not_addr0(daddr, ep_num, ep_dir); + + if (!ep) { + return false; // not opened + } + + tu_memclr(ep, sizeof(max3421_ep_t)); + + return true; +} + /* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes. * Then the microcontroller writes the SNDBC register, which this does three things: * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send. diff --git a/src/portable/analog/max3421/hcd_max3421.h b/src/portable/analog/max3421/hcd_max3421.h new file mode 100644 index 000000000..4631fa21a --- /dev/null +++ b/src/portable/analog/max3421/hcd_max3421.h @@ -0,0 +1,63 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef TUSB_HCD_MAX3421_H +#define TUSB_HCD_MAX3421_H + +#ifdef __cplusplus + extern "C" { +#endif + +//--------------------------------------------------------------------+ +// SPI transfer API with MAX3421E are implemented by application +// - spi_cs_api(), spi_xfer_api(), int_api() +//--------------------------------------------------------------------+ + +// API to control MAX3421 SPI CS +extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); + +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes); + +// API to enable/disable MAX3421 INTR pin interrupt +extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); + +//--------------------------------------------------------------------+ +// API for read/write MAX3421 registers +// are implemented by this driver, can be used by application +//--------------------------------------------------------------------+ + +// API to read MAX3421's register. Implemented by TinyUSB +uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); + +// API to write MAX3421's register. Implemented by TinyUSB +bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 6422afff1..225a44dcf 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -122,6 +122,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre); } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + uint8_t const pio_rhport = RHPORT_PIO(rhport); + return pio_usb_host_endpoint_close(pio_rhport, daddr, ep_addr); +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { uint8_t const pio_rhport = RHPORT_PIO(rhport); return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen); diff --git a/tools/get_deps.py b/tools/get_deps.py index 3f529bd7e..ba9dc23ce 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -58,8 +58,8 @@ deps_optional = { 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', '144f1eb7ea8c06512e12f12b27383601c0272410', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], - 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - '0ca3657d55ea20e7fa4483bbd21ce951bc1d6fa5', + 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', + '810653f66adadba3e0e4b4b56d5167ac4f7fdbf7', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', -- cgit v1.3.1 From 3851c7c97a2a743b63d879ab622dd267b4195f08 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 17 Apr 2025 16:07:10 +0700 Subject: - run arm-iar using github action - add skip_ci.txt to family folder to skip boards in ci run --- .github/workflows/build.yml | 62 ++++++++++++++++++----------- .github/workflows/build_util.yml | 2 + hw/bsp/rp2040/skip_ci.txt | 7 ++++ hw/bsp/stm32h7/boards/stm32h743eval/board.h | 10 ++--- hw/bsp/stm32h7/family.c | 4 +- tools/build.py | 7 +++- 6 files changed, 61 insertions(+), 31 deletions(-) create mode 100644 hw/bsp/rp2040/skip_ci.txt (limited to 'tools') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index f42499ef7..6419efbe8 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -110,35 +110,51 @@ jobs: one-per-family: true # --------------------------------------- - # Build IAR on HFP self-hosted + # Build IAR # Since IAR Token secret is not passed to forked PR, only build on PR from the same repo # --------------------------------------- arm-iar: if: github.repository_owner == 'hathach' && github.event_name == 'push' needs: set-matrix - runs-on: [self-hosted, Linux, X64, hifiphile] - env: - BUILD_ARGS: ${{ join(fromJSON(needs.set-matrix.outputs.json)['arm-iar'], ' ') }} - IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }} - steps: - - name: Clean workspace - run: | - echo "Cleaning up previous run" - rm -rf "${{ github.workspace }}" - mkdir -p "${{ github.workspace }}" - - - name: Toolchain version - run: | - iccarm --version - - - name: Checkout TinyUSB - uses: actions/checkout@v4 - - - name: Get Dependencies - run: python3 tools/get_deps.py $BUILD_ARGS + uses: ./.github/workflows/build_util.yml + secrets: inherit + strategy: + fail-fast: false + matrix: + build-system: + - 'cmake' + with: + build-system: ${{ matrix.build-system }} + toolchain: 'arm-iar' + build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)['arm-iar']) }} + one-per-family: ${{ github.event_name == 'push' }} - - name: Build - run: python3 tools/build.py --one-per-family --toolchain iar $BUILD_ARGS +# arm-iar: +# if: github.repository_owner == 'hathach' && github.event_name == 'push' +# needs: set-matrix +# runs-on: [self-hosted, Linux, X64, hifiphile] +# env: +# BUILD_ARGS: ${{ join(fromJSON(needs.set-matrix.outputs.json)['arm-iar'], ' ') }} +# IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }} +# steps: +# - name: Clean workspace +# run: | +# echo "Cleaning up previous run" +# rm -rf "${{ github.workspace }}" +# mkdir -p "${{ github.workspace }}" +# +# - name: Toolchain version +# run: | +# iccarm --version +# +# - name: Checkout TinyUSB +# uses: actions/checkout@v4 +# +# - name: Get Dependencies +# run: python3 tools/get_deps.py $BUILD_ARGS +# +# - name: Build +# run: python3 tools/build.py --one-per-family --toolchain iar $BUILD_ARGS # --------------------------------------- # Zephyr diff --git a/.github/workflows/build_util.yml b/.github/workflows/build_util.yml index 2de68c6f3..a2c96f3c0 100644 --- a/.github/workflows/build_util.yml +++ b/.github/workflows/build_util.yml @@ -58,6 +58,8 @@ jobs: shell: bash - name: Build + env: + IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }} run: | if [ "${{ inputs.toolchain }}" == "esp-idf" ]; then docker run --rm -v $PWD:/project -w /project espressif/idf:tinyusb python tools/build.py ${{ matrix.arg }} diff --git a/hw/bsp/rp2040/skip_ci.txt b/hw/bsp/rp2040/skip_ci.txt new file mode 100644 index 000000000..fe99c9f65 --- /dev/null +++ b/hw/bsp/rp2040/skip_ci.txt @@ -0,0 +1,7 @@ +# boards in this files are skipped when running CI with this family +adafruit_feather_rp2040_usb_host +adafruit_fruit_jam +adafruit_metro_rp2350 +feather_rp2040_max3421 +pico_sdk +raspberry_pi_pico_w diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 334876e51..cb6d772e6 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -184,7 +184,7 @@ static MFXSTM32L152_Object_t mfx_obj = { 0 }; static MFXSTM32L152_IO_Mode_t* mfx_io = NULL; static uint32_t mfx_vbus_pin[2] = { MFXSTM32L152_GPIO_PIN_7, MFXSTM32L152_GPIO_PIN_9 }; -int32_t board_i2c_init(void) { +static int32_t board_i2c_init(void) { __HAL_RCC_I2C1_CLK_ENABLE(); __HAL_RCC_I2C1_FORCE_RESET(); __HAL_RCC_I2C1_RELEASE_RESET(); @@ -200,16 +200,16 @@ int32_t board_i2c_init(void) { return 0; } -int32_t board_i2c_deinit(void) { +static int32_t board_i2c_deinit(void) { return 0; } -int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { +static int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); return 0; } -int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { +static int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); return 0; } @@ -249,7 +249,7 @@ static inline void board_init2(void) { } // VBUS1 is actually controlled by USB3320C PHY (using dwc2 drivebus signal) -void board_vbus_set(uint8_t rhport, bool state) { +static void board_vbus_set(uint8_t rhport, bool state) { if (mfx_io) { mfx_io->IO_WritePin(&mfx_obj, mfx_vbus_pin[rhport], state); } diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index e5228b29b..f8723b0c7 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -80,7 +80,7 @@ void OTG_HS_IRQHandler(void) { } #ifdef TRACE_ETM -void trace_etm_init(void) { +static void trace_etm_init(void) { // H7 trace pin is PE2 to PE6 GPIO_InitTypeDef gpio_init; gpio_init.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; @@ -94,7 +94,7 @@ void trace_etm_init(void) { DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN; } #else - #define trace_etm_init() +#define trace_etm_init() #endif void board_init(void) { diff --git a/tools/build.py b/tools/build.py index 633d2b582..d28ddd929 100755 --- a/tools/build.py +++ b/tools/build.py @@ -182,9 +182,14 @@ def build_boards_list(boards, toolchain, build_system, build_flags_on): def build_family(family, toolchain, build_system, build_flags_on, one_per_family, boards): + skip_ci = ['pico_sdk'] + if os.getenv('GITHUB_ACTIONS') or os.getenv('CIRCLECI'): + skip_ci_file = Path(f"hw/bsp/{family}/skip_ci.txt") + if skip_ci_file.exists(): + skip_ci = skip_ci_file.read_text().split() all_boards = [] for entry in os.scandir(f"hw/bsp/{family}/boards"): - if entry.is_dir() and entry.name != 'pico_sdk': + if entry.is_dir() and not entry.name in skip_ci: all_boards.append(entry.name) all_boards.sort() -- cgit v1.3.1 From 0937a2b2d3dbc0b5595c6ea3a6acc8a691f73941 Mon Sep 17 00:00:00 2001 From: Eli Hughes Date: Sat, 26 Apr 2025 13:04:39 -0400 Subject: using get-deps from tinyuf2 --- tools/get_deps.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index ba9dc23ce..d89c1b2b1 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -243,11 +243,13 @@ def get_a_dep(d): p.mkdir(parents=True) run_cmd(f"{git_cmd} init") run_cmd(f"{git_cmd} remote add origin {url}") + head = None + else: + # Check if commit is already fetched + result = run_cmd(f"{git_cmd} rev-parse HEAD") + head = result.stdout.decode("utf-8").splitlines()[0] + run_cmd(f"{git_cmd} reset --hard") - # Check if commit is already fetched - result = run_cmd(f"{git_cmd} rev-parse HEAD") - head = result.stdout.decode("utf-8").splitlines()[0] - run_cmd(f"{git_cmd} reset --hard") if commit != head: run_cmd(f"{git_cmd} fetch --depth 1 origin {commit}") run_cmd(f"{git_cmd} checkout FETCH_HEAD") -- cgit v1.3.1 From f392b4c91d725a02010cea46f94af3cb948b5136 Mon Sep 17 00:00:00 2001 From: Eli Hughes Date: Wed, 1 Jan 2025 13:22:48 -0500 Subject: Added initial support for FRDM-MCXA156 and fixed up a crash with MCXN947 I will be porting tinyuf2 to MCXA156 and N947 and need this work in place. This is the 1st step before bringing in support for other MCX devices. We had previous patched https://github.com/hathach/mcux-sdk.git' for MCX support as it was not pulically available I updated get_deps to point to the mcux-sdk version 2.16.10 from NXP. I repointed the entry in the get_deps script to use NXP MCU repo. The existing current code couldn't build as the MCUXpresso SDK was old. - For now, I put a copy of fsl_spc.c in the drivers folder for the mcx family. None of the ports could build with the version in the mcux github sdk. The sdk on github has version 2.4.0. The SDK package that can be downloaded with the SDK generator uses 2.4.2. All of the clock_config routines use versions of the datastructure from 2.4.2. For now, keeping an updated copy in hw/bsp/mcx/drivers so we can build against the latest mcuxpresso sdk and enable MCXA156. I'll file an issue on the nxp github. - Cleaned up the MCX family.c a little bit. the MCXA/N these chips don't have SCT so I removed the neopixel code. - fixed a clock init issue w/ N947 that was causing it to crash when initializing the uart. - I tested the cmake and make scripts on the A153,A156 and N947 using the CDC/MSC sample. All worked OK. - Patched get_deps so it will do a fetch/check on a new folder. Some of the deps were failing on a fresh clone of tinyusb - Fixed lpc51,54 and lpc55 make/cmake files to build with mcuxpresso sdk 2.16.10 The folder structure for flexcomm/uart changed a little bit - lpc55s59 libpower_hardabi.a no longer is included in mcuxpressosdk, (fsl_power.c is replacement). remove of libpower_hardabi.a from the linker config. LPC55 still works as expected. - Using tinyuf2 get deps --- README.rst | 4 +- hw/bsp/lpc51/family.cmake | 2 +- hw/bsp/lpc51/family.mk | 9 +- hw/bsp/lpc54/family.cmake | 3 +- hw/bsp/lpc54/family.mk | 3 +- hw/bsp/lpc55/family.cmake | 4 +- hw/bsp/lpc55/family.mk | 7 +- hw/bsp/mcx/boards/frdm_mcxa153/board.h | 4 +- hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c | 4 +- hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h | 2 +- hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c | 53 +- hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h | 6 +- hw/bsp/mcx/boards/frdm_mcxa156/board.cmake | 21 + hw/bsp/mcx/boards/frdm_mcxa156/board.h | 69 + hw/bsp/mcx/boards/frdm_mcxa156/board.mk | 14 + hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c | 482 +++++ hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h | 170 ++ hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c | 144 ++ hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h | 51 + hw/bsp/mcx/boards/frdm_mcxn947/board.h | 13 +- hw/bsp/mcx/drivers/spc/fsl_spc.c | 1680 +++++++++++++++++ hw/bsp/mcx/drivers/spc/fsl_spc.h | 2433 +++++++++++++++++++++++++ hw/bsp/mcx/family.c | 30 +- hw/bsp/mcx/family.cmake | 28 +- hw/bsp/mcx/family.mk | 21 +- tools/get_deps.py | 14 +- 26 files changed, 5165 insertions(+), 106 deletions(-) create mode 100644 hw/bsp/mcx/boards/frdm_mcxa156/board.cmake create mode 100644 hw/bsp/mcx/boards/frdm_mcxa156/board.h create mode 100644 hw/bsp/mcx/boards/frdm_mcxa156/board.mk create mode 100644 hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c create mode 100644 hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h create mode 100644 hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c create mode 100644 hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h create mode 100644 hw/bsp/mcx/drivers/spc/fsl_spc.c create mode 100644 hw/bsp/mcx/drivers/spc/fsl_spc.h (limited to 'tools') diff --git a/README.rst b/README.rst index efbfa354b..0d6b147d9 100644 --- a/README.rst +++ b/README.rst @@ -167,7 +167,9 @@ Supported CPUs | | +-------------------+--------+------+-----------+------------------------+-------------------+ | | | 54, 55 | ✔ | | ✔ | lpc_ip3511 | | | +---------+-------------------+--------+------+-----------+------------------------+-------------------+ -| | MCX | N9, A15 | ✔ | | ✔ | ci_fs, ci_hs | | +| | MCX | N9 | ✔ | | ✔ | ci_fs, ci_hs | | +| | +-------------------+--------+------+-----------+------------------------+-------------------+ +| | | A15 | ✔ | | | ci_fs | | +--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+ | Raspberry Pi | RP2040, RP2350 | ✔ | ✔ | ✖ | rp2040, pio_usb | | +--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index 2146c29f7..09d97d256 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -36,7 +36,7 @@ function(add_board_target BOARD_TARGET) # driver ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk index b41b5438e..f37360a71 100644 --- a/hw/bsp/lpc51/family.mk +++ b/hw/bsp/lpc51/family.mk @@ -28,18 +28,19 @@ SRC_C += \ $(MCU_DIR)/drivers/fsl_reset.c \ $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_usart.c + $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MCU_DIR) \ $(TOP)/$(MCU_DIR)/drivers \ $(TOP)/$(SDK_DIR)/drivers/common \ $(TOP)/$(SDK_DIR)/drivers/flexcomm \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ $(TOP)/$(SDK_DIR)/drivers/lpc_gpio - + SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index 90497b9fb..66320870a 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET) ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c ${SDK_DIR}/drivers/common/fsl_common_arm.c ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c @@ -56,6 +56,7 @@ function(add_board_target BOARD_TARGET) # driver ${SDK_DIR}/drivers/common ${SDK_DIR}/drivers/flexcomm + ${SDK_DIR}/drivers/flexcomm/usart ${SDK_DIR}/drivers/lpc_iocon ${SDK_DIR}/drivers/lpc_gpio ${SDK_DIR}/drivers/lpuart diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk index ea4c9c39c..8dc70f621 100644 --- a/hw/bsp/lpc54/family.mk +++ b/hw/bsp/lpc54/family.mk @@ -36,7 +36,7 @@ SRC_C += \ $(MCU_DIR)/drivers/fsl_reset.c \ $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_usart.c \ + $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ $(SDK_DIR)/drivers/common/fsl_common_arm.c INC += \ @@ -46,6 +46,7 @@ INC += \ $(TOP)/$(MCU_DIR)/drivers \ $(TOP)/$(SDK_DIR)/drivers/common \ $(TOP)/$(SDK_DIR)/drivers/flexcomm \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ $(TOP)/$(SDK_DIR)/drivers/lpc_gpio diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index cd1eb5f78..a89548635 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET) ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c ${SDK_DIR}/drivers/common/fsl_common_arm.c ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c - ${SDK_DIR}/drivers/flexcomm/fsl_usart.c + ${SDK_DIR}/drivers/flexcomm/usart/fsl_usart.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c @@ -56,9 +56,9 @@ function(add_board_target BOARD_TARGET) # driver ${SDK_DIR}/drivers/common ${SDK_DIR}/drivers/flexcomm + ${SDK_DIR}/drivers/flexcomm/usart ${SDK_DIR}/drivers/lpc_iocon ${SDK_DIR}/drivers/lpc_gpio - ${SDK_DIR}/drivers/lpuart ${SDK_DIR}/drivers/sctimer # mcu ${SDK_DIR}/devices/${MCU_VARIANT} diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk index d82e85904..85b9a2cc9 100644 --- a/hw/bsp/lpc55/family.mk +++ b/hw/bsp/lpc55/family.mk @@ -45,7 +45,7 @@ SRC_C += \ $(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \ $(SDK_DIR)/drivers/common/fsl_common_arm.c \ $(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \ - $(SDK_DIR)/drivers/flexcomm/fsl_usart.c \ + $(SDK_DIR)/drivers/flexcomm/usart/fsl_usart.c \ lib/sct_neopixel/sct_neopixel.c INC += \ @@ -55,11 +55,12 @@ INC += \ $(TOP)/$(MCU_DIR) \ $(TOP)/$(MCU_DIR)/drivers \ $(TOP)/$(SDK_DIR)/drivers/common \ - $(TOP)/$(SDK_DIR)/drivers/flexcomm \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/usart \ + $(TOP)/$(SDK_DIR)/drivers/flexcomm/ \ $(TOP)/$(SDK_DIR)/drivers/lpc_iocon \ $(TOP)/$(SDK_DIR)/drivers/lpc_gpio \ $(TOP)/$(SDK_DIR)/drivers/sctimer SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S -LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a + diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h index fb1290088..86f987de9 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h @@ -39,10 +39,10 @@ extern "C" { // LED #define LED_GPIO GPIO3 #define LED_CLK kCLOCK_GateGPIO3 -#define LED_PIN 12 // red +#define LED_PIN 12 //red #define LED_STATE_ON 0 -// ISP button (Dummy, use unused pin +// ISP button #define BUTTON_GPIO GPIO3 #define BUTTON_CLK kCLOCK_GateGPIO3 #define BUTTON_PIN 29 //sw2 diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c index f16bc51f6..5a132dc67 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c @@ -45,14 +45,13 @@ processor_version: 0.13.0 * Variables ******************************************************************************/ /* System clock frequency. */ -//uint32_t SystemCoreClock; +//extern uint32_t SystemCoreClock; /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { - BOARD_BootClockFRO96M(); } /******************************************************************************* @@ -386,7 +385,6 @@ void BOARD_BootClockFRO64M(void) /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockFRO96M -called_from_default_init: true outputs: - {id: CLK_1M_clock.outFreq, value: 1 MHz} - {id: CLK_48M_clock.outFreq, value: 48 MHz} diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h index aae811052..079d0d312 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h @@ -4,7 +4,7 @@ * * SPDX-License-Identifier: BSD-3-Clause */ - + /*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c index cc8f56e63..fce756e72 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c @@ -4,7 +4,6 @@ * * SPDX-License-Identifier: BSD-3-Clause */ - /*********************************************************************************************************************** * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. @@ -18,16 +17,13 @@ product: Pins v14.0 processor: MCXA153 package_id: MCXA153VLH mcu_data: ksdk2_0 -processor_version: 0.14.3 -pin_labels: -- {pin_num: '38', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, label: LED_RED, identifier: LED_RED} +processor_version: 0.14.4 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ #include "fsl_common.h" #include "fsl_port.h" -#include "fsl_gpio.h" #include "pin_mux.h" /* FUNCTION ************************************************************************************************************ @@ -47,8 +43,10 @@ void BOARD_InitBootPins(void) BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} - pin_list: - - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'false', slew_rate: fast, - open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ /* clang-format on */ @@ -61,15 +59,6 @@ BOARD_InitPins: * END ****************************************************************************************************************/ void BOARD_InitPins(void) { - RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn); - RESET_PeripheralReset(kPORT0_RST_SHIFT_RSTn); - CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); - CLOCK_AttachClk(kFRO12M_to_LPUART0); - - /* write to PORT0: Peripheral clock is enabled */ - CLOCK_EnableClock(kCLOCK_GatePORT0); - - /* Write to GPIO3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GateGPIO3); /* Write to PORT3: Peripheral clock is enabled */ CLOCK_EnableClock(kCLOCK_GatePORT3); @@ -78,30 +67,13 @@ void BOARD_InitPins(void) /* PORT3 peripheral is released from reset */ RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); - const port_pin_config_t port3_12_pin38_config = {/* Internal pull-up/down resistor is disabled */ - kPORT_PullDisable, - /* Low internal pull resistor value is selected. */ - kPORT_LowPullResistor, - /* Fast slew rate is configured */ - kPORT_FastSlewRate, - /* Passive input filter is disabled */ - kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - kPORT_NormalDriveStrength, - /* Pin is configured as P3_12 */ - kPORT_MuxAlt0, - /* Digital input enabled */ - kPORT_InputBufferEnable, - /* Digital input is not inverted */ - kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - kPORT_UnlockRegister}; - /* PORT3_12 (pin 38) is configured as P3_12 */ - PORT_SetPinConfig(PORT3, 12U, &port3_12_pin38_config); + + /* Write to PORT0: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* LPUART0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + /* PORT0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */ kPORT_PullUp, @@ -152,7 +124,6 @@ void BOARD_InitPins(void) kPORT_UnlockRegister}; /* PORT0_3 (pin 52) is configured as LPUART0_TXD */ PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config); - } /*********************************************************************************************************************** * EOF diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h index 06b6fdee9..2c0e617a5 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h @@ -1,9 +1,13 @@ /* - * Copyright 2022 NXP + * Copyright 2023 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ #ifndef _PIN_MUX_H_ #define _PIN_MUX_H_ diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake new file mode 100644 index 000000000..a6aa6c2e4 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.cmake @@ -0,0 +1,21 @@ +set(MCU_VARIANT MCXA156) +set(MCU_CORE MCXA156) + +set(JLINK_DEVICE MCXA156_M33) +set(PYOCD_TARGET MCXA156) +set(NXPLINK_DEVICE MCXA156:MCXA156) + +set(PORT 0) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + CPU_MCXA156VLH + BOARD_TUD_RHPORT=0 + BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + CFG_EXAMPLE_VIDEO_READONLY + ) + target_sources(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c + ) +endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.h b/hw/bsp/mcx/boards/frdm_mcxa156/board.h new file mode 100644 index 000000000..6c19797c6 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.h @@ -0,0 +1,69 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Freedom MCXA156 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA156 +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_GPIO GPIO3 +#define LED_CLK kCLOCK_GateGPIO3 +#define LED_PIN 12 // red +#define LED_STATE_ON 0 + +// ISP button +#define BUTTON_GPIO GPIO0 +#define BUTTON_CLK kCLOCK_GateGPIO0 +#define BUTTON_PIN 6 //SW3 +#define BUTTON_STATE_ACTIVE 0 + +// UART +#define UART_DEV LPUART0 + +static inline void board_uart_init_clock(void) { + /* attach 12 MHz clock to LPUART0 (debug console) */ + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPUART0); + + RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn); +} + +// XTAL +#define XTAL0_CLK_HZ (24 * 1000 * 1000U) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/board.mk b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk new file mode 100644 index 000000000..d4a59b32a --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/board.mk @@ -0,0 +1,14 @@ +MCU_VARIANT = MCXA156 +MCU_CORE = MCXA156 +PORT = 0 + +CPU_CORE = cortex-m33-nodsp-nofp +CFLAGS += \ + -DCPU_MCXA156VLH \ + -DCFG_TUSB_MCU=OPT_MCU_MCXA15 \ + +JLINK_DEVICE = MCXA156 +PYOCD_TARGET = MCXA156 + +# flash using pyocd +flash: flash-jlink diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c new file mode 100644 index 000000000..f549af243 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.c @@ -0,0 +1,482 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v13.0 +processor: MCXA156 +package_id: MCXA156VLL +mcu_data: ksdk2_0 +processor_version: 0.15.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" +#include "fsl_spc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +//extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockFRO96M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CPU_clock.outFreq, value: 12 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 12 MHz} +- {id: Slow_clock.outFreq, value: 3 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO24M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 24 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 6 MHz} +- {id: System_clock.outFreq, value: 24 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +void BOARD_BootClockFRO24M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO48M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +void BOARD_BootClockFRO48M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO64M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 64 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz} +- {id: FRO_HF_clock.outFreq, value: 64 MHz} +- {id: MAIN_clock.outFreq, value: 64 MHz} +- {id: Slow_clock.outFreq, value: 16 MHz} +- {id: System_clock.outFreq, value: 64 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +sources: +- {id: SCG.FIRC.outFreq, value: 64 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +void BOARD_BootClockFRO64M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO96M +called_from_default_init: true +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 96 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz} +- {id: FRO_HF_clock.outFreq, value: 96 MHz} +- {id: MAIN_clock.outFreq, value: 96 MHz} +- {id: Slow_clock.outFreq, value: 24 MHz} +- {id: System_clock.outFreq, value: 96 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: CLKOUTDIV_HALT, value: Enable} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +sources: +- {id: SCG.FIRC.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +void BOARD_BootClockFRO96M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK; +} diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h new file mode 100644 index 000000000..db80b79f3 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/clock_config.h @@ -0,0 +1,170 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO24M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO64M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c new file mode 100644 index 000000000..317c311b5 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.c @@ -0,0 +1,144 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v15.0 +processor: MCXA156 +package_id: MCXA156VLL +mcu_data: ksdk2_0 +processor_version: 0.15.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_port.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ + + RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn); + CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPUART0); + + /* GPIO3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GateGPIO3); + /* PORT3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT3); + /* GPIO3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + /* PORT3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + + /* GPIO3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GateGPIO0); + /* PORT3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* GPIO3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn); + /* PORT3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + + /* PORT0: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* LPUART0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + /* PORT0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + + const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_RXD */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_2 (pin 78) is configured as LPUART0_RXD */ + PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config); + + const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_TXD */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ + PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h new file mode 100644 index 000000000..fb7d1fc04 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa156/pin_mux.h @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.h b/hw/bsp/mcx/boards/frdm_mcxn947/board.h index a35b6818a..bb15620ef 100644 --- a/hw/bsp/mcx/boards/frdm_mcxn947/board.h +++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.h @@ -49,17 +49,22 @@ #define BUTTON_STATE_ACTIVE 0 // UART -#define UART_DEV LPUART4 +#define UART_DEV LPUART4 +#define LP_FLEXCOMM_INST 4 + +#include "fsl_lpflexcomm.h" static inline void board_uart_init_clock(void) { + /* attach FRO 12M to FLEXCOMM4 */ + + LP_FLEXCOMM_Init(LP_FLEXCOMM_INST, LP_FLEXCOMM_PERIPH_LPUART); + CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u); CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn); -} -//#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN -//#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN +} // XTAL #define XTAL0_CLK_HZ (24 * 1000 * 1000U) diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.c b/hw/bsp/mcx/drivers/spc/fsl_spc.c new file mode 100644 index 000000000..c6a9b2932 --- /dev/null +++ b/hw/bsp/mcx/drivers/spc/fsl_spc.c @@ -0,0 +1,1680 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_spc" +#endif + +/* + * $Coverage Justification Reference$ + * + * $Justification spc_c_ref_1$ + * The SPC busy status flag is too short to get coverage data. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets selected power domain's requested low power mode. + * + * param base SPC peripheral base address. + * param powerDomainId Power Domain Id, please refer to spc_power_domain_id_t. + * + * return The selected power domain's requested low power mode, please refer to spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + + uint32_t val; + + val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT); + return (spc_power_domain_low_power_mode_t)val; +} + +/*! + * brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * param base SPC peripheral base address. + * return Current isolation status for each power domains. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base) +{ + uint32_t reg; + + reg = base->SC; + return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT); +} + +/*! + * brief Configs Low power request output pin. + * + * This function configs the low power request output pin + * + * param base SPC peripheral base address. + * param config Pointer the spc_LowPower_Request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = base->LPREQ_CFG; + reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK); + + if (config->enable) + { + reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) | + SPC_LPREQ_CFG_LPREQOV((uint8_t)(config->override)); + } + else + { + reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK; + } + + base->LPREQ_CFG = reg; +} + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * param base SPC peripheral base address. + * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = (base->VDD_CORE_GLITCH_DETECT_SC) & + ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK); + + reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) | + SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) | + SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt); + + base->VDD_CORE_GLITCH_DETECT_SC = reg; +} +#endif + +/*! + * brief Set SRAM operate voltage. + * + * param base SPC peripheral base address. + * param config The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= SPC_SRAMCTL_VSM(config->operateVoltage); + + base->SRAMCTL = reg; + + if (config->requestVoltageUpdate) + { + base->SRAMCTL |= SPC_SRAMCTL_REQ_MASK; + while ((base->SRAMCTL & SPC_SRAMCTL_ACK_MASK) == 0UL) + { + /* Wait until acknowledged */ + ; + } + base->SRAMCTL &= ~SPC_SRAMCTL_REQ_MASK; + } +} + +/*! + * brief Configs Bandgap mode in Active mode. + * + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configrue LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * retval kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->ACTIVE_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = SPC_GetActiveModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + } + + reg &= ~SPC_ACTIVE_CFG_BGMODE_MASK; + reg |= SPC_ACTIVE_CFG_BGMODE(mode); + + base->ACTIVE_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs Bandgap mode in Low Power mode. + * + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->LP_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) == + SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif + } + + reg &= ~SPC_LP_CFG_BGMODE_MASK; + reg |= SPC_LP_CFG_BGMODE(mode); + base->LP_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs CORE voltage detect options. + * + * This function configs CORE voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U); + + base->VD_CORE_CFG = reg; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * brief Enables the Core High Voltage Detector in Active mode. + * + * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * retval kStatus_Success Enable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core High Voltage Detector in Low Power mode. + * + * note If the CORE_LDO high voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each regulator + * must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * retval kStatus_Success Enable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_HVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! + * brief Enables the Core VDD Low Voltage Detector in Active mode. + * + * note If the Core VDD high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core Low Voltage Detector in Low Power mode. + * + * note If the Core VDD low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * + * param base SPC peripheral base address. + * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + (void)level; + (void)base; + + /* + uint32_t reg; + + reg = base->VD_SYS_CFG; + + base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK); + reg |= SPC_VD_SYS_CFG_LVSEL(level); + + base->VD_SYS_CFG = reg; */ +} + +/*! + * brief Configs SYS VDD voltage detect options. + * + * This function config SYS voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_SYS_CFG_HVDIE(1U) : SPC_VD_SYS_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_SYS_CFG_LVDIE(1U) : SPC_VD_SYS_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_SYS_CFG_HVDRE(1U) : SPC_VD_SYS_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_SYS_CFG_LVDRE(1U) : SPC_VD_SYS_CFG_LVDRE(0U); + + base->VD_SYS_CFG = reg; + + (void)(config->level); + /* SPC_SetSystemVDDLowVoltageLevel(base, config->level); */ +} + +/*! + * brief Enables the System VDD High Voltage Detector in Active mode. + * + * note If the System_LDO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of + * each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * retval kStatus_Success Enable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD Low Voltage Detector in Active mode. + * + * note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * retval kStatus_Success Enable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD High Voltage Detector in Low Power mode. + * + * note If the System_LDO high voltage detect is enabled in low power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * retval kStatus_Success Enable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD Low Voltage Detector in Low Power mode. + * + * note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * retval kStatus_Success Enable System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_LVDE_MASK; + } + + return status; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * param base SPC peripheral base address. + * param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + uint32_t reg; + + reg = base->VD_IO_CFG; + + base->VD_IO_CFG &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_LVSEL_MASK); + reg |= SPC_VD_IO_CFG_LVSEL(level); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Configs IO VDD voltage detect options. + * + * This function config IO voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_IO_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + /* Set trip voltage level. */ + SPC_SetIOVDDLowVoltageLevel(base, config->level); + + reg = base->VD_IO_CFG; + reg &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_HVDRE_MASK | SPC_VD_IO_CFG_HVDIE_MASK); + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_IO_CFG_HVDIE(1U) : SPC_VD_IO_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_IO_CFG_LVDIE(1U) : SPC_VD_IO_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_IO_CFG_HVDRE(1U) : SPC_VD_IO_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_IO_CFG_LVDRE(1U) : SPC_VD_IO_CFG_LVDRE(0U); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Enables the IO VDD High Voltage Detector in Active mode. + * + * note If the IO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * retval kStatus_Success Enable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD Low Voltage Detector in Active mode. + * + * note If the IO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD High Voltage Detector in Low Power mode. + * + * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * retval kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD Low Voltage Detector in Low Power mode. + * + * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_LVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * param base SPC peripheral base address. + * param lowPowerIsoMask The mask of external domains isolate enable during low power mode. + * param IsoMask The mask of external domains isolate. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask) +{ + uint32_t reg = 0UL; + + reg |= SPC_EVD_CFG_REG_EVDISO(IsoMask) | SPC_EVD_CFG_REG_EVDLPISO(lowPowerIsoMask); + base->EVD_CFG = reg; +} + +/*! + * brief Configs Core LDO Regulator in Active mode. + * + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Core_LDO_option_t structure. + * + * retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + + /* Check input parameters. */ + /* 1. Bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 2. To set to low drive strength, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + + if ((uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) != (uint8_t)(option->CoreLDOVoltage)) + { +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, kSPC_CoreLDO_NormalDriveStrength); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval kStatus_SPC_CORELDOVoltageSetFail Core LDO voltage level should only be + * changed when the CORE_LDO is in normal drive strength. + * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base)) + { +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + if (SPC_GetActiveModeCoreLDODriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength) + { + return kStatus_SPC_CORELDOVoltageSetFail; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel)); + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + } + return kStatus_Success; +} + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength is set as Normal. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure. + * retval kStatus_Success Config Core LDO regulator in power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore HVDs/LVDs are not disabled before invoking this function. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option) +{ + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + if (status == kStatus_Success) + { + (void)SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + + return status; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If Core LDO's drive strengths are same in active and low power mode, the Core LDO's voltage must be set to the + * same value in active and low power mode. Application should take care of this limitation. + * + * @note Some devices require Core LDO and DCDC have the same voltage level even if Core LDO is off. Application should + * take care of this limitation. + * + * param base SPC peripheral base address. + * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval #kStatus_SPC_Busy The SPC instance is busy to execute other operation. + * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel)); + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to + * low. + */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + else + { + /* To specify normal drive strength, the bandgap must be enabled in low power mode. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | SPC_LP_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * brief Configs System LDO VDD Regulator in Active mode. + * + * This function configs System LDO VDD Regulator in Active mode. + * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enable the bandgap. + * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. + * Otherwise it will be fail to regulator to Over Drive Voltage. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure. + * retval kStatus_Success Config System LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + /* Check input parameters before setting registers. */ + /* 1. To set to low DS, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + /* 2. If specify normal drive strength, bandgap must not be disabled. */ + if ((SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) && + (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 3. Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) && + ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + + (void)SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + (void)SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel) +{ + if (voltageLevel == kSPC_SysLDO_OverDriveVoltage) + { + /* Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + } + + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_SysLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * param base SPC peripheral base address. + * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure. + * + * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option) +{ + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + + return status; +} + +/*! + * brief Set System LDO Regulator drive strength in Low Power Mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + else + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * brief Configs DCDC VDD Regulator in Active mode. + * + * note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_DCDC_option_t structure. + * + * retval kStatus_Success Config DCDC regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option) +{ + assert(option != NULL); + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + + if (status == kStatus_Success) + { + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Active mode. + * + * note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs DCDC VDD Regulator in Low power modes. + * + * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * In Deep Power Down mode, DCDC regulator is always turned off. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure. + * + * retval kStatus_Success Config DCDC regulator in low power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap should be enabled before invoking this function. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option) +{ + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + /* Check input parameter before setting registers. */ + if ((option->DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) && + (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* + 1. Configure to desired voltage level. + 2. Change to low drive strength. + 3. Configure same voltage level in active mode. + */ + SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + + /* Change to desired drive strength. */ + if (option->DCDCDriveStrength != kSPC_DCDC_LowDriveStrength) + { + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Config DCDC Burst options + * + * param base SPC peripheral base address. + * param config Pointer to spc_DCDC_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config) +{ + assert(config != NULL); + uint32_t reg; + reg = base->DCDC_CFG; + reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK); + reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq); + reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U); + base->DCDC_CFG = reg; + + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + if ((config->sofwareBurstRequest) || (config->externalBurstRequest)) + { + /* Clear DCDC burst acknowledge flag. */ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; + } + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest); + + if (config->sofwareBurstRequest) + { + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; + } +} + +/*! + * brief Set the count value of the reference clock. + * + * This function set the count value of the reference clock to control the frequency + * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * + * param base SPC peripheral base address. + * param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count) +{ + uint32_t reg; + + reg = base->DCDC_BURST_CFG; + reg &= ~SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK; + reg |= SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(count); + + base->DCDC_BURST_CFG = reg; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * brief Configs all settings of regulators in Active mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other low-level functions. + * + * param base SPC peripheral base address. + * param config Pointer to spc_active_mode_regulators_config_t structure. + * retval kStatus_Success Config regulators in Active power mode successful. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config) +{ + assert(config != NULL); + + uint32_t activeModeVDValue = SPC_GetActiveModeVoltageDetectStatus(base); + + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((activeModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckActiveModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. Must disable system LDO high voltage detector before specifing SysLDO to overdrive voltage */ + if (((activeModeVDValue & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) && + (config->SysLDOOption.SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 3. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 4. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & ~(SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; +} + +/*! + * brief Configs regulators in Low Power mode. + * + * This function provides the method to config all on-chip regulators in Low Power mode. + * + * param base SPC peripheral base address. + * param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * retval #kStatus_Success Config regulators in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config) +{ + assert(config != NULL); + uint32_t lpModeVDValue = SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((lpModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 3. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + base->LP_CFG = ((base->LP_CFG) & ~(SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableLowPowerModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; +} diff --git a/hw/bsp/mcx/drivers/spc/fsl_spc.h b/hw/bsp/mcx/drivers/spc/fsl_spc.h new file mode 100644 index 000000000..52cb71c24 --- /dev/null +++ b/hw/bsp/mcx/drivers/spc/fsl_spc.h @@ -0,0 +1,2433 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SPC_H_ +#define FSL_SPC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_spc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief SPC driver version 2.4.2. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) +/*! @} */ + +#define SPC_EVD_CFG_REG_EVDISO_SHIFT 0UL +#define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL +#define SPC_EVD_CFG_REG_EVDSTAT_SHIFT 16UL + +#define SPC_EVD_CFG_REG_EVDISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDSTAT(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT) + +#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)) +#define VDD_CORE_GLITCH_DETECT_SC GLITCH_DETECT_SC +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG +#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK SPC_GLITCH_DETECT_SC_LOCK_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT SPC_GLITCH_DETECT_SC_CNT_SELECT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK SPC_GLITCH_DETECT_SC_RE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE SPC_GLITCH_DETECT_SC_RE +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK SPC_GLITCH_DETECT_SC_TIMEOUT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT SPC_GLITCH_DETECT_SC_TIMEOUT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK SPC_GLITCH_DETECT_SC_IE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE SPC_GLITCH_DETECT_SC_IE +#endif + +/*! + * @brief SPC status enumeration. + * + * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual + * to check. + */ +enum +{ + kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any + type of power mode transition. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be + ignored for LVD/HVD enabled. */ + kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive + strength setting be ignored for LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive + voltage failed for SYS LDO HVD must be disabled. */ + kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U), /*!< SYS LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ + kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO voltage is wrong. */ + kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U), /*!< Core LDO voltage set fail. */ + kStatus_SPC_BandgapModeWrong = MAKE_STATUS(kStatusGroup_SPC, 6U), /*!< Selected Bandgap Mode wrong. */ +}; + +/*! + * @brief Voltage Detect Status Flags. + */ +enum _spc_voltage_detect_flags +{ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK, /*!< IO VDD High-Voltage detect flag. */ + kSPC_IOVDDLowVoltageDetectFlag = SPC_VD_STAT_IOVDD_LVDF_MASK, /*!< IO VDD Low-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */ + kSPC_SystemVDDLowVoltageDetectFlag = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage detect flag. */ +}; + +/*! + * @brief SPC power domain isolation status. + * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to + * check. + */ +enum _spc_power_domains +{ + kSPC_MAINPowerDomainRetain = 1UL << 16U, /*!< Peripherals and IO pads retain in MAIN Power Domain. */ + kSPC_WAKEPowerDomainRetain = 1UL << 17U, /*!< Peripherals and IO pads retain in WAKE Power Domain. */ +}; + +/*! + * @brief The enumeration of all analog module that can be controlled by SPC in active or low-power modes. + * @anchor spc_analog_module_control + */ +enum _spc_analog_module_control +{ + kSPC_controlVref = 1UL << 0UL, /*!< Enable/disable VREF in active or low-power modes. */ + kSPC_controlUsb3vDet = 1UL << 1UL, /*!< Enable/disable USB3V_Det in active or low-power modes. */ + kSPC_controlDac0 = 1UL << 4UL, /*!< Enable/disable DAC0 in active or low-power modes. */ + kSPC_controlDac1 = 1UL << 5UL, /*!< Enable/disable DAC1 in active or low-power modes. */ + kSPC_controlDac2 = 1UL << 6UL, /*!< Enable/disable DAC2 in active or low-power modes. */ + kSPC_controlOpamp0 = 1UL << 8UL, /*!< Enable/disable OPAMP0 in active or low-power modes. */ + kSPC_controlOpamp1 = 1UL << 9UL, /*!< Enable/disable OPAMP1 in active or low-power modes. */ + kSPC_controlOpamp2 = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */ + kSPC_controlCmp0 = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */ + kSPC_controlCmp1 = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */ + kSPC_controlCmp2 = 1UL << 18UL, /*!< Enable/disable CMP2 in active or low-power modes. */ + kSPC_controlCmp0Dac = 1UL << 20UL, /*!< Enable/disable CMP0_DAC in active or low-power modes. */ + kSPC_controlCmp1Dac = 1UL << 21UL, /*!< Enable/disable CMP1_DAC in active or low-power modes. */ + kSPC_controlCmp2Dac = 1UL << 22UL, /*!< Enable/disable CMP2_DAC in active or low-power modes. */ + kSPC_controlAllModules = 0x770773UL, /*!< Enable/disable all modules in active or low-power modes. */ +}; + +/*! + * @brief The enumeration of spc power domain, the connected power domain is chip specfic, please refer to chip's RM + * for details. + */ +typedef enum _spc_power_domain_id +{ + kSPC_PowerDomain0 = 0U, /*!< Power domain0, the connected power domain is chip specific. */ + kSPC_PowerDomain1 = 1U, /*!< Power domain1, the connected power domain is chip specific. */ +} spc_power_domain_id_t; + +/*! + * @brief The enumeration of Power domain's low power mode. + */ +typedef enum _spc_power_domain_low_power_mode +{ + kSPC_SleepWithSYSClockRunning = 0U, /*!< Power domain request SLEEP mode with SYS clock running. */ + kSPC_DeepSleepWithSysClockOff = 1U, /*!< Power domain request deep sleep mode with system clock off. */ + kSPC_PowerDownWithSysClockOff = 2U, /*!< Power domain request power down mode with system clock off. */ + kSPC_DeepPowerDownWithSysClockOff = 4U, /*!< Power domain request deep power down mode with system clock off. */ +} spc_power_domain_low_power_mode_t; + +/*! + * @brief SPC low power request output pin polarity. + */ +typedef enum _spc_lowPower_request_pin_polarity +{ + kSPC_HighTruePolarity = 0x0U, /*!< Control the High Polarity of the Low Power Reqest Pin. */ + kSPC_LowTruePolarity = 0x1U, /*!< Control the Low Polarity of the Low Power Reqest Pin. */ +} spc_lowpower_request_pin_polarity_t; + +/*! + * @brief SPC low power request output override. + */ +typedef enum _spc_lowPower_request_output_override +{ + kSPC_LowPowerRequestNotForced = 0x0U, /*!< Not Forced. */ + kSPC_LowPowerRequestReserved = 0x1U, /*!< Reserved. */ + kSPC_LowPowerRequestForcedLow = 0x2U, /*!< Forced Low (Ignore LowPower request output polarity setting.) */ + kSPC_LowPowerRequestForcedHigh = 0x3U, /*!< Forced High (Ignore LowPower request output polarity setting.) */ +} spc_lowpower_request_output_override_t; + +/*! + * @brief SPC Bandgap mode enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_bandgap_mode +{ + kSPC_BandgapDisabled = 0x0U, /*!< Bandgap disabled. */ + kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */ + kSPC_BandgapEnabledBufferEnabled = 0x2U, /*!< Bandgap enabled with Buffer enabled. */ + kSPC_BandgapReserved = 0x3U, /*!< Reserved. */ +} spc_bandgap_mode_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode. + * + * @note #kSPC_DCDC_RetentionVoltage not supported for all power modes. + */ +typedef enum _spc_dcdc_voltage_level +{ + kSPC_DCDC_RetentionVoltage = 0x0U, /*!< DCDC_CORE Regulator regulate to retention + Voltage(Only supportedin low power modes) */ + kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC_CORE Regulator regulate to Mid Voltage(1.0V). */ + kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC_CORE Regulator regulate to Normal Voltage(1.1V). */ + kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC_CORE Regulator regulate to Safe-Mode Voltage(1.2V). */ +} spc_dcdc_voltage_level_t; + +/*! + * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode. + * + * @note Different drive strength differ in these DCDC characterstics: + * Maximum load current + * Quiescent current + * Transient response. + */ +typedef enum _spc_dcdc_drive_strength +{ + kSPC_DCDC_PulseRefreshMode = 0x0U, /*!< DCDC_CORE Regulator Drive Strength set to Pulse Refresh Mode, + * This enum member is only useful for Low Power Mode config, please + * note that pluse refresh mode is invalid in SLEEP mode. + */ + kSPC_DCDC_LowDriveStrength = 0x1U, /*!< DCDC_CORE regulator Drive Strength set to low. */ + kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC_CORE regulator Drive Strength set to Normal. */ +} spc_dcdc_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief SYS LDO regulator voltage level enumeration in Active mode. + */ +typedef enum _spc_sys_ldo_voltage_level +{ + kSPC_SysLDO_NormalVoltage = 0x0U, /*!< SYS LDO VDD Regulator regulate to Normal Voltage(1.8V). */ + kSPC_SysLDO_OverDriveVoltage = 0x1U, /*!< SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V). */ +} spc_sys_ldo_voltage_level_t; + +/*! + * @brief SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_sys_ldo_drive_strength +{ + kSPC_SysLDO_LowDriveStrength = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */ + kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */ +} spc_sys_ldo_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +/*! + * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_core_ldo_voltage_level +{ + kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< @deprecated, to align with description of latest RM, please use + #kSPC_Core_LDO_RetentionVoltage as instead. */ + kSPC_Core_LDO_RetentionVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to retention voltage, please note that + only useful in low power modes and not all devices support this options + please refer to devices' RM for details. */ + kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ + kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ + kSPC_CoreLDO_OverDriveVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to overdrive Voltage. */ +} spc_core_ldo_voltage_level_t; + +/*! + * @brief CORE LDO VDD regulator Drive Strength enumeration in Low Power mode. + */ +typedef enum _spc_core_ldo_drive_strength +{ + kSPC_CoreLDO_LowDriveStrength = 0x0U, /*!< Core LDO VDD regulator Drive Strength set to low. */ + kSPC_CoreLDO_NormalDriveStrength = 0x1U, /*!< Core LDO VDD regulator Drive Strength set to Normal. */ +} spc_core_ldo_drive_strength_t; + +/*! + * @brief IO VDD Low-Voltage Level Select. + */ +typedef enum _spc_low_voltage_level_select +{ + kSPC_LowVoltageNormalLevel = 0x0U, /*!< @deprecated, please use kSPC_LowVoltageHighRange as instead. */ + kSPC_LowVoltageSafeLevel = 0x1U, /*!< @deprecated, please use kSPC_LowVoltageLowRange as instead. */ + + kSPC_LowVoltageHighRange = 0x0U, /*!< High range LVD threshold. */ + kSPC_LowVoltageLowRange = 0x1U, /*!< Low range LVD threshold. */ +} spc_low_voltage_level_select_t; + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core. + */ +typedef enum _spc_vdd_core_glitch_ripple_counter_select +{ + kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ +} spc_vdd_core_glitch_ripple_counter_select_t; +#endif + +/*! + * @brief The list of the operating voltage for the SRAM's read/write timing margin. + */ +typedef enum _spc_sram_operate_voltage +{ + kSPC_sramOperateAt1P0V = 0x1U, /*!< SRAM configured for 1.0V operation. */ + kSPC_sramOperateAt1P1V = 0x2U, /*!< SRAM configured for 1.1V operation. */ + kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */ +} spc_sram_operate_voltage_t; + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief The configuration of VDD Core glitch detector. + */ +typedef struct _spc_vdd_core_glitch_detector_config +{ + spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */ + uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial + glitch is detected. */ + bool enableReset; /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */ + bool enableInterrupt; /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */ +} spc_vdd_core_glitch_detector_config_t; +#endif + +typedef struct _spc_sram_voltage_config +{ + spc_sram_operate_voltage_t operateVoltage; /*!< Specifies the operating voltage for the SRAM's + read/write timing margin. */ + bool requestVoltageUpdate; /*!< Used to control whether request an SRAM trim value change. */ +} spc_sram_voltage_config_t; + +/*! + * @brief Low Power Request output pin configuration. + */ +typedef struct _spc_lowpower_request_config +{ + bool enable; /*!< Low Power Request Output enable. */ + spc_lowpower_request_pin_polarity_t polarity; /*!< Low Power Request Output pin polarity select. */ + spc_lowpower_request_output_override_t override; /*!< Low Power Request Output Override. */ +} spc_lowpower_request_config_t; + +/*! + * @brief Core LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */ +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Active mode */ +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ +} spc_active_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_sys_ldo_option +{ + spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Active mode. */ +} spc_active_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Active mode. + */ +typedef struct _spc_active_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Active mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Active mode. */ +} spc_active_mode_dcdc_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief Core LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */ + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Low Power mode */ +} spc_lowpower_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_sys_ldo_option +{ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Low Power mode. */ +} spc_lowpower_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Low Power mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Low Power mode. */ +} spc_lowpower_mode_dcdc_option_t; + +/*! + * @brief DCDC Burst configuration. + * @deprecated Do not recommend to use this structure. + */ +typedef struct _spc_dcdc_burst_config +{ + bool sofwareBurstRequest; /*!< Enable/Disable DCDC Software Burst Request. */ + bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */ + bool stabilizeBurstFreq; /*!< Enable/Disable DCDC frequency stabilization. */ + uint8_t freq; /*!< The frequency of the current burst. */ +} spc_dcdc_burst_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief CORE/SYS/IO VDD Voltage Detect options. + */ +typedef struct _spc_voltage_detect_option +{ + bool HVDInterruptEnable; /*!< CORE/SYS/IO VDD High Voltage Detect interrupt enable. */ + bool HVDResetEnable; /*!< CORE/SYS/IO VDD High Voltage Detect reset enable. */ + bool LVDInterruptEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect interrupt enable. */ + bool LVDResetEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */ +} spc_voltage_detect_option_t; + +/*! + * @brief Core Voltage Detect configuration. + */ +typedef struct _spc_core_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< Core VDD Voltage Detect option. */ +} spc_core_voltage_detect_config_t; + +/*! + * @brief System Voltage Detect Configuration. + */ +typedef struct _spc_system_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< System VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< @deprecated, reserved for all devices, will removed in next release. */ +} spc_system_voltage_detect_config_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @brief IO Voltage Detect Configuration. + */ +typedef struct _spc_io_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< IO VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */ +} spc_io_voltage_detect_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @brief Active mode configuration. + */ +typedef struct _spc_active_mode_regulators_config +{ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_active_mode_sys_ldo_option_t SysLDOOption; /*!< Specify System LDO configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */ +} spc_active_mode_regulators_config_t; + +/*! + * @brief Low Power Mode configuration. + */ +typedef struct _spc_lowpower_mode_regulators_config +{ + bool lpIREF; /*!< Enable/disable low power IREF in low power modes. */ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_lowpower_mode_sys_ldo_option_t SysLDOOption; /*!< Specify system LDO configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */ +} spc_lowpower_mode_regulators_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name SPC Status + * @{ + */ +/*! + * @brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * @param base SPC peripheral base address. + * @return Current isolation status for each power domains. See @ref _spc_power_domains for details. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base); + +/*! + * @brief Clears peripherals and I/O pads isolation flags for each power domains. + * + * This function clears peripherals and I/O pads isolation flags for each power domains. + * After recovering from the POWERDOWN mode, user must invoke this function to release the + * I/O pads and certain peripherals to their normal run mode state. Before invoking this + * function, user must restore chip configuration in particular pin configuration for enabled + * WUU wakeup pins. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base) +{ + base->SC |= SPC_SC_ISO_CLR_MASK; +} + +/*! + * @brief Gets SPC busy status flag. + * + * This function gets SPC busy status flag. When SPC executing any type of power mode + * transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set + * and this function returns true. When changing CORE LDO voltage level and DCDC voltage level + * in ACTIVE mode, the SPC busy status flag is set and this function return true. + * + * @param base SPC peripheral base address. + * @return Ack busy flag. + * true - SPC is busy. + * false - SPC is not busy. + */ +static inline bool SPC_GetBusyStatusFlag(SPC_Type *base) +{ + return ((base->SC & SPC_SC_BUSY_MASK) != 0UL); +} + +/*! + * @brief Checks system low power request. + * + * @note Only when all power domains request low power mode entry, the result of this function is true. That means when + * all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register. + * + * @param base SPC peripheral base address. + * @return The system low power request check result. + * - \b true All power domains have requested low power mode and SPC has entered a low power state and power mode + * configuration are based on the LP_CFG configuration register. + * - \b false SPC in active mode and ACTIVE_CFG register control system power supply. + */ +static inline bool SPC_CheckLowPowerReqest(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SPC_LP_REQ_MASK) == SPC_SC_SPC_LP_REQ_MASK); +} + +/*! + * @brief Clears system low power request, set SPC in active mode. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearLowPowerRequest(SPC_Type *base) +{ + base->SC |= SPC_SC_SPC_LP_REQ_MASK; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) +/*! + * @brief Checks whether the power switch is on. + * + * @param base SPC peripheral base address. + * + * @retval true The power switch is on. + * @retval false The power switch is off. + */ +static inline bool SPC_CheckSwitchState(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL); +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */ + +/*! + * @brief Gets selected power domain's requested low power mode. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * + * @return The selected power domain's requested low power mode, please refer to @ref spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId); + +/*! + * @brief Checks power domain's low power request. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * @return The result of power domain's low power request. + * - \b true The selected power domain requests low power mode entry. + * - \b false The selected power domain does not request low power mode entry. + */ +static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) == + SPC_PD_STATUS_PWR_REQ_STATUS_MASK); +} + +/*! + * @brief Clears selected power domain's low power request flag. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + */ +static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK; +} + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) +/*! + * @name SRAM Retention LDO Control APIs + * @{ + */ + +/*! + * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V. + * + * @param base SPC peripheral base address. + * @param trimValue Reference voltage trim value. + */ +static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue) +{ + base->SRAMRETLDO_REFTRIM = + ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue)); +} + +/*! + * @brief Enables/disables SRAM retention LDO. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable SRAM LDO : + * - \b true Enable SRAM LDO; + * - \b false Disable SRAM LDO. + */ +static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable) +{ + if (enable) + { + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } + else + { + base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } +} + +/*! + * @brief + * + * @todo Need to check. + * + * @param base SPC peripheral base address. + * @param mask The OR'ed value of SRAM Array. + */ +static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask) +{ + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */ + +/*! + * @name Low Power Request configuration + * @{ + */ +/*! + * @brief Configs Low power request output pin. + * + * This function config the low power request output pin + * + * @param base SPC peripheral base address. + * @param config Pointer the @ref spc_lowpower_request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config); + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG) +/*! + * @name Integrated Power Switch Control APIs + * @{ + */ + +/*! + * @brief Enables/disables the integrated power switch manually. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable the integrated power switch: + * - \b true Enable the integrated power switch; + * - \b false Disable the integrated power switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } + else + { + base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } +} + +/*! + * @brief Enables/disables the integrated power switch automatically. + * + * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low + * power modes: + * @code + * SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true); + * @endcode + * + * @param base SPC peripheral base address. + * @param sleepGate Enable the integrated power switch when chip enter low power modes: + * - \b true SPC asserts an output pin at low-power entry to power-gate the switch; + * - \b false SPC does not assert an output pin at low-power entry to power-gate the switch. + * @param wakeupUngate Enables the switch after wake-up from low power modes: + * - \b true SPC asserts an output pin at low-power exit to power-ungate the switch; + * - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate) +{ + uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)); + + tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate); + + base->CFG = tmp32; +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @name VDD Core Glitch Detector Control APIs + * @{ + */ + +/*! + * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * @param base SPC peripheral base address. + * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config); + +/*! + * @brief Checks selected 4-bit glitch ripple counter's output. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + * + * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings. + * @retval false The selected ripple counter output is 0. + */ + +static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) == + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter))); +} + +/*! + * @brief Clears output of selected glitch ripple counter. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + */ +static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)); +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * + * @param base SPC peripheral base address. + * + * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable. + */ +static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif + +/*! + * @name SRAM Control APIs + * @{ + */ + +/*! + * @brief Set SRAM operate voltage. + * + * @param base SPC peripheral base address. + * @param config The pointer to @ref spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config); + +/*! @} */ + +/*! + * @name Active Mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Active mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_BGMODE_MASK) >> + SPC_ACTIVE_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets all voltage detectors status in Active mode. + * + * @param base SPC peripheral base address. + * @return All voltage detectors status in Active mode. + */ +static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->ACTIVE_CFG & + ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_ACTIVE_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Configs Bandgap mode in Active mode. + * + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configrue LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * @retval #kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disable the CMP Bandgap Buffer in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference voltage to CMP. + * false - Disable Buffer Stored Reference voltage to CMP. + */ +static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +/*! + * @brief Sets the delay when the regulators change voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles. + */ +static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay) +{ + base->ACTIVE_VDELAY = SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(delay); +} + +/*! + * @brief Configs all settings of regulators in Active mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_active_mode_regulators_config_t structure. + * + * @retval #kStatus_Success Config regulators in Active power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Based on input setting, bandgap can not be disabled. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage due to + * System VDD HVD is not disabled. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config); + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Disables/Enables VDD Core Glitch Detect in Active mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Check if Glitch detect hardware is enabled in active mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckActiveModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} + +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ + +/*! + * @brief Enables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 |= SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 &= ~SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in active mode. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in active mode. + */ +static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base) +{ + return base->ACTIVE_CFG1; +} + +/*! @} */ + +/*! + * @name Low Power mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Low Power mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_BGMODE_MASK) >> SPC_LP_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets the status of all voltage detectors in Low Power mode. + * + * @param base SPC peripheral base address. + * @return The status of all voltage detectors in low power mode. + */ +static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->LP_CFG & ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_LP_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Enables/Disables Low Power IREF in low power modes. + * + * This function enables/disables Low Power IREF. Low Power IREF can only get + * disabled in Deep power down mode. In other low power modes, the Low Power IREF + * is always enabled. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Low Power IREF. + * true - Enable Low Power IREF for Low Power modes. + * false - Disable Low Power IREF for Deep Power Down mode. + */ +static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LP_IREFEN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LP_IREFEN_MASK; + } +} + +/*! + * @brief Configs Bandgap mode in Low Power mode. + * + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) +/*! + * @brief Enables/disables SRAM_LDO deep power low power IREF. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable low power IREF : + * - \b true: Low Power IREF is enabled ; + * - \b false: Low Power IREF is disabled for power saving. + */ +static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @deprecated No longer used, please use SPC_EnableLowPowerModeCMPBandgapBuffer as instead. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} + +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @deprecated No longer used. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) +/*! + * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes. + * + * This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the + * external input CORE VDD to a lower voltage level to reduce internal leakage. + * IVS is invalid in Sleep or Deep power down mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IVS. + * true - enable CORE VDD IVS in Power Down mode. + * false - disable CORE VDD IVS in Power Down mode. + */ +static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +/*! + * @brief Sets the delay when exit the low power modes. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles that the SPC waits on exit from low power modes. + */ +static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay) +{ + base->LPWKUP_DELAY = SPC_LPWKUP_DELAY_LPWKUP_DELAY(delay); +} + +/*! + * @brief Configs all settings of regulators in Low power mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in low power mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * @retval #kStatus_Success Config regulators in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config); + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Disable/Enable VDD Core Glitch Detect in low power mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->LP_CFG |= SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Check if Glitch detect hardware is enabled in low power mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} +#endif + +/*! + * @brief Enables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 |= SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 &= ~SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in low power modes. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in low power modes. + */ +static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base) +{ + return base->LP_CFG1; +} + +/*! @} */ + +/*! + * @name Voltage Detect Status + * @{ + */ +/*! + * @brief Get Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base) +{ + return (uint8_t)(base->VD_STAT); +} + +/*! + * @brief Clear Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @param mask The mask of the voltage detect status flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask) +{ + base->VD_STAT |= mask; +} + +/*! @} */ + +/*! + * @name Voltage Detect configuration for Core voltage domain. + * @{ + */ + +/*! + * @brief Configs CORE voltage detect options. + * + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config); + +/*! + * @brief Locks Core voltage detect reset setting. + * + * This function locks core voltage detect reset setting. After invoking this function + * any configuration of Core voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG |= SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Unlocks Core voltage detect reset setting. + * + * This function unlocks core voltage detect reset setting. If locks the Core + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Active mode. + * + * @note If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode. + * + * This function enables/disables the Core Low Voltage Detector. + * If enabled the Core Low Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * @brief Enables/Disables the Core High Voltage Detector in Active mode. + * + * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core High Voltage Detector in Low Power mode. + * + * This function enables/disables the Core High Voltage Detector. + * If enabled the Core High Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in low power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! @} */ + +/*! + * @name Voltage detect configuration for System Voltage domain + * @{ + */ +/*! + * @brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * + * @param base SPC peripheral base address. + * @param level System VDD Low-Voltage level selection. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs SYS voltage detect options. + * + * This function config SYS voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config); + +/*! + * @brief Lock System voltage detect reset setting. + * + * This function locks system voltage detect reset setting. After invoking this function + * any configuration of System Voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG |= SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock System voltage detect reset setting. + * + * This function unlocks system voltage detect reset setting. If locks the System + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG &= ~SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the System High Voltage Detector in Active mode. + * + * @note If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disable the System Low Voltage Detector in Active mode. + * + * @note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System High Voltage Detector in Low Power mode. + * + * @note If the System_LDO high voltage detect is enabled in Low Power mode, please note + * that the bandgap must be enabled and the drive strength of each regulator must + * not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System Low Voltage Detector in Low Power mode. + * + * @note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enables System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @name Voltage detect configuration for IO voltage domain + * @{ + */ +/*! + * @brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * @param base SPC peripheral base address. + * @param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs IO voltage detect options. + * + * This function config IO voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config); + +/*! + * @brief Lock IO Voltage detect reset setting. + * + * This function locks IO voltage detect reset setting. After invoking this function + * any configuration of system voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG |= SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock IO voltage detect reset setting. + * + * This function unlocks IO voltage detect reset setting. If locks the IO + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG &= ~SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Active mode. + * + * @note If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Active mode. + * + * @note If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Low Power mode. + * + * @note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Low Power mode. + * + * @note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! @} */ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @name External Voltage domains configuration + * @{ + */ +/*! + * @brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * @param base SPC peripheral base address. + * @param lowPowerIsoMask The mask of external domains isolate enable during low power mode. Please read the Reference + * Manual for the Bitmap. + * @param IsoMask The mask of external domains isolate. Please read the Reference Manual for the Bitmap. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask); + +/*! + * @brief Gets External Domains status. + * + * @param base SPC peripheral base address. + * @return The status of each external domain. + */ +static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base) +{ + return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); +} + +/*! @} */ + +/*! + * @name Low Level APIs To Set CORE LDO Regulator + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) +/*! + * @brief Enable/Disable Core LDO regulator. + * + * @note The CORE LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CORE LDO Regulator. + * true - Enable CORE LDO Regulator. + * false - Disable CORE LDO Regulator. + */ +static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_CORELDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If CORE_LDO is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && \ + FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) +/*! + * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down. + * + * @note This function only useful when enabled the CORE LDO Regulator. + * + * @param base SPC peripheral base address. + * @param pulldown Enable/Disable CORE LDO pulldown in Deep Power Down mode. + * true - CORE LDO Regulator will discharge in Deep Power Down mode. + * false - CORE LDO Regulator will not discharge in Deep Power Down mode. + */ +static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown) +{ + if (pulldown) + { + base->CORELDO_CFG &= ~SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } + else + { + base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */ + +/*! + * @brief Configs Core LDO Regulator in Active mode. + * + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_core_ldo_option_t structure. + * + * @retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * @retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * @retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO Regulator Voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * @retval kStatus_SPC_CORELDOVoltageSetFail The drive strength of Core LDO is not normal. + * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets CORE LDO Regulator Voltage level. + * + * This function returns the voltage level of CORE LDO Regulator in Active mode. + * + * @param base SPC peripheral base address. + * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT); +} + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT); +} +#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * @brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength set as Normal. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_core_ldo_option_t structure. + * + * @retval #kStatus_Success Config Core LDO regulator in power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * @param base SPC peripheral base address. + * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO VDD Regulator's voltage level. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Drive Strength for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO's VDD Drive Strength. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >> + SPC_LP_CFG_CORELDO_VDD_DS_SHIFT); +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @name Low Level APIs To Set System LDO Regulator + * @{ + */ + +/*! + * @brief Enable/Disable System LDO regulator. + * + * @note The SYSTEM LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LDO Regulator. + * true - Enable System LDO Regulator. + * false - Disable System LDO Regulator. + */ +static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_SYSLDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If SYSTEM_LDO is disabled, may cause some unexpected issues. + */ + base->CNTRL &= ~SPC_CNTRL_SYSLDO_EN_MASK; + } +} + +/*! + * @brief Enable/Disable current sink feature of System LDO Regulator. + * + * @param base SPC peripheral base address. + * @param sink Enable/Disable current sink feature. + * true - Enable current sink feature of System LDO Regulator. + * false - Disable current sink feature of System LDO Regulator. + */ +static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink) +{ + if (sink) + { + base->SYSLDO_CFG |= SPC_SYSLDO_CFG_ISINKEN_MASK; + } + else + { + base->SYSLDO_CFG &= ~SPC_SYSLDO_CFG_ISINKEN_MASK; + } +} + +/*! + * @brief Configs System LDO VDD Regulator in Active mode. + * + * @note If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enables the bandgap. + * @note If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be + * disabled. Otherwise it will be fail to regulator to Over Drive Voltage. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive + * voltage. + * @retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Get System LDO Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t. + */ +static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT); +} + +/*! + * @brief Set System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT); +} + +/*! + * @brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * @param base SPC peripheral base address. + * @param option Pointer to spc_lowpower_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT); +} +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @name Low Level APIs To Set DCDC Regulator + * @{ + */ + +/*! + * @brief Enable/Disable DCDC Regulator. + * + * @note The DCDC enable bit is write-once, settings only reset after a POR, LVD, or HVD event. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable DCDC Regulator. + * true - Enable DCDC Regulator. + * false - Disable DCDC Regulator. + */ +static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_DCDC_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If DCDC is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_DCDC_EN_MASK; + } +} + +/*! + * @brief Config DCDC Burst options + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_dcdc_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config); + +/*! + * @brief Trigger a software burst request to DCDC. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_TriggerDCDCBurstRequest(SPC_Type *base) +{ + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; +} + +/*! + * @brief Check if burst acknowlege flag is asserted. + * + * @param base SPC peripheral base address. + * + * @retval false DCDC burst not complete. + * @retval true DCDC burst complete. + */ +static inline bool SPC_CheckDCDCBurstAck(SPC_Type *base) +{ + return ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0UL); +} + +/*! + * @brief Clear DCDC busrt acknowledge flag. + * + * @param base SPC periphral base address. + */ +static inline void SPC_ClearDCDCBurstAckFlag(SPC_Type *base) +{ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; +} + +/*! + * @brief Set the count value of the reference clock to configure the period of DCDC not active. + * + * @note This function is only useful when DCDC's drive strength is set as pulse refresh. + * @note The pulse duration(time between on and off) is: reference clock period * (count + 2). + * + * @param base SPC peripheral base address. + * @param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) && FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) +/*! + * @brief Enable a bleed resistor to discharge DCDC output when DCDC is disabled. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable bleed resistor. + */ +static inline void SPC_EnableDCDCBleedResistor(SPC_Type *base, bool enable) +{ + if (enable) + { + base->DCDC_CFG |= SPC_DCDC_CFG_BLEED_EN_MASK; + } + else + { + base->DCDC_CFG &= ~SPC_DCDC_CFG_BLEED_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN */ + +/*! + * @brief Configs DCDC_CORE Regulator in Active mode. + * + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC_CORE Regulator voltage level in Active mode. + * + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = + (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator drive strength in Active mode. + * + * @note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Configs DCDC_CORE Regulator in Low power modes. + * + * @note If DCDC_CORE Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * @note In Deep Power Down mode, DCDC regulator is always turned off. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in low power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC_CORE Regulator drive strength in Low power mode. + * + * @note To set drive strength as normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Low power mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >> + SPC_LP_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator voltage level in Low power mode. + * + * @note To change DCDC level in Low-Power mode: + * 1. Configure LP_CFG[DCDC_VDD_LVL] to desired level; + * 2. Configure LP_CFG[DCDC_VDD_DS] to low driver strength; + * 3. Configure ACTIVE_CFG[DCDC_VDD_LVL] to same level programmed in #1. + * + * @note After invoking this function, the voltage level in active mode(wakeup from low power modes) also changed, + * if it is necessary, please invoke SPC_SetActiveModeDCDCRegulatorVoltageLevel() to change to desried voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel); + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, kSPC_DCDC_LowDriveStrength); + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >> + SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* FSL_SPC_H_ */ diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index 2b9c60beb..2dfefeb92 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -60,9 +60,14 @@ void USB0_IRQHandler(void) { void board_init(void) { + BOARD_InitPins(); + BOARD_InitBootClocks(); + + #ifdef XTAL0_CLK_HZ CLOCK_SetupExtClocking(XTAL0_CLK_HZ); + #endif #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -84,15 +89,7 @@ void board_init(void) { board_led_write(0); #ifdef NEOPIXEL_PIN - // Neopixel - static uint32_t pixelData[NEOPIXEL_NUMBER]; - IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN); - - sctpix_init(NEOPIXEL_TYPE); - sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER); - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010); - sctpix_show(); + // No neo pixel support yet #endif // Button @@ -103,9 +100,6 @@ void board_init(void) { #endif #ifdef UART_DEV - // UART -// IOCON_PinMuxSet(IOCON, UART_RX_PINMUX); -// IOCON_PinMuxSet(IOCON, UART_TX_PINMUX); // Enable UART when debug log is on board_uart_init_clock(); @@ -115,6 +109,7 @@ void board_init(void) { uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE; uart_config.enableTx = true; uart_config.enableRx = true; + LPUART_Init(UART_DEV, &uart_config, 12000000u); #endif @@ -196,17 +191,6 @@ void board_init(void) { void board_led_write(bool state) { GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); - -#ifdef NEOPIXEL_PIN - if (state) { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010); - } else { - sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000); - sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010); - } - sctpix_show(); -#endif } uint32_t board_button_read(void) { diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 413c1b372..305497b79 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -10,6 +10,9 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) if (MCU_VARIANT STREQUAL "MCXA153") set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor") set(FAMILY_MCUS MCXA15 CACHE INTERNAL "") +elseif (MCU_VARIANT STREQUAL "MCXA156") + set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") + set(FAMILY_MCUS MCXA15 CACHE INTERNAL "") elseif (MCU_VARIANT STREQUAL "MCXN947") set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(FAMILY_MCUS MCXN9 CACHE INTERNAL "") @@ -38,12 +41,14 @@ function(add_board_target BOARD_TARGET) endif() set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + add_library(${BOARD_TARGET} STATIC ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} # driver - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c + ${SDK_DIR}/drivers/gpio/fsl_gpio.c + ${SDK_DIR}/drivers/common/fsl_common_arm.c + ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc/fsl_spc.c # mcu ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c @@ -51,18 +56,27 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMSIS_DIR}/CMSIS/Core/Include + ${SDK_DIR}/drivers/gpio/ + ${SDK_DIR}/drivers/lpuart + ${SDK_DIR}/drivers/common + ${SDK_DIR}/drivers/port + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/drivers/spc ${SDK_DIR}/devices/${MCU_VARIANT} ${SDK_DIR}/devices/${MCU_VARIANT}/drivers ) if (${FAMILY_MCUS} STREQUAL "MCXN9") + target_sources(${BOARD_TARGET} PRIVATE - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c + ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c + ) + + target_include_directories(${BOARD_TARGET} PUBLIC + ${SDK_DIR}/drivers/lpflexcomm ) elseif(${FAMILY_MCUS} STREQUAL "MCXA15") - target_sources(${BOARD_TARGET} PRIVATE - ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_spc.c - ) + + endif() update_board(${BOARD_TARGET}) diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk index 58149fb8d..676475cc9 100644 --- a/hw/bsp/mcx/family.mk +++ b/hw/bsp/mcx/family.mk @@ -35,18 +35,19 @@ SRC_C += \ $(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \ $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \ - $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \ + ${SDK_DIR}/drivers/gpio/fsl_gpio.c \ + ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \ + ${SDK_DIR}/drivers/common/fsl_common_arm.c\ + hw/bsp/mcx/drivers/spc/fsl_spc.c # fsl_lpflexcomm for MCXN9 ifeq ($(MCU_VARIANT), MCXN947) - SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c + SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c endif # fsl_spc for MCXNA15 ifeq ($(MCU_VARIANT), MCXA153) - SRC_C += $(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_spc.c + endif INC += \ @@ -54,5 +55,15 @@ INC += \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \ $(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \ + $(TOP)/$(SDK_DIR)/drivers/ \ + $(TOP)/$(SDK_DIR)/drivers/lpuart \ + $(TOP)/$(SDK_DIR)/drivers/lpflexcomm \ + $(TOP)/$(SDK_DIR)/drivers/common\ + $(TOP)/$(SDK_DIR)/drivers/gpio\ + $(TOP)/$(SDK_DIR)/drivers/port\ + $(TOP)/hw/bsp/mcx/drivers/spc + + + SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/tools/get_deps.py b/tools/get_deps.py index ba9dc23ce..f5164f31c 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -55,8 +55,8 @@ deps_optional = { 'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git', 'b41cf930e65c734d8ec6de04f1d57d46787c76ae', 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'], - 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', - '144f1eb7ea8c06512e12f12b27383601c0272410', + 'hw/mcu/nxp/mcux-sdk': ['https://github.com/nxp-mcuxpresso/mcux-sdk', + 'a1bdae309a14ec95a4f64a96d3315a4f89c397c6', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', '810653f66adadba3e0e4b4b56d5167ac4f7fdbf7', @@ -243,11 +243,13 @@ def get_a_dep(d): p.mkdir(parents=True) run_cmd(f"{git_cmd} init") run_cmd(f"{git_cmd} remote add origin {url}") + head = None + else: + # Check if commit is already fetched + result = run_cmd(f"{git_cmd} rev-parse HEAD") + head = result.stdout.decode("utf-8").splitlines()[0] + run_cmd(f"{git_cmd} reset --hard") - # Check if commit is already fetched - result = run_cmd(f"{git_cmd} rev-parse HEAD") - head = result.stdout.decode("utf-8").splitlines()[0] - run_cmd(f"{git_cmd} reset --hard") if commit != head: run_cmd(f"{git_cmd} fetch --depth 1 origin {commit}") run_cmd(f"{git_cmd} checkout FETCH_HEAD") -- cgit v1.3.1 From ed087b9ed83814e81d303c956de1541e9a82bb47 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 13 May 2025 16:13:50 +0700 Subject: pump up pico-pio-usb and cmsis_device_wb --- tools/get_deps.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index d89c1b2b1..1f46a8e05 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -59,7 +59,7 @@ deps_optional = { '144f1eb7ea8c06512e12f12b27383601c0272410', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', - '810653f66adadba3e0e4b4b56d5167ac4f7fdbf7', + 'd15f0c62ac22348a8708e1626525fdba9466e1ee', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', @@ -122,7 +122,7 @@ deps_optional = { '5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309', 'stm32u5'], 'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git', - '9c5d1920dd9fabbe2548e10561d63db829bb744f', + 'd6a7fa2e7de084f5e5e47f2ab88b022fe9b50e5a', 'stm32wb'], 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', '7f4389efee9c6a655b55e5df3fceef5586b35f9b', -- cgit v1.3.1 From 38e5a67461cf7c819e845a110ef67184c2becbe4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 May 2025 10:27:00 +0700 Subject: bump up pio-usb and codeql version --- .github/workflows/codeql.yml | 6 +++--- tools/get_deps.py | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index be4c2dd87..a22c65c79 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -66,7 +66,7 @@ jobs: # Initializes the CodeQL tools for scanning. - name: Initialize CodeQL - uses: github/codeql-action/init@v2 + uses: github/codeql-action/init@v3 with: languages: ${{ matrix.language }} # If you wish to specify custom queries, you can do so here or in a config file. @@ -93,7 +93,7 @@ jobs: ./.github/workflows/codeql-buildscript.sh - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v2 + uses: github/codeql-action/analyze@v3 with: category: "/language:${{matrix.language}}" upload: false @@ -129,7 +129,7 @@ jobs: sarif_file: ${{ steps.step1.outputs.sarif-output }} category: "/language:${{matrix.language}}" - - name: Archive CodeQL results + - name: Upload CodeQL results as an artifact uses: actions/upload-artifact@v4 with: name: codeql-results diff --git a/tools/get_deps.py b/tools/get_deps.py index 1f46a8e05..df8dbb6e1 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -59,7 +59,7 @@ deps_optional = { '144f1eb7ea8c06512e12f12b27383601c0272410', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', - 'd15f0c62ac22348a8708e1626525fdba9466e1ee', + '032a469e79f6a4ba40760d7868e6db26e15002d7', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', -- cgit v1.3.1 From bffe5d97cc2f4f5a9ba8b4f09d30be97ce70a3de Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 19 May 2025 20:22:29 +0700 Subject: limit hil-hfp iar build to 4 parallel jobs --- .github/workflows/build.yml | 2 +- tools/build.py | 12 ++++++++++-- 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 28447cc80..fe2ed61c9 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -266,7 +266,7 @@ jobs: run: python3 tools/get_deps.py $BUILD_ARGS - name: Build - run: python3 tools/build.py --toolchain iar $BUILD_ARGS + run: python3 tools/build.py -j 4 --toolchain iar $BUILD_ARGS - name: Test on actual hardware (hardware in the loop) run: python3 test/hil/hil_test.py hfp.json diff --git a/tools/build.py b/tools/build.py index d28ddd929..f2f6e6228 100755 --- a/tools/build.py +++ b/tools/build.py @@ -23,6 +23,7 @@ build_separator = '-' * 95 build_status = [STATUS_OK, STATUS_FAILED, STATUS_SKIPPED] verbose = False +parallel_jobs = os.cpu_count() # ----------------------------- # Helper @@ -110,13 +111,17 @@ def cmake_board(board, toolchain, build_flags_on): f'-DTOOLCHAIN={toolchain} {build_flags}') if rcmd.returncode == 0: cmd = f"cmake --build {build_dir}" - # circleci docker return $nproc as 36 core, limit parallel according to resource class. Required for IAR, also prevent crashed/killed by docker + njobs = parallel_jobs + + # circleci docker return $nproc as 36 core, limit parallel according to resource class. + # Required for IAR, also prevent crashed/killed by docker if os.getenv('CIRCLECI'): resource_class = { 'small': 1, 'medium': 2, 'medium+': 3, 'large': 4 } for rc in resource_class: if rc in os.getenv('CIRCLE_JOB'): - cmd += f' --parallel {resource_class[rc]}' + njobs = resource_class[rc] break + cmd += f' --parallel {njobs}' rcmd = run_cmd(cmd) ret[0 if rcmd.returncode == 0 else 1] += 1 @@ -211,6 +216,7 @@ def build_family(family, toolchain, build_system, build_flags_on, one_per_family # ----------------------------- def main(): global verbose + global parallel_jobs parser = argparse.ArgumentParser() parser.add_argument('families', nargs='*', default=[], help='Families to build') @@ -219,6 +225,7 @@ def main(): parser.add_argument('-s', '--build-system', default='cmake', help='Build system to use, default is cmake') parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Build flag to pass to build system') parser.add_argument('-1', '--one-per-family', action='store_true', default=False, help='Build only one random board inside a family') + parser.add_argument('-j', '--jobs', type=int, default=os.cpu_count(), help='Number of jobs to run in parallel') parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output') args = parser.parse_args() @@ -229,6 +236,7 @@ def main(): build_flags_on = args.build_flags_on one_per_family = args.one_per_family verbose = args.verbose + parallel_jobs = args.jobs if len(families) == 0 and len(boards) == 0: print("Please specify families or board to build") -- cgit v1.3.1 From 132c55aca0aa9bb68b4ffb96ec89947e08e19b88 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 28 May 2025 08:38:26 +0700 Subject: add OPT_MCU_MAX32665 --- .github/workflows/codeql.yml | 2 +- src/CMakeLists.txt | 5 +---- src/tusb_option.h | 1 + tools/build.py | 4 ++-- 4 files changed, 5 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index a22c65c79..dfcca6315 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -124,7 +124,7 @@ jobs: output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - name: Upload SARIF - uses: github/codeql-action/upload-sarif@v2 + uses: github/codeql-action/upload-sarif@v3 with: sarif_file: ${{ steps.step1.outputs.sarif-output }} category: "/language:${{matrix.language}}" diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 55c52033c..99d3059fc 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -1,9 +1,6 @@ -# TODO more docs and example on how to use this file -# TINYUSB_TARGET_PREFIX and TINYUSB_TARGET_SUFFIX can be used to change the name of the target - cmake_minimum_required(VERSION 3.20) -# Add tinyusb to a existing target +# Add tinyusb to a existing target, DCD and HCD drivers are not included function(tinyusb_target_add TARGET) target_sources(${TARGET} PRIVATE # common diff --git a/src/tusb_option.h b/src/tusb_option.h index 6d733a429..104f669c9 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -195,6 +195,7 @@ // Analog Devices #define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 +#define OPT_MCU_MAX32665 2401 ///< ADI MAX32666/5 #define OPT_MCU_MAX32666 2401 ///< ADI MAX32666/5 #define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2 #define OPT_MCU_MAX78002 2403 ///< ADI MAX78002 diff --git a/tools/build.py b/tools/build.py index f2f6e6228..6e73681fe 100755 --- a/tools/build.py +++ b/tools/build.py @@ -101,13 +101,13 @@ def cmake_board(board, toolchain, build_flags_on): if build_utils.skip_example(example, board): ret[2] += 1 else: - rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" ' + rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G Ninja ' f'-DBOARD={board} {build_flags}') if rcmd.returncode == 0: rcmd = run_cmd(f'cmake --build {build_dir}/{example}') ret[0 if rcmd.returncode == 0 else 1] += 1 else: - rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel ' + rcmd = run_cmd(f'cmake examples -B {build_dir} -G Ninja -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel ' f'-DTOOLCHAIN={toolchain} {build_flags}') if rcmd.returncode == 0: cmd = f"cmake --build {build_dir}" -- cgit v1.3.1 From 56c9521abdef663b455a345c99a4f6b22591aa56 Mon Sep 17 00:00:00 2001 From: James Sandison Date: Wed, 4 Jun 2025 11:21:27 +1000 Subject: chore: squash previous commits from other branches --- docs/reference/boards.rst | 2 + docs/reference/dependencies.rst | 1 + examples/build_system/cmake/cpu/cortex-m55.cmake | 26 + examples/build_system/make/cpu/cortex-m55.mk | 28 + examples/device/net_lwip_webserver/skip.txt | 1 + examples/host/bare_api/only.txt | 1 + examples/host/cdc_msc_hid/only.txt | 1 + examples/host/cdc_msc_hid_freertos/only.txt | 1 + examples/host/device_info/only.txt | 1 + examples/host/hid_controller/only.txt | 1 + examples/host/midi_rx/only.txt | 1 + examples/host/msc_file_explorer/only.txt | 1 + hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h | 149 ++ .../stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld | 203 +++ hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake | 25 + hw/bsp/stm32n6/boards/stm32n657nucleo/board.h | 283 ++++ hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk | 23 + .../boards/stm32n657nucleo/tcpp0203/LICENSE.txt | 6 + .../stm32n657nucleo/tcpp0203/Release_Notes.html | 205 +++ .../stm32n657nucleo/tcpp0203/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../tcpp0203/_htmresc/mini-st_2020.css | 1703 ++++++++++++++++++++ .../tcpp0203/_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../boards/stm32n657nucleo/tcpp0203/tcpp0203.c | 886 ++++++++++ .../boards/stm32n657nucleo/tcpp0203/tcpp0203.h | 353 ++++ .../boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c | 73 + .../boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h | 98 ++ hw/bsp/stm32n6/family.c | 276 ++++ hw/bsp/stm32n6/family.cmake | 147 ++ hw/bsp/stm32n6/family.mk | 101 ++ hw/bsp/stm32n6/partition_stm32n657xx.h | 792 +++++++++ hw/bsp/stm32n6/stm32n6xx_hal_conf.h | 504 ++++++ hw/bsp/zephyr_board_aliases.cmake | 1 + src/common/tusb_mcu.h | 9 + src/portable/synopsys/dwc2/dcd_dwc2.c | 5 + src/portable/synopsys/dwc2/dwc2_info.py | 1 + src/portable/synopsys/dwc2/dwc2_stm32.h | 11 + src/portable/synopsys/dwc2/hcd_dwc2.c | 4 + src/tusb_option.h | 1 + tools/get_deps.py | 8 +- 39 files changed, 5931 insertions(+), 1 deletion(-) create mode 100644 examples/build_system/cmake/cpu/cortex-m55.cmake create mode 100644 examples/build_system/make/cpu/cortex-m55.mk create mode 100644 hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/board.h create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h create mode 100644 hw/bsp/stm32n6/family.c create mode 100644 hw/bsp/stm32n6/family.cmake create mode 100644 hw/bsp/stm32n6/family.mk create mode 100644 hw/bsp/stm32n6/partition_stm32n657xx.h create mode 100644 hw/bsp/stm32n6/stm32n6xx_hal_conf.h (limited to 'tools') diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst index 5786b2182..317a40c9c 100644 --- a/docs/reference/boards.rst +++ b/docs/reference/boards.rst @@ -269,6 +269,8 @@ stm32l412nucleo STM32 L412 Nucleo stm32l4 https://www.st stm32l476disco STM32 L476 Disco stm32l4 https://www.st.com/en/evaluation-tools/32l476gdiscovery.html stm32l4p5nucleo STM32 L4P5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html stm32l4r5nucleo STM32 L4R5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html +stm32n657_dk STM32 N657 Discovery Kit stm32n6 https://www.st.com/en/evaluation-tools/stm32n6570-dk.html +stm32n657nucleo STM32 N657 Nucleo stm32n6 https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html b_u585i_iot2a STM32 B-U585i IOT2A Discovery kit stm32u5 https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html stm32u545nucleo STM32 U545 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html stm32u575eval STM32 U575 Eval stm32u5 https://www.st.com/en/evaluation-tools/stm32u575i-ev.html diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst index e124466da..98545b4cf 100644 --- a/docs/reference/dependencies.rst +++ b/docs/reference/dependencies.rst @@ -57,6 +57,7 @@ hw/mcu/st/stm32l0xx_hal_driver https://github.com/STMicroelectronics/ hw/mcu/st/stm32l1xx_hal_driver https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git 44efc446fa69ed8344e7fd966e68ed11043b35d9 stm32l1 hw/mcu/st/stm32l4xx_hal_driver https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git aee3d5bf283ae5df87532b781bdd01b7caf256fc stm32l4 hw/mcu/st/stm32l5xx_hal_driver https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git 675c32a75df37f39d50d61f51cb0dcf53f07e1cb stm32l5 +hw/mcu/st/stm32n6xx_hal_driver https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git 49f9989d10cf6817d4b07ac01848956b46bd0fd6 stm32n6 hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git 4d93097a67928e9377e655ddd14622adc31b9770 stm32u5 hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8 stm32wb hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 msp430 msp432e4 tm4c diff --git a/examples/build_system/cmake/cpu/cortex-m55.cmake b/examples/build_system/cmake/cpu/cortex-m55.cmake new file mode 100644 index 000000000..a7a57957c --- /dev/null +++ b/examples/build_system/cmake/cpu/cortex-m55.cmake @@ -0,0 +1,26 @@ +if (TOOLCHAIN STREQUAL "gcc") + set(TOOLCHAIN_COMMON_FLAGS + -mthumb + -mcpu=cortex-m55 + -mfloat-abi=hard + -mfpu=fpv5-d16 + -mcmse + ) + set(FREERTOS_PORT GCC_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "") + +elseif (TOOLCHAIN STREQUAL "clang") + set(TOOLCHAIN_COMMON_FLAGS + --target=arm-none-eabi + -mcpu=cortex-m55 + -mfpu=fpv5-d16 + ) + set(FREERTOS_PORT GCC_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "") + +elseif (TOOLCHAIN STREQUAL "iar") + set(TOOLCHAIN_COMMON_FLAGS + --cpu cortex-m55 + --fpu VFPv5_D16 + ) + set(FREERTOS_PORT IAR_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "") + +endif () diff --git a/examples/build_system/make/cpu/cortex-m55.mk b/examples/build_system/make/cpu/cortex-m55.mk new file mode 100644 index 000000000..de627caed --- /dev/null +++ b/examples/build_system/make/cpu/cortex-m55.mk @@ -0,0 +1,28 @@ +ifeq ($(TOOLCHAIN),gcc) + CFLAGS += \ + -mthumb \ + -mcpu=cortex-m55 \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mcmse + +else ifeq ($(TOOLCHAIN),clang) + CFLAGS += \ + --target=arm-none-eabi \ + -mcpu=cortex-m55 \ + -mfpu=fpv5-d16 \ + +else ifeq ($(TOOLCHAIN),iar) + CFLAGS += \ + --cpu cortex-m55 \ + --fpu VFPv5_D16 \ + + ASFLAGS += \ + --cpu cortex-m55 \ + --fpu VFPv5_D16 \ + +else + $(error "TOOLCHAIN is not supported") +endif + +FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM55_NTZ/non_secure diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt index 5ebe71612..c2e0d54ec 100644 --- a/examples/device/net_lwip_webserver/skip.txt +++ b/examples/device/net_lwip_webserver/skip.txt @@ -10,6 +10,7 @@ mcu:SAMD11 mcu:STM32L0 mcu:STM32F0 mcu:KINETIS_KL +mcu:STM32N6 family:broadcom_64bit family:broadcom_32bit family:espressif diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index e3ae25260..4ff3841a4 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -13,3 +13,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index b6f87f423..6e6e2184f 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -18,3 +18,4 @@ mcu:RAXXX mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/midi_rx/only.txt b/examples/host/midi_rx/only.txt index b6f87f423..6e6e2184f 100644 --- a/examples/host/midi_rx/only.txt +++ b/examples/host/midi_rx/only.txt @@ -18,3 +18,4 @@ mcu:RAXXX mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..9fd3f6c50 --- /dev/null +++ b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "stm32h7rsxx.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 4 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake new file mode 100644 index 000000000..197b5108f --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake @@ -0,0 +1,25 @@ +set(MCU_VARIANT stm32n657xx) +set(JLINK_DEVICE stm32n6xx) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_LRUN.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + STM32N6xx + SEGGER_RTT_SECTION="noncacheable_buffer" + BUFFER_SIZE_UP=0x3000 + ) + + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203_reg.c + ) + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203 + ) +endfunction() diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h new file mode 100644 index 000000000..d3781c6d0 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h @@ -0,0 +1,283 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: STM32 H723 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h723zg.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32n657xx.h" +#include "stm32n6xx_ll_exti.h" +#include "stm32n6xx_ll_system.h" +#include "tcpp0203.h" + +#define UART_DEV USART1 +#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE + +#define BOARD_TUD_RHPORT 1 + +// VBUS Sense detection +#define OTG_FS_VBUS_SENSE 1 +#define OTG_HS_VBUS_SENSE 1 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_TCPP0203_EN 4 + +static board_pindef_t board_pindef[] = { + {// LED + .port = GPIOG, + .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 1}, + {// Button + .port = GPIOC, + .pin_init = {.Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 1}, + {// UART TX + .port = GPIOE, + .pin_init = {.Pin = GPIO_PIN_5, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1}, + .active_state = 0}, + {// UART RX + .port = GPIOE, + .pin_init = {.Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1}, + .active_state = 0}, + {// VBUS input pin used for TCPP0203 EN + .port = GPIOA, + .pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 0}, + { + // I2C SCL for TCPP0203 + .port = GPIOB, + .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2}, + }, + { + // I2C SDA for TCPP0203 + .port = GPIOB, + .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2}, + }, + { + // INT for TCPP0203 + .port = GPIOD, + .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + }, +}; + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + /* Configure the power domain */ + if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) { + Error_Handler(); + } + + /* Get current CPU/System buses clocks configuration */ + /* and if necessary switch to intermediate HSI clock */ + /* to ensure target clock can be set */ + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct); + if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) || + (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) { + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { + Error_Handler(); + } + } + + /* HSE selected as source (stable clock on Level 0 samples */ + /* PLL1 output = ((HSE/PLLM)*PLLN)/PLLP1/PLLP2 */ + /* = ((48000000/3)*75)/1/1 */ + /* = (16000000*75)/1/1 */ + /* = 1200000000 (1200 MHz) */ + /* PLL2 off */ + /* PLL3 off */ + /* PLL4 off */ + + /* Enable HSE && HSI */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 48 MHz */ + + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL1.PLLM = 3; + RCC_OscInitStruct.PLL1.PLLN = 75; /* PLL1 VCO = 48/3 * 75 = 1200MHz */ + RCC_OscInitStruct.PLL1.PLLP1 = 1; /* PLL output = PLL VCO frequency / (PLLP1 * PLLP2) */ + RCC_OscInitStruct.PLL1.PLLP2 = 1; /* PLL output = 1200 MHz */ + RCC_OscInitStruct.PLL1.PLLFractional = 0; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + /* Initialization error */ + Error_Handler(); + } + + /* Select PLL1 outputs as CPU and System bus clock source */ + /* CPUCLK = ic1_ck = PLL1 output/ic1_divider = 600 MHz */ + /* SYSCLK = ic2_ck = PLL1 output/ic2_divider = 400 MHz */ + /* Configure the HCLK clock divider */ + /* HCLK = PLL1 SYSCLK/HCLK divider = 200 MHz */ + /* PCLKx = HCLK / PCLKx divider = 200 MHz */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1; + RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC1Selection.ClockDivider = 2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11; + RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC2Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC6Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC11Selection.ClockDivider = 3; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1; + PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } + + /** Set USB OTG HS PHY1 Reference Clock Source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1; + PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } +} + +//--------------------------------------------------------------------+ +// USB PD +//--------------------------------------------------------------------+ +static I2C_HandleTypeDef i2c_handle = { + .Instance = I2C2, + .Init = { + .Timing = 0x20C0EDFF, + .OwnAddress1 = 0, + .AddressingMode = I2C_ADDRESSINGMODE_7BIT, + .DualAddressMode = I2C_DUALADDRESS_DISABLE, + .OwnAddress2 = 0, + .OwnAddress2Masks = I2C_OA2_NOMASK, + .GeneralCallMode = I2C_GENERALCALL_DISABLE, + .NoStretchMode = I2C_NOSTRETCH_DISABLE, + }}; +static TCPP0203_Object_t tcpp0203_obj = {0}; + +int32_t board_tcpp0203_init(void) { + board_pindef_t *pindef = &board_pindef[PINID_TCPP0203_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET); + + __HAL_RCC_I2C2_CLK_ENABLE(); + __HAL_RCC_I2C2_FORCE_RESET(); + __HAL_RCC_I2C2_RELEASE_RESET(); + if (HAL_I2C_Init(&i2c_handle) != HAL_OK) { + return HAL_ERROR; + } + + NVIC_SetPriority(EXTI8_IRQn, 12); + NVIC_EnableIRQ(EXTI8_IRQn); + + return 0; +} + +int32_t board_tcpp0203_deinit(void) { + return 0; +} + +int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +static inline void board_init2(void) { + TCPP0203_IO_t io_ctx; + + io_ctx.Address = TCPP0203_I2C_ADDRESS_X68; + io_ctx.Init = board_tcpp0203_init; + io_ctx.DeInit = board_tcpp0203_deinit; + io_ctx.ReadReg = i2c_readreg; + io_ctx.WriteReg = i2c_writereg; + + TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); +} + +void board_vbus_set(uint8_t rhport, bool state) { + (void) state; + if (rhport == 1) { + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +void EXTI8_IRQHandler(void) { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8); + if (tcpp0203_obj.IsInitialized) { + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk new file mode 100644 index 000000000..b851da0ca --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk @@ -0,0 +1,23 @@ +MCU_VARIANT = stm32n6xx +CFLAGS += -DSTM32N6xx + +# For flash-jlink target +JLINK_DEVICE = stm32n6xx + +# flash target using on-board stlink +flash: flash-stlink + +PORT = 1 + + +SRC_C += \ + $(BOARD_PATH)/tcpp0203/tcpp0203.c \ + $(BOARD_PATH)/tcpp0203/tcpp0203_reg.c \ + +INC += \ + $(TOP)/$(BOARD_PATH)/tcpp0203 \ + +CFLAGS += \ + -DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \ + -DSTM32N657xx + -DBUFFER_SIZE_UP=0x3000 \ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt new file mode 100644 index 000000000..1cbbc544a --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html new file mode 100644 index 000000000..6bbba86a4 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html @@ -0,0 +1,205 @@ + + + + + + + Release Notes for TCPP0203 Component Driver + + + + + + +
+
+
+

Release Notes for TCPP0203 Component Driver

+

Copyright © 2020 STMicroelectronics
+

+ +
+

Purpose

+

This driver provides a set of functions needed to drive TCPP0203 Type-C Port Protection component

+
+
+

Update History

+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + +
Headline
MISRA Rule-81.13 correction on TCPP0203 component driver files
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
MISRA corrections on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.8.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
License updates
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.6.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
CodeSpell correction on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.5.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
MCUAstyle correction on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.5.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+
    +
  • First official release of TCPP0203 Type-C port Protection Component drivers
    • +
+
+
+
+
+
+

For complete documentation on STM32,visit: [www.st.com/stm32]

+This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
+ + diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png new file mode 100644 index 000000000..06713eec4 Binary files /dev/null and b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png differ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css new file mode 100644 index 000000000..dd19969d1 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css @@ -0,0 +1,1703 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); 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+ overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png new file mode 100644 index 000000000..d6cebb5ac Binary files /dev/null and b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png differ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c new file mode 100644 index 000000000..952ff16c9 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c @@ -0,0 +1,886 @@ +/** + ****************************************************************************** + * @file tcpp0203.c + * @author MCD Application Team + * @brief This file provides the TCPP02/03 Type-C port protection driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203.h" + +#if defined(_TRACE) +#include "usbpd_core.h" +#include "usbpd_trace.h" +#include "string.h" +#include "stdio.h" +#endif /* _TRACE */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup TCPP0203 + * @brief This file provides a set of functions needed to drive the + * TCPP02/03 Type-C port protection. + * @{ + */ + +/** @defgroup TCPP0203_Private_Constants Private Constants + * @{ + */ + +/* Compilation option in order to enable/disable a concistency check performed + after each I2C access into TCPP0203 registers : goal is to check that written value in Reg0 + is properly reflected into reg1 register content. + To enable register consistency check, please uncomment below definition. + To disable it, comment below line */ +/* #define TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** @defgroup TCPP0203_Private_Types Private Types + * @{ + */ +/* TCPP02/03 Type-C port protection driver structure initialization */ +TCPP0203_Drv_t TCPP0203_Driver = +{ + TCPP0203_Init, + TCPP0203_DeInit, + TCPP0203_Reset, + TCPP0203_SetVConnSwitch, + TCPP0203_SetGateDriverProvider, + TCPP0203_SetGateDriverConsumer, + TCPP0203_SetPowerMode, + TCPP0203_SetVBusDischarge, + TCPP0203_SetVConnDischarge, + TCPP0203_GetVConnSwitchAck, + TCPP0203_GetGateDriverProviderAck, + TCPP0203_GetGateDriverConsumerAck, + TCPP0203_GetPowerModeAck, + TCPP0203_GetVBusDischargeAck, + TCPP0203_GetVConnDischargeAck, + TCPP0203_GetOCPVConnFlag, + TCPP0203_GetOCPVBusFlag, + TCPP0203_GetOVPVBusFlag, + TCPP0203_GetOVPCCFlag, + TCPP0203_GetOTPFlag, + TCPP0203_GetVBusOkFlag, + TCPP0203_ReadTCPPType, + TCPP0203_ReadVCONNPower, + TCPP0203_WriteCtrlRegister, + TCPP0203_ReadAckRegister, + TCPP0203_ReadFlagRegister, +}; + +/** + * @} + */ + +/** @defgroup TCPP0203_Private_Variables Private Variables + * @{ + */ +static uint8_t TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_03; + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +static uint8_t Reg0_Expected_Value = 0x00; +static uint8_t Reg1_LastRead_Value = 0x00; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TCPP0203_Private_Function_Prototypes TCPP0203 Private Function Prototypes + * @{ + */ +static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); +static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); + +static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue); +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions + * @{ + */ + +/** + * @brief Register Bus Io to component + * @param Component object pointer + * @retval Status of execution + */ +int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO) +{ + int32_t ret; + + if (pObj == NULL) + { + ret = TCPP0203_ERROR; + } + else + { + pObj->IO.Init = pIO->Init; + pObj->IO.DeInit = pIO->DeInit; + pObj->IO.Address = pIO->Address; + pObj->IO.WriteReg = pIO->WriteReg; + pObj->IO.ReadReg = pIO->ReadReg; + pObj->IO.GetTick = pIO->GetTick; + + pObj->Ctx.ReadReg = TCPP0203_ReadRegWrap; + pObj->Ctx.WriteReg = TCPP0203_WriteRegWrap; + pObj->Ctx.handle = pObj; + + if (pObj->IO.Init != NULL) + { + ret = pObj->IO.Init(); + } + else + { + ret = TCPP0203_ERROR; + } + } + + return ret; +} + +/** + * @brief Initializes the TCPP0203 interface + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_Init(TCPP0203_Object_t *pObj) +{ + int32_t ret = 0; + uint8_t tmp; + + if (pObj->IsInitialized == 0U) + { + /* Read TCPP Device type */ + ret += tcpp0203_read_reg(&pObj->Ctx, TCPP0203_READ_REG2, &tmp, 1); + + if (ret == TCPP0203_OK) + { + TCPP0203_DeviceType = (tmp & TCPP0203_DEVICE_TYPE_MSK); + } + else + { + TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_02; + } + pObj->IsInitialized = 1U; + } + + if (ret != TCPP0203_OK) + { + ret = TCPP0203_ERROR; + } + + return ret; +} + +/** + * @brief Deinitializes the TCPP0203 interface + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj) +{ + if (pObj->IsInitialized == 1U) + { + /* De-Initialize IO BUS layer */ + pObj->IO.DeInit(); + + pObj->IsInitialized = 0U; + } + + return TCPP0203_OK; +} + +/** + * @brief Resets TCPP0203 register (Reg0) + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj) +{ + int32_t ret = TCPP0203_OK; + uint8_t tmp = TCPP0203_REG0_RST_VALUE; + + /* Write reset values in Reg0 register */ + if (tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1) != TCPP0203_OK) + { + ret = TCPP0203_ERROR; + } + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = TCPP0203_REG0_RST_VALUE; + Reg1_LastRead_Value = TCPP0203_REG0_RST_VALUE; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +/** + * @brief Configure TCPP0203 VConn Switch + * @param pObj Pointer to component object + * @param VConnSwitch VConn Switch requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open + * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 + * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 + * @retval Component status + */ +int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch) +{ + int32_t ret = TCPP0203_OK; + + if ((VConnSwitch != TCPP0203_VCONN_SWITCH_OPEN) + && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC1) + && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC2)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VConn switch setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VConnSwitch, TCPP0203_VCONN_SWITCH_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param GateDriverProvider GDP switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_GD_PROVIDER_SWITCH_OPEN GDP Switch Load Open + * @arg TCPP0203_GD_PROVIDER_SWITCH_CLOSED GDP Switch Load closed + * @retval Component status + */ +int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider) +{ + int32_t ret = TCPP0203_OK; + + if ((GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_OPEN) + && (GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_CLOSED)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update GDP Switch Load setting in Writing register Reg0 */ + if (GateDriverProvider == TCPP0203_GD_PROVIDER_SWITCH_CLOSED) + { + /* If Gate Driver Provider is to be closed, Gate Driver Consumer should be open */ + ret += TCPP0203_ModifyReg0(pObj, (GateDriverProvider | TCPP0203_GD_CONSUMER_SWITCH_OPEN), + (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); + } + else + { + ret += TCPP0203_ModifyReg0(pObj, GateDriverProvider, TCPP0203_GD_PROVIDER_SWITCH_MSK); + } + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Consumer path + * @param pObj Pointer to component object + * @param GateDriverConsumer GDC switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_GD_CONSUMER_SWITCH_OPEN GDC Switch Load Open + * @arg TCPP0203_GD_CONSUMER_SWITCH_CLOSED GDC Switch Load closed + * @retval Component status + */ +int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer) +{ + int32_t ret = TCPP0203_OK; + + /* Check if TCPP type is TCPP03. Otherwise, return error */ + if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) + { + return (TCPP0203_ERROR); + } + + if ((GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_OPEN) + && (GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_CLOSED)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update GDC Switch Load setting in Writing register Reg0 */ + if (GateDriverConsumer == TCPP0203_GD_CONSUMER_SWITCH_CLOSED) + { + /* If Gate Driver Consumer is to be closed, Gate Driver Provider should be open */ + ret += TCPP0203_ModifyReg0(pObj, (GateDriverConsumer | TCPP0203_GD_PROVIDER_SWITCH_OPEN), + (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); + } + else + { + ret += TCPP0203_ModifyReg0(pObj, GateDriverConsumer, TCPP0203_GD_CONSUMER_SWITCH_MSK); + } + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Power Mode + * @param pObj Pointer to component object + * @param PowerMode Power mode requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_POWER_MODE_HIBERNATE Hibernate + * @arg TCPP0203_POWER_MODE_LOWPOWER Low Power + * @arg TCPP0203_POWER_MODE_NORMAL Normal + * @retval Component status + */ +int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode) +{ + int32_t ret = TCPP0203_OK; + + if ((PowerMode != TCPP0203_POWER_MODE_HIBERNATE) + && (PowerMode != TCPP0203_POWER_MODE_LOWPOWER) + && (PowerMode != TCPP0203_POWER_MODE_NORMAL)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update Power Mode setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, PowerMode, TCPP0203_POWER_MODE_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param VBusDischarge VBUS Discharge requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VBUS_DISCHARGE_OFF VBUS Discharge Off + * @arg TCPP0203_VBUS_DISCHARGE_ON VBUS Discharge On + * @retval Component status + */ +int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge) +{ + int32_t ret = TCPP0203_OK; + + if ((VBusDischarge != TCPP0203_VBUS_DISCHARGE_OFF) + && (VBusDischarge != TCPP0203_VBUS_DISCHARGE_ON)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VBUS Discharge setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VBusDischarge, TCPP0203_VBUS_DISCHARGE_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param VConnDischarge GDP switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VCONN_DISCHARGE_OFF VConn Discharge Off + * @arg TCPP0203_VCONN_DISCHARGE_ON VConn Discharge On + * @retval Component status + */ +int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge) +{ + int32_t ret = TCPP0203_OK; + + if ((VConnDischarge != TCPP0203_VCONN_DISCHARGE_OFF) + && (VConnDischarge != TCPP0203_VCONN_DISCHARGE_ON)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VConn Discharge setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VConnDischarge, TCPP0203_VCONN_DISCHARGE_MSK); + } + + return ret; +} + +/** + * @brief Get VConn switch Ack value + * @param pObj Pointer to component object + * @param pVConnSwitchAck Pointer on VConn switch Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open Ack + * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 Ack + * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 Ack + * @retval Component status + */ +int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVConnSwitchAck = (tmp & TCPP0203_VCONN_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Gate Driver Provider Ack value + * @param pObj Pointer to component object + * @param pGateDriverProviderAck Pointer on Gate Driver Provider Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN Gate Driver Provider Open Ack + * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED Gate Driver Provider Closed Ack + * @retval Component status + */ +int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pGateDriverProviderAck = (tmp & TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Gate Driver Consumer Ack value + * @param pObj Pointer to component object + * @param pGateDriverConsumerAck Pointer on Gate Driver Consumer Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN Gate Driver Consumer Open Ack + * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED Gate Driver Consumer Closed Ack + * @retval Component status + */ +int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck) +{ + int32_t ret; + uint8_t tmp; + + /* Check if TCPP type is TCPP03. Otherwise, return error */ + if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) + { + return (TCPP0203_ERROR); + } + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pGateDriverConsumerAck = (tmp & TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Power Mode Ack value + * @param pObj Pointer to component object + * @param pPowerModeAck Pointer on Power Mode Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_POWER_MODE_ACK_HIBERNATE Power Mode Hibernate Ack + * @arg TCPP0203_POWER_MODE_ACK_LOWPOWER Power Mode Low Power Ack + * @arg TCPP0203_POWER_MODE_ACK_NORMAL Power Mode Normal Ack + * @retval Component status + */ +int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pPowerModeAck = (tmp & TCPP0203_POWER_MODE_ACK_MSK); + + return ret; +} + +/** + * @brief Get VBUS Discharge Ack value + * @param pObj Pointer to component object + * @param pVBusDischargeAck Pointer on VBUS Discharge Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VBUS_DISCHARGE_ACK_OFF VBUS Discharge Off Ack + * @arg TCPP0203_VBUS_DISCHARGE_ACK_ON VBUS Discharge On Ack + * @retval Component status + */ +int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVBusDischargeAck = (tmp & TCPP0203_VBUS_DISCHARGE_ACK_MSK); + + return ret; +} + +/** + * @brief Get VConn Discharge Ack value + * @param pObj Pointer to component object + * @param pVConnDischargeAck Pointer on VConn Discharge Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VCONN_DISCHARGE_ACK_OFF VConn Discharge Off Ack + * @arg TCPP0203_VCONN_DISCHARGE_ACK_ON VConn Discharge On Ack + * @retval Component status + */ +int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVConnDischargeAck = (tmp & TCPP0203_VCONN_DISCHARGE_ACK_MSK); + + return ret; +} + +/** + * @brief Get OCP VConn Flag value + * @param pObj Pointer to component object + * @param pOCPVConnFlag Pointer on OCP VConn Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OCP_VCONN_RESET OCP VConn flag not set + * @arg TCPP0203_FLAG_OCP_VCONN_SET OCP VConn flag set + * @retval Component status + */ +int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOCPVConnFlag = (tmp & TCPP0203_FLAG_OCP_VCONN_MSK); + + return ret; +} + +/** + * @brief Get OCP VBUS Flag value + * @param pObj Pointer to component object + * @param pGetOCPVBusFlag Pointer on OCP VBUS Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OCP_VBUS_RESET OCP VBUS flag not set + * @arg TCPP0203_FLAG_OCP_VBUS_SET OCP VBUS flag set + * @retval Component status + */ +int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pGetOCPVBusFlag = (tmp & TCPP0203_FLAG_OCP_VBUS_MSK); + + return ret; +} + +/** + * @brief Get OVP VBUS Flag value + * @param pObj Pointer to component object + * @param pOVPVBusFlag Pointer on OVP VBUS Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OVP_VBUS_RESET OVP VBUS flag not set + * @arg TCPP0203_FLAG_OVP_VBUS_SET OVP VBUS flag set + * @retval Component status + */ +int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOVPVBusFlag = (tmp & TCPP0203_FLAG_OVP_VBUS_MSK); + + return ret; +} + +/** + * @brief Get OVP CC Flag value + * @param pObj Pointer to component object + * @param pOVPCCFlag Pointer on OVP CC Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OVP_CC_RESET OVP CC flag not set + * @arg TCPP0203_FLAG_OVP_CC_SET OVP CC flag set + * @retval Component status + */ +int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOVPCCFlag = (tmp & TCPP0203_FLAG_OVP_CC_MSK); + + return ret; +} + +/** + * @brief Get Over Temperature Flag value + * @param pObj Pointer to component object + * @param pOTPFlag Pointer on Over Temperature Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OTP_RESET Over Temperature flag not set + * @arg TCPP0203_FLAG_OTP_SET Over Temperature flag set + * @retval Component status + */ +int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOTPFlag = (tmp & TCPP0203_FLAG_OTP_MSK); + + return ret; +} + +/** + * @brief Get VBUS OK Flag value + * @param pObj Pointer to component object + * @param pVBusOkFlag Pointer on VBUS OK Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_VBUS_OK_RESET VBUS OK flag not set + * @arg TCPP0203_FLAG_VBUS_OK_SET VBUS OK flag set + * @retval Component status + */ +int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pVBusOkFlag = (tmp & TCPP0203_FLAG_VBUS_OK_MSK); + + return ret; +} + +/** + * @brief Get TCPP0203 Device Type value + * @param pObj Pointer to component object + * @param pTCPPType Pointer on TCPP0203 Device Type value + * This output parameter can be one of the following values: + * @arg TCPP0203_DEVICE_TYPE_02 TCPP02 Type + * @arg TCPP0203_DEVICE_TYPE_03 TCPP03 Type + * @retval Component status + */ +int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pTCPPType = (tmp & TCPP0203_DEVICE_TYPE_MSK); + + return ret; +} + +/** + * @brief Get VConn Power value + * @param pObj Pointer to component object + * @param pVCONNPower Pointer on VConn Power value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_VCONN_PWR_1W OCP VConn flag not set + * @arg TCPP0203_FLAG_VCONN_PWR_0_1W OCP VConn flag set + * @retval Component status + */ +int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pVCONNPower = (tmp & TCPP0203_FLAG_VCONN_PWR_MSK); + + return ret; +} + +/** + * @brief Set complete Ctrl register value (Reg 0) + * @param pObj Pointer to component object + * @param pCtrlRegister Pointer on Ctrl register value + * @retval Component status + */ +int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister) +{ + int32_t ret; + + /* Update value in writing register (reg0) */ + ret = tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, pCtrlRegister, 1); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = *pCtrlRegister; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +/** + * @brief Get complete Ack register value + * @param pObj Pointer to component object + * @param pAckRegister Pointer on Ack register value + * @retval Component status + */ +int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister) +{ + int32_t ret; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, pAckRegister, 1); + + return ret; +} + +/** + * @brief Get complete Flag register value + * @param pObj Pointer to component object + * @param pFlagRegister Pointer on Flag register value + * @retval Component status + */ +int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister) +{ + int32_t ret; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, pFlagRegister, 1); + + return ret; +} + +/******************** Static functions ****************************************/ +/** + * @brief Wrap TCPP0203 read function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to read + * @param pData Buffer where Target register value should be stored + * @param Length buffer size to be read + * @retval error status + */ +static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) +{ + const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; + + return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length); +} + +/** + * @brief Wrap TCPP0203 write function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to write + * @param pData Target register value to be written + * @param Length Buffer size to be written + * @retval error status + */ +static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) +{ + const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = *pData; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length); +} + +/** + * @brief TCPP0203 register update function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to write + * @param pData Target register value to be written + * @param Length Buffer size to be written + * @retval error status + */ +static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask) +{ + int32_t ret; + uint8_t tmp; + + /* Read current content of ACK register (reflects content of bits set to 1 in Writing register Reg0) */ + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + + /* Update only the area dedicated to Mask */ + tmp &= ~(Mask); + tmp |= (Value & Mask); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = tmp; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + /* Update value in writing register (reg0) */ + ret += tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + ret += TCPP0203_CheckReg0Reg1(pObj, Reg0_Expected_Value); +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +/** + * @brief TCPP0203 register control function between Reg0 and Reg1 value + * @param handle Component object handle + * @param Reg0ExpectedValue Value expected in Reg0 (built after all calls to write functions) + * @retval error status + */ +static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue) +{ + int32_t ret; + + /* Read current content of ACK register (expected to reflect content of bits set to 1 in Writing register Reg0) */ + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &Reg1_LastRead_Value, 1); + +#ifdef _TRACE + char str[12]; + sprintf(str, "Exp0_0x%02x", Reg0ExpectedValue); + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); + sprintf(str, "Reg1_0x%02x", Reg1_LastRead_Value); + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); +#endif /* _TRACE */ + + /* Control if Reg1 value is same as Reg0 expected one */ + if (Reg1_LastRead_Value != Reg0ExpectedValue) + { + while (1); + } + + return ret; +} +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h new file mode 100644 index 000000000..271b534fc --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h @@ -0,0 +1,353 @@ +/** + ****************************************************************************** + * @file tcpp0203.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the + * tcpp0203.c driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef TCPP0203_H +#define TCPP0203_H + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203_reg.h" +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @addtogroup TCPP0203 + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup TCPP0203_Exported_Types TCPP0203 Exported Types + * @{ + */ +typedef int32_t (*TCPP0203_Init_Func)(void); +typedef int32_t (*TCPP0203_DeInit_Func)(void); +typedef int32_t (*TCPP0203_GetTick_Func)(void); +typedef int32_t (*TCPP0203_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); +typedef int32_t (*TCPP0203_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); + +typedef struct +{ + TCPP0203_Init_Func Init; + TCPP0203_DeInit_Func DeInit; + uint16_t Address; + TCPP0203_WriteReg_Func WriteReg; + TCPP0203_ReadReg_Func ReadReg; + TCPP0203_GetTick_Func GetTick; +} TCPP0203_IO_t; + + +typedef struct +{ + TCPP0203_IO_t IO; + TCPP0203_ctx_t Ctx; + uint8_t IsInitialized; +} TCPP0203_Object_t; + +typedef struct +{ + int32_t (*Init)(TCPP0203_Object_t *); + int32_t (*DeInit)(TCPP0203_Object_t *); + int32_t (*Reset)(TCPP0203_Object_t *); + int32_t (*SetVConnSwitch)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetGateDriverProvider)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetGateDriverConsumer)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetPowerMode)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetVBusDischarge)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetVConnDischarge)(TCPP0203_Object_t *, uint8_t); + int32_t (*GetVConnSwitchAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetGateDriverProviderAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetGateDriverConsumerAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetPowerModeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVBusDischargeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVConnDischargeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOCPVConnFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOCPVBusFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOVPVBusFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOVPCCFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOTPFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVBusOkFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadTCPPType)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadVCONNPower)(TCPP0203_Object_t *, uint8_t *); + int32_t (*WriteCtrlRegister)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadAckRegister)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadFlagRegister)(TCPP0203_Object_t *, uint8_t *); +} TCPP0203_Drv_t; + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants + * @{ + */ +/** + * @brief TCPP0203 Driver Response codes + */ +#define TCPP0203_OK (0) +#define TCPP0203_ERROR (-1) + +/** + * @brief TCPP0203 possible I2C Addresses + */ +#define TCPP0203_I2C_ADDRESS_X68 (0x68U) +#define TCPP0203_I2C_ADDRESS_X6A (0x6AU) + +/** + * @brief TCPP0203 Reg0 Reset Value + */ +#define TCPP0203_REG0_RST_VALUE TCPP0203_GD_CONSUMER_SWITCH_CLOSED + +/** + * @brief TCPP0203 VCONN Switch + */ +#define TCPP0203_VCONN_SWITCH_POS (0U) +#define TCPP0203_VCONN_SWITCH_MSK (0x03U << TCPP0203_VCONN_SWITCH_POS) +#define TCPP0203_VCONN_SWITCH_OPEN (0x00U) +#define TCPP0203_VCONN_SWITCH_CC1 (0x01U << TCPP0203_VCONN_SWITCH_POS) +#define TCPP0203_VCONN_SWITCH_CC2 (0x02U << TCPP0203_VCONN_SWITCH_POS) + +/** + * @brief TCPP0203 Gate Driver Provider values + */ +#define TCPP0203_GD_PROVIDER_SWITCH_POS (2U) +#define TCPP0203_GD_PROVIDER_SWITCH_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_POS) +#define TCPP0203_GD_PROVIDER_SWITCH_OPEN (0x00U) +#define TCPP0203_GD_PROVIDER_SWITCH_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_MSK) + +/** + * @brief TCPP0203 Gate Driver Consumer values + */ +#define TCPP0203_GD_CONSUMER_SWITCH_POS (3U) +#define TCPP0203_GD_CONSUMER_SWITCH_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_POS) +#define TCPP0203_GD_CONSUMER_SWITCH_CLOSED (0x00U) +#define TCPP0203_GD_CONSUMER_SWITCH_OPEN (TCPP0203_GD_CONSUMER_SWITCH_MSK) + +/** + * @brief TCPP0203 Power Mode values + */ +#define TCPP0203_POWER_MODE_POS (4U) +#define TCPP0203_POWER_MODE_MSK (0x03U << TCPP0203_POWER_MODE_POS) +#define TCPP0203_POWER_MODE_HIBERNATE (0x00U) +#define TCPP0203_POWER_MODE_LOWPOWER (0x02U << TCPP0203_POWER_MODE_POS) +#define TCPP0203_POWER_MODE_NORMAL (0x01U << TCPP0203_POWER_MODE_POS) + +/** + * @brief TCPP0203 VBUS Discharge management + */ +#define TCPP0203_VBUS_DISCHARGE_POS (6U) +#define TCPP0203_VBUS_DISCHARGE_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_POS) +#define TCPP0203_VBUS_DISCHARGE_OFF (0x00U) +#define TCPP0203_VBUS_DISCHARGE_ON (TCPP0203_VBUS_DISCHARGE_MSK) + +/** + * @brief TCPP0203 VConn Discharge management + */ +#define TCPP0203_VCONN_DISCHARGE_POS (7U) +#define TCPP0203_VCONN_DISCHARGE_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_POS) +#define TCPP0203_VCONN_DISCHARGE_OFF (0x00U) +#define TCPP0203_VCONN_DISCHARGE_ON (TCPP0203_VCONN_DISCHARGE_MSK) + +/** + * @brief TCPP0203 VCONN Switch Acknowledge + */ +#define TCPP0203_VCONN_SWITCH_ACK_POS (0U) +#define TCPP0203_VCONN_SWITCH_ACK_MSK (0x03U << TCPP0203_VCONN_SWITCH_ACK_POS) +#define TCPP0203_VCONN_SWITCH_ACK_OPEN (0x00U) +#define TCPP0203_VCONN_SWITCH_ACK_CC1 (0x02U << TCPP0203_VCONN_SWITCH_ACK_POS) +#define TCPP0203_VCONN_SWITCH_ACK_CC2 (0x01U << TCPP0203_VCONN_SWITCH_ACK_POS) + +/** + * @brief TCPP0203 Gate Driver Provider Acknowledge + */ +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_POS (2U) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_ACK_POS) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN (0x00U) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK) + +/** + * @brief TCPP0203 Gate Driver Consumer Acknowledge + */ +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_POS (3U) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_ACK_POS) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED (0x00U) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN (TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK) + +/** + * @brief TCPP0203 Power Mode Acknowledge + */ +#define TCPP0203_POWER_MODE_ACK_POS (4U) +#define TCPP0203_POWER_MODE_ACK_MSK (0x03U << TCPP0203_POWER_MODE_ACK_POS) +#define TCPP0203_POWER_MODE_ACK_HIBERNATE (0x00U) +#define TCPP0203_POWER_MODE_ACK_LOWPOWER (0x01U << TCPP0203_POWER_MODE_ACK_POS) +#define TCPP0203_POWER_MODE_ACK_NORMAL (0x02U << TCPP0203_POWER_MODE_ACK_POS) + +/** + * @brief TCPP0203 VBUS Discharge Acknowledge + */ +#define TCPP0203_VBUS_DISCHARGE_ACK_POS (6U) +#define TCPP0203_VBUS_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_ACK_POS) +#define TCPP0203_VBUS_DISCHARGE_ACK_OFF (0x00U) +#define TCPP0203_VBUS_DISCHARGE_ACK_ON (TCPP0203_VBUS_DISCHARGE_ACK_MSK) + +/** + * @brief TCPP0203 VConn Discharge Acknowledge + */ +#define TCPP0203_VCONN_DISCHARGE_ACK_POS (7U) +#define TCPP0203_VCONN_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_ACK_POS) +#define TCPP0203_VCONN_DISCHARGE_ACK_OFF (0x00U) +#define TCPP0203_VCONN_DISCHARGE_ACK_ON (TCPP0203_VCONN_DISCHARGE_ACK_MSK) + +/** + * @brief TCPP0203 OCP Vconn Flag management + */ +#define TCPP0203_FLAG_OCP_VCONN_POS (0U) +#define TCPP0203_FLAG_OCP_VCONN_MSK (0x01U << TCPP0203_FLAG_OCP_VCONN_POS) +#define TCPP0203_FLAG_OCP_VCONN_SET (TCPP0203_FLAG_OCP_VCONN_MSK) +#define TCPP0203_FLAG_OCP_VCONN_RESET (0x00U) + +/** + * @brief TCPP0203 OCP VBUS Flag management + */ +#define TCPP0203_FLAG_OCP_VBUS_POS (1U) +#define TCPP0203_FLAG_OCP_VBUS_MSK (0x01U << TCPP0203_FLAG_OCP_VBUS_POS) +#define TCPP0203_FLAG_OCP_VBUS_SET (TCPP0203_FLAG_OCP_VBUS_MSK) +#define TCPP0203_FLAG_OCP_VBUS_RESET (0x00U) + +/** + * @brief TCPP0203 OVP VBUS Flag management + */ +#define TCPP0203_FLAG_OVP_VBUS_POS (2U) +#define TCPP0203_FLAG_OVP_VBUS_MSK (0x01U << TCPP0203_FLAG_OVP_VBUS_POS) +#define TCPP0203_FLAG_OVP_VBUS_SET (TCPP0203_FLAG_OVP_VBUS_MSK) +#define TCPP0203_FLAG_OVP_VBUS_RESET (0x00U) + +/** + * @brief TCPP0203 OVP CC Flag management + */ +#define TCPP0203_FLAG_OVP_CC_POS (3U) +#define TCPP0203_FLAG_OVP_CC_MSK (0x01U << TCPP0203_FLAG_OVP_CC_POS) +#define TCPP0203_FLAG_OVP_CC_SET (TCPP0203_FLAG_OVP_CC_MSK) +#define TCPP0203_FLAG_OVP_CC_RESET (0x00U) + +/** + * @brief TCPP0203 OTP Flag management + */ +#define TCPP0203_FLAG_OTP_POS (4U) +#define TCPP0203_FLAG_OTP_MSK (0x01U << TCPP0203_FLAG_OTP_POS) +#define TCPP0203_FLAG_OTP_SET (TCPP0203_FLAG_OTP_MSK) +#define TCPP0203_FLAG_OTP_RESET (0x00U) + +/** + * @brief TCPP0203 VBUS OK Flag management + */ +#define TCPP0203_FLAG_VBUS_OK_POS (5U) +#define TCPP0203_FLAG_VBUS_OK_MSK (0x01U << TCPP0203_FLAG_VBUS_OK_POS) +#define TCPP0203_FLAG_VBUS_OK_SET (TCPP0203_FLAG_VBUS_OK_MSK) +#define TCPP0203_FLAG_VBUS_OK_RESET (0x00U) + +/** + * @brief TCPP0203 VConn Power + */ +#define TCPP0203_FLAG_VCONN_PWR_POS (6U) +#define TCPP0203_FLAG_VCONN_PWR_MSK (0x01U << TCPP0203_FLAG_VCONN_PWR_POS) +#define TCPP0203_FLAG_VCONN_PWR_1W (TCPP0203_FLAG_VCONN_PWR_MSK) +#define TCPP0203_FLAG_VCONN_PWR_0_1W (0x00U) + +/** + * @brief TCPP0203 Device Type + */ +#define TCPP0203_DEVICE_TYPE_POS (7U) +#define TCPP0203_DEVICE_TYPE_MSK (0x01U << TCPP0203_DEVICE_TYPE_POS) +#define TCPP0203_DEVICE_TYPE_02 (TCPP0203_DEVICE_TYPE_MSK) +#define TCPP0203_DEVICE_TYPE_03 (0x00U) + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Macros TCPP0203 Exported Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions + * @{ + */ + +/*------------------------------------------------------------------------------ + TCPP02/03 Type-C port protection functions +------------------------------------------------------------------------------*/ +/* High Layer codec functions */ +int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO); +int32_t TCPP0203_Init(TCPP0203_Object_t *pObj); +int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj); +int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj); +int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch); +int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider); +int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer); +int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode); +int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge); +int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge); +int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck); +int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck); +int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck); +int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck); +int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck); +int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck); +int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag); +int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag); +int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag); +int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag); +int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag); +int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag); +int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType); +int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower); +int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister); +int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister); +int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister); + +/** + * @} + */ + +/* TCPP02/03 Type-C port protection driver structure */ +extern TCPP0203_Drv_t TCPP0203_Driver; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TCPP0203_H */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c new file mode 100644 index 000000000..8025fa85e --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file tcpp0203_reg.c + * @author MCD Application Team + * @brief This file provides unitary register function to control the TCPP02-03 + * Type-C port protection driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203_reg.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup TCPP0203 + * @brief This file provides a set of functions needed to drive the + * TCPP02/03 Type-C port protection codec. + * @{ + */ + +/************** Generic Function *******************/ +/******************************************************************************* + * Function Name : tcpp0203_read_reg + * Description : Generic Reading function. It must be fulfilled with either + * I2C or SPI reading functions + * Input : Register Address, length of buffer + * Output : data Read + *******************************************************************************/ +int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) +{ + return ctx->ReadReg(ctx->handle, reg, data, length); +} + +/******************************************************************************* + * Function Name : tcpp0203_write_reg + * Description : Generic Writing function. It must be fulfilled with either + * I2C or SPI writing function + * Input : Register Address, data to be written, length of buffer + * Output : None + *******************************************************************************/ +int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) +{ + return ctx->WriteReg(ctx->handle, reg, data, length); +} + +/******************************************************************************/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h new file mode 100644 index 000000000..92420e1fe --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file tcpp0203_reg.h + * @author MCD Application Team + * @brief Header of tcpp0203_reg.c + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef TCPP0203_REG_H +#define TCPP0203_REG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @addtogroup TCPP0203 + * @{ + */ + + +/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants + * @{ + */ +/******************************************************************************/ +/****************************** REGISTER MAPPING ******************************/ +/******************************************************************************/ +#define TCPP0203_WRITE_REG 0x00U +#define TCPP0203_PROG_CTRL TCPP0203_WRITE_REG +#define TCPP0203_READ_REG1 0x01U +#define TCPP0203_ACK_REG TCPP0203_READ_REG1 +#define TCPP0203_READ_REG2 0x02U +#define TCPP0203_FLAG_REG TCPP0203_READ_REG2 + +/** + * @} + */ + +/************** Generic Function *******************/ + +typedef int32_t (*TCPP0203_Write_Func)(const void *, uint8_t, uint8_t *, uint8_t); +typedef int32_t (*TCPP0203_Read_Func)(const void *, uint8_t, uint8_t *, uint8_t); + +typedef struct +{ + TCPP0203_Write_Func WriteReg; + TCPP0203_Read_Func ReadReg; + void *handle; +} TCPP0203_ctx_t; + +/******************************************************************************* + * Register : Generic - All + * Address : Generic - All + * Bit Group Name: None + * Permission : W + *******************************************************************************/ +int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); +int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* TCPP0203_REG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c new file mode 100644 index 000000000..0ec1875ac --- /dev/null +++ b/hw/bsp/stm32n6/family.c @@ -0,0 +1,276 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 + * William D. Jones (thor0505@comcast.net), + * Ha Thach (tinyusb.org) + * Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: STMicroelectronics +*/ + +// Suppress warning caused by mcu driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wcast-align" +#endif + +#include "stm32n6xx_hal.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "bsp/board_api.h" + +TU_ATTR_UNUSED static void Error_Handler(void) { } + +void HardFault_Handler(void); + +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; + +#include "board.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif + +#ifndef SWO_FREQ +#define SWO_FREQ 4000000 +#endif + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +// Despite being call USB2_OTG_FS on some MCUs +// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port +void USB2_OTG_HS_IRQHandler(void) { + tusb_int_handler(0, true); +} + +// Despite being call USB1_OTG_HS on some MCUs +// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port +void USB1_OTG_HS_IRQHandler(void) { + tusb_int_handler(1, true); +} + +void board_init(void) { + + /* Enable BusFault and SecureFault handlers (HardFault is default) */ + SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk); + + HAL_PWREx_EnableVddA(); + HAL_PWREx_EnableVddIO2(); + HAL_PWREx_EnableVddIO3(); + HAL_PWREx_EnableVddIO4(); + HAL_PWREx_EnableVddIO5(); + + HAL_Init(); + + // Implemented in board.h + SystemClock_Config(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + __HAL_RCC_GPIOQ_CLK_ENABLE(); + + // HAL_ICACHE_Enable(); + + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } + + NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0)); + NVIC_EnableIRQ(UCPD1_IRQn); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + + NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + + +#ifdef UART_DEV + UART_CLK_EN(); + HAL_UART_Init(&UartHandle); +#endif + + + __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_EnableVddUSBVMEN(); + while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY)); + HAL_PWREx_EnableVddUSB(); + + LL_AHB5_GRP1_ForceReset(0x00800000); + __HAL_RCC_USB1_OTG_HS_FORCE_RESET(); + __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET(); + + LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(); + LL_AHB5_GRP1_ReleaseReset(0x00800000); + + /* Peripheral clock enable */ + __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); + + /* Required few clock cycles before accessing USB PHY Controller Registers */ + HAL_Delay(1); + + USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4); + + USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) | + (0x2 << 4) | + (0x1 << 2) | + 0x1U; + + __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET(); + + /* Required few clock cycles before Releasing Reset */ + HAL_Delay(1); + + __HAL_RCC_USB1_OTG_HS_RELEASE_RESET(); + + /* Peripheral PHY clock enable */ + __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE(); + + board_init2(); + +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUH_RHPORT, 1); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif +} + +uint32_t board_button_read(void) { +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) + buf, len, 0xffff); + return len; +#else + (void) buf; (void) len; + return -1; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + HAL_IncTick(); + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} + +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/stm32n6/family.cmake b/hw/bsp/stm32n6/family.cmake new file mode 100644 index 000000000..600af7cdb --- /dev/null +++ b/hw/bsp/stm32n6/family.cmake @@ -0,0 +1,147 @@ +include_guard() + +set(ST_FAMILY n6) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m55 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32N6 CACHE INTERNAL "") + +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif () + +if (NOT DEFINED RHPORT_SPEED) + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif() + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + + if(NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld) + endif() + set(LD_FILE_Clang ${LD_FILE_GNU}) + if(NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + endif() + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}_ns.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32N6 ${RTOS}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_stlink(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32n6/family.mk b/hw/bsp/stm32n6/family.mk new file mode 100644 index 000000000..97930e189 --- /dev/null +++ b/hw/bsp/stm32n6/family.mk @@ -0,0 +1,101 @@ +ST_FAMILY = n6 +ST_PREFIX = stm32${ST_FAMILY}xx +ST_PREFIX_LONG = stm32${ST_FAMILY}57xx +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver + +UF2_FAMILY_ID = 0x6db66083 + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m55 + +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 1 + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32N6 \ + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += \ + -Wno-error=cast-align \ + -Wno-error=unused-parameter \ + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}_fsbl.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_hcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rif.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# Linker +LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(ST_PREFIX_LONG)_fsbl.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(ST_PREFIX_LONG)_flash.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32n6/partition_stm32n657xx.h b/hw/bsp/stm32n6/partition_stm32n657xx.h new file mode 100644 index 000000000..713068609 --- /dev/null +++ b/hw/bsp/stm32n6/partition_stm32n657xx.h @@ -0,0 +1,792 @@ +/** + ****************************************************************************** + * @file partition_stm32n657xx.h + * @author MCD Application Team + * @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32N657XX_H +#define PARTITION_STM32N657XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state +// CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state +// IAC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// CRYP_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// MCE1_IRQn <0=> Secure state <1=> Non-Secure state +// MCE2_IRQn <0=> Secure state <1=> Non-Secure state +// MCE3_IRQn <0=> Secure state <1=> Non-Secure state +// MCE4_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state +// CSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// NPU0_IRQn <0=> Secure state <1=> Non-Secure state +// NPU1_IRQn <0=> Secure state <1=> Non-Secure state +// NPU2_IRQn <0=> Secure state <1=> Non-Secure state +// NPU3_IRQn <0=> Secure state <1=> Non-Secure state +// CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +// VENC_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM9_IRQn <0=> Secure state <1=> Non-Secure state +// TIM10_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// TIM18_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state +// SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 + +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI3_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// ETH1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state +// MDIOS_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 + +/* +// Interrupts 192..223 +// Reserved <0=> Secure state <1=> Non-Secure state +// LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} + +#endif /* PARTITION_STM32N657XX_H */ diff --git a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h new file mode 100644 index 000000000..d98d365a3 --- /dev/null +++ b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h @@ -0,0 +1,504 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32n6xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_CONF_H +#define STM32N6xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_BSEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DCMIPP_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GFXTIM_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +#define HAL_HCD_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_ICACHE_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MCE_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +#define HAL_RIF_MODULE_ENABLED +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED*/ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_MDIOS_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */ +/* The real value may vary depending on the variations in voltage and temperature.*/ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32n6xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ########################## */ +#define USE_SDIO_TRANSCEIVER 1U +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32n6xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_RIF_MODULE_ENABLED +#include "stm32n6xx_hal_rif.h" +#endif /* HAL_RIF_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32n6xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CACHEAXI_MODULE_ENABLED +#include "stm32n6xx_hal_cacheaxi.h" +#endif /* HAL_CACHEAXI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32n6xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32n6xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_BSEC_MODULE_ENABLED +#include "stm32n6xx_hal_bsec.h" +#endif /* HAL_BSEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32n6xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32n6xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32n6xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32n6xx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32n6xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32n6xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32n6xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32n6xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32n6xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32n6xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32n6xx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32n6xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32n6xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32n6xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32n6xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32n6xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32n6xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32n6xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32n6xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32n6xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32n6xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32n6xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32n6xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32n6xx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32n6xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED +#include "stm32n6xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32n6xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32n6xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32n6xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32n6xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32n6xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32n6xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32n6xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32n6xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32n6xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32n6xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32n6xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32n6xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32n6xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32n6xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#include "stm32n6xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32n6xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32n6xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32n6xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32n6xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32n6xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32n6xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macros -----------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_CONF_H */ diff --git a/hw/bsp/zephyr_board_aliases.cmake b/hw/bsp/zephyr_board_aliases.cmake index 91ffc3a39..b85ecec81 100644 --- a/hw/bsp/zephyr_board_aliases.cmake +++ b/hw/bsp/zephyr_board_aliases.cmake @@ -1 +1,2 @@ set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) +set(stm32n657nucleo_BOARD_ALIAS nucleo_n657x0_q) \ No newline at end of file diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 6678265b5..027446a85 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -322,6 +322,15 @@ // MCU with on-chip HS Phy #define TUP_RHPORT_HIGHSPEED 1 +#elif TU_CHECK_MCU(OPT_MCU_STM32N6) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_STM32 + + #define TUP_DCD_ENDPOINT_MAX 9 + + // MCU with on-chip HS Phy + #define TUP_RHPORT_HIGHSPEED 2 + //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 865c51894..5f86d6b76 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -425,6 +425,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Clear A override, force B Valid dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; +#if CFG_TUSB_MCU == OPT_MCU_STM32N6 + // No hardware detection of Vbus B-session is available on the STM32N6 + dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL; +#endif + // Enable required interrupts dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 25edcf22d..38aa5656a 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -22,6 +22,7 @@ dwc2_reg_value = { 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'ST N6xx HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030], 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], } diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index c11c1eb05..0c1f835a9 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -77,6 +77,17 @@ extern "C" { #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 +#elif CFG_TUSB_MCU == OPT_MCU_STM32N6 + #include "stm32n6xx.h" + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 + + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 + + #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_BASE + #define OTG_HS_IRQn USB1_OTG_HS_IRQn + #elif CFG_TUSB_MCU == OPT_MCU_STM32F7 #include "stm32f7xx.h" #define EP_MAX_FS 6 diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 2de15068a..257fa2833 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -381,6 +381,10 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; +#if CFG_TUSB_MCU == OPT_MCU_STM32N6 + // No hardware detection of Vbus B-session is available on the STM32N6 + dwc2->stm32_gccfg &= ~STM32_GCCFG_VBVALOVAL; +#endif while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} // configure fixed-allocated fifo scheme diff --git a/src/tusb_option.h b/src/tusb_option.h index 104f669c9..cca6096c6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -94,6 +94,7 @@ #define OPT_MCU_STM32U0 316 ///< ST U0 #define OPT_MCU_STM32H7RS 317 ///< ST F7RS #define OPT_MCU_STM32C0 318 ///< ST C0 +#define OPT_MCU_STM32N6 319 ///< ST N6 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 diff --git a/tools/get_deps.py b/tools/get_deps.py index 1ce8be6c7..ab9d50585 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -118,6 +118,9 @@ deps_optional = { 'hw/mcu/st/cmsis_device_l5': ['https://github.com/STMicroelectronics/cmsis_device_l5.git', 'd922865fc0326a102c26211c44b8e42f52c1e53d', 'stm32l5'], + 'hw/mcu/st/cmsis_device_n6': ['https://github.com/STMicroelectronics/cmsis-device-n6.git', + 'f818b00f775444e8d19ef6cad822534c345e054f', + 'stm32n6'], 'hw/mcu/st/cmsis_device_u5': ['https://github.com/STMicroelectronics/cmsis_device_u5.git', '5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309', 'stm32u5'], @@ -172,6 +175,9 @@ deps_optional = { 'hw/mcu/st/stm32l5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git', '675c32a75df37f39d50d61f51cb0dcf53f07e1cb', 'stm32l5'], + 'hw/mcu/st/stm32n6xx_hal_driver': ['https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git', + '49f9989d10cf6817d4b07ac01848956b46bd0fd6', + 'stm32n6'], 'hw/mcu/st/stm32u5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git', '4d93097a67928e9377e655ddd14622adc31b9770', 'stm32u5'], @@ -198,7 +204,7 @@ deps_optional = { 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' - 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb ' + 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32n6 stm32u5 stm32wb ' 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg ' 'tm4c '], 'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git', -- cgit v1.3.1 From 3cf7234d67f2cf3350cf0779a1ddd2e15e6a4b0e Mon Sep 17 00:00:00 2001 From: James Sandison Date: Wed, 4 Jun 2025 11:37:45 +1000 Subject: chore: whitespace fix --- hw/bsp/stm32n6/partition_stm32n657xx.h | 2 +- hw/mcu/st/cmsis_device_h7rs | 1 + hw/mcu/st/cmsis_device_n6 | 1 + hw/mcu/st/stm32h7rsxx_hal_driver | 1 + hw/mcu/st/stm32n6xx_hal_driver | 1 + lib/CMSIS_5 | 1 + lib/FreeRTOS-Kernel | 1 + lib/lwip | 1 + modules/crypto/mbedtls | 1 + modules/hal/cmsis | 1 + modules/hal/stm32 | 1 + tools/uf2 | 1 + zephyr | 1 + 13 files changed, 13 insertions(+), 1 deletion(-) create mode 160000 hw/mcu/st/cmsis_device_h7rs create mode 160000 hw/mcu/st/cmsis_device_n6 create mode 160000 hw/mcu/st/stm32h7rsxx_hal_driver create mode 160000 hw/mcu/st/stm32n6xx_hal_driver create mode 160000 lib/CMSIS_5 create mode 160000 lib/FreeRTOS-Kernel create mode 160000 lib/lwip create mode 160000 modules/crypto/mbedtls create mode 160000 modules/hal/cmsis create mode 160000 modules/hal/stm32 create mode 160000 tools/uf2 create mode 160000 zephyr (limited to 'tools') diff --git a/hw/bsp/stm32n6/partition_stm32n657xx.h b/hw/bsp/stm32n6/partition_stm32n657xx.h index 713068609..4efdc5668 100644 --- a/hw/bsp/stm32n6/partition_stm32n657xx.h +++ b/hw/bsp/stm32n6/partition_stm32n657xx.h @@ -785,7 +785,7 @@ __STATIC_INLINE void TZ_SAU_Setup (void) #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif + #endif } diff --git a/hw/mcu/st/cmsis_device_h7rs b/hw/mcu/st/cmsis_device_h7rs new file mode 160000 index 000000000..832649d1f --- /dev/null +++ b/hw/mcu/st/cmsis_device_h7rs @@ -0,0 +1 @@ +Subproject commit 832649d1fd09bd901e9f68e979522e5c209ebf20 diff --git a/hw/mcu/st/cmsis_device_n6 b/hw/mcu/st/cmsis_device_n6 new file mode 160000 index 000000000..f818b00f7 --- /dev/null +++ b/hw/mcu/st/cmsis_device_n6 @@ -0,0 +1 @@ +Subproject commit f818b00f775444e8d19ef6cad822534c345e054f diff --git a/hw/mcu/st/stm32h7rsxx_hal_driver b/hw/mcu/st/stm32h7rsxx_hal_driver new file mode 160000 index 000000000..7ca2e07ca --- /dev/null +++ b/hw/mcu/st/stm32h7rsxx_hal_driver @@ -0,0 +1 @@ +Subproject commit 7ca2e07ca21bc66b53654e845b4c85c884343b60 diff --git a/hw/mcu/st/stm32n6xx_hal_driver b/hw/mcu/st/stm32n6xx_hal_driver new file mode 160000 index 000000000..49f9989d1 --- /dev/null +++ b/hw/mcu/st/stm32n6xx_hal_driver @@ -0,0 +1 @@ +Subproject commit 49f9989d10cf6817d4b07ac01848956b46bd0fd6 diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 new file mode 160000 index 000000000..2b7495b85 --- /dev/null +++ b/lib/CMSIS_5 @@ -0,0 +1 @@ +Subproject commit 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c diff --git a/lib/FreeRTOS-Kernel b/lib/FreeRTOS-Kernel new file mode 160000 index 000000000..cc0e0707c --- /dev/null +++ b/lib/FreeRTOS-Kernel @@ -0,0 +1 @@ +Subproject commit cc0e0707c0c748713485b870bb980852b210877f diff --git a/lib/lwip b/lib/lwip new file mode 160000 index 000000000..159e31b68 --- /dev/null +++ b/lib/lwip @@ -0,0 +1 @@ +Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10 diff --git a/modules/crypto/mbedtls b/modules/crypto/mbedtls new file mode 160000 index 000000000..5f8899343 --- /dev/null +++ b/modules/crypto/mbedtls @@ -0,0 +1 @@ +Subproject commit 5f889934359deccf421554c7045a8381ef75298f diff --git a/modules/hal/cmsis b/modules/hal/cmsis new file mode 160000 index 000000000..d1b8b20b6 --- /dev/null +++ b/modules/hal/cmsis @@ -0,0 +1 @@ +Subproject commit d1b8b20b6278615b00e136374540eb1c00dcabe7 diff --git a/modules/hal/stm32 b/modules/hal/stm32 new file mode 160000 index 000000000..5cbc642b1 --- /dev/null +++ b/modules/hal/stm32 @@ -0,0 +1 @@ +Subproject commit 5cbc642b1a79d4f373b1587f8c3027f31bf0d30c diff --git a/tools/uf2 b/tools/uf2 new file mode 160000 index 000000000..c594542b2 --- /dev/null +++ b/tools/uf2 @@ -0,0 +1 @@ +Subproject commit c594542b2faa01cc33a2b97c9fbebc38549df80a diff --git a/zephyr b/zephyr new file mode 160000 index 000000000..c2c1495b4 --- /dev/null +++ b/zephyr @@ -0,0 +1 @@ +Subproject commit c2c1495b4c523a679a57e7b72891c02a34351f43 -- cgit v1.3.1 From efc8c08a66517054f38213be2e191ea60ac04333 Mon Sep 17 00:00:00 2001 From: James Sandison Date: Wed, 4 Jun 2025 11:42:21 +1000 Subject: chore: delete accidentally commited submodules --- hw/mcu/st/cmsis_device_h7rs | 1 - hw/mcu/st/cmsis_device_n6 | 1 - hw/mcu/st/stm32h7rsxx_hal_driver | 1 - hw/mcu/st/stm32n6xx_hal_driver | 1 - lib/CMSIS_5 | 1 - lib/FreeRTOS-Kernel | 1 - lib/lwip | 1 - modules/crypto/mbedtls | 1 - modules/hal/cmsis | 1 - modules/hal/stm32 | 1 - tools/uf2 | 1 - zephyr | 1 - 12 files changed, 12 deletions(-) delete mode 160000 hw/mcu/st/cmsis_device_h7rs delete mode 160000 hw/mcu/st/cmsis_device_n6 delete mode 160000 hw/mcu/st/stm32h7rsxx_hal_driver delete mode 160000 hw/mcu/st/stm32n6xx_hal_driver delete mode 160000 lib/CMSIS_5 delete mode 160000 lib/FreeRTOS-Kernel delete mode 160000 lib/lwip delete mode 160000 modules/crypto/mbedtls delete mode 160000 modules/hal/cmsis delete mode 160000 modules/hal/stm32 delete mode 160000 tools/uf2 delete mode 160000 zephyr (limited to 'tools') diff --git a/hw/mcu/st/cmsis_device_h7rs b/hw/mcu/st/cmsis_device_h7rs deleted file mode 160000 index 832649d1f..000000000 --- a/hw/mcu/st/cmsis_device_h7rs +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 832649d1fd09bd901e9f68e979522e5c209ebf20 diff --git a/hw/mcu/st/cmsis_device_n6 b/hw/mcu/st/cmsis_device_n6 deleted file mode 160000 index f818b00f7..000000000 --- a/hw/mcu/st/cmsis_device_n6 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f818b00f775444e8d19ef6cad822534c345e054f diff --git a/hw/mcu/st/stm32h7rsxx_hal_driver b/hw/mcu/st/stm32h7rsxx_hal_driver deleted file mode 160000 index 7ca2e07ca..000000000 --- a/hw/mcu/st/stm32h7rsxx_hal_driver +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7ca2e07ca21bc66b53654e845b4c85c884343b60 diff --git a/hw/mcu/st/stm32n6xx_hal_driver b/hw/mcu/st/stm32n6xx_hal_driver deleted file mode 160000 index 49f9989d1..000000000 --- a/hw/mcu/st/stm32n6xx_hal_driver +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 49f9989d10cf6817d4b07ac01848956b46bd0fd6 diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 deleted file mode 160000 index 2b7495b85..000000000 --- a/lib/CMSIS_5 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c diff --git a/lib/FreeRTOS-Kernel b/lib/FreeRTOS-Kernel deleted file mode 160000 index cc0e0707c..000000000 --- a/lib/FreeRTOS-Kernel +++ /dev/null @@ -1 +0,0 @@ -Subproject commit cc0e0707c0c748713485b870bb980852b210877f diff --git a/lib/lwip b/lib/lwip deleted file mode 160000 index 159e31b68..000000000 --- a/lib/lwip +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10 diff --git a/modules/crypto/mbedtls b/modules/crypto/mbedtls deleted file mode 160000 index 5f8899343..000000000 --- a/modules/crypto/mbedtls +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 5f889934359deccf421554c7045a8381ef75298f diff --git a/modules/hal/cmsis b/modules/hal/cmsis deleted file mode 160000 index d1b8b20b6..000000000 --- a/modules/hal/cmsis +++ /dev/null @@ -1 +0,0 @@ -Subproject commit d1b8b20b6278615b00e136374540eb1c00dcabe7 diff --git a/modules/hal/stm32 b/modules/hal/stm32 deleted file mode 160000 index 5cbc642b1..000000000 --- a/modules/hal/stm32 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 5cbc642b1a79d4f373b1587f8c3027f31bf0d30c diff --git a/tools/uf2 b/tools/uf2 deleted file mode 160000 index c594542b2..000000000 --- a/tools/uf2 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c594542b2faa01cc33a2b97c9fbebc38549df80a diff --git a/zephyr b/zephyr deleted file mode 160000 index c2c1495b4..000000000 --- a/zephyr +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c2c1495b4c523a679a57e7b72891c02a34351f43 -- cgit v1.3.1 From b56265f38182b71e39179a88ddaeca4786e6b780 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 10 Jun 2025 22:28:03 +0700 Subject: merge all maxim (32650, 32666, 32690, 78002) family into common bsp/maxim. Only support cmake build system rename hw/mcu/analog/max32 to hw/mcu/analog/msdk --- .github/workflows/ci_set_matrix.py | 2 +- hw/bsp/espressif/family.cmake | 2 - hw/bsp/family_support.cmake | 16 +- hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h | 149 ---------------- hw/bsp/max32650/README.md | 46 ----- hw/bsp/max32650/boards/max32650evkit/board.cmake | 10 -- hw/bsp/max32650/boards/max32650evkit/board.h | 61 ------- hw/bsp/max32650/boards/max32650evkit/board.mk | 2 - hw/bsp/max32650/boards/max32650evkit/max32650.ld | 119 ------------- hw/bsp/max32650/boards/max32650fthr/board.cmake | 10 -- hw/bsp/max32650/boards/max32650fthr/board.h | 62 ------- hw/bsp/max32650/boards/max32650fthr/board.mk | 2 - hw/bsp/max32650/boards/max32650fthr/max32650.ld | 119 ------------- hw/bsp/max32650/boards/max32651evkit/board.cmake | 30 ---- hw/bsp/max32650/boards/max32651evkit/board.h | 61 ------- hw/bsp/max32650/boards/max32651evkit/board.mk | 5 - hw/bsp/max32650/boards/max32651evkit/max32651.ld | 132 -------------- hw/bsp/max32650/family.c | 177 ------------------- hw/bsp/max32650/family.cmake | 169 ------------------ hw/bsp/max32650/family.mk | 140 --------------- hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h | 149 ---------------- hw/bsp/max32666/README.md | 32 ---- hw/bsp/max32666/boards/max32666evkit/board.cmake | 1 - hw/bsp/max32666/boards/max32666evkit/board.h | 62 ------- hw/bsp/max32666/boards/max32666evkit/board.mk | 1 - hw/bsp/max32666/boards/max32666fthr/board.cmake | 1 - hw/bsp/max32666/boards/max32666fthr/board.h | 62 ------- hw/bsp/max32666/boards/max32666fthr/board.mk | 1 - hw/bsp/max32666/family.c | 177 ------------------- hw/bsp/max32666/family.cmake | 147 ---------------- hw/bsp/max32666/family.mk | 93 ---------- hw/bsp/max32666/max32666.ld | 135 -------------- hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h | 149 ---------------- hw/bsp/max32690/README.md | 31 ---- hw/bsp/max32690/boards/apard32690/board.cmake | 1 - hw/bsp/max32690/boards/apard32690/board.h | 61 ------- hw/bsp/max32690/boards/apard32690/board.mk | 1 - hw/bsp/max32690/boards/max32690evkit/board.cmake | 1 - hw/bsp/max32690/boards/max32690evkit/board.h | 61 ------- hw/bsp/max32690/boards/max32690evkit/board.mk | 1 - hw/bsp/max32690/family.c | 175 ------------------- hw/bsp/max32690/family.cmake | 152 ---------------- hw/bsp/max32690/family.mk | 101 ----------- hw/bsp/max32690/max32690.ld | 164 ----------------- hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h | 149 ---------------- hw/bsp/max78002/README.md | 28 --- hw/bsp/max78002/boards/max78002evkit/board.cmake | 1 - hw/bsp/max78002/boards/max78002evkit/board.h | 63 ------- hw/bsp/max78002/boards/max78002evkit/board.mk | 1 - hw/bsp/max78002/family.c | 173 ------------------ hw/bsp/max78002/family.cmake | 166 ------------------ hw/bsp/max78002/family.mk | 99 ----------- hw/bsp/max78002/max78002.ld | 182 ------------------- hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h | 149 ++++++++++++++++ hw/bsp/maxim/README.md | 43 +++++ hw/bsp/maxim/boards/apard32690/board.cmake | 4 + hw/bsp/maxim/boards/apard32690/board.h | 61 +++++++ hw/bsp/maxim/boards/max32650evkit/board.cmake | 8 + hw/bsp/maxim/boards/max32650evkit/board.h | 61 +++++++ hw/bsp/maxim/boards/max32650fthr/board.cmake | 8 + hw/bsp/maxim/boards/max32650fthr/board.h | 62 +++++++ hw/bsp/maxim/boards/max32651evkit/board.cmake | 31 ++++ hw/bsp/maxim/boards/max32651evkit/board.h | 61 +++++++ hw/bsp/maxim/boards/max32666evkit/board.cmake | 4 + hw/bsp/maxim/boards/max32666evkit/board.h | 62 +++++++ hw/bsp/maxim/boards/max32666fthr/board.cmake | 4 + hw/bsp/maxim/boards/max32666fthr/board.h | 62 +++++++ hw/bsp/maxim/boards/max32690evkit/board.cmake | 4 + hw/bsp/maxim/boards/max32690evkit/board.h | 61 +++++++ hw/bsp/maxim/boards/max78002evkit/board.cmake | 4 + hw/bsp/maxim/boards/max78002evkit/board.h | 63 +++++++ hw/bsp/maxim/family.c | 213 +++++++++++++++++++++++ hw/bsp/maxim/family.cmake | 205 ++++++++++++++++++++++ hw/bsp/maxim/linker/max32650.ld | 119 +++++++++++++ hw/bsp/maxim/linker/max32651.ld | 132 ++++++++++++++ hw/bsp/maxim/linker/max32665.ld | 135 ++++++++++++++ hw/bsp/maxim/linker/max32690.ld | 164 +++++++++++++++++ hw/bsp/maxim/linker/max78002.ld | 182 +++++++++++++++++++ tools/get_deps.py | 4 +- 79 files changed, 1916 insertions(+), 3925 deletions(-) delete mode 100644 hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h delete mode 100644 hw/bsp/max32650/README.md delete mode 100644 hw/bsp/max32650/boards/max32650evkit/board.cmake delete mode 100644 hw/bsp/max32650/boards/max32650evkit/board.h delete mode 100644 hw/bsp/max32650/boards/max32650evkit/board.mk delete mode 100644 hw/bsp/max32650/boards/max32650evkit/max32650.ld delete mode 100644 hw/bsp/max32650/boards/max32650fthr/board.cmake delete mode 100644 hw/bsp/max32650/boards/max32650fthr/board.h delete mode 100644 hw/bsp/max32650/boards/max32650fthr/board.mk delete mode 100644 hw/bsp/max32650/boards/max32650fthr/max32650.ld delete mode 100644 hw/bsp/max32650/boards/max32651evkit/board.cmake delete mode 100644 hw/bsp/max32650/boards/max32651evkit/board.h delete mode 100644 hw/bsp/max32650/boards/max32651evkit/board.mk delete mode 100644 hw/bsp/max32650/boards/max32651evkit/max32651.ld delete mode 100644 hw/bsp/max32650/family.c delete mode 100644 hw/bsp/max32650/family.cmake delete mode 100644 hw/bsp/max32650/family.mk delete mode 100644 hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h delete mode 100644 hw/bsp/max32666/README.md delete mode 100644 hw/bsp/max32666/boards/max32666evkit/board.cmake delete mode 100644 hw/bsp/max32666/boards/max32666evkit/board.h delete mode 100644 hw/bsp/max32666/boards/max32666evkit/board.mk delete mode 100644 hw/bsp/max32666/boards/max32666fthr/board.cmake delete mode 100644 hw/bsp/max32666/boards/max32666fthr/board.h delete mode 100644 hw/bsp/max32666/boards/max32666fthr/board.mk delete mode 100644 hw/bsp/max32666/family.c delete mode 100644 hw/bsp/max32666/family.cmake delete mode 100644 hw/bsp/max32666/family.mk delete mode 100644 hw/bsp/max32666/max32666.ld delete mode 100644 hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h delete mode 100644 hw/bsp/max32690/README.md delete mode 100644 hw/bsp/max32690/boards/apard32690/board.cmake delete mode 100644 hw/bsp/max32690/boards/apard32690/board.h delete mode 100644 hw/bsp/max32690/boards/apard32690/board.mk delete mode 100644 hw/bsp/max32690/boards/max32690evkit/board.cmake delete mode 100644 hw/bsp/max32690/boards/max32690evkit/board.h delete mode 100644 hw/bsp/max32690/boards/max32690evkit/board.mk delete mode 100644 hw/bsp/max32690/family.c delete mode 100644 hw/bsp/max32690/family.cmake delete mode 100644 hw/bsp/max32690/family.mk delete mode 100644 hw/bsp/max32690/max32690.ld delete mode 100644 hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h delete mode 100644 hw/bsp/max78002/README.md delete mode 100644 hw/bsp/max78002/boards/max78002evkit/board.cmake delete mode 100644 hw/bsp/max78002/boards/max78002evkit/board.h delete mode 100644 hw/bsp/max78002/boards/max78002evkit/board.mk delete mode 100644 hw/bsp/max78002/family.c delete mode 100644 hw/bsp/max78002/family.cmake delete mode 100644 hw/bsp/max78002/family.mk delete mode 100644 hw/bsp/max78002/max78002.ld create mode 100644 hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/maxim/README.md create mode 100644 hw/bsp/maxim/boards/apard32690/board.cmake create mode 100644 hw/bsp/maxim/boards/apard32690/board.h create mode 100644 hw/bsp/maxim/boards/max32650evkit/board.cmake create mode 100644 hw/bsp/maxim/boards/max32650evkit/board.h create mode 100644 hw/bsp/maxim/boards/max32650fthr/board.cmake create mode 100644 hw/bsp/maxim/boards/max32650fthr/board.h create mode 100644 hw/bsp/maxim/boards/max32651evkit/board.cmake create mode 100644 hw/bsp/maxim/boards/max32651evkit/board.h create mode 100644 hw/bsp/maxim/boards/max32666evkit/board.cmake create mode 100644 hw/bsp/maxim/boards/max32666evkit/board.h create mode 100644 hw/bsp/maxim/boards/max32666fthr/board.cmake create mode 100644 hw/bsp/maxim/boards/max32666fthr/board.h create mode 100644 hw/bsp/maxim/boards/max32690evkit/board.cmake create mode 100644 hw/bsp/maxim/boards/max32690evkit/board.h create mode 100644 hw/bsp/maxim/boards/max78002evkit/board.cmake create mode 100644 hw/bsp/maxim/boards/max78002evkit/board.h create mode 100644 hw/bsp/maxim/family.c create mode 100644 hw/bsp/maxim/family.cmake create mode 100644 hw/bsp/maxim/linker/max32650.ld create mode 100644 hw/bsp/maxim/linker/max32651.ld create mode 100644 hw/bsp/maxim/linker/max32665.ld create mode 100644 hw/bsp/maxim/linker/max32690.ld create mode 100644 hw/bsp/maxim/linker/max78002.ld (limited to 'tools') diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index fa73dc1b6..bccb07e3e 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -24,7 +24,7 @@ family_list = { "lpc11 lpc13 lpc15": ["arm-gcc", "arm-clang"], "lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"], "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"], - "max32650 max32666 max32690 max78002": ["arm-gcc"], + "maxim": ["arm-gcc"], "mcx": ["arm-gcc"], "mm32": ["arm-gcc"], "msp430": ["msp430-gcc"], diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index b544689d9..2aad7d185 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -32,8 +32,6 @@ endif () # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") - -# set SDKCONFIG for each IDF Target set(SDKCONFIG ${CMAKE_BINARY_DIR}/sdkconfig) include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 3a6890690..ac1276f7d 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -482,7 +482,7 @@ function(family_flash_openocd TARGET) # note skip verify since it has issue with rp2040 add_custom_target(${TARGET}-openocd DEPENDS ${TARGET} - COMMAND ${OPENOCD} -c "tcl_port disabled" -c "gdb_port disabled" ${OPTION_LIST} -c init -c halt -c "program $" -c reset ${OPTION_LIST2} -c exit + COMMAND ${OPENOCD} -c "tcl_port disabled; gdb_port disabled" ${OPTION_LIST} -c "init; halt; program $" -c reset ${OPTION_LIST2} -c exit VERBATIM ) endfunction() @@ -502,10 +502,16 @@ endfunction() # Add flash openocd adi (Analog Devices) target # included with msdk or compiled from release branch of https://github.com/analogdevicesinc/openocd function(family_flash_openocd_adi TARGET) - if (DEFINED $ENV{MAXIM_PATH}) - # use openocd from msdk - set(OPENOCD ENV{MAXIM_PATH}/Tools/OpenOCD/openocd) - set(OPENOCD_OPTION2 "-s ENV{MAXIM_PATH}/Tools/OpenOCD/scripts") + if (DEFINED MAXIM_PATH) + # use openocd from msdk with MAXIM_PATH cmake variable first if the user specified it + set(OPENOCD ${MAXIM_PATH}/Tools/OpenOCD/openocd) + set(OPENOCD_OPTION2 "-s ${MAXIM_PATH}/Tools/OpenOCD/scripts") + elseif (DEFINED ENV{MAXIM_PATH}) + # use openocd from msdk with MAXIM_PATH environment variable. Normalize + # since msdk can be Windows (MinGW) or Linux + file(TO_CMAKE_PATH "$ENV{MAXIM_PATH}" MAXIM_PATH_NORM) + set(OPENOCD ${MAXIM_PATH_NORM}/Tools/OpenOCD/openocd) + set(OPENOCD_OPTION2 "-s ${MAXIM_PATH_NORM}/Tools/OpenOCD/scripts") else() # compiled from source if (NOT DEFINED OPENOCD_ADI_PATH) diff --git a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h deleted file mode 100644 index e5a76af85..000000000 --- a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.0 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -// skip if included from IAR assembler -#ifndef __IASMARM__ - #include "mxc_device.h" -#endif - -/* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configCPU_CLOCK_HZ SystemCoreClock -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) -#define configMAX_TASK_NAME_LEN 16 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 4 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TIME_SLICING 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Hook function related definitions. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configCHECK_HANDLER_INSTALLATION 0 - -/* Run time and task stats gathering related definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define configRECORD_STACK_HIGH_ADDRESS 1 -#define configUSE_TRACE_FACILITY 1 // legacy trace -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) -#define configTIMER_QUEUE_LENGTH 32 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Optional functions - most linkers will remove unused functions anyway. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY -#define INCLUDE_xResumeFromISR 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 -#define INCLUDE_pcTaskGetTaskName 0 -#define INCLUDE_eTaskGetState 0 -#define INCLUDE_xEventGroupSetBitFromISR 0 -#define INCLUDE_xTimerPendFunctionCall 0 - -/* FreeRTOS hooks to NVIC vectors */ -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler -#define vPortSVCHandler SVC_Handler - -//--------------------------------------------------------------------+ -// Interrupt nesting behavior configuration. -//--------------------------------------------------------------------+ - -// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header -#define configPRIO_BITS __NVIC_PRIO_BITS - -/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake. - -Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP -compatible debug probe. However, at the time of writing, the necessary flashing -algorithms for OpenOCD have not yet been incorporated into the OpenOCD master -branch. To utilize the provided debug probes, please install the bundled MSDK -package which includes the appropriate OpenOCD modifications. To leverage this -OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake -target. - -### MAX32651 - -The MAX32651 features an integrated secure bootloader which requires the -application image be signed prior to flashing. Both the Makefile and CMake -scripts account for this signing automatically when building for the -MAX32651EVKIT. - -To flash the signed image, the MSDK's OpenOCD variant must be used. To flash -the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk` -and `-msdk` rule and target. diff --git a/hw/bsp/max32650/boards/max32650evkit/board.cmake b/hw/bsp/max32650/boards/max32650evkit/board.cmake deleted file mode 100644 index fffdcc9fb..000000000 --- a/hw/bsp/max32650/boards/max32650evkit/board.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# Use the standard, non-secure linker file -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) - -function(update_board_extras TARGET) - #No extra arguments -endfunction() - -function(prepare_image TARGET_IN) - #No signing required -endfunction() diff --git a/hw/bsp/max32650/boards/max32650evkit/board.h b/hw/bsp/max32650/boards/max32650evkit/board.h deleted file mode 100644 index 65ed2659e..000000000 --- a/hw/bsp/max32650/boards/max32650evkit/board.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: MAX32650 EVKIT - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO2 -#define LED_PIN MXC_GPIO_PIN_25 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT MXC_GPIO2 -#define BUTTON_PIN MXC_GPIO_PIN_28 -#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP -#define BUTTON_STATE_ACTIVE 0 - -// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 0 - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32650/boards/max32650evkit/board.mk b/hw/bsp/max32650/boards/max32650evkit/board.mk deleted file mode 100644 index 0bc210e11..000000000 --- a/hw/bsp/max32650/boards/max32650evkit/board.mk +++ /dev/null @@ -1,2 +0,0 @@ -# Use the standard, non-secure linker file -LD_FILE = $(BOARD_PATH)/max32650.ld diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/max32650/boards/max32650evkit/max32650.ld deleted file mode 100644 index 0e56a91ec..000000000 --- a/hw/bsp/max32650/boards/max32650evkit/max32650.ld +++ /dev/null @@ -1,119 +0,0 @@ -MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ -} - -SECTIONS { - .text : - { - _text = .; - KEEP(*(.isr_vector)) - *(.text*) /* program code */ - *(.rodata*) /* read-only data: "const" */ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* C++ Exception handling */ - KEEP(*(.eh_frame*)) - _etext = .; - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - /* it's used for C++ exception handling */ - /* we need to keep this to avoid overlapping */ - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - - .data : - { - _data = ALIGN(., 4); - *(vtable) - *(.data*) /*read-write initialized data: initialized global variable*/ - *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ - *(.flashprog*) /* Flash program */ - - - /* These array sections are used by __libc_init_array to call static C++ constructors */ - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - _edata = ALIGN(., 4); - } > SRAM AT>FLASH - __load_data = LOADADDR(.data); - .bss : - { - . = ALIGN(4); - _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ - *(COMMON) - _ebss = ALIGN(., 4); - } > SRAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > SRAM - - .heap (COPY): - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - *(.heap*) - __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM - - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") -} diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake deleted file mode 100644 index fffdcc9fb..000000000 --- a/hw/bsp/max32650/boards/max32650fthr/board.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# Use the standard, non-secure linker file -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) - -function(update_board_extras TARGET) - #No extra arguments -endfunction() - -function(prepare_image TARGET_IN) - #No signing required -endfunction() diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/max32650/boards/max32650fthr/board.h deleted file mode 100644 index 755fa15b5..000000000 --- a/hw/bsp/max32650/boards/max32650fthr/board.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: MAX32650 Feather - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO1 -#define LED_PIN MXC_GPIO_PIN_14 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIO -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT MXC_GPIO1 -#define BUTTON_PIN MXC_GPIO_PIN_19 -#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP -#define BUTTON_STATE_ACTIVE 0 - -// UART Enable for SWD UART Pins. Pin Mux handled by the HAL -#define UART_NUM 0 - - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk deleted file mode 100644 index 0bc210e11..000000000 --- a/hw/bsp/max32650/boards/max32650fthr/board.mk +++ /dev/null @@ -1,2 +0,0 @@ -# Use the standard, non-secure linker file -LD_FILE = $(BOARD_PATH)/max32650.ld diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld deleted file mode 100644 index 0e56a91ec..000000000 --- a/hw/bsp/max32650/boards/max32650fthr/max32650.ld +++ /dev/null @@ -1,119 +0,0 @@ -MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ -} - -SECTIONS { - .text : - { - _text = .; - KEEP(*(.isr_vector)) - *(.text*) /* program code */ - *(.rodata*) /* read-only data: "const" */ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* C++ Exception handling */ - KEEP(*(.eh_frame*)) - _etext = .; - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - /* it's used for C++ exception handling */ - /* we need to keep this to avoid overlapping */ - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - - .data : - { - _data = ALIGN(., 4); - *(vtable) - *(.data*) /*read-write initialized data: initialized global variable*/ - *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ - *(.flashprog*) /* Flash program */ - - - /* These array sections are used by __libc_init_array to call static C++ constructors */ - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - _edata = ALIGN(., 4); - } > SRAM AT>FLASH - __load_data = LOADADDR(.data); - .bss : - { - . = ALIGN(4); - _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ - *(COMMON) - _ebss = ALIGN(., 4); - } > SRAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > SRAM - - .heap (COPY): - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - *(.heap*) - __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM - - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") -} diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/max32650/boards/max32651evkit/board.cmake deleted file mode 100644 index bd8077a42..000000000 --- a/hw/bsp/max32650/boards/max32651evkit/board.cmake +++ /dev/null @@ -1,30 +0,0 @@ -# Use the secure linker file -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld) - -function(update_board_extras TARGET) - # for the signed target, need to add the __SLA_FWK__ define - target_compile_definitions(${TARGET} PUBLIC - __SLA_FWK__ - ) -endfunction() - -function(prepare_image TARGET_IN) - #For the signed target, set up a POST_BUILD command to sign the elf file once - #created - if((WIN32) OR (MINGW) OR (MSYS)) - set(SIGN_EXE "sign_app.exe") - else() - set(SIGN_EXE "sign_app") - endif() - set(MCU_PATH "${TOP}/hw/mcu/analog/max32/") - - # Custom POST_BUILD command - add_custom_command( - TARGET ${TARGET_IN} POST_BUILD - COMMAND ${CMAKE_OBJCOPY} $ -R .sig -O binary $/${TARGET_IN}.bin - COMMAND ${MCU_PATH}/Tools/SBT/bin/${SIGN_EXE} -c MAX32651 key_file=${MCU_PATH}/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key - ca=$/${TARGET_IN}.bin sca=$/${TARGET_IN}.sbin - COMMAND ${CMAKE_OBJCOPY} $ --update-section .sig=$/${TARGET_IN}.sig - VERBATIM - ) -endfunction() diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/max32650/boards/max32651evkit/board.h deleted file mode 100644 index 0b49ff309..000000000 --- a/hw/bsp/max32650/boards/max32651evkit/board.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: MAX32651 EVKIT - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO2 -#define LED_PIN MXC_GPIO_PIN_25 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT MXC_GPIO2 -#define BUTTON_PIN MXC_GPIO_PIN_28 -#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP -#define BUTTON_STATE_ACTIVE 0 - -// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 0 - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/max32650/boards/max32651evkit/board.mk deleted file mode 100644 index b609598c1..000000000 --- a/hw/bsp/max32650/boards/max32651evkit/board.mk +++ /dev/null @@ -1,5 +0,0 @@ -# Use the secure linker file -LD_FILE = $(BOARD_PATH)/max32651.ld - -# Let the family script know the build needs to be signed -SIGNED_BUILD := 1 diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/max32650/boards/max32651evkit/max32651.ld deleted file mode 100644 index 3921d10f2..000000000 --- a/hw/bsp/max32650/boards/max32651evkit/max32651.ld +++ /dev/null @@ -1,132 +0,0 @@ -MEMORY { - HEADER (rx): ORIGIN = 0x10000000, LENGTH = 0x200 - FLASH (rx) : ORIGIN = 0x10000200, LENGTH = 0x002FFE00 /* 3MB flash */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ -} - -/* Added Oct 9, 2018 to go to correct reset vector. */ -ENTRY(Reset_Handler) -PROVIDE( _start_SWAP = (((Reset_Handler) >> 24) | (((Reset_Handler) & 0x00FF0000) >> 8) | (((Reset_Handler) & 0x0000FF00) << 8) | ((Reset_Handler) << 24))); -PROVIDE_HIDDEN( _SLA_Size = _endimage - __end_header ); -PROVIDE( _SLA_Size_SWAP = (((_SLA_Size) >> 24) | (((_SLA_Size) & 0x00FF0000) >> 8) | (((_SLA_Size) & 0x0000FF00) << 8) | ((_SLA_Size) << 24))); - -/* Sections Definitions */ -SECTIONS { - .sb_sla_header : ALIGN(4) - { - FILL(0xFF) - KEEP(*(.sb_sla_header)) /* Header for ROM code */ - __end_header = . ; - . = ALIGN(512); - } > HEADER - - .text : - { - _text = .; - KEEP(*(.isr_vector)) - *(.text*) /* program code */ - *(.rodata*) /* read-only data: "const" */ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* C++ Exception handling */ - KEEP(*(.eh_frame*)) - _etext = .; - } > FLASH - - /* it's used for C++ exception handling */ - /* we need to keep this to avoid overlapping */ - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } > FLASH - - .data : - { - _data = ALIGN(., 4); - *(.data*) /*read-write initialized data: initialized global variable*/ - *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ - *(.flashprog*) /* Flash program */ - - - /* These array sections are used by __libc_init_array to call static C++ constructors */ - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - _edata = ALIGN(., 4); - } > SRAM AT>FLASH - __load_data = LOADADDR(.data); - _enddata = LOADADDR(.data)+SIZEOF(.data); - - .sb_sla_trailer : AT(_enddata) - { - KEEP(*(.sb_sla_trailer)) - /* Align image with 16 byte boundary to conform to flash encryption block size. */ - FILL(0xDEADC0DE); - /* NOTE: The FILL and ALIGN will not work unless something is written to the section. So, we use LONG. */ - LONG(0xDEADC0DE); - . = ALIGN(16); - } > FLASH - _endimage = LOADADDR(.sb_sla_trailer)+SIZEOF(.sb_sla_trailer); - .sig : - { - KEEP(*(.sig)) - LONG(0xDEADBEEF); - - } > FLASH - .bss : - { - . = ALIGN(4); - _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ - *(COMMON) - _ebss = ALIGN(., 4); - } > SRAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > SRAM - - .heap (COPY): - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - *(.heap*) - __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM - - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") -} diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c deleted file mode 100644 index 8f0e56734..000000000 --- a/hw/bsp/max32650/family.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - manufacturer: Analog Devices -*/ - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() -#endif - -#include "gpio.h" -#include "mxc_sys.h" -#include "mxc_device.h" -#include "uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "board.h" -#include "bsp/board_api.h" - - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB_IRQHandler(void) { - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ -mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); - -void board_init(void) { -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - mxc_gpio_cfg_t gpioConfig; - - // LED - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_OUT; - gpioConfig.mask = LED_PIN; - gpioConfig.pad = MXC_GPIO_PAD_NONE; - gpioConfig.port = LED_PORT; - gpioConfig.vssel = LED_VDDIO; - MXC_GPIO_Config(&gpioConfig); - board_led_write(false); - - // Button - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_IN; - gpioConfig.mask = BUTTON_PIN; - gpioConfig.pad = BUTTON_PULL; - gpioConfig.port = BUTTON_PORT; - gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; - MXC_GPIO_Config(&gpioConfig); - - // UART - MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE); - - //USB - // Startup the HIRC96M clock if it's not on already - if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) { - MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN; - MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY); - } - - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); - MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { -#if LED_STATE_ON - state = !state; -#endif - if (state) { - MXC_GPIO_OutClr(LED_PORT, LED_PIN); - } else { - MXC_GPIO_OutSet(LED_PORT, LED_PIN); - } -} - -uint32_t board_button_read(void) { - uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; - return BUTTON_STATE_ACTIVE == state; -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[13];//USN Buffer - MXC_SYS_GetUSN(hw_id, 13); - - size_t act_len = TU_MIN(max_len, 13); - memcpy(id, hw_id, act_len); - return act_len; -} - -int board_uart_read(uint8_t *buf, int len) { - int uart_val; - int act_len = 0; - - while (act_len < len) { - if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { - break; - } else { - *buf++ = (uint8_t) uart_val; - act_len++; - } - } - return act_len; -} - -int board_uart_write(void const *buf, int len) { - int act_len = 0; - const uint8_t *ch_ptr = (const uint8_t *) buf; - while (act_len < len) { - MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); - act_len++; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - -void HardFault_Handler(void) { - __asm("BKPT #0\n"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) { -} diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake deleted file mode 100644 index b1d5dded7..000000000 --- a/hw/bsp/max32650/family.cmake +++ /dev/null @@ -1,169 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific information and functions -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max32650) -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg") - -set(FAMILY_MCUS MAX32650 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX32650 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX32650 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX32650 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) - - # Run any board specific updates - update_board_extras(${TARGET}) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/header_MAX32650.c - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_me10.c - ${PERIPH_SRC}/SYS/sys_me10.c - ${PERIPH_SRC}/TPU/tpu_me10.c - ${PERIPH_SRC}/TPU/tpu_reva.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_me10.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_me10.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_me10.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/ICC/icc_common.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_me10.c - ${PERIPH_SRC}/UART/uart_reva.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include - ${MAX32_PERIPH}/Include/MAX32650 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/TPU - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - -u sb_header #Needed when linking libraries to not lose the Signing header - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32650) - target_sources(${TARGET} PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - - - # Flashing - family_add_bin_hex(${TARGET}) - family_flash_jlink(${TARGET}) - family_flash_openocd_adi(${TARGET}) - - # Add the optional MSDK OpenOCD flashing - family_flash_msdk(${TARGET}) -endfunction() - -function(family_flash_msdk TARGET) - # Prepare the image (signed) if the board requires it - prepare_image(${TARGET}) - - set(MAXIM_PATH "$ENV{MAXIM_PATH}") - add_custom_target(${TARGET}-msdk - DEPENDS ${TARGET} - COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts - -f interface/cmsis-dap.cfg -f target/max32650.cfg - -c "program $ verify; init; reset; exit" - VERBATIM - ) -endfunction() diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk deleted file mode 100644 index d2fc293e4..000000000 --- a/hw/bsp/max32650/family.mk +++ /dev/null @@ -1,140 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX32650/1/2 SDK -CFLAGS += -DTARGET=MAX32650 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX32650 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX32650 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes \ - -Wno-error=unused-parameter \ - -Wno-error=cast-align \ - -Wno-error=cast-qual \ - -Wno-error=sign-compare - -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# Configure the flash rule. By default, use JLink. -SIGNED_BUILD ?= 0 -DEFAULT_FLASH = flash-jlink - -# If the applications needs to be signed (for the MAX32651), sign it first and -# then need to use MSDK's OpenOCD to flash it -# Also need to include the __SLA_FWK__ define to enable the signed header into -# memory -ifeq ($(SIGNED_BUILD), 1) -# Extra definitions to build for the secure part -CFLAGS += -D__SLA_FWK__ -DEFAULT_FLASH := sign-build flash-msdk -endif - -# For flash-jlink target -JLINK_DEVICE = max32650 - -# Configure the flash rule -flash: $(DEFAULT_FLASH) - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_me10.c \ - $(PERIPH_SRC)/SYS/sys_me10.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_me10.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_me10.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_me10.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/ICC/icc_common.c \ - $(PERIPH_SRC)/TPU/tpu_me10.c \ - $(PERIPH_SRC)/TPU/tpu_reva.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_me10.c \ - $(PERIPH_SRC)/UART/uart_reva.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/TPU \ - $(PERIPH_SRC)/UART - - -# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the -# MAX32651 has a secure bootloader which requires the image to be signed before -# loading into flash. All MAX32651EVKIT's have the same key for evaluation -# purposes, so create a special flash rule to sign the binary and flash using -# the MSDK. -MCU_PATH = $(TOP)/hw/mcu/analog/max32/ -# Assume no extension for sign utility -SIGN_EXE = sign_app -ifeq ($(OS), Windows_NT) -# Must use .exe extension on Windows, since the binaries -# for Linux may live in the same place. -SIGN_EXE := sign_app.exe -else -UNAME = $(shell uname -s) -ifneq ($(findstring MSYS_NT,$(UNAME)),) -# Must also use .exe extension for MSYS2 -SIGN_EXE := sign_app.exe -endif -endif - -# Rule to sign the build. This will in-place modify the existing .elf file -# an populate the .sig section with the signature value -sign-build: $(BUILD)/$(PROJECT).elf - $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin - $(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \ - key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \ - ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin - $(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32650.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" diff --git a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h deleted file mode 100644 index e5a76af85..000000000 --- a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.0 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -// skip if included from IAR assembler -#ifndef __IASMARM__ - #include "mxc_device.h" -#endif - -/* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configCPU_CLOCK_HZ SystemCoreClock -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) -#define configMAX_TASK_NAME_LEN 16 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 4 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TIME_SLICING 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Hook function related definitions. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configCHECK_HANDLER_INSTALLATION 0 - -/* Run time and task stats gathering related definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define configRECORD_STACK_HIGH_ADDRESS 1 -#define configUSE_TRACE_FACILITY 1 // legacy trace -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) -#define configTIMER_QUEUE_LENGTH 32 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Optional functions - most linkers will remove unused functions anyway. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY -#define INCLUDE_xResumeFromISR 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 -#define INCLUDE_pcTaskGetTaskName 0 -#define INCLUDE_eTaskGetState 0 -#define INCLUDE_xEventGroupSetBitFromISR 0 -#define INCLUDE_xTimerPendFunctionCall 0 - -/* FreeRTOS hooks to NVIC vectors */ -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler -#define vPortSVCHandler SVC_Handler - -//--------------------------------------------------------------------+ -// Interrupt nesting behavior configuration. -//--------------------------------------------------------------------+ - -// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header -#define configPRIO_BITS __NVIC_PRIO_BITS - -/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake. - -Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP -compatible debug probe. However, at the time of writing, the necessary flashing -algorithms for OpenOCD have not yet been incorporated into the OpenOCD master -branch. To utilize the provided debug probes, please install the bundled MSDK -package which includes the appropriate OpenOCD modifications. To leverage this -OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake -target. diff --git a/hw/bsp/max32666/boards/max32666evkit/board.cmake b/hw/bsp/max32666/boards/max32666evkit/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32666/boards/max32666evkit/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32666/boards/max32666evkit/board.h b/hw/bsp/max32666/boards/max32666evkit/board.h deleted file mode 100644 index 54589444d..000000000 --- a/hw/bsp/max32666/boards/max32666evkit/board.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: MAX32666 EVKIT - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO1 -#define LED_PIN MXC_GPIO_PIN_14 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT MXC_GPIO1 -#define BUTTON_PIN MXC_GPIO_PIN_6 -#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP -#define BUTTON_STATE_ACTIVE 0 - -// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 1 -#define UART_MAP MAP_A - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32666/boards/max32666evkit/board.mk b/hw/bsp/max32666/boards/max32666evkit/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32666/boards/max32666evkit/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32666/boards/max32666fthr/board.cmake b/hw/bsp/max32666/boards/max32666fthr/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32666/boards/max32666fthr/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/max32666/boards/max32666fthr/board.h deleted file mode 100644 index 0caea5934..000000000 --- a/hw/bsp/max32666/boards/max32666fthr/board.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: MAX32666 Feather - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO0 -#define LED_PIN MXC_GPIO_PIN_29 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT MXC_GPIO1 -#define BUTTON_PIN MXC_GPIO_PIN_10 -#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP -#define BUTTON_STATE_ACTIVE 0 - -// UART Enable for UART on SWD. Pin Mux handled by the HAL -#define UART_NUM 1 -#define UART_MAP MAP_B - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32666/boards/max32666fthr/board.mk b/hw/bsp/max32666/boards/max32666fthr/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32666/boards/max32666fthr/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c deleted file mode 100644 index 05306c6c9..000000000 --- a/hw/bsp/max32666/family.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - manufacturer: Analog Devices -*/ - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() -#endif - -#include "gpio.h" -#include "mxc_sys.h" -#include "mcr_regs.h" -#include "mxc_device.h" -#include "uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "board.h" -#include "bsp/board_api.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB_IRQHandler(void) { - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ -mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); - -void board_init(void) { -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - mxc_gpio_cfg_t gpioConfig; - - // LED - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_OUT; - gpioConfig.mask = LED_PIN; - gpioConfig.pad = MXC_GPIO_PAD_NONE; - gpioConfig.port = LED_PORT; - gpioConfig.vssel = LED_VDDIO; - MXC_GPIO_Config(&gpioConfig); - board_led_write(false); - - // Button - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_IN; - gpioConfig.mask = BUTTON_PIN; - gpioConfig.pad = BUTTON_PULL; - gpioConfig.port = BUTTON_PORT; - gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; - MXC_GPIO_Config(&gpioConfig); - - // UART - MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, UART_MAP); - - //USB - // Startup the HIRC96M clock if it's not on already - if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) { - MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN; - } - - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); - MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { -#if LED_STATE_ON - state = !state; -#endif - if (state) { - MXC_GPIO_OutClr(LED_PORT, LED_PIN); - } else { - MXC_GPIO_OutSet(LED_PORT, LED_PIN); - } -} - -uint32_t board_button_read(void) { - uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; - return BUTTON_STATE_ACTIVE == state; -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checksum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); - - size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); - memcpy(id, hw_id, act_len); - return act_len; -} - -int board_uart_read(uint8_t *buf, int len) { - int uart_val; - int act_len = 0; - - while (act_len < len) { - if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { - break; - } else { - *buf++ = (uint8_t) uart_val; - act_len++; - } - } - return act_len; -} - -int board_uart_write(void const *buf, int len) { - int act_len = 0; - const uint8_t *ch_ptr = (const uint8_t *) buf; - while (act_len < len) { - MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); - act_len++; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - -void HardFault_Handler(void) { - __asm("BKPT #0\n"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) { -} diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake deleted file mode 100644 index 49798729a..000000000 --- a/hw/bsp/max32666/family.cmake +++ /dev/null @@ -1,147 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file from current location (family) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld) -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max32666) -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg") - -set(FAMILY_MCUS MAX32666 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX32665 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX32665 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX32666 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/system_max32665.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_me14.c - ${PERIPH_SRC}/SYS/sys_me14.c - ${PERIPH_SRC}/TPU/tpu_me14.c - ${PERIPH_SRC}/TPU/tpu_reva.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_me14.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_me14.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_me14.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_me14.c - ${PERIPH_SRC}/UART/uart_reva.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include - ${MAX32_PERIPH}/Include/MAX32665 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/TPU - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32666) - target_sources(${TARGET} PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - - - # Flashing - family_add_bin_hex(${TARGET}) - family_flash_jlink(${TARGET}) - family_flash_openocd_adi(${TARGET}) -endfunction() diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk deleted file mode 100644 index b4f7d1e57..000000000 --- a/hw/bsp/max32666/family.mk +++ /dev/null @@ -1,93 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S -LD_FILE = $(FAMILY_PATH)/max32666.ld - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX32665/6 SDK -CFLAGS += -DTARGET=MAX32665 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX32665 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX32666 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes \ - -Wno-error=unused-parameter \ - -Wno-error=cast-align \ - -Wno-error=cast-qual -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# For flash-jlink target -JLINK_DEVICE = max32666 - -# flash target using Jlink by default -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32665.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_me14.c \ - $(PERIPH_SRC)/SYS/sys_me14.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_me14.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_me14.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_me14.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/TPU/tpu_me14.c \ - $(PERIPH_SRC)/TPU/tpu_reva.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_me14.c \ - $(PERIPH_SRC)/UART/uart_reva.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/TPU \ - $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/max32666/max32666.ld deleted file mode 100644 index 06c124247..000000000 --- a/hw/bsp/max32666/max32666.ld +++ /dev/null @@ -1,135 +0,0 @@ -/* SPID and SPIX Sections here are maximum possible sizes */ -/* If used, they should be adjusted for the external Flash/RAM size */ -MEMORY { - - SPIX (rx) : ORIGIN = 0x08000000, LENGTH = 0x08000000 - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00100000 - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0008C000 - SPID (rw) : ORIGIN = 0x80000000, LENGTH = 512M -} - -/* Sections Definitions */ -SECTIONS { - .text : - { - _text = .; - KEEP(*(.isr_vector)) - *(.text*) /* program code */ - *(.rodata*) /* read-only data: "const" */ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* C++ Exception handling */ - KEEP(*(.eh_frame*)) - _etext = .; - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - /* This section will keep the SPIX data until loaded into the external device */ - /* Upon initialization of SPIX (user code needs to do this) */ - .xip_section : - { - KEEP(*(.xip_section*)) - } > SPIX AT>FLASH - - __load_start_xip = LOADADDR(.xip_section); - __load_length_xip = SIZEOF(.xip_section); - - /* it's used for C++ exception handling */ - /* we need to keep this to avoid overlapping */ - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - - .data : - { - _data = ALIGN(., 4); - *(vtable) - *(.data*) /*read-write initialized data: initialized global variable*/ - *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ - *(.flashprog*) /* Flash program */ - - - /* These array sections are used by __libc_init_array to call static C++ constructors */ - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - _edata = ALIGN(., 4); - } > SRAM AT>FLASH - __load_data = LOADADDR(.data); - - .bss : - { - . = ALIGN(4); - _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ - *(COMMON) - _ebss = ALIGN(., 4); - } > SRAM - - /* Setup the stack for Core 1, it will only be used if the user code - * includes a definition of Stack_Size_Core1, which defines the space - * reserved above the main core's stack for core 1's stack */ - - __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1; - - /* Set stack top to end of RAM, and stack limit move down by Stack_Size. - * If core 1 is used, set the stack to the bottom of Core 1's stack region */ - - __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit = __StackTop - Stack_Size; - - .heap (COPY): - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - *(.heap*) - __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM - - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack(s) exceeds RAM limit */ - ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") -} diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h deleted file mode 100644 index e5a76af85..000000000 --- a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.0 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -// skip if included from IAR assembler -#ifndef __IASMARM__ - #include "mxc_device.h" -#endif - -/* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configCPU_CLOCK_HZ SystemCoreClock -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) -#define configMAX_TASK_NAME_LEN 16 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 4 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TIME_SLICING 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Hook function related definitions. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configCHECK_HANDLER_INSTALLATION 0 - -/* Run time and task stats gathering related definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define configRECORD_STACK_HIGH_ADDRESS 1 -#define configUSE_TRACE_FACILITY 1 // legacy trace -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) -#define configTIMER_QUEUE_LENGTH 32 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Optional functions - most linkers will remove unused functions anyway. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY -#define INCLUDE_xResumeFromISR 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 -#define INCLUDE_pcTaskGetTaskName 0 -#define INCLUDE_eTaskGetState 0 -#define INCLUDE_xEventGroupSetBitFromISR 0 -#define INCLUDE_xTimerPendFunctionCall 0 - -/* FreeRTOS hooks to NVIC vectors */ -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler -#define vPortSVCHandler SVC_Handler - -//--------------------------------------------------------------------+ -// Interrupt nesting behavior configuration. -//--------------------------------------------------------------------+ - -// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header -#define configPRIO_BITS __NVIC_PRIO_BITS - -/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake. - -Both the Evaluation Kit and APARD boards are shipped with a CMSIS-DAP -compatible debug probe. However, at the time of writing, the necessary flashing -algorithms for OpenOCD have not yet been incorporated into the OpenOCD master -branch. To utilize the provided debug probes, please install the bundled MSDK -package which includes the appropriate OpenOCD modifications. To leverage this -OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake -target. diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32690/boards/apard32690/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/max32690/boards/apard32690/board.h deleted file mode 100644 index 87b9c4e88..000000000 --- a/hw/bsp/max32690/boards/apard32690/board.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: APARD32690-SL - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO2 -#define LED_PIN MXC_GPIO_PIN_1 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 1 - -// Button -#define BUTTON_PORT MXC_GPIO1 -#define BUTTON_PIN MXC_GPIO_PIN_27 -#define BUTTON_PULL MXC_GPIO_PAD_NONE -#define BUTTON_STATE_ACTIVE 1 - -// UART Enable for UART on ARM SWD Connector -#define UART_NUM 0 - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32690/boards/apard32690/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32690/boards/max32690evkit/board.cmake b/hw/bsp/max32690/boards/max32690evkit/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max32690/boards/max32690evkit/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/max32690/boards/max32690evkit/board.h deleted file mode 100644 index aa8dbb1de..000000000 --- a/hw/bsp/max32690/boards/max32690evkit/board.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: MAX32690 EVKIT - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO0 -#define LED_PIN MXC_GPIO_PIN_14 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT MXC_GPIO4 -#define BUTTON_PIN MXC_GPIO_PIN_0 -#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP -#define BUTTON_STATE_ACTIVE 0 - -// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 2 - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/boards/max32690evkit/board.mk b/hw/bsp/max32690/boards/max32690evkit/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max32690/boards/max32690evkit/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c deleted file mode 100644 index 7ba5fbef3..000000000 --- a/hw/bsp/max32690/family.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - manufacturer: Analog Devices -*/ - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() -#endif - -#include "gpio.h" -#include "mxc_sys.h" -#include "mcr_regs.h" -#include "mxc_device.h" -#include "uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "board.h" -#include "bsp/board_api.h" - - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB_IRQHandler(void) { - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ -mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); - -void board_init(void) { -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - mxc_gpio_cfg_t gpioConfig; - - // LED - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_OUT; - gpioConfig.mask = LED_PIN; - gpioConfig.pad = MXC_GPIO_PAD_NONE; - gpioConfig.port = LED_PORT; - gpioConfig.vssel = LED_VDDIO; - MXC_GPIO_Config(&gpioConfig); - board_led_write(false); - - // Button - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_IN; - gpioConfig.mask = BUTTON_PIN; - gpioConfig.pad = BUTTON_PULL; - gpioConfig.port = BUTTON_PORT; - gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; - MXC_GPIO_Config(&gpioConfig); - - // UART - MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK); - - //USB - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO); - MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { -#if LED_STATE_ON - state = !state; -#endif - if (state) { - MXC_GPIO_OutClr(LED_PORT, LED_PIN); - } else { - MXC_GPIO_OutSet(LED_PORT, LED_PIN); - } -} - -uint32_t board_button_read(void) { - uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; - return BUTTON_STATE_ACTIVE == state; -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checksum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); - - size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); - memcpy(id, hw_id, act_len); - return act_len; -} - -int board_uart_read(uint8_t *buf, int len) { - int uart_val; - int act_len = 0; - - while (act_len < len) { - if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { - break; - } else { - *buf++ = (uint8_t) uart_val; - act_len++; - } - } - return act_len; -} - -int board_uart_write(void const *buf, int len) { - int act_len = 0; - const uint8_t *ch_ptr = (const uint8_t *) buf; - while (act_len < len) { - MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); - act_len++; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - -void HardFault_Handler(void) { - __asm("BKPT #0\n"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) { -} diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake deleted file mode 100644 index 0d544d9e6..000000000 --- a/hw/bsp/max32690/family.cmake +++ /dev/null @@ -1,152 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file from current location (family) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld) -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max32690) -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg") - -set(FAMILY_MCUS MAX32690 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX32690 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX32690 - FLASH_ORIGIN=0x10000000 - FLASH_SIZE=0x340000 - SRAM_ORIGIN=0x20000000 - SRAM_SIZE=0x100000 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX32690 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_me18.c - ${PERIPH_SRC}/SYS/sys_me18.c - ${PERIPH_SRC}/CTB/ctb_me18.c - ${PERIPH_SRC}/CTB/ctb_reva.c - ${PERIPH_SRC}/CTB/ctb_common.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_me18.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_me18.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_me18.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_me18.c - ${PERIPH_SRC}/UART/uart_revb.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include - ${MAX32_PERIPH}/Include/MAX32690 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/CTB - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32690) - target_sources(${TARGET} PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - ) - - - - # Flashing - family_add_bin_hex(${TARGET}) - family_flash_jlink(${TARGET}) - family_flash_openocd_adi(${TARGET}) -endfunction() diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk deleted file mode 100644 index d4df8ef2f..000000000 --- a/hw/bsp/max32690/family.mk +++ /dev/null @@ -1,101 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S -LD_FILE = $(FAMILY_PATH)/max32690.ld - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX32690 SDK -CFLAGS += -DTARGET=MAX32690 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX32690 \ - -DFLASH_ORIGIN=0x10000000 \ - -DFLASH_SIZE=0x340000 \ - -DSRAM_ORIGIN=0x20000000 \ - -DSRAM_SIZE=0x100000 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter \ - -Wno-error=strict-prototypes \ - -Wno-error=old-style-declaration \ - -Wno-error=sign-compare \ - -Wno-error=cast-qual \ - -Wno-lto-type-mismatch - -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# For flash-jlink target -JLINK_DEVICE = max32690 - -# flash target using Jlink by default -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32690.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_me18.c \ - $(PERIPH_SRC)/SYS/sys_me18.c \ - $(PERIPH_SRC)/CTB/ctb_me18.c \ - $(PERIPH_SRC)/CTB/ctb_reva.c \ - $(PERIPH_SRC)/CTB/ctb_common.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_me18.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_me18.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_me18.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_me18.c \ - $(PERIPH_SRC)/UART/uart_revb.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/CTB \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld deleted file mode 100644 index 64b906a54..000000000 --- a/hw/bsp/max32690/max32690.ld +++ /dev/null @@ -1,164 +0,0 @@ -MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 /* 128kB ROM */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00340000 - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 - - /* - * Note that CS0/CS1 address mappings may be reversed using MXC_HPC->mbr0 and ->mbr1 - * The following mappings are selected for simplicity - */ - HPB_CS0 (rwx) : ORIGIN = 0x60000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 0 */ - HPB_CS1 (rwx) : ORIGIN = 0x70000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 1 */ -} - -SECTIONS { - .rom : - { - KEEP(*(.rom_vector)) - *(.rom_handlers*) - } > ROM - - .text : - { - _text = .; - KEEP(*(.isr_vector)) - EXCLUDE_FILE (*riscv.o) *(.text*) /* program code, exclude RISCV code */ - *(.rodata*) /* read-only data: "const" */ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* C++ Exception handling */ - KEEP(*(.eh_frame*)) - _etext = .; - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - /* These sections allow code to be compiled/linked for HPB addresses, but reside in - * flash until copied by code to the external HPB flash device - */ - .hpb_cs0_section : - { - __hpb_cs0_start = ABSOLUTE(.); - KEEP(*(.hpb_cs0_section*)) - } > HPB_CS0 AT>FLASH - - __load_start_hpb_cs0 = LOADADDR(.hpb_cs0_section); - __load_length_hpb_cs0 = SIZEOF(.hpb_cs0_section); - - .hpb_cs1_section : - { - __hpb_cs1_start = ABSOLUTE(.); - KEEP(*(.hpb_cs1_section*)) - } > HPB_CS1 AT>FLASH - - __load_start_hpb_cs1 = LOADADDR(.hpb_cs1_section); - __load_length_hpb_cs1 = SIZEOF(.hpb_cs1_section); - - /* Binary import */ - .bin_storage : - { - FILL(0xFF) - _bin_start_ = .; - KEEP(*(.bin_storage_img)) - _bin_end_ = .; - . = ALIGN(4); - } > FLASH - - /* it's used for C++ exception handling */ - /* we need to keep this to avoid overlapping */ - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - - .data : - { - _data = ALIGN(., 4); - *(vtable) - *(.data*) /*read-write initialized data: initialized global variable*/ - - /* These array sections are used by __libc_init_array to call static C++ constructors */ - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - /* Run the flash programming functions from SRAM */ - *(.flashprog) - - _edata = ALIGN(., 4); - } > SRAM AT>FLASH - __load_data = LOADADDR(.data); - - .bss : - { - . = ALIGN(4); - _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ - *(COMMON) - _ebss = ALIGN(., 4); - } > SRAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > SRAM - - .heap (COPY): - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - *(.heap*) - __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM - - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") -} diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h deleted file mode 100644 index e5a76af85..000000000 --- a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * FreeRTOS Kernel V10.0.0 - * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. If you wish to use our Amazon - * FreeRTOS name, please do so in a fair use way that does not cause confusion. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -// skip if included from IAR assembler -#ifndef __IASMARM__ - #include "mxc_device.h" -#endif - -/* Cortex M23/M33 port configuration. */ -#define configENABLE_MPU 0 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 0 -#define configMINIMAL_SECURE_STACK_SIZE (1024) - -#define configUSE_PREEMPTION 1 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configCPU_CLOCK_HZ SystemCoreClock -#define configTICK_RATE_HZ ( 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( 128 ) -#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) -#define configMAX_TASK_NAME_LEN 16 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configQUEUE_REGISTRY_SIZE 4 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TIME_SLICING 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configENABLE_BACKWARD_COMPATIBILITY 1 -#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 - -#define configSUPPORT_STATIC_ALLOCATION 1 -#define configSUPPORT_DYNAMIC_ALLOCATION 0 - -/* Hook function related definitions. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configCHECK_HANDLER_INSTALLATION 0 - -/* Run time and task stats gathering related definitions. */ -#define configGENERATE_RUN_TIME_STATS 0 -#define configRECORD_STACK_HIGH_ADDRESS 1 -#define configUSE_TRACE_FACILITY 1 // legacy trace -#define configUSE_STATS_FORMATTING_FUNCTIONS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES 2 - -/* Software timer related definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) -#define configTIMER_QUEUE_LENGTH 32 -#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE - -/* Optional functions - most linkers will remove unused functions anyway. */ -#define INCLUDE_vTaskPrioritySet 0 -#define INCLUDE_uxTaskPriorityGet 0 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY -#define INCLUDE_xResumeFromISR 0 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 -#define INCLUDE_pcTaskGetTaskName 0 -#define INCLUDE_eTaskGetState 0 -#define INCLUDE_xEventGroupSetBitFromISR 0 -#define INCLUDE_xTimerPendFunctionCall 0 - -/* FreeRTOS hooks to NVIC vectors */ -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler -#define vPortSVCHandler SVC_Handler - -//--------------------------------------------------------------------+ -// Interrupt nesting behavior configuration. -//--------------------------------------------------------------------+ - -// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header -#define configPRIO_BITS __NVIC_PRIO_BITS - -/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake. - -The Evaluation Kit is shipped with a CMSIS-DAP compatible debug probe. However, -at the time of writing, the necessary flashing algorithms for OpenOCD have not -yet been incorporated into the OpenOCD master branch. To utilize the provided -debug probes, please install the bundled MSDK package which includes the -appropriate OpenOCD modifications. To leverage this OpenOCD instance, run the -`flash-msdk` Makefile rule, or `-msdk` CMake target. diff --git a/hw/bsp/max78002/boards/max78002evkit/board.cmake b/hw/bsp/max78002/boards/max78002evkit/board.cmake deleted file mode 100644 index 9dc6962eb..000000000 --- a/hw/bsp/max78002/boards/max78002evkit/board.cmake +++ /dev/null @@ -1 +0,0 @@ -# Nothing to be done at the board level diff --git a/hw/bsp/max78002/boards/max78002evkit/board.h b/hw/bsp/max78002/boards/max78002evkit/board.h deleted file mode 100644 index 85d55d7de..000000000 --- a/hw/bsp/max78002/boards/max78002evkit/board.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: MAX78002 EVKIT - url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "gpio.h" -#include "mxc_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// LED -#define LED_PORT MXC_GPIO2 -#define LED_PIN MXC_GPIO_PIN_4 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 1 - -// Button -#define BUTTON_PORT MXC_GPIO2 -#define BUTTON_PIN MXC_GPIO_PIN_6 -#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP -#define BUTTON_STATE_ACTIVE 0 - -// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 0 -#define UART_PORT MXC_GPIO0 -#define UART_VDDIO_BITS 0xF - -#ifdef __cplusplus -} -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/max78002/boards/max78002evkit/board.mk b/hw/bsp/max78002/boards/max78002evkit/board.mk deleted file mode 100644 index a813a5327..000000000 --- a/hw/bsp/max78002/boards/max78002evkit/board.mk +++ /dev/null @@ -1 +0,0 @@ -# No specific build requirements for the board. diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c deleted file mode 100644 index 5c23f40f9..000000000 --- a/hw/bsp/max78002/family.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - manufacturer: Analog Devices -*/ - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() -#endif - -#include "gpio.h" -#include "mxc_sys.h" -#include "mcr_regs.h" -#include "mxc_device.h" -#include "uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "board.h" -#include "bsp/board_api.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ -void USB_IRQHandler(void) { - tud_int_handler(0); -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ -mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); - -void board_init(void) { -#if CFG_TUSB_OS == OPT_OS_NONE - // 1ms tick timer - SysTick_Config(SystemCoreClock / 1000); -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif - mxc_gpio_cfg_t gpioConfig; - - // LED - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_OUT; - gpioConfig.mask = LED_PIN; - gpioConfig.pad = MXC_GPIO_PAD_NONE; - gpioConfig.port = LED_PORT; - gpioConfig.vssel = LED_VDDIO; - MXC_GPIO_Config(&gpioConfig); - board_led_write(false); - - // Button - gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; - gpioConfig.func = MXC_GPIO_FUNC_IN; - gpioConfig.mask = BUTTON_PIN; - gpioConfig.pad = BUTTON_PULL; - gpioConfig.port = BUTTON_PORT; - gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; - MXC_GPIO_Config(&gpioConfig); - - // UART - MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK); - UART_PORT->vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V - - //USB - MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { -#if LED_STATE_ON - state = !state; -#endif - if (state) { - MXC_GPIO_OutClr(LED_PORT, LED_PIN); - } else { - MXC_GPIO_OutSet(LED_PORT, LED_PIN); - } -} - -uint32_t board_button_read(void) { - uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; - return BUTTON_STATE_ACTIVE == state; -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checksum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); - - size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); - memcpy(id, hw_id, act_len); - return act_len; -} - -int board_uart_read(uint8_t *buf, int len) { - int uart_val; - int act_len = 0; - - while (act_len < len) { - if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { - break; - } else { - *buf++ = (uint8_t) uart_val; - act_len++; - } - } - return act_len; -} - -int board_uart_write(void const *buf, int len) { - int act_len = 0; - const uint8_t *ch_ptr = (const uint8_t *) buf; - while (act_len < len) { - MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); - act_len++; - } - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - -void HardFault_Handler(void) { - __asm("BKPT #0\n"); -} - -// Required by __libc_init_array in startup code if we are compiling using -// -nostdlib/-nostartfiles. -void _init(void) { -} diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake deleted file mode 100644 index ce0fcfa08..000000000 --- a/hw/bsp/max78002/family.cmake +++ /dev/null @@ -1,166 +0,0 @@ -include_guard() - -set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) -set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) -set(CMSIS_5 ${TOP}/lib/CMSIS_5) - -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# Get the linker file from current location (family) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld) -set(LD_FILE_Clang ${LD_FILE_GNU}) - -# toolchain set up -set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(JLINK_DEVICE max78000) - -set(FAMILY_MCUS MAX78002 CACHE INTERNAL "") - -function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - TARGET=MAX78002 - TARGET_REV=0x4131 - MXC_ASSERT_ENABLE - MAX78002 - IAR_PRAGMAS=0 - CFG_TUSB_MCU=OPT_MCU_MAX78002 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) -endfunction() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif () - - # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S) - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - set(PERIPH_SRC ${MAX32_PERIPH}/Source) - add_library(${BOARD_TARGET} STATIC - ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c - ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c - ${PERIPH_SRC}/SYS/mxc_assert.c - ${PERIPH_SRC}/SYS/mxc_delay.c - ${PERIPH_SRC}/SYS/mxc_lock.c - ${PERIPH_SRC}/SYS/nvic_table.c - ${PERIPH_SRC}/SYS/pins_ai87.c - ${PERIPH_SRC}/SYS/sys_ai87.c - ${PERIPH_SRC}/AES/aes_ai87.c - ${PERIPH_SRC}/AES/aes_revb.c - ${PERIPH_SRC}/FLC/flc_common.c - ${PERIPH_SRC}/FLC/flc_ai87.c - ${PERIPH_SRC}/FLC/flc_reva.c - ${PERIPH_SRC}/GPIO/gpio_common.c - ${PERIPH_SRC}/GPIO/gpio_ai87.c - ${PERIPH_SRC}/GPIO/gpio_reva.c - ${PERIPH_SRC}/ICC/icc_ai87.c - ${PERIPH_SRC}/ICC/icc_reva.c - ${PERIPH_SRC}/TRNG/trng_ai87.c - ${PERIPH_SRC}/TRNG/trng_revb.c - ${PERIPH_SRC}/UART/uart_common.c - ${PERIPH_SRC}/UART/uart_ai87.c - ${PERIPH_SRC}/UART/uart_revb.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${MAX32_CMSIS}/Include - ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include - ${MAX32_PERIPH}/Include/MAX78002 - ${PERIPH_SRC}/SYS - ${PERIPH_SRC}/GPIO - ${PERIPH_SRC}/AES - ${PERIPH_SRC}/TRNG - ${PERIPH_SRC}/ICC - ${PERIPH_SRC}/FLC - ${PERIPH_SRC}/UART - ) - - target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls - ) - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_Clang}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls - ) - - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX78002) - target_sources(${TARGET} PUBLIC - ${TOP}/src/portable/mentor/musb/dcd_musb.c - ) - target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - target_compile_options(${TARGET} PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls - ) - - - - # Flashing - family_add_bin_hex(${TARGET}) - family_flash_jlink(${TARGET}) - family_flash_msdk(${TARGET}) -endfunction() - -# Add flash msdk target -function(family_flash_msdk TARGET) - set(MAXIM_PATH "$ENV{MAXIM_PATH}") - - add_custom_target(${TARGET}-msdk - DEPENDS ${TARGET} - COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts - -f interface/cmsis-dap.cfg -f target/max78002.cfg - -c "program $ verify; init; reset; exit" - VERBATIM - ) -endfunction() diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk deleted file mode 100644 index 997816261..000000000 --- a/hw/bsp/max78002/family.mk +++ /dev/null @@ -1,99 +0,0 @@ -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 - -# Important locations in the hw support for MCU -MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS -MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers - -# Add any board specific make rules -include $(TOP)/$(BOARD_PATH)/board.mk - -CPU_CORE ?= cortex-m4 -PORT ?= 0 - -# GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S -LD_FILE = $(FAMILY_PATH)/max78002.ld - -# -------------- -# Compiler Flags -# -------------- -# Flags for the MAX78002 SDK -CFLAGS += -DTARGET=MAX78002 \ - -DTARGET_REV=0x4131 \ - -DMXC_ASSERT_ENABLE \ - -DMAX78002 \ - -DIAR_PRAGMAS=0 - -# Flags for TUSB features -CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \ - -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - -# mcu driver cause following warnings -CFLAGS += -Wno-error=redundant-decls \ - -Wno-error=strict-prototypes \ - -Wno-error=unused-parameter \ - -Wno-error=enum-conversion \ - -Wno-error=sign-compare \ - -Wno-error=cast-qual - -LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs - -# For flash-jlink target -JLINK_DEVICE = max78000 - -# flash target using Jlink by default -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max78002.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" - -# ----------------- -# Sources & Include -# ----------------- -PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source -SRC_C += \ - src/portable/mentor/musb/dcd_musb.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \ - $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \ - $(PERIPH_SRC)/SYS/mxc_assert.c \ - $(PERIPH_SRC)/SYS/mxc_delay.c \ - $(PERIPH_SRC)/SYS/mxc_lock.c \ - $(PERIPH_SRC)/SYS/nvic_table.c \ - $(PERIPH_SRC)/SYS/pins_ai87.c \ - $(PERIPH_SRC)/SYS/sys_ai87.c \ - $(PERIPH_SRC)/AES/aes_ai87.c \ - $(PERIPH_SRC)/AES/aes_revb.c \ - $(PERIPH_SRC)/FLC/flc_common.c \ - $(PERIPH_SRC)/FLC/flc_ai87.c \ - $(PERIPH_SRC)/FLC/flc_reva.c \ - $(PERIPH_SRC)/GPIO/gpio_common.c \ - $(PERIPH_SRC)/GPIO/gpio_ai87.c \ - $(PERIPH_SRC)/GPIO/gpio_reva.c \ - $(PERIPH_SRC)/ICC/icc_ai87.c \ - $(PERIPH_SRC)/ICC/icc_reva.c \ - $(PERIPH_SRC)/TRNG/trng_ai87.c \ - $(PERIPH_SRC)/TRNG/trng_revb.c \ - $(PERIPH_SRC)/UART/uart_common.c \ - $(PERIPH_SRC)/UART/uart_ai87.c \ - $(PERIPH_SRC)/UART/uart_revb.c \ - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(MAX32_CMSIS)/Include \ - $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \ - $(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \ - $(PERIPH_SRC)/SYS \ - $(PERIPH_SRC)/GPIO \ - $(PERIPH_SRC)/AES \ - $(PERIPH_SRC)/ICC \ - $(PERIPH_SRC)/FLC \ - $(PERIPH_SRC)/TRNG \ - $(PERIPH_SRC)/UART diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld deleted file mode 100644 index e5c4866ee..000000000 --- a/hw/bsp/max78002/max78002.ld +++ /dev/null @@ -1,182 +0,0 @@ -MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64 kB ROM */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00280000 /* 2.5 MB Flash */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00060000 /* 384 kB SRAM */ - /*CSI2 (rwx) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 4096 B CSI2 Buffer */ -} - -SECTIONS { - .rom : - { - KEEP(*(.rom_vector)) - *(.rom_handlers*) - } > ROM - - .text : - { - _text = .; - KEEP(*(.isr_vector)) - EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ - *(.rodata*) /* read-only data: "const" */ - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* C++ Exception handling */ - KEEP(*(.eh_frame*)) - _etext = .; - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - /* Binary import */ - .bin_storage : - { - FILL(0xFF) - _bin_start_ = .; - KEEP(*(.bin_storage_img)) - _bin_end_ = .; - . = ALIGN(4); - } > FLASH - - .rom_code : - { - . = ALIGN(16); - _sran_code = .; - *(.rom_code_section) - _esran_code = .; - } > ROM - - .flash_code : - { - . = ALIGN(16); - _sran_code = .; - *(.flash_code_section) - _esran_code = .; - } > FLASH - - .sram_code : - { - . = ALIGN(16); - _sran_code = .; - *(.sram_code_section) - _esran_code = .; - } > SRAM - - /* it's used for C++ exception handling */ - /* we need to keep this to avoid overlapping */ - .ARM.exidx : - { - __exidx_start = .; - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - __exidx_end = .; - } > FLASH - - .data : - { - _data = ALIGN(., 4); - _csi = . + 0x20000; - *(vtable) - *(.data*) /*read-write initialized data: initialized global variable*/ - - - /* These array sections are used by __libc_init_array to call static C++ constructors */ - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - _edata = ALIGN(., 4); - - } > SRAM AT>FLASH - __load_data = LOADADDR(.data); - - .bss : - { - . = ALIGN(4); - _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ - *(COMMON) - _ebss = ALIGN(., 4); - } > SRAM - - .shared : - { - . = ALIGN(4); - _shared = .; - *(.mailbox*) - . = ALIGN(4); - *(.shared*) /*read-write zero initialized data: uninitialized global variable*/ - _eshared = ALIGN(., 4); - } > SRAM - __shared_data = LOADADDR(.shared); - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > SRAM - - .heap (COPY): - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - *(.heap*) - __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM - - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") - - /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */ - .riscv_flash : - { - /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/ - . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/ - . += 0x100; - _riscv_boot = .; - KEEP(*riscv.o (.text*)) - } > FLASH -} diff --git a/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..e5a76af85 --- /dev/null +++ b/hw/bsp/maxim/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "mxc_device.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS __NVIC_PRIO_BITS + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<-jlink` target for CMake. + +Most the Evaluation Kit and boards are shipped with a CMSIS-DAP +compatible debug probe. However, at the time of writing, the necessary flashing +algorithms for OpenOCD have not yet been incorporated into the OpenOCD master +branch. To utilize the provided debug probes, please install the bundled MSDK +package which includes the appropriate OpenOCD modifications. To leverage this +OpenOCD instance, run the `-openocd` CMake +target. diff --git a/hw/bsp/maxim/boards/apard32690/board.cmake b/hw/bsp/maxim/boards/apard32690/board.cmake new file mode 100644 index 000000000..a03d05f8d --- /dev/null +++ b/hw/bsp/maxim/boards/apard32690/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32690) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/maxim/boards/apard32690/board.h b/hw/bsp/maxim/boards/apard32690/board.h new file mode 100644 index 000000000..87b9c4e88 --- /dev/null +++ b/hw/bsp/maxim/boards/apard32690/board.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: APARD32690-SL + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_1 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 1 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_27 +#define BUTTON_PULL MXC_GPIO_PAD_NONE +#define BUTTON_STATE_ACTIVE 1 + +// UART Enable for UART on ARM SWD Connector +#define UART_NUM 0 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/boards/max32650evkit/board.cmake b/hw/bsp/maxim/boards/max32650evkit/board.cmake new file mode 100644 index 000000000..59721e756 --- /dev/null +++ b/hw/bsp/maxim/boards/max32650evkit/board.cmake @@ -0,0 +1,8 @@ +set(MAX_DEVICE max32650) + +function(update_board TARGET) +endfunction() + +function(prepare_image TARGET_IN) + #No signing required +endfunction() diff --git a/hw/bsp/maxim/boards/max32650evkit/board.h b/hw/bsp/maxim/boards/max32650evkit/board.h new file mode 100644 index 000000000..65ed2659e --- /dev/null +++ b/hw/bsp/maxim/boards/max32650evkit/board.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: MAX32650 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_25 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO2 +#define BUTTON_PIN MXC_GPIO_PIN_28 +#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL +#define UART_NUM 0 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/boards/max32650fthr/board.cmake b/hw/bsp/maxim/boards/max32650fthr/board.cmake new file mode 100644 index 000000000..59721e756 --- /dev/null +++ b/hw/bsp/maxim/boards/max32650fthr/board.cmake @@ -0,0 +1,8 @@ +set(MAX_DEVICE max32650) + +function(update_board TARGET) +endfunction() + +function(prepare_image TARGET_IN) + #No signing required +endfunction() diff --git a/hw/bsp/maxim/boards/max32650fthr/board.h b/hw/bsp/maxim/boards/max32650fthr/board.h new file mode 100644 index 000000000..755fa15b5 --- /dev/null +++ b/hw/bsp/maxim/boards/max32650fthr/board.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: MAX32650 Feather + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO1 +#define LED_PIN MXC_GPIO_PIN_14 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIO +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_19 +#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for SWD UART Pins. Pin Mux handled by the HAL +#define UART_NUM 0 + + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/boards/max32651evkit/board.cmake b/hw/bsp/maxim/boards/max32651evkit/board.cmake new file mode 100644 index 000000000..773989126 --- /dev/null +++ b/hw/bsp/maxim/boards/max32651evkit/board.cmake @@ -0,0 +1,31 @@ +set(MAX_DEVICE max32650) + +# Use the secure linker file +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/max32651.ld) + +function(update_board TARGET) + # for the signed target, need to add the __SLA_FWK__ define + target_compile_definitions(${TARGET} PUBLIC + __SLA_FWK__ + ) +endfunction() + +function(sign_image TARGET_IN) + #For the signed target, set up a POST_BUILD command to sign the elf file once created + if((WIN32) OR (MINGW) OR (MSYS)) + set(SIGN_EXE "sign_app.exe") + else() + set(SIGN_EXE "sign_app") + endif() + set(MCU_PATH "${TOP}/hw/mcu/analog/msdk/") + + # Custom POST_BUILD command + add_custom_command( + TARGET ${TARGET_IN} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} $ -R .sig -O binary $/${TARGET_IN}.bin + COMMAND ${MCU_PATH}/Tools/SBT/bin/${SIGN_EXE} -c MAX32651 key_file=${MCU_PATH}/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key + ca=$/${TARGET_IN}.bin sca=$/${TARGET_IN}.sbin + COMMAND ${CMAKE_OBJCOPY} $ --update-section .sig=$/${TARGET_IN}.sig + VERBATIM + ) +endfunction() diff --git a/hw/bsp/maxim/boards/max32651evkit/board.h b/hw/bsp/maxim/boards/max32651evkit/board.h new file mode 100644 index 000000000..0b49ff309 --- /dev/null +++ b/hw/bsp/maxim/boards/max32651evkit/board.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: MAX32651 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_25 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO2 +#define BUTTON_PIN MXC_GPIO_PIN_28 +#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL +#define UART_NUM 0 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/boards/max32666evkit/board.cmake b/hw/bsp/maxim/boards/max32666evkit/board.cmake new file mode 100644 index 000000000..e7116b603 --- /dev/null +++ b/hw/bsp/maxim/boards/max32666evkit/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32665) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/maxim/boards/max32666evkit/board.h b/hw/bsp/maxim/boards/max32666evkit/board.h new file mode 100644 index 000000000..54589444d --- /dev/null +++ b/hw/bsp/maxim/boards/max32666evkit/board.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: MAX32666 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO1 +#define LED_PIN MXC_GPIO_PIN_14 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_6 +#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL +#define UART_NUM 1 +#define UART_MAP MAP_A + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/boards/max32666fthr/board.cmake b/hw/bsp/maxim/boards/max32666fthr/board.cmake new file mode 100644 index 000000000..e7116b603 --- /dev/null +++ b/hw/bsp/maxim/boards/max32666fthr/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32665) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/maxim/boards/max32666fthr/board.h b/hw/bsp/maxim/boards/max32666fthr/board.h new file mode 100644 index 000000000..0caea5934 --- /dev/null +++ b/hw/bsp/maxim/boards/max32666fthr/board.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: MAX32666 Feather + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO0 +#define LED_PIN MXC_GPIO_PIN_29 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_10 +#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for UART on SWD. Pin Mux handled by the HAL +#define UART_NUM 1 +#define UART_MAP MAP_B + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/boards/max32690evkit/board.cmake b/hw/bsp/maxim/boards/max32690evkit/board.cmake new file mode 100644 index 000000000..a03d05f8d --- /dev/null +++ b/hw/bsp/maxim/boards/max32690evkit/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max32690) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/maxim/boards/max32690evkit/board.h b/hw/bsp/maxim/boards/max32690evkit/board.h new file mode 100644 index 000000000..aa8dbb1de --- /dev/null +++ b/hw/bsp/maxim/boards/max32690evkit/board.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: MAX32690 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO0 +#define LED_PIN MXC_GPIO_PIN_14 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO4 +#define BUTTON_PIN MXC_GPIO_PIN_0 +#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL +#define UART_NUM 2 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/boards/max78002evkit/board.cmake b/hw/bsp/maxim/boards/max78002evkit/board.cmake new file mode 100644 index 000000000..dd4c3c215 --- /dev/null +++ b/hw/bsp/maxim/boards/max78002evkit/board.cmake @@ -0,0 +1,4 @@ +set(MAX_DEVICE max78002) + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/maxim/boards/max78002evkit/board.h b/hw/bsp/maxim/boards/max78002evkit/board.h new file mode 100644 index 000000000..85d55d7de --- /dev/null +++ b/hw/bsp/maxim/boards/max78002evkit/board.h @@ -0,0 +1,63 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: MAX78002 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_4 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 1 + +// Button +#define BUTTON_PORT MXC_GPIO2 +#define BUTTON_PIN MXC_GPIO_PIN_6 +#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL +#define UART_NUM 0 +#define UART_PORT MXC_GPIO0 +#define UART_VDDIO_BITS 0xF + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/maxim/family.c b/hw/bsp/maxim/family.c new file mode 100644 index 000000000..0ef6b8c4d --- /dev/null +++ b/hw/bsp/maxim/family.c @@ -0,0 +1,213 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: Analog Devices +*/ + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + +#include "gpio.h" +#include "mxc_sys.h" +#if __has_include("mcr_regs.h") +#include "mcr_regs.h" +#endif +#include "mxc_device.h" +#include "uart.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_IRQHandler(void) { + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ +mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); + +void board_init(void) { +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + mxc_gpio_cfg_t gpioConfig; + + // LED + gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; + gpioConfig.func = MXC_GPIO_FUNC_OUT; + gpioConfig.mask = LED_PIN; + gpioConfig.pad = MXC_GPIO_PAD_NONE; + gpioConfig.port = LED_PORT; + gpioConfig.vssel = LED_VDDIO; + MXC_GPIO_Config(&gpioConfig); + board_led_write(false); + + // Button + gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; + gpioConfig.func = MXC_GPIO_FUNC_IN; + gpioConfig.mask = BUTTON_PIN; + gpioConfig.pad = BUTTON_PULL; + gpioConfig.port = BUTTON_PORT; + gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; + MXC_GPIO_Config(&gpioConfig); + + // UART +#if MAX_PERIPH_ID == 14 + MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, UART_MAP); +#elif MAX_PERIPH_ID == 18 || MAX_PERIPH_ID == 87 + MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE, MXC_UART_IBRO_CLK); + #if MAX_PERIPH_ID == 87 + UART_PORT->vssel |= UART_VDDIO_BITS; // Set necessary bits to 3.3V + #endif +#endif + + //USB +#if defined(MAX32650) + // Startup the HIRC96M clock if it's not on already + if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) { + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN; + MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY); + } + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); + +#elif defined(MAX32665) || defined(MAX32666) + // Startup the HIRC96M clock if it's not on already + if (!(MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) { + MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN; + } + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); + +#elif defined(MAX32690) + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IPO); + MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB); + +# elif defined(MAX78002) + MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); +#else + #error "Unsupported MAXIM MCU for board_dfu_init" +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { + MXC_GPIO_OutClr(LED_PORT, LED_PIN); + } else { + MXC_GPIO_OutSet(LED_PORT, LED_PIN); + } +} + +uint32_t board_button_read(void) { + uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; + return BUTTON_STATE_ACTIVE == state; +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { +#if defined(MAX32650) + // USN is 13 bytes on this device + MXC_SYS_GetUSN(id, 13); + return 13; +#else + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer + MXC_SYS_GetUSN(hw_id, NULL); // 2nd parameter is optional checksum buffer + + size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); + memcpy(id, hw_id, act_len); + return act_len; +#endif +} + +int board_uart_read(uint8_t *buf, int len) { + int uart_val; + int act_len = 0; + + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + break; + } else { + *buf++ = (uint8_t) uart_val; + act_len++; + } + } + return act_len; +} + +int board_uart_write(void const *buf, int len) { + int act_len = 0; + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { + MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); + act_len++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/maxim/family.cmake b/hw/bsp/maxim/family.cmake new file mode 100644 index 000000000..1fd5215ba --- /dev/null +++ b/hw/bsp/maxim/family.cmake @@ -0,0 +1,205 @@ +include_guard() + +# stub: overridden by board.cmake if needed +function(sign_image TARGET_IN) +endfunction() + +set(MSDK_LIB ${TOP}/hw/mcu/analog/msdk/Libraries) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +cmake_print_variables(MAX_DEVICE) +string(TOUPPER ${MAX_DEVICE} MAX_DEVICE_UPPER) + +set(JLINK_DEVICE ${MAX_DEVICE}) +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${MAX_DEVICE}.cfg") + +set(FAMILY_MCUS ${MAX_DEVICE_UPPER} CACHE INTERNAL "") + +if (${MAX_DEVICE} STREQUAL "max32650") + set(PERIPH_ID 10) + set(PERIPH_SUFFIX "me") +elseif (${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666") + set(PERIPH_ID 14) + set(PERIPH_SUFFIX "me") +elseif (${MAX_DEVICE} STREQUAL "max32690") + set(PERIPH_ID 18) + set(PERIPH_SUFFIX "me") +elseif (${MAX_DEVICE} STREQUAL "max78002") + set(PERIPH_ID 87) + set(PERIPH_SUFFIX "ai") +else() + message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}") +endif() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/GCC/startup_${MAX_DEVICE}.S) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MAX_DEVICE}.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + + # Common + add_library(${BOARD_TARGET} STATIC + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/heap.c + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Source/system_${MAX_DEVICE}.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_assert.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_delay.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/mxc_lock.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/nvic_table.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/pins_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/SYS/sys_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_common.c + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/FLC/flc_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_common.c + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/GPIO/gpio_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_common.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_${PERIPH_SUFFIX}${PERIPH_ID}.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/CMSIS/5.9.0/Core/Include + ${MSDK_LIB}/CMSIS/Device/Maxim/${MAX_DEVICE_UPPER}/Include + ${MSDK_LIB}/PeriphDrivers/Include/${MAX_DEVICE_UPPER} + ${MSDK_LIB}/PeriphDrivers/Source/SYS + ${MSDK_LIB}/PeriphDrivers/Source/GPIO + ${MSDK_LIB}/PeriphDrivers/Source/ICC + ${MSDK_LIB}/PeriphDrivers/Source/FLC + ${MSDK_LIB}/PeriphDrivers/Source/UART + ) + + # device specific + if (${MAX_DEVICE} STREQUAL "max32650" OR + ${MAX_DEVICE} STREQUAL "max32665" OR ${MAX_DEVICE} STREQUAL "max32666") + target_sources(${BOARD_TARGET} PRIVATE + ${MSDK_LIB}/PeriphDrivers/Source/ICC/icc_common.c + ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/TPU/tpu_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_reva.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/PeriphDrivers/Source/TPU + ) + elseif (${MAX_DEVICE} STREQUAL "max32690") + target_sources(${BOARD_TARGET} PRIVATE + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_reva.c + ${MSDK_LIB}/PeriphDrivers/Source/CTB/ctb_common.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/PeriphDrivers/Source/CTB + ) + elseif (${MAX_DEVICE} STREQUAL "max78002") + target_sources(${BOARD_TARGET} PRIVATE + ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/AES/aes_revb.c + ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_${PERIPH_SUFFIX}${PERIPH_ID}.c + ${MSDK_LIB}/PeriphDrivers/Source/TRNG/trng_revb.c + ${MSDK_LIB}/PeriphDrivers/Source/UART/uart_revb.c + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${MSDK_LIB}/PeriphDrivers/Source/AES + ${MSDK_LIB}/PeriphDrivers/Source/TRNG + ) + else() + message(FATAL_ERROR "Unsupported MAX device: ${MAX_DEVICE}") + endif() + + target_compile_definitions(${BOARD_TARGET} PUBLIC + TARGET=${MAX_DEVICE_UPPER} + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + ${MAX_DEVICE_UPPER} + IAR_PRAGMAS=0 + FLASH_BOOT_SIZE=${FLASH_BOOT_SIZE} + MAX_PERIPH_ID=${PERIPH_ID} + ) + + target_compile_definitions(${TARGET} PUBLIC + TARGET=MAX32690 + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + MAX32690 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) + + target_compile_options(${BOARD_TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_${MAX_DEVICE_UPPER}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/mentor/musb/dcd_musb.c + ) + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) + + sign_image(${TARGET}) # for secured device such as max32651 + family_flash_openocd_adi(${TARGET}) +endfunction() diff --git a/hw/bsp/maxim/linker/max32650.ld b/hw/bsp/maxim/linker/max32650.ld new file mode 100644 index 000000000..0e56a91ec --- /dev/null +++ b/hw/bsp/maxim/linker/max32650.ld @@ -0,0 +1,119 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ +} + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/hw/bsp/maxim/linker/max32651.ld b/hw/bsp/maxim/linker/max32651.ld new file mode 100644 index 000000000..3921d10f2 --- /dev/null +++ b/hw/bsp/maxim/linker/max32651.ld @@ -0,0 +1,132 @@ +MEMORY { + HEADER (rx): ORIGIN = 0x10000000, LENGTH = 0x200 + FLASH (rx) : ORIGIN = 0x10000200, LENGTH = 0x002FFE00 /* 3MB flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ +} + +/* Added Oct 9, 2018 to go to correct reset vector. */ +ENTRY(Reset_Handler) +PROVIDE( _start_SWAP = (((Reset_Handler) >> 24) | (((Reset_Handler) & 0x00FF0000) >> 8) | (((Reset_Handler) & 0x0000FF00) << 8) | ((Reset_Handler) << 24))); +PROVIDE_HIDDEN( _SLA_Size = _endimage - __end_header ); +PROVIDE( _SLA_Size_SWAP = (((_SLA_Size) >> 24) | (((_SLA_Size) & 0x00FF0000) >> 8) | (((_SLA_Size) & 0x0000FF00) << 8) | ((_SLA_Size) << 24))); + +/* Sections Definitions */ +SECTIONS { + .sb_sla_header : ALIGN(4) + { + FILL(0xFF) + KEEP(*(.sb_sla_header)) /* Header for ROM code */ + __end_header = . ; + . = ALIGN(512); + } > HEADER + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + _enddata = LOADADDR(.data)+SIZEOF(.data); + + .sb_sla_trailer : AT(_enddata) + { + KEEP(*(.sb_sla_trailer)) + /* Align image with 16 byte boundary to conform to flash encryption block size. */ + FILL(0xDEADC0DE); + /* NOTE: The FILL and ALIGN will not work unless something is written to the section. So, we use LONG. */ + LONG(0xDEADC0DE); + . = ALIGN(16); + } > FLASH + _endimage = LOADADDR(.sb_sla_trailer)+SIZEOF(.sb_sla_trailer); + .sig : + { + KEEP(*(.sig)) + LONG(0xDEADBEEF); + + } > FLASH + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/hw/bsp/maxim/linker/max32665.ld b/hw/bsp/maxim/linker/max32665.ld new file mode 100644 index 000000000..06c124247 --- /dev/null +++ b/hw/bsp/maxim/linker/max32665.ld @@ -0,0 +1,135 @@ +/* SPID and SPIX Sections here are maximum possible sizes */ +/* If used, they should be adjusted for the external Flash/RAM size */ +MEMORY { + + SPIX (rx) : ORIGIN = 0x08000000, LENGTH = 0x08000000 + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0008C000 + SPID (rw) : ORIGIN = 0x80000000, LENGTH = 512M +} + +/* Sections Definitions */ +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* This section will keep the SPIX data until loaded into the external device */ + /* Upon initialization of SPIX (user code needs to do this) */ + .xip_section : + { + KEEP(*(.xip_section*)) + } > SPIX AT>FLASH + + __load_start_xip = LOADADDR(.xip_section); + __load_length_xip = SIZEOF(.xip_section); + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Setup the stack for Core 1, it will only be used if the user code + * includes a definition of Stack_Size_Core1, which defines the space + * reserved above the main core's stack for core 1's stack */ + + __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1; + + /* Set stack top to end of RAM, and stack limit move down by Stack_Size. + * If core 1 is used, set the stack to the bottom of Core 1's stack region */ + + __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - Stack_Size; + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack(s) exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/hw/bsp/maxim/linker/max32690.ld b/hw/bsp/maxim/linker/max32690.ld new file mode 100644 index 000000000..64b906a54 --- /dev/null +++ b/hw/bsp/maxim/linker/max32690.ld @@ -0,0 +1,164 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 /* 128kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00340000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 + + /* + * Note that CS0/CS1 address mappings may be reversed using MXC_HPC->mbr0 and ->mbr1 + * The following mappings are selected for simplicity + */ + HPB_CS0 (rwx) : ORIGIN = 0x60000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 0 */ + HPB_CS1 (rwx) : ORIGIN = 0x70000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 1 */ +} + +SECTIONS { + .rom : + { + KEEP(*(.rom_vector)) + *(.rom_handlers*) + } > ROM + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + EXCLUDE_FILE (*riscv.o) *(.text*) /* program code, exclude RISCV code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* These sections allow code to be compiled/linked for HPB addresses, but reside in + * flash until copied by code to the external HPB flash device + */ + .hpb_cs0_section : + { + __hpb_cs0_start = ABSOLUTE(.); + KEEP(*(.hpb_cs0_section*)) + } > HPB_CS0 AT>FLASH + + __load_start_hpb_cs0 = LOADADDR(.hpb_cs0_section); + __load_length_hpb_cs0 = SIZEOF(.hpb_cs0_section); + + .hpb_cs1_section : + { + __hpb_cs1_start = ABSOLUTE(.); + KEEP(*(.hpb_cs1_section*)) + } > HPB_CS1 AT>FLASH + + __load_start_hpb_cs1 = LOADADDR(.hpb_cs1_section); + __load_length_hpb_cs1 = SIZEOF(.hpb_cs1_section); + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* Run the flash programming functions from SRAM */ + *(.flashprog) + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/hw/bsp/maxim/linker/max78002.ld b/hw/bsp/maxim/linker/max78002.ld new file mode 100644 index 000000000..e5c4866ee --- /dev/null +++ b/hw/bsp/maxim/linker/max78002.ld @@ -0,0 +1,182 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64 kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00280000 /* 2.5 MB Flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00060000 /* 384 kB SRAM */ + /*CSI2 (rwx) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 4096 B CSI2 Buffer */ +} + +SECTIONS { + .rom : + { + KEEP(*(.rom_vector)) + *(.rom_handlers*) + } > ROM + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > FLASH + + .rom_code : + { + . = ALIGN(16); + _sran_code = .; + *(.rom_code_section) + _esran_code = .; + } > ROM + + .flash_code : + { + . = ALIGN(16); + _sran_code = .; + *(.flash_code_section) + _esran_code = .; + } > FLASH + + .sram_code : + { + . = ALIGN(16); + _sran_code = .; + *(.sram_code_section) + _esran_code = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + _csi = . + 0x20000; + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + .shared : + { + . = ALIGN(4); + _shared = .; + *(.mailbox*) + . = ALIGN(4); + *(.shared*) /*read-write zero initialized data: uninitialized global variable*/ + _eshared = ALIGN(., 4); + } > SRAM + __shared_data = LOADADDR(.shared); + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") + + /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */ + .riscv_flash : + { + /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/ + . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/ + . += 0x100; + _riscv_boot = .; + KEEP(*riscv.o (.text*)) + } > FLASH +} diff --git a/tools/get_deps.py b/tools/get_deps.py index 1ce8be6c7..635edaa66 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -25,9 +25,9 @@ deps_optional = { 'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git', '8e5e89e8e132c0fd90e72d5422e5d3d68232b756', 'fc100s'], - 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git', + 'hw/mcu/analog/msdk' : ['https://github.com/analogdevicesinc/msdk.git', 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75', - 'max32650 max32666 max32690 max78002'], + 'maxim'], 'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git', '91060164afe239fcb394122e8bf9eb24d3194eb1', 'brtmm90x'], -- cgit v1.3.1 From 76b7468c746af5ad8496e9ed512366af249f972f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Jun 2025 15:08:46 +0700 Subject: ci skip clang/iar build for stm32n6 add stm32-tcpp0203 driver as dependency for h7rs and n6 --- .github/workflows/ci_set_matrix.py | 3 +- .../stm32h7rs/boards/stm32h7s3nucleo/board.cmake | 11 +- hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk | 10 +- .../boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt | 6 - .../stm32h7s3nucleo/tcpp0203/Release_Notes.html | 205 --- .../stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png | Bin 4126 -> 0 bytes .../tcpp0203/_htmresc/mini-st_2020.css | 1703 -------------------- .../tcpp0203/_htmresc/st_logo_2020.png | Bin 7520 -> 0 bytes .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c | 886 ---------- .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h | 353 ---- .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c | 73 - .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h | 98 -- hw/bsp/stm32h7rs/family.cmake | 3 + hw/bsp/stm32h7rs/family.mk | 3 + hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake | 8 +- hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk | 6 +- .../boards/stm32n657nucleo/tcpp0203/LICENSE.txt | 6 - .../stm32n657nucleo/tcpp0203/Release_Notes.html | 205 --- .../stm32n657nucleo/tcpp0203/_htmresc/favicon.png | Bin 4126 -> 0 bytes .../tcpp0203/_htmresc/mini-st_2020.css | 1703 -------------------- .../tcpp0203/_htmresc/st_logo_2020.png | Bin 7520 -> 0 bytes .../boards/stm32n657nucleo/tcpp0203/tcpp0203.c | 886 ---------- .../boards/stm32n657nucleo/tcpp0203/tcpp0203.h | 353 ---- .../boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c | 73 - .../boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h | 98 -- hw/bsp/stm32n6/family.cmake | 1 + hw/bsp/stm32n6/family.mk | 1 + tools/get_deps.py | 3 + 28 files changed, 25 insertions(+), 6672 deletions(-) delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c delete mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c delete mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h (limited to 'tools') diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index 048c5f0ce..ddb3ee1fb 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -41,7 +41,8 @@ family_list = { "stm32f7": ["arm-gcc", "arm-clang", "arm-iar"], "stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"], "stm32h7 stm32h7rs": ["arm-gcc", "arm-clang", "arm-iar"], - "stm32l0 stm32l4 stm32n6": ["arm-gcc", "arm-clang", "arm-iar"], + "stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"], + "stm32n6": ["arm-gcc"], "stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"], "xmc4000": ["arm-gcc"], "-bespressif_s2_devkitc": ["esp-idf"], diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake index ea9ffacf4..f52b70408 100644 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake @@ -6,19 +6,14 @@ set(LD_FILE_Clang ${LD_FILE_GNU}) set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32h7s3xx_flash.icf) function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC STM32H7S3xx - SEGGER_RTT_SECTION="noncacheable_buffer" - BUFFER_SIZE_UP=0x3000 ) - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203_reg.c + ${ST_TCPP0203}/tcpp0203.c + ${ST_TCPP0203}/tcpp0203_reg.c ) target_include_directories(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203 + ${ST_TCPP0203} ) endfunction() diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk index 1946f523c..cf0c2ff54 100644 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk @@ -12,12 +12,8 @@ LD_FILE_GCC = $(BOARD_PATH)/stm32h7s3xx_flash.ld LD_FILE_IAR = $(BOARD_PATH)/stm32h7s3xx_flash.icf SRC_C += \ - $(BOARD_PATH)/tcpp0203/tcpp0203.c \ - $(BOARD_PATH)/tcpp0203/tcpp0203_reg.c \ + $(ST_TCPP0203)/tcpp0203.c \ + $(ST_TCPP0203)/tcpp0203_reg.c \ INC += \ - $(TOP)/$(BOARD_PATH)/tcpp0203 \ - -CFLAGS += \ - -DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \ - -DBUFFER_SIZE_UP=0x3000 \ + $(TOP)/$(ST_TCPP0203) \ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt deleted file mode 100644 index 1cbbc544a..000000000 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt +++ /dev/null @@ -1,6 +0,0 @@ -This software component is provided to you as part of a software package and -applicable license terms are in the Package_license file. If you received this -software component outside of a package or without applicable license terms, -the terms of the BSD-3-Clause license shall apply. -You may obtain a copy of the BSD-3-Clause at: -https://opensource.org/licenses/BSD-3-Clause diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html deleted file mode 100644 index 6bbba86a4..000000000 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html +++ /dev/null @@ -1,205 +0,0 @@ - - - - - - - Release Notes for TCPP0203 Component Driver - - - - - - -
-
-
-

Release Notes for TCPP0203 Component Driver

-

Copyright © 2020 STMicroelectronics
-

- -
-

Purpose

-

This driver provides a set of functions needed to drive TCPP0203 Type-C Port Protection component

-
-
-

Update History

-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - -
Headline
MISRA Rule-81.13 correction on TCPP0203 component driver files
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
MISRA corrections on TCPP0203 component driver files
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.8.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
License updates
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.6.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
CodeSpell correction on TCPP0203 component driver files
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.5.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
MCUAstyle correction on TCPP0203 component driver files
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.5.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-
    -
  • First official release of TCPP0203 Type-C port Protection Component drivers
    • -
-
-
-
-
-
-

For complete documentation on STM32,visit: [www.st.com/stm32]

-This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. -
- - diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png deleted file mode 100644 index 06713eec4..000000000 Binary files a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png and /dev/null differ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css deleted file mode 100644 index dd19969d1..000000000 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css +++ /dev/null @@ -1,1703 +0,0 @@ -@charset "UTF-8"; -/* - Flavor name: Custom (mini-custom) - Generated online - https://minicss.org/flavors - mini.css version: v3.0.1 -*/ -/* - Browsers resets and base typography. -*/ -/* Core module CSS variable definitions */ -:root { - --fore-color: #03234b; - --secondary-fore-color: #03234b; - --back-color: #ffffff; - --secondary-back-color: #ffffff; - --blockquote-color: #e6007e; - --pre-color: #e6007e; - --border-color: #3cb4e6; - --secondary-border-color: #3cb4e6; - --heading-ratio: 1.2; - --universal-margin: 0.5rem; - --universal-padding: 0.25rem; - --universal-border-radius: 0.075rem; - --background-margin: 1.5%; - --a-link-color: #3cb4e6; - --a-visited-color: #8c0078; } - -html { - font-size: 13.5px; } - -a, b, del, em, i, ins, q, span, strong, u { - font-size: 1em; } - -html, * { - font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; - line-height: 1.25; - -webkit-text-size-adjust: 100%; } - -* { - font-size: 1rem; } - -body { - margin: 0; - color: var(--fore-color); - @background: var(--back-color); - background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; - background-size: var(--background-margin); - } - -details { - display: block; } - -summary { - display: list-item; } - -abbr[title] { - border-bottom: none; - text-decoration: underline dotted; } - -input { - overflow: visible; } - -img { - max-width: 100%; - height: auto; } - -h1, h2, h3, h4, h5, h6 { - line-height: 1.25; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 400; } - h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { - color: var(--secondary-fore-color); - display: block; - margin-top: -0.25rem; } - -h1 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } - -h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); - border-style: none none solid none ; - border-width: thin; - border-color: var(--border-color); } -h3 { - font-size: calc(1rem * var(--heading-ratio) ); } - -h4 { - font-size: calc(1rem * var(--heading-ratio)); } - -h5 { - font-size: 1rem; } - -h6 { - font-size: calc(1rem / var(--heading-ratio)); } - -p { - margin: var(--universal-margin); } - -ol, ul { - margin: var(--universal-margin); - padding-left: calc(3 * var(--universal-margin)); } - -b, strong { - font-weight: 700; } - -hr { - box-sizing: content-box; - border: 0; - line-height: 1.25em; - margin: var(--universal-margin); - height: 0.0714285714rem; - background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } - -blockquote { - display: block; - position: relative; - font-style: italic; - color: var(--secondary-fore-color); - margin: var(--universal-margin); - padding: calc(3 * var(--universal-padding)); - border: 0.0714285714rem solid var(--secondary-border-color); - border-left: 0.3rem solid var(--blockquote-color); - border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } - blockquote:before { - position: absolute; - top: calc(0rem - var(--universal-padding)); - left: 0; - font-family: sans-serif; - font-size: 2rem; - font-weight: 800; - content: "\201c"; - color: var(--blockquote-color); } - blockquote[cite]:after { - font-style: normal; - font-size: 0.75em; - font-weight: 700; - content: "\a— " attr(cite); - white-space: pre; } - -code, kbd, pre, samp { - font-family: Menlo, Consolas, monospace; - font-size: 0.85em; } - -code { - background: var(--secondary-back-color); - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } - -kbd { - background: var(--fore-color); - color: var(--back-color); - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } - -pre { - overflow: auto; - background: var(--secondary-back-color); - padding: calc(1.5 * var(--universal-padding)); - margin: var(--universal-margin); - border: 0.0714285714rem solid var(--secondary-border-color); - border-left: 0.2857142857rem solid var(--pre-color); - border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } - -sup, sub, code, kbd { - line-height: 0; - position: relative; - vertical-align: baseline; } - -small, sup, sub, figcaption { - font-size: 0.75em; } - -sup { - top: -0.5em; } - -sub { - bottom: -0.25em; } - -figure { - margin: var(--universal-margin); } - -figcaption { - color: var(--secondary-fore-color); } - -a { - text-decoration: none; } - a:link { - color: var(--a-link-color); } - a:visited { - color: var(--a-visited-color); } - a:hover, a:focus { - text-decoration: underline; } - -/* - Definitions for the grid system, cards and containers. -*/ -.container { - margin: 0 auto; - padding: 0 calc(1.5 * var(--universal-padding)); } - -.row { - box-sizing: border-box; - display: flex; - flex: 0 1 auto; - flex-flow: row wrap; - margin: 0 0 0 var(--background-margin); } - -.col-sm, -[class^='col-sm-'], -[class^='col-sm-offset-'], -.row[class*='cols-sm-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - -.col-sm, -.row.cols-sm > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - -.col-sm-1, -.row.cols-sm-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - -.col-sm-offset-0 { - margin-left: 0; } - -.col-sm-2, -.row.cols-sm-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - -.col-sm-offset-1 { - margin-left: 8.3333333333%; } - -.col-sm-3, -.row.cols-sm-3 > * { - max-width: 25%; - flex-basis: 25%; } - -.col-sm-offset-2 { - margin-left: 16.6666666667%; } - -.col-sm-4, -.row.cols-sm-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - -.col-sm-offset-3 { - margin-left: 25%; } - -.col-sm-5, -.row.cols-sm-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - -.col-sm-offset-4 { - margin-left: 33.3333333333%; } - -.col-sm-6, -.row.cols-sm-6 > * { - max-width: 50%; - flex-basis: 50%; } - -.col-sm-offset-5 { - margin-left: 41.6666666667%; } - -.col-sm-7, -.row.cols-sm-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - -.col-sm-offset-6 { - margin-left: 50%; } - -.col-sm-8, -.row.cols-sm-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - -.col-sm-offset-7 { - margin-left: 58.3333333333%; } - -.col-sm-9, -.row.cols-sm-9 > * { - max-width: 75%; - flex-basis: 75%; } - -.col-sm-offset-8 { - margin-left: 66.6666666667%; } - -.col-sm-10, -.row.cols-sm-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - -.col-sm-offset-9 { - margin-left: 75%; } - -.col-sm-11, -.row.cols-sm-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - -.col-sm-offset-10 { - margin-left: 83.3333333333%; } - -.col-sm-12, -.row.cols-sm-12 > * { - max-width: 100%; - flex-basis: 100%; } - -.col-sm-offset-11 { - margin-left: 91.6666666667%; } - -.col-sm-normal { - order: initial; } - -.col-sm-first { - order: -999; } - -.col-sm-last { - order: 999; } - -@media screen and (min-width: 500px) { - .col-md, - [class^='col-md-'], - [class^='col-md-offset-'], - .row[class*='cols-md-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - - .col-md, - .row.cols-md > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - - .col-md-1, - .row.cols-md-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - - .col-md-offset-0 { - margin-left: 0; } - - .col-md-2, - .row.cols-md-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - - .col-md-offset-1 { - margin-left: 8.3333333333%; } - - .col-md-3, - .row.cols-md-3 > * { - max-width: 25%; - flex-basis: 25%; } - - .col-md-offset-2 { - margin-left: 16.6666666667%; } - - .col-md-4, - .row.cols-md-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - - .col-md-offset-3 { - margin-left: 25%; } - - .col-md-5, - .row.cols-md-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - - .col-md-offset-4 { - margin-left: 33.3333333333%; } - - .col-md-6, - .row.cols-md-6 > * { - max-width: 50%; - flex-basis: 50%; } - - .col-md-offset-5 { - margin-left: 41.6666666667%; } - - .col-md-7, - .row.cols-md-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - - .col-md-offset-6 { - margin-left: 50%; } - - .col-md-8, - .row.cols-md-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - - .col-md-offset-7 { - margin-left: 58.3333333333%; } - - .col-md-9, - .row.cols-md-9 > * { - max-width: 75%; - flex-basis: 75%; } - - .col-md-offset-8 { - margin-left: 66.6666666667%; } - - .col-md-10, - .row.cols-md-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - - .col-md-offset-9 { - margin-left: 75%; } - - .col-md-11, - .row.cols-md-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - - .col-md-offset-10 { - margin-left: 83.3333333333%; } - - .col-md-12, - .row.cols-md-12 > * { - max-width: 100%; - flex-basis: 100%; } - - .col-md-offset-11 { - margin-left: 91.6666666667%; } - - .col-md-normal { - order: initial; } - - .col-md-first { - order: -999; } - - .col-md-last { - order: 999; } } -@media screen and (min-width: 1280px) { - .col-lg, - [class^='col-lg-'], - [class^='col-lg-offset-'], - .row[class*='cols-lg-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - - .col-lg, - .row.cols-lg > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - - .col-lg-1, - .row.cols-lg-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - - .col-lg-offset-0 { - margin-left: 0; } - - .col-lg-2, - .row.cols-lg-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - - .col-lg-offset-1 { - margin-left: 8.3333333333%; } - - .col-lg-3, - .row.cols-lg-3 > * { - max-width: 25%; - flex-basis: 25%; } - - .col-lg-offset-2 { - margin-left: 16.6666666667%; } - - .col-lg-4, - .row.cols-lg-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - - .col-lg-offset-3 { - margin-left: 25%; } - - .col-lg-5, - .row.cols-lg-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - - .col-lg-offset-4 { - margin-left: 33.3333333333%; } - - .col-lg-6, - .row.cols-lg-6 > * { - max-width: 50%; - flex-basis: 50%; } - - .col-lg-offset-5 { - margin-left: 41.6666666667%; } - - .col-lg-7, - .row.cols-lg-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - - .col-lg-offset-6 { - margin-left: 50%; } - - .col-lg-8, - .row.cols-lg-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - - .col-lg-offset-7 { - margin-left: 58.3333333333%; } - - .col-lg-9, - .row.cols-lg-9 > * { - max-width: 75%; - flex-basis: 75%; } - - .col-lg-offset-8 { - margin-left: 66.6666666667%; } - - .col-lg-10, - .row.cols-lg-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - - .col-lg-offset-9 { - margin-left: 75%; } - - .col-lg-11, - .row.cols-lg-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - - .col-lg-offset-10 { - margin-left: 83.3333333333%; } - - .col-lg-12, - .row.cols-lg-12 > * { - max-width: 100%; - flex-basis: 100%; } - - .col-lg-offset-11 { - margin-left: 91.6666666667%; } - - .col-lg-normal { - order: initial; } - - .col-lg-first { - order: -999; } - - .col-lg-last { - order: 999; } } -/* Card component CSS variable definitions */ -:root { - --card-back-color: #3cb4e6; - --card-fore-color: #03234b; - --card-border-color: #03234b; } - -.card { - display: flex; - flex-direction: column; - justify-content: space-between; - align-self: center; - position: relative; - width: 100%; - background: var(--card-back-color); - color: var(--card-fore-color); - border: 0.0714285714rem solid var(--card-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); - overflow: hidden; } - @media screen and (min-width: 320px) { - .card { - max-width: 320px; } } - .card > .sectione { - background: var(--card-back-color); - color: var(--card-fore-color); - box-sizing: border-box; - margin: 0; - border: 0; - border-radius: 0; - border-bottom: 0.0714285714rem solid var(--card-border-color); - padding: var(--universal-padding); - width: 100%; } - .card > .sectione.media { - height: 200px; - padding: 0; - -o-object-fit: cover; - object-fit: cover; } - .card > .sectione:last-child { - border-bottom: 0; } - -/* - Custom elements for card elements. -*/ -@media screen and (min-width: 240px) { - .card.small { - max-width: 240px; } } -@media screen and (min-width: 480px) { - .card.large { - max-width: 480px; } } -.card.fluid { - max-width: 100%; - width: auto; } - -.card.warning { - --card-back-color: #e5b8b7; - --card-fore-color: #3b234b; - --card-border-color: #8c0078; } - -.card.error { - --card-back-color: #464650; - --card-fore-color: #ffffff; - --card-border-color: #8c0078; } - -.card > .sectione.dark { - --card-back-color: #3b234b; - --card-fore-color: #ffffff; } - -.card > .sectione.double-padded { - padding: calc(1.5 * var(--universal-padding)); } - -/* - Definitions for forms and input elements. -*/ -/* Input_control module CSS variable definitions */ -:root { - --form-back-color: #ffe97f; - --form-fore-color: #03234b; - --form-border-color: #3cb4e6; - --input-back-color: #ffffff; - --input-fore-color: #03234b; - --input-border-color: #3cb4e6; - --input-focus-color: #0288d1; - --input-invalid-color: #d32f2f; - --button-back-color: #e2e2e2; - --button-hover-back-color: #dcdcdc; - --button-fore-color: #212121; - --button-border-color: transparent; - --button-hover-border-color: transparent; - --button-group-border-color: rgba(124, 124, 124, 0.54); } - -form { - background: var(--form-back-color); - color: var(--form-fore-color); - border: 0.0714285714rem solid var(--form-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); - padding: calc(2 * var(--universal-padding)) var(--universal-padding); } - -fieldset { - border: 0.0714285714rem solid var(--form-border-color); - border-radius: var(--universal-border-radius); - margin: calc(var(--universal-margin) / 4); - padding: var(--universal-padding); } - -legend { - box-sizing: border-box; - display: table; - max-width: 100%; - white-space: normal; - font-weight: 500; - padding: calc(var(--universal-padding) / 2); } - -label { - padding: calc(var(--universal-padding) / 2) var(--universal-padding); } - -.input-group { - display: inline-block; } - .input-group.fluid { - display: flex; - align-items: center; - justify-content: center; } - .input-group.fluid > input { - max-width: 100%; - flex-grow: 1; - flex-basis: 0px; } - @media screen and (max-width: 499px) { - .input-group.fluid { - align-items: stretch; - flex-direction: column; } } - .input-group.vertical { - display: flex; - align-items: stretch; - flex-direction: column; } - .input-group.vertical > input { - max-width: 100%; - flex-grow: 1; - flex-basis: 0px; } - -[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { - height: auto; } - -[type="search"] { - -webkit-appearance: textfield; - outline-offset: -2px; } - -[type="search"]::-webkit-search-cancel-button, -[type="search"]::-webkit-search-decoration { - -webkit-appearance: none; } - -input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], -[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { - box-sizing: border-box; - background: var(--input-back-color); - color: var(--input-fore-color); - border: 0.0714285714rem solid var(--input-border-color); - border-radius: var(--universal-border-radius); - margin: calc(var(--universal-margin) / 2); - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } - -input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { - border-color: var(--input-focus-color); - box-shadow: none; } -input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { - border-color: var(--input-invalid-color); - box-shadow: none; } -input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { - background: var(--secondary-back-color); } - -select { - max-width: 100%; } - -option { - overflow: hidden; - text-overflow: ellipsis; } - -[type="checkbox"], [type="radio"] { - -webkit-appearance: none; - -moz-appearance: none; - appearance: none; - position: relative; - height: calc(1rem + var(--universal-padding) / 2); - width: calc(1rem + var(--universal-padding) / 2); - vertical-align: text-bottom; - padding: 0; - flex-basis: calc(1rem + var(--universal-padding) / 2) !important; - flex-grow: 0 !important; } - [type="checkbox"]:checked:before, [type="radio"]:checked:before { - position: absolute; } - -[type="checkbox"]:checked:before { - content: '\2713'; - font-family: sans-serif; - font-size: calc(1rem + var(--universal-padding) / 2); - top: calc(0rem - var(--universal-padding)); - left: calc(var(--universal-padding) / 4); } - -[type="radio"] { - border-radius: 100%; } - [type="radio"]:checked:before { - border-radius: 100%; - content: ''; - top: calc(0.0714285714rem + var(--universal-padding) / 2); - left: calc(0.0714285714rem + var(--universal-padding) / 2); - background: var(--input-fore-color); - width: 0.5rem; - height: 0.5rem; } - -:placeholder-shown { - color: var(--input-fore-color); } - -::-ms-placeholder { - color: var(--input-fore-color); - opacity: 0.54; } - -button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { - border-style: none; - padding: 0; } - -button, html [type="button"], [type="reset"], [type="submit"] { - -webkit-appearance: button; } - -button { - overflow: visible; - text-transform: none; } - -button, [type="button"], [type="submit"], [type="reset"], -a.button, label.button, .button, -a[role="button"], label[role="button"], [role="button"] { - display: inline-block; - background: var(--button-back-color); - color: var(--button-fore-color); - border: 0.0714285714rem solid var(--button-border-color); - border-radius: var(--universal-border-radius); - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); - margin: var(--universal-margin); - text-decoration: none; - cursor: pointer; - transition: background 0.3s; } - button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, - a.button:hover, - a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, - a[role="button"]:hover, - a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { - background: var(--button-hover-back-color); - border-color: var(--button-hover-border-color); } - -input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { - cursor: not-allowed; - opacity: 0.75; } - -.button-group { - display: flex; - border: 0.0714285714rem solid var(--button-group-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); } - .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { - margin: 0; - max-width: 100%; - flex: 1 1 auto; - text-align: center; - border: 0; - border-radius: 0; - box-shadow: none; } - .button-group > :not(:first-child) { - border-left: 0.0714285714rem solid var(--button-group-border-color); } - @media screen and (max-width: 499px) { - .button-group { - flex-direction: column; } - .button-group > :not(:first-child) { - border: 0; - border-top: 0.0714285714rem solid var(--button-group-border-color); } } - -/* - Custom elements for forms and input elements. -*/ -button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { - --button-back-color: #1976d2; - --button-fore-color: #f8f8f8; } - button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { - --button-hover-back-color: #1565c0; } - -button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { - --button-back-color: #d32f2f; - --button-fore-color: #f8f8f8; } - button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { - --button-hover-back-color: #c62828; } - -button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { - --button-back-color: #308732; - --button-fore-color: #f8f8f8; } - button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { - --button-hover-back-color: #277529; } - -button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { - --button-back-color: #212121; - --button-fore-color: #f8f8f8; } - button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { - --button-hover-back-color: #111; } - -button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { - padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); - margin: var(--universal-margin); } - -button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { - padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); - margin: var(--universal-margin); } - -/* - Definitions for navigation elements. -*/ -/* Navigation module CSS variable definitions */ -:root { - --header-back-color: #03234b; - --header-hover-back-color: #ffd200; - --header-fore-color: #ffffff; - --header-border-color: #3cb4e6; - --nav-back-color: #ffffff; - --nav-hover-back-color: #ffe97f; - --nav-fore-color: #e6007e; - --nav-border-color: #3cb4e6; - --nav-link-color: #3cb4e6; - --footer-fore-color: #ffffff; - --footer-back-color: #03234b; - --footer-border-color: #3cb4e6; - --footer-link-color: #3cb4e6; - --drawer-back-color: #ffffff; - --drawer-hover-back-color: #ffe97f; - --drawer-border-color: #3cb4e6; - --drawer-close-color: #e6007e; } - -header { - height: 2.75rem; - background: var(--header-back-color); - color: var(--header-fore-color); - border-bottom: 0.0714285714rem solid var(--header-border-color); - padding: calc(var(--universal-padding) / 4) 0; - white-space: nowrap; - overflow-x: auto; - overflow-y: hidden; } - header.row { - box-sizing: content-box; } - header .logo { - color: var(--header-fore-color); - font-size: 1.75rem; - padding: var(--universal-padding) calc(2 * var(--universal-padding)); - text-decoration: none; } - header button, header [type="button"], header .button, header [role="button"] { - box-sizing: border-box; - position: relative; - top: calc(0rem - var(--universal-padding) / 4); - height: calc(3.1875rem + var(--universal-padding) / 2); - background: var(--header-back-color); - line-height: calc(3.1875rem - var(--universal-padding) * 1.5); - text-align: center; - color: var(--header-fore-color); - border: 0; - border-radius: 0; - margin: 0; - text-transform: uppercase; } - header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { - background: var(--header-hover-back-color); } - -nav { - background: var(--nav-back-color); - color: var(--nav-fore-color); - border: 0.0714285714rem solid var(--nav-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); } - nav * { - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } - nav a, nav a:visited { - display: block; - color: var(--nav-link-color); - border-radius: var(--universal-border-radius); - transition: background 0.3s; } - nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { - text-decoration: none; - background: var(--nav-hover-back-color); } - nav .sublink-1 { - position: relative; - margin-left: calc(2 * var(--universal-padding)); } - nav .sublink-1:before { - position: absolute; - left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0714285714rem; - content: ''; - height: 100%; - border: 0.0714285714rem solid var(--nav-border-color); - border-left: 0; } - nav .sublink-2 { - position: relative; - margin-left: calc(4 * var(--universal-padding)); } - nav .sublink-2:before { - position: absolute; - left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0714285714rem; - content: ''; - height: 100%; - border: 0.0714285714rem solid var(--nav-border-color); - border-left: 0; } - -footer { - background: var(--footer-back-color); - color: var(--footer-fore-color); - border-top: 0.0714285714rem solid var(--footer-border-color); - padding: calc(2 * var(--universal-padding)) var(--universal-padding); - font-size: 0.875rem; } - footer a, footer a:visited { - color: var(--footer-link-color); } - -header.sticky { - position: -webkit-sticky; - position: sticky; - z-index: 1101; - top: 0; } - -footer.sticky { - position: -webkit-sticky; - position: sticky; - z-index: 1101; - bottom: 0; } - -.drawer-toggle:before { - display: inline-block; - position: relative; - vertical-align: bottom; - content: '\00a0\2261\00a0'; - font-family: sans-serif; - font-size: 1.5em; } -@media screen and (min-width: 500px) { - .drawer-toggle:not(.persistent) { - display: none; } } - -[type="checkbox"].drawer { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - [type="checkbox"].drawer + * { - display: block; - box-sizing: border-box; - position: fixed; - top: 0; - width: 320px; - height: 100vh; - overflow-y: auto; - background: var(--drawer-back-color); - border: 0.0714285714rem solid var(--drawer-border-color); - border-radius: 0; - margin: 0; - z-index: 1110; - right: -320px; - transition: right 0.3s; } - [type="checkbox"].drawer + * .drawer-close { - position: absolute; - top: var(--universal-margin); - right: var(--universal-margin); - z-index: 1111; - width: 2rem; - height: 2rem; - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - margin: 0; - cursor: pointer; - transition: background 0.3s; } - [type="checkbox"].drawer + * .drawer-close:before { - display: block; - content: '\00D7'; - color: var(--drawer-close-color); - position: relative; - font-family: sans-serif; - font-size: 2rem; - line-height: 1; - text-align: center; } - [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { - background: var(--drawer-hover-back-color); } - @media screen and (max-width: 320px) { - [type="checkbox"].drawer + * { - width: 100%; } } - [type="checkbox"].drawer:checked + * { - right: 0; } - @media screen and (min-width: 500px) { - [type="checkbox"].drawer:not(.persistent) + * { - position: static; - height: 100%; - z-index: 1100; } - [type="checkbox"].drawer:not(.persistent) + * .drawer-close { - display: none; } } - -/* - Definitions for the responsive table component. -*/ -/* Table module CSS variable definitions. */ -:root { - --table-border-color: #03234b; - --table-border-separator-color: #03234b; - --table-head-back-color: #03234b; - --table-head-fore-color: #ffffff; - --table-body-back-color: #ffffff; - --table-body-fore-color: #03234b; - --table-body-alt-back-color: #f4f4f4; } - -table { - border-collapse: separate; - border-spacing: 0; - margin: 0; - display: flex; - flex: 0 1 auto; - flex-flow: row wrap; - padding: var(--universal-padding); - padding-top: 0; } - table caption { - font-size: 1rem; - margin: calc(2 * var(--universal-margin)) 0; - max-width: 100%; - flex: 0 0 100%; } - table thead, table tbody { - display: flex; - flex-flow: row wrap; - border: 0.0714285714rem solid var(--table-border-color); } - table thead { - z-index: 999; - border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } - table tbody { - border-top: 0; - margin-top: calc(0 - var(--universal-margin)); - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - table tr { - display: flex; - padding: 0; } - table th, table td { - padding: calc(0.5 * var(--universal-padding)); - font-size: 0.9rem; } - table th { - text-align: left; - background: var(--table-head-back-color); - color: var(--table-head-fore-color); } - table td { - background: var(--table-body-back-color); - color: var(--table-body-fore-color); - border-top: 0.0714285714rem solid var(--table-border-color); } - -table:not(.horizontal) { - overflow: auto; - max-height: 100%; } - table:not(.horizontal) thead, table:not(.horizontal) tbody { - max-width: 100%; - flex: 0 0 100%; } - table:not(.horizontal) tr { - flex-flow: row wrap; - flex: 0 0 100%; } - table:not(.horizontal) th, table:not(.horizontal) td { - flex: 1 0 0%; - overflow: hidden; - text-overflow: ellipsis; } - table:not(.horizontal) thead { - position: sticky; - top: 0; } - table:not(.horizontal) tbody tr:first-child td { - border-top: 0; } - -table.horizontal { - border: 0; } - table.horizontal thead, table.horizontal tbody { - border: 0; - flex: .2 0 0; - flex-flow: row nowrap; } - table.horizontal tbody { - overflow: auto; - justify-content: space-between; - flex: .8 0 0; - margin-left: 0; - padding-bottom: calc(var(--universal-padding) / 4); } - table.horizontal tr { - flex-direction: column; - flex: 1 0 auto; } - table.horizontal th, table.horizontal td { - width: auto; - border: 0; - border-bottom: 0.0714285714rem solid var(--table-border-color); } - table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { - border-top: 0; } - table.horizontal th { - text-align: right; - border-left: 0.0714285714rem solid var(--table-border-color); - border-right: 0.0714285714rem solid var(--table-border-separator-color); } - table.horizontal thead tr:first-child { - padding-left: 0; } - table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0714285714rem solid var(--table-border-color); } - table.horizontal tbody tr:last-child td { - border-right: 0.0714285714rem solid var(--table-border-color); } - table.horizontal tbody tr:last-child td:first-child { - border-top-right-radius: 0.25rem; } - table.horizontal tbody tr:last-child td:last-child { - border-bottom-right-radius: 0.25rem; } - table.horizontal thead tr:first-child th:first-child { - border-top-left-radius: 0.25rem; } - table.horizontal thead tr:first-child th:last-child { - border-bottom-left-radius: 0.25rem; } - -@media screen and (max-width: 499px) { - table, table.horizontal { - border-collapse: collapse; - border: 0; - width: 100%; - display: table; } - table thead, table th, table.horizontal thead, table.horizontal th { - border: 0; - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - padding: 0; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - table tbody, table.horizontal tbody { - border: 0; - display: table-row-group; } - table tr, table.horizontal tr { - display: block; - border: 0.0714285714rem solid var(--table-border-color); - border-radius: var(--universal-border-radius); - background: #ffffff; - padding: var(--universal-padding); - margin: var(--universal-margin); - margin-bottom: calc(1 * var(--universal-margin)); } - table th, table td, table.horizontal th, table.horizontal td { - width: auto; } - table td, table.horizontal td { - display: block; - border: 0; - text-align: right; } - table td:before, table.horizontal td:before { - content: attr(data-label); - float: left; - font-weight: 600; } - table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0; } - table tbody tr:last-child td, table.horizontal tbody tr:last-child td { - border-right: 0; } } -table tr:nth-of-type(2n) > td { - background: var(--table-body-alt-back-color); } - -@media screen and (max-width: 500px) { - table tr:nth-of-type(2n) { - background: var(--table-body-alt-back-color); } } -:root { - --table-body-hover-back-color: #90caf9; } - -table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { - background: var(--table-body-hover-back-color); } - -@media screen and (max-width: 500px) { - table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { - background: var(--table-body-hover-back-color); } } -/* - Definitions for contextual background elements, toasts and tooltips. -*/ -/* Contextual module CSS variable definitions */ -:root { - --mark-back-color: #3cb4e6; - --mark-fore-color: #ffffff; } - -mark { - background: var(--mark-back-color); - color: var(--mark-fore-color); - font-size: 0.95em; - line-height: 1em; - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) var(--universal-padding); } - mark.inline-block { - display: inline-block; - font-size: 1em; - line-height: 1.4; - padding: calc(var(--universal-padding) / 2) var(--universal-padding); } - -:root { - --toast-back-color: #424242; - --toast-fore-color: #fafafa; } - -.toast { - position: fixed; - bottom: calc(var(--universal-margin) * 3); - left: 50%; - transform: translate(-50%, -50%); - z-index: 1111; - color: var(--toast-fore-color); - background: var(--toast-back-color); - border-radius: calc(var(--universal-border-radius) * 16); - padding: var(--universal-padding) calc(var(--universal-padding) * 3); } - -:root { - --tooltip-back-color: #212121; - --tooltip-fore-color: #fafafa; } - -.tooltip { - position: relative; - display: inline-block; } - .tooltip:before, .tooltip:after { - position: absolute; - opacity: 0; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); - transition: all 0.3s; - z-index: 1010; - left: 50%; } - .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { - bottom: 75%; } - .tooltip.bottom:before, .tooltip.bottom:after { - top: 75%; } - .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { - opacity: 1; - clip: auto; - -webkit-clip-path: inset(0%); - clip-path: inset(0%); } - .tooltip:before { - content: ''; - background: transparent; - border: var(--universal-margin) solid transparent; - left: calc(50% - var(--universal-margin)); } - .tooltip:not(.bottom):before { - border-top-color: #212121; } - .tooltip.bottom:before { - border-bottom-color: #212121; } - .tooltip:after { - content: attr(aria-label); - color: var(--tooltip-fore-color); - background: var(--tooltip-back-color); - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - white-space: nowrap; - transform: translateX(-50%); } - .tooltip:not(.bottom):after { - margin-bottom: calc(2 * var(--universal-margin)); } - .tooltip.bottom:after { - margin-top: calc(2 * var(--universal-margin)); } - -:root { - --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #e6007e; - --modal-close-hover-color: #ffe97f; } - -[type="checkbox"].modal { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - [type="checkbox"].modal + div { - position: fixed; - top: 0; - left: 0; - display: none; - width: 100vw; - height: 100vh; - background: var(--modal-overlay-color); } - [type="checkbox"].modal + div .card { - margin: 0 auto; - max-height: 50vh; - overflow: auto; } - [type="checkbox"].modal + div .card .modal-close { - position: absolute; - top: 0; - right: 0; - width: 1.75rem; - height: 1.75rem; - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - margin: 0; - cursor: pointer; - transition: background 0.3s; } - [type="checkbox"].modal + div .card .modal-close:before { - display: block; - content: '\00D7'; - color: var(--modal-close-color); - position: relative; - font-family: sans-serif; - font-size: 1.75rem; - line-height: 1; - text-align: center; } - [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { - background: var(--modal-close-hover-color); } - [type="checkbox"].modal:checked + div { - display: flex; - flex: 0 1 auto; - z-index: 1200; } - [type="checkbox"].modal:checked + div .card .modal-close { - z-index: 1211; } - -:root { - --collapse-label-back-color: #03234b; - --collapse-label-fore-color: #ffffff; - --collapse-label-hover-back-color: #3cb4e6; - --collapse-selected-label-back-color: #3cb4e6; - --collapse-border-color: var(--collapse-label-back-color); - --collapse-selected-border-color: #ceecf8; - --collapse-content-back-color: #ffffff; - --collapse-selected-label-border-color: #3cb4e6; } - -.collapse { - width: calc(100% - 2 * var(--universal-margin)); - opacity: 1; - display: flex; - flex-direction: column; - margin: var(--universal-margin); - border-radius: var(--universal-border-radius); } - .collapse > [type="radio"], .collapse > [type="checkbox"] { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - .collapse > label { - flex-grow: 1; - display: inline-block; - height: 1.25rem; - cursor: pointer; - transition: background 0.2s; - color: var(--collapse-label-fore-color); - background: var(--collapse-label-back-color); - border: 0.0714285714rem solid var(--collapse-selected-border-color); - padding: calc(1.25 * var(--universal-padding)); } - .collapse > label:hover, .collapse > label:focus { - background: var(--collapse-label-hover-back-color); } - .collapse > label + div { - flex-basis: auto; - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); - transition: max-height 0.3s; - max-height: 1px; } - .collapse > :checked + label { - background: var(--collapse-selected-label-back-color); - border-color: var(--collapse-selected-label-border-color); } - .collapse > :checked + label + div { - box-sizing: border-box; - position: relative; - width: 100%; - height: auto; - overflow: auto; - margin: 0; - background: var(--collapse-content-back-color); - border: 0.0714285714rem solid var(--collapse-selected-border-color); - border-top: 0; - padding: var(--universal-padding); - clip: auto; - -webkit-clip-path: inset(0%); - clip-path: inset(0%); - max-height: 100%; } - .collapse > label:not(:first-of-type) { - border-top: 0; } - .collapse > label:first-of-type { - border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } - .collapse > label:last-of-type:not(:first-of-type) { - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - .collapse > label:last-of-type:first-of-type { - border-radius: var(--universal-border-radius); } - .collapse > :checked:last-of-type:not(:first-of-type) + label { - border-radius: 0; } - .collapse > :checked:last-of-type + label + div { - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - -/* - Custom elements for contextual background elements, toasts and tooltips. -*/ -mark.tertiary { - --mark-back-color: #3cb4e6; } - -mark.tag { - padding: calc(var(--universal-padding)/2) var(--universal-padding); - border-radius: 1em; } - -/* - Definitions for progress elements and spinners. -*/ -/* Progress module CSS variable definitions */ -:root { - --progress-back-color: #3cb4e6; - --progress-fore-color: #555; } - -progress { - display: block; - vertical-align: baseline; - -webkit-appearance: none; - -moz-appearance: none; - appearance: none; - height: 0.75rem; - width: calc(100% - 2 * var(--universal-margin)); - margin: var(--universal-margin); - border: 0; - border-radius: calc(2 * var(--universal-border-radius)); - background: var(--progress-back-color); - color: var(--progress-fore-color); } - progress::-webkit-progress-value { - background: var(--progress-fore-color); - border-top-left-radius: calc(2 * var(--universal-border-radius)); - border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } - progress::-webkit-progress-bar { - background: var(--progress-back-color); } - progress::-moz-progress-bar { - background: var(--progress-fore-color); - border-top-left-radius: calc(2 * var(--universal-border-radius)); - border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } - progress[value="1000"]::-webkit-progress-value { - border-radius: calc(2 * var(--universal-border-radius)); } - progress[value="1000"]::-moz-progress-bar { - border-radius: calc(2 * var(--universal-border-radius)); } - progress.inline { - display: inline-block; - vertical-align: middle; - width: 60%; } - -:root { - --spinner-back-color: #ddd; - --spinner-fore-color: #555; } - -@keyframes spinner-donut-anim { - 0% { - transform: rotate(0deg); } - 100% { - transform: rotate(360deg); } } -.spinner { - display: inline-block; - margin: var(--universal-margin); - border: 0.25rem solid var(--spinner-back-color); - border-left: 0.25rem solid var(--spinner-fore-color); - border-radius: 50%; - width: 1.25rem; - height: 1.25rem; - animation: spinner-donut-anim 1.2s linear infinite; } - -/* - Custom elements for progress bars and spinners. -*/ -progress.primary { - --progress-fore-color: #1976d2; } - -progress.secondary { - --progress-fore-color: #d32f2f; } - -progress.tertiary { - --progress-fore-color: #308732; } - -.spinner.primary { - --spinner-fore-color: #1976d2; } - -.spinner.secondary { - --spinner-fore-color: #d32f2f; } - -.spinner.tertiary { - --spinner-fore-color: #308732; } - -/* - Definitions for icons - powered by Feather (https://feathericons.com/). -*/ -span[class^='icon-'] { - display: inline-block; - height: 1em; - width: 1em; - vertical-align: -0.125em; - background-size: contain; - margin: 0 calc(var(--universal-margin) / 4); } - span[class^='icon-'].secondary { - -webkit-filter: invert(25%); - filter: invert(25%); } - span[class^='icon-'].inverse { - -webkit-filter: invert(100%); - filter: invert(100%); } - -span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } -span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } -span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } -span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } -span.icon-phone { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-rss { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } -span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-share { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } - -/* - Definitions for utilities and helper classes. -*/ -/* Utility module CSS variable definitions */ -:root { - --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } - -.hidden { - display: none !important; } - -.visually-hidden { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; 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- width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } } - -/*# sourceMappingURL=mini-custom.css.map */ - -img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } -img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} - -.figure { - display: block; - margin-left: auto; - margin-right: auto; - text-align: center; -} diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png deleted file mode 100644 index d6cebb5ac..000000000 Binary files a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png and /dev/null differ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c deleted file mode 100644 index 952ff16c9..000000000 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c +++ /dev/null @@ -1,886 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203.c - * @author MCD Application Team - * @brief This file provides the TCPP02/03 Type-C port protection driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tcpp0203.h" - -#if defined(_TRACE) -#include "usbpd_core.h" -#include "usbpd_trace.h" -#include "string.h" -#include "stdio.h" -#endif /* _TRACE */ - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup TCPP0203 - * @brief This file provides a set of functions needed to drive the - * TCPP02/03 Type-C port protection. - * @{ - */ - -/** @defgroup TCPP0203_Private_Constants Private Constants - * @{ - */ - -/* Compilation option in order to enable/disable a concistency check performed - after each I2C access into TCPP0203 registers : goal is to check that written value in Reg0 - is properly reflected into reg1 register content. - To enable register consistency check, please uncomment below definition. - To disable it, comment below line */ -/* #define TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** @defgroup TCPP0203_Private_Types Private Types - * @{ - */ -/* TCPP02/03 Type-C port protection driver structure initialization */ -TCPP0203_Drv_t TCPP0203_Driver = -{ - TCPP0203_Init, - TCPP0203_DeInit, - TCPP0203_Reset, - TCPP0203_SetVConnSwitch, - TCPP0203_SetGateDriverProvider, - TCPP0203_SetGateDriverConsumer, - TCPP0203_SetPowerMode, - TCPP0203_SetVBusDischarge, - TCPP0203_SetVConnDischarge, - TCPP0203_GetVConnSwitchAck, - TCPP0203_GetGateDriverProviderAck, - TCPP0203_GetGateDriverConsumerAck, - TCPP0203_GetPowerModeAck, - TCPP0203_GetVBusDischargeAck, - TCPP0203_GetVConnDischargeAck, - TCPP0203_GetOCPVConnFlag, - TCPP0203_GetOCPVBusFlag, - TCPP0203_GetOVPVBusFlag, - TCPP0203_GetOVPCCFlag, - TCPP0203_GetOTPFlag, - TCPP0203_GetVBusOkFlag, - TCPP0203_ReadTCPPType, - TCPP0203_ReadVCONNPower, - TCPP0203_WriteCtrlRegister, - TCPP0203_ReadAckRegister, - TCPP0203_ReadFlagRegister, -}; - -/** - * @} - */ - -/** @defgroup TCPP0203_Private_Variables Private Variables - * @{ - */ -static uint8_t TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_03; - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) -static uint8_t Reg0_Expected_Value = 0x00; -static uint8_t Reg1_LastRead_Value = 0x00; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup TCPP0203_Private_Function_Prototypes TCPP0203 Private Function Prototypes - * @{ - */ -static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); -static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); - -static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) -static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue); -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions - * @{ - */ - -/** - * @brief Register Bus Io to component - * @param Component object pointer - * @retval Status of execution - */ -int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO) -{ - int32_t ret; - - if (pObj == NULL) - { - ret = TCPP0203_ERROR; - } - else - { - pObj->IO.Init = pIO->Init; - pObj->IO.DeInit = pIO->DeInit; - pObj->IO.Address = pIO->Address; - pObj->IO.WriteReg = pIO->WriteReg; - pObj->IO.ReadReg = pIO->ReadReg; - pObj->IO.GetTick = pIO->GetTick; - - pObj->Ctx.ReadReg = TCPP0203_ReadRegWrap; - pObj->Ctx.WriteReg = TCPP0203_WriteRegWrap; - pObj->Ctx.handle = pObj; - - if (pObj->IO.Init != NULL) - { - ret = pObj->IO.Init(); - } - else - { - ret = TCPP0203_ERROR; - } - } - - return ret; -} - -/** - * @brief Initializes the TCPP0203 interface - * @param pObj Pointer to component object - * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) - */ -int32_t TCPP0203_Init(TCPP0203_Object_t *pObj) -{ - int32_t ret = 0; - uint8_t tmp; - - if (pObj->IsInitialized == 0U) - { - /* Read TCPP Device type */ - ret += tcpp0203_read_reg(&pObj->Ctx, TCPP0203_READ_REG2, &tmp, 1); - - if (ret == TCPP0203_OK) - { - TCPP0203_DeviceType = (tmp & TCPP0203_DEVICE_TYPE_MSK); - } - else - { - TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_02; - } - pObj->IsInitialized = 1U; - } - - if (ret != TCPP0203_OK) - { - ret = TCPP0203_ERROR; - } - - return ret; -} - -/** - * @brief Deinitializes the TCPP0203 interface - * @param pObj Pointer to component object - * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) - */ -int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj) -{ - if (pObj->IsInitialized == 1U) - { - /* De-Initialize IO BUS layer */ - pObj->IO.DeInit(); - - pObj->IsInitialized = 0U; - } - - return TCPP0203_OK; -} - -/** - * @brief Resets TCPP0203 register (Reg0) - * @param pObj Pointer to component object - * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) - */ -int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj) -{ - int32_t ret = TCPP0203_OK; - uint8_t tmp = TCPP0203_REG0_RST_VALUE; - - /* Write reset values in Reg0 register */ - if (tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1) != TCPP0203_OK) - { - ret = TCPP0203_ERROR; - } - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = TCPP0203_REG0_RST_VALUE; - Reg1_LastRead_Value = TCPP0203_REG0_RST_VALUE; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return ret; -} - -/** - * @brief Configure TCPP0203 VConn Switch - * @param pObj Pointer to component object - * @param VConnSwitch VConn Switch requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open - * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 - * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 - * @retval Component status - */ -int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch) -{ - int32_t ret = TCPP0203_OK; - - if ((VConnSwitch != TCPP0203_VCONN_SWITCH_OPEN) - && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC1) - && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC2)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update VConn switch setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, VConnSwitch, TCPP0203_VCONN_SWITCH_MSK); - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Provider path - * @param pObj Pointer to component object - * @param GateDriverProvider GDP switch load requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_GD_PROVIDER_SWITCH_OPEN GDP Switch Load Open - * @arg TCPP0203_GD_PROVIDER_SWITCH_CLOSED GDP Switch Load closed - * @retval Component status - */ -int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider) -{ - int32_t ret = TCPP0203_OK; - - if ((GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_OPEN) - && (GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_CLOSED)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update GDP Switch Load setting in Writing register Reg0 */ - if (GateDriverProvider == TCPP0203_GD_PROVIDER_SWITCH_CLOSED) - { - /* If Gate Driver Provider is to be closed, Gate Driver Consumer should be open */ - ret += TCPP0203_ModifyReg0(pObj, (GateDriverProvider | TCPP0203_GD_CONSUMER_SWITCH_OPEN), - (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); - } - else - { - ret += TCPP0203_ModifyReg0(pObj, GateDriverProvider, TCPP0203_GD_PROVIDER_SWITCH_MSK); - } - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Consumer path - * @param pObj Pointer to component object - * @param GateDriverConsumer GDC switch load requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_GD_CONSUMER_SWITCH_OPEN GDC Switch Load Open - * @arg TCPP0203_GD_CONSUMER_SWITCH_CLOSED GDC Switch Load closed - * @retval Component status - */ -int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer) -{ - int32_t ret = TCPP0203_OK; - - /* Check if TCPP type is TCPP03. Otherwise, return error */ - if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) - { - return (TCPP0203_ERROR); - } - - if ((GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_OPEN) - && (GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_CLOSED)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update GDC Switch Load setting in Writing register Reg0 */ - if (GateDriverConsumer == TCPP0203_GD_CONSUMER_SWITCH_CLOSED) - { - /* If Gate Driver Consumer is to be closed, Gate Driver Provider should be open */ - ret += TCPP0203_ModifyReg0(pObj, (GateDriverConsumer | TCPP0203_GD_PROVIDER_SWITCH_OPEN), - (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); - } - else - { - ret += TCPP0203_ModifyReg0(pObj, GateDriverConsumer, TCPP0203_GD_CONSUMER_SWITCH_MSK); - } - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Power Mode - * @param pObj Pointer to component object - * @param PowerMode Power mode requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_POWER_MODE_HIBERNATE Hibernate - * @arg TCPP0203_POWER_MODE_LOWPOWER Low Power - * @arg TCPP0203_POWER_MODE_NORMAL Normal - * @retval Component status - */ -int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode) -{ - int32_t ret = TCPP0203_OK; - - if ((PowerMode != TCPP0203_POWER_MODE_HIBERNATE) - && (PowerMode != TCPP0203_POWER_MODE_LOWPOWER) - && (PowerMode != TCPP0203_POWER_MODE_NORMAL)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update Power Mode setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, PowerMode, TCPP0203_POWER_MODE_MSK); - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Provider path - * @param pObj Pointer to component object - * @param VBusDischarge VBUS Discharge requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_VBUS_DISCHARGE_OFF VBUS Discharge Off - * @arg TCPP0203_VBUS_DISCHARGE_ON VBUS Discharge On - * @retval Component status - */ -int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge) -{ - int32_t ret = TCPP0203_OK; - - if ((VBusDischarge != TCPP0203_VBUS_DISCHARGE_OFF) - && (VBusDischarge != TCPP0203_VBUS_DISCHARGE_ON)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update VBUS Discharge setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, VBusDischarge, TCPP0203_VBUS_DISCHARGE_MSK); - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Provider path - * @param pObj Pointer to component object - * @param VConnDischarge GDP switch load requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_VCONN_DISCHARGE_OFF VConn Discharge Off - * @arg TCPP0203_VCONN_DISCHARGE_ON VConn Discharge On - * @retval Component status - */ -int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge) -{ - int32_t ret = TCPP0203_OK; - - if ((VConnDischarge != TCPP0203_VCONN_DISCHARGE_OFF) - && (VConnDischarge != TCPP0203_VCONN_DISCHARGE_ON)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update VConn Discharge setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, VConnDischarge, TCPP0203_VCONN_DISCHARGE_MSK); - } - - return ret; -} - -/** - * @brief Get VConn switch Ack value - * @param pObj Pointer to component object - * @param pVConnSwitchAck Pointer on VConn switch Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open Ack - * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 Ack - * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 Ack - * @retval Component status - */ -int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pVConnSwitchAck = (tmp & TCPP0203_VCONN_SWITCH_ACK_MSK); - - return ret; -} - -/** - * @brief Get Gate Driver Provider Ack value - * @param pObj Pointer to component object - * @param pGateDriverProviderAck Pointer on Gate Driver Provider Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN Gate Driver Provider Open Ack - * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED Gate Driver Provider Closed Ack - * @retval Component status - */ -int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pGateDriverProviderAck = (tmp & TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK); - - return ret; -} - -/** - * @brief Get Gate Driver Consumer Ack value - * @param pObj Pointer to component object - * @param pGateDriverConsumerAck Pointer on Gate Driver Consumer Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN Gate Driver Consumer Open Ack - * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED Gate Driver Consumer Closed Ack - * @retval Component status - */ -int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck) -{ - int32_t ret; - uint8_t tmp; - - /* Check if TCPP type is TCPP03. Otherwise, return error */ - if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) - { - return (TCPP0203_ERROR); - } - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pGateDriverConsumerAck = (tmp & TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK); - - return ret; -} - -/** - * @brief Get Power Mode Ack value - * @param pObj Pointer to component object - * @param pPowerModeAck Pointer on Power Mode Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_POWER_MODE_ACK_HIBERNATE Power Mode Hibernate Ack - * @arg TCPP0203_POWER_MODE_ACK_LOWPOWER Power Mode Low Power Ack - * @arg TCPP0203_POWER_MODE_ACK_NORMAL Power Mode Normal Ack - * @retval Component status - */ -int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pPowerModeAck = (tmp & TCPP0203_POWER_MODE_ACK_MSK); - - return ret; -} - -/** - * @brief Get VBUS Discharge Ack value - * @param pObj Pointer to component object - * @param pVBusDischargeAck Pointer on VBUS Discharge Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_VBUS_DISCHARGE_ACK_OFF VBUS Discharge Off Ack - * @arg TCPP0203_VBUS_DISCHARGE_ACK_ON VBUS Discharge On Ack - * @retval Component status - */ -int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pVBusDischargeAck = (tmp & TCPP0203_VBUS_DISCHARGE_ACK_MSK); - - return ret; -} - -/** - * @brief Get VConn Discharge Ack value - * @param pObj Pointer to component object - * @param pVConnDischargeAck Pointer on VConn Discharge Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_VCONN_DISCHARGE_ACK_OFF VConn Discharge Off Ack - * @arg TCPP0203_VCONN_DISCHARGE_ACK_ON VConn Discharge On Ack - * @retval Component status - */ -int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pVConnDischargeAck = (tmp & TCPP0203_VCONN_DISCHARGE_ACK_MSK); - - return ret; -} - -/** - * @brief Get OCP VConn Flag value - * @param pObj Pointer to component object - * @param pOCPVConnFlag Pointer on OCP VConn Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OCP_VCONN_RESET OCP VConn flag not set - * @arg TCPP0203_FLAG_OCP_VCONN_SET OCP VConn flag set - * @retval Component status - */ -int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOCPVConnFlag = (tmp & TCPP0203_FLAG_OCP_VCONN_MSK); - - return ret; -} - -/** - * @brief Get OCP VBUS Flag value - * @param pObj Pointer to component object - * @param pGetOCPVBusFlag Pointer on OCP VBUS Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OCP_VBUS_RESET OCP VBUS flag not set - * @arg TCPP0203_FLAG_OCP_VBUS_SET OCP VBUS flag set - * @retval Component status - */ -int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pGetOCPVBusFlag = (tmp & TCPP0203_FLAG_OCP_VBUS_MSK); - - return ret; -} - -/** - * @brief Get OVP VBUS Flag value - * @param pObj Pointer to component object - * @param pOVPVBusFlag Pointer on OVP VBUS Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OVP_VBUS_RESET OVP VBUS flag not set - * @arg TCPP0203_FLAG_OVP_VBUS_SET OVP VBUS flag set - * @retval Component status - */ -int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOVPVBusFlag = (tmp & TCPP0203_FLAG_OVP_VBUS_MSK); - - return ret; -} - -/** - * @brief Get OVP CC Flag value - * @param pObj Pointer to component object - * @param pOVPCCFlag Pointer on OVP CC Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OVP_CC_RESET OVP CC flag not set - * @arg TCPP0203_FLAG_OVP_CC_SET OVP CC flag set - * @retval Component status - */ -int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOVPCCFlag = (tmp & TCPP0203_FLAG_OVP_CC_MSK); - - return ret; -} - -/** - * @brief Get Over Temperature Flag value - * @param pObj Pointer to component object - * @param pOTPFlag Pointer on Over Temperature Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OTP_RESET Over Temperature flag not set - * @arg TCPP0203_FLAG_OTP_SET Over Temperature flag set - * @retval Component status - */ -int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOTPFlag = (tmp & TCPP0203_FLAG_OTP_MSK); - - return ret; -} - -/** - * @brief Get VBUS OK Flag value - * @param pObj Pointer to component object - * @param pVBusOkFlag Pointer on VBUS OK Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_VBUS_OK_RESET VBUS OK flag not set - * @arg TCPP0203_FLAG_VBUS_OK_SET VBUS OK flag set - * @retval Component status - */ -int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pVBusOkFlag = (tmp & TCPP0203_FLAG_VBUS_OK_MSK); - - return ret; -} - -/** - * @brief Get TCPP0203 Device Type value - * @param pObj Pointer to component object - * @param pTCPPType Pointer on TCPP0203 Device Type value - * This output parameter can be one of the following values: - * @arg TCPP0203_DEVICE_TYPE_02 TCPP02 Type - * @arg TCPP0203_DEVICE_TYPE_03 TCPP03 Type - * @retval Component status - */ -int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pTCPPType = (tmp & TCPP0203_DEVICE_TYPE_MSK); - - return ret; -} - -/** - * @brief Get VConn Power value - * @param pObj Pointer to component object - * @param pVCONNPower Pointer on VConn Power value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_VCONN_PWR_1W OCP VConn flag not set - * @arg TCPP0203_FLAG_VCONN_PWR_0_1W OCP VConn flag set - * @retval Component status - */ -int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pVCONNPower = (tmp & TCPP0203_FLAG_VCONN_PWR_MSK); - - return ret; -} - -/** - * @brief Set complete Ctrl register value (Reg 0) - * @param pObj Pointer to component object - * @param pCtrlRegister Pointer on Ctrl register value - * @retval Component status - */ -int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister) -{ - int32_t ret; - - /* Update value in writing register (reg0) */ - ret = tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, pCtrlRegister, 1); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = *pCtrlRegister; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return ret; -} - -/** - * @brief Get complete Ack register value - * @param pObj Pointer to component object - * @param pAckRegister Pointer on Ack register value - * @retval Component status - */ -int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister) -{ - int32_t ret; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, pAckRegister, 1); - - return ret; -} - -/** - * @brief Get complete Flag register value - * @param pObj Pointer to component object - * @param pFlagRegister Pointer on Flag register value - * @retval Component status - */ -int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister) -{ - int32_t ret; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, pFlagRegister, 1); - - return ret; -} - -/******************** Static functions ****************************************/ -/** - * @brief Wrap TCPP0203 read function to Bus IO function - * @param handle Component object handle - * @param Reg Target register address to read - * @param pData Buffer where Target register value should be stored - * @param Length buffer size to be read - * @retval error status - */ -static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) -{ - const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; - - return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length); -} - -/** - * @brief Wrap TCPP0203 write function to Bus IO function - * @param handle Component object handle - * @param Reg Target register address to write - * @param pData Target register value to be written - * @param Length Buffer size to be written - * @retval error status - */ -static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) -{ - const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = *pData; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length); -} - -/** - * @brief TCPP0203 register update function to Bus IO function - * @param handle Component object handle - * @param Reg Target register address to write - * @param pData Target register value to be written - * @param Length Buffer size to be written - * @retval error status - */ -static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask) -{ - int32_t ret; - uint8_t tmp; - - /* Read current content of ACK register (reflects content of bits set to 1 in Writing register Reg0) */ - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - - /* Update only the area dedicated to Mask */ - tmp &= ~(Mask); - tmp |= (Value & Mask); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = tmp; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - /* Update value in writing register (reg0) */ - ret += tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - ret += TCPP0203_CheckReg0Reg1(pObj, Reg0_Expected_Value); -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return ret; -} - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) -/** - * @brief TCPP0203 register control function between Reg0 and Reg1 value - * @param handle Component object handle - * @param Reg0ExpectedValue Value expected in Reg0 (built after all calls to write functions) - * @retval error status - */ -static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue) -{ - int32_t ret; - - /* Read current content of ACK register (expected to reflect content of bits set to 1 in Writing register Reg0) */ - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &Reg1_LastRead_Value, 1); - -#ifdef _TRACE - char str[12]; - sprintf(str, "Exp0_0x%02x", Reg0ExpectedValue); - USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); - sprintf(str, "Reg1_0x%02x", Reg1_LastRead_Value); - USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); -#endif /* _TRACE */ - - /* Control if Reg1 value is same as Reg0 expected one */ - if (Reg1_LastRead_Value != Reg0ExpectedValue) - { - while (1); - } - - return ret; -} -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h deleted file mode 100644 index 271b534fc..000000000 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h +++ /dev/null @@ -1,353 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the - * tcpp0203.c driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef TCPP0203_H -#define TCPP0203_H - -/* Includes ------------------------------------------------------------------*/ -#include "tcpp0203_reg.h" -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Component - * @{ - */ - -/** @addtogroup TCPP0203 - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup TCPP0203_Exported_Types TCPP0203 Exported Types - * @{ - */ -typedef int32_t (*TCPP0203_Init_Func)(void); -typedef int32_t (*TCPP0203_DeInit_Func)(void); -typedef int32_t (*TCPP0203_GetTick_Func)(void); -typedef int32_t (*TCPP0203_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); -typedef int32_t (*TCPP0203_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); - -typedef struct -{ - TCPP0203_Init_Func Init; - TCPP0203_DeInit_Func DeInit; - uint16_t Address; - TCPP0203_WriteReg_Func WriteReg; - TCPP0203_ReadReg_Func ReadReg; - TCPP0203_GetTick_Func GetTick; -} TCPP0203_IO_t; - - -typedef struct -{ - TCPP0203_IO_t IO; - TCPP0203_ctx_t Ctx; - uint8_t IsInitialized; -} TCPP0203_Object_t; - -typedef struct -{ - int32_t (*Init)(TCPP0203_Object_t *); - int32_t (*DeInit)(TCPP0203_Object_t *); - int32_t (*Reset)(TCPP0203_Object_t *); - int32_t (*SetVConnSwitch)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetGateDriverProvider)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetGateDriverConsumer)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetPowerMode)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetVBusDischarge)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetVConnDischarge)(TCPP0203_Object_t *, uint8_t); - int32_t (*GetVConnSwitchAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetGateDriverProviderAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetGateDriverConsumerAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetPowerModeAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetVBusDischargeAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetVConnDischargeAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOCPVConnFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOCPVBusFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOVPVBusFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOVPCCFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOTPFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetVBusOkFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadTCPPType)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadVCONNPower)(TCPP0203_Object_t *, uint8_t *); - int32_t (*WriteCtrlRegister)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadAckRegister)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadFlagRegister)(TCPP0203_Object_t *, uint8_t *); -} TCPP0203_Drv_t; - -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants - * @{ - */ -/** - * @brief TCPP0203 Driver Response codes - */ -#define TCPP0203_OK (0) -#define TCPP0203_ERROR (-1) - -/** - * @brief TCPP0203 possible I2C Addresses - */ -#define TCPP0203_I2C_ADDRESS_X68 (0x68U) -#define TCPP0203_I2C_ADDRESS_X6A (0x6AU) - -/** - * @brief TCPP0203 Reg0 Reset Value - */ -#define TCPP0203_REG0_RST_VALUE TCPP0203_GD_CONSUMER_SWITCH_CLOSED - -/** - * @brief TCPP0203 VCONN Switch - */ -#define TCPP0203_VCONN_SWITCH_POS (0U) -#define TCPP0203_VCONN_SWITCH_MSK (0x03U << TCPP0203_VCONN_SWITCH_POS) -#define TCPP0203_VCONN_SWITCH_OPEN (0x00U) -#define TCPP0203_VCONN_SWITCH_CC1 (0x01U << TCPP0203_VCONN_SWITCH_POS) -#define TCPP0203_VCONN_SWITCH_CC2 (0x02U << TCPP0203_VCONN_SWITCH_POS) - -/** - * @brief TCPP0203 Gate Driver Provider values - */ -#define TCPP0203_GD_PROVIDER_SWITCH_POS (2U) -#define TCPP0203_GD_PROVIDER_SWITCH_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_POS) -#define TCPP0203_GD_PROVIDER_SWITCH_OPEN (0x00U) -#define TCPP0203_GD_PROVIDER_SWITCH_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_MSK) - -/** - * @brief TCPP0203 Gate Driver Consumer values - */ -#define TCPP0203_GD_CONSUMER_SWITCH_POS (3U) -#define TCPP0203_GD_CONSUMER_SWITCH_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_POS) -#define TCPP0203_GD_CONSUMER_SWITCH_CLOSED (0x00U) -#define TCPP0203_GD_CONSUMER_SWITCH_OPEN (TCPP0203_GD_CONSUMER_SWITCH_MSK) - -/** - * @brief TCPP0203 Power Mode values - */ -#define TCPP0203_POWER_MODE_POS (4U) -#define TCPP0203_POWER_MODE_MSK (0x03U << TCPP0203_POWER_MODE_POS) -#define TCPP0203_POWER_MODE_HIBERNATE (0x00U) -#define TCPP0203_POWER_MODE_LOWPOWER (0x02U << TCPP0203_POWER_MODE_POS) -#define TCPP0203_POWER_MODE_NORMAL (0x01U << TCPP0203_POWER_MODE_POS) - -/** - * @brief TCPP0203 VBUS Discharge management - */ -#define TCPP0203_VBUS_DISCHARGE_POS (6U) -#define TCPP0203_VBUS_DISCHARGE_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_POS) -#define TCPP0203_VBUS_DISCHARGE_OFF (0x00U) -#define TCPP0203_VBUS_DISCHARGE_ON (TCPP0203_VBUS_DISCHARGE_MSK) - -/** - * @brief TCPP0203 VConn Discharge management - */ -#define TCPP0203_VCONN_DISCHARGE_POS (7U) -#define TCPP0203_VCONN_DISCHARGE_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_POS) -#define TCPP0203_VCONN_DISCHARGE_OFF (0x00U) -#define TCPP0203_VCONN_DISCHARGE_ON (TCPP0203_VCONN_DISCHARGE_MSK) - -/** - * @brief TCPP0203 VCONN Switch Acknowledge - */ -#define TCPP0203_VCONN_SWITCH_ACK_POS (0U) -#define TCPP0203_VCONN_SWITCH_ACK_MSK (0x03U << TCPP0203_VCONN_SWITCH_ACK_POS) -#define TCPP0203_VCONN_SWITCH_ACK_OPEN (0x00U) -#define TCPP0203_VCONN_SWITCH_ACK_CC1 (0x02U << TCPP0203_VCONN_SWITCH_ACK_POS) -#define TCPP0203_VCONN_SWITCH_ACK_CC2 (0x01U << TCPP0203_VCONN_SWITCH_ACK_POS) - -/** - * @brief TCPP0203 Gate Driver Provider Acknowledge - */ -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_POS (2U) -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_ACK_POS) -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN (0x00U) -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK) - -/** - * @brief TCPP0203 Gate Driver Consumer Acknowledge - */ -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_POS (3U) -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_ACK_POS) -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED (0x00U) -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN (TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK) - -/** - * @brief TCPP0203 Power Mode Acknowledge - */ -#define TCPP0203_POWER_MODE_ACK_POS (4U) -#define TCPP0203_POWER_MODE_ACK_MSK (0x03U << TCPP0203_POWER_MODE_ACK_POS) -#define TCPP0203_POWER_MODE_ACK_HIBERNATE (0x00U) -#define TCPP0203_POWER_MODE_ACK_LOWPOWER (0x01U << TCPP0203_POWER_MODE_ACK_POS) -#define TCPP0203_POWER_MODE_ACK_NORMAL (0x02U << TCPP0203_POWER_MODE_ACK_POS) - -/** - * @brief TCPP0203 VBUS Discharge Acknowledge - */ -#define TCPP0203_VBUS_DISCHARGE_ACK_POS (6U) -#define TCPP0203_VBUS_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_ACK_POS) -#define TCPP0203_VBUS_DISCHARGE_ACK_OFF (0x00U) -#define TCPP0203_VBUS_DISCHARGE_ACK_ON (TCPP0203_VBUS_DISCHARGE_ACK_MSK) - -/** - * @brief TCPP0203 VConn Discharge Acknowledge - */ -#define TCPP0203_VCONN_DISCHARGE_ACK_POS (7U) -#define TCPP0203_VCONN_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_ACK_POS) -#define TCPP0203_VCONN_DISCHARGE_ACK_OFF (0x00U) -#define TCPP0203_VCONN_DISCHARGE_ACK_ON (TCPP0203_VCONN_DISCHARGE_ACK_MSK) - -/** - * @brief TCPP0203 OCP Vconn Flag management - */ -#define TCPP0203_FLAG_OCP_VCONN_POS (0U) -#define TCPP0203_FLAG_OCP_VCONN_MSK (0x01U << TCPP0203_FLAG_OCP_VCONN_POS) -#define TCPP0203_FLAG_OCP_VCONN_SET (TCPP0203_FLAG_OCP_VCONN_MSK) -#define TCPP0203_FLAG_OCP_VCONN_RESET (0x00U) - -/** - * @brief TCPP0203 OCP VBUS Flag management - */ -#define TCPP0203_FLAG_OCP_VBUS_POS (1U) -#define TCPP0203_FLAG_OCP_VBUS_MSK (0x01U << TCPP0203_FLAG_OCP_VBUS_POS) -#define TCPP0203_FLAG_OCP_VBUS_SET (TCPP0203_FLAG_OCP_VBUS_MSK) -#define TCPP0203_FLAG_OCP_VBUS_RESET (0x00U) - -/** - * @brief TCPP0203 OVP VBUS Flag management - */ -#define TCPP0203_FLAG_OVP_VBUS_POS (2U) -#define TCPP0203_FLAG_OVP_VBUS_MSK (0x01U << TCPP0203_FLAG_OVP_VBUS_POS) -#define TCPP0203_FLAG_OVP_VBUS_SET (TCPP0203_FLAG_OVP_VBUS_MSK) -#define TCPP0203_FLAG_OVP_VBUS_RESET (0x00U) - -/** - * @brief TCPP0203 OVP CC Flag management - */ -#define TCPP0203_FLAG_OVP_CC_POS (3U) -#define TCPP0203_FLAG_OVP_CC_MSK (0x01U << TCPP0203_FLAG_OVP_CC_POS) -#define TCPP0203_FLAG_OVP_CC_SET (TCPP0203_FLAG_OVP_CC_MSK) -#define TCPP0203_FLAG_OVP_CC_RESET (0x00U) - -/** - * @brief TCPP0203 OTP Flag management - */ -#define TCPP0203_FLAG_OTP_POS (4U) -#define TCPP0203_FLAG_OTP_MSK (0x01U << TCPP0203_FLAG_OTP_POS) -#define TCPP0203_FLAG_OTP_SET (TCPP0203_FLAG_OTP_MSK) -#define TCPP0203_FLAG_OTP_RESET (0x00U) - -/** - * @brief TCPP0203 VBUS OK Flag management - */ -#define TCPP0203_FLAG_VBUS_OK_POS (5U) -#define TCPP0203_FLAG_VBUS_OK_MSK (0x01U << TCPP0203_FLAG_VBUS_OK_POS) -#define TCPP0203_FLAG_VBUS_OK_SET (TCPP0203_FLAG_VBUS_OK_MSK) -#define TCPP0203_FLAG_VBUS_OK_RESET (0x00U) - -/** - * @brief TCPP0203 VConn Power - */ -#define TCPP0203_FLAG_VCONN_PWR_POS (6U) -#define TCPP0203_FLAG_VCONN_PWR_MSK (0x01U << TCPP0203_FLAG_VCONN_PWR_POS) -#define TCPP0203_FLAG_VCONN_PWR_1W (TCPP0203_FLAG_VCONN_PWR_MSK) -#define TCPP0203_FLAG_VCONN_PWR_0_1W (0x00U) - -/** - * @brief TCPP0203 Device Type - */ -#define TCPP0203_DEVICE_TYPE_POS (7U) -#define TCPP0203_DEVICE_TYPE_MSK (0x01U << TCPP0203_DEVICE_TYPE_POS) -#define TCPP0203_DEVICE_TYPE_02 (TCPP0203_DEVICE_TYPE_MSK) -#define TCPP0203_DEVICE_TYPE_03 (0x00U) - -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Macros TCPP0203 Exported Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions - * @{ - */ - -/*------------------------------------------------------------------------------ - TCPP02/03 Type-C port protection functions -------------------------------------------------------------------------------*/ -/* High Layer codec functions */ -int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO); -int32_t TCPP0203_Init(TCPP0203_Object_t *pObj); -int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj); -int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj); -int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch); -int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider); -int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer); -int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode); -int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge); -int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge); -int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck); -int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck); -int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck); -int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck); -int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck); -int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck); -int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag); -int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag); -int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag); -int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag); -int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag); -int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag); -int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType); -int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower); -int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister); -int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister); -int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister); - -/** - * @} - */ - -/* TCPP02/03 Type-C port protection driver structure */ -extern TCPP0203_Drv_t TCPP0203_Driver; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TCPP0203_H */ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c deleted file mode 100644 index 8025fa85e..000000000 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c +++ /dev/null @@ -1,73 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203_reg.c - * @author MCD Application Team - * @brief This file provides unitary register function to control the TCPP02-03 - * Type-C port protection driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tcpp0203_reg.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup TCPP0203 - * @brief This file provides a set of functions needed to drive the - * TCPP02/03 Type-C port protection codec. - * @{ - */ - -/************** Generic Function *******************/ -/******************************************************************************* - * Function Name : tcpp0203_read_reg - * Description : Generic Reading function. It must be fulfilled with either - * I2C or SPI reading functions - * Input : Register Address, length of buffer - * Output : data Read - *******************************************************************************/ -int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) -{ - return ctx->ReadReg(ctx->handle, reg, data, length); -} - -/******************************************************************************* - * Function Name : tcpp0203_write_reg - * Description : Generic Writing function. It must be fulfilled with either - * I2C or SPI writing function - * Input : Register Address, data to be written, length of buffer - * Output : None - *******************************************************************************/ -int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) -{ - return ctx->WriteReg(ctx->handle, reg, data, length); -} - -/******************************************************************************/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h deleted file mode 100644 index 92420e1fe..000000000 --- a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203_reg.h - * @author MCD Application Team - * @brief Header of tcpp0203_reg.c - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef TCPP0203_REG_H -#define TCPP0203_REG_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Component - * @{ - */ - -/** @addtogroup TCPP0203 - * @{ - */ - - -/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants - * @{ - */ -/******************************************************************************/ -/****************************** REGISTER MAPPING ******************************/ -/******************************************************************************/ -#define TCPP0203_WRITE_REG 0x00U -#define TCPP0203_PROG_CTRL TCPP0203_WRITE_REG -#define TCPP0203_READ_REG1 0x01U -#define TCPP0203_ACK_REG TCPP0203_READ_REG1 -#define TCPP0203_READ_REG2 0x02U -#define TCPP0203_FLAG_REG TCPP0203_READ_REG2 - -/** - * @} - */ - -/************** Generic Function *******************/ - -typedef int32_t (*TCPP0203_Write_Func)(const void *, uint8_t, uint8_t *, uint8_t); -typedef int32_t (*TCPP0203_Read_Func)(const void *, uint8_t, uint8_t *, uint8_t); - -typedef struct -{ - TCPP0203_Write_Func WriteReg; - TCPP0203_Read_Func ReadReg; - void *handle; -} TCPP0203_ctx_t; - -/******************************************************************************* - * Register : Generic - All - * Address : Generic - All - * Bit Group Name: None - * Permission : W - *******************************************************************************/ -int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); -int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); - -#ifdef __cplusplus -} -#endif - -#endif /* TCPP0203_REG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake index 61c3ebaea..e5e98f914 100644 --- a/hw/bsp/stm32h7rs/family.cmake +++ b/hw/bsp/stm32h7rs/family.cmake @@ -5,6 +5,7 @@ set(ST_PREFIX stm32${ST_FAMILY}xx) set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # include board specific @@ -86,6 +87,8 @@ function(add_board_target BOARD_TARGET) BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} BOARD_TUH_RHPORT=${RHPORT_HOST} BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + SEGGER_RTT_SECTION="noncacheable_buffer" + BUFFER_SIZE_UP=0x3000 ) update_board(${BOARD_TARGET}) diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk index d679b72f1..9970059f8 100644 --- a/hw/bsp/stm32h7rs/family.mk +++ b/hw/bsp/stm32h7rs/family.mk @@ -2,6 +2,7 @@ ST_FAMILY = h7rs ST_PREFIX = stm32${ST_FAMILY}xx ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver +ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203 UF2_FAMILY_ID = 0x6db66083 @@ -42,6 +43,8 @@ CFLAGS += \ -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ + -DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \ + -DBUFFER_SIZE_UP=0x3000 \ # GCC Flags CFLAGS_GCC += \ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake index 789eb9a2e..e88efefb9 100644 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake @@ -7,13 +7,11 @@ function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32N657xx ) - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203_reg.c + ${ST_TCPP0203}/tcpp0203.c + ${ST_TCPP0203}/tcpp0203_reg.c ) target_include_directories(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203 + ${ST_TCPP0203} ) endfunction() diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk index bfbe5b23c..05717699c 100644 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk @@ -10,8 +10,8 @@ flash: flash-stlink PORT = 1 SRC_C += \ - $(BOARD_PATH)/tcpp0203/tcpp0203.c \ - $(BOARD_PATH)/tcpp0203/tcpp0203_reg.c \ + $(ST_TCPP0203)/tcpp0203.c \ + $(ST_TCPP0203)/tcpp0203_reg.c \ INC += \ - $(TOP)/$(BOARD_PATH)/tcpp0203 \ + $(TOP)/$(ST_TCPP0203) \ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt deleted file mode 100644 index 1cbbc544a..000000000 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt +++ /dev/null @@ -1,6 +0,0 @@ -This software component is provided to you as part of a software package and -applicable license terms are in the Package_license file. If you received this -software component outside of a package or without applicable license terms, -the terms of the BSD-3-Clause license shall apply. -You may obtain a copy of the BSD-3-Clause at: -https://opensource.org/licenses/BSD-3-Clause diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html deleted file mode 100644 index 6bbba86a4..000000000 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html +++ /dev/null @@ -1,205 +0,0 @@ - - - - - - - Release Notes for TCPP0203 Component Driver - - - - - - -
-
-
-

Release Notes for TCPP0203 Component Driver

-

Copyright © 2020 STMicroelectronics
-

- -
-

Purpose

-

This driver provides a set of functions needed to drive TCPP0203 Type-C Port Protection component

-
-
-

Update History

-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - -
Headline
MISRA Rule-81.13 correction on TCPP0203 component driver files
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
MISRA corrections on TCPP0203 component driver files
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.8.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
License updates
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.6.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
CodeSpell correction on TCPP0203 component driver files
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.5.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-

Maintenance release

-

Contents

- - - - - - - - - - - - -
Fixed bugs list
Headline
MCUAstyle correction on TCPP0203 component driver files
-

Known Limitations

-

Outstanding bugs list : None

-

Requirements not met or planned in a forthcoming release : None

-

Development Toolchains and Compilers

-
    -
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • -
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • -
  • STM32CubeIDE toolchain V1.5.0
    • -
-

Backward compatibility

-

No compatibility break with previous version

-

Dependencies

-
-
-
- -
-

Main Changes

-
    -
  • First official release of TCPP0203 Type-C port Protection Component drivers
    • -
-
-
-
-
-
-

For complete documentation on STM32,visit: [www.st.com/stm32]

-This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. -
- - diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png deleted file mode 100644 index 06713eec4..000000000 Binary files a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png and /dev/null differ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css deleted file mode 100644 index dd19969d1..000000000 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css +++ /dev/null @@ -1,1703 +0,0 @@ -@charset "UTF-8"; -/* - Flavor name: Custom (mini-custom) - Generated online - https://minicss.org/flavors - mini.css version: v3.0.1 -*/ -/* - Browsers resets and base typography. -*/ -/* Core module CSS variable definitions */ -:root { - --fore-color: #03234b; - --secondary-fore-color: #03234b; - --back-color: #ffffff; - --secondary-back-color: #ffffff; - --blockquote-color: #e6007e; - --pre-color: #e6007e; - --border-color: #3cb4e6; - --secondary-border-color: #3cb4e6; - --heading-ratio: 1.2; - --universal-margin: 0.5rem; - --universal-padding: 0.25rem; - --universal-border-radius: 0.075rem; - --background-margin: 1.5%; - --a-link-color: #3cb4e6; - --a-visited-color: #8c0078; } - -html { - font-size: 13.5px; } - -a, b, del, em, i, ins, q, span, strong, u { - font-size: 1em; } - -html, * { - font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; - line-height: 1.25; - -webkit-text-size-adjust: 100%; } - -* { - font-size: 1rem; } - -body { - margin: 0; - color: var(--fore-color); - @background: var(--back-color); - background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; - background-size: var(--background-margin); - } - -details { - display: block; } - -summary { - display: list-item; } - -abbr[title] { - border-bottom: none; - text-decoration: underline dotted; } - -input { - overflow: visible; } - -img { - max-width: 100%; - height: auto; } - -h1, h2, h3, h4, h5, h6 { - line-height: 1.25; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 400; } - h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { - color: var(--secondary-fore-color); - display: block; - margin-top: -0.25rem; } - -h1 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } - -h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); - border-style: none none solid none ; - border-width: thin; - border-color: var(--border-color); } -h3 { - font-size: calc(1rem * var(--heading-ratio) ); } - -h4 { - font-size: calc(1rem * var(--heading-ratio)); } - -h5 { - font-size: 1rem; } - -h6 { - font-size: calc(1rem / var(--heading-ratio)); } - -p { - margin: var(--universal-margin); } - -ol, ul { - margin: var(--universal-margin); - padding-left: calc(3 * var(--universal-margin)); } - -b, strong { - font-weight: 700; } - -hr { - box-sizing: content-box; - border: 0; - line-height: 1.25em; - margin: var(--universal-margin); - height: 0.0714285714rem; - background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } - -blockquote { - display: block; - position: relative; - font-style: italic; - color: var(--secondary-fore-color); - margin: var(--universal-margin); - padding: calc(3 * var(--universal-padding)); - border: 0.0714285714rem solid var(--secondary-border-color); - border-left: 0.3rem solid var(--blockquote-color); - border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } - blockquote:before { - position: absolute; - top: calc(0rem - var(--universal-padding)); - left: 0; - font-family: sans-serif; - font-size: 2rem; - font-weight: 800; - content: "\201c"; - color: var(--blockquote-color); } - blockquote[cite]:after { - font-style: normal; - font-size: 0.75em; - font-weight: 700; - content: "\a— " attr(cite); - white-space: pre; } - -code, kbd, pre, samp { - font-family: Menlo, Consolas, monospace; - font-size: 0.85em; } - -code { - background: var(--secondary-back-color); - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } - -kbd { - background: var(--fore-color); - color: var(--back-color); - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } - -pre { - overflow: auto; - background: var(--secondary-back-color); - padding: calc(1.5 * var(--universal-padding)); - margin: var(--universal-margin); - border: 0.0714285714rem solid var(--secondary-border-color); - border-left: 0.2857142857rem solid var(--pre-color); - border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } - -sup, sub, code, kbd { - line-height: 0; - position: relative; - vertical-align: baseline; } - -small, sup, sub, figcaption { - font-size: 0.75em; } - -sup { - top: -0.5em; } - -sub { - bottom: -0.25em; } - -figure { - margin: var(--universal-margin); } - -figcaption { - color: var(--secondary-fore-color); } - -a { - text-decoration: none; } - a:link { - color: var(--a-link-color); } - a:visited { - color: var(--a-visited-color); } - a:hover, a:focus { - text-decoration: underline; } - -/* - Definitions for the grid system, cards and containers. -*/ -.container { - margin: 0 auto; - padding: 0 calc(1.5 * var(--universal-padding)); } - -.row { - box-sizing: border-box; - display: flex; - flex: 0 1 auto; - flex-flow: row wrap; - margin: 0 0 0 var(--background-margin); } - -.col-sm, -[class^='col-sm-'], -[class^='col-sm-offset-'], -.row[class*='cols-sm-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - -.col-sm, -.row.cols-sm > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - -.col-sm-1, -.row.cols-sm-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - -.col-sm-offset-0 { - margin-left: 0; } - -.col-sm-2, -.row.cols-sm-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - -.col-sm-offset-1 { - margin-left: 8.3333333333%; } - -.col-sm-3, -.row.cols-sm-3 > * { - max-width: 25%; - flex-basis: 25%; } - -.col-sm-offset-2 { - margin-left: 16.6666666667%; } - -.col-sm-4, -.row.cols-sm-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - -.col-sm-offset-3 { - margin-left: 25%; } - -.col-sm-5, -.row.cols-sm-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - -.col-sm-offset-4 { - margin-left: 33.3333333333%; } - -.col-sm-6, -.row.cols-sm-6 > * { - max-width: 50%; - flex-basis: 50%; } - -.col-sm-offset-5 { - margin-left: 41.6666666667%; } - -.col-sm-7, -.row.cols-sm-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - -.col-sm-offset-6 { - margin-left: 50%; } - -.col-sm-8, -.row.cols-sm-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - -.col-sm-offset-7 { - margin-left: 58.3333333333%; } - -.col-sm-9, -.row.cols-sm-9 > * { - max-width: 75%; - flex-basis: 75%; } - -.col-sm-offset-8 { - margin-left: 66.6666666667%; } - -.col-sm-10, -.row.cols-sm-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - -.col-sm-offset-9 { - margin-left: 75%; } - -.col-sm-11, -.row.cols-sm-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - -.col-sm-offset-10 { - margin-left: 83.3333333333%; } - -.col-sm-12, -.row.cols-sm-12 > * { - max-width: 100%; - flex-basis: 100%; } - -.col-sm-offset-11 { - margin-left: 91.6666666667%; } - -.col-sm-normal { - order: initial; } - -.col-sm-first { - order: -999; } - -.col-sm-last { - order: 999; } - -@media screen and (min-width: 500px) { - .col-md, - [class^='col-md-'], - [class^='col-md-offset-'], - .row[class*='cols-md-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - - .col-md, - .row.cols-md > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - - .col-md-1, - .row.cols-md-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - - .col-md-offset-0 { - margin-left: 0; } - - .col-md-2, - .row.cols-md-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - - .col-md-offset-1 { - margin-left: 8.3333333333%; } - - .col-md-3, - .row.cols-md-3 > * { - max-width: 25%; - flex-basis: 25%; } - - .col-md-offset-2 { - margin-left: 16.6666666667%; } - - .col-md-4, - .row.cols-md-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - - .col-md-offset-3 { - margin-left: 25%; } - - .col-md-5, - .row.cols-md-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - - .col-md-offset-4 { - margin-left: 33.3333333333%; } - - .col-md-6, - .row.cols-md-6 > * { - max-width: 50%; - flex-basis: 50%; } - - .col-md-offset-5 { - margin-left: 41.6666666667%; } - - .col-md-7, - .row.cols-md-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - - .col-md-offset-6 { - margin-left: 50%; } - - .col-md-8, - .row.cols-md-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - - .col-md-offset-7 { - margin-left: 58.3333333333%; } - - .col-md-9, - .row.cols-md-9 > * { - max-width: 75%; - flex-basis: 75%; } - - .col-md-offset-8 { - margin-left: 66.6666666667%; } - - .col-md-10, - .row.cols-md-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - - .col-md-offset-9 { - margin-left: 75%; } - - .col-md-11, - .row.cols-md-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - - .col-md-offset-10 { - margin-left: 83.3333333333%; } - - .col-md-12, - .row.cols-md-12 > * { - max-width: 100%; - flex-basis: 100%; } - - .col-md-offset-11 { - margin-left: 91.6666666667%; } - - .col-md-normal { - order: initial; } - - .col-md-first { - order: -999; } - - .col-md-last { - order: 999; } } -@media screen and (min-width: 1280px) { - .col-lg, - [class^='col-lg-'], - [class^='col-lg-offset-'], - .row[class*='cols-lg-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - - .col-lg, - .row.cols-lg > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - - .col-lg-1, - .row.cols-lg-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - - .col-lg-offset-0 { - margin-left: 0; } - - .col-lg-2, - .row.cols-lg-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - - .col-lg-offset-1 { - margin-left: 8.3333333333%; } - - .col-lg-3, - .row.cols-lg-3 > * { - max-width: 25%; - flex-basis: 25%; } - - .col-lg-offset-2 { - margin-left: 16.6666666667%; } - - .col-lg-4, - .row.cols-lg-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - - .col-lg-offset-3 { - margin-left: 25%; } - - .col-lg-5, - .row.cols-lg-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - - .col-lg-offset-4 { - margin-left: 33.3333333333%; } - - .col-lg-6, - .row.cols-lg-6 > * { - max-width: 50%; - flex-basis: 50%; } - - .col-lg-offset-5 { - margin-left: 41.6666666667%; } - - .col-lg-7, - .row.cols-lg-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - - .col-lg-offset-6 { - margin-left: 50%; } - - .col-lg-8, - .row.cols-lg-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - - .col-lg-offset-7 { - margin-left: 58.3333333333%; } - - .col-lg-9, - .row.cols-lg-9 > * { - max-width: 75%; - flex-basis: 75%; } - - .col-lg-offset-8 { - margin-left: 66.6666666667%; } - - .col-lg-10, - .row.cols-lg-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - - .col-lg-offset-9 { - margin-left: 75%; } - - .col-lg-11, - .row.cols-lg-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - - .col-lg-offset-10 { - margin-left: 83.3333333333%; } - - .col-lg-12, - .row.cols-lg-12 > * { - max-width: 100%; - flex-basis: 100%; } - - .col-lg-offset-11 { - margin-left: 91.6666666667%; } - - .col-lg-normal { - order: initial; } - - .col-lg-first { - order: -999; } - - .col-lg-last { - order: 999; } } -/* Card component CSS variable definitions */ -:root { - --card-back-color: #3cb4e6; - --card-fore-color: #03234b; - --card-border-color: #03234b; } - -.card { - display: flex; - flex-direction: column; - justify-content: space-between; - align-self: center; - position: relative; - width: 100%; - background: var(--card-back-color); - color: var(--card-fore-color); - border: 0.0714285714rem solid var(--card-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); - overflow: hidden; } - @media screen and (min-width: 320px) { - .card { - max-width: 320px; } } - .card > .sectione { - background: var(--card-back-color); - color: var(--card-fore-color); - box-sizing: border-box; - margin: 0; - border: 0; - border-radius: 0; - border-bottom: 0.0714285714rem solid var(--card-border-color); - padding: var(--universal-padding); - width: 100%; } - .card > .sectione.media { - height: 200px; - padding: 0; - -o-object-fit: cover; - object-fit: cover; } - .card > .sectione:last-child { - border-bottom: 0; } - -/* - Custom elements for card elements. -*/ -@media screen and (min-width: 240px) { - .card.small { - max-width: 240px; } } -@media screen and (min-width: 480px) { - .card.large { - max-width: 480px; } } -.card.fluid { - max-width: 100%; - width: auto; } - -.card.warning { - --card-back-color: #e5b8b7; - --card-fore-color: #3b234b; - --card-border-color: #8c0078; } - -.card.error { - --card-back-color: #464650; - --card-fore-color: #ffffff; - --card-border-color: #8c0078; } - -.card > .sectione.dark { - --card-back-color: #3b234b; - --card-fore-color: #ffffff; } - -.card > .sectione.double-padded { - padding: calc(1.5 * var(--universal-padding)); } - -/* - Definitions for forms and input elements. -*/ -/* Input_control module CSS variable definitions */ -:root { - --form-back-color: #ffe97f; - --form-fore-color: #03234b; - --form-border-color: #3cb4e6; - --input-back-color: #ffffff; - --input-fore-color: #03234b; - --input-border-color: #3cb4e6; - --input-focus-color: #0288d1; - --input-invalid-color: #d32f2f; - --button-back-color: #e2e2e2; - --button-hover-back-color: #dcdcdc; - --button-fore-color: #212121; - --button-border-color: transparent; - --button-hover-border-color: transparent; - --button-group-border-color: rgba(124, 124, 124, 0.54); } - -form { - background: var(--form-back-color); - color: var(--form-fore-color); - border: 0.0714285714rem solid var(--form-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); - padding: calc(2 * var(--universal-padding)) var(--universal-padding); } - -fieldset { - border: 0.0714285714rem solid var(--form-border-color); - border-radius: var(--universal-border-radius); - margin: calc(var(--universal-margin) / 4); - padding: var(--universal-padding); } - -legend { - box-sizing: border-box; - display: table; - max-width: 100%; - white-space: normal; - font-weight: 500; - padding: calc(var(--universal-padding) / 2); } - -label { - padding: calc(var(--universal-padding) / 2) var(--universal-padding); } - -.input-group { - display: inline-block; } - .input-group.fluid { - display: flex; - align-items: center; - justify-content: center; } - .input-group.fluid > input { - max-width: 100%; - flex-grow: 1; - flex-basis: 0px; } - @media screen and (max-width: 499px) { - .input-group.fluid { - align-items: stretch; - flex-direction: column; } } - .input-group.vertical { - display: flex; - align-items: stretch; - flex-direction: column; } - .input-group.vertical > input { - max-width: 100%; - flex-grow: 1; - flex-basis: 0px; } - -[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { - height: auto; } - -[type="search"] { - -webkit-appearance: textfield; - outline-offset: -2px; } - -[type="search"]::-webkit-search-cancel-button, -[type="search"]::-webkit-search-decoration { - -webkit-appearance: none; } - -input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], -[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { - box-sizing: border-box; - background: var(--input-back-color); - color: var(--input-fore-color); - border: 0.0714285714rem solid var(--input-border-color); - border-radius: var(--universal-border-radius); - margin: calc(var(--universal-margin) / 2); - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } - -input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { - border-color: var(--input-focus-color); - box-shadow: none; } -input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { - border-color: var(--input-invalid-color); - box-shadow: none; } -input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { - background: var(--secondary-back-color); } - -select { - max-width: 100%; } - -option { - overflow: hidden; - text-overflow: ellipsis; } - -[type="checkbox"], [type="radio"] { - -webkit-appearance: none; - -moz-appearance: none; - appearance: none; - position: relative; - height: calc(1rem + var(--universal-padding) / 2); - width: calc(1rem + var(--universal-padding) / 2); - vertical-align: text-bottom; - padding: 0; - flex-basis: calc(1rem + var(--universal-padding) / 2) !important; - flex-grow: 0 !important; } - [type="checkbox"]:checked:before, [type="radio"]:checked:before { - position: absolute; } - -[type="checkbox"]:checked:before { - content: '\2713'; - font-family: sans-serif; - font-size: calc(1rem + var(--universal-padding) / 2); - top: calc(0rem - var(--universal-padding)); - left: calc(var(--universal-padding) / 4); } - -[type="radio"] { - border-radius: 100%; } - [type="radio"]:checked:before { - border-radius: 100%; - content: ''; - top: calc(0.0714285714rem + var(--universal-padding) / 2); - left: calc(0.0714285714rem + var(--universal-padding) / 2); - background: var(--input-fore-color); - width: 0.5rem; - height: 0.5rem; } - -:placeholder-shown { - color: var(--input-fore-color); } - -::-ms-placeholder { - color: var(--input-fore-color); - opacity: 0.54; } - -button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { - border-style: none; - padding: 0; } - -button, html [type="button"], [type="reset"], [type="submit"] { - -webkit-appearance: button; } - -button { - overflow: visible; - text-transform: none; } - -button, [type="button"], [type="submit"], [type="reset"], -a.button, label.button, .button, -a[role="button"], label[role="button"], [role="button"] { - display: inline-block; - background: var(--button-back-color); - color: var(--button-fore-color); - border: 0.0714285714rem solid var(--button-border-color); - border-radius: var(--universal-border-radius); - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); - margin: var(--universal-margin); - text-decoration: none; - cursor: pointer; - transition: background 0.3s; } - button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, - a.button:hover, - a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, - a[role="button"]:hover, - a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { - background: var(--button-hover-back-color); - border-color: var(--button-hover-border-color); } - -input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { - cursor: not-allowed; - opacity: 0.75; } - -.button-group { - display: flex; - border: 0.0714285714rem solid var(--button-group-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); } - .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { - margin: 0; - max-width: 100%; - flex: 1 1 auto; - text-align: center; - border: 0; - border-radius: 0; - box-shadow: none; } - .button-group > :not(:first-child) { - border-left: 0.0714285714rem solid var(--button-group-border-color); } - @media screen and (max-width: 499px) { - .button-group { - flex-direction: column; } - .button-group > :not(:first-child) { - border: 0; - border-top: 0.0714285714rem solid var(--button-group-border-color); } } - -/* - Custom elements for forms and input elements. -*/ -button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { - --button-back-color: #1976d2; - --button-fore-color: #f8f8f8; } - button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { - --button-hover-back-color: #1565c0; } - -button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { - --button-back-color: #d32f2f; - --button-fore-color: #f8f8f8; } - button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { - --button-hover-back-color: #c62828; } - -button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { - --button-back-color: #308732; - --button-fore-color: #f8f8f8; } - button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { - --button-hover-back-color: #277529; } - -button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { - --button-back-color: #212121; - --button-fore-color: #f8f8f8; } - button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { - --button-hover-back-color: #111; } - -button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { - padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); - margin: var(--universal-margin); } - -button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { - padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); - margin: var(--universal-margin); } - -/* - Definitions for navigation elements. -*/ -/* Navigation module CSS variable definitions */ -:root { - --header-back-color: #03234b; - --header-hover-back-color: #ffd200; - --header-fore-color: #ffffff; - --header-border-color: #3cb4e6; - --nav-back-color: #ffffff; - --nav-hover-back-color: #ffe97f; - --nav-fore-color: #e6007e; - --nav-border-color: #3cb4e6; - --nav-link-color: #3cb4e6; - --footer-fore-color: #ffffff; - --footer-back-color: #03234b; - --footer-border-color: #3cb4e6; - --footer-link-color: #3cb4e6; - --drawer-back-color: #ffffff; - --drawer-hover-back-color: #ffe97f; - --drawer-border-color: #3cb4e6; - --drawer-close-color: #e6007e; } - -header { - height: 2.75rem; - background: var(--header-back-color); - color: var(--header-fore-color); - border-bottom: 0.0714285714rem solid var(--header-border-color); - padding: calc(var(--universal-padding) / 4) 0; - white-space: nowrap; - overflow-x: auto; - overflow-y: hidden; } - header.row { - box-sizing: content-box; } - header .logo { - color: var(--header-fore-color); - font-size: 1.75rem; - padding: var(--universal-padding) calc(2 * var(--universal-padding)); - text-decoration: none; } - header button, header [type="button"], header .button, header [role="button"] { - box-sizing: border-box; - position: relative; - top: calc(0rem - var(--universal-padding) / 4); - height: calc(3.1875rem + var(--universal-padding) / 2); - background: var(--header-back-color); - line-height: calc(3.1875rem - var(--universal-padding) * 1.5); - text-align: center; - color: var(--header-fore-color); - border: 0; - border-radius: 0; - margin: 0; - text-transform: uppercase; } - header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { - background: var(--header-hover-back-color); } - -nav { - background: var(--nav-back-color); - color: var(--nav-fore-color); - border: 0.0714285714rem solid var(--nav-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); } - nav * { - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } - nav a, nav a:visited { - display: block; - color: var(--nav-link-color); - border-radius: var(--universal-border-radius); - transition: background 0.3s; } - nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { - text-decoration: none; - background: var(--nav-hover-back-color); } - nav .sublink-1 { - position: relative; - margin-left: calc(2 * var(--universal-padding)); } - nav .sublink-1:before { - position: absolute; - left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0714285714rem; - content: ''; - height: 100%; - border: 0.0714285714rem solid var(--nav-border-color); - border-left: 0; } - nav .sublink-2 { - position: relative; - margin-left: calc(4 * var(--universal-padding)); } - nav .sublink-2:before { - position: absolute; - left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0714285714rem; - content: ''; - height: 100%; - border: 0.0714285714rem solid var(--nav-border-color); - border-left: 0; } - -footer { - background: var(--footer-back-color); - color: var(--footer-fore-color); - border-top: 0.0714285714rem solid var(--footer-border-color); - padding: calc(2 * var(--universal-padding)) var(--universal-padding); - font-size: 0.875rem; } - footer a, footer a:visited { - color: var(--footer-link-color); } - -header.sticky { - position: -webkit-sticky; - position: sticky; - z-index: 1101; - top: 0; } - -footer.sticky { - position: -webkit-sticky; - position: sticky; - z-index: 1101; - bottom: 0; } - -.drawer-toggle:before { - display: inline-block; - position: relative; - vertical-align: bottom; - content: '\00a0\2261\00a0'; - font-family: sans-serif; - font-size: 1.5em; } -@media screen and (min-width: 500px) { - .drawer-toggle:not(.persistent) { - display: none; } } - -[type="checkbox"].drawer { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - [type="checkbox"].drawer + * { - display: block; - box-sizing: border-box; - position: fixed; - top: 0; - width: 320px; - height: 100vh; - overflow-y: auto; - background: var(--drawer-back-color); - border: 0.0714285714rem solid var(--drawer-border-color); - border-radius: 0; - margin: 0; - z-index: 1110; - right: -320px; - transition: right 0.3s; } - [type="checkbox"].drawer + * .drawer-close { - position: absolute; - top: var(--universal-margin); - right: var(--universal-margin); - z-index: 1111; - width: 2rem; - height: 2rem; - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - margin: 0; - cursor: pointer; - transition: background 0.3s; } - [type="checkbox"].drawer + * .drawer-close:before { - display: block; - content: '\00D7'; - color: var(--drawer-close-color); - position: relative; - font-family: sans-serif; - font-size: 2rem; - line-height: 1; - text-align: center; } - [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { - background: var(--drawer-hover-back-color); } - @media screen and (max-width: 320px) { - [type="checkbox"].drawer + * { - width: 100%; } } - [type="checkbox"].drawer:checked + * { - right: 0; } - @media screen and (min-width: 500px) { - [type="checkbox"].drawer:not(.persistent) + * { - position: static; - height: 100%; - z-index: 1100; } - [type="checkbox"].drawer:not(.persistent) + * .drawer-close { - display: none; } } - -/* - Definitions for the responsive table component. -*/ -/* Table module CSS variable definitions. */ -:root { - --table-border-color: #03234b; - --table-border-separator-color: #03234b; - --table-head-back-color: #03234b; - --table-head-fore-color: #ffffff; - --table-body-back-color: #ffffff; - --table-body-fore-color: #03234b; - --table-body-alt-back-color: #f4f4f4; } - -table { - border-collapse: separate; - border-spacing: 0; - margin: 0; - display: flex; - flex: 0 1 auto; - flex-flow: row wrap; - padding: var(--universal-padding); - padding-top: 0; } - table caption { - font-size: 1rem; - margin: calc(2 * var(--universal-margin)) 0; - max-width: 100%; - flex: 0 0 100%; } - table thead, table tbody { - display: flex; - flex-flow: row wrap; - border: 0.0714285714rem solid var(--table-border-color); } - table thead { - z-index: 999; - border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } - table tbody { - border-top: 0; - margin-top: calc(0 - var(--universal-margin)); - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - table tr { - display: flex; - padding: 0; } - table th, table td { - padding: calc(0.5 * var(--universal-padding)); - font-size: 0.9rem; } - table th { - text-align: left; - background: var(--table-head-back-color); - color: var(--table-head-fore-color); } - table td { - background: var(--table-body-back-color); - color: var(--table-body-fore-color); - border-top: 0.0714285714rem solid var(--table-border-color); } - -table:not(.horizontal) { - overflow: auto; - max-height: 100%; } - table:not(.horizontal) thead, table:not(.horizontal) tbody { - max-width: 100%; - flex: 0 0 100%; } - table:not(.horizontal) tr { - flex-flow: row wrap; - flex: 0 0 100%; } - table:not(.horizontal) th, table:not(.horizontal) td { - flex: 1 0 0%; - overflow: hidden; - text-overflow: ellipsis; } - table:not(.horizontal) thead { - position: sticky; - top: 0; } - table:not(.horizontal) tbody tr:first-child td { - border-top: 0; } - -table.horizontal { - border: 0; } - table.horizontal thead, table.horizontal tbody { - border: 0; - flex: .2 0 0; - flex-flow: row nowrap; } - table.horizontal tbody { - overflow: auto; - justify-content: space-between; - flex: .8 0 0; - margin-left: 0; - padding-bottom: calc(var(--universal-padding) / 4); } - table.horizontal tr { - flex-direction: column; - flex: 1 0 auto; } - table.horizontal th, table.horizontal td { - width: auto; - border: 0; - border-bottom: 0.0714285714rem solid var(--table-border-color); } - table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { - border-top: 0; } - table.horizontal th { - text-align: right; - border-left: 0.0714285714rem solid var(--table-border-color); - border-right: 0.0714285714rem solid var(--table-border-separator-color); } - table.horizontal thead tr:first-child { - padding-left: 0; } - table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0714285714rem solid var(--table-border-color); } - table.horizontal tbody tr:last-child td { - border-right: 0.0714285714rem solid var(--table-border-color); } - table.horizontal tbody tr:last-child td:first-child { - border-top-right-radius: 0.25rem; } - table.horizontal tbody tr:last-child td:last-child { - border-bottom-right-radius: 0.25rem; } - table.horizontal thead tr:first-child th:first-child { - border-top-left-radius: 0.25rem; } - table.horizontal thead tr:first-child th:last-child { - border-bottom-left-radius: 0.25rem; } - -@media screen and (max-width: 499px) { - table, table.horizontal { - border-collapse: collapse; - border: 0; - width: 100%; - display: table; } - table thead, table th, table.horizontal thead, table.horizontal th { - border: 0; - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - padding: 0; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - table tbody, table.horizontal tbody { - border: 0; - display: table-row-group; } - table tr, table.horizontal tr { - display: block; - border: 0.0714285714rem solid var(--table-border-color); - border-radius: var(--universal-border-radius); - background: #ffffff; - padding: var(--universal-padding); - margin: var(--universal-margin); - margin-bottom: calc(1 * var(--universal-margin)); } - table th, table td, table.horizontal th, table.horizontal td { - width: auto; } - table td, table.horizontal td { - display: block; - border: 0; - text-align: right; } - table td:before, table.horizontal td:before { - content: attr(data-label); - float: left; - font-weight: 600; } - table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0; } - table tbody tr:last-child td, table.horizontal tbody tr:last-child td { - border-right: 0; } } -table tr:nth-of-type(2n) > td { - background: var(--table-body-alt-back-color); } - -@media screen and (max-width: 500px) { - table tr:nth-of-type(2n) { - background: var(--table-body-alt-back-color); } } -:root { - --table-body-hover-back-color: #90caf9; } - -table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { - background: var(--table-body-hover-back-color); } - -@media screen and (max-width: 500px) { - table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { - background: var(--table-body-hover-back-color); } } -/* - Definitions for contextual background elements, toasts and tooltips. -*/ -/* Contextual module CSS variable definitions */ -:root { - --mark-back-color: #3cb4e6; - --mark-fore-color: #ffffff; } - -mark { - background: var(--mark-back-color); - color: var(--mark-fore-color); - font-size: 0.95em; - line-height: 1em; - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) var(--universal-padding); } - mark.inline-block { - display: inline-block; - font-size: 1em; - line-height: 1.4; - padding: calc(var(--universal-padding) / 2) var(--universal-padding); } - -:root { - --toast-back-color: #424242; - --toast-fore-color: #fafafa; } - -.toast { - position: fixed; - bottom: calc(var(--universal-margin) * 3); - left: 50%; - transform: translate(-50%, -50%); - z-index: 1111; - color: var(--toast-fore-color); - background: var(--toast-back-color); - border-radius: calc(var(--universal-border-radius) * 16); - padding: var(--universal-padding) calc(var(--universal-padding) * 3); } - -:root { - --tooltip-back-color: #212121; - --tooltip-fore-color: #fafafa; } - -.tooltip { - position: relative; - display: inline-block; } - .tooltip:before, .tooltip:after { - position: absolute; - opacity: 0; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); - transition: all 0.3s; - z-index: 1010; - left: 50%; } - .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { - bottom: 75%; } - .tooltip.bottom:before, .tooltip.bottom:after { - top: 75%; } - .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { - opacity: 1; - clip: auto; - -webkit-clip-path: inset(0%); - clip-path: inset(0%); } - .tooltip:before { - content: ''; - background: transparent; - border: var(--universal-margin) solid transparent; - left: calc(50% - var(--universal-margin)); } - .tooltip:not(.bottom):before { - border-top-color: #212121; } - .tooltip.bottom:before { - border-bottom-color: #212121; } - .tooltip:after { - content: attr(aria-label); - color: var(--tooltip-fore-color); - background: var(--tooltip-back-color); - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - white-space: nowrap; - transform: translateX(-50%); } - .tooltip:not(.bottom):after { - margin-bottom: calc(2 * var(--universal-margin)); } - .tooltip.bottom:after { - margin-top: calc(2 * var(--universal-margin)); } - -:root { - --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #e6007e; - --modal-close-hover-color: #ffe97f; } - -[type="checkbox"].modal { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - [type="checkbox"].modal + div { - position: fixed; - top: 0; - left: 0; - display: none; - width: 100vw; - height: 100vh; - background: var(--modal-overlay-color); } - [type="checkbox"].modal + div .card { - margin: 0 auto; - max-height: 50vh; - overflow: auto; } - [type="checkbox"].modal + div .card .modal-close { - position: absolute; - top: 0; - right: 0; - width: 1.75rem; - height: 1.75rem; - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - margin: 0; - cursor: pointer; - transition: background 0.3s; } - [type="checkbox"].modal + div .card .modal-close:before { - display: block; - content: '\00D7'; - color: var(--modal-close-color); - position: relative; - font-family: sans-serif; - font-size: 1.75rem; - line-height: 1; - text-align: center; } - [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { - background: var(--modal-close-hover-color); } - [type="checkbox"].modal:checked + div { - display: flex; - flex: 0 1 auto; - z-index: 1200; } - [type="checkbox"].modal:checked + div .card .modal-close { - z-index: 1211; } - -:root { - --collapse-label-back-color: #03234b; - --collapse-label-fore-color: #ffffff; - --collapse-label-hover-back-color: #3cb4e6; - --collapse-selected-label-back-color: #3cb4e6; - --collapse-border-color: var(--collapse-label-back-color); - --collapse-selected-border-color: #ceecf8; - --collapse-content-back-color: #ffffff; - --collapse-selected-label-border-color: #3cb4e6; } - -.collapse { - width: calc(100% - 2 * var(--universal-margin)); - opacity: 1; - display: flex; - flex-direction: column; - margin: var(--universal-margin); - border-radius: var(--universal-border-radius); } - .collapse > [type="radio"], .collapse > [type="checkbox"] { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - .collapse > label { - flex-grow: 1; - display: inline-block; - height: 1.25rem; - cursor: pointer; - transition: background 0.2s; - color: var(--collapse-label-fore-color); - background: var(--collapse-label-back-color); - border: 0.0714285714rem solid var(--collapse-selected-border-color); - padding: calc(1.25 * var(--universal-padding)); } - .collapse > label:hover, .collapse > label:focus { - background: var(--collapse-label-hover-back-color); } - .collapse > label + div { - flex-basis: auto; - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); - transition: max-height 0.3s; - max-height: 1px; } - .collapse > :checked + label { - background: var(--collapse-selected-label-back-color); - border-color: var(--collapse-selected-label-border-color); } - .collapse > :checked + label + div { - box-sizing: border-box; - position: relative; - width: 100%; - height: auto; - overflow: auto; - margin: 0; - background: var(--collapse-content-back-color); - border: 0.0714285714rem solid var(--collapse-selected-border-color); - border-top: 0; - padding: var(--universal-padding); - clip: auto; - -webkit-clip-path: inset(0%); - clip-path: inset(0%); - max-height: 100%; } - .collapse > label:not(:first-of-type) { - border-top: 0; } - .collapse > label:first-of-type { - border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } - .collapse > label:last-of-type:not(:first-of-type) { - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - .collapse > label:last-of-type:first-of-type { - border-radius: var(--universal-border-radius); } - .collapse > :checked:last-of-type:not(:first-of-type) + label { - border-radius: 0; } - .collapse > :checked:last-of-type + label + div { - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - -/* - Custom elements for contextual background elements, toasts and tooltips. -*/ -mark.tertiary { - --mark-back-color: #3cb4e6; } - -mark.tag { - padding: calc(var(--universal-padding)/2) var(--universal-padding); - border-radius: 1em; } - -/* - Definitions for progress elements and spinners. -*/ -/* Progress module CSS variable definitions */ -:root { - --progress-back-color: #3cb4e6; - --progress-fore-color: #555; } - -progress { - display: block; - vertical-align: baseline; - -webkit-appearance: none; - -moz-appearance: none; - appearance: none; - height: 0.75rem; - width: calc(100% - 2 * var(--universal-margin)); - margin: var(--universal-margin); - border: 0; - border-radius: calc(2 * var(--universal-border-radius)); - background: var(--progress-back-color); - color: var(--progress-fore-color); } - progress::-webkit-progress-value { - background: var(--progress-fore-color); - border-top-left-radius: calc(2 * var(--universal-border-radius)); - border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } - progress::-webkit-progress-bar { - background: var(--progress-back-color); } - progress::-moz-progress-bar { - background: var(--progress-fore-color); - border-top-left-radius: calc(2 * var(--universal-border-radius)); - border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } - progress[value="1000"]::-webkit-progress-value { - border-radius: calc(2 * var(--universal-border-radius)); } - progress[value="1000"]::-moz-progress-bar { - border-radius: calc(2 * var(--universal-border-radius)); } - progress.inline { - display: inline-block; - vertical-align: middle; - width: 60%; } - -:root { - --spinner-back-color: #ddd; - --spinner-fore-color: #555; } - -@keyframes spinner-donut-anim { - 0% { - transform: rotate(0deg); } - 100% { - transform: rotate(360deg); } } -.spinner { - display: inline-block; - margin: var(--universal-margin); - border: 0.25rem solid var(--spinner-back-color); - border-left: 0.25rem solid var(--spinner-fore-color); - border-radius: 50%; - width: 1.25rem; - height: 1.25rem; - animation: spinner-donut-anim 1.2s linear infinite; } - -/* - Custom elements for progress bars and spinners. -*/ -progress.primary { - --progress-fore-color: #1976d2; } - -progress.secondary { - --progress-fore-color: #d32f2f; } - -progress.tertiary { - --progress-fore-color: #308732; } - -.spinner.primary { - --spinner-fore-color: #1976d2; } - -.spinner.secondary { - --spinner-fore-color: #d32f2f; } - -.spinner.tertiary { - --spinner-fore-color: #308732; } - -/* - Definitions for icons - powered by Feather (https://feathericons.com/). -*/ -span[class^='icon-'] { - display: inline-block; - height: 1em; - width: 1em; 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} -span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } - -/* - Definitions for utilities and helper classes. -*/ -/* Utility module CSS variable definitions */ -:root { - --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } - -.hidden { - display: none !important; } - -.visually-hidden { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } - -.bordered { - border: 0.0714285714rem solid var(--generic-border-color) !important; } - -.rounded { - border-radius: var(--universal-border-radius) !important; } - -.circular { - border-radius: 50% !important; } - -.shadowed { - box-shadow: var(--generic-box-shadow) !important; } - -.responsive-margin { - margin: calc(var(--universal-margin) / 4) !important; } - @media screen and (min-width: 500px) { - .responsive-margin { - margin: calc(var(--universal-margin) / 2) !important; } } - @media screen and (min-width: 1280px) { - .responsive-margin { - margin: var(--universal-margin) !important; } } - -.responsive-padding { - padding: calc(var(--universal-padding) / 4) !important; } - @media screen and (min-width: 500px) { - .responsive-padding { - padding: calc(var(--universal-padding) / 2) !important; } } - @media screen and (min-width: 1280px) { - .responsive-padding { - padding: var(--universal-padding) !important; } } - -@media screen and (max-width: 499px) { - .hidden-sm { - display: none !important; } } -@media screen and (min-width: 500px) and (max-width: 1279px) { - .hidden-md { - display: none !important; } } -@media screen and (min-width: 1280px) { - .hidden-lg { - display: none !important; } } -@media screen and (max-width: 499px) { - .visually-hidden-sm { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } } -@media screen and (min-width: 500px) and (max-width: 1279px) { - .visually-hidden-md { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } } -@media screen and (min-width: 1280px) { - .visually-hidden-lg { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } } - -/*# sourceMappingURL=mini-custom.css.map */ - -img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } -img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} - -.figure { - display: block; - margin-left: auto; - margin-right: auto; - text-align: center; -} diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png deleted file mode 100644 index d6cebb5ac..000000000 Binary files a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png and /dev/null differ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c deleted file mode 100644 index 952ff16c9..000000000 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c +++ /dev/null @@ -1,886 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203.c - * @author MCD Application Team - * @brief This file provides the TCPP02/03 Type-C port protection driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tcpp0203.h" - -#if defined(_TRACE) -#include "usbpd_core.h" -#include "usbpd_trace.h" -#include "string.h" -#include "stdio.h" -#endif /* _TRACE */ - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup TCPP0203 - * @brief This file provides a set of functions needed to drive the - * TCPP02/03 Type-C port protection. - * @{ - */ - -/** @defgroup TCPP0203_Private_Constants Private Constants - * @{ - */ - -/* Compilation option in order to enable/disable a concistency check performed - after each I2C access into TCPP0203 registers : goal is to check that written value in Reg0 - is properly reflected into reg1 register content. - To enable register consistency check, please uncomment below definition. - To disable it, comment below line */ -/* #define TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** @defgroup TCPP0203_Private_Types Private Types - * @{ - */ -/* TCPP02/03 Type-C port protection driver structure initialization */ -TCPP0203_Drv_t TCPP0203_Driver = -{ - TCPP0203_Init, - TCPP0203_DeInit, - TCPP0203_Reset, - TCPP0203_SetVConnSwitch, - TCPP0203_SetGateDriverProvider, - TCPP0203_SetGateDriverConsumer, - TCPP0203_SetPowerMode, - TCPP0203_SetVBusDischarge, - TCPP0203_SetVConnDischarge, - TCPP0203_GetVConnSwitchAck, - TCPP0203_GetGateDriverProviderAck, - TCPP0203_GetGateDriverConsumerAck, - TCPP0203_GetPowerModeAck, - TCPP0203_GetVBusDischargeAck, - TCPP0203_GetVConnDischargeAck, - TCPP0203_GetOCPVConnFlag, - TCPP0203_GetOCPVBusFlag, - TCPP0203_GetOVPVBusFlag, - TCPP0203_GetOVPCCFlag, - TCPP0203_GetOTPFlag, - TCPP0203_GetVBusOkFlag, - TCPP0203_ReadTCPPType, - TCPP0203_ReadVCONNPower, - TCPP0203_WriteCtrlRegister, - TCPP0203_ReadAckRegister, - TCPP0203_ReadFlagRegister, -}; - -/** - * @} - */ - -/** @defgroup TCPP0203_Private_Variables Private Variables - * @{ - */ -static uint8_t TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_03; - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) -static uint8_t Reg0_Expected_Value = 0x00; -static uint8_t Reg1_LastRead_Value = 0x00; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup TCPP0203_Private_Function_Prototypes TCPP0203 Private Function Prototypes - * @{ - */ -static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); -static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); - -static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) -static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue); -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions - * @{ - */ - -/** - * @brief Register Bus Io to component - * @param Component object pointer - * @retval Status of execution - */ -int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO) -{ - int32_t ret; - - if (pObj == NULL) - { - ret = TCPP0203_ERROR; - } - else - { - pObj->IO.Init = pIO->Init; - pObj->IO.DeInit = pIO->DeInit; - pObj->IO.Address = pIO->Address; - pObj->IO.WriteReg = pIO->WriteReg; - pObj->IO.ReadReg = pIO->ReadReg; - pObj->IO.GetTick = pIO->GetTick; - - pObj->Ctx.ReadReg = TCPP0203_ReadRegWrap; - pObj->Ctx.WriteReg = TCPP0203_WriteRegWrap; - pObj->Ctx.handle = pObj; - - if (pObj->IO.Init != NULL) - { - ret = pObj->IO.Init(); - } - else - { - ret = TCPP0203_ERROR; - } - } - - return ret; -} - -/** - * @brief Initializes the TCPP0203 interface - * @param pObj Pointer to component object - * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) - */ -int32_t TCPP0203_Init(TCPP0203_Object_t *pObj) -{ - int32_t ret = 0; - uint8_t tmp; - - if (pObj->IsInitialized == 0U) - { - /* Read TCPP Device type */ - ret += tcpp0203_read_reg(&pObj->Ctx, TCPP0203_READ_REG2, &tmp, 1); - - if (ret == TCPP0203_OK) - { - TCPP0203_DeviceType = (tmp & TCPP0203_DEVICE_TYPE_MSK); - } - else - { - TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_02; - } - pObj->IsInitialized = 1U; - } - - if (ret != TCPP0203_OK) - { - ret = TCPP0203_ERROR; - } - - return ret; -} - -/** - * @brief Deinitializes the TCPP0203 interface - * @param pObj Pointer to component object - * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) - */ -int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj) -{ - if (pObj->IsInitialized == 1U) - { - /* De-Initialize IO BUS layer */ - pObj->IO.DeInit(); - - pObj->IsInitialized = 0U; - } - - return TCPP0203_OK; -} - -/** - * @brief Resets TCPP0203 register (Reg0) - * @param pObj Pointer to component object - * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) - */ -int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj) -{ - int32_t ret = TCPP0203_OK; - uint8_t tmp = TCPP0203_REG0_RST_VALUE; - - /* Write reset values in Reg0 register */ - if (tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1) != TCPP0203_OK) - { - ret = TCPP0203_ERROR; - } - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = TCPP0203_REG0_RST_VALUE; - Reg1_LastRead_Value = TCPP0203_REG0_RST_VALUE; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return ret; -} - -/** - * @brief Configure TCPP0203 VConn Switch - * @param pObj Pointer to component object - * @param VConnSwitch VConn Switch requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open - * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 - * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 - * @retval Component status - */ -int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch) -{ - int32_t ret = TCPP0203_OK; - - if ((VConnSwitch != TCPP0203_VCONN_SWITCH_OPEN) - && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC1) - && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC2)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update VConn switch setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, VConnSwitch, TCPP0203_VCONN_SWITCH_MSK); - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Provider path - * @param pObj Pointer to component object - * @param GateDriverProvider GDP switch load requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_GD_PROVIDER_SWITCH_OPEN GDP Switch Load Open - * @arg TCPP0203_GD_PROVIDER_SWITCH_CLOSED GDP Switch Load closed - * @retval Component status - */ -int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider) -{ - int32_t ret = TCPP0203_OK; - - if ((GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_OPEN) - && (GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_CLOSED)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update GDP Switch Load setting in Writing register Reg0 */ - if (GateDriverProvider == TCPP0203_GD_PROVIDER_SWITCH_CLOSED) - { - /* If Gate Driver Provider is to be closed, Gate Driver Consumer should be open */ - ret += TCPP0203_ModifyReg0(pObj, (GateDriverProvider | TCPP0203_GD_CONSUMER_SWITCH_OPEN), - (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); - } - else - { - ret += TCPP0203_ModifyReg0(pObj, GateDriverProvider, TCPP0203_GD_PROVIDER_SWITCH_MSK); - } - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Consumer path - * @param pObj Pointer to component object - * @param GateDriverConsumer GDC switch load requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_GD_CONSUMER_SWITCH_OPEN GDC Switch Load Open - * @arg TCPP0203_GD_CONSUMER_SWITCH_CLOSED GDC Switch Load closed - * @retval Component status - */ -int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer) -{ - int32_t ret = TCPP0203_OK; - - /* Check if TCPP type is TCPP03. Otherwise, return error */ - if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) - { - return (TCPP0203_ERROR); - } - - if ((GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_OPEN) - && (GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_CLOSED)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update GDC Switch Load setting in Writing register Reg0 */ - if (GateDriverConsumer == TCPP0203_GD_CONSUMER_SWITCH_CLOSED) - { - /* If Gate Driver Consumer is to be closed, Gate Driver Provider should be open */ - ret += TCPP0203_ModifyReg0(pObj, (GateDriverConsumer | TCPP0203_GD_PROVIDER_SWITCH_OPEN), - (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); - } - else - { - ret += TCPP0203_ModifyReg0(pObj, GateDriverConsumer, TCPP0203_GD_CONSUMER_SWITCH_MSK); - } - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Power Mode - * @param pObj Pointer to component object - * @param PowerMode Power mode requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_POWER_MODE_HIBERNATE Hibernate - * @arg TCPP0203_POWER_MODE_LOWPOWER Low Power - * @arg TCPP0203_POWER_MODE_NORMAL Normal - * @retval Component status - */ -int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode) -{ - int32_t ret = TCPP0203_OK; - - if ((PowerMode != TCPP0203_POWER_MODE_HIBERNATE) - && (PowerMode != TCPP0203_POWER_MODE_LOWPOWER) - && (PowerMode != TCPP0203_POWER_MODE_NORMAL)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update Power Mode setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, PowerMode, TCPP0203_POWER_MODE_MSK); - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Provider path - * @param pObj Pointer to component object - * @param VBusDischarge VBUS Discharge requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_VBUS_DISCHARGE_OFF VBUS Discharge Off - * @arg TCPP0203_VBUS_DISCHARGE_ON VBUS Discharge On - * @retval Component status - */ -int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge) -{ - int32_t ret = TCPP0203_OK; - - if ((VBusDischarge != TCPP0203_VBUS_DISCHARGE_OFF) - && (VBusDischarge != TCPP0203_VBUS_DISCHARGE_ON)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update VBUS Discharge setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, VBusDischarge, TCPP0203_VBUS_DISCHARGE_MSK); - } - - return ret; -} - -/** - * @brief Configure TCPP0203 Gate Driver for Provider path - * @param pObj Pointer to component object - * @param VConnDischarge GDP switch load requested setting - * This parameter can be one of the following values: - * @arg TCPP0203_VCONN_DISCHARGE_OFF VConn Discharge Off - * @arg TCPP0203_VCONN_DISCHARGE_ON VConn Discharge On - * @retval Component status - */ -int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge) -{ - int32_t ret = TCPP0203_OK; - - if ((VConnDischarge != TCPP0203_VCONN_DISCHARGE_OFF) - && (VConnDischarge != TCPP0203_VCONN_DISCHARGE_ON)) - { - ret = TCPP0203_ERROR; - } - else - { - /* Update VConn Discharge setting in Writing register Reg0 */ - ret += TCPP0203_ModifyReg0(pObj, VConnDischarge, TCPP0203_VCONN_DISCHARGE_MSK); - } - - return ret; -} - -/** - * @brief Get VConn switch Ack value - * @param pObj Pointer to component object - * @param pVConnSwitchAck Pointer on VConn switch Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open Ack - * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 Ack - * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 Ack - * @retval Component status - */ -int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pVConnSwitchAck = (tmp & TCPP0203_VCONN_SWITCH_ACK_MSK); - - return ret; -} - -/** - * @brief Get Gate Driver Provider Ack value - * @param pObj Pointer to component object - * @param pGateDriverProviderAck Pointer on Gate Driver Provider Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN Gate Driver Provider Open Ack - * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED Gate Driver Provider Closed Ack - * @retval Component status - */ -int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pGateDriverProviderAck = (tmp & TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK); - - return ret; -} - -/** - * @brief Get Gate Driver Consumer Ack value - * @param pObj Pointer to component object - * @param pGateDriverConsumerAck Pointer on Gate Driver Consumer Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN Gate Driver Consumer Open Ack - * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED Gate Driver Consumer Closed Ack - * @retval Component status - */ -int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck) -{ - int32_t ret; - uint8_t tmp; - - /* Check if TCPP type is TCPP03. Otherwise, return error */ - if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) - { - return (TCPP0203_ERROR); - } - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pGateDriverConsumerAck = (tmp & TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK); - - return ret; -} - -/** - * @brief Get Power Mode Ack value - * @param pObj Pointer to component object - * @param pPowerModeAck Pointer on Power Mode Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_POWER_MODE_ACK_HIBERNATE Power Mode Hibernate Ack - * @arg TCPP0203_POWER_MODE_ACK_LOWPOWER Power Mode Low Power Ack - * @arg TCPP0203_POWER_MODE_ACK_NORMAL Power Mode Normal Ack - * @retval Component status - */ -int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pPowerModeAck = (tmp & TCPP0203_POWER_MODE_ACK_MSK); - - return ret; -} - -/** - * @brief Get VBUS Discharge Ack value - * @param pObj Pointer to component object - * @param pVBusDischargeAck Pointer on VBUS Discharge Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_VBUS_DISCHARGE_ACK_OFF VBUS Discharge Off Ack - * @arg TCPP0203_VBUS_DISCHARGE_ACK_ON VBUS Discharge On Ack - * @retval Component status - */ -int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pVBusDischargeAck = (tmp & TCPP0203_VBUS_DISCHARGE_ACK_MSK); - - return ret; -} - -/** - * @brief Get VConn Discharge Ack value - * @param pObj Pointer to component object - * @param pVConnDischargeAck Pointer on VConn Discharge Ack value - * This output parameter can be one of the following values: - * @arg TCPP0203_VCONN_DISCHARGE_ACK_OFF VConn Discharge Off Ack - * @arg TCPP0203_VCONN_DISCHARGE_ACK_ON VConn Discharge On Ack - * @retval Component status - */ -int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - *pVConnDischargeAck = (tmp & TCPP0203_VCONN_DISCHARGE_ACK_MSK); - - return ret; -} - -/** - * @brief Get OCP VConn Flag value - * @param pObj Pointer to component object - * @param pOCPVConnFlag Pointer on OCP VConn Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OCP_VCONN_RESET OCP VConn flag not set - * @arg TCPP0203_FLAG_OCP_VCONN_SET OCP VConn flag set - * @retval Component status - */ -int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOCPVConnFlag = (tmp & TCPP0203_FLAG_OCP_VCONN_MSK); - - return ret; -} - -/** - * @brief Get OCP VBUS Flag value - * @param pObj Pointer to component object - * @param pGetOCPVBusFlag Pointer on OCP VBUS Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OCP_VBUS_RESET OCP VBUS flag not set - * @arg TCPP0203_FLAG_OCP_VBUS_SET OCP VBUS flag set - * @retval Component status - */ -int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pGetOCPVBusFlag = (tmp & TCPP0203_FLAG_OCP_VBUS_MSK); - - return ret; -} - -/** - * @brief Get OVP VBUS Flag value - * @param pObj Pointer to component object - * @param pOVPVBusFlag Pointer on OVP VBUS Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OVP_VBUS_RESET OVP VBUS flag not set - * @arg TCPP0203_FLAG_OVP_VBUS_SET OVP VBUS flag set - * @retval Component status - */ -int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOVPVBusFlag = (tmp & TCPP0203_FLAG_OVP_VBUS_MSK); - - return ret; -} - -/** - * @brief Get OVP CC Flag value - * @param pObj Pointer to component object - * @param pOVPCCFlag Pointer on OVP CC Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OVP_CC_RESET OVP CC flag not set - * @arg TCPP0203_FLAG_OVP_CC_SET OVP CC flag set - * @retval Component status - */ -int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOVPCCFlag = (tmp & TCPP0203_FLAG_OVP_CC_MSK); - - return ret; -} - -/** - * @brief Get Over Temperature Flag value - * @param pObj Pointer to component object - * @param pOTPFlag Pointer on Over Temperature Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_OTP_RESET Over Temperature flag not set - * @arg TCPP0203_FLAG_OTP_SET Over Temperature flag set - * @retval Component status - */ -int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pOTPFlag = (tmp & TCPP0203_FLAG_OTP_MSK); - - return ret; -} - -/** - * @brief Get VBUS OK Flag value - * @param pObj Pointer to component object - * @param pVBusOkFlag Pointer on VBUS OK Flag value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_VBUS_OK_RESET VBUS OK flag not set - * @arg TCPP0203_FLAG_VBUS_OK_SET VBUS OK flag set - * @retval Component status - */ -int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pVBusOkFlag = (tmp & TCPP0203_FLAG_VBUS_OK_MSK); - - return ret; -} - -/** - * @brief Get TCPP0203 Device Type value - * @param pObj Pointer to component object - * @param pTCPPType Pointer on TCPP0203 Device Type value - * This output parameter can be one of the following values: - * @arg TCPP0203_DEVICE_TYPE_02 TCPP02 Type - * @arg TCPP0203_DEVICE_TYPE_03 TCPP03 Type - * @retval Component status - */ -int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pTCPPType = (tmp & TCPP0203_DEVICE_TYPE_MSK); - - return ret; -} - -/** - * @brief Get VConn Power value - * @param pObj Pointer to component object - * @param pVCONNPower Pointer on VConn Power value - * This output parameter can be one of the following values: - * @arg TCPP0203_FLAG_VCONN_PWR_1W OCP VConn flag not set - * @arg TCPP0203_FLAG_VCONN_PWR_0_1W OCP VConn flag set - * @retval Component status - */ -int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower) -{ - int32_t ret; - uint8_t tmp; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); - *pVCONNPower = (tmp & TCPP0203_FLAG_VCONN_PWR_MSK); - - return ret; -} - -/** - * @brief Set complete Ctrl register value (Reg 0) - * @param pObj Pointer to component object - * @param pCtrlRegister Pointer on Ctrl register value - * @retval Component status - */ -int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister) -{ - int32_t ret; - - /* Update value in writing register (reg0) */ - ret = tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, pCtrlRegister, 1); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = *pCtrlRegister; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return ret; -} - -/** - * @brief Get complete Ack register value - * @param pObj Pointer to component object - * @param pAckRegister Pointer on Ack register value - * @retval Component status - */ -int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister) -{ - int32_t ret; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, pAckRegister, 1); - - return ret; -} - -/** - * @brief Get complete Flag register value - * @param pObj Pointer to component object - * @param pFlagRegister Pointer on Flag register value - * @retval Component status - */ -int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister) -{ - int32_t ret; - - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, pFlagRegister, 1); - - return ret; -} - -/******************** Static functions ****************************************/ -/** - * @brief Wrap TCPP0203 read function to Bus IO function - * @param handle Component object handle - * @param Reg Target register address to read - * @param pData Buffer where Target register value should be stored - * @param Length buffer size to be read - * @retval error status - */ -static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) -{ - const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; - - return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length); -} - -/** - * @brief Wrap TCPP0203 write function to Bus IO function - * @param handle Component object handle - * @param Reg Target register address to write - * @param pData Target register value to be written - * @param Length Buffer size to be written - * @retval error status - */ -static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) -{ - const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = *pData; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length); -} - -/** - * @brief TCPP0203 register update function to Bus IO function - * @param handle Component object handle - * @param Reg Target register address to write - * @param pData Target register value to be written - * @param Length Buffer size to be written - * @retval error status - */ -static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask) -{ - int32_t ret; - uint8_t tmp; - - /* Read current content of ACK register (reflects content of bits set to 1 in Writing register Reg0) */ - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); - - /* Update only the area dedicated to Mask */ - tmp &= ~(Mask); - tmp |= (Value & Mask); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - Reg0_Expected_Value = tmp; -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - /* Update value in writing register (reg0) */ - ret += tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1); - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) - ret += TCPP0203_CheckReg0Reg1(pObj, Reg0_Expected_Value); -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - - return ret; -} - -#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) -/** - * @brief TCPP0203 register control function between Reg0 and Reg1 value - * @param handle Component object handle - * @param Reg0ExpectedValue Value expected in Reg0 (built after all calls to write functions) - * @retval error status - */ -static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue) -{ - int32_t ret; - - /* Read current content of ACK register (expected to reflect content of bits set to 1 in Writing register Reg0) */ - ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &Reg1_LastRead_Value, 1); - -#ifdef _TRACE - char str[12]; - sprintf(str, "Exp0_0x%02x", Reg0ExpectedValue); - USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); - sprintf(str, "Reg1_0x%02x", Reg1_LastRead_Value); - USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); -#endif /* _TRACE */ - - /* Control if Reg1 value is same as Reg0 expected one */ - if (Reg1_LastRead_Value != Reg0ExpectedValue) - { - while (1); - } - - return ret; -} -#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h deleted file mode 100644 index 271b534fc..000000000 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h +++ /dev/null @@ -1,353 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the - * tcpp0203.c driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef TCPP0203_H -#define TCPP0203_H - -/* Includes ------------------------------------------------------------------*/ -#include "tcpp0203_reg.h" -#include - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Component - * @{ - */ - -/** @addtogroup TCPP0203 - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup TCPP0203_Exported_Types TCPP0203 Exported Types - * @{ - */ -typedef int32_t (*TCPP0203_Init_Func)(void); -typedef int32_t (*TCPP0203_DeInit_Func)(void); -typedef int32_t (*TCPP0203_GetTick_Func)(void); -typedef int32_t (*TCPP0203_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); -typedef int32_t (*TCPP0203_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); - -typedef struct -{ - TCPP0203_Init_Func Init; - TCPP0203_DeInit_Func DeInit; - uint16_t Address; - TCPP0203_WriteReg_Func WriteReg; - TCPP0203_ReadReg_Func ReadReg; - TCPP0203_GetTick_Func GetTick; -} TCPP0203_IO_t; - - -typedef struct -{ - TCPP0203_IO_t IO; - TCPP0203_ctx_t Ctx; - uint8_t IsInitialized; -} TCPP0203_Object_t; - -typedef struct -{ - int32_t (*Init)(TCPP0203_Object_t *); - int32_t (*DeInit)(TCPP0203_Object_t *); - int32_t (*Reset)(TCPP0203_Object_t *); - int32_t (*SetVConnSwitch)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetGateDriverProvider)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetGateDriverConsumer)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetPowerMode)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetVBusDischarge)(TCPP0203_Object_t *, uint8_t); - int32_t (*SetVConnDischarge)(TCPP0203_Object_t *, uint8_t); - int32_t (*GetVConnSwitchAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetGateDriverProviderAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetGateDriverConsumerAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetPowerModeAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetVBusDischargeAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetVConnDischargeAck)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOCPVConnFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOCPVBusFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOVPVBusFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOVPCCFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetOTPFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*GetVBusOkFlag)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadTCPPType)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadVCONNPower)(TCPP0203_Object_t *, uint8_t *); - int32_t (*WriteCtrlRegister)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadAckRegister)(TCPP0203_Object_t *, uint8_t *); - int32_t (*ReadFlagRegister)(TCPP0203_Object_t *, uint8_t *); -} TCPP0203_Drv_t; - -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants - * @{ - */ -/** - * @brief TCPP0203 Driver Response codes - */ -#define TCPP0203_OK (0) -#define TCPP0203_ERROR (-1) - -/** - * @brief TCPP0203 possible I2C Addresses - */ -#define TCPP0203_I2C_ADDRESS_X68 (0x68U) -#define TCPP0203_I2C_ADDRESS_X6A (0x6AU) - -/** - * @brief TCPP0203 Reg0 Reset Value - */ -#define TCPP0203_REG0_RST_VALUE TCPP0203_GD_CONSUMER_SWITCH_CLOSED - -/** - * @brief TCPP0203 VCONN Switch - */ -#define TCPP0203_VCONN_SWITCH_POS (0U) -#define TCPP0203_VCONN_SWITCH_MSK (0x03U << TCPP0203_VCONN_SWITCH_POS) -#define TCPP0203_VCONN_SWITCH_OPEN (0x00U) -#define TCPP0203_VCONN_SWITCH_CC1 (0x01U << TCPP0203_VCONN_SWITCH_POS) -#define TCPP0203_VCONN_SWITCH_CC2 (0x02U << TCPP0203_VCONN_SWITCH_POS) - -/** - * @brief TCPP0203 Gate Driver Provider values - */ -#define TCPP0203_GD_PROVIDER_SWITCH_POS (2U) -#define TCPP0203_GD_PROVIDER_SWITCH_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_POS) -#define TCPP0203_GD_PROVIDER_SWITCH_OPEN (0x00U) -#define TCPP0203_GD_PROVIDER_SWITCH_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_MSK) - -/** - * @brief TCPP0203 Gate Driver Consumer values - */ -#define TCPP0203_GD_CONSUMER_SWITCH_POS (3U) -#define TCPP0203_GD_CONSUMER_SWITCH_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_POS) -#define TCPP0203_GD_CONSUMER_SWITCH_CLOSED (0x00U) -#define TCPP0203_GD_CONSUMER_SWITCH_OPEN (TCPP0203_GD_CONSUMER_SWITCH_MSK) - -/** - * @brief TCPP0203 Power Mode values - */ -#define TCPP0203_POWER_MODE_POS (4U) -#define TCPP0203_POWER_MODE_MSK (0x03U << TCPP0203_POWER_MODE_POS) -#define TCPP0203_POWER_MODE_HIBERNATE (0x00U) -#define TCPP0203_POWER_MODE_LOWPOWER (0x02U << TCPP0203_POWER_MODE_POS) -#define TCPP0203_POWER_MODE_NORMAL (0x01U << TCPP0203_POWER_MODE_POS) - -/** - * @brief TCPP0203 VBUS Discharge management - */ -#define TCPP0203_VBUS_DISCHARGE_POS (6U) -#define TCPP0203_VBUS_DISCHARGE_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_POS) -#define TCPP0203_VBUS_DISCHARGE_OFF (0x00U) -#define TCPP0203_VBUS_DISCHARGE_ON (TCPP0203_VBUS_DISCHARGE_MSK) - -/** - * @brief TCPP0203 VConn Discharge management - */ -#define TCPP0203_VCONN_DISCHARGE_POS (7U) -#define TCPP0203_VCONN_DISCHARGE_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_POS) -#define TCPP0203_VCONN_DISCHARGE_OFF (0x00U) -#define TCPP0203_VCONN_DISCHARGE_ON (TCPP0203_VCONN_DISCHARGE_MSK) - -/** - * @brief TCPP0203 VCONN Switch Acknowledge - */ -#define TCPP0203_VCONN_SWITCH_ACK_POS (0U) -#define TCPP0203_VCONN_SWITCH_ACK_MSK (0x03U << TCPP0203_VCONN_SWITCH_ACK_POS) -#define TCPP0203_VCONN_SWITCH_ACK_OPEN (0x00U) -#define TCPP0203_VCONN_SWITCH_ACK_CC1 (0x02U << TCPP0203_VCONN_SWITCH_ACK_POS) -#define TCPP0203_VCONN_SWITCH_ACK_CC2 (0x01U << TCPP0203_VCONN_SWITCH_ACK_POS) - -/** - * @brief TCPP0203 Gate Driver Provider Acknowledge - */ -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_POS (2U) -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_ACK_POS) -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN (0x00U) -#define TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK) - -/** - * @brief TCPP0203 Gate Driver Consumer Acknowledge - */ -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_POS (3U) -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_ACK_POS) -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED (0x00U) -#define TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN (TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK) - -/** - * @brief TCPP0203 Power Mode Acknowledge - */ -#define TCPP0203_POWER_MODE_ACK_POS (4U) -#define TCPP0203_POWER_MODE_ACK_MSK (0x03U << TCPP0203_POWER_MODE_ACK_POS) -#define TCPP0203_POWER_MODE_ACK_HIBERNATE (0x00U) -#define TCPP0203_POWER_MODE_ACK_LOWPOWER (0x01U << TCPP0203_POWER_MODE_ACK_POS) -#define TCPP0203_POWER_MODE_ACK_NORMAL (0x02U << TCPP0203_POWER_MODE_ACK_POS) - -/** - * @brief TCPP0203 VBUS Discharge Acknowledge - */ -#define TCPP0203_VBUS_DISCHARGE_ACK_POS (6U) -#define TCPP0203_VBUS_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_ACK_POS) -#define TCPP0203_VBUS_DISCHARGE_ACK_OFF (0x00U) -#define TCPP0203_VBUS_DISCHARGE_ACK_ON (TCPP0203_VBUS_DISCHARGE_ACK_MSK) - -/** - * @brief TCPP0203 VConn Discharge Acknowledge - */ -#define TCPP0203_VCONN_DISCHARGE_ACK_POS (7U) -#define TCPP0203_VCONN_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_ACK_POS) -#define TCPP0203_VCONN_DISCHARGE_ACK_OFF (0x00U) -#define TCPP0203_VCONN_DISCHARGE_ACK_ON (TCPP0203_VCONN_DISCHARGE_ACK_MSK) - -/** - * @brief TCPP0203 OCP Vconn Flag management - */ -#define TCPP0203_FLAG_OCP_VCONN_POS (0U) -#define TCPP0203_FLAG_OCP_VCONN_MSK (0x01U << TCPP0203_FLAG_OCP_VCONN_POS) -#define TCPP0203_FLAG_OCP_VCONN_SET (TCPP0203_FLAG_OCP_VCONN_MSK) -#define TCPP0203_FLAG_OCP_VCONN_RESET (0x00U) - -/** - * @brief TCPP0203 OCP VBUS Flag management - */ -#define TCPP0203_FLAG_OCP_VBUS_POS (1U) -#define TCPP0203_FLAG_OCP_VBUS_MSK (0x01U << TCPP0203_FLAG_OCP_VBUS_POS) -#define TCPP0203_FLAG_OCP_VBUS_SET (TCPP0203_FLAG_OCP_VBUS_MSK) -#define TCPP0203_FLAG_OCP_VBUS_RESET (0x00U) - -/** - * @brief TCPP0203 OVP VBUS Flag management - */ -#define TCPP0203_FLAG_OVP_VBUS_POS (2U) -#define TCPP0203_FLAG_OVP_VBUS_MSK (0x01U << TCPP0203_FLAG_OVP_VBUS_POS) -#define TCPP0203_FLAG_OVP_VBUS_SET (TCPP0203_FLAG_OVP_VBUS_MSK) -#define TCPP0203_FLAG_OVP_VBUS_RESET (0x00U) - -/** - * @brief TCPP0203 OVP CC Flag management - */ -#define TCPP0203_FLAG_OVP_CC_POS (3U) -#define TCPP0203_FLAG_OVP_CC_MSK (0x01U << TCPP0203_FLAG_OVP_CC_POS) -#define TCPP0203_FLAG_OVP_CC_SET (TCPP0203_FLAG_OVP_CC_MSK) -#define TCPP0203_FLAG_OVP_CC_RESET (0x00U) - -/** - * @brief TCPP0203 OTP Flag management - */ -#define TCPP0203_FLAG_OTP_POS (4U) -#define TCPP0203_FLAG_OTP_MSK (0x01U << TCPP0203_FLAG_OTP_POS) -#define TCPP0203_FLAG_OTP_SET (TCPP0203_FLAG_OTP_MSK) -#define TCPP0203_FLAG_OTP_RESET (0x00U) - -/** - * @brief TCPP0203 VBUS OK Flag management - */ -#define TCPP0203_FLAG_VBUS_OK_POS (5U) -#define TCPP0203_FLAG_VBUS_OK_MSK (0x01U << TCPP0203_FLAG_VBUS_OK_POS) -#define TCPP0203_FLAG_VBUS_OK_SET (TCPP0203_FLAG_VBUS_OK_MSK) -#define TCPP0203_FLAG_VBUS_OK_RESET (0x00U) - -/** - * @brief TCPP0203 VConn Power - */ -#define TCPP0203_FLAG_VCONN_PWR_POS (6U) -#define TCPP0203_FLAG_VCONN_PWR_MSK (0x01U << TCPP0203_FLAG_VCONN_PWR_POS) -#define TCPP0203_FLAG_VCONN_PWR_1W (TCPP0203_FLAG_VCONN_PWR_MSK) -#define TCPP0203_FLAG_VCONN_PWR_0_1W (0x00U) - -/** - * @brief TCPP0203 Device Type - */ -#define TCPP0203_DEVICE_TYPE_POS (7U) -#define TCPP0203_DEVICE_TYPE_MSK (0x01U << TCPP0203_DEVICE_TYPE_POS) -#define TCPP0203_DEVICE_TYPE_02 (TCPP0203_DEVICE_TYPE_MSK) -#define TCPP0203_DEVICE_TYPE_03 (0x00U) - -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Macros TCPP0203 Exported Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions - * @{ - */ - -/*------------------------------------------------------------------------------ - TCPP02/03 Type-C port protection functions -------------------------------------------------------------------------------*/ -/* High Layer codec functions */ -int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO); -int32_t TCPP0203_Init(TCPP0203_Object_t *pObj); -int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj); -int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj); -int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch); -int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider); -int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer); -int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode); -int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge); -int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge); -int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck); -int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck); -int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck); -int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck); -int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck); -int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck); -int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag); -int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag); -int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag); -int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag); -int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag); -int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag); -int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType); -int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower); -int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister); -int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister); -int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister); - -/** - * @} - */ - -/* TCPP02/03 Type-C port protection driver structure */ -extern TCPP0203_Drv_t TCPP0203_Driver; - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TCPP0203_H */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c deleted file mode 100644 index 8025fa85e..000000000 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c +++ /dev/null @@ -1,73 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203_reg.c - * @author MCD Application Team - * @brief This file provides unitary register function to control the TCPP02-03 - * Type-C port protection driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "tcpp0203_reg.h" - -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Components - * @{ - */ - -/** @addtogroup TCPP0203 - * @brief This file provides a set of functions needed to drive the - * TCPP02/03 Type-C port protection codec. - * @{ - */ - -/************** Generic Function *******************/ -/******************************************************************************* - * Function Name : tcpp0203_read_reg - * Description : Generic Reading function. It must be fulfilled with either - * I2C or SPI reading functions - * Input : Register Address, length of buffer - * Output : data Read - *******************************************************************************/ -int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) -{ - return ctx->ReadReg(ctx->handle, reg, data, length); -} - -/******************************************************************************* - * Function Name : tcpp0203_write_reg - * Description : Generic Writing function. It must be fulfilled with either - * I2C or SPI writing function - * Input : Register Address, data to be written, length of buffer - * Output : None - *******************************************************************************/ -int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) -{ - return ctx->WriteReg(ctx->handle, reg, data, length); -} - -/******************************************************************************/ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h deleted file mode 100644 index 92420e1fe..000000000 --- a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file tcpp0203_reg.h - * @author MCD Application Team - * @brief Header of tcpp0203_reg.c - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef TCPP0203_REG_H -#define TCPP0203_REG_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/** @addtogroup BSP - * @{ - */ - -/** @addtogroup Component - * @{ - */ - -/** @addtogroup TCPP0203 - * @{ - */ - - -/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants - * @{ - */ -/******************************************************************************/ -/****************************** REGISTER MAPPING ******************************/ -/******************************************************************************/ -#define TCPP0203_WRITE_REG 0x00U -#define TCPP0203_PROG_CTRL TCPP0203_WRITE_REG -#define TCPP0203_READ_REG1 0x01U -#define TCPP0203_ACK_REG TCPP0203_READ_REG1 -#define TCPP0203_READ_REG2 0x02U -#define TCPP0203_FLAG_REG TCPP0203_READ_REG2 - -/** - * @} - */ - -/************** Generic Function *******************/ - -typedef int32_t (*TCPP0203_Write_Func)(const void *, uint8_t, uint8_t *, uint8_t); -typedef int32_t (*TCPP0203_Read_Func)(const void *, uint8_t, uint8_t *, uint8_t); - -typedef struct -{ - TCPP0203_Write_Func WriteReg; - TCPP0203_Read_Func ReadReg; - void *handle; -} TCPP0203_ctx_t; - -/******************************************************************************* - * Register : Generic - All - * Address : Generic - All - * Bit Group Name: None - * Permission : W - *******************************************************************************/ -int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); -int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); - -#ifdef __cplusplus -} -#endif - -#endif /* TCPP0203_REG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/hw/bsp/stm32n6/family.cmake b/hw/bsp/stm32n6/family.cmake index c2c634525..76763937e 100644 --- a/hw/bsp/stm32n6/family.cmake +++ b/hw/bsp/stm32n6/family.cmake @@ -6,6 +6,7 @@ set(ST_PREFIX stm32${ST_FAMILY}xx) set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) +set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) diff --git a/hw/bsp/stm32n6/family.mk b/hw/bsp/stm32n6/family.mk index d613e53d2..37087ed42 100644 --- a/hw/bsp/stm32n6/family.mk +++ b/hw/bsp/stm32n6/family.mk @@ -2,6 +2,7 @@ ST_FAMILY = n6 ST_PREFIX = stm32${ST_FAMILY}xx ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver +ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203 UF2_FAMILY_ID = 0x6db66083 diff --git a/tools/get_deps.py b/tools/get_deps.py index b2699b88c..6a36ef35d 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -133,6 +133,9 @@ deps_optional = { 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', '7f4389efee9c6a655b55e5df3fceef5586b35f9b', 'stm32h7'], + 'hw/mcu/st/stm32-tcpp0203': ['https://github.com/STMicroelectronics/stm32-tcpp0203.git', + '9918655bff176ac3046ccf378b5c7bbbc6a38d15', + 'stm32h7rs stm32n6'], 'hw/mcu/st/stm32c0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git', '41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3', 'stm32c0'], -- cgit v1.3.1 From 0388700ad7c0fc8565457a56d7e7bd5744ac0d1d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 2 Jul 2025 15:32:12 +0700 Subject: update esp build, replace TUSB_MCU_VENDOR_ESPRESSIF by ESP_PLATFORM --- .github/workflows/build.yml | 2 +- examples/device/audio_4_channel_mic_freertos/src/main.c | 11 +++++------ .../device/audio_4_channel_mic_freertos/src/tusb_config.h | 2 +- examples/device/audio_test_freertos/src/main.c | 8 ++++---- examples/device/audio_test_freertos/src/tusb_config.h | 2 +- examples/device/board_test/src/tusb_config.h | 2 +- examples/device/cdc_msc_freertos/src/main.c | 8 ++++---- examples/device/cdc_msc_freertos/src/tusb_config.h | 2 +- examples/device/hid_composite_freertos/src/main.c | 11 +++++------ examples/device/hid_composite_freertos/src/tusb_config.h | 2 +- examples/device/midi_test_freertos/src/main.c | 8 ++++---- examples/device/video_capture/src/main.c | 6 +++--- examples/device/video_capture/src/tusb_config.h | 2 +- examples/device/video_capture_2ch/src/main.c | 6 +++--- examples/device/video_capture_2ch/src/tusb_config.h | 2 +- examples/host/cdc_msc_hid_freertos/src/cdc_app.c | 2 +- examples/host/cdc_msc_hid_freertos/src/main.c | 8 ++++---- examples/host/cdc_msc_hid_freertos/src/tusb_config.h | 2 +- examples/host/device_info/src/main.c | 8 ++++---- examples/host/device_info/src/tusb_config.h | 2 +- examples/host/midi_rx/src/tusb_config.h | 2 +- examples/typec/power_delivery/src/main.c | 5 ++--- hw/bsp/board.c | 7 ++++--- hw/bsp/board_api.h | 3 ++- hw/bsp/espressif/boards/family.c | 4 ++++ tools/build.py | 6 ++---- tools/build_utils.py | 2 ++ 27 files changed, 64 insertions(+), 61 deletions(-) (limited to 'tools') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 58963013b..97f219e6f 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -93,7 +93,7 @@ jobs: matrix: toolchain: - 'aarch64-gcc' - - 'arm-clang' + #- 'arm-clang' - 'arm-gcc' - 'msp430-gcc' - 'riscv-gcc' diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c index 99278b5cc..d5a34b194 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/main.c +++ b/examples/device/audio_4_channel_mic_freertos/src/main.c @@ -39,7 +39,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -158,17 +158,16 @@ int main(void) xTaskCreate(audio_task, "audio", AUDIO_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); #endif - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUSB_MCU_VENDOR_ESPRESSIF + // only start scheduler for non-espressif mcu + #ifndef ESP_PLATFORM vTaskStartScheduler(); #endif return 0; } -#if TUSB_MCU_VENDOR_ESPRESSIF -void app_main(void) -{ +#ifdef ESP_PLATFORM +void app_main(void) { main(); } #endif diff --git a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h index 5ac51b153..f7c0efe08 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ extern "C" { #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c index c5143c3fc..3831be87f 100644 --- a/examples/device/audio_test_freertos/src/main.c +++ b/examples/device/audio_test_freertos/src/main.c @@ -38,7 +38,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -132,15 +132,15 @@ int main(void) xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); #endif - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUSB_MCU_VENDOR_ESPRESSIF + // only start scheduler for non-espressif mcu + #ifndef ESP_PLATFORM vTaskStartScheduler(); #endif return 0; } -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM void app_main(void) { main(); } diff --git a/examples/device/audio_test_freertos/src/tusb_config.h b/examples/device/audio_test_freertos/src/tusb_config.h index 61c5cbb96..0fb2106e2 100644 --- a/examples/device/audio_test_freertos/src/tusb_config.h +++ b/examples/device/audio_test_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ extern "C" { #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h index 8ac3bc8de..81829d450 100644 --- a/examples/device/board_test/src/tusb_config.h +++ b/examples/device/board_test/src/tusb_config.h @@ -44,7 +44,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 4dada9801..6fe964153 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -30,7 +30,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define USBD_STACK_SIZE 4096 #else // Increase stack size when debug log is enabled @@ -91,15 +91,15 @@ int main(void) { xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL); #endif -#if !TUSB_MCU_VENDOR_ESPRESSIF - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 +#ifndef ESP_PLATFORM + // only start scheduler for non-espressif mcu vTaskStartScheduler(); #endif return 0; } -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM void app_main(void) { main(); } diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h index c3f2f7fb5..71a0e985a 100644 --- a/examples/device/cdc_msc_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index 30c0331ef..3f5e8a91c 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -31,7 +31,7 @@ #include "tusb.h" #include "usb_descriptors.h" -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -112,17 +112,16 @@ int main(void) xTimerStart(blinky_tm, 0); - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUSB_MCU_VENDOR_ESPRESSIF + // only start scheduler for non-espressif mcu +#ifndef ESP_PLATFORM vTaskStartScheduler(); #endif return 0; } -#if TUSB_MCU_VENDOR_ESPRESSIF -void app_main(void) -{ +#ifdef ESP_PLATFORM +void app_main(void) { main(); } #endif diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h index 6ec38b95c..b28033a0c 100644 --- a/examples/device/hid_composite_freertos/src/tusb_config.h +++ b/examples/device/hid_composite_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/midi_test_freertos/src/main.c b/examples/device/midi_test_freertos/src/main.c index dbe89080c..3e406d38d 100644 --- a/examples/device/midi_test_freertos/src/main.c +++ b/examples/device/midi_test_freertos/src/main.c @@ -40,7 +40,7 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define USBD_STACK_SIZE 4096 #else // Increase stack size when debug log is enabled @@ -95,15 +95,15 @@ int main(void) { xTaskCreate(midi_task, "midi", MIDI_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL); #endif -#if !TUSB_MCU_VENDOR_ESPRESSIF - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 +#ifndef ESP_PLATFORM + // only start scheduler for non-espressif mcu vTaskStartScheduler(); #endif return 0; } -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM void app_main(void) { main(); } diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 04d4af4e5..0406279fd 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -292,7 +292,7 @@ void led_blinking_task(void* param) { #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE #define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4) -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define USBD_STACK_SIZE 4096 int main(void); void app_main(void) { @@ -351,8 +351,8 @@ void freertos_init_task(void) { xTaskCreate(video_task, "video", VIDEO_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL); #endif - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUSB_MCU_VENDOR_ESPRESSIF + // only start scheduler for non-espressif mcu + #ifndef ESP_PLATFORM vTaskStartScheduler(); #endif } diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 6dbd6f2a5..4ba86ca65 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -58,7 +58,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c index 245e7abb8..dc616e3fa 100644 --- a/examples/device/video_capture_2ch/src/main.c +++ b/examples/device/video_capture_2ch/src/main.c @@ -300,7 +300,7 @@ void led_blinking_task(void* param) { #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE #define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4) -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define USBD_STACK_SIZE 4096 int main(void); void app_main(void) { @@ -359,8 +359,8 @@ void freertos_init_task(void) { xTaskCreate(video_task, "video", VIDEO_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL); #endif - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUSB_MCU_VENDOR_ESPRESSIF + // only start scheduler for non-espressif mcu + #ifndef ESP_PLATFORM vTaskStartScheduler(); #endif } diff --git a/examples/device/video_capture_2ch/src/tusb_config.h b/examples/device/video_capture_2ch/src/tusb_config.h index 91775a327..e84e49879 100644 --- a/examples/device/video_capture_2ch/src/tusb_config.h +++ b/examples/device/video_capture_2ch/src/tusb_config.h @@ -58,7 +58,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c index e279ad509..d99760a02 100644 --- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c +++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c @@ -27,7 +27,7 @@ #include "tusb.h" #include "bsp/board_api.h" -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CDC_STACK_SZIE 2048 #else #define CDC_STACK_SZIE (3*configMINIMAL_STACK_SIZE/2) diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index 64a108254..0bcb355ec 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -30,7 +30,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define USBH_STACK_SIZE 4096 #else // Increase stack size when debug log is enabled @@ -86,15 +86,15 @@ int main(void) { xTimerStart(blinky_tm, 0); - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUSB_MCU_VENDOR_ESPRESSIF + // only start scheduler for non-espressif mcu +#ifndef ESP_PLATFORM vTaskStartScheduler(); #endif return 0; } -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM void app_main(void) { main(); } diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index bc8887211..3cdb227e2 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -44,7 +44,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index e924a137b..7189972d6 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -268,7 +268,7 @@ void led_blinking_task(void* param) { #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define USB_STACK_SIZE 4096 #else // Increase stack size when debug log is enabled @@ -285,7 +285,7 @@ StackType_t usb_stack[USB_STACK_SIZE]; StaticTask_t usb_taskdef; #endif -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM void app_main(void) { main(); } @@ -308,8 +308,8 @@ void init_freertos_task(void) { xTaskCreate(usb_host_task, "usbh", USB_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); #endif - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUSB_MCU_VENDOR_ESPRESSIF + // only start scheduler for non-espressif mcu +#ifndef ESP_PLATFORM vTaskStartScheduler(); #endif } diff --git a/examples/host/device_info/src/tusb_config.h b/examples/host/device_info/src/tusb_config.h index e12970c12..e4ca2528e 100644 --- a/examples/host/device_info/src/tusb_config.h +++ b/examples/host/device_info/src/tusb_config.h @@ -40,7 +40,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/host/midi_rx/src/tusb_config.h b/examples/host/midi_rx/src/tusb_config.h index c9b430388..76bdf87f3 100644 --- a/examples/host/midi_rx/src/tusb_config.h +++ b/examples/host/midi_rx/src/tusb_config.h @@ -40,7 +40,7 @@ extern "C" { #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUSB_MCU_VENDOR_ESPRESSIF +#ifdef ESP_PLATFORM #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index 068dbbeb1..de0db4721 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -71,9 +71,8 @@ int main(void) } } -#if TUSB_MCU_VENDOR_ESPRESSIF -void app_main(void) -{ +#ifdef ESP_PLATFORM +void app_main(void) { main(); } #endif diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 4b8e5950f..8f2f93306 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -66,7 +66,6 @@ int sys_read(int fhdl, char *buf, size_t count) { #elif defined(LOGGER_SWO) #define ITM_BASE 0xE0000000 - #define ITM_STIM0 (*((volatile uint8_t*)(ITM_BASE + 0))) #define ITM_TER *((volatile uint32_t*)(ITM_BASE + 0xE00)) #define ITM_TCR *((volatile uint32_t*)(ITM_BASE + 0xE80)) @@ -150,6 +149,9 @@ int board_getchar(void) { return (sys_read(0, &c, 1) > 0) ? (int) c : (-1); } +void board_putchar(int c) { + sys_write(0, (const char*)&c, 1); +} uint32_t tusb_time_millis_api(void) { return board_millis(); @@ -158,7 +160,7 @@ uint32_t tusb_time_millis_api(void) { //-------------------------------------------------------------------- // FreeRTOS hooks //-------------------------------------------------------------------- -#if CFG_TUSB_OS == OPT_OS_FREERTOS && !TUSB_MCU_VENDOR_ESPRESSIF +#if CFG_TUSB_OS == OPT_OS_FREERTOS && !defined(ESP_PLATFORM) #include "FreeRTOS.h" #include "task.h" @@ -240,5 +242,4 @@ void vApplicationSetupTimerInterrupt(void) { } #endif - #endif diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index 9cdbbf0d3..328fe9363 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -41,7 +41,7 @@ extern "C" { #if CFG_TUSB_OS == OPT_OS_ZEPHYR #include #elif CFG_TUSB_OS == OPT_OS_FREERTOS - #if TUSB_MCU_VENDOR_ESPRESSIF + #ifdef ESP_PLATFORM // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -195,6 +195,7 @@ static inline void board_delay(uint32_t ms) { // stdio getchar() is blocking, this is non-blocking version int board_getchar(void); +void board_putchar(int c); #ifdef __cplusplus } diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 8f6c4bee2..2a5deed26 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -156,6 +156,10 @@ int board_getchar(void) { return getchar(); } +void board_putchar(int c) { + putchar(c); +} + //-------------------------------------------------------------------- // PHY Init //-------------------------------------------------------------------- diff --git a/tools/build.py b/tools/build.py index 6e73681fe..eaa383d73 100755 --- a/tools/build.py +++ b/tools/build.py @@ -101,10 +101,8 @@ def cmake_board(board, toolchain, build_flags_on): if build_utils.skip_example(example, board): ret[2] += 1 else: - rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G Ninja ' - f'-DBOARD={board} {build_flags}') - if rcmd.returncode == 0: - rcmd = run_cmd(f'cmake --build {build_dir}/{example}') + rcmd = run_cmd(f'idf.py -C examples/{example} -B {build_dir}/{example} -G Ninja ' + f'-DBOARD={board} {build_flags} build') ret[0 if rcmd.returncode == 0 else 1] += 1 else: rcmd = run_cmd(f'cmake examples -B {build_dir} -G Ninja -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel ' diff --git a/tools/build_utils.py b/tools/build_utils.py index 2998f940d..d80ceea7c 100755 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -26,6 +26,8 @@ def skip_example(example, board): # family.mk family_mk = family_dir / "family.mk" + if not family_mk.exists(): + family_mk = family_dir / "family.cmake" mk_contents = family_mk.read_text() # Find the mcu, first in family mk then board mk -- cgit v1.3.1 From 52f0427096a9e20b62dc3055a153a60e50317297 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 2 Jul 2025 16:34:17 +0700 Subject: remove make wrapper for rp2040/espressif --- docs/reference/getting_started.rst | 2 +- hw/bsp/rp2040/family.mk | 16 ---------------- tools/build.py | 21 +++++++++++++-------- 3 files changed, 14 insertions(+), 25 deletions(-) delete mode 100644 hw/bsp/rp2040/family.mk (limited to 'tools') diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst index ee68f6386..5b009f21e 100644 --- a/docs/reference/getting_started.rst +++ b/docs/reference/getting_started.rst @@ -82,7 +82,7 @@ You only need to do this once per family. Check out `complete list of dependenci Build Examples ^^^^^^^^^^^^^^ -Examples support make and cmake build system, though some MCU family such as espressif/rp2040 only support cmake. First change directory to an example folder. +Examples support make and cmake build system for most MCUs, however some MCU families such as espressif or rp2040 only support cmake. First change directory to an example folder. .. code-block:: bash diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk deleted file mode 100644 index 813683c54..000000000 --- a/hw/bsp/rp2040/family.mk +++ /dev/null @@ -1,16 +0,0 @@ -JLINK_DEVICE = rp2040_m0_0 -PYOCD_TARGET = rp2040 - -ifeq ($(DEBUG), 1) -CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug -endif - -$(BUILD): - cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM) - -all: $(BUILD) - $(MAKE) -C $(BUILD) - -flash: flash-pyocd -flash-uf2: - @$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2 diff --git a/tools/build.py b/tools/build.py index eaa383d73..f639fba81 100755 --- a/tools/build.py +++ b/tools/build.py @@ -154,16 +154,21 @@ def make_one_example(example, board, make_option): def make_board(board, toolchain): print(build_separator) - all_examples = get_examples(find_family(board)) + family = find_family(board); + all_examples = get_examples(family) start_time = time.monotonic() ret = [0, 0, 0] - with Pool(processes=os.cpu_count()) as pool: - pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples))) - r = pool.starmap(make_one_example, pool_args) - # sum all element of same index (column sum) - ret = list(map(sum, list(zip(*r)))) - example = 'all' - print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time) + if family == 'espressif' or family == 'rp2040': + # espressif and rp2040 do not support make, use cmake instead + final_status = 2 + else: + with Pool(processes=os.cpu_count()) as pool: + pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples))) + r = pool.starmap(make_one_example, pool_args) + # sum all element of same index (column sum) + ret = list(map(sum, list(zip(*r)))) + final_status = 0 if ret[1] == 0 else 1 + print_build_result(board, 'all', final_status, time.monotonic() - start_time) return ret -- cgit v1.3.1 From 73bf9aeaa6e1ffd453b7bffa4dd3818773e6a763 Mon Sep 17 00:00:00 2001 From: zhiqiang Date: Mon, 7 Jul 2025 14:13:15 +0800 Subject: support at32 mcu --- .../at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f402_405/at32f402_405_clock.c | 127 + hw/bsp/at32f402_405/at32f402_405_clock.h | 44 + hw/bsp/at32f402_405/at32f402_405_conf.h | 151 + hw/bsp/at32f402_405/at32f402_405_int.c | 140 + hw/bsp/at32f402_405/at32f402_405_int.h | 56 + .../boards/AT_START_F402_405/AT32F405xC_FLASH.ld | 154 + .../boards/AT_START_F402_405/AT32F405xx_v2.svd | 45983 +++++++++++++++ .../at32f402_405/boards/AT_START_F402_405/board.h | 169 + .../at32f402_405/boards/AT_START_F402_405/board.mk | 4 + hw/bsp/at32f402_405/family.c | 297 + hw/bsp/at32f402_405/family.mk | 45 + hw/bsp/at32f402_405/startup_at32f402_405.s | 486 + .../at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f403a_407/at32f403a_407_clock.c | 87 + hw/bsp/at32f403a_407/at32f403a_407_clock.h | 44 + hw/bsp/at32f403a_407/at32f403a_407_conf.h | 161 + hw/bsp/at32f403a_407/at32f403a_407_int.c | 117 + hw/bsp/at32f403a_407/at32f403a_407_int.h | 56 + .../boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld | 154 + .../boards/AT_START_F403A_407/AT32F407xx_v2.svd | 28047 +++++++++ .../boards/AT_START_F403A_407/board.h | 61 + .../boards/AT_START_F403A_407/board.mk | 4 + hw/bsp/at32f403a_407/family.c | 287 + hw/bsp/at32f403a_407/family.mk | 42 + hw/bsp/at32f403a_407/startup_at32f403a_407.s | 478 + hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f413/at32f413_clock.c | 94 + hw/bsp/at32f413/at32f413_clock.h | 44 + hw/bsp/at32f413/at32f413_conf.h | 157 + hw/bsp/at32f413/at32f413_int.c | 141 + hw/bsp/at32f413/at32f413_int.h | 56 + .../boards/AT_START_F413/AT32F413xC_FLASH.ld | 168 + .../boards/AT_START_F413/AT32F413xx_v2.svd | 23368 ++++++++ hw/bsp/at32f413/boards/AT_START_F413/board.h | 62 + hw/bsp/at32f413/boards/AT_START_F413/board.mk | 4 + hw/bsp/at32f413/family.c | 286 + hw/bsp/at32f413/family.mk | 42 + hw/bsp/at32f413/startup_at32f413.s | 431 + hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f415/at32f415_clock.c | 92 + hw/bsp/at32f415/at32f415_clock.h | 44 + hw/bsp/at32f415/at32f415_conf.h | 145 + hw/bsp/at32f415/at32f415_int.c | 119 + hw/bsp/at32f415/at32f415_int.h | 56 + .../boards/AT_START_F415/AT32F415xC_FLASH.ld | 154 + .../boards/AT_START_F415/AT32F415xx_v2.svd | 27108 +++++++++ hw/bsp/at32f415/boards/AT_START_F415/board.h | 80 + hw/bsp/at32f415/boards/AT_START_F415/board.mk | 4 + hw/bsp/at32f415/family.c | 287 + hw/bsp/at32f415/family.mk | 43 + hw/bsp/at32f415/startup_at32f415.s | 407 + hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f423/at32f423_clock.c | 128 + hw/bsp/at32f423/at32f423_clock.h | 44 + hw/bsp/at32f423/at32f423_conf.h | 153 + hw/bsp/at32f423/at32f423_int.c | 140 + hw/bsp/at32f423/at32f423_int.h | 56 + .../boards/AT_START_F423/AT32F423xC_FLASH.ld | 154 + .../boards/AT_START_F423/AT32F423xx_v2.svd | 36050 ++++++++++++ hw/bsp/at32f423/boards/AT_START_F423/board.h | 91 + hw/bsp/at32f423/boards/AT_START_F423/board.mk | 4 + hw/bsp/at32f423/family.c | 294 + hw/bsp/at32f423/family.mk | 44 + hw/bsp/at32f423/startup_at32f423.s | 483 + hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f425/at32f425_clock.c | 91 + hw/bsp/at32f425/at32f425_clock.h | 44 + hw/bsp/at32f425/at32f425_conf.h | 145 + hw/bsp/at32f425/at32f425_int.c | 140 + hw/bsp/at32f425/at32f425_int.h | 56 + .../boards/AT_START_F425/AT32F425x8_FLASH.ld | 153 + .../boards/AT_START_F425/AT32F425xx_v2.svd | 30790 ++++++++++ hw/bsp/at32f425/boards/AT_START_F425/board.h | 90 + hw/bsp/at32f425/boards/AT_START_F425/board.mk | 4 + hw/bsp/at32f425/family.c | 298 + hw/bsp/at32f425/family.mk | 43 + hw/bsp/at32f425/startup_at32f425.s | 309 + .../at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f435_437/at32f435_437_clock.c | 119 + hw/bsp/at32f435_437/at32f435_437_clock.h | 44 + hw/bsp/at32f435_437/at32f435_437_conf.h | 173 + hw/bsp/at32f435_437/at32f435_437_int.c | 120 + hw/bsp/at32f435_437/at32f435_437_int.h | 56 + .../boards/AT_START_F435_437/AT32F437xM_FLASH.ld | 154 + .../boards/AT_START_F435_437/AT32F437xx_v2.svd | 58291 +++++++++++++++++++ .../at32f435_437/boards/AT_START_F435_437/board.h | 182 + .../at32f435_437/boards/AT_START_F435_437/board.mk | 4 + hw/bsp/at32f435_437/family.c | 370 + hw/bsp/at32f435_437/family.mk | 45 + hw/bsp/at32f435_437/startup_at32f435_437.s | 569 + src/common/tusb_mcu.h | 38 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 2 + src/portable/st/stm32_fsdev/fsdev_at32.h | 224 + src/portable/synopsys/dwc2/dwc2_at32.h | 135 + src/portable/synopsys/dwc2/dwc2_common.c | 14 +- src/portable/synopsys/dwc2/dwc2_common.h | 2 + src/tusb_option.h | 9 + tools/get_deps.py | 21 + 99 files changed, 262200 insertions(+), 1 deletion(-) create mode 100644 hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_clock.c create mode 100644 hw/bsp/at32f402_405/at32f402_405_clock.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_conf.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_int.c create mode 100644 hw/bsp/at32f402_405/at32f402_405_int.h create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk create mode 100644 hw/bsp/at32f402_405/family.c create mode 100644 hw/bsp/at32f402_405/family.mk create mode 100644 hw/bsp/at32f402_405/startup_at32f402_405.s create mode 100644 hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_clock.c create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_clock.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_conf.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_int.c create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_int.h create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk create mode 100644 hw/bsp/at32f403a_407/family.c create mode 100644 hw/bsp/at32f403a_407/family.mk create mode 100644 hw/bsp/at32f403a_407/startup_at32f403a_407.s create mode 100644 hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f413/at32f413_clock.c create mode 100644 hw/bsp/at32f413/at32f413_clock.h create mode 100644 hw/bsp/at32f413/at32f413_conf.h create mode 100644 hw/bsp/at32f413/at32f413_int.c create mode 100644 hw/bsp/at32f413/at32f413_int.h create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.h create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.mk create mode 100644 hw/bsp/at32f413/family.c create mode 100644 hw/bsp/at32f413/family.mk create mode 100644 hw/bsp/at32f413/startup_at32f413.s create mode 100644 hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f415/at32f415_clock.c create mode 100644 hw/bsp/at32f415/at32f415_clock.h create mode 100644 hw/bsp/at32f415/at32f415_conf.h create mode 100644 hw/bsp/at32f415/at32f415_int.c create mode 100644 hw/bsp/at32f415/at32f415_int.h create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.h create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.mk create mode 100644 hw/bsp/at32f415/family.c create mode 100644 hw/bsp/at32f415/family.mk create mode 100644 hw/bsp/at32f415/startup_at32f415.s create mode 100644 hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f423/at32f423_clock.c create mode 100644 hw/bsp/at32f423/at32f423_clock.h create mode 100644 hw/bsp/at32f423/at32f423_conf.h create mode 100644 hw/bsp/at32f423/at32f423_int.c create mode 100644 hw/bsp/at32f423/at32f423_int.h create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.h create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.mk create mode 100644 hw/bsp/at32f423/family.c create mode 100644 hw/bsp/at32f423/family.mk create mode 100644 hw/bsp/at32f423/startup_at32f423.s create mode 100644 hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f425/at32f425_clock.c create mode 100644 hw/bsp/at32f425/at32f425_clock.h create mode 100644 hw/bsp/at32f425/at32f425_conf.h create mode 100644 hw/bsp/at32f425/at32f425_int.c create mode 100644 hw/bsp/at32f425/at32f425_int.h create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.h create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.mk create mode 100644 hw/bsp/at32f425/family.c create mode 100644 hw/bsp/at32f425/family.mk create mode 100644 hw/bsp/at32f425/startup_at32f425.s create mode 100644 hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_clock.c create mode 100644 hw/bsp/at32f435_437/at32f435_437_clock.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_conf.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_int.c create mode 100644 hw/bsp/at32f435_437/at32f435_437_int.h create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk create mode 100644 hw/bsp/at32f435_437/family.c create mode 100644 hw/bsp/at32f435_437/family.mk create mode 100644 hw/bsp/at32f435_437/startup_at32f435_437.s create mode 100644 src/portable/st/stm32_fsdev/fsdev_at32.h create mode 100644 src/portable/synopsys/dwc2/dwc2_at32.h (limited to 'tools') diff --git a/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..d86c92542 --- /dev/null +++ b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f402_405.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd new file mode 100644 index 000000000..94a12b0f4 --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd @@ -0,0 +1,45983 @@ + + + + + + + + Keil + ArteryTek + AT32F405xx_v2 + AT32F405 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 168MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + SWPEN6 + Standby wake-up pin 6 enable + 13 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000012 + + + LDOOVSEL + LDO output voltage select + 0 + 2 + read-write + + + VREXLPEN + Voltage regulator extra low power mode enable + 4 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + PLLUSTBL + PLLU clock ready flag + 26 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FP + PLLP post-division + 16 + 4 + read-write + + + PLL_FU + PLLU post-division + 20 + 3 + read-write + + + PLLU_EN + PLLU enable + 29 + 1 + read-write + + + PLLRCS + PLL reference clock select + 30 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + I2S5CLKSEL + I2S clock select + 22 + 2 + read-write + + + CLKOUTDIV1 + Clock output division1 + 27 + 3 + read-write + + + CLKOUT_SEL1 + Clock output selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + OTGHSRST + OTGHS interface reset + 29 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + QSPI1RST + QSPI1 reset + 1 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + UART7RST + UART7 reset + 30 + 1 + + + UART8RST + UART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + I2S5RST + I2S5 reset + 20 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + OTGHSPHYRST + OTGHS phy reset + 31 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + OTGHSEN + OTGHS clock enable + 29 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + QSPI1EN + QSPI1 clock enable + 1 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + USART5EN + USART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + UART7EN + UART7 clock enable + 30 + 1 + + + UART8EN + UART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + I2S5EN + I2S5 clock enable + 20 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAMLPEN + SRAM clock enable during sleep mode + 16 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + OTGHSLPEN + OTGHS clock enable during sleep mode + 29 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + QSPI1LPEN + QSPI1 clock enable during sleep mode + 1 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + USART4LPEN + USART4 clock enable during sleep mode + 19 + 1 + + + USART5LPEN + USART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + UART7LPEN + UART7 clock enable during sleep mode + 30 + 1 + + + UART8LPEN + UART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + I2S5LPEN + I2S5 clock enable during sleep mode + 20 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + OTGHSPHYLPEN + OTGHS phy clock enable during sleep mode + 31 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + OTGHS + OTGHS + OTGHS register + 0x78 + 0x20 + 0x00000000 + + + XTLSEL + PHY clock source select + 0 + 1 + read-write + + + USBHS_PHY12_SEL + USBHS phy12 select value + 3 + 2 + read-write + + + USBHS_PHY30_SEL + USBHS phy12 select value + 8 + 2 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + CLKOUT_SEL2 + Clock output select2 + 16 + 4 + read-write + + + CLKOUTDIV2 + Clock output division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + PLLU_USB48_SEL + USB clock source select + 10 + 1 + read-write + + + HICK_TO_SCLK_DIV + HICK as system clock frequency division + 16 + 3 + read-write + + + HEXT_TO_SCLK_DIV + HEXT as system clock frequency division + 19 + 3 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + TOGR + TOGR + GPIO bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + IOTB0 + toggle bit 0 + 0 + 1 + + + IOTB1 + toggle bit 1 + 1 + 1 + + + IOTB2 + toggle bit 2 + 2 + 1 + + + IOTB3 + toggle bit 3 + 3 + 1 + + + IOTB4 + toggle bit 4 + 4 + 1 + + + IOTB5 + toggle bit 5 + 5 + 1 + + + IOTB6 + toggle bit 6 + 6 + 1 + + + IOTB7 + toggle bit 7 + 7 + 1 + + + IOTB8 + toggle bit 8 + 8 + 1 + + + IOTB9 + toggle bit 9 + 9 + 1 + + + IOTB10 + toggle bit 10 + 10 + 1 + + + IOTB11 + toggle bit 11 + 11 + 1 + + + IOTB12 + toggle bit 12 + 12 + 1 + + + IOTB13 + toggle bit 13 + 13 + 1 + + + IOTB14 + toggle bit 14 + 14 + 1 + + + IOTB15 + toggle bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOF + 0x40021400 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + OTGHS_WKUP + OTGHS_WKUP interrupt connect to EXINT line20 + 76 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40026000 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026400 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR6DT + BPR6DT + Battery powered domain register + 0x64 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR7DT + BPR7DT + Battery powered domain register + 0x68 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR8DT + BPR8DT + Battery powered domain register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR9DT + BPR9DT + Battery powered domain register + 0x70 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR10DT + BPR10DT + Battery powered domain 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register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + SOFSEL + SOF Select + read-write + 2 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + I2SF5 + Serial peripheral interface + SPI + 0x40015000 + + 0x0 + 0x400 + registers + + + I2SF5 + I2SF5 global interrupt + 85 + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SFDUPEN + I2S full duplex mode enable + 13 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + MISC1 + MISC1 + MISC1 register + 0x30 + 0x20 + read-write + 00000000 + + + I2SFPCMCKSEL + I2S PCM clock edge select + 0 + 1 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CMDF + Character match detection flag + 17 + 1 + read-write + + + RTODF + Reiceiver time out detection flag + 11 + 1 + read-write + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + RTODEN + Receiver time out detection enable + 27 + 1 + + + RETODIE + Receiver time out detection interrupt enable + 26 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + CMDIE + Character match detection interrupt enable + 14 + 1 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + IDH + bit 7-4 for usart identification + 28 + 4 + + + MTF + MSB transmit first + 19 + 1 + + + DTREV + DT register polarity reverse + 18 + 1 + + + TXREV + TX polarity reverse + 17 + 1 + + + RXREV + RX polarity reverse + 16 + 1 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + IDL + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + RTOV + RTOV + Receiver time out value register + 0x1C + 0x20 + read-write + 0x0000 + + + RTOV + Receiver time out value + 0 + 24 + + + + + IFC + IFC + Interruption flag clear register + 0x20 + 0x20 + read-write + 0x0000 + + + CMDFC + Character match detection flag clear + 17 + 1 + + + RTODFC + Receiver time out detection flag clear + 11 + 1 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART4 + 0x40004C00 + + USART4 + USART4 global interrupt + 52 + + + + USART5 + 0x40005000 + + USART5 + USART5 global interrupt + 53 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + + + + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + + 20 + 1 + + + OCTESEL + Low bit of trigger event select for ordinary channels conversion + + 17 + 3 + + + PCTEN + + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADCDIV + ADC division + 16 + 4 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data 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+ Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTGFS_GLOBAL + USB on-the-go full speed + USB_OTGFS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTGFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTGFS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTGFS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + USB_OTGHS_GLOBAL + USB on the go high speed + USB_OTGHS + 0x40040000 + + 0x0 + 0x400 + registers + + + OTGHS + USB On The Go HS global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGHS control and status register + (OTGHS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGHS interrupt register + (OTGHS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGHS AHB configuration register + (OTGHS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst Length + 1 + 4 + + + DMAEN + DMA Enable + 5 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGHS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + HS timeout calibration + 0 + 3 + read-write + + + PHYIF + PHY Interface + 3 + 1 + read-write + + + PHYSEL + USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial + Transceiver Select + 6 + 1 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGHS reset register + (OTGHS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA Request Signal + 30 + 1 + read-only + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGHS core interrupt register + (OTGHS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTGHS interrupt mask register + (OTGHS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGHS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGHS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGHS Receive FIFO size register + (OTGHS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGHS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGHS non-periodic transmit FIFO/queue + status register (OTGHS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGHS general core configuration register + (OTGHS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + WAIT_CLK_RCV + Wait Clock Soure Recover + 22 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGHS Host periodic transmit FIFO size + register (OTGHS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTGHS_HOST + USB on the go high speed + USB_OTGHS + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGHS host configuration register + (OTGHS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGHS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGHS host frame number/frame time + remaining register (OTGHS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGHS_Host periodic transmit FIFO/queue + status register (OTGHS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-only + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGHS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGHS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGHS host port control and status register + (OTGHS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGHS host channel-0 characteristics + register (OTGHS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGHS host channel-1 characteristics + register (OTGHS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGHS host channel-2 characteristics + register (OTGHS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGHS host channel-3 characteristics + register (OTGHS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGHS host channel-4 characteristics + register (OTGHS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGHS host channel-5 characteristics + register (OTGHS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGHS host channel-6 characteristics + register (OTGHS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGHS host channel-7 characteristics + register (OTGHS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGHS host channel-8 characteristics + register (OTGHS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGHS host channel-9 characteristics + register (OTGHS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGHS host channel-10 characteristics + register (OTGHS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGHS host channel-7 characteristics + register (OTGHS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGHS host channel-12 characteristics + register (OTGHS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGHS host channel-13 characteristics + register (OTGHS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGHS host channel-14 characteristics + register (OTGHS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGHS host channel-15 characteristics + register (OTGHS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCSPLT0 + HCSPLT0 + Host Channel 0 Split Control Register + 0x104 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT1 + HCSPLT1 + Host Channel 1 Split Control Register + 0x124 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT2 + HCSPLT2 + Host Channel 2 Split Control Register + 0x144 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT3 + HCSPLT3 + Host Channel 3 Split Control Register + 0x164 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT4 + HCSPLT4 + Host Channel 1 Split Control Register + 0x184 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT5 + HCSPLT5 + Host Channel 5 Split Control Register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT6 + HCSPLT6 + Host Channel 6 Split Control Register + 0x1C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT7 + HCSPLT7 + Host Channel 7 Split Control Register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT8 + HCSPLT8 + Host Channel 8 Split Control Register + 0x204 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT9 + HCSPLT9 + Host Channel 9 Split Control Register + 0x224 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT10 + HCSPLT10 + Host Channel 10 Split Control Register + 0x244 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT11 + HCSPLT11 + Host Channel 11 Split Control Register + 0x264 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT12 + HCSPLT12 + Host Channel 12 Split Control Register + 0x284 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT13 + HCSPLT13 + Host Channel 13 Split Control Register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT14 + HCSPLT14 + Host Channel 14 Split Control Register + 0x2C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT15 + HCSPLT15 + Host Channel 15 Split Control Register + 0x2E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGHS host channel-0 interrupt register + (OTGHS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTGHS host channel-1 interrupt register + (OTGHS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGHS host channel-2 interrupt register + (OTGHS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGHS host channel-3 interrupt register + (OTGHS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGHS host channel-4 interrupt register + (OTGHS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGHS host channel-5 interrupt register + (OTGHS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGHS host channel-6 interrupt register + (OTGHS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGHS host channel-7 interrupt register + (OTGHS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGHS host channel-8 interrupt register + (OTGHS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGHS host channel-9 interrupt register + (OTGHS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGHS host channel-10 interrupt register + (OTGHS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGHS host channel-11 interrupt register + (OTGHS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGHS host channel-12 interrupt register + (OTGHS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGHS host channel-13 interrupt register + (OTGHS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGHS host channel-14 interrupt register + (OTGHS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGHS host channel-15 interrupt register + (OTGHS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGHS host channel-0 mask register + (OTGHS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGHS host channel-1 mask register + (OTGHS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGHS host channel-2 mask register + (OTGHS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGHS host channel-3 mask register + (OTGHS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGHS host channel-4 mask register + (OTGHS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGHS host channel-5 mask register + (OTGHS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGHS host channel-6 mask register + (OTGHS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGHS host channel-7 mask register + (OTGHS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGHS host channel-8 mask register + (OTGHS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGHS host channel-9 mask register + (OTGHS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGHS host channel-10 mask register + (OTGHS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGHS host channel-11 mask register + (OTGHS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGHS host channel-12 mask register + (OTGHS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGHS host channel-13 mask register + (OTGHS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGHS host channel-14 mask register + (OTGHS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGHS host channel-15 mask register + (OTGHS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGHS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ1 + HCTSIZ1 + OTGHS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ2 + HCTSIZ2 + OTGHS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ3 + HCTSIZ3 + OTGHS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ4 + HCTSIZ4 + OTGHS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ5 + HCTSIZ5 + OTGHS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ6 + HCTSIZ6 + OTGHS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ7 + HCTSIZ7 + OTGHS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ8 + HCTSIZ8 + OTGHS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ9 + HCTSIZ9 + OTGHS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ10 + HCTSIZ10 + OTGHS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ11 + HCTSIZ11 + OTGHS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ12 + HCTSIZ12 + OTGHS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ13 + HCTSIZ13 + OTGHS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ14 + HCTSIZ14 + OTGHS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ15 + HCTSIZ15 + OTGHS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCDMA0 + HCDMA0 + Host channel 0 DMA address + register + 0x114 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA1 + HCDMA1 + Host channel 1 DMA address + register + 0x134 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA2 + HCDMA2 + Host channel 2 DMA address + register + 0x154 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA3 + HCDMA3 + Host channel 3 DMA address + register + 0x174 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA4 + HCDMA4 + Host channel 4 DMA address + register + 0x194 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA5 + HCDMA5 + Host channel 5 DMA address + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA6 + HCDMA6 + Host channel 6 DMA address + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA7 + HCDMA7 + Host channel 7 DMA address + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA8 + HCDMA8 + Host channel 8 DMA address + register + 0x214 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA9 + HCDMA9 + Host channel 9 DMA address + register + 0x234 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA10 + HCDMA10 + Host channel 10 DMA address + register + 0x254 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA11 + HCDMA11 + Host channel 11 DMA address + register + 0x274 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA12 + HCDMA12 + Host channel 12 DMA address + register + 0x294 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA13 + HCDMA13 + Host channel 13 DMA address + register + 0x2B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA14 + HCDMA14 + Host channel 14 DMA address + register + 0x2D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA15 + HCDMA15 + Host channel 15 DMA address + register + 0x2F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + + + USB_OTGHS_DEVICE + USB on the go high speed + USB_OTGHS + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGHS device configuration register + (OTGHS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGHS device control register + (OTGHS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + DEVLNSTS + Device Line Status + 22 + 2 + + + + + DIEPMSK + DIEPMSK + OTGHS device IN endpoint common interrupt + mask register (OTGHS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + + + DOEPMSK + DOEPMSK + OTGHS device OUT endpoint common interrupt + mask register (OTGHS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + STSPHSERCVDMSK + Status Phase Received + mask + 5 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + BBLEERRMSK + Babble Error interrupt + mask + 12 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + NYETMSK + NYET interrupt + mask + 14 + 1 + + + + + DAINT + DAINT + OTGHS device all endpoints interrupt + register (OTGHS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGHS all endpoints interrupt mask register + (OTGHS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGHS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DEACHINT + DEACHINT + ODevice Each Endpoints + Interrupt Register + 0x38 + 0x20 + read-write + 0x00000000 + + + ECHINEPINT + Each IN Endpoint Interrupt + bits + 0 + 16 + + + ECHOUTEPINT + Each OUT Endpoint Interrupt + bits + 16 + 16 + + + + + DEACHINTMSK + DEACHINTMSK + Device Each Endpoints + Interrupt Mask Register + 0x3C + 0x20 + read-write + 0x00000000 + + + ECHINEPINTMSK + Each IN Endpoint Interrupt Mask + bits + 0 + 16 + + + ECHOUTEPINTMSK + Each OUT Endpoint Interrupt Mask + bits + 16 + 16 + + + + + DIEPEACHMSK1 + DIEPEACHMSK1 + Device Each IN Endpoint 1 Interrupt Register + 0x44 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + + + DOEPEACHMSK1 + DOEPEACHMSK1 + Device Each OUT Endpoint 1 Interrupt Register + 0x84 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + STSPHSERCVDMSK + Status Phase Received + mask + 5 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + BBLEERRMSK + Babble Error interrupt + mask + 12 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + NYETMSK + NYET interrupt + mask + 14 + 1 + + + + + DIEPCTL0 + DIEPCTL0 + OTGHS device control IN endpoint 0 control + register (OTGHS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL1 + DIEPCTL1 + OTGHS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGHS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGHS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGHS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGHS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGHS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGHS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGHS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGHS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 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+ Multi count + 29 + 2 + + + + + DIEPDMA0 + DIEPDMA0 + Device IN Endpoint 0 DMA Address + register + 0x114 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA1 + DIEPDMA1 + Device IN Endpoint 1 DMA Address + register + 0x134 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA2 + DIEPDMA2 + Device IN Endpoint 2 DMA Address + register + 0x154 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA3 + DIEPDMA3 + Device IN Endpoint 3 DMA Address + register + 0x174 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA4 + DIEPDMA4 + Device IN Endpoint 4 DMA Address + register + 0x194 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA5 + DIEPDMA5 + Device IN Endpoint 5 DMA Address + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA6 + DIEPDMA6 + Device IN Endpoint 6 DMA Address + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA7 + DIEPDMA7 + Device IN Endpoint 7 DMA Address + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DTXFSTS0 + DTXFSTS0 + OTGHS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGHS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGHS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGHS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGHS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGHS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGHS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGHS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGHS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGHS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGHS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGHS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGHS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGHS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGHS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPDMA0 + DOEPDMA0 + Device OUT Endpoint 0 DMA Address + register + 0x314 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA1 + DOEPDMA1 + Device OUT Endpoint 1 DMA Address + register + 0x334 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA2 + DOEPDMA2 + Device OUT Endpoint 2 DMA Address + register + 0x354 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA3 + DOEPDMA3 + Device OUT Endpoint 3 DMA Address + register + 0x374 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA4 + DOEPDMA4 + Device OUT Endpoint 4 DMA Address + register + 0x394 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA5 + DOEPDMA5 + Device OUT Endpoint 5 DMA Address + register + 0x3B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA6 + DOEPDMA6 + Device OUT Endpoint 6 DMA Address + register + 0x3D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA7 + DOEPDMA7 + Device OUT Endpoint 7 DMA Address + register + 0x3F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + + + USB_OTGHS_PWRCLK + USB on the go high speed + USB_OTGHS + 0x40040E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGHS power and clock gating control + register (OTGHS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + LOCKUP_LK + CM4F LOCKUP bit enable + 0 + 1 + + + SRAM_OPERR_LK + SRAM odd parity error lock enable + 1 + 1 + + + PVM_LK + PVM lock enable + 2 + 1 + + + SRAM_OPERR_STS + SRAM odd parity error status + 8 + 1 + + + I2S_FD + I2S full duplex config + 30 + 2 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PB10_UH + PB10 ultra high sourcing/sinking strength + 2 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + PB3_UH + PB3 ultra high sourcing/sinking strength + 0 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 5 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 5 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h new file mode 100644 index 000000000..9c07bf192 --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h @@ -0,0 +1,169 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE +//#define USB_SOF_OUTPUT_ENABLE + +// LED +#define LED_PORT GPIOF +#define LED_PIN GPIO_PINS_4 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +//USART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +//USB +#ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + #define USB_ID USB_OTG1_ID + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_FULL_SPEED_CORE_ID + #elif BOARD_TUD_RHPORT == 1 + #define USB_ID USB_OTG2_ID + #define OTG_CLOCK CRM_OTGHS_PERIPH_CLOCK + #define OTG_IRQ OTGHS_IRQn + #define OTG_IRQ_HANDLER OTGHS_IRQHandler + #define OTG_WKUP_IRQ OTGHS_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGHS_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_HIGH_SPEED_CORE_ID + #endif +#endif +#ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + #define USB_ID USB_OTG1_ID + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_FULL_SPEED_CORE_ID + #elif BOARD_TUH_RHPORT == 1 + #define USB_ID USB_OTG2_ID + #define OTG_CLOCK CRM_OTGHS_PERIPH_CLOCK + #define OTG_IRQ OTGHS_IRQn + #define OTG_IRQ_HANDLER OTGHS_IRQHandler + #define OTG_WKUP_IRQ OTGHS_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGHS_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_HIGH_SPEED_CORE_ID + #endif +#endif + +//Vbus +static inline void board_vbus_sense_init(void) +{ + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUD_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif + #ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUH_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk new file mode 100644 index 000000000..527d3706b --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F405xC_FLASH.ld + +CFLAGS += \ + -DAT32F405RCT7 diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c new file mode 100644 index 000000000..dd8e7de10 --- /dev/null +++ b/hw/bsp/at32f402_405/family.c @@ -0,0 +1,297 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f402_405_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_botton_init(void); +void usb_gpio_config(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGHS_IRQHandler(void) +{ + tusb_int_handler(1, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGHS_WKUP_IRQHandler(void) +{ + tusb_int_handler(1, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* config usb io*/ + usb_gpio_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + SysTick_Config(system_core_clock / 1000); + + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #else + NVIC_SetPriority(OTG_IRQ, 0); + #endif + + /* config led and key */ + led_and_botton_init(); + + /* config usart to printf */ + uart_print_init(115200); + // printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +void led_and_botton_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN | GPIO_PINS_5 | GPIO_PINS_6; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + gpio_bits_set(LED_PORT, GPIO_PINS_5); + gpio_bits_set(LED_PORT, GPIO_PINS_6); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + crm_pllu_output_set(TRUE); + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLLU_STABLE_FLAG) != SET){} + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_PLLU); + } +} + +void usb_gpio_config(void) +{ + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + #ifdef USB_SOF_OUTPUT_ENABLE + crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); + gpio_init_struct.gpio_pins = OTG_PIN_SOF; + gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + #endif + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + uint32_t board_millis(void) + { + return system_ticks; + } + void SVC_Handler(void) + { + } + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk new file mode 100644 index 000000000..9dbdb1a55 --- /dev/null +++ b/hw/bsp/at32f402_405/family.mk @@ -0,0 +1,45 @@ +# Submodules +AT32F402_405_SDK = hw/mcu/artery/at32f402_405 +DEPS_SUBMODULES += $(AT32F402_405_SDK) + +# AT32 SDK path +AT32F402_405_SDK_SRC = $(AT32F402_405_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F402_405 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_gpio.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_misc.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_usart.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_crm.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_acc.c \ + $(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support/system_at32f402_405.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F402_405_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f402_405.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f402_405/startup_at32f402_405.s b/hw/bsp/at32f402_405/startup_at32f402_405.s new file mode 100644 index 000000000..251ec5058 --- /dev/null +++ b/hw/bsp/at32f402_405/startup_at32f402_405.s @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file startup_at32f402_405.s + * @brief at32f402_405 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word 0 /* Reserved */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI3_IRQHandler /* SPI3 */ + .word USART4_IRQHandler /* USART4 */ + .word USART5_IRQHandler /* USART5 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word OTGHS_EP1_OUT_IRQHandler /* OTGHS endpoint1 out */ + .word OTGHS_EP1_IN_IRQHandler /* OTGHS endpoint1 in */ + .word OTGHS_WKUP_IRQHandler /* OTGHS Wakeup from suspend */ + .word OTGHS_IRQHandler /* OTGHS */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word 0 /* Reserved */ + .word I2SF5_IRQHandler /* I2SF5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QSPI1_IRQHandler /* QSPI1 */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* DMAMUX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ACC_IRQHandler /* ACC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak OTGHS_EP1_OUT_IRQHandler + .thumb_set OTGHS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTGHS_EP1_IN_IRQHandler + .thumb_set OTGHS_EP1_IN_IRQHandler,Default_Handler + + .weak OTGHS_WKUP_IRQHandler + .thumb_set OTGHS_WKUP_IRQHandler,Default_Handler + + .weak OTGHS_IRQHandler + .thumb_set OTGHS_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I2SF5_IRQHandler + .thumb_set I2SF5_IRQHandler,Default_Handler + + .weak QSPI1_IRQHandler + .thumb_set QSPI1_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..d63959c4e --- /dev/null +++ b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f403a_407.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd new file mode 100644 index 000000000..323218b23 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd @@ -0,0 +1,28047 @@ + + + + + + + + Keil + ArteryTek + AT32F407xx_v2 + AT32F407 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK2CTRL + BK2CTRL + PC Card/NAND Flash control register 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK2IS + BK2IS + FIFO status and interrupt register 2 + 0x64 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK2TMGMEM + BK2TMGMEM + Regular memory space timing register 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK2TMGATT + BK2TMGATT + special memory space timing register 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK2ECC + BK2ECC + ECC result register 2 + 0x74 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + BUSLATW2W + 0 + 8 + + + BUSLATR2R + BUSLATR2R + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + PLLRANGE + PLL clock output frequency up 72MHz or not + 31 + 1 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O + reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOERST + IO port E reset + 6 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + ADC2RST + ADC2 reset + 10 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TMR8RST + Timer8 reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + ADC3RST + ADC3 reset + 15 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + USART6RST + USART6 reset + 24 + 1 + + + UART7RST + UART7 reset + 25 + 1 + + + UART8RST + UART8 reset + 26 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + TMR6RST + Timer 6 reset + 4 + 1 + + + TMR7RST + Timer 7 reset + 5 + 1 + + + TMR12RST + Timer 12 reset + 6 + 1 + + + TMR13RST + Timer 13 reset + 7 + 1 + + + TMR14RST + Timer 14 reset + 8 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + SPI4RST + SPI4 reset + 16 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + BPRRST + Battery powered domain register reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + XMCEN + XMC clock enable + 8 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + SDIO2EN + SDIO2 clock enable + 11 + 1 + + + EMACEN + EMACEN clock enable + 14 + 1 + + + EMACTXEN + EMACEN Tx clock enable + 15 + 1 + + + EMACRXEN + EMACEN Rx clock enable + 16 + 1 + + + EMACPTPEN + EMACPTP clock enable + 28 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock + enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOEEN + I/O port E clock enable + 6 + 1 + + + ADC1EN + ADC1 clock + enable + 9 + 1 + + + ADC2EN + ADC2 clock + enable + 10 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TMR8EN + Timer8 clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + ADC3EN + ADC3 clock enable + 15 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + USART6EN + USART6 clock enable + 24 + 1 + + + UART7EN + UART7 clock enable + 25 + 1 + + + UART8EN + UART8 clock enable + 26 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPI4EN + SPI4 clock enable + 16 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + BPREN + Barrery powered domain register clock + enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + EMACRST + EMAC reset + 14 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + USBBUFS + USB buffer size selection + 24 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x50 + 0x20 + 0x00000000 + + + CLK_TO_TMR + Clock output internal connect to timer10 + 16 + 1 + read-write + + + + + MISC3 + MISC3 + Miscellaneous register3 + 0x54 + 0x20 + 0x00000000 + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + HEXTDIV + HEXT division + 12 + 2 + read-write + + + EMAC_PPS_SEL + Ethernet pulse width Select + 15 + 1 + read-write + + + + + INTMAP + INTMAP + Interrupt remap register + 0x5C + 0x20 + 0x00000000 + + + USB_INT_MAP + USBDEV interrupt remap + 0 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect + register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + HDRV + HDRV + Port configuration driver + register + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port hdrv bit 0 + 0 + 1 + + + HDRV1 + Port hdrv bit 1 + 1 + 1 + + + HDRV2 + Port hdrv bit 2 + 2 + 1 + + + HDRV3 + Port hdrv bit 3 + 3 + 1 + + + HDRV4 + Port hdrv bit 4 + 4 + 1 + + + HDRV5 + Port hdrv bit 5 + 5 + 1 + + + HDRV6 + Port hdrv bit 6 + 6 + 1 + + + HDRV7 + Port hdrv bit 7 + 7 + 1 + + + HDRV8 + Port hdrv bit 8 + 8 + 1 + + + HDRV9 + Port hdrv bit 9 + 9 + 1 + + + HDRV10 + Port hdrv bit 10 + 10 + 1 + + + HDRV11 + Port hdrv bit 11 + 11 + 1 + + + HDRV12 + Port hdrv bit 12 + 12 + 1 + + + HDRV13 + Port hdrv bit 13 + 13 + 1 + + + HDRV14 + Port hdrv bit 14 + 14 + 1 + + + HDRV15 + Port hdrv bit 15 + 15 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + (IOMUX_EVTOUT) + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + (IOMUX_REMAP) + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART2_MUX + USART2 muxing + 3 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + TMR4_MUX + TMR4 muxing + 12 + 1 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted + conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary + conversion muxing + 18 + 1 + read-write + + + ADC2_ETP_MUX + ADC2 external trigger preempted + conversion muxing + 19 + 1 + read-write + + + ADC2_ETO_MUX + ADC2 external trigger ordinary + conversion muxing + 20 + 1 + read-write + + + EMAC_MUX + Ethernet MAC muxing + 21 + 1 + read-write + + + CAN2_MUX + CAN2 muxing + 22 + 1 + read-write + + + MII_RMII_SEL_MUX + MII_RMII select muxing + 23 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI3_MUX + SPI3 muxing + 28 + 1 + read-write + + + TMR2ITR1_MUX + TMR2 internal trigger 1 + muxing + 29 + 1 + read-write + + + PTP_PPS_MUX + PTP_PPS muxing + 30 + 1 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + (IOMUX_EXINTC1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + (IOMUX_EXINTC2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + (IOMUX_EXINTC3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + (IOMUX_EXINTC4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + (IOMUX_REMAP2) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR9_MUX + TMR9 muxing + 5 + 1 + + + XMC_NADV_MUX + NADV connect/disconnect + 10 + 1 + + + SPI4_MUX + SPI4 muxing + 17 + 1 + + + I2C3_MUX + I2C3 muxing + 18 + 1 + + + SDIO2_MUX + SDIO2 muxing + 19 + 2 + + + EXT_SPIM_EN_MUX + SPIM enable muxing + 21 + 1 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + (IOMUX_REMAP3) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + (IOMUX_REMAP4) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 2 + + + TMR2ITR1_GMUX + TMR2 internal trigger 1 + muxing + 6 + 2 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR4_GMUX + TMR4 muxing + 12 + 4 + + + TMR5CH4_GMUX + TMR5 channel4 internal + muxing + 19 + 1 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + (IOMUX_REMAP5) + 0x28 + 0x20 + read-write + 0x00000000 + + + USART5_GMUX + USART5 muxing + 0 + 4 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + I2C3_GMUX + I2C3 muxing + 12 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + SPI3_GMUX + SPI3 muxing + 24 + 4 + + + SPI4_GMUX + SPI4 muxing + 28 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + (IOMUX_REMAP6) + 0x2C + 0x20 + read-write + 0x00000000 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + CAN2_GMUX + CAN2 muxing + 4 + 4 + + + SDIO2_GMUX + SDIO2 muxing + 12 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + USART2_GMUX + USART2 muxing + 20 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + (IOMUX_REMAP7) + 0x30 + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_GMUX + SPIM muxing + 0 + 3 + + + EXT_SPIM_GEN + SPIM enable + 3 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted + conversion muxing + 4 + 1 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary + conversion muxing + 5 + 1 + + + ADC2_ETP_GMUX + ADC2 external trigger preempted + conversion muxing + 8 + 1 + + + ADC2_ETO_GMUX + ADC2 external trigger ordinary + conversion muxing + 9 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + PD01_GMUX + PortD0/PortD1 mappingon + OSC_IN/OSC_OUT + 20 + 1 + + + XMC_GMUX + XMC muxing + 24 + 3 + + + XMC_NADV_GMUX + XMC_NADV muxing + 27 + 1 + + + + + REMAP8 + REMAP8 + IO MUX remap register 8 + (IOMUX_REMAP8) + 0x34 + 0x20 + read-write + 0x00000000 + + + EMAC_GMUX + Ethernet MAC muxing + 16 + 2 + + + MII_RMII_SEL_GMUX + MII_RMII select muxing + 18 + 1 + + + PTP_PPS_GMUX + PTP_PPS muxing + 19 + 1 + + + USART6_GMUX + USART6 muxing + 20 + 4 + + + UART7_GMUX + UART7 muxing + 24 + 4 + + + UART8_GMUX + UART8 muxing + 28 + 4 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + RTCALARM + RTC Alarm interrupt connect to EXINT line17 + 41 + + + USBFSWakeUp + USB Device FS Wakeup interrupt connect to EXINT line18 + 42 + + + EMAC_WKUP + EMAC_WKUP interrupt connect to EXINT line19 + 80 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global + interrupt + 75 + + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO interrupt enable register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x40023400 + + SDIO2 + SDIO2 global interrupt + 60 + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 3 + + + + CTRLH + CTRLH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + TAIEN + Time alarm interrupt enable + 1 + 1 + + + TSIEN + Time second interrupt enable + 2 + 1 + + + + + CTRLL + CTRLL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + TSF + Time second flag + 0 + 1 + read-write + + + TAF + Time alarm flag + 1 + 1 + read-write + + + OVFF + Overflow Flag + 2 + 1 + read-write + + + UPDF + RTC update finish + 3 + 1 + read-write + + + CFGEN + RTC configuration enable + 4 + 1 + read-write + + + CFGF + RTC configuration finish + 5 + 1 + read-only + + + + + DIVH + DIVH + RTC Divider Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + DIV + RTC divider high + 0 + 4 + + + + + DIVL + DIVL + RTC Divider Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + DIV + RTC divider low + 0 + 16 + + + + + DIVCNTH + DIVCNTH + RTC Divider Register High + 0x10 + 0x20 + read-write + 0x00000000 + + + DIVCNT + RTC divider register high + 0 + 4 + + + + + DIVCNTL + DIVCNTL + RTC Divider Register Low + 0x14 + 0x20 + read-write + 0x8000 + + + DIVCNT + RTC divider register low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register low + 0 + 16 + + + + + TAH + TAH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + TA + Time alarm register high + 0 + 16 + + + + + TAL + TAL + Time alarm register low + 0x24 + 0x20 + write-only + 0xFFFF + + + TA + RTC alarm register low + 0 + 16 + + + + + + + BPR + Battery powered register + BPR + 0x40006C04 + + 0x0 + 0x3FC + registers + + + + DT1 + DT1 + Battery powered domain data + register (BPR_DTx) + 0x0 + 0x20 + read-write + 0x00000000 + + + DT1 + BPR data1 + 0 + 16 + + + + + DT2 + DT2 + Battery powered domain data + register (BPR_DTx) + 0x4 + 0x20 + read-write + 0x00000000 + + + DT2 + BPR data2 + 0 + 16 + + + + + DT3 + DT3 + Battery powered domain data + register (BPR_DTx) + 0x8 + 0x20 + read-write + 0x00000000 + + + DT3 + BPR data3 + 0 + 16 + + + + + DT4 + DT4 + Battery powered domain data + register (BPR_DTx) + 0xC + 0x20 + read-write + 0x00000000 + + + DT4 + BPR data4 + 0 + 16 + + + + + DT5 + DT5 + Battery powered domain data + register (BPR_DTx) + 0x10 + 0x20 + read-write + 0x00000000 + + + DT5 + BPR data5 + 0 + 16 + + + + + DT6 + DT6 + Battery powered domain data + register (BPR_DTx) + 0x14 + 0x20 + read-write + 0x00000000 + + + DT6 + BPR data6 + 0 + 16 + + + + + DT7 + DT7 + Battery powered domain data + register (BPR_DTx) + 0x18 + 0x20 + read-write + 0x00000000 + + + DT7 + BPR data7 + 0 + 16 + + + + + DT8 + DT8 + Battery powered domain data + register (BPR_DTx) + 0x1C + 0x20 + read-write + 0x00000000 + + + DT8 + BPR data8 + 0 + 16 + + + + + DT9 + DT9 + Battery powered domain data + register (BPR_DTx) + 0x20 + 0x20 + read-write + 0x00000000 + + + DT9 + BPR data9 + 0 + 16 + + + + + DT10 + DT10 + Battery powered domain data + register (BPR_DTx) + 0x24 + 0x20 + read-write + 0x00000000 + + + DT10 + BPR data10 + 0 + 16 + + + + + DT11 + DT11 + Battery powered domain data + register (BPR_DTx) + 0x3C + 0x20 + read-write + 0x00000000 + + + DT11 + BPR data11 + 0 + 16 + + + + + DT12 + DT12 + Battery powered domain data + register (BPR_DTx) + 0x40 + 0x20 + read-write + 0x00000000 + + + DT12 + BPR data12 + 0 + 16 + + + + + DT13 + DT13 + Battery powered domain data + register (BPR_DTx) + 0x44 + 0x20 + read-write + 0x00000000 + + + DT13 + BPR data13 + 0 + 16 + + + + + DT14 + DT14 + Battery powered domain data + register (BPR_DTx) + 0x48 + 0x20 + read-write + 0x00000000 + + + DT14 + BPR data14 + 0 + 16 + + + + + DT15 + DT15 + Battery powered domain data + register (BPR_DTx) + 0x4C + 0x20 + read-write + 0x00000000 + + + DT15 + BPR data15 + 0 + 16 + + + + + DT16 + DT16 + Battery powered domain data + register (BPR_DTx) + 0x50 + 0x20 + read-write + 0x00000000 + + + DT16 + BPR data16 + 0 + 16 + + + + + DT17 + DT17 + Battery powered domain data + register (BPR_DTx) + 0x54 + 0x20 + read-write + 0x00000000 + + + DT17 + BPR data17 + 0 + 16 + + + + + DT18 + DT18 + Battery powered domain data + register (BPR_DTx) + 0x58 + 0x20 + read-write + 0x00000000 + + + DT18 + BPR data18 + 0 + 16 + + + + + DT19 + DT19 + Battery powered domain data + register (BPR_DTx) + 0x5C + 0x20 + read-write + 0x00000000 + + + DT19 + BPR data19 + 0 + 16 + + + + + DT20 + DT20 + Battery powered domain data + register (BPR_DTx) + 0x60 + 0x20 + read-write + 0x00000000 + + + DT20 + BPR data20 + 0 + 16 + + + + + DT21 + DT21 + Battery powered domain data + register (BPR_DTx) + 0x64 + 0x20 + read-write + 0x00000000 + + + DT21 + BPR data21 + 0 + 16 + + + + + DT22 + DT22 + Battery powered domain data + register (BPR_DTx) + 0x68 + 0x20 + read-write + 0x00000000 + + + DT22 + BPR data22 + 0 + 16 + + + + + DT23 + DT23 + Battery powered domain data + register (BPR_DTx) + 0x6C + 0x20 + read-write + 0x00000000 + + + DT23 + BPR data23 + 0 + 16 + + + + + DT24 + DT24 + Battery powered domain data + register (BPR_DTx) + 0x70 + 0x20 + read-write + 0x00000000 + + + DT24 + BPR data24 + 0 + 16 + + + + + DT25 + DT25 + Battery powered domain data + register (BPR_DTx) + 0x74 + 0x20 + read-write + 0x00000000 + + + DT25 + BPR data25 + 0 + 16 + + + + + DT26 + DT26 + Battery powered domain data + register (BPR_DTx) + 0x78 + 0x20 + read-write + 0x00000000 + + + DT26 + BPR data26 + 0 + 16 + + + + + DT27 + DT27 + Battery powered domain data + register (BPR_DTx) + 0x7C + 0x20 + read-write + 0x00000000 + + + DT27 + BPR data27 + 0 + 16 + + + + + DT28 + DT28 + Battery powered domain data + register (BPR_DTx) + 0x80 + 0x20 + read-write + 0x00000000 + + + DT28 + BPR data28 + 0 + 16 + + + + + DT29 + DT29 + Battery powered domain data + register (BPR_DTx) + 0x84 + 0x20 + read-write + 0x00000000 + + + DT29 + BPR data29 + 0 + 16 + + + + + DT30 + DT30 + Battery powered domain data + register (BPR_DTx) + 0x88 + 0x20 + read-write + 0x00000000 + + + DT30 + BPR data30 + 0 + 16 + + + + + DT31 + DT31 + Battery powered domain data + register (BPR_DTx) + 0x8C + 0x20 + read-write + 0x00000000 + + + DT31 + BPR data31 + 0 + 16 + + + + + DT32 + DT32 + Battery powered domain data + register (BPR_DTx) + 0x90 + 0x20 + read-write + 0x00000000 + + + DT32 + BPR data32 + 0 + 16 + + + + + DT33 + DT33 + Battery powered domain data + register (BPR_DTx) + 0x94 + 0x20 + read-write + 0x00000000 + + + DT33 + BPR data33 + 0 + 16 + + + + + DT34 + DT34 + Battery powered domain data + register (BPR_DTx) + 0x98 + 0x20 + read-write + 0x00000000 + + + DT34 + BPR data34 + 0 + 16 + + + + + DT35 + DT35 + Battery powered domain data + register (BPR_DTx) + 0x9C + 0x20 + read-write + 0x00000000 + + + DT35 + BPR data35 + 0 + 16 + + + + + DT36 + DT36 + Battery powered domain data + register (BPR_DTx) + 0xA0 + 0x20 + read-write + 0x00000000 + + + DT36 + BPR data36 + 0 + 16 + + + + + DT37 + DT37 + Battery powered domain data + register (BPR_DTx) + 0xA4 + 0x20 + read-write + 0x00000000 + + + DT37 + BPR data37 + 0 + 16 + + + + + DT38 + DT38 + Battery powered domain data + register (BPR_DTx) + 0xA8 + 0x20 + read-write + 0x00000000 + + + DT38 + BPR data38 + 0 + 16 + + + + + DT39 + DT39 + Battery powered domain data + register (BPR_DTx) + 0xAC + 0x20 + read-write + 0x00000000 + + + DT39 + BPR data39 + 0 + 16 + + + + + DT40 + DT40 + Battery powered domain data + register (BPR_DTx) + 0xB0 + 0x20 + read-write + 0x00000000 + + + DT40 + BPR data40 + 0 + 16 + + + + + DT41 + DT41 + Battery powered domain data + register (BPR_DTx) + 0xB4 + 0x20 + read-write + 0x00000000 + + + DT41 + BPR data41 + 0 + 16 + + + + + DT42 + DT42 + Battery powered domain data + register (BPR_DTx) + 0xB8 + 0x20 + read-write + 0x00000000 + + + DT42 + BPR data42 + 0 + 16 + + + + + RTCCAL + RTCCAL + RTC clock calibration register + (BPR_RTCCAL) + 0x28 + 0x20 + read-write + 0x00000000 + + + CALVAL + Calibration value + 0 + 7 + + + CALOUT + Calibration Clock Output + 7 + 1 + + + OUTEN + Output enable + 8 + 1 + + + OUTSEL + Output selection + 9 + 1 + + + CCOS + Calibration clock output selection + 10 + 1 + + + OUTM + Output mode + 11 + 1 + + + + + CTRL + CTRL + BPR control register + (BPR_CTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TPEN + Tamper pin enable + 0 + 1 + + + TPP + TAMPER pin polarity + 1 + 1 + + + + + CTRLSTS + CTRLSTS + BPR control/status register + (BPR_CTRLSTS) + 0x30 + 0x20 + 0x00000000 + + + TPEFCLR + Tamper event flag clear + 0 + 1 + write-only + + + TPIFCLR + Tamper interrupt flag clear + 1 + 1 + write-only + + + TPIEN + Tamper pin interrupt enable + 2 + 1 + read-write + + + TPEF + Tamper event flag + 8 + 1 + read-write + + + TPIF + Tamper interrupt flag + 9 + 1 + read-write + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + read-write + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-write + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + + + + + WWDT + Window watchdog + WWDT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDT + Window Watchdog interrupt + 0 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + CNT + Decrement counter + 0 + 7 + + + WWDTEN + Window watchdog enable + 7 + 1 + + + + + CFG + CFG + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WIN + Window value + 0 + 7 + + + DIV + Clock division value + 7 + 2 + + + RLDIEN + Reload counter interrupt + 9 + 1 + + + + + STS + STS + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + RLDF + Reload counter interrupt flag + 0 + 1 + + + + + + + TMR1 + Advanced timer + TIMER + 0x40012C00 + + 0x0 + 0x400 + registers + + + TMR1_BRK_TMR9 + TMR1 brake interrupt and TMR9 global + interrupt + 24 + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + TMR1_CH + TMR1 channel interrupt + 27 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode + selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C4IOS + Channel 4 idle output state + 14 + 1 + + + C3CIOS + Channel 3 complementary idle output state + 13 + 1 + + + C3IOS + Channel 3 idle output state + 12 + 1 + + + C2CIOS + Channel 2 complementary idle output state + 11 + 1 + + + C2IOS + Channel 2 idle output state + 10 + 1 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + C1INSEL + C1IN selection + 7 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + ESP + External signal polarity + 15 + 1 + + + ECMBEN + External clock mode B enable + 14 + 1 + + + ESDIV + External signal divider + 12 + 2 + + + ESF + External signal filter + 8 + 4 + + + STS + Subordinate TMR synchronization + 7 + 1 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDEN + Trigger DMA request enable + 14 + 1 + + + HALLDE + HALL DMA request enable + 13 + 1 + + + C4DEN + Channel 4 DMA request + enable + 12 + 1 + + + C3DEN + Channel 3 DMA request + enable + 11 + 1 + + + C2DEN + Channel 2 DMA request + enable + 10 + 1 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + TIEN + Trigger interrupt enable + 6 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C4IEN + Channel 4 interrupt + enable + 4 + 1 + + + C3IEN + Channel 3 interrupt + enable + 3 + 1 + + + C2IEN + Channel 2 interrupt + enable + 2 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C4RF + Channel 4 recapture flag + 12 + 1 + + + C3RF + Channel 3 recapture flag + 11 + 1 + + + C2RF + Channel 2 recapture flag + 10 + 1 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C4IF + Channel 4 interrupt flag + 4 + 1 + + + C3IF + Channel 3 interrupt flag + 3 + 1 + + + C2IF + Channel 2 interrupt flag + 2 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C4SWTR + Channel 4 event triggered by software + 4 + 1 + + + C3SWTR + Channel 3 event triggered by software + 3 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM2_OUTPUT + CM2_OUTPUT + Channel output mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + C4OSEN + Channel 4 output switch enable + 15 + 1 + + + C4OCTRL + Channel 4 output control + 12 + 3 + + + C4OBEN + Channel 4 output buffer enable + 11 + 1 + + + C4OIEN + Channel 4 output immediately enable + 10 + 1 + + + C4C + Channel 4 configure + 8 + 2 + + + C3OSEN + Channel 3 output switch enable + 7 + 1 + + + C3OCTRL + Channel 3 output control + 4 + 3 + + + C3OBEN + Channel 3 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data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + + TMR10 + General purpose timer + TIMER + 0x40015000 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + + + TMR11 + 0x40015400 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40015800 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + TMR13 + 0x40001C00 + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + + TMR14 + 0x40002000 + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RESET + I2C peripheral reset + 15 + 1 + + + SMBALERT + SMBus alert pin set + 13 + 1 + + + PECTEN + Request PEC transmission enable + 12 + 1 + + + MACKCTRL + Master receiving mode acknowledge control + 11 + 1 + + + ACKEN + Acknowledge enable + 10 + 1 + + + GENSTOP + Stop generation + 9 + 1 + + + GENSTART + Start generation + 8 + 1 + + + STRETCH + Clock stretching mode + 7 + 1 + + + GCAEN + General call address enable + 6 + 1 + + + PECEN + PEC calculation enable + 5 + 1 + + + ARPEN + SMBus address resolution protocol enable + 4 + 1 + + + SMBMODE + SMBus device mode + 3 + 1 + + + PERMODE + I2C peripheral mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + DMAEND + DMA transfer end indication + 12 + 1 + + + DMAEN + DMA transfer enable + 11 + 1 + + + DATAIEN + Data transmission interrupt enable + 10 + 1 + + + EVTIEN + Event interrupt enable + 9 + 1 + + + ERRIEN + Error interrupt enable + 8 + 1 + + + CLKFREQ + Input clock frequency + 0 + 8 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDR1MODE + Address mode + 15 + 1 + + + ADDR1 + Own address 1 + 0 + 10 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2EN + Own address 2 enable + 0 + 1 + + + + + DT + DT + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DT + data register + 0 + 8 + + + + + STS1 + STS1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + ALERTF + SMBus alert + 15 + 1 + read-write + + + TMOUT + Timeout error + 14 + 1 + read-write + + + PECERR + PEC receive error + 12 + 1 + read-write + + + OUF + Overflow or underflow + 11 + 1 + read-write + + + ACKFAIL + Acknowledge failure + 10 + 1 + read-write + + + ARLOST + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BUSERR + Bus error + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + (transmitters) + 7 + 1 + read-only + + + RDBF + Receive data buffer full + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADDRHF + address header match (Master + mode) + 3 + 1 + read-only + + + TDC + Transmit data complete + 2 + 1 + read-only + + + ADDR7F + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + STARTF + Start bit (Master mode) + 0 + 1 + read-only + + + + + STS2 + STS2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PECVAL + PEC value + 8 + 8 + + + ADDR2F + Received address 2 + 7 + 1 + + + HOSTADDRF + SMBus host address receiving + 6 + 1 + + + DEVADDRF + SMBus device address receiving + 5 + 1 + + + GCADDRF + General call address reception + 4 + 1 + + + DIRF + Transmission direction + 2 + 1 + + + BUSYF + Bus busy + 1 + 1 + + + TRMODE + Transmission mode + 0 + 1 + + + + + CLKCTRL + CLKCTRL + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + SPEEDMODE + Speed mode selection + 15 + 1 + + + DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40015C00 + + I2C3_EVT + I2C3 event interrupt + 61 + + + I2C3_ERR + I2C3 error interrupt + 62 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40004000 + + SPI4 + SPI4 global interrupt + 63 + + + + I2S2_EXT + 0x40016C00 + + + I2S3_EXT + 0x40017000 + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40016000 + + USART6 + USART6 global interrupt + 76 + + + + ADC1 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + MSSEL + Master slave mode select + 16 + 4 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC2ODT + ADC2 conversion data of ordinary channel + 16 + 16 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC2 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC3 + Analog to digital converter + ADC + 0x40013C00 + + 0x0 + 0x400 + registers + + + ADC3 + ADC3 global interrupt + 47 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + USBFS_H_CAN1_TX + CAN1 TX interrupt + 19 + + + USBFS_L_CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB2 + F3FB2 + Filter bank 3 filtrate bit register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB1 + F4FB1 + Filter bank 4 filtrate bit register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + 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data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB1 + F12FB1 + Filter bank 12 filtrate bit filtrate bit register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 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+ + + + F12FB2 + F12FB2 + Filter bank 12 filtrate bit filtrate bit register 2 + 0x2A4 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 68 + + + CAN2_RX0 + CAN2 RX0 interrupt + 69 + + + CAN2_RX1 + CAN2 RX1 interrupt + 70 + + + CAN2_SE + CAN2 SE interrupt + 71 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + DEBUG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 13 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 17 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 18 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 19 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 20 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 21 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 25 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 26 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 27 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 28 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 29 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 30 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 31 + 1 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40016400 + + UART7 + UART7 global interrupt + 77 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40016800 + + UART8 + UART8 global interrupt + 78 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + UNLOCK3 + UNLOCK3 + Unlock 3 register + 0x84 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + SELECT + SELECT + Select register + 0x88 + 0x20 + write-only + 0x00000000 + + + SELECT + spim type selection + 0 + 32 + + + + + STS3 + STS3 + Status 3 register + 0x8C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL3 + CTRL3 + Control 3 register + 0x90 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + CHPERS + Chip erase + 2 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR3 + ADDR3 + Address 3 register + 0x94 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + DA + DA + Spim decryption address + 0x98 + 0x20 + write-only + 0x00000000 + + + FDA + Flash decryption address + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + read-only + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + read-only + + + SLIB_ES + sLib end sector + 22 + 10 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting,valid input: 0~511 + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting,valid input: 0~511, 0 means no data area + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting,valid input: 0~511 + 22 + 10 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USBFS + Universal serial bus full-speed device + interface + USBFS + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EPT0 + EPT0 + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT1 + EPT1 + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT2 + EPT2 + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT3 + EPT3 + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT4 + EPT4 + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT5 + EPT5 + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT6 + EPT6 + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT7 + EPT7 + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + CTRL + CTRL + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + CSRST + Core soft reset + 0 + 1 + + + DISUSB + Disable usb phy + 1 + 1 + + + LPM + Low power mode + 2 + 1 + + + SSP + Soft suspend config + 3 + 1 + + + GRESUME + Generate resume request + 4 + 1 + + + LSOFIEN + Lost start of frame interrupt enable + 8 + 1 + + + SOFIEN + Start of frame interrupt + enable + 9 + 1 + + + RSTIEN + Bus reset interrupt enable + 10 + 1 + + + SPIEN + Bus suspend mode interrupt + enable + 11 + 1 + + + WKIEN + Wakeup/Remote wakeup interrupt enable + 12 + 1 + + + BEIEN + Bus error interrupt enable + 13 + 1 + + + UCFORIEN + USB Core fifo overrun + interrupt enable + 14 + 1 + + + TCIEN + transmission completed interrupt + enable + 15 + 1 + + + + + INTSTS + INTSTS + interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EPT_NUM + Endpoint number + 0 + 4 + + + INOUT + In/Out transaction + 4 + 1 + + + LSOF + Lost start of frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RST + Bus reset + 10 + 1 + + + SP + Bus suspend + 11 + 1 + + + WK + Wakeup + 12 + 1 + + + BE + Bus error + 13 + 1 + + + UCFOR + USB core fifo overrun memory + 14 + 1 + + + TC + transaction completed + 15 + 1 + + + + + SOFRNUM + SOFRNUM + frame number register + 0x48 + 0x20 + read-write + 0x0000 + + + SOFNUM + Start of frame number + 0 + 11 + + + LSOFNUM + Lost start of frame number + 11 + 2 + + + CLCK + Connect locked + 13 + 1 + + + DMSTS + DM status + 14 + 1 + + + DPSTS + DP status + 15 + 1 + + + + + DEVADDR + DEVADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADDR + Host assign device address + 0 + 7 + + + CEN + USB core enable + 7 + 1 + + + + + BUFTBL + BUFTBL + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTADDR + Endpoint buffer table start address + 3 + 13 + + + + + CFG + CFG + CFG control register + 0x60 + 0x20 + read-write + 0x0000 + + + PUO + DP pullup off + 1 + 1 + + + SOFOUTEN + SOF output enable + 0 + 1 + + + + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x100 + registers + + + EMAC + Ethernet mac global interrupt + 79 + + + + MACCTRL + MACCTRL + Ethernet MAC configuration register + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + DC + Deferral check + 4 + 1 + + + BL + Back-off limit + 5 + 2 + + + ACS + Automatic pad/CRC + stripping + 7 + 1 + + + DR + Disable retry + 9 + 1 + + + IPC + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + DRO + Disable receive own + 13 + 1 + + + FES + Fast EMAC speed + 14 + 1 + + + DCS + Disable carrier sense + 16 + 1 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + + + MACFRMF + MACFRMF + Ethernet MAC frame filter register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Promiscuous mode + 0 + 1 + + + HUC + Hash unicast + 1 + 1 + + + HMC + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PMC + Pass multicast + 4 + 1 + + + DBF + Disable broadcast frames + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTH + MACHTH + Ethernet MAC hash table high register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTL + MACHTL + Ethernet MAC hash table low register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIADDR + MACMIIADDR + Ethernet MAC MII address register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MII + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDT + MACMIIDT + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCTRL + MACFCTRL + Ethernet MAC flow control register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + Flow control busy/back pressure + activate + 0 + 1 + + + ETF + Enable transmit flow control + + 1 + 1 + + + ERF + Enable receive flow control + + 2 + 1 + + + DUP + Detect unicast pause frame + 3 + 1 + + + PLT + Pause low threshold + 4 + 2 + + + DZQP + Disable zero-quanta pause + 7 + 1 + + + PT + Pass time + 16 + 16 + + + + + MACVLT + MACVLT + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + ETV + Enable 12-bit VLAN tag comparison + 16 + 1 + + + + + MACRWFF + MACRWFF + Ethernet MAC remote wakeup frame filter register + 0x28 + 0x20 + read-write + 0x00000000 + + + MACPMTCTRLSTS + MACPMTCTRLSTS + Ethernet MAC PMT control and status register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + EMP + Enable magic packet + 1 + 1 + + + ERWF + Enable remote wakeup frame + 2 + 1 + + + RMP + Received magic packet + 5 + 1 + + + RRWF + Recevied remote wakeup frame + 6 + 1 + + + GUC + Global unicast + 9 + 1 + + + RWFFPR + Remote wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACISTS + MACISTS + Ethernet MAC interrupt status register + 0x38 + 0x20 + read-write + 0x00000000 + + + PIS + PMT interrupt status + 3 + 1 + + + MIS + MMC interrupt status + 4 + 1 + + + MRIS + MMC receive interrupt status + 5 + 1 + + + MTIS + MMC transmit interrupt status + 6 + 1 + + + TIS + Timestamp interrupt status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + PIM + PMT interrupt mask + 3 + 1 + + + TIM + Timestamp interrupt mask + 9 + 1 + + + + + MACA0H + MACA0H + Ethernet MAC address 0 high register + 0x40 + 0x20 + 0x0010FFFF + + + MA0H + MAC address0 high + 0 + 16 + read-write + + + AE + Address enable + 31 + 1 + read-only + + + + + MACA0L + MACA0L + Ethernet MAC address 0 low register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MA0L + MAC address0 low + 0 + 32 + + + + + MACA1H + MACA1H + Ethernet MAC address 1 high register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1L + MACA1L + Ethernet MAC address1 low register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MA1L + MAC address1 low + 0 + 32 + + + + + MACA2H + MACA2H + Ethernet MAC address 2 high register + 0x50 + 0x20 + read-write + 0x0050 + + + MA2H + MAC address 2 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2L + MACA2L + Ethernet MAC address 2 low register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MA2L + MAC address2 low + 0 + 31 + + + + + MACA3H + MACA3H + Ethernet MAC address 3 high register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3L + MACA3L + Ethernet MAC address 3 low register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MA3L + MAC address3 low + 0 + 32 + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x100 + registers + + + + MMCCTRL + MMCCTRL + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RC + Reset counter + 0 + 1 + + + SCR + Stop counter rollover + 1 + 1 + + + RR + Reset on read + 2 + 1 + + + FMC + Freeze MMC counter + 31 + 1 + + + + + MMCRI + MMCRI + Ethernet MMC receive interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCE + Received frames CRC error + 5 + 1 + + + RFAE + Received frames alignment error + 6 + 1 + + + RGUF + Received good unicast frames + 17 + 1 + + + + + MMCTI + MMCTI + Ethernet MMC transmit interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + TSCGFCI + Transmit single collision good frame + counter interrupt + 14 + 1 + + + TGFMSC + Transmit good frames more single + collision + 15 + 1 + + + TGF + Transmitted good frames + 21 + 1 + + + + + MMCRIM + MMCRIM + Ethernet MMC receive interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + RCEFCIM + Received CRC error frame counter interrupt + mask + 5 + 1 + + + RAEFACIM + Received alignment error frame alignment + counter interrupt mask + 6 + 1 + + + RUGFCIM + Received unicast good frame counter + interrupt mask + 17 + 1 + + + + + MMCTIM + MMCTIM + Ethernet MMC transmit interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSCGFCIM + Transmit single collision good frame + counter interrupt mask + 14 + 1 + + + TMCGFCIM + Transmit multiple collision good frame + counter interrupt mask + 15 + 1 + + + TGFCIM + Transmitted good frame counter interrupt + mask + 21 + 1 + + + + + MMCTFSCC + MMCTFSCC + Ethernet MMC transmitted good frames after a single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames single + collision counter + 0 + 32 + + + + + MMCTFMSCC + MMCTFMSCC + Ethernet MMC transmitted good frames after more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frame more single + collision counter + 0 + 32 + + + + + MMCTFCNT + MMCTFCNT + Ethernet MMC transmitted good frames counter register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECNT + MMCRFCECNT + Ethernet MMC received frames with CRC error counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCEC + Received frames CRC error counter + 0 + 32 + + + + + MMCRFAECNT + MMCRFAECNT + Ethernet MMC received frames with alignment error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames alignment error counter + 0 + 32 + + + + + MMCRGUFCNT + MMCRGUFCNT + MMC received good unicast frames counter register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x100 + registers + + + + PTPTSCTRL + PTPTSCTRL + Ethernet PTP time stamp control register + 0x0 + 0x20 + read-write + 0x2000 + + + TE + Timestamp enable + 0 + 1 + + + TFCU + Timestamp fine or coarse + update + 1 + 1 + + + TI + Timestamp initialize + 2 + 1 + + + TU + Timestamp update + 3 + 1 + + + TITE + Timestamp interrupt trigger + enable + 4 + 1 + + + ARU + Addend register update + 5 + 1 + + + ETAF + Enable timestamp for all frames + 8 + 1 + + + TDBRC + Timestamp digital or binary + rollover control + 9 + 1 + + + EPPV2F + Enable PTP packet processing for + version2 format + 10 + 1 + + + EPPEF + Enable processing of PTP + over EMAC frames + 11 + 1 + + + EPPFSIP6U + Enable processing of PTP frames + sent over IPv6-UDP + 12 + 1 + + + EPPFSIP4U + Enable processing of PTP frames + sent over IPv4-UDP + 13 + 1 + + + ETSFEM + Enable timestamp snapshot for + event message + 14 + 1 + + + ESFMRTM + Enable snapshot for message + relevant to master + 15 + 1 + + + SPPFTS + Select PTP packet for taking snapshot + 16 + 2 + + + EMAFPFF + Enable MAC address for PTP frame filtering + 18 + 1 + + + + + PTPSSINC + PTPSSINC + Ethernet PTP subsecond increment register + 0x4 + 0x20 + read-write + 0x00000000 + + + SSIV + Sub-second increment value + 0 + 8 + + + + + PTPTSH + PTPTSH + Ethernet PTP time stamp high register + 0x8 + 0x20 + read-only + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSL + PTPTSL + Ethernet PTP time stamp low register + 0xC + 0x20 + read-only + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSHUD + PTPTSHUD + Ethernet PTP time stamp high update register + 0x10 + 0x20 + read-write + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSLUD + PTPTSLUD + Ethernet PTP time stamp low update register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSAD + PTPTSAD + Ethernet PTP time stamp addend register + 0x18 + 0x20 + read-write + 0x00000000 + + + TAR + Timestamp addend register + 0 + 32 + + + + + PTPTTH + PTPTTH + Ethernet PTP target time high register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSR + Target time seconds register + 0 + 32 + + + + + PTPTTL + PTPTTL + Ethernet PTP target time low register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTLR + Target timestamp low register + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSO + Timestamp second overflow + 0 + 1 + + + TTTR + Timestamp target time reached + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control register + 0x2C + 0x20 + read-only + 0x00000000 + + + POFC + PPS Output frequency control + 0 + 4 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x100 + registers + + + + DMABM + DMABM + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x20101 + + + SWR + Software reset + 0 + 1 + + + DA + DMA Arbitration + 1 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + PBL + Programmable burst length + 8 + 6 + + + PR + Priority ratio + 14 + 2 + + + FB + Fixed burst + 16 + 1 + + + RDP + Rx DMA PBL + 17 + 6 + + + USP + Use separate PBL + 23 + 1 + + + PBLx8 + PNLx8 mode + 24 + 1 + + + AAB + Address-aligned beats + 25 + 1 + + + + + DMATPD + DMATPD + Ethernet DMA transmit poll demand register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPD + DMARPD + EHERNET DMA receive poll demand register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLADDR + DMARDLADDR + Ethernet DMA receive descriptor list address register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLADDR + DMATDLADDR + Ethernet DMA transmit descriptor list address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASTS + DMASTS + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TI + Transmit interrupt + 0 + 1 + read-write + + + TPS + Transmit process stopped + 1 + 1 + read-write + + + TBU + Transmit buffer unavailable + 2 + 1 + read-write + + + TJT + Transmit jabber timeout + 3 + 1 + read-write + + + OVF + Receive overflow + 4 + 1 + read-write + + + UNF + Transmit underflow + 5 + 1 + read-write + + + RI + Receive interrupt + 6 + 1 + read-write + + + RBU + Receive buffer unavailable + 7 + 1 + read-write + + + RPS + Receive process stopped + 8 + 1 + read-write + + + RWT + Receive watchdog timeout + 9 + 1 + read-write + + + ETI + Early transmit interrupt + 10 + 1 + read-write + + + FBEI + Fatal bus error interrupt + 13 + 1 + read-write + + + ERI + Early receive interrupt + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RS + Receive process state + 17 + 3 + read-only + + + TS + Transmit process state + 20 + 3 + read-only + + + EB + Error bits + 23 + 3 + read-only + + + MMI + MAC MMC interrupt + 27 + 1 + read-only + + + MPI + MAC PMT interrupt + 28 + 1 + read-only + + + TTI + Timestamp trigger interrupt + 29 + 1 + read-only + + + + + DMAOPM + DMAOPM + Ethernet DMA operation mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + SSR + Start or stop receive + 1 + 1 + + + OSF + Operate on second frame + 2 + 1 + + + RTC + Receive threshold control + 3 + 2 + + + FUGF + Forward undersized good frames + 6 + 1 + + + FEF + Forward error frames + 7 + 1 + + + SSTC + Start of stop transmission command + 13 + 1 + + + TTC + Transmit threshold control + 14 + 3 + + + FTF + Flush transmit FIFO + 20 + 1 + + + TSF + Transmit store and forward + 21 + 1 + + + DFRF + Disable flushing of received + frames + 24 + 1 + + + RSF + Receive store and forward + 25 + 1 + + + DT + Disable dropping of TCP/IP + checksum error frames + 26 + 1 + + + + + DMAIE + DMAIE + Ethernet DMA interrupt enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TSE + Transmit stopped enable + 1 + 1 + + + TUE + Transmit buffer unavailable enable + 2 + 1 + + + TJE + Transmit jabber timeout enable + 3 + 1 + + + OVE + Overflow interrupt enable + 4 + 1 + + + UNE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUE + Receive buffer unavailable enable + 7 + 1 + + + RSE + Receive stopped enable + 8 + 1 + + + RWTE + receive watchdog timeout enable + 9 + 1 + + + EIE + Early transmit interrupt enable + 10 + 1 + + + FBEE + Fatal bus error enable + 13 + 1 + + + ERE + Early receive interrupt + enable + 14 + 1 + + + AIE + Abnormal interrupt enable + 15 + 1 + + + NIE + Normal interrupt enable + 16 + 1 + + + + + DMAMFBOCNT + DMAMFBOCNT + Ethernet DMA missed frame and buffer overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames control + 0 + 16 + + + OBMFC + Overflow bit for missed frame + counter + 16 + 1 + + + OFC + Overflow frame counter + 17 + 11 + + + OBFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACTD + DMACTD + Ethernet DMA current host transmit descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address pointer + 0 + 32 + + + + + DMACRD + DMACRD + Ethernet DMA current host receive descriptor register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address pointer + 0 + 32 + + + + + DMACTBADDR + DMACTBADDR + Ethernet DMA current host transmit buffer address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address pointer + 0 + 32 + + + + + DMACRBADDR + DMACRBADDR + Ethernet DMA current host receive buffer address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address pointer + 0 + 32 + + + + + + + diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h new file mode 100644 index 000000000..55d9d05dc --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +static inline void board_vbus_sense_init(void) +{ +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk new file mode 100644 index 000000000..58b3fdb11 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F403AxG_FLASH.ld + +CFLAGS += \ + -DAT32F403ACGU7 diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c new file mode 100644 index 000000000..23798526f --- /dev/null +++ b/hw/bsp/at32f403a_407/family.c @@ -0,0 +1,287 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f403a_407_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void uart_print_init(uint32_t baudrate); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USBFS_H_CAN1_TX_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_L_CAN1_RX0_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPH_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPL_IRQHandler(void) { + tud_int_handler(0); +} +void USBFSWakeUp_IRQHandler(void) { + tud_int_handler(0); +} + +void board_init(void) +{ + system_clock_config(); + + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HICK); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + + /* enable usb clock */ + crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USBFS_H_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_L_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFSWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); + + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + default: + break; + + } + } +} + +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void board_led_write(bool state) { + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) { + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f403a_407/family.mk b/hw/bsp/at32f403a_407/family.mk new file mode 100644 index 000000000..4a1c3949c --- /dev/null +++ b/hw/bsp/at32f403a_407/family.mk @@ -0,0 +1,42 @@ +# Submodules +AT32F403A_407_SDK = hw/mcu/artery/at32f403a_407 +DEPS_SUBMODULES += $(AT32F403A_407_SDK) + +# AT32 SDK path +AT32F403A_407_SDK_SRC = $(AT32F403A_407_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F403A_407 + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_gpio.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_misc.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_usart.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_acc.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_crm.c \ + $(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support/system_at32f403a_407.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f403a_407.s + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f403a_407/startup_at32f403a_407.s b/hw/bsp/at32f403a_407/startup_at32f403a_407.s new file mode 100644 index 000000000..8bb76a062 --- /dev/null +++ b/hw/bsp/at32f403a_407/startup_at32f403a_407.s @@ -0,0 +1,478 @@ +/** + ****************************************************************************** + * @file startup_at32f403a_407.s + * @brief at32f403a_407xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_I2S2EXT_IRQHandler /* SPI2 & I2S2EXT */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ + .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ + .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word ADC3_IRQHandler /* ADC3 */ + .word XMC_IRQHandler /* XMC */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word SPI3_I2S3EXT_IRQHandler /* SPI3 & I2S3EXT */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word SDIO2_IRQHandler /* SDIO2 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word ACC_IRQHandler /* ACC */ + .word USBFS_MAPH_IRQHandler /* USB Map HP */ + .word USBFS_MAPL_IRQHandler /* USB Map LP */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + .word USART6_IRQHandler /* USART6 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word EMAC_IRQHandler /* EMAC */ + .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBFS_H_CAN1_TX_IRQHandler + .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler + + .weak USBFS_L_CAN1_RX0_IRQHandler + .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_I2S2EXT_IRQHandler + .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBFSWakeUp_IRQHandler + .thumb_set USBFSWakeUp_IRQHandler,Default_Handler + + .weak TMR8_BRK_TMR12_IRQHandler + .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler + + .weak TMR8_OVF_TMR13_IRQHandler + .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_TMR14_IRQHandler + .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak XMC_IRQHandler + .thumb_set XMC_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_I2S3EXT_IRQHandler + .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak SDIO2_IRQHandler + .thumb_set SDIO2_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak USBFS_MAPH_IRQHandler + .thumb_set USBFS_MAPH_IRQHandler,Default_Handler + + .weak USBFS_MAPL_IRQHandler + .thumb_set USBFS_MAPL_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak EMAC_IRQHandler + .thumb_set EMAC_IRQHandler,Default_Handler + + .weak EMAC_WKUP_IRQHandler + .thumb_set EMAC_WKUP_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..599d22ffc --- /dev/null +++ b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f413.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + _spim_init_base = LOADADDR(.spim); + _spim_init_length = SIZEOF(.spim); + + .spim : + { + . = ALIGN(4); + _spim_start = .; /* create a global symbol at spim start */ + *(.spim) /* .spim sections */ + *(.spim*) /* .spim* sections */ + . = ALIGN(4); + _spim_end = .; /* define a global symbols at end of spim */ + } >SPIM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd new file mode 100644 index 000000000..a4a95208e --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd @@ -0,0 +1,23368 @@ + + + + + + + + Keil + ArteryTek + AT32F413xx_v2 + AT32F413 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + PLLRANGE + PLL clock output frequency up 72MHz or not + 31 + 1 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O reset + 0 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOFRST + IO port F reset + 7 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + ADC2RST + ADC2 reset + 10 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TMR8RST + Timer8 reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + BPRRST + Battery powered domain register reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + CAN2RST + CAN2 reset + 31 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOFEN + I/O port F clock enable + 7 + 1 + + + ADC1EN + ADC1 clock enable + 9 + 1 + + + ADC2EN + ADC2 clock enable + 10 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TMR8EN + Timer8 clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + WWDTEN + Window watchdog timer clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + BPREN + Barrery powered domain register clock enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + CAN2EN + CAN2 clock enable + 31 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register 1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + USBBUFS + USB buffer size selection + 24 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register 2 + 0x50 + 0x20 + 0x00000000 + + + CLK_TO_TMR + Clock output internal connect to timer10 + 16 + 1 + read-write + + + + + MISC3 + MISC3 + Miscellaneous register 3 + 0x54 + 0x20 + 0x00000000 + + + AUTO_STEP_EN + Auto step en + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + INTMAP + INTMAP + Interrupt remap register + 0x5C + 0x20 + 0x00000000 + + + USB_INT_MAP + USBDEV interrupt remap + 0 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted + conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary + conversion muxing + 18 + 1 + read-write + + + ADC2_ETP_MUX + ADC2 external trigger preempted + conversion muxing + 19 + 1 + read-write + + + ADC2_ETO_MUX + ADC2 external trigger ordinary + conversion muxing + 20 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_EN_MUX + SPIM enable + 21 + 1 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + TMR10_GMUX + TMR10 muxing + 4 + 4 + + + TMR11_GMUX + TMR11 muxing + 8 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 3 + + + TMR2ITR1_GMUX + TMR2 internal trigger 1 muxing + 7 + 1 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR5_GMUX + TMR5 muxing + 16 + 3 + + + TMR5CH4_GMUX + TMR5 channel4 internal muxing + 19 + 1 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + 0x28 + 0x20 + read-write + 0x00000000 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + I2C2_GMUX + I2C2 muxing + 8 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + 0x2C + 0x20 + read-write + 0x00000000 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + CAN2_GMUX + CAN2 muxing + 4 + 4 + + + SDIO1_GMUX + SDIO1 muxing + 8 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + 0x30 + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_GMUX + SPIM muxing + 0 + 3 + + + EXT_SPIM_GEN + SPIM enable + 3 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted + conversion muxing + 4 + 1 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary + conversion muxing + 5 + 1 + + + ADC2_ETP_GMUX + ADC2 external trigger preempted + conversion muxing + 8 + 1 + + + ADC2_ETO_GMUX + ADC2 external trigger ordinary + conversion muxing + 9 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + PD01_GMUX + PortD0/PortD1 mappingon + OSC_IN/OSC_OUT + 20 + 1 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + RTCALARM + RTC Alarm interrupt connect to EXINT line17 + 41 + + + USBFSWakeUp + USB Device FS Wakeup interrupt connect to EXINT line18 + 42 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global interrupt + 75 + + + + SDIO + Secure digital input/output interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 3 + + + + CTRLH + CTRLH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + TAIEN + Time alarm interrupt enable + 1 + 1 + + + TSIEN + Time second interrupt enable + 2 + 1 + + + + + CTRLL + CTRLL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + TSF + Time second flag + 0 + 1 + read-write + + + TAF + Time alarm flag + 1 + 1 + read-write + + + OVFF + Overflow Flag + 2 + 1 + read-write + + + UPDF + RTC update finish + 3 + 1 + read-write + + + CFGEN + RTC configuration enable + 4 + 1 + read-write + + + CFGF + RTC configuration finish + 5 + 1 + read-only + + + + + DIVH + DIVH + RTC Divider Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + DIV + RTC divider high + 0 + 4 + + + + + DIVL + DIVL + RTC Divider Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + DIV + RTC divider low + 0 + 16 + + + + + DIVCNTH + DIVCNTH + RTC Divider Register High + 0x10 + 0x20 + read-write + 0x00000000 + + + DIVCNT + RTC divider register high + 0 + 4 + + + + + DIVCNTL + DIVCNTL + RTC Divider Register Low + 0x14 + 0x20 + read-write + 0x8000 + + + DIVCNT + RTC divider register low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register low + 0 + 16 + + + + + TAH + TAH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + TA + Time alarm register high + 0 + 16 + + + + + TAL + TAL + Time alarm register low + 0x24 + 0x20 + write-only + 0xFFFF + + + TA + RTC alarm register low + 0 + 16 + + + + + + + BPR + Battery powered register + BPR + 0x40006C04 + + 0x0 + 0x3FC + registers + + + + DT1 + DT1 + Battery powered domain data + register (BPR_DTx) + 0x0 + 0x20 + read-write + 0x00000000 + + + DT1 + BPR data1 + 0 + 16 + + + + + DT2 + DT2 + Battery powered domain data + register (BPR_DTx) + 0x4 + 0x20 + read-write + 0x00000000 + + + DT2 + BPR data2 + 0 + 16 + + + + + DT3 + DT3 + Battery powered domain data + register (BPR_DTx) + 0x8 + 0x20 + read-write + 0x00000000 + + + DT3 + BPR data3 + 0 + 16 + + + + + DT4 + DT4 + Battery powered domain data + register (BPR_DTx) + 0xC + 0x20 + read-write + 0x00000000 + + + DT4 + BPR data4 + 0 + 16 + + + + + DT5 + DT5 + Battery powered domain data + register (BPR_DTx) + 0x10 + 0x20 + read-write + 0x00000000 + + + DT5 + BPR data5 + 0 + 16 + + + + + DT6 + DT6 + Battery powered domain data + register (BPR_DTx) + 0x14 + 0x20 + read-write + 0x00000000 + + + DT6 + BPR data6 + 0 + 16 + + + + + DT7 + DT7 + Battery powered domain data + register (BPR_DTx) + 0x18 + 0x20 + read-write + 0x00000000 + + + DT7 + BPR data7 + 0 + 16 + + + + + DT8 + DT8 + Battery powered domain data + register (BPR_DTx) + 0x1C + 0x20 + read-write + 0x00000000 + + + DT8 + BPR data8 + 0 + 16 + + + + + DT9 + DT9 + Battery powered domain data + register (BPR_DTx) + 0x20 + 0x20 + read-write + 0x00000000 + + + DT9 + BPR data9 + 0 + 16 + + + + + DT10 + DT10 + Battery powered domain data + register (BPR_DTx) + 0x24 + 0x20 + read-write + 0x00000000 + + + DT10 + BPR data10 + 0 + 16 + + + + + DT11 + DT11 + Battery powered domain data + register (BPR_DTx) + 0x3C + 0x20 + read-write + 0x00000000 + + + DT11 + BPR data11 + 0 + 16 + + + + + DT12 + DT12 + Battery powered domain data + register (BPR_DTx) + 0x40 + 0x20 + read-write + 0x00000000 + + + DT12 + BPR data12 + 0 + 16 + + + + + DT13 + DT13 + Battery powered domain data + register (BPR_DTx) + 0x44 + 0x20 + read-write + 0x00000000 + + + DT13 + BPR data13 + 0 + 16 + + + + + DT14 + DT14 + Battery powered domain data + register (BPR_DTx) + 0x48 + 0x20 + read-write + 0x00000000 + + + DT14 + BPR data14 + 0 + 16 + + + + + DT15 + DT15 + Battery powered domain data + register (BPR_DTx) + 0x4C + 0x20 + read-write + 0x00000000 + + + DT15 + BPR data15 + 0 + 16 + + + + + DT16 + DT16 + Battery powered domain data + register (BPR_DTx) + 0x50 + 0x20 + read-write + 0x00000000 + + + DT16 + BPR data16 + 0 + 16 + + + + + DT17 + DT17 + Battery powered domain data + register (BPR_DTx) + 0x54 + 0x20 + read-write + 0x00000000 + + + DT17 + BPR data17 + 0 + 16 + + + + + DT18 + DT18 + Battery powered domain data + register (BPR_DTx) + 0x58 + 0x20 + read-write + 0x00000000 + + + DT18 + BPR data18 + 0 + 16 + + + + + DT19 + DT19 + Battery powered domain data + register (BPR_DTx) + 0x5C + 0x20 + read-write + 0x00000000 + + + DT19 + BPR data19 + 0 + 16 + + + + + DT20 + DT20 + Battery powered domain data + register (BPR_DTx) + 0x60 + 0x20 + read-write + 0x00000000 + + + DT20 + BPR data20 + 0 + 16 + + + + + DT21 + DT21 + Battery powered domain data + register (BPR_DTx) + 0x64 + 0x20 + read-write + 0x00000000 + + + DT21 + BPR data21 + 0 + 16 + + + + + DT22 + DT22 + Battery powered domain data + register (BPR_DTx) + 0x68 + 0x20 + read-write + 0x00000000 + + + DT22 + BPR data22 + 0 + 16 + + + + + DT23 + DT23 + Battery powered domain data + register (BPR_DTx) + 0x6C + 0x20 + read-write + 0x00000000 + + + DT23 + BPR data23 + 0 + 16 + + + + + DT24 + DT24 + Battery powered domain data + register (BPR_DTx) + 0x70 + 0x20 + read-write + 0x00000000 + + + DT24 + BPR data24 + 0 + 16 + + + + + DT25 + DT25 + Battery powered domain data + register (BPR_DTx) + 0x74 + 0x20 + read-write + 0x00000000 + + + DT25 + BPR data25 + 0 + 16 + + + + + DT26 + DT26 + Battery powered domain data + register (BPR_DTx) + 0x78 + 0x20 + read-write + 0x00000000 + + + DT26 + BPR data26 + 0 + 16 + + + + + DT27 + DT27 + Battery powered domain data + register (BPR_DTx) + 0x7C + 0x20 + read-write + 0x00000000 + + + DT27 + BPR data27 + 0 + 16 + + + + + DT28 + DT28 + Battery powered domain data + register (BPR_DTx) + 0x80 + 0x20 + read-write + 0x00000000 + + + DT28 + BPR data28 + 0 + 16 + + + + + DT29 + DT29 + Battery powered domain data + register (BPR_DTx) + 0x84 + 0x20 + read-write + 0x00000000 + + + DT29 + BPR data29 + 0 + 16 + + + + + DT30 + DT30 + Battery powered domain data + register (BPR_DTx) + 0x88 + 0x20 + read-write + 0x00000000 + + + DT30 + BPR data30 + 0 + 16 + + + + + DT31 + DT31 + Battery powered domain data + register (BPR_DTx) + 0x8C + 0x20 + read-write + 0x00000000 + + + DT31 + BPR data31 + 0 + 16 + + + + + DT32 + DT32 + Battery powered domain data + register (BPR_DTx) + 0x90 + 0x20 + read-write + 0x00000000 + + + DT32 + BPR data32 + 0 + 16 + + + + + DT33 + DT33 + Battery powered domain data + register (BPR_DTx) + 0x94 + 0x20 + read-write + 0x00000000 + + + DT33 + BPR data33 + 0 + 16 + + + + + DT34 + DT34 + Battery powered domain data + register (BPR_DTx) + 0x98 + 0x20 + read-write + 0x00000000 + + + DT34 + BPR data34 + 0 + 16 + + + + + DT35 + DT35 + Battery powered domain data + register (BPR_DTx) + 0x9C + 0x20 + read-write + 0x00000000 + + + DT35 + BPR data35 + 0 + 16 + + + + + DT36 + DT36 + Battery powered domain data + register (BPR_DTx) + 0xA0 + 0x20 + read-write + 0x00000000 + + + DT36 + BPR data36 + 0 + 16 + + + + + DT37 + DT37 + Battery powered domain data + register (BPR_DTx) + 0xA4 + 0x20 + read-write + 0x00000000 + + + DT37 + BPR data37 + 0 + 16 + + + + + DT38 + DT38 + Battery powered domain data + register (BPR_DTx) + 0xA8 + 0x20 + read-write + 0x00000000 + + + DT38 + BPR data38 + 0 + 16 + + + + + DT39 + DT39 + Battery powered domain data + register (BPR_DTx) + 0xAC + 0x20 + read-write + 0x00000000 + + + DT39 + BPR data39 + 0 + 16 + + + + + DT40 + DT40 + Battery powered domain data + register (BPR_DTx) + 0xB0 + 0x20 + read-write + 0x00000000 + + + DT40 + BPR data40 + 0 + 16 + + + + + DT41 + DT41 + Battery powered domain data + register (BPR_DTx) + 0xB4 + 0x20 + read-write + 0x00000000 + + + DT41 + BPR data41 + 0 + 16 + + + + + DT42 + DT42 + Battery powered domain data + register (BPR_DTx) + 0xB8 + 0x20 + read-write + 0x00000000 + + + DT42 + BPR data42 + 0 + 16 + + + + + RTCCAL + RTCCAL + RTC clock calibration register + (BPR_RTCCAL) + 0x28 + 0x20 + read-write + 0x00000000 + + + CALVAL + Calibration value + 0 + 7 + + + CALOUT + Calibration Clock Output + 7 + 1 + + + OUTEN + Output enable + 8 + 1 + + + OUTSEL + Output selection + 9 + 1 + + + + + CTRL + CTRL + BPR control register + (BPR_CTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TPEN + Tamper pin enable + 0 + 1 + + + TPP + TAMPER pin polarity + 1 + 1 + + + + + CTRLSTS + CTRLSTS + BPR control/status register + (BPR_CTRLSTS) + 0x30 + 0x20 + 0x00000000 + + + TPEFCLR + Tamper event flag clear + 0 + 1 + write-only + + + TPIFCLR + Tamper interrupt flag clear + 1 + 1 + write-only + + + TPIEN + Tamper pin interrupt enable + 2 + 1 + read-write + + + TPEF + Tamper event flag + 8 + 1 + read-write + + + TPIF + Tamper interrupt flag + 9 + 1 + read-write + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + read-write + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-write + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + + + + + WWDT + Window watchdog + WWDT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDT + Window Watchdog interrupt + 0 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + CNT + Decrement counter + 0 + 7 + + + WWDTEN + Window watchdog enable + 7 + 1 + + + + + CFG + CFG + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WIN + Window value + 0 + 7 + + + DIV + Clock division value + 7 + 2 + + + RLDIEN + Reload counter interrupt + 9 + 1 + + + + + STS + STS + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + RLDF + Reload counter interrupt flag + 0 + 1 + + + + + + + TMR1 + Advanced timer + TIMER + 0x40012C00 + + 0x0 + 0x400 + registers + + + TMR1_BRK_TMR9 + TMR1 brake interrupt and TMR9 global + interrupt + 24 + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + TMR1_CH + TMR1 channel interrupt + 27 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode + selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C4IOS + Channel 4 idle output state + 14 + 1 + + + C3CIOS + Channel 3 complementary idle output state + 13 + 1 + + + C3IOS + Channel 3 idle output state + 12 + 1 + + + C2CIOS + Channel 2 complementary idle output state + 11 + 1 + + + C2IOS + Channel 2 idle output state + 10 + 1 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + C1INSEL + C1IN selection + 7 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + ESP + External signal polarity + 15 + 1 + + + ECMBEN + External clock mode B enable + 14 + 1 + + + ESDIV + External signal divider + 12 + 2 + + + ESF + External signal filter + 8 + 4 + + + STS + Subordinate TMR synchronization + 7 + 1 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDEN + Trigger DMA request enable + 14 + 1 + + + HALLDE + HALL DMA request enable + 13 + 1 + + + C4DEN + Channel 4 DMA request + enable + 12 + 1 + + + C3DEN + Channel 3 DMA request + enable + 11 + 1 + + + C2DEN + Channel 2 DMA request + enable + 10 + 1 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + TIEN + Trigger interrupt enable + 6 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C4IEN + Channel 4 interrupt + enable + 4 + 1 + + + C3IEN + Channel 3 interrupt + enable + 3 + 1 + + + C2IEN + Channel 2 interrupt + enable + 2 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C4RF + Channel 4 recapture flag + 12 + 1 + + + C3RF + Channel 3 recapture flag + 11 + 1 + + + C2RF + Channel 2 recapture flag + 10 + 1 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C4IF + Channel 4 interrupt flag + 4 + 1 + + + C3IF + Channel 3 interrupt flag + 3 + 1 + + + C2IF + Channel 2 interrupt flag + 2 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C4SWTR + Channel 4 event triggered by software + 4 + 1 + + + C3SWTR + Channel 3 event triggered by software + 3 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM2_OUTPUT + CM2_OUTPUT + Channel output mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + C4OSEN + Channel 4 output switch enable + 15 + 1 + + + C4OCTRL + Channel 4 output control + 12 + 3 + + + C4OBEN + Channel 4 output buffer enable + 11 + 1 + + + C4OIEN + Channel 4 output immediately enable + 10 + 1 + + + C4C + Channel 4 configure + 8 + 2 + + + C3OSEN + Channel 3 output switch enable + 7 + 1 + + + C3OCTRL + Channel 3 output control + 4 + 3 + + + C3OBEN + Channel 3 output buffer enable + 3 + 1 + + + C3OIEN + Channel 3 output immediately enable + 2 + 1 + + + C3C + Channel 3 configure + 0 + 2 + + + + + CM2_INPUT + CM2_INPUT + Channel input mode register 2 + CM2_OUTPUT + 0x1C + 0x20 + read-write + 0x00000000 + + + C4DF + Channel 4 digital filter + 12 + 4 + + + C4IDIV + Channel 4 input divider + 10 + 2 + + + C4C + Channel 4 configure + 8 + 2 + + + C3DF + Channel 3 digital filter + 4 + 4 + + + C3IDIV + Channel 3 input divider + 2 + 2 + + + C3C + Channel 3 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C4P + Channel 4 Polarity + 13 + 1 + + + C4EN + Channel 4 enable + 12 + 1 + + + C3CP + Channel 3 complementary polarity + 11 + 1 + + + C3CEN + Channel 3 complementary enable + 10 + 1 + + + C3P + Channel 3 Polarity + 9 + 1 + + + C3EN + Channel 3 enable + 8 + 1 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + C3DT + C3DT + Channel 3 data register + 0x3C + 0x20 + read-write + 0x00000000 + + + C3DT + Channel 3 data register + 0 + 16 + + + + + C4DT + C4DT + Channel 4 data register + 0x40 + 0x20 + read-write + 0x00000000 + + + C4DT + Channel 4 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR8 + 0x40013400 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 + + + TMR8_CH + TMR8 channel interrupt + 46 + + + + TMR2 + General purpose timer + TIMER + 0x40000000 + + 0x0 + 0x400 + registers + + + TMR2 + TMR2 global interrupt + 28 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PMEN + Plus Mode Enable + 10 + 1 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode + selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control 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8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RESET + I2C peripheral reset + 15 + 1 + + + SMBALERT + SMBus alert pin set + 13 + 1 + + + PECTEN + Request PEC transmission enable + 12 + 1 + + + MACKCTRL + Master receiving mode acknowledge control + 11 + 1 + + + ACKEN + Acknowledge enable + 10 + 1 + + + GENSTOP + Stop generation + 9 + 1 + + + GENSTART + Start generation + 8 + 1 + + + STRETCH + Clock stretching mode + 7 + 1 + + + GCAEN + General call address enable + 6 + 1 + + + PECEN + PEC calculation enable + 5 + 1 + + + ARPEN + SMBus address resolution protocol enable + 4 + 1 + + + SMBMODE + SMBus device mode + 3 + 1 + + + PERMODE + I2C peripheral mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + DMAEND + DMA transfer end indication + 12 + 1 + + + DMAEN + DMA transfer enable + 11 + 1 + + + DATAIEN + Data transmission interrupt enable + 10 + 1 + + + EVTIEN + Event interrupt enable + 9 + 1 + + + ERRIEN + Error interrupt enable + 8 + 1 + + + CLKFREQ + Input clock frequency + 0 + 8 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDR1MODE + Address mode + 15 + 1 + + + ADDR1 + Own address 1 + 0 + 10 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2EN + Own address 2 enable + 0 + 1 + + + + + DT + DT + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DT + data register + 0 + 8 + + + + + STS1 + STS1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + ALERTF + SMBus alert + 15 + 1 + read-write + + + TMOUT + Timeout error + 14 + 1 + read-write + + + PECERR + PEC receive error + 12 + 1 + read-write + + + OUF + Overflow or underflow + 11 + 1 + read-write + + + ACKFAIL + Acknowledge failure + 10 + 1 + read-write + + + ARLOST + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BUSERR + Bus error + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + (transmitters) + 7 + 1 + read-only + + + RDBF + Receive data buffer full + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADDRHF + address header match (Master + mode) + 3 + 1 + read-only + + + TDC + Transmit data complete + 2 + 1 + read-only + + + ADDR7F + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + STARTF + Start bit (Master mode) + 0 + 1 + read-only + + + + + STS2 + STS2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PECVAL + PEC value + 8 + 8 + + + ADDR2F + Received address 2 + 7 + 1 + + + HOSTADDRF + SMBus host address receiving + 6 + 1 + + + DEVADDRF + SMBus device address receiving + 5 + 1 + + + GCADDRF + General call address reception + 4 + 1 + + + DIRF + Transmission direction + 2 + 1 + + + BUSYF + Bus busy + 1 + 1 + + + TRMODE + Transmission mode + 0 + 1 + + + + + CLKCTRL + CLKCTRL + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + SPEEDMODE + Speed mode selection + 15 + 1 + + + DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + ADC1 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + MSSEL + Master slave mode select + 16 + 4 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC2ODT + ADC2 conversion data of ordinary channel + 16 + 16 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC2 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + USBFS_H_CAN1_TX + CAN1 TX interrupt + 19 + + + USBFS_L_CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + 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0x00000000 + + + FDA + Flash decryption address + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + read-only + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + read-only + + + SLIB_ES + sLib end sector + 22 + 10 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 7 + + + CRC_SN + CRC sector numbler + 7 + 7 + + + CRC_STRT + CRC start + 14 + 1 + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USBFS + Universal serial bus full-speed device + interface + USBFS + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EPT0 + EPT0 + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT1 + EPT1 + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT2 + EPT2 + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT3 + EPT3 + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT4 + EPT4 + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT5 + EPT5 + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT6 + EPT6 + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT7 + EPT7 + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + CTRL + CTRL + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + CSRST + Core soft reset + 0 + 1 + + + DISUSB + Disable usb phy + 1 + 1 + + + LPM + Low power mode + 2 + 1 + + + SSP + Soft suspend config + 3 + 1 + + + GRESUME + Generate resume request + 4 + 1 + + + LSOFIEN + Lost start of frame interrupt enable + 8 + 1 + + + SOFIEN + Start of frame interrupt + enable + 9 + 1 + + + RSTIEN + Bus reset interrupt enable + 10 + 1 + + + SPIEN + Bus suspend mode interrupt + enable + 11 + 1 + + + WKIEN + Wakeup/Remote wakeup interrupt enable + 12 + 1 + + + BEIEN + Bus error interrupt enable + 13 + 1 + + + UCFORIEN + USB Core fifo overrun + interrupt enable + 14 + 1 + + + TCIEN + transmission completed interrupt + enable + 15 + 1 + + + + + INTSTS + INTSTS + interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EPT_NUM + Endpoint number + 0 + 4 + + + INOUT + In/Out transaction + 4 + 1 + + + LSOF + Lost start of frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RST + Bus reset + 10 + 1 + + + SP + Bus suspend + 11 + 1 + + + WK + Wakeup + 12 + 1 + + + BE + Bus error + 13 + 1 + + + UCFOR + USB core fifo overrun memory + 14 + 1 + + + TC + transaction completed + 15 + 1 + + + + + SOFRNUM + SOFRNUM + frame number register + 0x48 + 0x20 + read-write + 0x0000 + + + SOFNUM + Start of frame number + 0 + 11 + + + LSOFNUM + Lost start of frame number + 11 + 2 + + + CLCK + Connect locked + 13 + 1 + + + DMSTS + DM status + 14 + 1 + + + DPSTS + DP status + 15 + 1 + + + + + DEVADDR + DEVADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADDR + Host assign device address + 0 + 7 + + + CEN + USB core enable + 7 + 1 + + + + + BUFTBL + BUFTBL + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTADDR + Endpoint buffer table start address + 3 + 13 + + + + + CFG + CFG + CFG control register + 0x60 + 0x20 + read-write + 0x0000 + + + SOFOUTEN + SOF output enable + 0 + 1 + + + + + + + diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.h b/hw/bsp/at32f413/boards/AT_START_F413/board.h new file mode 100644 index 000000000..f0bf0e4ae --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +static inline void board_vbus_sense_init(void) +{ + +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.mk b/hw/bsp/at32f413/boards/AT_START_F413/board.mk new file mode 100644 index 000000000..28351265d --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F413xC_FLASH.ld + +CFLAGS += \ + -DAT32F413RCT7 diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c new file mode 100644 index 000000000..a38fe450e --- /dev/null +++ b/hw/bsp/at32f413/family.c @@ -0,0 +1,286 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f413_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void uart_print_init(uint32_t baudrate); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USBFS_H_CAN1_TX_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_L_CAN1_RX0_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPH_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPL_IRQHandler(void) { + tud_int_handler(0); +} +void USBFSWakeUp_IRQHandler(void) { + tud_int_handler(0); +} + +void board_init(void) +{ + system_clock_config(); + + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HICK); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + + /* enable usb clock */ + crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USBFS_H_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_L_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFSWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); + + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + default: + break; + } + } +} + +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void board_led_write(bool state) { + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) { + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f413/family.mk b/hw/bsp/at32f413/family.mk new file mode 100644 index 000000000..c56d1064c --- /dev/null +++ b/hw/bsp/at32f413/family.mk @@ -0,0 +1,42 @@ +# Submodules +AT32F413_SDK = hw/mcu/artery/at32f413 +DEPS_SUBMODULES += $(AT32F413_SDK) + +# AT32 SDK path +AT32F413_SDK_SRC = $(AT32F413_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F413 + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_gpio.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_misc.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_usart.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_acc.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_crm.c \ + $(AT32F413_SDK_SRC)/cmsis/cm4/device_support/system_at32f413.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F413_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f413.s + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f413/startup_at32f413.s b/hw/bsp/at32f413/startup_at32f413.s new file mode 100644 index 000000000..4fc1f2a86 --- /dev/null +++ b/hw/bsp/at32f413/startup_at32f413.s @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file startup_at32f413.s + * @brief at32f413xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TMR8_BRK_IRQHandler /* TMR8 Brake */ + .word TMR8_OVF_IRQHandler /* TMR8 Overflow */ + .word TMR8_TRG_HALL_IRQHandler /* TMR8 Trigger and hall */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word 0 /* Reserved */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word ACC_IRQHandler /* ACC */ + .word USBFS_MAPH_IRQHandler /* USB Map HP */ + .word USBFS_MAPL_IRQHandler /* USB Map LP */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBFS_H_CAN1_TX_IRQHandler + .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler + + .weak USBFS_L_CAN1_RX0_IRQHandler + .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBFSWakeUp_IRQHandler + .thumb_set USBFSWakeUp_IRQHandler,Default_Handler + + .weak TMR8_BRK_IRQHandler + .thumb_set TMR8_BRK_IRQHandler,Default_Handler + + .weak TMR8_OVF_IRQHandler + .thumb_set TMR8_OVF_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_IRQHandler + .thumb_set TMR8_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak USBFS_MAPH_IRQHandler + .thumb_set USBFS_MAPH_IRQHandler,Default_Handler + + .weak USBFS_MAPL_IRQHandler + .thumb_set USBFS_MAPL_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..73889ebf9 --- /dev/null +++ b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f415.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd new file mode 100644 index 000000000..cd22346c7 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd @@ -0,0 +1,27108 @@ + + + + + + + + Keil + ArteryTek + AT32F415xx_v2 + AT32F415 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 150MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control register + (PWC_CTRLST) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O + reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOFRST + IO port F reset + 7 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + CMPRST + Comparator reset + 9 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 12 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock + enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOFEN + I/O port F clock enable + 7 + 1 + + + ADC1EN + ADC1 clock + enable + 9 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + CMPEN + Comparator clock enable + 9 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 12 + 1 + read-write + + + + + PLL + PLL + PLL configuration register + (RCC_PLL) + 0x2C + 0x20 + 0x00001F10 + + + PLL_FR + PLL_FR + 0 + 3 + read-write + + + PLL_MS + PLL_MS + 4 + 4 + read-write + + + PLL_NS + PLL_NS + 8 + 9 + read-write + + + PLL_FREF + PLL entry clock reference frequency + 24 + 3 + read-write + + + PLLCFGEN + PLL config enable + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + OTG_EXTCTRL + OTG_EXTCTRL + OTGFS external ctrl register1 + 0x44 + 0x20 + 0x00000000 + + + USBDIV_RST + USB divider reset + 30 + 1 + read-write + + + EP3_RMPEN + OTGFS end-point 3 remap enable + 31 + 1 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x54 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect + register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOF + 0x40011C00 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + (IOMUX_EVTOUT) + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary conversion muxing + 18 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + (IOMUX_EXINTC1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + (IOMUX_EXINTC2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + (IOMUX_EXINTC3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + (IOMUX_EXINTC4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + 0x1C + 0x20 + write-only + 0x00000000 + + + CMP_MUX + CMP internal muxing + 26 + 2 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR11_GMUX + TMR11 muxing + 8 + 4 + + + TMR10_GMUX + TMR10 muxing + 4 + 4 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR5CH4_GMUX + TMR5CH4 muxing + 19 + 1 + + + TMR5_GMUX + TMR5 muxing + 16 + 3 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 3 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + 0x28 + 0x20 + read-write + 0x00000000 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + I2C2_GMUX + I2C2 muxing + 8 + 4 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + 0x2C + 0x20 + read-write + 0x00000000 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + SDIO1_GMUX + SDIO1 muxing + 8 + 4 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + 0x30 + 0x20 + read-write + 0x00000000 + + + PD01_GMUX + PortD0/PortD1 muxing on OSC_IN/OSC_OUT + 20 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary conversion muxing + 5 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted conversion muxing + 4 + 1 + + + + + REMAP8 + REMAP8 + IO MUX remap register 8 + 0x34 + 0x20 + read-write + 0x00000000 + + + TMR3_CH1_CMP_GMUX + TMR3 CH1 CMP muxing + 6 + 2 + + + TMR2_CH4_CMP_GMUX + TMR2 CH4 CMP muxing + 4 + 2 + + + TMR1_CH1_CMP_GMUX + TMR1 CH1 CMP muxing + 2 + 2 + + + TMR1_BK1_CMP_GMUX + TMR1 BK1 CMP muxing + 0 + 2 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + PVM + PVD interrupt + 1 + + + ERTC + ERTC interrupt + 3 + + + TAMPER + Tamper interrupt + 2 + + + ERTCAlarm + ERTCAlarm interrupt + 41 + + + CMP1 + CMP1 interrupt + 70 + + + CMP2 + CMP2 interrupt + 71 + + + EXTINT0 + EXTI Line0 interrupt + 6 + + + EXTINT1 + EXTI Line1 interrupt + 7 + + + EXTINT2 + EXTI Line2 interrupt + 8 + + + EXTINT3 + EXTI Line3 interrupt + 9 + + + EXTINT4 + EXTI Line4 interrupt + 10 + + + EXTINT9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTINT15_10 + EXTI Line[15:10] interrupts + 40 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global + interrupt + 75 + + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + POWER + POWER + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SDI clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKPSC + Clock divide factor + 0 + 8 + + + CLKEN + Clock enable bit + 8 + 1 + + + PWRSVG + Power saving configuration + bit + 9 + 1 + + + BYPS + Clock divider bypass enable + bit + 10 + 1 + + + BUSWIDTH + Wide bus mode enable bit + 11 + 2 + + + CLKEDG + SDIO_CK dephasing selection + bit + 13 + 1 + + + FLWCTRLEN + HW Flow Control enable + 14 + 1 + + + CLKPSC98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARG + ARG + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARG + Command argument + 0 + 32 + + + + + CMD + CMD + SDIO command register + (SDIO_CMD) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + WAITRESP + 6 + 2 + + + INTWT + WAITINT + 8 + 1 + + + PNDWT + WAITPEND + 9 + 1 + + + CMDMEN + CPSMEN + 10 + 1 + + + SDIOSUSP + SDIOSuspend + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = DATATIME: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + SDIOEN + SDIOEN + 11 + 1 + + + + + DTCNTR + DTCNTR + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + CCRCFAIL + 0 + 1 + + + DTFAIL + DCRCFAIL + 1 + 1 + + + CMDTIMEOUT + CTIMEOUT + 2 + 1 + + + DTTIMEOUT + DTIMEOUT + 3 + 1 + + + TXERRU + TXUNDERR + 4 + 1 + + + RXERRO + RXOVERR + 5 + 1 + + + CMDRSPCMPL + CMDREND + 6 + 1 + + + CMDCMPL + CMDSENT + 7 + 1 + + + DTCMPL + DATAEND + 8 + 1 + + + SBITERR + STBITERR + 9 + 1 + + + DTBLKCMPL + DBCKEND + 10 + 1 + + + DOCMD + CMDACT + 11 + 1 + + + DOTX + TXACT + 12 + 1 + + + DORX + RXACT + 13 + 1 + + + TXBUF_H + TXFIFOHE + 14 + 1 + + + RXBUF_H + RXFIFOHF + 15 + 1 + + + TXBUF_F + TXFIFOF + 16 + 1 + + + RXBUF_F + RXFIFOF + 17 + 1 + + + TXBUF_E + TXFIFOE + 18 + 1 + + + RXBUF_E + RXFIFOE + 19 + 1 + + + TXBUF + TXDAVL + 20 + 1 + + + RXBUF + RXDAVL + 21 + 1 + + + SDIOIF + SDIOIT + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + CCRCFAILC + 0 + 1 + + + DTFAIL + DCRCFAILC + 1 + 1 + + + CMDTIMEOUT + CTIMEOUTC + 2 + 1 + + + DTTIMEOUT + DTIMEOUTC + 3 + 1 + + + TXERRU + TXUNDERRC + 4 + 1 + + + RXERRU + RXOVERRC + 5 + 1 + + + CMDRSPCMPL + CMDRENDC + 6 + 1 + + + CMDCMPL + CMDSENTC + 7 + 1 + + + DTCMPL + DATAENDC + 8 + 1 + + + SBITERR + STBITERRC + 9 + 1 + + + DTBLKCMPL + DBCKENDC + 10 + 1 + + + SDIOIF + SDIOITC + 22 + 1 + + + + + INTEN + INTEN + SDIO interrupt enable register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAIL + CCRCFAILIE + 0 + 1 + + + DTFAIL + DCRCFAILIE + 1 + 1 + + + CMDTIMEOUT + CTIMEOUTIE + 2 + 1 + + + DTTIMEOUT + DTIMEOUTIE + 3 + 1 + + + TXERRU + TXUNDERRIE + 4 + 1 + + + RXERRU + RXOVERRIE + 5 + 1 + + + CMDRSPCMPL + CMDRENDIE + 6 + 1 + + + CMDCMPL + CMDSENTIE + 7 + 1 + + + DTCMPL + DATAENDIE + 8 + 1 + + + SBITERR + STBITERRIE + 9 + 1 + + + DTBLKCMPL + DBACKENDIE + 10 + 1 + + + DOCMD + CMDACTIE + 11 + 1 + + + DOTX + TXACTIE + 12 + 1 + + + DORX + RXACTIE + 13 + 1 + + + TXBUF_H + TXFIFOHEIE + 14 + 1 + + + RXBUF_H + RXFIFOHFIE + 15 + 1 + + + TXBUF_F + TXFIFOFIE + 16 + 1 + + + RXBUF_F + RXFIFOFIE + 17 + 1 + + + TXBUF_E + TXFIFOEIE + 18 + 1 + + + RXBUF_E + RXFIFOEIE + 19 + 1 + + + TXBUF + TXDAVLIE + 20 + 1 + + + RXBUF + RXDAVLIE + 21 + 1 + + + SDIOIF + SDIOITIE + 22 + 1 + + + + + BUFCNTR + BUFCNTR + Bits 23:0 = FIFOCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = FIFOData: Receive and transmit + FIFO data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + FIFOData + 0 + 32 + + + + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40015800 + + 0x0 + 0x400 + registers + + + ACC + ACC global interrupt + 72 + + + + STS + STS + Status register + 0x0 + 0x20 + read-write + 0x00000000 + + + CALRDY + Internal high-speed clock calibration ready + 0 + 1 + + + RSLOST + Reference Signal Lost + 1 + 1 + + + + + CTRL1 + CTRL1 + Control register 1 + 0x4 + 0x20 + read-write + 0x00000100 + + + CALON + Internal high-speed clock calibration ready + 0 + 1 + + + ENTRIM + Enable trim + 1 + 1 + + + EIEN + RSLOST error interrupt enable + 4 + 1 + + + CALRDYIEN + CALRDY interrupt enable + 5 + 1 + + + STEP + STEP + 8 + 4 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x8 + 0x20 + read-only + 0x00002080 + + + ACC_HSICAL + Internal high-speed auto clock calibration + 0 + 8 + + + ACC_HSITRIM + Internal high-speed auto clock trimming + 8 + 6 + + + + + C1 + C1 + Compare 1 + 0xC + 0x20 + read-write + 0x00001F2C + + + C1 + Compare 1 + 0 + 16 + + + + + C2 + C2 + Compare 2 + 0x10 + 0x20 + read-write + 0x00001F40 + + + C2 + Compare 2 + 0 + 16 + + + + + C3 + C3 + Compare 3 + 0x14 + 0x20 + read-write + 0x00001F54 + + + C3 + Compare 3 + 0 + 16 + + + + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens 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1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain 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+ STRETCH + Clock stretching mode + 7 + 1 + + + GCAEN + General call address enable + 6 + 1 + + + PECEN + PEC calculation enable + 5 + 1 + + + ARPEN + SMBus address resolution protocol enable + 4 + 1 + + + SMBMODE + SMBus device mode + 3 + 1 + + + PERMODE + I2C peripheral mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + DMAEND + DMA transfer end indication + 12 + 1 + + + DMAEN + DMA transfer enable + 11 + 1 + + + DATAIEN + Data transmission interrupt enable + 10 + 1 + + + EVTIEN + Event interrupt enable + 9 + 1 + + + ERRIEN + Error interrupt enable + 8 + 1 + + + CLKFREQ + Input clock frequency + 0 + 8 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDR1MODE + Address mode + 15 + 1 + + + ADDR1 + Own address 1 + 0 + 10 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2EN + Own address 2 enable + 0 + 1 + + + + + DT + DT + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DT + data register + 0 + 8 + + + + + STS1 + STS1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + ALERTF + SMBus alert + 15 + 1 + read-write + + + TMOUT + Timeout error + 14 + 1 + read-write + + + PECERR + PEC receive error + 12 + 1 + read-write + + + OUF + Overflow or underflow + 11 + 1 + read-write + + + ACKFAIL + Acknowledge failure + 10 + 1 + read-write + + + ARLOST + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BUSERR + Bus error + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + (transmitters) + 7 + 1 + read-only + + + RDBF + Receive data buffer full + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADDRHF + address header match (Master + mode) + 3 + 1 + read-only + + + TDC + Transmit data complete + 2 + 1 + read-only + + + ADDR7F + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + STARTF + Start bit (Master mode) + 0 + 1 + read-only + + + + + STS2 + STS2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PECVAL + PEC value + 8 + 8 + + + ADDR2F + Received address 2 + 7 + 1 + + + HOSTADDRF + SMBus host address receiving + 6 + 1 + + + DEVADDRF + SMBus device address receiving + 5 + 1 + + + GCADDRF + General call address reception + 4 + 1 + + + DIRF + Transmission direction + 2 + 1 + + + BUSYF + Bus busy + 1 + 1 + + + TRMODE + Transmission mode + 0 + 1 + + + + + CLKCTRL + CLKCTRL + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + SPEEDMODE + Speed mode selection + 15 + 1 + + + DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + ADC1 + Analog to digital converter + ADC1 + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN1_RX1 + CAN1 RX1 interrupt + 21 + + + CAN1_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 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Comparator2 inverting selection + 20 + 3 + read-write + + + DCMPEN + Double comparator mode enable + 23 + 1 + read-write + + + CMP2TAG + Comparator2 output target + 24 + 3 + read-write + + + CMP2P + Comparator2 polarity + 27 + 1 + read-write + + + CMP2HYST + Comparator2 hysteresis + 28 + 2 + read-write + + + CMP2VALUE + Comparator2 output value + 30 + 1 + read-only + + + CMP2WP + Comparator2 write protect + 31 + 1 + read-write + + + + + CTRLSTS2 + CTRLSTS2 + CMP control/status register2 + 0x4 + 0x20 + 0x00000000 + + + COMP1NINVSEL + Comparator1 non-inverting input selection + 0 + 2 + read-write + + + COMP2NINVSEL + Comparator2 non-inverting input selection + 16 + 2 + read-write + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + DEBUG_IDCODE + DEBUG_IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + MCUDBG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 13 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 18 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 28 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 29 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 30 + 1 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + WTCYC + Wait cycle + 0 + 3 + read-write + + + HFCYC_EN + Half cycle acceleration access enable + 3 + 1 + read-write + + + PFT_EN + Prefetch enable + 4 + 1 + read-write + + + PFT_ENF + Prefetch enabled flag + 5 + 1 + read-only + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + FAP_HL_DIS + FAP high level disable + 16 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + FAP_HL + FAP high level + 26 + 1 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0x74 + 0x20 + read-only + 0x00000000 + + + BTM_AP_ENF + Boot memory store application code enabled flag + 0 + 1 + + + EM_SLIB_ENF + Extension memory sLib enabled flag + 2 + 1 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + + + EM_SLIB_DAT_SS + Extension memory sLib data start sector + 16 + 8 + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0x78 + 0x20 + read-only + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 11 + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + + + SLIB_ES + sLib end sector + 22 + 10 + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0x7C + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0x80 + 0x20 + 0x00000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + + + CRC_ADDR + CRC_ADDR + Flash CRC data start address register + 0x84 + 0x20 + write-only + 0x00000000 + + + CRC_ADDR + CRC address + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controll register + 0x88 + 0x20 + 0x00000000 + + + CRC_SN + CRC sector numbler + 0 + 16 + read-write + + + CRC_STRT + CRC start + 16 + 1 + write-only + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0x8C + 0x20 + read-only + 0x00000000 + + + FCRC_OUT + CRC32 verification result of flash user code or SLIB code + 0 + 32 + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0x160 + 0x20 + write-only + 0x00000000 + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0x164 + 0x20 + write-only + 0x00000000 + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + EM_SLIB_SET + EM_SLIB_SET + Extension momery slib set register + 0x168 + 0x20 + write-only + 0x00000000 + + + EM_SLIB_SET + Extension memory sLib setting + 0 + 16 + + + EM_SLIB_DSS_SET + Extension memory sLib data start sector setting + 16 + 8 + + + + + BTM_MODE_SET + BTM_MODE_SET + Boot memory mode setting register + 0x16C + 0x20 + write-only + 0x00000000 + + + BTM_MODE_SET + Boot memory mode setting + 0 + 8 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0x170 + 0x20 + write-only + 0x00000000 + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USB_OTG_GLOBAL + USB on the go full speed + USB_OTG + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS + USB On The Go FS global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + AVALIDSESEN + sense Avalid enable + 18 + 1 + + + BVALIDSESEN + sense Bvalid enable + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG_HOST + USB on the go full speed + USB_OTG + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG_DEVICE + USB on the go full speed + USB_OTG + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG_PWRCLK + USB on the go full speed + USB_OTG + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.h b/hw/bsp/at32f415/boards/AT_START_F415/board.h new file mode 100644 index 000000000..8b933f9e9 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.h @@ -0,0 +1,80 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// Usart +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 + +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.mk b/hw/bsp/at32f415/boards/AT_START_F415/board.mk new file mode 100644 index 000000000..6c877ec71 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F415xC_FLASH.ld + +CFLAGS += \ + -DAT32F415RCT7 diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c new file mode 100644 index 000000000..6c7600783 --- /dev/null +++ b/hw/bsp/at32f415/family.c @@ -0,0 +1,287 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f415_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + (void) clk_s; + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + default: + break; + } +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f415/family.mk b/hw/bsp/at32f415/family.mk new file mode 100644 index 000000000..d0cca67ab --- /dev/null +++ b/hw/bsp/at32f415/family.mk @@ -0,0 +1,43 @@ +# Submodules +AT32F415_SDK = hw/mcu/artery/at32f415 +DEPS_SUBMODULES += $(AT32F415_SDK) + +# AT32 SDK path +AT32F415_SDK_SRC = $(AT32F415_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m3 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F415 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_gpio.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_misc.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_usart.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_crm.c \ + $(AT32F415_SDK_SRC)/cmsis/cm4/device_support/system_at32f415.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F415_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f415.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f415/startup_at32f415.s b/hw/bsp/at32f415/startup_at32f415.s new file mode 100644 index 000000000..47a913e36 --- /dev/null +++ b/hw/bsp/at32f415/startup_at32f415.s @@ -0,0 +1,407 @@ +/** + ****************************************************************************** + * @file startup_at32f415.s + * @brief at32f415xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word 0 /* Reserved */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CMP1_IRQHandler /* CMP1 */ + .word CMP2_IRQHandler /* CMP2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak CMP1_IRQHandler + .thumb_set CMP1_IRQHandler,Default_Handler + + .weak CMP2_IRQHandler + .thumb_set CMP2_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..06afc3860 --- /dev/null +++ b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f423.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd new file mode 100644 index 000000000..4954c417f --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd @@ -0,0 +1,36050 @@ + + + + + + + + Keil + ArteryTek + AT32F423xx_v2 + AT32F423 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL2 + BK1CTRL2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG2 + BK1TMG2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR2 + BK1TMGWR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT2 + EXT2 + externl timeing register 2 + 0x224 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + SWPEN6 + Standby wake-up pin 6 enable + 13 + 1 + read-write + + + SWPEN7 + Standby wake-up pin 7 enable + 14 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000000 + + + LDOOVSEL + LDO output voltage select + 0 + 2 + read-write + + + VREXLPEN + Voltage regulator extra low power mode enable + 4 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FR + PLL post-division + 16 + 3 + read-write + + + PLLRCS + PLL reference clock select + 22 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + CLKOUTDIV1 + Clock output division1 + 27 + 3 + read-write + + + CLKOUT_SEL1 + Clock output selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + XMCRST + XMC reset + 0 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR12RST + Timer12 reset + 6 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + USART7RST + USART7 reset + 30 + 1 + + + USART8RST + USART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOEEN + IO E clock enable + 4 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + XMCEN + XMC clock enable + 0 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + USART5EN + USART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + USART7EN + USART7 clock enable + 30 + 1 + + + USART8EN + USART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADCEN + ADC clock enable + 8 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOELPEN + IO E clock enable during sleep mode + 4 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAMLPEN + SRAM clock enable during sleep mode + 16 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + XMCLPEN + XMC clock enable during sleep mode + 0 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR12LPEN + Timer12 clock enable during sleep mode + 6 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + USART4LPEN + USART4 clock enable during sleep mode + 19 + 1 + + + USART5LPEN + USART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + CAN2LPEN + CAN2 clock enable during sleep mode + 26 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + DACLPEN + DAC clock enable during sleep mode + 29 + 1 + + + USART7LPEN + USART7 clock enable during sleep mode + 30 + 1 + + + USART8LPEN + USART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + ADCLPEN + ADC clock enable during sleep mode + 8 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + + + PICLKS + PICLKS + Peripheral independent clock register + (CRM_PICLKS) + 0x68 + 0x20 + 0x00000000 + + + USART1SEL + USART1 clock select + 0 + 2 + read-write + + + USART2SEL + USART2 clock select + 2 + 2 + read-write + + + USART3SEL + USART3 clock select + 4 + 2 + read-write + + + I2C1SEL + I2C1 clock select + 12 + 2 + read-write + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_USB + HICK to usb clock + 13 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + PLLCLK_TO_ADC + ADC clock source select + 15 + 1 + read-write + + + CLKOUT_SEL2 + Clock output select2 + 16 + 4 + read-write + + + CLKOUTDIV2 + Clock output division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + USBDIV + USB division + 12 + 4 + read-write + + + HICK_TO_SCLK_DIV + HICK as system clock frequency division + 16 + 3 + read-write + + + HEXT_TO_SCLK_DIV + HEXT as system clock frequency division + 19 + 3 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 2 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + TOGR + TOGR + GPIO bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + IOTB0 + Toggle bit 0 + 0 + 1 + + + IOTB1 + Toggle bit 1 + 1 + 1 + + + IOTB2 + Toggle bit 2 + 2 + 1 + + + IOTB3 + Toggle bit 3 + 3 + 1 + + + IOTB4 + Toggle bit 4 + 4 + 1 + + + IOTB5 + Toggle bit 5 + 5 + 1 + + + IOTB6 + Toggle bit 6 + 6 + 1 + + + IOTB7 + Toggle bit 7 + 7 + 1 + + + IOTB8 + Toggle bit 8 + 8 + 1 + + + IOTB9 + Toggle bit 9 + 9 + 1 + + + IOTB10 + Toggle bit 10 + 10 + 1 + + + IOTB11 + Toggle bit 11 + 11 + 1 + + + IOTB12 + Toggle bit 12 + 12 + 1 + + + IOTB13 + Toggle bit 13 + 13 + 1 + + + IOTB14 + Toggle bit 14 + 14 + 1 + + + IOTB15 + Toggle bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOE + 0x40021000 + + + GPIOF + 0x40021400 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + I2C1_EVT + I2C1_EVT interrupt connect to EXINT line23 + 31 + + + USART1 + ERTC Global interrupt connect to EXINT line25 + 37 + + + USART2 + ERTC Global interrupt connect to EXINT line26 + 38 + + + USART3 + USART3 Global interrupt connect to EXINT line28 + 39 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + INTEN23 + Interrupt enable or disable on line 23 + 23 + 1 + + + INTEN25 + Interrupt enable or disable on line 25 + 25 + 1 + + + INTEN26 + Interrupt enable or disable on line 26 + 26 + 1 + + + INTEN28 + Interrupt enable or disable on line 28 + 28 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + EVTEN23 + Event enable or disable on line 23 + 23 + 1 + + + EVTEN25 + Event enable or disable on line 25 + 25 + 1 + + + EVTEN26 + Event enable or disable on line 26 + 26 + 1 + + + EVTEN28 + Event enable or disable on line 28 + 28 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + RP23 + Rising polarity configuration bit of line 23 + 23 + 1 + + + RP25 + Rising polarity configuration bit of line 25 + 25 + 1 + + + RP26 + Rising polarity configuration bit of line 26 + 26 + 1 + + + RP28 + Rising polarity configuration bit of line 28 + 28 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + FP23 + Falling polarity event configuration bit of line 23 + 23 + 1 + + + FP25 + Falling polarity event configuration bit of line 25 + 25 + 1 + + + FP26 + Falling polarity event configuration bit of line 26 + 26 + 1 + + + FP28 + Falling polarity event configuration bit of line 28 + 28 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + SWT23 + Software triggle on line 233 + 23 + 1 + + + SWT25 + Software triggle on line 255 + 25 + 1 + + + SWT26 + Software triggle on line 26 + 26 + 1 + + + SWT28 + Software triggle on line 28 + 28 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + LINE23 + Line 23 state bit + 23 + 1 + + + LINE25 + Line 25 state bit + 25 + 1 + + + LINE26 + Line 26 state bit + 26 + 1 + + + LINE28 + Line 28 state bit + 28 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40026000 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026400 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR6DT + BPR6DT + Battery powered domain register + 0x64 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR7DT + BPR7DT + Battery powered domain register + 0x68 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR8DT + BPR8DT + Battery powered domain register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR9DT + BPR9DT + Battery powered domain register + 0x70 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR10DT + BPR10DT + Battery powered domain register + 0x74 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR11DT + BPR11DT + Battery powered domain register + 0x78 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR12DT + BPR12DT + Battery powered domain register + 0x7C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR13DT + BPR13DT + Battery powered domain register + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR14DT + BPR14DT + Battery powered domain register + 0x84 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR15DT + BPR15DT + Battery powered domain register + 0x88 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR16DT + BPR16DT + Battery powered domain register + 0x8C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR17DT + BPR17DT + Battery powered domain register + 0x90 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR18DT + BPR18DT + Battery powered domain register + 0x94 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR19DT + BPR19DT + Battery powered domain register + 0x98 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR20DT + BPR20DT + Battery powered domain register + 0x9C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + WINF + Window value update complete flag + 2 + 1 + + + + + WIN + WIN + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Window value + 0 + 12 + + + + + + + WWDT + Window watchdog + WWDT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDT + Window Watchdog interrupt + 0 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + CNT + Decrement counter + 0 + 7 + + + WWDTEN + Window watchdog enable + 7 + 1 + + + + + CFG + CFG + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WIN + Window value + 0 + 7 + + + DIV + Clock division value + 7 + 2 + + + RLDIEN + Reload counter interrupt + 9 + 1 + + + + + STS + STS + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + RLDF + Reload counter interrupt flag + 0 + 1 + + + + + + + TMR1 + Advanced timer + TIMER + 0x40010000 + + 0x0 + 0x400 + registers + + + TMR1_BRK_TMR9 + TMR1 brake interrupt and TMR9 global + interrupt + 24 + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts 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30 + + + + TMR9 + General purpose timer + TIMER + 0x40014000 + + 0x0 + 0x400 + registers + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C2CIOS + Channel 2 complementary idle output state + 11 + 1 + + + C2IOS + Channel 2 idle output state + 10 + 1 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + STS + Subordinate TMR synchronization + 7 + 1 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDEN + Trigger DMA request enable + 14 + 1 + + + HALLDE + HALL DMA request enable + 13 + 1 + + + C2DEN + Channel 2 DMA request + enable + 10 + 1 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + TIEN + Trigger interrupt enable + 6 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C2IEN + Channel 2 interrupt + enable + 2 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C2RF + Channel 2 recapture flag + 10 + 1 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C2IF + Channel 2 interrupt flag + 2 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + + TMR10 + General purpose timer + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C1IEN + Channel 1 interrupt enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR11 + 0x40014800 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + TMR13 + 0x40001C00 + + + TMR14 + 0x40002000 + + + RMP + RMP + TMR14 channel 1 input remap + 0x50 + 0x20 + read-write + 0x00000000 + + + TMR14_CH1_IRMP + TMR14 channel 1 input remap + 6 + 2 + + + + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40017400 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLKP + I2SCLKP + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + ID3_0 + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + RDY + ADC ready to conversion flag + 6 + 1 + read-only + + + OCCO + Ordinary channel conversion overflow flag + 5 + 1 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + OCCE + Ordinary channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCCOIEN + Ordinary channel conversion overflow interrupt enable + 26 + 1 + + + CRSEL + Conversion resolution select + 24 + 2 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + OCCEIEN + Ordinary channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCSWTRG + Ordinary channel software conversion trigger + 30 + 1 + + + OCETE + Ordinary channel external trigger edge select + 28 + 2 + + + OCTESEL + trigger event select for ordinary channels conversion + 24 + 4 + + + PCSWTRG + Preempted channel software conversion trigger + 22 + 1 + + + PCETE + Preempted channel external trigger edge select + 20 + 2 + + + PCTESEL + trigger event select for preempted channels conversion + 16 + 4 + + + DTALIGN + Data alignment + 11 + 1 + + + EOCSFEN + Each ordinary channel conversion set OCCE flag enable + 10 + 1 + + + OCDRCEN + Ordinary channel DMA request continuation enable for independent mode + 9 + 1 + + + OCDMAEN + Ordinary channel DMA transfer enable for independent mode + 8 + 1 + + + ADABRT + ADC conversion abort + 4 + 1 + + + ADCALINIT + Initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT18 + Selection sample time of channel ADC_IN18 + 24 + 3 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + SPT3 + SPT3 + sample time register 3 + 0x50 + 0x20 + read-write + 0x00000000 + + + CSPT27 + Selection sample time of channel ADC_IN27 + 21 + 3 + + + CSPT26 + Selection sample time of channel ADC_IN26 + 18 + 3 + + + CSPT25 + Selection sample time of channel ADC_IN25 + 15 + 3 + + + CSPT24 + Selection sample time of channel ADC_IN24 + 12 + 3 + + + CSPT23 + Selection sample time of channel ADC_IN23 + 9 + 3 + + + CSPT22 + Selection sample time of channel ADC_IN22 + 6 + 3 + + + CSPT21 + Selection sample time of channel ADC_IN21 + 3 + 3 + + + CSPT20 + Selection sample time of channel ADC_IN20 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 16 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 16 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 5 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + OSQ4 + OSQ4 + Ordinary sequence register 4 + 0x54 + 0x20 + read-write + 0x00000000 + + + OSN22 + Number of 22th conversion in ordinary sequence + 25 + 5 + + + OSN21 + Number of 21th conversion in ordinary sequence + 20 + 5 + + + OSN20 + Number of 20th conversion in ordinary sequence + 15 + 5 + + + OSN19 + number of 19rd conversion in ordinary sequence + 10 + 5 + + + OSN18 + Number of 18nd conversion in ordinary sequence + 5 + 5 + + + OSN17 + Number of 17st conversion in ordinary sequence + 0 + 5 + + + + + OSQ5 + OSQ5 + Ordinary sequence register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + OSN28 + Number of 28th conversion in ordinary sequence + 25 + 5 + + + OSN27 + Number of 27th conversion in ordinary sequence + 20 + 5 + + + OSN26 + Number of 26th conversion in ordinary sequence + 15 + 5 + + + OSN25 + number of 25rd conversion in ordinary sequence + 10 + 5 + + + OSN24 + Number of 24nd conversion in ordinary sequence + 5 + 5 + + + OSN23 + Number of 23st conversion in ordinary sequence + 0 + 5 + + + + + OSQ6 + OSQ6 + Ordinary sequence register 6 + 0x5C + 0x20 + read-write + 0x00000000 + + + OSN32 + Number of 32th conversion in ordinary sequence + 15 + 5 + + + OSN31 + number of 31rd conversion in ordinary sequence + 10 + 5 + + + OSN30 + Number of 30nd conversion in ordinary sequence + 5 + 5 + + + OSN29 + Number of 29st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + CALVAL + CALVAL + Calibration value register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALVAL + A/D Calibration value + 0 + 7 + + + + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CSTS + CSTS + Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + RDY1 + ADC ready to conversion flag of ADC1 + 6 + 1 + + + OCCO1 + Ordinary channel conversion overflow flag of ADC1 + 5 + 1 + + + OCCS1 + Ordinary channel conversion start flag of ADC1 + 4 + 1 + + + PCCS1 + Preempted channel conversion start flag of ADC1 + 3 + 1 + + + PCCE1 + Preempted channels conversion end flag of ADC1 + 2 + 1 + + + OCCE1 + Ordinary channels conversion end flag of ADC1 + 1 + 1 + + + VMOR1 + Voltage monitoring out of range flag of ADC1 + 0 + 1 + + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + VBATEN + VBAT enable + 22 + 1 + + + ADCDIV + ADC division + 16 + 4 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB2 + F3FB2 + Filter bank 3 filtrate bit register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + 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Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB1 + F12FB1 + Filter bank 12 filtrate bit register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB2 + F12FB2 + Filter bank 12 filtrate bit register 2 + 0x2A4 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 63 + + + CAN2_RX0 + CAN2 RX0 interrupt + 64 + + + CAN2_RX1 + CAN2 RX1 interrupt + 65 + + + CAN2_SE + CAN2 SE interrupt + 66 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D1DMAUDRIEN + DAC1 DMA underrun interrupt enable + 13 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + D2DMAUDRIEN + DAC2 DMA underrun interrupt enable + 29 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + STS + STS + DAC2 status register + (DAC_STS) + 0x34 + 0x20 + read-write + 0x00000000 + + + D1DMAUDRF + DAC1 DMA underrun flag + 13 + 1 + + + D2DMAUDRF + DAC2 DMA underrun flag + 29 + 1 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + Product ID + 0 + 32 + + + + + CTRL + CTRL + DEBUG CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + + + APB1_PAUSE + APB1_PAUSE + DEBUG APB1 PAUSE + 0x8 + 0x20 + read-write + 0x0 + + + TMR2_PAUSE + TMR2_PAUSE + 0 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 1 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 2 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 4 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 5 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 6 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 7 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 8 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 10 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 11 + 1 + + + WDT_PAUSE + WDT_PAUSE + 12 + 1 + + + ERTC512_PAUSE + ERTC512_PAUSE + 15 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 24 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 25 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 26 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 27 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 28 + 1 + + + + + APB2_PAUSE + APB2_PAUSE + DEBUG APB2 PAUSE + 0xC + 0x20 + read-write + 0x0 + + + TMR1_PAUSE + TMR1_PAUSE + 0 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 1 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 16 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 17 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 18 + 1 + + + + + SER_ID + SER_ID + SERIES ID + 0x20 + 0x20 + read-only + 0x0 + + + REV_ID + version ID + 0 + 3 + + + SER_ID + series ID + 8 + 8 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000330 + + + NZW_BST_STS + Flash non-zero wait area boost status + 13 + 1 + read-only + + + NZW_BST + Flash non-zero wait area boost + 12 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + nWDT_DEPSLP + WDT deep sleep + 7 + 1 + + + nWDT_STDBY + WDT standby + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS0 + EPPS0 + Erase/program protection status register 0 + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + EPPS1 + EPPS1 + Erase/program protection status register 1 + 0x2C + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + CONTR + CONTR + Flash continue read register + 0x58 + 0x20 + read-write + 0x00000080 + + + FCONTR_EN + Flash continue read enable + 31 + 1 + + + + + DIVR + DIVR + Flash divider register + 0x60 + 0x20 + 0x00000022 + + + FDIV + Flash divider + 0 + 2 + read-write + + + FDIV_STS + Flash divider status + 4 + 2 + read-only + + + + + SLIB_STS2 + SLIB_STS2 + sLib status 2 register + 0xC8 + 0x20 + 0x0000FFFF + + + SLIB_INST_SS + sLib instruction start sector + 0 + 16 + read-only + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 16 + read-only + + + SLIB_ES + sLib end sector + 16 + 16 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE0 + SLIB_SET_RANGE0 + Configure sLib range register 0 + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 16 + + + SLIB_ES_SET + sLib end sector setting + 16 + 16 + + + + + SLIB_SET_RANGE1 + SLIB_SET_RANGE1 + Configure sLib range register 1 + 0xE4 + 0x20 + 0x00000000 + write-only + + + SLIB_ISS_SET + sLib instruction start sector setting + 0 + 16 + + + SET_SLIB_STRT + sLib start setting + 31 + 1 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTGFS_GLOBAL + USB on-the-go full speed + USB_OTGFS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTGFS_HOST + USB on the go full speed + USB_OTGFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTGFS_DEVICE + USB on the go full speed + USB_OTGFS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTGFS_PWRCLK + USB on the go full speed + USB_OTGFS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + LOCKUP_LK + CM4 LOCKUP bit enable + 0 + 1 + + + PVM_LK + PVM lock enable + 2 + 1 + + + I2S_FD + I2S full duplex configuration bit + 30 + 2 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PD13_UH + PD13 ultra high sourcing/sinking strength + 6 + 1 + + + PD12_UH + PD12 ultra high sourcing/sinking strength + 5 + 1 + + + PB8_UH + PB8 ultra high sourcing/sinking strength + 3 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + ACTR + ACTR + AC timing control register + 0x14 + 0x20 + read-write + 0x0000000F + + + CSDLY + CS delay + 0 + 4 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 6 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 6 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + QSPI2 + 0xA0002000 + + QSPI2 + QSPI2 global interrupt + 91 + + + + diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.h b/hw/bsp/at32f423/boards/AT_START_F423/board.h new file mode 100644 index 000000000..fc8e2d8a5 --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.h @@ -0,0 +1,91 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 +#define OTG_PIN_MUX GPIO_MUX_10 + +//Vbus +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.mk b/hw/bsp/at32f423/boards/AT_START_F423/board.mk new file mode 100644 index 000000000..95ec21d02 --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F423xC_FLASH.ld + +CFLAGS += \ + -DAT32F423VCT7 diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c new file mode 100644 index 000000000..f63fb8962 --- /dev/null +++ b/hw/bsp/at32f423/family.c @@ -0,0 +1,294 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f423_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); +void uart_print_init(uint32_t baudrate); +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_6); + break; + + default: + break; + } + } +} +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f423/family.mk b/hw/bsp/at32f423/family.mk new file mode 100644 index 000000000..2653842da --- /dev/null +++ b/hw/bsp/at32f423/family.mk @@ -0,0 +1,44 @@ +# Submodules +AT32F423_SDK = hw/mcu/artery/at32f423 +DEPS_SUBMODULES += $(AT32F423_SDK) + +# AT32 SDK path +AT32F423_SDK_SRC = $(AT32F423_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F423 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_gpio.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_misc.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_usart.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_crm.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_acc.c \ + $(AT32F423_SDK_SRC)/cmsis/cm4/device_support/system_at32f423.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F423_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f423.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f423/startup_at32f423.s b/hw/bsp/at32f423/startup_at32f423.s new file mode 100644 index 000000000..764380f0e --- /dev/null +++ b/hw/bsp/at32f423/startup_at32f423.s @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file startup_at32f423.s + * @brief at32f423 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word TMR12_GLOBAL_IRQHandler /* TMR12 */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI3_IRQHandler /* SPI3 */ + .word USART4_IRQHandler /* USART4 */ + .word USART5_IRQHandler /* USART5 */ + .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word USART7_IRQHandler /* USART7 */ + .word USART8_IRQHandler /* USART8 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* DMAMUX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ACC_IRQHandler /* ACC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR12_GLOBAL_IRQHandler + .thumb_set TMR12_GLOBAL_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak TMR6_DAC_GLOBAL_IRQHandler + .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak USART7_IRQHandler + .thumb_set USART7_IRQHandler,Default_Handler + + .weak USART8_IRQHandler + .thumb_set USART8_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..6cc39f727 --- /dev/null +++ b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f425.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd new file mode 100644 index 000000000..d18e75e8e --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd @@ -0,0 +1,30790 @@ + + + + + + + + Keil + ArteryTek + AT32F425xx_v2 + AT32F425 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 120MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + PVM + PVM through EXTI line detection interrupt + 1 + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + read-write + + + LPSEL + Low power mode select when Cortex-M4 sleepdeep + 1 + 1 + read-write + + + CLSWEF + Clear SWEF flag + 2 + 1 + write-only + + + CLSEF + Clear SEF flag + 3 + 1 + write-only + + + PVMEN + Power voltage monitoring enable + 4 + 1 + read-write + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + read-write + + + BPWEN + Battery power domain write enable + 8 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Power control register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin2 enable + 9 + 1 + read-write + + + SWPEN4 + Standby wake-up pin4 enable + 11 + 1 + read-write + + + SWPEN5 + Standby wake-up pin5 enable + 12 + 1 + read-write + + + SWPEN6 + Standby wake-up pin6 enable + 13 + 1 + read-write + + + SWPEN7 + Standby wake-up pin7 enable + 14 + 1 + read-write + + + + + CTRL2 + CTRL2 + Power control register 2 + (PWC_CTRL2) + 0x20 + 0x20 + 0x00000000 + + + VREXLPEN + Voltage regulator extra low power mode enable + 5 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 4 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + SCFGRST + System config reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + TMR1RST + TMR1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR15RST + Timer15 reset + 16 + 1 + + + TMR16RST + Timer16 reset + 17 + 1 + + + TMR17RST + Timer17 reset + 18 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR6RST + Timer 6 reset + 4 + 1 + + + TMR7RST + Timer 7 reset + 5 + 1 + + + TMR13RST + Timer 13 reset + 7 + 1 + + + TMR14RST + Timer 14 reset + 8 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + USART4RST + USART 4 reset + 19 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + ACCRST + ACC reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 12 + 1 + + + GPIOAEN + I/O port A clock enable + 17 + 1 + + + GPIOBEN + I/O port B clock enable + 18 + 1 + + + GPIOCEN + I/O port C clock enable + 19 + 1 + + + GPIODEN + I/O port D clock enable + 20 + 1 + + + GPIOFEN + I/O port F clock enable + 22 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + SCFGEN + System config clock enable + 0 + 1 + + + ADC1EN + ADC1 clock enable + 9 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR15EN + Timer15 clock enable + 16 + 1 + + + TMR16EN + Timer16 clock enable + 17 + 1 + + + TMR17EN + Timer17 clock enable + 18 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + ACCEN + ACC clock enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 12 + 1 + + + GPIOARST + IO port A reset + 17 + 1 + + + GPIOBRST + IO port B reset + 18 + 1 + + + GPIOCRST + IO port C reset + 19 + 1 + + + GPIODRST + IO port D reset + 20 + 1 + + + GPIOFRST + IO port F reset + 22 + 1 + + + + + PLL + PLL + PLL configuration register + (CRM_PLL) + 0x2C + 0x20 + 0x00001F10 + + + PLL_FR + PLL_FR + 0 + 3 + read-write + + + PLL_MS + PLL_MS + 4 + 4 + read-write + + + PLL_NS + PLL_NS + 8 + 9 + read-write + + + PLL_FREF + PLL entry clock reference frequency + 24 + 3 + read-write + + + PLLCFGEN + PLL config enable + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x54 + 0x20 + 0x0000000D + + + HICK_TO_USB + HICK_TO_USB + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x48000400 + + + GPIOC + 0x48000800 + + + GPIOD + 0x48000C00 + + + GPIOF + 0x48001400 + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + PVM + PVM interrupt connect to EXTI line16 + 1 + + + ERTC + ERTC interrupt connect to EXTI line17_19_20 + 2 + + + EXTINT1_0 + EXINT Line1_0 interrupt + 5 + + + EXTINT3_2 + EXINT Line3_2 interrupt + 6 + + + EXTINT15_4 + EXINT Line15_4 interrupt + 7 + + + OTGFS + OTGFS interrupt connect to EXTI Line18 + 31 + + + + INTEN + INTEN + Interrupt enable register (EXTINT_INTEN) + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + + + EVTEN + EVTEN + Event enable register (EXTINT_EVTEN) + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register(EXTINT_POLCFG1) + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register(EXTINT_POLCFG2) + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + + + SWTRG + SWTRG + Software triggle register + (EXTINT_SWIE) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + + + INTSTS + INTSTS + Interrupt status register (EXTINT_INTSTS) + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 9 + + + DMA1_Channel3_2 + DMA1 Channel3_2 global interrupt + 10 + + + DMA1_Channel7_4 + DMA1 Channel7_4 global interrupt + 11 + + + + STS + STS + DMA interrupt status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC 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HALLSWTR + HALL event triggered by software + 5 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 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DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR16 + General-purpose-timers + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR16 + TMR16 global interrupt + 21 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C4IF + Channel 4 interrupt flag + 4 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR17 + 0x40014800 + + TMR17 + TMR17 global interrupt + 22 + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 23 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 24 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1 + CAN1 global interrupt + 30 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit 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register 2 + 0x28C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F10FB1 + F10FB1 + Filter bank 10 filtrate bit register 1 + 0x290 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F10FB2 + F10FB2 + Filter bank 10 filtrate bit register 2 + 0x294 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit 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data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F11FB2 + F11FB2 + Filter bank 11 filtrate bit register 2 + 0x29C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB1 + F12FB1 + Filter bank 12 filtrate bit filtrate bit register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit 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FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + ACC + HSI Auto Clock Calibration + ACC + 0x40006C00 + + 0x0 + 0x400 + registers + + + ACC + ACC interrupts + 8 + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + ACC_HSITRIM + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + ACC_HSICAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 25 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency 3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-only + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 26 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 33 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 27 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 28 + + + + USART3 + 0x40004800 + + USART3 + USART4_3 global interrupt + 29 + + + + USART4 + 0x40004C00 + + + ADC + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 12 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + + + SCFG + System configuration controller + SCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory mapping selection + bits + 0 + 2 + + + PA11_12_RMP + PA11/PA12 pins remapping bit + 4 + 1 + + + IR_POL + Infrared output polarity selection + 5 + 1 + + + IR_SRC_SEL + Infrared modulation envelope signal source selection + 6 + 2 + + + PB14_UH + PB14 Ultra high sourcing/sinking strength + 16 + 1 + + + PB13_UH + PB13 Ultra high sourcing/sinking strength + 17 + 1 + + + PB9_UH + PB9 Ultra high sourcing/sinking strength + 18 + 1 + + + PB8_UH + PB8 Ultra high sourcing/sinking strength + 19 + 1 + + + + + EXTIC1 + EXTIC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTINT3 + EXTINT 3 configuration bits + 12 + 4 + + + EXTINT2 + EXTINT 2 configuration bits + 8 + 4 + + + EXTINT1 + EXTINT 1 configuration bits + 4 + 4 + + + EXTINT0 + EXTINT 0 configuration bits + 0 + 4 + + + + + EXTIC2 + EXTIC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTINT7 + EXTINT 7 configuration bits + 12 + 4 + + + EXTINT6 + EXTINT 6 configuration bits + 8 + 4 + + + EXTINT5 + EXTINT 5 configuration bits + 4 + 4 + + + EXTINT4 + EXTINT 4 configuration bits + 0 + 4 + + + + + EXTIC3 + EXTIC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTINT11 + EXTINT 11 configuration bits + 12 + 4 + + + EXTINT10 + EXTINT 10 configuration bits + 8 + 4 + + + EXTINT9 + EXTINT 9 configuration bits + 4 + 4 + + + EXTINT8 + EXTINT 8 configuration bits + 0 + 4 + + + + + EXTIC4 + EXTIC4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTINT15 + EXTINT 15 configuration bits + 12 + 4 + + + EXTINT14 + EXTINT 14 configuration bits + 8 + 4 + + + EXTINT13 + EXTINT 13 configuration bits + 4 + 4 + + + EXTINT12 + EXTINT 12 configuration bits + 0 + 4 + + + + + CFG2 + CFG2 + configuration register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + PVM_LK + PVM lock enable + 2 + 1 + + + I2S_FD + I2S full duplex + 30 + 2 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + DEBUG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + CAN_PAUSE + CAN_PAUSE + 3 + 1 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 19 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 20 + 1 + + + ERTC_512_PAUSE + ERTC_512_PAUSE + 21 + 1 + + + TMR15_PAUSE + TMR15_PAUSE + 22 + 1 + + + TMR16_PAUSE + TMR16_PAUSE + 23 + 1 + + + TMR17_PAUSE + TMR17_PAUSE + 24 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 26 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 27 + 1 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 3 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + WTCYC + Wait cycle + 0 + 3 + read-write + + + HFCYC_EN + Half cycle acceleration access enable + 3 + 1 + read-write + + + PFT_EN + Prefetch enable + 4 + 1 + read-write + + + PFT_ENF + Prefetch enabled flag + 5 + 1 + read-only + + + PFT_EN2 + Prefetch enable 2 + 6 + 1 + read-write + + + PFT_ENF2 + Prefetch enabled flag 2 + 7 + 1 + read-only + + + PFT_LAT_DIS + Prefetch latency disable + 8 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00020080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + LPMEN + Low power mode enable + 17 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + nBOOT1 + boot1 + 6 + 1 + + + nDEPSLP_WDT + Deepsleep wdt stop count + 7 + 1 + + + nSTDBY_WDT + Standby wdt stop count + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + FAP_HL + FAP high level + 26 + 1 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0x74 + 0x20 + 0x00000000 + + + BTM_AP_ENF + Boot memory store application code enabled flag + 0 + 1 + + + EM_SLIB_ENF + Extension memory sLib enabled flag + 2 + 1 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + + + EM_SLIB_INST_SS + Extension memory sLib instruction start sector + 16 + 8 + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0x78 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + + + SLIB_INST_SS + sLib instruction start sector + 11 + 11 + + + SLIB_ES + sLib end sector + 22 + 10 + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0x7C + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0x80 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + + + CRC_ADDR + CRC_ADDR + Flash CRC data start address register + 0x84 + 0x20 + write-only + 0x00000000 + + + CRC_ADDR + CRC address + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controll register + 0x88 + 0x20 + 0x00000000 + + + CRC_SN + CRC sector numbler + 0 + 16 + read-write + + + CRC_STRT + CRC start + 16 + 1 + write-only + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0x8C + 0x20 + read-only + 0x00000000 + + + FCRC_OUT + CRC32 verification result of flash user code or SLIB code + 0 + 32 + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0x160 + 0x20 + write-only + 0x00000000 + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0x164 + 0x20 + write-only + 0x00000000 + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_ISS_SET + sLib instruction start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + EM_SLIB_SET + EM_SLIB_SET + Extension momery slib set register + 0x168 + 0x20 + write-only + 0x00000000 + + + EM_SLIB_SET + Extension memory sLib setting + 0 + 16 + + + EM_SLIB_ISS_SET + Extension memory sLib instruction start sector setting + 16 + 8 + + + + + BTM_MODE_SET + BTM_MODE_SET + Boot memory mode setting register + 0x16C + 0x20 + write-only + 0x00000000 + + + BTM_MODE_SET + Boot memory mode setting + 0 + 8 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0x170 + 0x20 + write-only + 0x00000000 + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USB_OTG1_GLOBAL + USB on-the-go full speed + USB_OTG1 + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTG1 + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTG1 + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTG1 + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.h b/hw/bsp/at32f425/boards/AT_START_F425/board.h new file mode 100644 index 000000000..ddfe1f71b --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.h @@ -0,0 +1,90 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// Usart +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_1 + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 +#define OTG_PIN_MUX GPIO_MUX_3 + +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.mk b/hw/bsp/at32f425/boards/AT_START_F425/board.mk new file mode 100644 index 000000000..3fa74d95a --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F425x8_FLASH.ld + +CFLAGS += \ + -DAT32F425R8T7 diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c new file mode 100644 index 000000000..e0b66730a --- /dev/null +++ b/hw/bsp/at32f425/family.c @@ -0,0 +1,298 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f425_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + /* usb divider reset */ + crm_usb_div_reset(); + + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + default: + break; + } + } +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f425/family.mk b/hw/bsp/at32f425/family.mk new file mode 100644 index 000000000..d1bcdfda3 --- /dev/null +++ b/hw/bsp/at32f425/family.mk @@ -0,0 +1,43 @@ +# Submodules +AT32F425_SDK = hw/mcu/artery/at32f425 +DEPS_SUBMODULES += $(AT32F425_SDK) + +# AT32 SDK path +AT32F425_SDK_SRC = $(AT32F425_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m3 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F425 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_gpio.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_misc.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_usart.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_crm.c \ + $(AT32F425_SDK_SRC)/cmsis/cm4/device_support/system_at32f425.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F425_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f425.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f425/startup_at32f425.s b/hw/bsp/at32f425/startup_at32f425.s new file mode 100644 index 000000000..38127c759 --- /dev/null +++ b/hw/bsp/at32f425/startup_at32f425.s @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file startup_at32f425.s + * @brief at32f425xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word ERTC_IRQHandler /* ERTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT1_0_IRQHandler /* EXINT Line 1 & 0 */ + .word EXINT3_2_IRQHandler /* EXINT Line 3 & 2 */ + .word EXINT15_4_IRQHandler /* EXINT Line 15 ~ 4 */ + .word ACC_IRQHandler /* ACC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel3_2_IRQHandler /* DMA1 Channel 3 & 2 */ + .word DMA1_Channel7_4_IRQHandler /* DMA1 Channel 7 & 4 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TMR1_BRK_OVF_TRG_HALL_IRQHandler /* TMR1 brake overflow trigger and hall */ + .word TMR1_CH_IRQHandler /* TMR1 channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word TMR15_GLOBAL_IRQHandler /* TMR15 */ + .word TMR16_GLOBAL_IRQHandler /* TMR16 */ + .word TMR17_GLOBAL_IRQHandler /* TMR17 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART4_3_IRQHandler /* USART3 & USART4 */ + .word CAN1_IRQHandler /* CAN1 */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word SPI3_IRQHandler /* SPI3 */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak ERTC_IRQHandler + .thumb_set ERTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT1_0_IRQHandler + .thumb_set EXINT1_0_IRQHandler,Default_Handler + + .weak EXINT3_2_IRQHandler + .thumb_set EXINT3_2_IRQHandler,Default_Handler + + .weak EXINT15_4_IRQHandler + .thumb_set EXINT15_4_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel3_2_IRQHandler + .thumb_set DMA1_Channel3_2_IRQHandler,Default_Handler + + .weak DMA1_Channel7_4_IRQHandler + .thumb_set DMA1_Channel7_4_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TMR1_BRK_OVF_TRG_HALL_IRQHandler + .thumb_set TMR1_BRK_OVF_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak TMR15_GLOBAL_IRQHandler + .thumb_set TMR15_GLOBAL_IRQHandler,Default_Handler + + .weak TMR16_GLOBAL_IRQHandler + .thumb_set TMR16_GLOBAL_IRQHandler,Default_Handler + + .weak TMR17_GLOBAL_IRQHandler + .thumb_set TMR17_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART4_3_IRQHandler + .thumb_set USART4_3_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..a42e4d414 --- /dev/null +++ b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f435_437.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd new file mode 100644 index 000000000..4f34af9d3 --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd @@ -0,0 +1,58291 @@ + + + + + + + + Keil + ArteryTek + AT32F437xx_v2 + AT32F437 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL2 + BK1CTRL2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG2 + BK1TMG2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL3 + BK1CTRL3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG3 + BK1TMG3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK2CTRL + BK2CTRL + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK2IS + BK2IS + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK2TMGRG + BK2TMGRG + Regular memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK2TMGSP + BK2TMGSP + special memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK2ECC + BK2ECC + ECC result register 2 + 0x74 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK3CTRL + BK3CTRL + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK3IS + BK3IS + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK3TMGRG + BK3TMGRG + Regular memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK3TMGSP + BK3TMGSP + special memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK3ECC + BK3ECC + ECC result register 3 + 0x94 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK4CTRL + BK4CTRL + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK4IS + BK4IS + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK4TMGCM + BK4TMGCM + Regular memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + CMDHIZT + Regular memory databus High resistance time + 24 + 8 + + + CMHT + Regular memory hold time + 16 + 8 + + + CMWT + Regular memory wait time + 8 + 8 + + + CMST + Regular memory setup time + 0 + 8 + + + + + BK4TMGAT + BK4TMGAT + special memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATDHIZT + special memory databus High resistance time + 24 + 8 + + + ATHT + special memory hold time + 16 + 8 + + + ATWT + special memory wait time + 8 + 8 + + + ATST + special memory setup time + 0 + 8 + + + + + BK4TMGIO + BK4TMGIO + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IODHIZT + WRSTP + 24 + 8 + + + IOHT + HLD + 16 + 8 + + + IOWT + OP + 8 + 8 + + + IOST + STP + 0 + 8 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR2 + BK1TMGWR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR3 + BK1TMGWR3 + SRAM/NOR-Flash write timing registers + 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + CTRL1 + CTRL1 + SDRAM Control Register 1 + 0x140 + 0x20 + read-write + 0x000002D0 + + + CA + Number of column address + bits + 0 + 2 + + + RA + Number of row address bits + 2 + 2 + + + DB + Memory data bus width + 4 + 2 + + + INBK + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WRP + Write protection + 9 + 1 + + + CLKDIV + Clock division configuration + 10 + 2 + + + BSTR + Burst read + 12 + 1 + + + RD + Read delay + 13 + 2 + + + + + CTRL2 + CTRL2 + SDRAM Control Register 2 + 0x144 + 0x20 + read-write + 0x000002D0 + + + CA + Number of column address + bits + 0 + 2 + + + RA + Number of row address bits + 2 + 2 + + + DB + Memory data bus width + 4 + 2 + + + INBK + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WRP + Write protection + 9 + 1 + + + CLKDIV + Clock division configuration + 10 + 2 + + + BSTR + Burst read + 12 + 1 + + + RD + Read pipe + 13 + 2 + + + + + TM1 + TM1 + SDRAM Timing register 1 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Mode register program to active delay + 0 + 4 + + + TXSR + Exit Self-refresh to active delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Refresh to active delay + 12 + 4 + + + TWR + Write Recovery delay + 16 + 4 + + + TRP + Precharge to active delay + 20 + 4 + + + TRCD + Row active to Read/Write delay + 24 + 4 + + + + + TM2 + TM2 + SDRAM Timing register 2 + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Mode register program to active delay + 0 + 4 + + + TXSR + Exit Self-refresh to active delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Refresh to active delay + 12 + 4 + + + TWR + Write Recovery delay + 16 + 4 + + + TRP + Precharge to active delay + 20 + 4 + + + TRCD + Row active to Read/Write delay + 24 + 4 + + + + + CMD + CMD + SDRAM Command Mode register + 0x150 + 0x20 + 0x00000000 + + + CMD + SDRAM Command + 0 + 3 + write-only + + + BK2 + SDRAM Bank 2 + 3 + 1 + write-only + + + BK1 + SDRAM Bank 1 + 4 + 1 + write-only + + + ART + Auto-refresh times + 5 + 4 + read-write + + + MRD + Mode register data + 9 + 13 + read-write + + + + + RCNT + RCNT + SDRAM Refresh Timer register + 0x154 + 0x20 + 0x00000000 + + + ERRC + error flag clear + 0 + 1 + write-only + + + RC + Refresh Count + 1 + 13 + read-write + + + ERIEN + error Interrupt Enable + 14 + 1 + read-write + + + + + STS + STS + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + ERR + error flag + 0 + 1 + + + BK1STS + Bank 1 Status + 1 + 2 + + + BK2STS + Bank 2 Status + 3 + 2 + + + BUSY + Busy status + 5 + 1 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT2 + EXT2 + externl timeing register 2 + 0x224 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT3 + EXT3 + externl timeing register 3 + 0x228 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000000 + + + LDOOVSEL + LDO output voltage select + 0 + 3 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FR + PLL post-division + 16 + 3 + read-write + + + PLLRCS + PLL reference clock select + 22 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + CLKOUT1_SEL + Clock output1 selection + 21 + 2 + read-write + + + CLKOUT1DIV1 + Clock output1 division1 + 24 + 3 + read-write + + + CLKOUT2DIV1 + Clock output2 division1 + 27 + 3 + read-write + + + CLKOUT2_SEL1 + Clock output2 selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + EDMARST + EDMA reset + 21 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + EMACRST + EMAC reset + 25 + 1 + + + OTGFS2RST + OTGFS2 interface reset + 29 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + DVPRST + DVP reset + 0 + 1 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + SDIO1RST + SDIO1 reset + 15 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + XMCRST + XMC reset + 0 + 1 + + + QSPI1RST + QSPI1 reset + 1 + 1 + + + QSPI2RST + QSPI2 reset + 14 + 1 + + + SDIO2RST + SDIO2 reset + 15 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR5RST + Timer5 reset + 3 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR12RST + Timer12 reset + 6 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + UART4RST + UART4 reset + 19 + 1 + + + UART5RST + UART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + UART7RST + UART7 reset + 30 + 1 + + + UART8RST + UART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + TMR8RST + Timer8 reset + 1 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SPI4RST + SPI4 reset + 13 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + TMR20RST + Timer20 reset + 20 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOEEN + IO E clock enable + 4 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + GPIOGEN + IO G clock enable + 6 + 1 + + + GPIOHEN + IO H clock enable + 7 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + EDMAEN + DMA1 clock enable + 21 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + EMACEN + EMAC clock enable + 25 + 1 + + + EMACTXEN + EMAC Tx clock enable + 26 + 1 + + + EMACRXEN + EMAC Rx clock enable + 27 + 1 + + + EMACPTPEN + EMAC PTP clock enable + 28 + 1 + + + OTGFS2EN + OTGFS2 clock enable + 29 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + DVPEN + DVP clock enable + 0 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + SDIO1EN + SDIO1 clock enable + 15 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + XMCEN + XMC clock enable + 0 + 1 + + + QSPI1EN + QSPI1 clock enable + 1 + 1 + + + QSPI2EN + QSPI2 clock enable + 14 + 1 + + + SDIO2EN + SDIO 2 clock enable + 15 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + UART7EN + UART7 clock enable + 30 + 1 + + + UART8EN + UART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + TMR8EN + Timer8 clock enable + 1 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SPI4EN + SPI4 clock enable + 13 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + TMR20EN + Timer20 clock enable + 20 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOELPEN + IO E clock enable during sleep mode + 4 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + GPIOGLPEN + IO G clock enable during sleep mode + 6 + 1 + + + GPIOHLPEN + IO H clock enable during sleep mode + 7 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAM1LPEN + SRAM1 clock enable during sleep mode + 16 + 1 + + + SRAM2LPEN + SRAM2 clock enable during sleep mode + 17 + 1 + + + EDMALPEN + EDMA clock enable during sleep mode + 21 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + EMACLPEN + EMAC clock enable during sleep mode + 25 + 1 + + + EMACTXLPEN + EMAC Tx clock enable during sleep mode + 26 + 1 + + + EMACRXLPEN + EMAC Rx clock enable during sleep mode + 27 + 1 + + + EMACPTPLPEN + EMAC PTP clock enable during sleep mode + 28 + 1 + + + OTGFS2LPEN + OTGFS2 clock enable during sleep mode + 29 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + DVPLPEN + DVP clock enable during sleep mode + 0 + 1 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + SDIO1LPEN + SDIO1 clock enable during sleep mode + 15 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + XMCLPEN + XMC clock enable during sleep mode + 0 + 1 + + + QSPI1LPEN + QSPI1 clock enable during sleep mode + 1 + 1 + + + QSPI2LPEN + QSPI2 clock enable during sleep mode + 14 + 1 + + + SDIO2LPEN + SDIO2 clock enable during sleep mode + 15 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR5LPEN + Timer5 clock enable during sleep mode + 3 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR12LPEN + Timer12 clock enable during sleep mode + 6 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + UART4LPEN + UART4 clock enable during sleep mode + 19 + 1 + + + UART5LPEN + UART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + CAN2LPEN + CAN2 clock enable during sleep mode + 26 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + DACLPEN + DAC clock enable during sleep mode + 29 + 1 + + + UART7LPEN + UART7 clock enable during sleep mode + 30 + 1 + + + UART8LPEN + UART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + TMR8LPEN + Timer8 clock enable during sleep mode + 1 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + ADC1CPEN + ADC1 clock enable during sleep mode + 8 + 1 + + + ADC2CPEN + ADC2 clock enable during sleep mode + 9 + 1 + + + ADC3EN + ADC3 clock enable during sleep mode + 10 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SPI4LPEN + SPI4 clock enable during sleep mode + 13 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + TMR20LPEN + Timer20 clock enable during sleep mode + 20 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_USB + HICK to usb clock + 13 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + CLKOUT2_SEL2 + Clock output2 select2 + 16 + 4 + read-write + + + CLKOUT1DIV2 + Clock output1 division2 + 24 + 4 + read-write + + + CLKOUT2DIV2 + Clock output2 division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + CLK_TO_TMR + Clock output internal connect to timer10 + 8 + 1 + read-write + + + USBDIV + USB division + 12 + 4 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOE + 0x40021000 + + + GPIOF + 0x40021400 + + + GPIOG + 0x40021800 + + + GPIOH + 0x40021C00 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + EMAC_WKUP + EMAC_WKUP interrupt connect to EXINT line19 + 62 + + + OTGFS2_WKUP + OTGFS2_WKUP interrupt connect to EXINT line20 + 76 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + EDMA + EDMA controller + EDMA + 0x40026000 + + 0x0 + 0x400 + registers + + + EDMA_Stream1 + EDMA Stream1 global interrupt + 11 + + + EDMA_Stream2 + EDMA Stream2 global interrupt + 12 + + + EDMA_Stream3 + EDMA Stream3 global interrupt + 13 + + + EDMA_Stream4 + EDMA Stream4 global interrupt + 14 + + + EDMA_Stream5 + EDMA Stream5 global interrupt + 15 + + + EDMA_Stream6 + EDMA Stream6 global interrupt + 16 + + + EDMA_Stream7 + EDMA Stream7 global interrupt + 17 + + + EDMA_Stream8 + EDMA Stream8 global interrupt + 47 + + + + STS1 + STS1 + Interrupt status register1 + 0x0 + 0x20 + read-only + 0x00000000 + + + FDTF4 + Stream 4 Full data transfer interrupt flag + + 27 + 1 + + + HDTF4 + Stream 4 half data transfer interrupt flag + + 26 + 1 + + + DTERRF4 + Stream 4 transfer error interrupt flag + + 25 + 1 + + + DMERRF4 + Stream 4 direct mode error interrupt flag + + 24 + 1 + + + FERRF4 + Stream 4 FIFO error interrupt flag + + 22 + 1 + + + FDTF3 + Stream 3 Full data transfer interrupt flag + + 21 + 1 + + + HDTF3 + Stream 3 half data transfer interrupt flag + + 20 + 1 + + + DTERRF3 + Stream 3 transfer error interrupt flag + + 19 + 1 + + + DMERRF3 + Stream 3 direct mode error interrupt flag + + 18 + 1 + + + FERRF3 + Stream 3 FIFO error interrupt flag + + 16 + 1 + + + FDTF2 + Stream 2 Full data transfer interrupt flag + + 11 + 1 + + + HDTF2 + Stream 2 half data transfer interrupt flag + + 10 + 1 + + + DTERRF2 + Stream 2 transfer error interrupt flag + + 9 + 1 + + + DMERRF2 + Stream 2 direct mode error interrupt flag + + 8 + 1 + + + FERRF2 + Stream 2 FIFO error interrupt flag + + 6 + 1 + + + FDTF1 + Stream 1 Full data transfer interrupt flag + + 5 + 1 + + + HDTF1 + Stream 1 half data transfer interrupt flag + + 4 + 1 + + + DTERRF1 + Stream 1 transfer error interrupt flag + + 3 + 1 + + + DMERRF1 + Stream 1 direct mode error interrupt flag + + 2 + 1 + + + FERRF1 + Stream 1 FIFO error interrupt flag + + 0 + 1 + + + + + STS2 + STS2 + Interrupt status register2 + 0x4 + 0x20 + read-only + 0x00000000 + + + FDTF8 + Stream 8 full data transfer interrupt flag + + 27 + 1 + + + HDTF8 + Stream 8 half data transfer interrupt flag + + 26 + 1 + + + DTERRF8 + Stream 8 transfer error interrupt flag + + 25 + 1 + + + DMERRF8 + Stream 8 direct mode error interrupt flag + + 24 + 1 + + + FERRF8 + Stream 8 FIFO error interrupt flag + + 22 + 1 + + + FDTF7 + Stream 7 full data transfer interrupt flag + + 21 + 1 + + + HDTF7 + Stream 7 half data transfer interrupt flag + + 20 + 1 + + + DTERRF7 + Stream 7 transfer error interrupt flag + + 19 + 1 + + + DMERRF7 + Stream 7 direct mode error interrupt flag + + 18 + 1 + + + FERRF7 + Stream 7 FIFO error interrupt flag + + 16 + 1 + + + FDTF6 + Stream 6 full data transfer interrupt flag + + 11 + 1 + + + HDTF6 + Stream 6 half data transfer interrupt flag + + 10 + 1 + + + DTERRF6 + Stream 6 transfer error interrupt flag + + 9 + 1 + + + DMERRF6 + Stream 6 direct mode error interrupt flag + + 8 + 1 + + + FERRF6 + Stream 6 FIFO error interrupt flag + + 6 + 1 + + + FDTF5 + Stream 5 full data transfer interrupt flag + + 5 + 1 + + + HDTF5 + Stream 5 half data transfer interrupt flag + + 4 + 1 + + + DTERRF5 + Stream 5 transfer error interrupt flag + + 3 + 1 + + + DMERRF5 + Stream 5 direct mode error interrupt flag + + 2 + 1 + + + FERRF5 + Stream 5 FIFO error interrupt flag + + 0 + 1 + + + + + CLR1 + CLR1 + Interrupt flag clear register1 + + 0x8 + 0x20 + read-write + 0x00000000 + + + FDTFC4 + Stream 4 clear full data transfer complete interrupt flag + + 27 + 1 + + + HDTFC4 + Stream 4 clear half data transfer interrupt flag + + 26 + 1 + + + DTERRFC4 + Stream 4 clear transfer error interrupt flag + + 25 + 1 + + + DMERRFC4 + Stream 4 clear direct mode error interrupt flag + + 24 + 1 + + + FERRFC4 + Stream 4 clear FIFO error interrupt flag + + 22 + 1 + + + FDTFC3 + Stream 3 clear full data transfer complete interrupt flag + + 21 + 1 + + + HDTFC3 + Stream 3 clear half data transfer interrupt flag + + 20 + 1 + + + DTERRFC3 + Stream 3 clear transfer error interrupt flag + + 19 + 1 + + + DMERRFC3 + Stream 3 clear direct mode error interrupt flag + + 18 + 1 + + + FERRFC3 + Stream 3 clear FIFO error interrupt flag + + 16 + 1 + + + FDTFC2 + Stream 2 clear full data transfer complete interrupt flag + + 11 + 1 + + + HDTFC2 + Stream 2 clear half data transfer interrupt flag + + 10 + 1 + + + DTERRFC2 + Stream 2 clear transfer error interrupt flag + + 9 + 1 + + + DMERRFC2 + Stream 2 clear direct mode error interrupt flag + + 8 + 1 + + + FERRFC2 + Stream 2 clear FIFO error interrupt flag + + 6 + 1 + + + FDTFC1 + Stream 1 clear full data transfer complete interrupt flag + + 5 + 1 + + + HDTFC1 + Stream 1 clear half data transfer interrupt flag + + 4 + 1 + + + DTERRFC1 + Stream 1 clear transfer error interrupt flag + + 3 + 1 + + + DMERRFC1 + Stream 1 clear direct mode error interrupt flag + + 2 + 1 + + + FERRFC1 + Stream 1 clear FIFO error interrupt flag + + 0 + 1 + + + + + CLR2 + CLR2 + Interrupt flag clear register2 + + 0xC + 0x20 + read-write + 0x00000000 + + + FDTFC8 + Stream 8 clear full data transfer complete interrupt flag + + 27 + 1 + + + HDTFC8 + Stream 8 clear half data transfer interrupt flag + + 26 + 1 + + + DTERRFC8 + Stream 8 clear transfer error interrupt flag + + 25 + 1 + + + DMERRFC8 + Stream 8 clear direct mode error interrupt flag + + 24 + 1 + + + FERRFC8 + Stream 8 clear FIFO error interrupt flag + + 22 + 1 + + + FDTFC7 + Stream 7 clear full data transfer complete interrupt flag + + 21 + 1 + + + HDTFC7 + Stream 7 clear half data transfer interrupt flag + + 20 + 1 + + + DTERRFC7 + Stream 7 clear transfer error interrupt flag + + 19 + 1 + + + DMERRFC7 + Stream 7 clear direct mode error interrupt flag + + 18 + 1 + + + FERRFC7 + Stream 7 clear FIFO error interrupt flag + + 16 + 1 + + + FDTFC6 + Stream 6 clear full data transfer complete interrupt flag + + 11 + 1 + + + HDTFC6 + Stream 6 clear half data transfer interrupt flag + + 10 + 1 + + + DTERRFC6 + Stream 6 clear transfer error interrupt flag + + 9 + 1 + + + DMERRFC6 + Stream 6 clear direct mode error interrupt flag + + 8 + 1 + + + FERRFC6 + Stream 6 clear FIFO error interrupt flag + + 6 + 1 + + + FDTFC5 + Stream 5 clear full data transfer complete interrupt flag + + 5 + 1 + + + HDTFC5 + Stream 5 clear half data transfer interrupt flag + + 4 + 1 + + + DTERRFC5 + Stream 5 clear transfer error interrupt flag + + 3 + 1 + + + DMERRFC5 + Stream 5 clear direct mode error interrupt flag + + 2 + 1 + + + FERRFC5 + Stream 5 clear FIFO error interrupt flag + + 0 + 1 + + + + + S1CTRL + S1CTRL + stream 1 control + register + 0x10 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S1DTCNT + S1DTCNT + stream 1 number of data + register + 0x14 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S1PADDR + S1PADDR + stream 1 peripheral address + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S1M0ADDR + S1M0ADDR + stream 1 memory 0 address + register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S1M1ADDR + S1M1ADDR + stream 1 memory 1 address + register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S1FCTRL + S1FCTRL + stream 1 FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S2CTRL + S2CTRL + stream 2 control + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S2DTCNT + S2DTCNT + stream 2 number of data + register + 0x2C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S2PADDR + S2PADDR + stream 2 peripheral address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S2M0ADDR + S2M0ADDR + stream 2 memory 0 address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S2M1ADDR + S2M1ADDR + stream 2 memory 1 address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S2FCTRL + S2FCTRL + stream 2 FIFO control register + 0x3C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S3CTRL + S3CTRL + stream 3 control + register + 0x40 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S3DTCNT + S3DTCNT + stream 3 number of data + register + 0x44 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S3PADDR + S3PADDR + stream 3 peripheral address + register + 0x48 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S3M0ADDR + S3M0ADDR + stream 3 memory 0 address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S3M1ADDR + S3M1ADDR + stream 3 memory 1 address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S3FCTRL + S3FCTRL + stream 3 FIFO control register + 0x54 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S4CTRL + S4CTRL + stream 4 control + register + 0x58 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S4DTCNT + S4DTCNT + stream 4 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S4PADDR + S4PADDR + stream 4 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S4M0ADDR + S4M0ADDR + stream 4 memory 0 address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S4M1ADDR + S4M1ADDR + stream 4 memory 1 address + register + 0x68 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S4FCTRL + S4FCTRL + stream 4 FIFO control register + 0x6C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S5CTRL + S5CTRL + stream 5 control + register + 0x70 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S5DTCNT + S5DTCNT + stream 5 number of data + register + 0x74 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S5PADDR + S5PADDR + stream 5 peripheral address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S5M0ADDR + S5M0ADDR + stream 5 memory 0 address + register + 0x7C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S5M1ADDR + S5M1ADDR + stream 5 memory 1 address + register + 0x80 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S5FCTRL + S5FCTRL + stream 5 FIFO control register + 0x84 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S6CTRL + S6CTRL + stream 6 control + register + 0x88 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S6DTCNT + S6DTCNT + stream 6 number of data + register + 0x8C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S6PADDR + S6PADDR + stream 6 peripheral address + register + 0x90 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S6M0ADDR + S6M0ADDR + stream 6 memory 0 address + register + 0x94 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S6M1ADDR + S6M1ADDR + stream 6 memory 1 address + register + 0x98 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S6FCTRL + S6FCTRL + stream 6 FIFO control register + 0x9C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S7CTRL + S7CTRL + stream 7 control + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S7DTCNT + S7DTCNT + stream 7 number of data + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S7PADDR + S7PADDR + stream 7 peripheral address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S7M0ADDR + S7M0ADDR + stream 7 memory 0 address + register + 0xAC + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S7M1ADDR + S7M1ADDR + stream 7 memory 1 address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S7FCTRL + S7FCTRL + stream 7 FIFO control register + 0xB4 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S8CTRL + S8CTRL + stream 8 control + register + 0xB8 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S8DTCNT + S8DTCNT + stream 8 number of data + register + 0xBC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S8PADDR + S8PADDR + stream 8 peripheral address + register + 0xC0 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S8M0ADDR + S8M0ADDR + stream 8 memory 0 address + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S8M1ADDR + S8M1ADDR + stream 8 memory 1 address + register + 0xC8 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S8FCTRL + S8FCTRL + stream 8 FIFO control register + 0xCC + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + LLCTRL + LLCTRL + DMA Link List Control Register + 0xD0 + 0x20 + 0x00000000 + + + S1LLEN + Stream 1 link list enable + 0 + 1 + read-write + + + S2LLEN + Stream 2 link list enable + 1 + 1 + read-write + + + S3LLEN + Stream 3 link list enable + 2 + 1 + read-write + + + S4LLEN + Stream 4 link list enable + 3 + 1 + read-write + + + S5LLEN + Stream 5 link list enable + 4 + 1 + read-write + + + S6LLEN + Stream 6 link list enable + 5 + 1 + read-write + + + S7LLEN + Stream 7 link list enable + 6 + 1 + read-write + + + S8LLEN + Stream 8 link list enable + 7 + 1 + read-write + + + + + S1LLP + S1LLP + Stream 1 Link List Pointer + 0xD4 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S2LLP + S2LLP + Stream 2 Link List Pointer + 0xD8 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S3LLP + S3LLP + Stream 3 Link List Pointer + 0xDC + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S4LLP + S4LLP + Stream 4 Link List Pointer + 0xE0 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S5LLP + S5LLP + Stream 5 Link List Pointer + 0xE4 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S6LLP + S6LLP + Stream 6 Link List Pointer + 0xE8 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S7LLP + S7LLP + Stream 7 Link List Pointer + 0xEC + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S8LLP + S8LLP + Stream 8 Link List Pointer + 0xF0 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S2DCTRL + S2DCTRL + EDMA 2D Transfer Control Register + 0xF4 + 0x20 + 0x00000000 + + + S1_2DEN + Stream 1 2D transfer enable + 0 + 1 + read-write + + + S2_2DEN + Stream 2 2D transfer enable + 1 + 1 + read-write + + + S3_2DEN + Stream 3 2D transfer enable + 2 + 1 + read-write + + + S4_2DEN + Stream 4 2D transfer enable + 3 + 1 + read-write + + + S5_2DEN + Stream 5 2D transfer enable + 4 + 1 + read-write + + + S6_2DEN + Stream 6 2D transfer enable + 5 + 1 + read-write + + + S7_2DEN + Stream 7 2D transfer enable + 6 + 1 + read-write + + + S8_2DEN + Stream 8 2D transfer enable + 7 + 1 + read-write + + + + + S1_2DCNT + S1_2DCNT + Stream 1 2D Transfer Count + 0xF8 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S1_STRIDE + S1_STRIDE + Stream 1 2D Transfer Stride + 0xFC + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S2_2DCNT + S2_2DCNT + Stream 2 2D Transfer Count + 0x100 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S2_STRIDE + S2_STRIDE + Stream 2 2D Transfer Stride + 0x104 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S3_2DCNT + S3_2DCNT + Stream 3 2D Transfer Count + 0x108 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S3_STRIDE + S3_STRIDE + Stream 3 2D Transfer Stride + 0x10C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S4_2DCNT + S4_2DCNT + Stream 4 2D Transfer Count + 0x110 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S4_STRIDE + S4_STRIDE + Stream 4 2D Transfer Stride + 0x114 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S5_2DCNT + S5_2DCNT + Stream 5 2D Transfer Count + 0x118 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S5_STRIDE + S5_STRIDE + Stream 5 2D Transfer Stride + 0x11C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S6_2DCNT + S6_2DCNT + Stream 6 2D Transfer Count + 0x120 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S6_STRIDE + S6_STRIDE + Stream 6 2D Transfer Stride + 0x124 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S7_2DCNT + S7_2DCNT + Stream 7 2D Transfer Count + 0x128 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S7_STRIDE + S7_STRIDE + Stream 7 2D Transfer Stride + 0x12C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S8_2DCNT + S8_2DCNT + Stream 8 2D Transfer Count + 0x130 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S8_STRIDE + S8_STRIDE + Stream 8 2D Transfer Stride + 0x134 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + SYNCEN + SYNCEN + Sync Enable + 0x138 + 0x20 + 0x00000000 + + + S1SYNC + Stream 1 sync enable + 0 + 1 + read-write + + + S2SYNC + Stream 2 sync enable + 1 + 1 + read-write + + + S3SYNC + Stream 3 sync enable + 2 + 1 + read-write + + + S4SYNC + Stream 4 sync enable + 3 + 1 + read-write + + + S5SYNC + Stream 5 sync enable + 4 + 1 + read-write + + + S6SYNC + Stream 6 sync enable + 5 + 1 + read-write + + + S7SYNC + Stream 7 sync enable + 6 + 1 + read-write + + + S8SYNC + Stream 8 sync enable + 7 + 1 + read-write + + + + + MUXSEL + MUXSEL + EDMA MUX Table Selection + 0x13C + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXS1CTRL + MUXS1CTRL + Stream 1 Configuration Register + 0x140 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS2CTRL + MUXS2CTRL + Stream 2 Configuration Register + 0x144 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS3CTRL + MUXS3CTRL + Stream 3 Configuration Register + 0x148 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS4CTRL + MUXS4CTRL + Stream 4 Configuration Register + 0x14C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS5CTRL + MUXS5CTRL + Stream x Configuration Register + 0x150 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS6CTRL + MUXS6CTRL + Stream 6 Configuration Register + 0x154 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS7CTRL + MUXS7CTRL + Stream 7 Configuration Register + 0x158 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS8CTRL + MUXS8CTRL + Stream 8 Configuration Register + 0x15C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x160 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x164 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x168 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x16C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x170 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + SYNCOVF8 + Synchronizaton overrun interrupt flag + 7 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x174 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + SYNCOVFC8 + Clear synchronizaton overrun interrupt flag + 7 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x178 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x17C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA1 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 56 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 57 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 58 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 59 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 60 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 68 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 69 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026600 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR6DT + BPR6DT + Battery powered domain register + 0x64 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR7DT + BPR7DT + Battery powered domain register + 0x68 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR8DT + BPR8DT + Battery powered domain register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR9DT + BPR9DT + Battery powered domain register + 0x70 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR10DT + BPR10DT + Battery powered domain register + 0x74 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR11DT + BPR11DT + Battery powered domain register + 0x78 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR12DT + BPR12DT + Battery powered domain register + 0x7C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR13DT + BPR13DT + Battery powered domain register + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR14DT + BPR14DT + Battery powered domain register + 0x84 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR15DT + BPR15DT + Battery powered domain register + 0x88 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR16DT + BPR16DT + Battery powered domain register + 0x8C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR17DT + BPR17DT + Battery powered domain register + 0x90 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR18DT + BPR18DT + Battery powered domain register + 0x94 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR19DT + BPR19DT + Battery powered domain register + 0x98 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR20DT + BPR20DT + Battery powered domain register + 0x9C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + WINF + Window value update complete flag + 2 + 1 + + + + + WIN + WIN + Window register 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control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + CM3_OUTPUT + CM3_OUTPUT + Channel output mode register + 0x70 + 0x20 + read-write + 0x00000000 + + + C5OSEN + Channel 5 output switch enable + 7 + 1 + + + C5OCTRL + Channel 5 output control + 4 + 3 + + + C5OBEN + Channel 5 output buffer enable + 3 + 1 + + + C5OIEN + Channel 5 output immediately enable + 2 + 1 + + + + + C5DT + C5DT + Channel 5 data register + 0x74 + 0x20 + read-write + 0x00000000 + + + C5DT + Channel 5 data register + 0 + 16 + + + + + + + TMR8 + 0x40010400 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 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Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + C4SWTR + Channel 4 event triggered by software + 4 + 1 + + + C3SWTR + Channel 3 event triggered by software + 3 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 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Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + + TMR10 + General purpose timer + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + + + TMR11 + 0x40014800 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + TMR13 + 0x40001C00 + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + + TMR14 + 0x40002000 + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + ACC + HSI Auto Clock Calibration + ACC + 0x40017400 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + SOFSEL + SOF Select + read-write + 2 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI4 global interrupt + 84 + + + + I2S2_EXT + 0x40017800 + + + I2S3_EXT + 0x40017C00 + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + ID3_0 + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + RDY + ADC ready to conversion flag + 6 + 1 + read-only + + + OCCO + Ordinary channel conversion overflow flag + 5 + 1 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + OCCE + Ordinary channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCCOIEN + Ordinary channel conversion overflow interrupt enable + 26 + 1 + + + CRSEL + Conversion resolution select + 24 + 2 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + OCCEIEN + Ordinary channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 31 + 1 + + + OCSWTRG + Ordinary channel software conversion trigger + 30 + 1 + + + OCETE + Ordinary channel external trigger edge select + 28 + 2 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 24 + 4 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 23 + 1 + + + PCSWTRG + Preempted channel software conversion trigger + 22 + 1 + + + PCETE + Preempted channel external trigger edge select + 20 + 2 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 16 + 4 + + + DTALIGN + Data alignment + 11 + 1 + + + EOCSFEN + Each ordinary channel conversion set OCCE flag enable + 10 + 1 + + + OCDRCEN + Ordinary channel DMA request continuation enable for independent mode + 9 + 1 + + + OCDMAEN + Ordinary channel DMA transfer enable for independent mode + 8 + 1 + + + ADABRT + ADC conversion abort + 4 + 1 + + + ADCALINIT + Initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT18 + Selection sample time of channel ADC_IN18 + 24 + 3 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + CALVAL + CALVAL + Calibration value register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALVAL + A/D Calibration value + 0 + 7 + + + + + + + ADC2 + 0x40012100 + + ADC + ADC2 global interrupts + 18 + + + + ADC3 + 0x40012200 + + ADC + ADC3 global interrupts + 18 + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CSTS + CSTS + Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + RDY3 + ADC ready to conversion flag of ADC3 + 22 + 1 + + + OCCO3 + Ordinary channel conversion overflow flag of ADC3 + 21 + 1 + + + OCCS3 + Ordinary channel conversion start flag of ADC3 + 20 + 1 + + + PCCS3 + Preempted channel conversion start flag of ADC3 + 19 + 1 + + + PCCE3 + Preempted channels conversion end flag of ADC3 + 18 + 1 + + + OCCE3 + Ordinary channels conversion end flag of ADC3 + 17 + 1 + + + VMOR3 + Voltage monitoring out of range flag of ADC3 + 16 + 1 + + + RDY2 + ADC ready to conversion flag of ADC2 + 14 + 1 + + + OCCO2 + Ordinary channel conversion overflow flag of ADC2 + 13 + 1 + + + OCCS2 + Ordinary channel conversion start flag of ADC2 + 12 + 1 + + + PCCS2 + Preempted channel conversion start flag of ADC2 + 11 + 1 + + + PCCE2 + Preempted channels conversion end flag of ADC2 + 10 + 1 + + + OCCE2 + Ordinary channels conversion end flag of ADC2 + 9 + 1 + + + VMOR2 + Voltage monitoring out of range flag of ADC2 + 8 + 1 + + + RDY1 + ADC ready to conversion flag of ADC1 + 6 + 1 + + + OCCO1 + Ordinary channel conversion overflow flag of ADC1 + 5 + 1 + + + OCCS1 + Ordinary channel conversion start flag of ADC1 + 4 + 1 + + + PCCS1 + Preempted channel conversion start flag of ADC1 + 3 + 1 + + + PCCE1 + Preempted channels conversion end flag of ADC1 + 2 + 1 + + + OCCE1 + Ordinary channels conversion end flag of ADC1 + 1 + 1 + + + VMOR1 + Voltage monitoring out of range flag of ADC1 + 0 + 1 + + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + MSDMASEL_H + High bit of ordinary channel DMA transfer mode select for master slave mode + 28 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + VBATEN + VBAT enable + 22 + 1 + + + ADCDIV + ADC division + 16 + 4 + + + MSDMASEL_L + Low bit of ordinary channel DMA transfer mode select for master slave mode + 14 + 2 + + + MSDRCEN + Ordinary channel DMA request continuation enable for master slave mode + 13 + 1 + + + ASISEL + Adjacent ADC sampling interval select for ordinary shifting mode + 8 + 4 + + + MSSEL + Master slave mode select + 0 + 5 + + + + + CODT + CODT + Common Ordinary data register + 0x8 + 0x20 + read-only + 0x00000000 + + + CODTH + Ordinary conversion high halfword data for master slave mode + 16 + 16 + + + CODTL + Ordinary conversion low halfword data for master slave mode + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC 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LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + FMSEL14 + Filter mode select + 14 + 1 + + + FMSEL15 + Filter mode select + 15 + 1 + + + FMSEL16 + Filter mode select + 16 + 1 + + + FMSEL17 + Filter mode select + 17 + 1 + + + FMSEL18 + Filter mode select + 18 + 1 + + + FMSEL19 + Filter mode select + 19 + 1 + + + FMSEL20 + Filter mode select + 20 + 1 + + + FMSEL21 + Filter mode select + 21 + 1 + + + FMSEL22 + Filter mode select + 22 + 1 + + + FMSEL23 + Filter mode select + 23 + 1 + + + FMSEL24 + Filter mode select + 24 + 1 + + + FMSEL25 + Filter mode select + 25 + 1 + + + FMSEL26 + Filter mode select + 26 + 1 + + + FMSEL27 + Filter mode select + 27 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + FBWSEL14 + Filter bit width select + 14 + 1 + + + FBWSEL15 + Filter bit width select + 15 + 1 + + + FBWSEL16 + Filter bit width select + 16 + 1 + + + FBWSEL17 + Filter bit width select + 17 + 1 + + + FBWSEL18 + Filter bit width select + 18 + 1 + + + FBWSEL19 + Filter bit width select + 19 + 1 + + + FBWSEL20 + Filter bit width select + 20 + 1 + + + FBWSEL21 + Filter bit width select + 21 + 1 + + + FBWSEL22 + Filter bit width select + 22 + 1 + + + FBWSEL23 + Filter bit width select + 23 + 1 + + + FBWSEL24 + Filter bit width select + 24 + 1 + + + FBWSEL25 + Filter bit width select + 25 + 1 + + + FBWSEL26 + Filter bit width select + 26 + 1 + + + FBWSEL27 + Filter bit width select + 27 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + FRFSEL14 + Filter relation FIFO select + 14 + 1 + + + FRFSEL15 + Filter relation FIFO select + 15 + 1 + + + FRFSEL16 + Filter relation FIFO select + 16 + 1 + + FRFSEL17 + Filter relation FIFO select + 17 + 1 + + + FRFSEL18 + Filter relation FIFO select + 18 + 1 + + + FRFSEL19 + Filter relation FIFO select + 19 + 1 + + + FRFSEL20 + Filter relation FIFO select + 20 + 1 + + + FRFSEL21 + Filter relation FIFO select + 21 + 1 + + + FRFSEL22 + Filter relation FIFO select + 22 + 1 + + + FRFSEL23 + Filter relation FIFO select + 23 + 1 + + + FRFSEL24 + Filter relation FIFO select + 24 + 1 + + + FRFSEL25 + Filter relation FIFO select + 25 + 1 + + + FRFSEL26 + Filter relation FIFO select + 26 + 1 + + + FRFSEL27 + Filter relation FIFO select + 27 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + FAEN14 + Filter activate enable + 14 + 1 + + FAEN15 + Filter activate enable + 15 + 1 + + + FAEN16 + Filter activate enable + 16 + 1 + + + FAEN17 + Filter activate enable + 17 + 1 + + + FAEN18 + Filter activate enable + 18 + 1 + + + FAEN19 + Filter activate enable + 19 + 1 + + + FAEN20 + Filter activate enable + 20 + 1 + + + FAEN21 + Filter activate enable + 21 + 1 + + + FAEN22 + Filter activate enable + 22 + 1 + + + FAEN23 + Filter activate enable + 23 + 1 + + + FAEN24 + Filter activate enable + 24 + 1 + + + FAEN25 + Filter activate enable + 25 + 1 + + + FAEN26 + Filter activate enable + 26 + 1 + + + FAEN27 + Filter activate enable + 27 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data 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bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F24FB2 + F24FB2 + Filter bank 24 filtrate bit register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F25FB1 + F25FB1 + Filter bank 25 filtrate bit register 1 + 0x308 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F25FB2 + F25FB2 + Filter bank 25 filtrate bit register 2 + 0x30C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F26FB1 + F26FB1 + Filter bank 26 filtrate bit register 1 + 0x310 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F26FB2 + F26FB2 + Filter bank 26 filtrate bit register 2 + 0x314 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F27FB1 + F27FB1 + Filter bank 27 filtrate bit register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F27FB2 + F27FB2 + Filter bank 27 filtrate bit register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 63 + + + CAN2_RX0 + CAN2 RX0 interrupt + 64 + + + CAN2_RX1 + CAN2 RX1 interrupt + 65 + + + CAN2_SE + CAN2 SE interrupt + 66 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D1DMAUDRIEN + DAC1 DMA underrun interrupt enable + 13 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + D2DMAUDRIEN + DAC2 DMA underrun interrupt enable + 29 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + STS + STS + DAC2 status register + (DAC_STS) + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR1 + DAC1 DMA underrun flag + 13 + 1 + + + DMAUDR2 + DAC2 DMA underrun flag + 29 + 1 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + Product ID + 0 + 32 + + + + + CTRL + CTRL + DEBUG CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + + + APB1_PAUSE + APB1_PAUSE + DEBUG APB1 PAUSE + 0x8 + 0x20 + read-write + 0x0 + + + TMR2_PAUSE + TMR2_PAUSE + 0 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 1 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 2 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 3 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 4 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 5 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 6 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 7 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 8 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 10 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 11 + 1 + + + WDT_PAUSE + WDT_PAUSE + 12 + 1 + + + ERTC512_PAUSE + ERTC512_PAUSE + 15 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 24 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 25 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 26 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 27 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 28 + 1 + + + + + APB2_PAUSE + APB2_PAUSE + DEBUG APB2 PAUSE + 0xC + 0x20 + read-write + 0x0 + + + TMR1_PAUSE + TMR1_PAUSE + 0 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 1 + 1 + + + TMR20_PAUSE + TIM20_PAUSE + 6 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 16 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 17 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 18 + 1 + + + + + SER_ID + SER_ID + SERIES ID + 0x20 + 0x20 + read-only + 0x0 + + + REV_ID + version ID + 0 + 3 + + + SER_ID + series ID + 8 + 8 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000330 + + + NZW_BST_STS + Flash non-zero wait area boost status + 13 + 1 + read-only + + + NZW_BST + Flash non-zero wait area boost + 12 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + nWDT_DEPSLP + WDT deep sleep + 7 + 1 + + + nWDT_STDBY + WDT standby + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS0 + EPPS0 + Erase/program protection status register 0 + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + EPPS1 + EPPS1 + Erase/program protection status register 1 + 0x2C + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + CONTR + CONTR + Flash continue read register + 0x58 + 0x20 + read-write + 0x00000080 + + + FCONTR_EN + Flash continue read enable + 31 + 1 + + + + + DIVR + DIVR + Flash divider register + 0x60 + 0x20 + 0x00000022 + + + FDIV + Flash divider + 0 + 2 + read-write + + + FDIV_STS + Flash divider status + 4 + 2 + read-only + + + + + SLIB_STS2 + SLIB_STS2 + sLib status 2 register + 0xC8 + 0x20 + 0x0000FFFF + + + SLIB_INST_SS + sLib instruction start sector + 0 + 16 + read-only + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 16 + read-only + + + SLIB_ES + sLib end sector + 16 + 16 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE0 + SLIB_SET_RANGE0 + Configure sLib range register 0 + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 16 + + + SLIB_ES_SET + sLib end sector setting + 16 + 16 + + + + + SLIB_SET_RANGE1 + SLIB_SET_RANGE1 + Configure sLib range register 1 + 0xE4 + 0x20 + 0x00000000 + write-only + + + SLIB_ISS_SET + sLib instruction start sector setting + 0 + 16 + + + SET_SLIB_STRT + sLib start setting + 31 + 1 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTG1_GLOBAL + USB on-the-go full speed + USB_OTG1 + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTG1 + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTG1 + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTG1 + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + USB_OTG2_GLOBAL + USB on the go full speed + USB_OTG2 + 0x40040000 + + 0x0 + 0x400 + registers + + + OTGFS2 + USB On The Go FS2 global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG2_HOST + USB on the go full speed + USB_OTG2 + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG2_DEVICE + USB on the go full speed + USB_OTG2 + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG2_PWRCLK + USB on the go full speed + USB_OTG2 + 0x40040E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + SWAP_XMC + XMC address mapping swap + 10 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + MII or RMII selection + bits + 23 + 1 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PF15_UH + PF15 ultra high sourcing/sinking strength + 10 + 1 + + + PF14_UH + PF14 ultra high sourcing/sinking strength + 9 + 1 + + + PD15_UH + PD15 ultra high sourcing/sinking strength + 8 + 1 + + + PD14_UH + PD14 ultra high sourcing/sinking strength + 7 + 1 + + + PD13_UH + PD13 ultra high sourcing/sinking strength + 6 + 1 + + + PD12_UH + PD12 ultra high sourcing/sinking strength + 5 + 1 + + + PB10_UH + PB10 ultra high sourcing/sinking strength + 2 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + PB3_UH + PB3 ultra high sourcing/sinking strength + 0 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + ACTR + ACTR + AC timing control register + 0x14 + 0x20 + read-write + 0x0000000F + + + CSDLY + CS delay + 0 + 4 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 6 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 6 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + QSPI2 + 0xA0002000 + + QSPI2 + QSPI2 global interrupt + 91 + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x100 + registers + + + EMAC + Ethernet mac global interrupt + 61 + + + + MACCTRL + MACCTRL + Ethernet MAC configuration register + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + DC + Deferral check + 4 + 1 + + + BL + Back-off limit + 5 + 2 + + + ACS + Automatic pad/CRC + stripping + 7 + 1 + + + DR + Disable retry + 9 + 1 + + + IPC + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + DRO + Disable receive own + 13 + 1 + + + FES + Fast EMAC speed + 14 + 1 + + + DCS + Disable carrier sense + 16 + 1 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + + + MACFRMF + MACFRMF + Ethernet MAC frame filter register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Promiscuous mode + 0 + 1 + + + HUC + Hash unicast + 1 + 1 + + + HMC + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PMC + Pass multicast + 4 + 1 + + + DBF + Disable broadcast frames + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTH + MACHTH + Ethernet MAC hash table high register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTL + MACHTL + Ethernet MAC hash table low register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIADDR + MACMIIADDR + Ethernet MAC MII address register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MII + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDT + MACMIIDT + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCTRL + MACFCTRL + Ethernet MAC flow control register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + Flow control busy/back pressure + activate + 0 + 1 + + + ETF + Enable transmit flow control + + 1 + 1 + + + ERF + Enable receive flow control + + 2 + 1 + + + DUP + Detect unicast pause frame + 3 + 1 + + + PLT + Pause low threshold + 4 + 2 + + + DZQP + Disable zero-quanta pause + 7 + 1 + + + PT + Pass time + 16 + 16 + + + + + MACVLT + MACVLT + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + ETV + Enable 12-bit VLAN tag comparison + 16 + 1 + + + + + MACRWFF + MACRWFF + Ethernet MAC remote wakeup frame filter register + 0x28 + 0x20 + read-write + 0x00000000 + + + MACPMTCTRLSTS + MACPMTCTRLSTS + Ethernet MAC PMT control and status register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + EMP + Enable magic packet + 1 + 1 + + + ERWF + Enable remote wakeup frame + 2 + 1 + + + RMP + Received magic packet + 5 + 1 + + + RRWF + Recevied remote wakeup frame + 6 + 1 + + + GUC + Global unicast + 9 + 1 + + + RWFFPR + Remote wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACISTS + MACISTS + Ethernet MAC interrupt status register + 0x38 + 0x20 + read-write + 0x00000000 + + + PIS + PMT interrupt status + 3 + 1 + + + MIS + MMC interrupt status + 4 + 1 + + + MRIS + MMC receive interrupt status + 5 + 1 + + + MTIS + MMC transmit interrupt status + 6 + 1 + + + TIS + Timestamp interrupt status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + PIM + PMT interrupt mask + 3 + 1 + + + TIM + Timestamp interrupt mask + 9 + 1 + + + + + MACA0H + MACA0H + Ethernet MAC address 0 high register + 0x40 + 0x20 + 0x0010FFFF + + + MA0H + MAC address0 high + 0 + 16 + read-write + + + AE + Address enable + 31 + 1 + read-only + + + + + MACA0L + MACA0L + Ethernet MAC address 0 low register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MA0L + MAC address0 low + 0 + 32 + + + + + MACA1H + MACA1H + Ethernet MAC address 1 high register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1L + MACA1L + Ethernet MAC address1 low register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MA1L + MAC address1 low + 0 + 32 + + + + + MACA2H + MACA2H + Ethernet MAC address 2 high register + 0x50 + 0x20 + read-write + 0x0050 + + + MA2H + MAC address 2 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2L + MACA2L + Ethernet MAC address 2 low register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MA2L + MAC address2 low + 0 + 31 + + + + + MACA3H + MACA3H + Ethernet MAC address 3 high register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3L + MACA3L + Ethernet MAC address 3 low register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MA3L + MAC address3 low + 0 + 32 + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x100 + registers + + + + MMCCTRL + MMCCTRL + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RC + Reset counter + 0 + 1 + + + SCR + Stop counter rollover + 1 + 1 + + + RR + Reset on read + 2 + 1 + + + FMC + Freeze MMC counter + 31 + 1 + + + + + MMCRI + MMCRI + Ethernet MMC receive interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCE + Received frames CRC error + 5 + 1 + + + RFAE + Received frames alignment error + 6 + 1 + + + RGUF + Received good unicast frames + 17 + 1 + + + + + MMCTI + MMCTI + Ethernet MMC transmit interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + TSCGFCI + Transmit single collision good frame + counter interrupt + 14 + 1 + + + TGFMSC + Transmit good frames more single + collision + 15 + 1 + + + TGF + Transmitted good frames + 21 + 1 + + + + + MMCRIM + MMCRIM + Ethernet MMC receive interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + RCEFCIM + Received CRC error frame counter interrupt + mask + 5 + 1 + + + RAEFACIM + Received alignment error frame alignment + counter interrupt mask + 6 + 1 + + + RUGFCIM + Received unicast good frame counter + interrupt mask + 17 + 1 + + + + + MMCTIM + MMCTIM + Ethernet MMC transmit interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSCGFCIM + Transmit single collision good frame + counter interrupt mask + 14 + 1 + + + TMCGFCIM + Transmit multiple collision good frame + counter interrupt mask + 15 + 1 + + + TGFCIM + Transmitted good frame counter interrupt + mask + 21 + 1 + + + + + MMCTFSCC + MMCTFSCC + Ethernet MMC transmitted good frames after a single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames single + collision counter + 0 + 32 + + + + + MMCTFMSCC + MMCTFMSCC + Ethernet MMC transmitted good frames after more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frame more single + collision counter + 0 + 32 + + + + + MMCTFCNT + MMCTFCNT + Ethernet MMC transmitted good frames counter register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECNT + MMCRFCECNT + Ethernet MMC received frames with CRC error counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCEC + Received frames CRC error counter + 0 + 32 + + + + + MMCRFAECNT + MMCRFAECNT + Ethernet MMC received frames with alignment error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames alignment error counter + 0 + 32 + + + + + MMCRGUFCNT + MMCRGUFCNT + MMC received good unicast frames counter register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x100 + registers + + + + PTPTSCTRL + PTPTSCTRL + Ethernet PTP time stamp control register + 0x0 + 0x20 + read-write + 0x2000 + + + TE + Timestamp enable + 0 + 1 + + + TFCU + Timestamp fine or coarse + update + 1 + 1 + + + TI + Timestamp initialize + 2 + 1 + + + TU + Timestamp update + 3 + 1 + + + TITE + Timestamp interrupt trigger + enable + 4 + 1 + + + ARU + Addend register update + 5 + 1 + + + ETAF + Enable timestamp for all frames + 8 + 1 + + + TDBRC + Timestamp digital or binary + rollover control + 9 + 1 + + + EPPV2F + Enable PTP packet processing for + version2 format + 10 + 1 + + + EPPEF + Enable processing of PTP + over EMAC frames + 11 + 1 + + + EPPFSIP6U + Enable processing of PTP frames + sent over IPv6-UDP + 12 + 1 + + + EPPFSIP4U + Enable processing of PTP frames + sent over IPv4-UDP + 13 + 1 + + + ETSFEM + Enable timestamp snapshot for + event message + 14 + 1 + + + ESFMRTM + Enable snapshot for message + relevant to master + 15 + 1 + + + SPPFTS + Select PTP packet for taking snapshot + 16 + 2 + + + EMAFPFF + Enable MAC address for PTP frame filtering + 18 + 1 + + + + + PTPSSINC + PTPSSINC + Ethernet PTP subsecond increment register + 0x4 + 0x20 + read-write + 0x00000000 + + + SSIV + Sub-second increment value + 0 + 8 + + + + + PTPTSH + PTPTSH + Ethernet PTP time stamp high register + 0x8 + 0x20 + read-only + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSL + PTPTSL + Ethernet PTP time stamp low register + 0xC + 0x20 + read-only + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSHUD + PTPTSHUD + Ethernet PTP time stamp high update register + 0x10 + 0x20 + read-write + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSLUD + PTPTSLUD + Ethernet PTP time stamp low update register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSAD + PTPTSAD + Ethernet PTP time stamp addend register + 0x18 + 0x20 + read-write + 0x00000000 + + + TAR + Timestamp addend register + 0 + 32 + + + + + PTPTTH + PTPTTH + Ethernet PTP target time high register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSR + Target time seconds register + 0 + 32 + + + + + PTPTTL + PTPTTL + Ethernet PTP target time low register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTLR + Target timestamp low register + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSO + Timestamp second overflow + 0 + 1 + + + TTTR + Timestamp target time reached + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control register + 0x2C + 0x20 + read-only + 0x00000000 + + + POFC + PPS Output frequency control + 0 + 4 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x100 + registers + + + + DMABM + DMABM + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x20101 + + + SWR + Software reset + 0 + 1 + + + DA + DMA Arbitration + 1 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + PBL + Programmable burst length + 8 + 6 + + + PR + Priority ratio + 14 + 2 + + + FB + Fixed burst + 16 + 1 + + + RDP + Rx DMA PBL + 17 + 6 + + + USP + Use separate PBL + 23 + 1 + + + PBLx8 + PNLx8 mode + 24 + 1 + + + AAB + Address-aligned beats + 25 + 1 + + + + + DMATPD + DMATPD + Ethernet DMA transmit poll demand register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPD + DMARPD + EHERNET DMA receive poll demand register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLADDR + DMARDLADDR + Ethernet DMA receive descriptor list address register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLADDR + DMATDLADDR + Ethernet DMA transmit descriptor list address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASTS + DMASTS + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TI + Transmit interrupt + 0 + 1 + read-write + + + TPS + Transmit process stopped + 1 + 1 + read-write + + + TBU + Transmit buffer unavailable + 2 + 1 + read-write + + + TJT + Transmit jabber timeout + 3 + 1 + read-write + + + OVF + Receive overflow + 4 + 1 + read-write + + + UNF + Transmit underflow + 5 + 1 + read-write + + + RI + Receive interrupt + 6 + 1 + read-write + + + RBU + Receive buffer unavailable + 7 + 1 + read-write + + + RPS + Receive process stopped + 8 + 1 + read-write + + + RWT + Receive watchdog timeout + 9 + 1 + read-write + + + ETI + Early transmit interrupt + 10 + 1 + read-write + + + FBEI + Fatal bus error interrupt + 13 + 1 + read-write + + + ERI + Early receive interrupt + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RS + Receive process state + 17 + 3 + read-only + + + TS + Transmit process state + 20 + 3 + read-only + + + EB + Error bits + 23 + 3 + read-only + + + MMI + MAC MMC interrupt + 27 + 1 + read-only + + + MPI + MAC PMT interrupt + 28 + 1 + read-only + + + TTI + Timestamp trigger interrupt + 29 + 1 + read-only + + + + + DMAOPM + DMAOPM + Ethernet DMA operation mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + SSR + Start or stop receive + 1 + 1 + + + OSF + Operate on second frame + 2 + 1 + + + RTC + Receive threshold control + 3 + 2 + + + FUGF + Forward undersized good frames + 6 + 1 + + + FEF + Forward error frames + 7 + 1 + + + SSTC + Start of stop transmission command + 13 + 1 + + + TTC + Transmit threshold control + 14 + 3 + + + FTF + Flush transmit FIFO + 20 + 1 + + + TSF + Transmit store and forward + 21 + 1 + + + DFRF + Disable flushing of received + frames + 24 + 1 + + + RSF + Receive store and forward + 25 + 1 + + + DT + Disable dropping of TCP/IP + checksum error frames + 26 + 1 + + + + + DMAIE + DMAIE + Ethernet DMA interrupt enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TSE + Transmit stopped enable + 1 + 1 + + + TUE + Transmit buffer unavailable enable + 2 + 1 + + + TJE + Transmit jabber timeout enable + 3 + 1 + + + OVE + Overflow interrupt enable + 4 + 1 + + + UNE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUE + Receive buffer unavailable enable + 7 + 1 + + + RSE + Receive stopped enable + 8 + 1 + + + RWTE + receive watchdog timeout enable + 9 + 1 + + + EIE + Early transmit interrupt enable + 10 + 1 + + + FBEE + Fatal bus error enable + 13 + 1 + + + ERE + Early receive interrupt + enable + 14 + 1 + + + AIE + Abnormal interrupt enable + 15 + 1 + + + NIE + Normal interrupt enable + 16 + 1 + + + + + DMAMFBOCNT + DMAMFBOCNT + Ethernet DMA missed frame and buffer overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames control + 0 + 16 + + + OBMFC + Overflow bit for missed frame + counter + 16 + 1 + + + OFC + Overflow frame counter + 17 + 11 + + + OBFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACTD + DMACTD + Ethernet DMA current host transmit descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address pointer + 0 + 32 + + + + + DMACRD + DMACRD + Ethernet DMA current host receive descriptor register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address pointer + 0 + 32 + + + + + DMACTBADDR + DMACTBADDR + Ethernet DMA current host transmit buffer address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address pointer + 0 + 32 + + + + + DMACRBADDR + DMACRBADDR + Ethernet DMA current host receive buffer address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address pointer + 0 + 32 + + + + + + + diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h new file mode 100644 index 000000000..ef4ec6dcf --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h @@ -0,0 +1,182 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//#define USB_VBUS_IGNORE +//#define USB_SOF_OUTPUT_ENABLE + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 1 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// USART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +// USB +#ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + #define USB_ID 0 + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_12 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_DM GPIO_PINS_11 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #elif BOARD_TUD_RHPORT == 1 + #define USB_ID 1 + #define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK + #define OTG_IRQ OTGFS2_IRQn + #define OTG_IRQ_HANDLER OTGFS2_IRQHandler + #define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_15 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + #define OTG_PIN_DM GPIO_PINS_14 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_12 + #endif +#endif + +#ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + #define USB_ID 0 + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_12 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_DM GPIO_PINS_11 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #elif BOARD_TUH_RHPORT == 1 + #define USB_ID 1 + #define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK + #define OTG_IRQ OTGFS2_IRQn + #define OTG_IRQ_HANDLER OTGFS2_IRQHandler + #define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_15 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + #define OTG_PIN_DM GPIO_PINS_14 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_12 + #endif +#endif + +// VBUS +static inline void board_vbus_sense_init(void) +{ + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUD_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif + #ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUH_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk new file mode 100644 index 000000000..823ae677d --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F437xM_FLASH.ld + +CFLAGS += \ + -DAT32F437ZMT7 diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c new file mode 100644 index 000000000..c238fff32 --- /dev/null +++ b/hw/bsp/at32f435_437/family.c @@ -0,0 +1,370 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f435_437_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_gpio_config(void); +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_botton_init(void); +int inHandlerMode(void); +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS2_IRQHandler(void) +{ + tusb_int_handler(1, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS2_WKUP_IRQHandler(void) +{ + tusb_int_handler(1, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock to 288Mhz */ + system_clock_config(); + + /* config usb io */ + usb_gpio_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* enable otgfs irq */ + //nvic_irq_enable(OTG_IRQ, 0, 0); + + /* vbus ignore */ + board_vbus_sense_init(); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* config led and key */ + led_and_botton_init(); + + /* config usart printf */ + uart_print_init(115200); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + acc_sof_select(ACC_SOF_OTG1); + #else + acc_sof_select(ACC_SOF_OTG2); + #endif + #endif + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + /* 216MHz */ + case 216000000: + crm_usb_clock_div_set(CRM_USB_DIV_4_5); + break; + + /* 240MHz */ + case 240000000: + crm_usb_clock_div_set(CRM_USB_DIV_5); + break; + + /* 264MHz */ + case 264000000: + crm_usb_clock_div_set(CRM_USB_DIV_5_5); + break; + + /* 288MHz */ + case 288000000: + crm_usb_clock_div_set(CRM_USB_DIV_6); + break; + + default: + break; + } + } +} + +void led_and_botton_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + gpio_bits_set(LED_PORT, LED_PIN); + gpio_bits_set(LED_PORT, GPIO_PINS_14); + gpio_bits_set(LED_PORT, GPIO_PINS_15); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +int inHandlerMode(void) +{ + return __get_IPSR(); +} + +void usb_gpio_config(void) +{ + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + /* dp and dm */ + gpio_init_struct.gpio_pins = OTG_PIN_DP | OTG_PIN_DM; + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DP_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DM_SOURCE, OTG_PIN_MUX); + #ifdef USB_SOF_OUTPUT_ENABLE + crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); + gpio_init_struct.gpio_pins = OTG_PIN_SOF; + gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + #endif + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + uint32_t board_millis(void) + { + return system_ticks; + } + void SVC_Handler(void) + { + } + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk new file mode 100644 index 000000000..47731b621 --- /dev/null +++ b/hw/bsp/at32f435_437/family.mk @@ -0,0 +1,45 @@ +# Submodules +AT32F435_437_SDK = hw/mcu/artery/at32f435_437 +DEPS_SUBMODULES += $(AT32F435_437_SDK) + +# AT32 SDK path +AT32F435_437_SDK_SRC = $(AT32F435_437_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F435_437 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_gpio.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_misc.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_usart.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_crm.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_acc.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_exint.c \ + $(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support/system_at32f435_437.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F435_437_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support \ + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f435_437.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f435_437/startup_at32f435_437.s b/hw/bsp/at32f435_437/startup_at32f435_437.s new file mode 100644 index 000000000..aa1aa3f4a --- /dev/null +++ b/hw/bsp/at32f435_437/startup_at32f435_437.s @@ -0,0 +1,569 @@ +/** + ****************************************************************************** + * @file startup_at32f435_437.s + * @brief at32f435_437 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word EDMA_Stream1_IRQHandler /* EDMA Stream 1 */ + .word EDMA_Stream2_IRQHandler /* EDMA Stream 2 */ + .word EDMA_Stream3_IRQHandler /* EDMA Stream 3 */ + .word EDMA_Stream4_IRQHandler /* EDMA Stream 4 */ + .word EDMA_Stream5_IRQHandler /* EDMA Stream 5 */ + .word EDMA_Stream6_IRQHandler /* EDMA Stream 6 */ + .word EDMA_Stream7_IRQHandler /* EDMA Stream 7 */ + .word ADC1_2_3_IRQHandler /* ADC1 & ADC2 & ADC3 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_I2S2EXT_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ + .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ + .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word EDMA_Stream8_IRQHandler /* EDMA Stream 8 */ + .word XMC_IRQHandler /* XMC */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word SPI3_I2S3EXT_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word EMAC_IRQHandler /* EMAC */ + .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS2_WKUP_IRQHandler /* OTGFS2 Wakeup from suspend */ + .word OTGFS2_IRQHandler /* OTGFS2 */ + .word DVP_IRQHandler /* DVP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QSPI2_IRQHandler /* QSPI2 */ + .word QSPI1_IRQHandler /* QSPI1 */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO2_IRQHandler /* SDIO2 */ + .word ACC_IRQHandler /* ACC */ + .word TMR20_BRK_IRQHandler /* TMR20 Brake */ + .word TMR20_OVF_IRQHandler /* TMR20 Overflow */ + .word TMR20_TRG_HALL_IRQHandler /* TMR20 Trigger and hall */ + .word TMR20_CH_IRQHandler /* TMR20 Channel */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak EDMA_Stream1_IRQHandler + .thumb_set EDMA_Stream1_IRQHandler,Default_Handler + + .weak EDMA_Stream2_IRQHandler + .thumb_set EDMA_Stream2_IRQHandler,Default_Handler + + .weak EDMA_Stream3_IRQHandler + .thumb_set EDMA_Stream3_IRQHandler,Default_Handler + + .weak EDMA_Stream4_IRQHandler + .thumb_set EDMA_Stream4_IRQHandler,Default_Handler + + .weak EDMA_Stream5_IRQHandler + .thumb_set EDMA_Stream5_IRQHandler,Default_Handler + + .weak EDMA_Stream6_IRQHandler + .thumb_set EDMA_Stream6_IRQHandler,Default_Handler + + .weak EDMA_Stream7_IRQHandler + .thumb_set EDMA_Stream7_IRQHandler,Default_Handler + + .weak ADC1_2_3_IRQHandler + .thumb_set ADC1_2_3_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_I2S2EXT_IRQHandler + .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR8_BRK_TMR12_IRQHandler + .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler + + .weak TMR8_OVF_TMR13_IRQHandler + .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_TMR14_IRQHandler + .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak EDMA_Stream8_IRQHandler + .thumb_set EDMA_Stream8_IRQHandler,Default_Handler + + .weak XMC_IRQHandler + .thumb_set XMC_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_I2S3EXT_IRQHandler + .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_DAC_GLOBAL_IRQHandler + .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak EMAC_IRQHandler + .thumb_set EMAC_IRQHandler,Default_Handler + + .weak EMAC_WKUP_IRQHandler + .thumb_set EMAC_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak OTGFS2_WKUP_IRQHandler + .thumb_set OTGFS2_WKUP_IRQHandler,Default_Handler + + .weak OTGFS2_IRQHandler + .thumb_set OTGFS2_IRQHandler,Default_Handler + + .weak DVP_IRQHandler + .thumb_set DVP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak QSPI2_IRQHandler + .thumb_set QSPI2_IRQHandler,Default_Handler + + .weak QSPI1_IRQHandler + .thumb_set QSPI1_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak SDIO2_IRQHandler + .thumb_set SDIO2_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak TMR20_BRK_IRQHandler + .thumb_set TMR20_BRK_IRQHandler,Default_Handler + + .weak TMR20_OVF_IRQHandler + .thumb_set TMR20_OVF_IRQHandler,Default_Handler + + .weak TMR20_TRG_HALL_IRQHandler + .thumb_set TMR20_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR20_CH_IRQHandler + .thumb_set TMR20_CH_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a08ed79c8..41c291600 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -550,6 +550,44 @@ #define TUP_RHPORT_HIGHSPEED 1 #define TUD_ENDPOINT_ONE_DIRECTION_ONLY +//--------------------------------------------------------------------+ +// ArteryTek +//--------------------------------------------------------------------+ +#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F413) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F415) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 4 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F423) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F425) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + #endif //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ef58957bb..5d6033a66 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -117,6 +117,8 @@ #include "fsdev_stm32.h" #elif defined(TUP_USBIP_FSDEV_CH32) #include "fsdev_ch32.h" +#elif defined(TUP_USBIP_FSDEV_AT32) + #include "fsdev_at32.h" #else #error "Unknown USB IP" #endif diff --git a/src/portable/st/stm32_fsdev/fsdev_at32.h b/src/portable/st/stm32_fsdev/fsdev_at32.h new file mode 100644 index 000000000..5f2ce4ba2 --- /dev/null +++ b/src/portable/st/stm32_fsdev/fsdev_at32.h @@ -0,0 +1,224 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2024, hathach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ +#ifndef TUSB_FSDEV_AT32_H +#define TUSB_FSDEV_AT32_H + +#include "common/tusb_compiler.h" + +#if CFG_TUSB_MCU == OPT_MCU_AT32F403A_407 + #include "at32f403a_407.h" + +#elif CFG_TUSB_MCU == OPT_MCU_AT32F413 + #include "at32f413.h" + +#endif + +//#include "fsdev_common.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) +static const IRQn_Type fsdev_irq[] = { + USBFS_H_CAN1_TX_IRQn, + USBFS_L_CAN1_RX0_IRQn, + USBFSWakeUp_IRQn +}; +enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) }; + +#else + #error "Unsupported MCU" +#endif + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_EnableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_DisableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_disconnect(uint8_t rhport) { + (void) rhport; + /* disable usb phy */ + //USB->ctrl_bit.disusb = TRUE; + *(int *)(0x40000000+0x5C00+0x40) |= (1<<1); + *(int *)(0x40000000+0x5C00+0x60) |= (1<<1); + /* D+ 1.5k pull-up disable */ + //USB->cfg_bit.puo = TRUE; +} + +void dcd_connect(uint8_t rhport) { + (void) rhport; + /* enable usb phy */ + //USB->ctrl_bit.disusb = 0; + *(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1); + *(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1); + /* Dp 1.5k pull-up enable */ + //USB->cfg_bit.puo = 0; +} + +#define FSDEV_PMA_SIZE (512u) +#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL) + +/**************************** ISTR interrupt events *************************/ +#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ +#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ +#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ +#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ +#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ +#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ +#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ +#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ +#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ + +/* Legacy defines */ +#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR + +#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ +#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ +#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ +#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ +#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ +#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ +#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ +#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ + +/* Legacy defines */ +#define USB_CLR_PMAOVRM USB_CLR_PMAOVR + +/************************* CNTR control register bits definitions ***********/ +#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ +#define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ +#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ +#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ +#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ +#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ + +/* Legacy defines */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR +#define USB_CNTR_LP_MODE USB_CNTR_LPMODE + +/******************** FNR Frame Number Register bit definitions ************/ +#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ +#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ +#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ +#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ +#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ + +/******************** DADDR Device ADDRess bit definitions ****************/ +#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */ +#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */ + +/****************************** Endpoint register *************************/ +#define USB_EP0R USB_BASE /*!< endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */ +/* bit positions */ +#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ +#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ +#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ +#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h new file mode 100644 index 000000000..10832a702 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -0,0 +1,135 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef DWC2_AT32_H_ +#define DWC2_AT32_H_ + +#define DWC2_EP_MAX TUP_DCD_ENDPOINT_MAX + +#if CFG_TUSB_MCU == OPT_MCU_AT32F415 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F435_437 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG2_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define OTG2_IRQn OTGFS2_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL + #define DWC2_OTG2_REG_BASE 0x40040000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F423 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG2_FIFO_SIZE 4096 + #define OTG1_IRQn OTGFS1_IRQn + #define OTG2_IRQn OTGHS_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL + #define DWC2_OTG2_REG_BASE 0x40040000UL //OTGHS +#elif CFG_TUSB_MCU == OPT_MCU_AT32F425 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +static const dwc2_controller_t _dwc2_controller[] = +{ + { .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE }, + #if defined DWC2_OTG2_REG_BASE + { .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE } + #endif +}; + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + (void) role; + const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; + if (enabled) { + NVIC_EnableIRQ(irqn); + } else { + NVIC_DisableIRQ(irqn); + } +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_disable (uint8_t rhport) +{ + NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); +} + +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = system_core_clock / 1000; + while ( count-- ) __asm volatile ("nop"); +} + +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + // Enable on-chip HS PHY + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) + { + + } + else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) + { + + } +} + +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN; +} + +#ifdef __cplusplus +} +#endif + +#endif /* DWC2_GD32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index e1e7d5c1a..56326d5a7 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -121,6 +121,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // Set 16-bit interface if supported if (ghwcfg4.phy_data_width) { gusbcfg |= GUSBCFG_PHYIF16; // 16 bit + + /* at32f402_405 does not actually support 16-bit */ + #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit + #endif + } else { gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit } @@ -139,7 +145,13 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (ghwcfg4.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + + /* at32f402_405 does not actually support 16-bit */ + #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos; + #endif + dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 18b93894f..33219f786 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -49,6 +49,8 @@ #include "dwc2_efm32.h" #elif TU_CHECK_MCU(OPT_MCU_XMC4000) #include "dwc2_xmc.h" +#elif defined(TUP_USBIP_DWC2_AT32) + #include "dwc2_at32.h" #else #error "Unsupported MCUs" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 867babc33..ebd8d9add 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -201,6 +201,15 @@ #define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2 #define OPT_MCU_MAX78002 2403 ///< ADI MAX78002 +// ArteryTek +#define OPT_MCU_AT32F403A_407 2500 ///< ArteryTek AT32F403A_AT32F407 +#define OPT_MCU_AT32F415 2501 ///< ArteryTek AT32F415 +#define OPT_MCU_AT32F435_437 2502 ///< ArteryTek AT32F435_AT32F437 +#define OPT_MCU_AT32F423 2503 ///< ArteryTek AT32F423 +#define OPT_MCU_AT32F402_405 2504 ///< ArteryTek AT32F402_405 +#define OPT_MCU_AT32F425 2505 ///< ArteryTek AT32F425 +#define OPT_MCU_AT32F413 2506 ///< ArteryTek AT32F413 + // Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) diff --git a/tools/get_deps.py b/tools/get_deps.py index 6a36ef35d..9a5fa37d9 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -208,6 +208,27 @@ deps_optional = { 'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git', '77c4095087e5ed2c548ec9058e655d0b8757663b', 'ch32f20x'], + 'hw/mcu/artery/at32f403a_407': ['https://github.com/ArteryTek/AT32F403A_407_Firmware_Library.git', + 'f2cb360c3d28fada76b374308b8c4c61d37a090b', + 'at32f403a_407'], + 'hw/mcu/artery/at32f415': ['https://github.com/ArteryTek/AT32F415_Firmware_Library.git', + '716f545aa1290ff144ccf023a8e797b951e1bc8e', + 'at32f415'], + 'hw/mcu/artery/at32f435_437': ['https://github.com/ArteryTek/AT32F435_437_Firmware_Library.git', + '25439cc6650a8ae0345934e8707a5f38c7ae41f8', + 'at32f435_437'], + 'hw/mcu/artery/at32f423': ['https://github.com/ArteryTek/AT32F423_Firmware_Library.git', + '2afa7f12852e57a9e8aab3a892c641e1a8635a18', + 'at32f423'], + 'hw/mcu/artery/at32f402_405': ['https://github.com/ArteryTek/AT32F402_405_Firmware_Library.git', + '4424515c2663e82438654e0947695295df2abdfe', + 'at32f402_405'], + 'hw/mcu/artery/at32f425': ['https://github.com/ArteryTek/AT32F425_Firmware_Library.git', + '620233e1357d5c1b7e2bde6b9dd5196822b91817', + 'at32f425'], + 'hw/mcu/artery/at32f413': ['https://github.com/ArteryTek/AT32F413_Firmware_Library.git', + 'f6fe62dfec9fd40c5b63d92fc5ef2c2b5e77a450', + 'at32f413'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c', 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' -- cgit v1.3.1 From b5694fd40a13445a6df7c88150593d152b54397d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 9 Jul 2025 17:58:11 +0700 Subject: add option to pass symbol defines to ci build.py add build.args option for hil json add MAX3421_HOST=1 for metro m4 express --- .../samd5x_e5x/boards/metro_m4_express/board.cmake | 3 --- test/hil/hil_ci_set_matrix.py | 20 ++++++++++------ test/hil/tinyusb.json | 3 +++ tools/build.py | 28 +++++++++++++--------- tools/get_deps.py | 1 + 5 files changed, 34 insertions(+), 21 deletions(-) (limited to 'tools') diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake index ebc32b1f7..86d12ca24 100644 --- a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake +++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake @@ -3,9 +3,6 @@ set(SAM_FAMILY samd51) set(JLINK_DEVICE ATSAMD51J19) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) -# force max3421e for testing with hardware-in-the-loop -set(MAX3421_HOST 1) - function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC __SAMD51J19A__ diff --git a/test/hil/hil_ci_set_matrix.py b/test/hil/hil_ci_set_matrix.py index 67ce2abb8..ecd964d87 100644 --- a/test/hil/hil_ci_set_matrix.py +++ b/test/hil/hil_ci_set_matrix.py @@ -28,14 +28,20 @@ def main(): else: toolchain = 'arm-gcc' - if 'build' in board and 'flags_on' in board['build']: - for f in board['build']['flags_on']: - if f == '': - matrix[toolchain].append(f'-b {name}') - else: - matrix[toolchain].append(f'-b {name} -f1 {f.replace(" ", " -f1 ")}') + build_board = f'-b {name}' + if 'build' in board: + if 'args' in board['build']: + build_board += ' ' + ' '.join(f'-D{a}' for a in board['build']['args']) + if 'flags_on' in board['build']: + for f in board['build']['flags_on']: + if f == '': + matrix[toolchain].append(build_board) + else: + matrix[toolchain].append(f'{build_board} -f1 {f.replace(" ", " -f1 ")}') + else: + matrix[toolchain].append(build_board) else: - matrix[toolchain].append(f'-b {name}') + matrix[toolchain].append(build_board) print(json.dumps(matrix)) diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 8a835e4c0..6afcb2186 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -61,6 +61,9 @@ { "name": "metro_m4_express", "uid": "9995AD485337433231202020FF100A34", + "build" : { + "args": ["MAX3421_HOST=1"] + }, "tests": { "device": true, "host": false, "dual": true, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] diff --git a/tools/build.py b/tools/build.py index f639fba81..ce4d0ef1a 100755 --- a/tools/build.py +++ b/tools/build.py @@ -82,7 +82,7 @@ def print_build_result(board, example, status, duration): # ----------------------------- # CMake # ----------------------------- -def cmake_board(board, toolchain, build_flags_on): +def cmake_board(board, build_args, build_flags_on): ret = [0, 0, 0] start_time = time.monotonic() @@ -106,7 +106,7 @@ def cmake_board(board, toolchain, build_flags_on): ret[0 if rcmd.returncode == 0 else 1] += 1 else: rcmd = run_cmd(f'cmake examples -B {build_dir} -G Ninja -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel ' - f'-DTOOLCHAIN={toolchain} {build_flags}') + f'{build_args} {build_flags}') if rcmd.returncode == 0: cmd = f"cmake --build {build_dir}" njobs = parallel_jobs @@ -152,7 +152,7 @@ def make_one_example(example, board, make_option): return ret -def make_board(board, toolchain): +def make_board(board, build_args): print(build_separator) family = find_family(board); all_examples = get_examples(family) @@ -163,7 +163,7 @@ def make_board(board, toolchain): final_status = 2 else: with Pool(processes=os.cpu_count()) as pool: - pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples))) + pool_args = list((map(lambda e, b=board, o=f"{build_args}": [e, b, o], all_examples))) r = pool.starmap(make_one_example, pool_args) # sum all element of same index (column sum) ret = list(map(sum, list(zip(*r)))) @@ -175,21 +175,23 @@ def make_board(board, toolchain): # ----------------------------- # Build Family # ----------------------------- -def build_boards_list(boards, toolchain, build_system, build_flags_on): +def build_boards_list(boards, build_defines, build_system, build_flags_on): ret = [0, 0, 0] for b in boards: r = [0, 0, 0] if build_system == 'cmake': - r = cmake_board(b, toolchain, build_flags_on) + build_args = ' '.join(f'-D{d}' for d in build_defines) + r = cmake_board(b, build_args, build_flags_on) elif build_system == 'make': - r = make_board(b, toolchain) + build_args = ' '.join(f'{d}' for d in build_defines) + r = make_board(b, build_args) ret[0] += r[0] ret[1] += r[1] ret[2] += r[2] return ret -def build_family(family, toolchain, build_system, build_flags_on, one_per_family, boards): +def build_family(family, build_defines, build_system, build_flags_on, one_per_family, boards): skip_ci = ['pico_sdk'] if os.getenv('GITHUB_ACTIONS') or os.getenv('CIRCLECI'): skip_ci_file = Path(f"hw/bsp/{family}/skip_ci.txt") @@ -210,7 +212,7 @@ def build_family(family, toolchain, build_system, build_flags_on, one_per_family return ret all_boards = [random.choice(all_boards)] - ret = build_boards_list(all_boards, toolchain, build_system, build_flags_on) + ret = build_boards_list(all_boards, build_defines, build_system, build_flags_on) return ret @@ -226,6 +228,7 @@ def main(): parser.add_argument('-b', '--board', action='append', default=[], help='Boards to build') parser.add_argument('-t', '--toolchain', default='gcc', help='Toolchain to use, default is gcc') parser.add_argument('-s', '--build-system', default='cmake', help='Build system to use, default is cmake') + parser.add_argument('-D', '--define-symbol', action='append', default=[], help='Define to pass to build system') parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Build flag to pass to build system') parser.add_argument('-1', '--one-per-family', action='store_true', default=False, help='Build only one random board inside a family') parser.add_argument('-j', '--jobs', type=int, default=os.cpu_count(), help='Number of jobs to run in parallel') @@ -236,11 +239,14 @@ def main(): boards = args.board toolchain = args.toolchain build_system = args.build_system + build_defines = args.define_symbol build_flags_on = args.build_flags_on one_per_family = args.one_per_family verbose = args.verbose parallel_jobs = args.jobs + build_defines.append(f'TOOLCHAIN={toolchain}') + if len(families) == 0 and len(boards) == 0: print("Please specify families or board to build") return 1 @@ -262,13 +268,13 @@ def main(): # succeeded, failed, skipped for f in all_families: - r = build_family(f, toolchain, build_system, build_flags_on, one_per_family, boards) + r = build_family(f, build_defines, build_system, build_flags_on, one_per_family, boards) result[0] += r[0] result[1] += r[1] result[2] += r[2] # build boards - r = build_boards_list(boards, toolchain, build_system, build_flags_on) + r = build_boards_list(boards, build_defines, build_system, build_flags_on) result[0] += r[0] result[1] += r[1] result[2] += r[2] diff --git a/tools/get_deps.py b/tools/get_deps.py index 6a36ef35d..4a980b255 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -286,6 +286,7 @@ def main(): parser = argparse.ArgumentParser() parser.add_argument('families', nargs='*', default=[], help='Families to fetch') parser.add_argument('-b', '--board', action='append', default=[], help='Boards to fetch') + parser.add_argument('-D', '--define', action='append', default=[], help='Have no effect') parser.add_argument('-f1', '--build-flags-on', action='append', default=[], help='Have no effect') parser.add_argument('--print', action='store_true', help='Print commit hash only') args = parser.parse_args() -- cgit v1.3.1 From aacd73ba42dfe58706fe83f8521ebe0ff957a79c Mon Sep 17 00:00:00 2001 From: Jie Feng Date: Thu, 24 Jul 2025 22:30:10 +0800 Subject: Add nanoch32v305 --- docs/reference/boards.rst | 3 +- .../ch32v307/boards/ch32v307v_r1_1v0/board.cmake | 4 - hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h | 55 -- hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk | 1 - hw/bsp/ch32v307/ch32v307.ld | 167 ----- hw/bsp/ch32v307/ch32v30x_conf.h | 38 - hw/bsp/ch32v307/ch32v30x_it.c | 47 -- hw/bsp/ch32v307/ch32v30x_it.h | 16 - hw/bsp/ch32v307/debug_uart.c | 119 ---- hw/bsp/ch32v307/debug_uart.h | 31 - hw/bsp/ch32v307/family.c | 195 ------ hw/bsp/ch32v307/family.cmake | 128 ---- hw/bsp/ch32v307/family.mk | 64 -- hw/bsp/ch32v307/system_ch32v30x.c | 776 --------------------- hw/bsp/ch32v307/system_ch32v30x.h | 27 - hw/bsp/ch32v307/wch-riscv.cfg | 17 - .../ch32v30x/boards/ch32v307v_r1_1v0/board.cmake | 4 + hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h | 55 ++ hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk | 1 + hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake | 4 + hw/bsp/ch32v30x/boards/nanoch32v305/board.h | 48 ++ hw/bsp/ch32v30x/boards/nanoch32v305/board.mk | 1 + hw/bsp/ch32v30x/ch32v307.ld | 167 +++++ hw/bsp/ch32v30x/ch32v30x_conf.h | 38 + hw/bsp/ch32v30x/ch32v30x_it.c | 47 ++ hw/bsp/ch32v30x/ch32v30x_it.h | 16 + hw/bsp/ch32v30x/debug_uart.c | 119 ++++ hw/bsp/ch32v30x/debug_uart.h | 31 + hw/bsp/ch32v30x/family.c | 200 ++++++ hw/bsp/ch32v30x/family.cmake | 128 ++++ hw/bsp/ch32v30x/family.mk | 64 ++ hw/bsp/ch32v30x/system_ch32v30x.c | 776 +++++++++++++++++++++ hw/bsp/ch32v30x/system_ch32v30x.h | 27 + hw/bsp/ch32v30x/wch-riscv.cfg | 17 + tools/get_deps.py | 2 +- 35 files changed, 1746 insertions(+), 1687 deletions(-) delete mode 100644 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake delete mode 100644 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h delete mode 100644 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk delete mode 100644 hw/bsp/ch32v307/ch32v307.ld delete mode 100644 hw/bsp/ch32v307/ch32v30x_conf.h delete mode 100644 hw/bsp/ch32v307/ch32v30x_it.c delete mode 100644 hw/bsp/ch32v307/ch32v30x_it.h delete mode 100644 hw/bsp/ch32v307/debug_uart.c delete mode 100644 hw/bsp/ch32v307/debug_uart.h delete mode 100644 hw/bsp/ch32v307/family.c delete mode 100644 hw/bsp/ch32v307/family.cmake delete mode 100644 hw/bsp/ch32v307/family.mk delete mode 100644 hw/bsp/ch32v307/system_ch32v30x.c delete mode 100644 hw/bsp/ch32v307/system_ch32v30x.h delete mode 100644 hw/bsp/ch32v307/wch-riscv.cfg create mode 100644 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake create mode 100644 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h create mode 100644 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk create mode 100644 hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake create mode 100644 hw/bsp/ch32v30x/boards/nanoch32v305/board.h create mode 100644 hw/bsp/ch32v30x/boards/nanoch32v305/board.mk create mode 100644 hw/bsp/ch32v30x/ch32v307.ld create mode 100644 hw/bsp/ch32v30x/ch32v30x_conf.h create mode 100644 hw/bsp/ch32v30x/ch32v30x_it.c create mode 100644 hw/bsp/ch32v30x/ch32v30x_it.h create mode 100644 hw/bsp/ch32v30x/debug_uart.c create mode 100644 hw/bsp/ch32v30x/debug_uart.h create mode 100644 hw/bsp/ch32v30x/family.c create mode 100644 hw/bsp/ch32v30x/family.cmake create mode 100644 hw/bsp/ch32v30x/family.mk create mode 100644 hw/bsp/ch32v30x/system_ch32v30x.c create mode 100644 hw/bsp/ch32v30x/system_ch32v30x.h create mode 100644 hw/bsp/ch32v30x/wch-riscv.cfg (limited to 'tools') diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst index 41e765683..824b1214b 100644 --- a/docs/reference/boards.rst +++ b/docs/reference/boards.rst @@ -326,5 +326,6 @@ ch32v103r_r1_1v0 CH32V103R-R1-1v1 ch32v10x https://github.com/openwch/ch32v10 ch32v203c_r0_1v0 CH32V203C-R0-1v0 ch32v20x https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 ch32v203g_r0_1v0 CH32V203G-R0-1v0 ch32v20x https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 nanoch32v203 nanoCH32V203 ch32v20x https://github.com/wuxx/nanoCH32V203 -ch32v307v_r1_1v0 CH32V307V-R1-1v0 ch32v307 https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0 +nanoch32v305 nanoCH32V305 ch32v30x https://github.com/wuxx/nanoCH32V305 +ch32v307v_r1_1v0 CH32V307V-R1-1v0 ch32v30x https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0 ================ ================ ======== ===================================================================== ====== diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake deleted file mode 100644 index 9f5682042..000000000 --- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -function(update_board TARGET) -# target_compile_definitions(${TARGET} PUBLIC -# ) -endfunction() diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h deleted file mode 100644 index 491347034..000000000 --- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -/* metadata: - name: CH32V307V-R1-1v0 - url: https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0 -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -// LED: need to wire pin LED1 to PC0 in the J3 header -#define LED_PORT GPIOC -#define LED_PIN GPIO_Pin_0 -#define LED_STATE_ON 0 -#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE) - -// Button: need to wire pin KEY to PC1 in the J3 header -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_Pin_1 -#define BUTTON_STATE_ACTIVE 0 -#define BUTTON_CLOCK_EN() do { } while(0) // same as LED clock, no need to do anything - -// TODO UART port - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk deleted file mode 100644 index 4e91d8938..000000000 --- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk +++ /dev/null @@ -1 +0,0 @@ -LD_FILE = $(FAMILY_PATH)/ch32v307.ld diff --git a/hw/bsp/ch32v307/ch32v307.ld b/hw/bsp/ch32v307/ch32v307.ld deleted file mode 100644 index 55bd10cd0..000000000 --- a/hw/bsp/ch32v307/ch32v307.ld +++ /dev/null @@ -1,167 +0,0 @@ -ENTRY( _start ) - -__stack_size = 4096; - -PROVIDE( _stack_size = __stack_size ); - - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K -} - - -SECTIONS -{ - - .init : - { - _sinit = .; - . = ALIGN(4); - KEEP(*(SORT_NONE(.init))) - . = ALIGN(4); - _einit = .; - } >FLASH AT>FLASH - - .vector : - { - *(.vector); - . = ALIGN(64); - } >FLASH AT>FLASH - - .text : - { - . = ALIGN(4); - *(.text) - *(.text.*) - *(.rodata) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t.*) - . = ALIGN(4); - } >FLASH AT>FLASH - - .fini : - { - KEEP(*(SORT_NONE(.fini))) - . = ALIGN(4); - } >FLASH AT>FLASH - - PROVIDE( _etext = . ); - PROVIDE( _eitcm = . ); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH AT>FLASH - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH AT>FLASH - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH AT>FLASH - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >FLASH AT>FLASH - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >FLASH AT>FLASH - - .dalign : - { - . = ALIGN(4); - PROVIDE(_data_vma = .); - } >RAM AT>FLASH - - .dlalign : - { - . = ALIGN(4); - PROVIDE(_data_lma = .); - } >FLASH AT>FLASH - - .data : - { - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.sdata2.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - . = ALIGN(4); - PROVIDE( _edata = .); - } >RAM AT>FLASH - - .bss : - { - . = ALIGN(4); - PROVIDE( _sbss = .); - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss*) - *(.gnu.linkonce.b.*) - *(COMMON*) - . = ALIGN(4); - PROVIDE( _ebss = .); - } >RAM AT>FLASH - - PROVIDE( _end = _ebss); - PROVIDE( end = . ); - - .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = ALIGN(4); - PROVIDE(_susrstack = . ); - . = . + __stack_size; - PROVIDE( _eusrstack = .); - __freertos_irq_stack_top = .; - } >RAM - -} diff --git a/hw/bsp/ch32v307/ch32v30x_conf.h b/hw/bsp/ch32v307/ch32v30x_conf.h deleted file mode 100644 index 0b86ad390..000000000 --- a/hw/bsp/ch32v307/ch32v30x_conf.h +++ /dev/null @@ -1,38 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_conf.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : Library configuration file. -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* SPDX-License-Identifier: Apache-2.0 -*******************************************************************************/ -#ifndef __CH32V30x_CONF_H -#define __CH32V30x_CONF_H - -#include "ch32v30x_adc.h" -#include "ch32v30x_bkp.h" -#include "ch32v30x_can.h" -#include "ch32v30x_crc.h" -#include "ch32v30x_dac.h" -#include "ch32v30x_dbgmcu.h" -#include "ch32v30x_dma.h" -#include "ch32v30x_exti.h" -#include "ch32v30x_flash.h" -#include "ch32v30x_fsmc.h" -#include "ch32v30x_gpio.h" -#include "ch32v30x_i2c.h" -#include "ch32v30x_iwdg.h" -#include "ch32v30x_pwr.h" -#include "ch32v30x_rcc.h" -#include "ch32v30x_rtc.h" -#include "ch32v30x_sdio.h" -#include "ch32v30x_spi.h" -#include "ch32v30x_tim.h" -#include "ch32v30x_usart.h" -#include "ch32v30x_wwdg.h" -#include "ch32v30x_it.h" -#include "ch32v30x_misc.h" - - -#endif /* __CH32V30x_CONF_H */ diff --git a/hw/bsp/ch32v307/ch32v30x_it.c b/hw/bsp/ch32v307/ch32v30x_it.c deleted file mode 100644 index c329c5613..000000000 --- a/hw/bsp/ch32v307/ch32v30x_it.c +++ /dev/null @@ -1,47 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_it.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : Main Interrupt Service Routines. -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* SPDX-License-Identifier: Apache-2.0 -*******************************************************************************/ -#include "ch32v30x_it.h" - -void NMI_Handler(void) __attribute__((naked)); -void HardFault_Handler(void) __attribute__((naked)); - -/********************************************************************* - * @fn NMI_Handler - * - * @brief This function handles NMI exception. - * - * @return none - */ -void NMI_Handle(void){ - __asm volatile ("call NMI_Handler_impl; mret"); -} - -__attribute__((used)) void NMI_Handler_impl(void) -{ - -} - -/********************************************************************* - * @fn HardFault_Handler - * - * @brief This function handles Hard Fault exception. - * - * @return none - */ -void HardFault_Handler(void){ - __asm volatile ("call HardFault_Handler_impl; mret"); -} - -__attribute__((used)) void HardFault_Handler_impl(void) -{ - while (1) - { - } -} diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h deleted file mode 100644 index f3977a8be..000000000 --- a/hw/bsp/ch32v307/ch32v30x_it.h +++ /dev/null @@ -1,16 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_it.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file contains the headers of the interrupt handlers. -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* SPDX-License-Identifier: Apache-2.0 -*******************************************************************************/ -#ifndef __CH32V30x_IT_H -#define __CH32V30x_IT_H - -// #include "debug.h" - - -#endif /* __CH32V30x_IT_H */ diff --git a/hw/bsp/ch32v307/debug_uart.c b/hw/bsp/ch32v307/debug_uart.c deleted file mode 100644 index 2fd3a9d64..000000000 --- a/hw/bsp/ch32v307/debug_uart.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Greg Davill - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "debug_uart.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" -#endif - -#include - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#define UART_RINGBUFFER_SIZE_TX 128 -#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1) - -static char tx_buf[UART_RINGBUFFER_SIZE_TX]; -static unsigned int tx_produce; -static volatile unsigned int tx_consume; - -void USART1_IRQHandler(void) __attribute__((naked)); -void USART1_IRQHandler(void) { - __asm volatile ("call USART1_IRQHandler_impl; mret"); -} - -__attribute__((used)) void USART1_IRQHandler_impl(void) -{ - if(USART_GetITStatus(USART1, USART_IT_TC) != RESET) - { - USART_ClearITPendingBit(USART1, USART_IT_TC); - - if(tx_consume != tx_produce) { - USART_SendData(USART1, tx_buf[tx_consume]); - tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX; - } - } - -} - -void uart_write(char c) -{ - unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; - - NVIC_DisableIRQ(USART1_IRQn); - if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) { - tx_buf[tx_produce] = c; - tx_produce = tx_produce_next; - } else { - USART_SendData(USART1, c); - } - NVIC_EnableIRQ(USART1_IRQn); -} - - -void uart_sync(void) -{ - while(tx_consume != tx_produce); -} - - -void usart_printf_init(uint32_t baudrate) -{ - GPIO_InitTypeDef GPIO_InitStructure; - USART_InitTypeDef USART_InitStructure; - - tx_produce = 0; - tx_consume = 0; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - USART_InitStructure.USART_BaudRate = baudrate; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Tx; - - USART_Init(USART1, &USART_InitStructure); - USART_ITConfig(USART1, USART_IT_TC, ENABLE); - USART_Cmd(USART1, ENABLE); - - NVIC_InitTypeDef NVIC_InitStructure = { 0 }; - NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -} diff --git a/hw/bsp/ch32v307/debug_uart.h b/hw/bsp/ch32v307/debug_uart.h deleted file mode 100644 index a7e070585..000000000 --- a/hw/bsp/ch32v307/debug_uart.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Greg Davill - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include - -void uart_write(char c); -void uart_sync(void); -void usart_printf_init(uint32_t baudrate); diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c deleted file mode 100644 index 48eb8a38c..000000000 --- a/hw/bsp/ch32v307/family.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Greg Davill - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - manufacturer: WCH -*/ - -#include "stdio.h" - -// https://github.com/openwch/ch32v307/pull/90 -// https://github.com/openwch/ch32v20x/pull/12 - -#ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-prototypes" -#endif - -#include "debug_uart.h" -#include "ch32v30x.h" - -#ifdef __GNUC__ -#pragma GCC diagnostic pop -#endif - -#include "bsp/board_api.h" -#include "board.h" - -//--------------------------------------------------------------------+ -// Forward USB interrupt events to TinyUSB IRQ Handler -//--------------------------------------------------------------------+ - -// TODO maybe having FS as port0, HS as port1 - -__attribute__((interrupt)) void USBHS_IRQHandler(void) { - #if CFG_TUD_WCH_USBIP_USBHS - tud_int_handler(0); - #endif -} - -__attribute__((interrupt)) void OTG_FS_IRQHandler(void) { - #if CFG_TUD_WCH_USBIP_USBFS - tud_int_handler(0); - #endif -} - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -uint32_t SysTick_Config(uint32_t ticks) { - NVIC_EnableIRQ(SysTicK_IRQn); - SysTick->CTLR = 0; - SysTick->SR = 0; - SysTick->CNT = 0; - SysTick->CMP = ticks - 1; - SysTick->CTLR = 0xF; - return 0; -} - -void board_init(void) { - - /* Disable interrupts during init */ - __disable_irq(); - -#if CFG_TUSB_OS == OPT_OS_NONE - SysTick_Config(SystemCoreClock / 1000); -#endif - - usart_printf_init(CFG_BOARD_UART_BAUDRATE); - -#ifdef CH32V30x_D8C - // v305/v307: Highspeed USB - RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY); - RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE); - RCC_USBHSConfig(RCC_USBPLL_Div2); - RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M); - RCC_USBHSPHYPLLALIVEcmd(ENABLE); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE); -#endif - - // Fullspeed USB - uint8_t otg_div; - switch (SystemCoreClock) { - case 48000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div1; break; - case 96000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div2; break; - case 144000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div3; break; - default: TU_ASSERT(0,); break; - } - RCC_OTGFSCLKConfig(otg_div); - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); - - GPIO_InitTypeDef GPIO_InitStructure = {0}; - - // LED - LED_CLOCK_EN(); - GPIO_InitStructure.GPIO_Pin = LED_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(LED_PORT, &GPIO_InitStructure); - - // Button - BUTTON_CLOCK_EN(); - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(BUTTON_PORT, &GPIO_InitStructure); - - /* Enable interrupts globally */ - __enable_irq(); - - board_delay(2); -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; - -__attribute__((interrupt)) void SysTick_Handler(void) { - SysTick->SR = 0; - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} - -#endif - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { - GPIO_WriteBit(LED_PORT, LED_PIN, state); -} - -uint32_t board_button_read(void) { - return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN); -} - -int board_uart_read(uint8_t* buf, int len) { - (void) buf; - (void) len; - return 0; -} - -int board_uart_write(void const* buf, int len) { - int txsize = len; - const char* bufc = (const char*) buf; - while (txsize--) { - uart_write(*bufc++); - } - uart_sync(); - return len; -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(char* file, uint32_t line) { - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line - number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) - */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake deleted file mode 100644 index 446e850c5..000000000 --- a/hw/bsp/ch32v307/family.cmake +++ /dev/null @@ -1,128 +0,0 @@ -include_guard() - -set(CH32_FAMILY ch32v30x) -set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v307) -set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) - -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - -# toolchain set up -set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") -set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) - -set(FAMILY_MCUS CH32V307 CACHE INTERNAL "") -set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg") - -# default to highspeed, used to select USBFS / USBHS driver -if (NOT DEFINED SPEED) - set(SPEED high) -endif() - -#------------------------------------ -# BOARD_TARGET -#------------------------------------ -# only need to be built ONCE for all examples -function(add_board_target BOARD_TARGET) - if (TARGET ${BOARD_TARGET}) - return() - endif() - - if (NOT DEFINED LD_FILE_GNU) - set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/ch32v307.ld) - endif () - set(LD_FILE_Clang ${LD_FILE_GNU}) - - if (NOT DEFINED STARTUP_FILE_GNU) - set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_D8C.S) - endif () - set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - - add_library(${BOARD_TARGET} STATIC - ${SDK_SRC_DIR}/Core/core_riscv.c - ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c - ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c - ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c - ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${CH32_FAMILY}_it.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c - ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${SDK_SRC_DIR}/Core - ${SDK_SRC_DIR}/Peripheral/inc - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ) - if (SPEED STREQUAL high) - target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUD_WCH_USBIP_USBHS=1 -# BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - ) - else () - target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUD_WCH_USBIP_USBFS=1 - ) - endif () - - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_compile_options(${BOARD_TARGET} PUBLIC - -msmall-data-limit=8 - -mno-save-restore - -fmessage-length=0 - -fsigned-char - ) - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - -nostartfiles - --specs=nosys.specs --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - message(FATAL_ERROR "Clang is not supported for MSP432E4") - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) - endif () -endfunction() - - -#------------------------------------ -# Functions -#------------------------------------ -function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) - - # Board target - add_board_target(board_${BOARD}) - - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC - # BSP - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/debug_uart.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ) - target_include_directories(${TARGET} PUBLIC - # family, hw, board - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ) - - # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_CH32V307) - target_sources(${TARGET} PUBLIC - ${TOP}/src/portable/wch/dcd_ch32_usbhs.c - ${TOP}/src/portable/wch/dcd_ch32_usbfs.c - ) - target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - - - - # Flashing - family_add_bin_hex(${TARGET}) - family_flash_openocd_wch(${TARGET}) -endfunction() diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk deleted file mode 100644 index bf2732106..000000000 --- a/hw/bsp/ch32v307/family.mk +++ /dev/null @@ -1,64 +0,0 @@ -# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable -#CROSS_COMPILE ?= riscv32-unknown-elf- - -# Toolchain from https://nucleisys.com/download.php -#CROSS_COMPILE ?= riscv-nuclei-elf- - -# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack -CROSS_COMPILE ?= riscv-none-elf- - -CH32_FAMILY = ch32v30x -SDK_DIR = hw/mcu/wch/ch32v307 -SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC - -include $(TOP)/$(BOARD_PATH)/board.mk -CPU_CORE ?= rv32imac-ilp32 - -# default to use high speed port, unless specified in board.mk or command line -SPEED ?= high - -CFLAGS += \ - -flto \ - -msmall-data-limit=8 \ - -mno-save-restore \ - -fmessage-length=0 \ - -fsigned-char \ - -DCFG_TUSB_MCU=OPT_MCU_CH32V307 \ - -# https://github.com/openwch/ch32v307/pull/90 -CFLAGS += -Wno-error=strict-prototypes - -ifeq ($(SPEED),high) - $(info "Using USBHS driver for HighSpeed mode") - CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1 -else - $(info "Using USBFS driver for FullSpeed mode") - CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1 -endif - -LDFLAGS_GCC += \ - -nostdlib -nostartfiles \ - --specs=nosys.specs --specs=nano.specs \ - -SRC_C += \ - src/portable/wch/dcd_ch32_usbhs.c \ - src/portable/wch/dcd_ch32_usbfs.c \ - $(SDK_SRC_DIR)/Core/core_riscv.c \ - $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \ - $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \ - $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \ - $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c - -SRC_S += \ - $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_D8C.S - -INC += \ - $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(SDK_SRC_DIR)/Core \ - $(TOP)/$(SDK_SRC_DIR)/Peripheral/inc - -# For freeRTOS port source -FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V - -OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -flash: flash-openocd-wch diff --git a/hw/bsp/ch32v307/system_ch32v30x.c b/hw/bsp/ch32v307/system_ch32v30x.c deleted file mode 100644 index 23f783df4..000000000 --- a/hw/bsp/ch32v307/system_ch32v30x.c +++ /dev/null @@ -1,776 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : system_ch32v30x.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : CH32V30x Device Peripheral Access Layer System Source File. -* For HSE = 8Mhz -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* SPDX-License-Identifier: Apache-2.0 -*********************************************************************************/ -#include "ch32v30x.h" - -/* -* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after -* reset the HSI is used as SYSCLK source). -* If none of the define below is enabled, the HSI is used as System clock source. -*/ -// #define SYSCLK_FREQ_HSE HSE_VALUE -/* #define SYSCLK_FREQ_24MHz 24000000 */ -//#define SYSCLK_FREQ_48MHz 48000000 -/* #define SYSCLK_FREQ_56MHz 56000000 */ -//#define SYSCLK_FREQ_72MHz 72000000 -//#define SYSCLK_FREQ_96MHz 96000000 -//#define SYSCLK_FREQ_120MHz 120000000 -#define SYSCLK_FREQ_144MHz 144000000 - -/* Clock Definitions */ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */ - -#elif defined SYSCLK_FREQ_96MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_120MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /* System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_144MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /* System Clock Frequency (Core Clock) */ - -#else /* HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - - -/* system_private_function_proto_types */ -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); - -#elif defined SYSCLK_FREQ_96MHz - static void SetSysClockTo96(void); -#elif defined SYSCLK_FREQ_120MHz - static void SetSysClockTo120(void); -#elif defined SYSCLK_FREQ_144MHz - static void SetSysClockTo144(void); - -#endif - - -/********************************************************************* - * @fn SystemInit - * - * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, - * the PLL and update the SystemCoreClock variable. - * - * @return none - */ -void SystemInit (void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - -#ifdef CH32V30x_D8C - RCC->CFGR0 &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR0 &= (uint32_t)0xF0FF0000; -#endif - - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - -#ifdef CH32V30x_D8C - RCC->CTLR &= (uint32_t)0xEBFFFFFF; - RCC->INTR = 0x00FF0000; - RCC->CFGR2 = 0x00000000; -#else - RCC->INTR = 0x009F0000; -#endif - SetSysClock(); -} - -/********************************************************************* - * @fn SystemCoreClockUpdate - * - * @brief Update SystemCoreClock variable according to Clock Register Values. - * - * @return none - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; - - tmp = RCC->CFGR0 & RCC_SWS; - - switch (tmp) - { - case 0x00: - SystemCoreClock = HSI_VALUE; - break; - case 0x04: - SystemCoreClock = HSE_VALUE; - break; - case 0x08: - pllmull = RCC->CFGR0 & RCC_PLLMULL; - pllsource = RCC->CFGR0 & RCC_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - -#ifdef CH32V30x_D8 - if(pllmull == 17) pllmull = 18; -#else - if(pllmull == 2) pllmull = 18; - if(pllmull == 15){ - pllmull = 13; /* *6.5 */ - Pll_6_5 = 1; - } - if(pllmull == 16) pllmull = 15; - if(pllmull == 17) pllmull = 16; -#endif - - if (pllsource == 0x00) - { - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) - { - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - } - - if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); - - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - - tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; - SystemCoreClock >>= tmp; -} - -/********************************************************************* - * @fn SetSysClock - * - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#elif defined SYSCLK_FREQ_96MHz - SetSysClockTo96(); -#elif defined SYSCLK_FREQ_120MHz - SetSysClockTo120(); -#elif defined SYSCLK_FREQ_144MHz - SetSysClockTo144(); - -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - * source (default after reset) - */ -} - - -#ifdef SYSCLK_FREQ_HSE - -/********************************************************************* - * @fn SetSysClockToHSE - * - * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) - { - } - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_24MHz - -/********************************************************************* - * @fn SetSysClockTo24 - * - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; - - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN); -#endif - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_48MHz - -/********************************************************************* - * @fn SetSysClockTo48 - * - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_56MHz - -/********************************************************************* - * @fn SetSysClockTo56 - * - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - -#elif defined SYSCLK_FREQ_72MHz - -/********************************************************************* - * @fn SetSysClockTo72 - * - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_96MHz - -/********************************************************************* - * @fn SetSysClockTo96 - * - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo96(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_120MHz - -/********************************************************************* - * @fn SetSysClockTo120 - * - * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo120(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#elif defined SYSCLK_FREQ_144MHz - -/********************************************************************* - * @fn SetSysClockTo144 - * - * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. - * - * @return none - */ -static void SetSysClockTo144(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - RCC->CTLR |= ((uint32_t)RCC_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTLR & RCC_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CTLR & RCC_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; - /* PCLK2 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; - /* PCLK1 = HCLK */ - RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; - - /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | - RCC_PLLMULL)); - -#ifdef CH32V30x_D8 - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); -#else - RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN); -#endif - - /* Enable PLL */ - RCC->CTLR |= RCC_PLLON; - /* Wait till PLL is ready */ - while((RCC->CTLR & RCC_PLLRDY) == 0) - { - } - /* Select PLL as system clock source */ - RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); - RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) - { - } - } - else - { - /* - * If HSE fails to start-up, the application will have wrong clock - * configuration. User can add here some code to deal with this error - */ - } -} - - -#endif diff --git a/hw/bsp/ch32v307/system_ch32v30x.h b/hw/bsp/ch32v307/system_ch32v30x.h deleted file mode 100644 index ad81058c7..000000000 --- a/hw/bsp/ch32v307/system_ch32v30x.h +++ /dev/null @@ -1,27 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : system_ch32v30x.h -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : CH32V30x Device Peripheral Access Layer System Header File. -* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. -* SPDX-License-Identifier: Apache-2.0 -*******************************************************************************/ -#ifndef __SYSTEM_CH32V30x_H -#define __SYSTEM_CH32V30x_H - -#ifdef __cplusplus - extern "C" { -#endif - -extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ - -/* System_Exported_Functions */ -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__CH32V30x_SYSTEM_H */ diff --git a/hw/bsp/ch32v307/wch-riscv.cfg b/hw/bsp/ch32v307/wch-riscv.cfg deleted file mode 100644 index aa35aa9c5..000000000 --- a/hw/bsp/ch32v307/wch-riscv.cfg +++ /dev/null @@ -1,17 +0,0 @@ -adapter driver wlinke -adapter speed 6000 -transport select sdi - -wlink_set_address 0x00000000 -set _CHIPNAME wch_riscv -sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 -set _FLASHNAME $_CHIPNAME.flash - -flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 - -echo "Ready for Remote Connections" diff --git a/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake new file mode 100644 index 000000000..9f5682042 --- /dev/null +++ b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake @@ -0,0 +1,4 @@ +function(update_board TARGET) +# target_compile_definitions(${TARGET} PUBLIC +# ) +endfunction() diff --git a/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h new file mode 100644 index 000000000..491347034 --- /dev/null +++ b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h @@ -0,0 +1,55 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* metadata: + name: CH32V307V-R1-1v0 + url: https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0 +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED: need to wire pin LED1 to PC0 in the J3 header +#define LED_PORT GPIOC +#define LED_PIN GPIO_Pin_0 +#define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE) + +// Button: need to wire pin KEY to PC1 in the J3 header +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_Pin_1 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_CLOCK_EN() do { } while(0) // same as LED clock, no need to do anything + +// TODO UART port + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk new file mode 100644 index 000000000..4e91d8938 --- /dev/null +++ b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk @@ -0,0 +1 @@ +LD_FILE = $(FAMILY_PATH)/ch32v307.ld diff --git a/hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake b/hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake new file mode 100644 index 000000000..9f5682042 --- /dev/null +++ b/hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake @@ -0,0 +1,4 @@ +function(update_board TARGET) +# target_compile_definitions(${TARGET} PUBLIC +# ) +endfunction() diff --git a/hw/bsp/ch32v30x/boards/nanoch32v305/board.h b/hw/bsp/ch32v30x/boards/nanoch32v305/board.h new file mode 100644 index 000000000..62bbef94c --- /dev/null +++ b/hw/bsp/ch32v30x/boards/nanoch32v305/board.h @@ -0,0 +1,48 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* metadata: + name: nanoCH32V305 + url: https://github.com/wuxx/nanoCH32V305 +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOA +#define LED_PIN GPIO_Pin_3 +#define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE) + +// TODO UART port + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/ch32v30x/boards/nanoch32v305/board.mk b/hw/bsp/ch32v30x/boards/nanoch32v305/board.mk new file mode 100644 index 000000000..4e91d8938 --- /dev/null +++ b/hw/bsp/ch32v30x/boards/nanoch32v305/board.mk @@ -0,0 +1 @@ +LD_FILE = $(FAMILY_PATH)/ch32v307.ld diff --git a/hw/bsp/ch32v30x/ch32v307.ld b/hw/bsp/ch32v30x/ch32v307.ld new file mode 100644 index 000000000..55bd10cd0 --- /dev/null +++ b/hw/bsp/ch32v30x/ch32v307.ld @@ -0,0 +1,167 @@ +ENTRY( _start ) + +__stack_size = 4096; + +PROVIDE( _stack_size = __stack_size ); + + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K +} + + +SECTIONS +{ + + .init : + { + _sinit = .; + . = ALIGN(4); + KEEP(*(SORT_NONE(.init))) + . = ALIGN(4); + _einit = .; + } >FLASH AT>FLASH + + .vector : + { + *(.vector); + . = ALIGN(64); + } >FLASH AT>FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t.*) + . = ALIGN(4); + } >FLASH AT>FLASH + + .fini : + { + KEEP(*(SORT_NONE(.fini))) + . = ALIGN(4); + } >FLASH AT>FLASH + + PROVIDE( _etext = . ); + PROVIDE( _eitcm = . ); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH AT>FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH AT>FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH AT>FLASH + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >FLASH AT>FLASH + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >FLASH AT>FLASH + + .dalign : + { + . = ALIGN(4); + PROVIDE(_data_vma = .); + } >RAM AT>FLASH + + .dlalign : + { + . = ALIGN(4); + PROVIDE(_data_lma = .); + } >FLASH AT>FLASH + + .data : + { + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + . = ALIGN(4); + PROVIDE( _edata = .); + } >RAM AT>FLASH + + .bss : + { + . = ALIGN(4); + PROVIDE( _sbss = .); + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss*) + *(.gnu.linkonce.b.*) + *(COMMON*) + . = ALIGN(4); + PROVIDE( _ebss = .); + } >RAM AT>FLASH + + PROVIDE( _end = _ebss); + PROVIDE( end = . ); + + .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = ALIGN(4); + PROVIDE(_susrstack = . ); + . = . + __stack_size; + PROVIDE( _eusrstack = .); + __freertos_irq_stack_top = .; + } >RAM + +} diff --git a/hw/bsp/ch32v30x/ch32v30x_conf.h b/hw/bsp/ch32v30x/ch32v30x_conf.h new file mode 100644 index 000000000..0b86ad390 --- /dev/null +++ b/hw/bsp/ch32v30x/ch32v30x_conf.h @@ -0,0 +1,38 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_conf.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Library configuration file. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_CONF_H +#define __CH32V30x_CONF_H + +#include "ch32v30x_adc.h" +#include "ch32v30x_bkp.h" +#include "ch32v30x_can.h" +#include "ch32v30x_crc.h" +#include "ch32v30x_dac.h" +#include "ch32v30x_dbgmcu.h" +#include "ch32v30x_dma.h" +#include "ch32v30x_exti.h" +#include "ch32v30x_flash.h" +#include "ch32v30x_fsmc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_i2c.h" +#include "ch32v30x_iwdg.h" +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" +#include "ch32v30x_rtc.h" +#include "ch32v30x_sdio.h" +#include "ch32v30x_spi.h" +#include "ch32v30x_tim.h" +#include "ch32v30x_usart.h" +#include "ch32v30x_wwdg.h" +#include "ch32v30x_it.h" +#include "ch32v30x_misc.h" + + +#endif /* __CH32V30x_CONF_H */ diff --git a/hw/bsp/ch32v30x/ch32v30x_it.c b/hw/bsp/ch32v30x/ch32v30x_it.c new file mode 100644 index 000000000..c329c5613 --- /dev/null +++ b/hw/bsp/ch32v30x/ch32v30x_it.c @@ -0,0 +1,47 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_it.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Main Interrupt Service Routines. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#include "ch32v30x_it.h" + +void NMI_Handler(void) __attribute__((naked)); +void HardFault_Handler(void) __attribute__((naked)); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handle(void){ + __asm volatile ("call NMI_Handler_impl; mret"); +} + +__attribute__((used)) void NMI_Handler_impl(void) +{ + +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void){ + __asm volatile ("call HardFault_Handler_impl; mret"); +} + +__attribute__((used)) void HardFault_Handler_impl(void) +{ + while (1) + { + } +} diff --git a/hw/bsp/ch32v30x/ch32v30x_it.h b/hw/bsp/ch32v30x/ch32v30x_it.h new file mode 100644 index 000000000..f3977a8be --- /dev/null +++ b/hw/bsp/ch32v30x/ch32v30x_it.h @@ -0,0 +1,16 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_it.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains the headers of the interrupt handlers. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __CH32V30x_IT_H +#define __CH32V30x_IT_H + +// #include "debug.h" + + +#endif /* __CH32V30x_IT_H */ diff --git a/hw/bsp/ch32v30x/debug_uart.c b/hw/bsp/ch32v30x/debug_uart.c new file mode 100644 index 000000000..2fd3a9d64 --- /dev/null +++ b/hw/bsp/ch32v30x/debug_uart.c @@ -0,0 +1,119 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Greg Davill + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "debug_uart.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" +#endif + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#define UART_RINGBUFFER_SIZE_TX 128 +#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1) + +static char tx_buf[UART_RINGBUFFER_SIZE_TX]; +static unsigned int tx_produce; +static volatile unsigned int tx_consume; + +void USART1_IRQHandler(void) __attribute__((naked)); +void USART1_IRQHandler(void) { + __asm volatile ("call USART1_IRQHandler_impl; mret"); +} + +__attribute__((used)) void USART1_IRQHandler_impl(void) +{ + if(USART_GetITStatus(USART1, USART_IT_TC) != RESET) + { + USART_ClearITPendingBit(USART1, USART_IT_TC); + + if(tx_consume != tx_produce) { + USART_SendData(USART1, tx_buf[tx_consume]); + tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX; + } + } + +} + +void uart_write(char c) +{ + unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; + + NVIC_DisableIRQ(USART1_IRQn); + if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) { + tx_buf[tx_produce] = c; + tx_produce = tx_produce_next; + } else { + USART_SendData(USART1, c); + } + NVIC_EnableIRQ(USART1_IRQn); +} + + +void uart_sync(void) +{ + while(tx_consume != tx_produce); +} + + +void usart_printf_init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + + tx_produce = 0; + tx_consume = 0; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + + USART_Init(USART1, &USART_InitStructure); + USART_ITConfig(USART1, USART_IT_TC, ENABLE); + USART_Cmd(USART1, ENABLE); + + NVIC_InitTypeDef NVIC_InitStructure = { 0 }; + NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} diff --git a/hw/bsp/ch32v30x/debug_uart.h b/hw/bsp/ch32v30x/debug_uart.h new file mode 100644 index 000000000..a7e070585 --- /dev/null +++ b/hw/bsp/ch32v30x/debug_uart.h @@ -0,0 +1,31 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Greg Davill + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include + +void uart_write(char c); +void uart_sync(void); +void usart_printf_init(uint32_t baudrate); diff --git a/hw/bsp/ch32v30x/family.c b/hw/bsp/ch32v30x/family.c new file mode 100644 index 000000000..bd01f4f46 --- /dev/null +++ b/hw/bsp/ch32v30x/family.c @@ -0,0 +1,200 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Greg Davill + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: WCH +*/ + +#include "stdio.h" + +// https://github.com/openwch/ch32v307/pull/90 +// https://github.com/openwch/ch32v20x/pull/12 + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" +#endif + +#include "debug_uart.h" +#include "ch32v30x.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "bsp/board_api.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +// TODO maybe having FS as port0, HS as port1 + +__attribute__((interrupt)) void USBHS_IRQHandler(void) { + #if CFG_TUD_WCH_USBIP_USBHS + tud_int_handler(0); + #endif +} + +__attribute__((interrupt)) void OTG_FS_IRQHandler(void) { + #if CFG_TUD_WCH_USBIP_USBFS + tud_int_handler(0); + #endif +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +uint32_t SysTick_Config(uint32_t ticks) { + NVIC_EnableIRQ(SysTicK_IRQn); + SysTick->CTLR = 0; + SysTick->SR = 0; + SysTick->CNT = 0; + SysTick->CMP = ticks - 1; + SysTick->CTLR = 0xF; + return 0; +} + +void board_init(void) { + + /* Disable interrupts during init */ + __disable_irq(); + +#if CFG_TUSB_OS == OPT_OS_NONE + SysTick_Config(SystemCoreClock / 1000); +#endif + + usart_printf_init(CFG_BOARD_UART_BAUDRATE); + +#ifdef CH32V30x_D8C + // v305/v307: Highspeed USB + RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY); + RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE); + RCC_USBHSConfig(RCC_USBPLL_Div2); + RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M); + RCC_USBHSPHYPLLALIVEcmd(ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE); +#endif + + // Fullspeed USB + uint8_t otg_div; + switch (SystemCoreClock) { + case 48000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div1; break; + case 96000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div2; break; + case 144000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div3; break; + default: TU_ASSERT(0,); break; + } + RCC_OTGFSCLKConfig(otg_div); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); + + GPIO_InitTypeDef GPIO_InitStructure = {0}; + + // LED + LED_CLOCK_EN(); + GPIO_InitStructure.GPIO_Pin = LED_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(LED_PORT, &GPIO_InitStructure); + + // Button +#ifdef BUTTON_PORT + BUTTON_CLOCK_EN(); + GPIO_InitStructure.GPIO_Pin = BUTTON_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(BUTTON_PORT, &GPIO_InitStructure); +#endif + /* Enable interrupts globally */ + __enable_irq(); + + board_delay(2); +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +__attribute__((interrupt)) void SysTick_Handler(void) { + SysTick->SR = 0; + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} + +#endif + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { + GPIO_WriteBit(LED_PORT, LED_PIN, state); +} + +uint32_t board_button_read(void) { +#ifdef BUTTON_PORT + return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN); +#else + return false; +#endif +} + +int board_uart_read(uint8_t* buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const* buf, int len) { + int txsize = len; + const char* bufc = (const char*) buf; + while (txsize--) { + uart_write(*bufc++); + } + uart_sync(); + return len; +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(char* file, uint32_t line) { + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line + number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) + */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/ch32v30x/family.cmake b/hw/bsp/ch32v30x/family.cmake new file mode 100644 index 000000000..446e850c5 --- /dev/null +++ b/hw/bsp/ch32v30x/family.cmake @@ -0,0 +1,128 @@ +include_guard() + +set(CH32_FAMILY ch32v30x) +set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v307) +set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS CH32V307 CACHE INTERNAL "") +set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg") + +# default to highspeed, used to select USBFS / USBHS driver +if (NOT DEFINED SPEED) + set(SPEED high) +endif() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif() + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/ch32v307.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + + if (NOT DEFINED STARTUP_FILE_GNU) + set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_D8C.S) + endif () + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + + add_library(${BOARD_TARGET} STATIC + ${SDK_SRC_DIR}/Core/core_riscv.c + ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c + ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c + ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c + ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${CH32_FAMILY}_it.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${SDK_SRC_DIR}/Core + ${SDK_SRC_DIR}/Peripheral/inc + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ) + if (SPEED STREQUAL high) + target_compile_definitions(${BOARD_TARGET} PUBLIC + CFG_TUD_WCH_USBIP_USBHS=1 +# BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) + else () + target_compile_definitions(${BOARD_TARGET} PUBLIC + CFG_TUD_WCH_USBIP_USBFS=1 + ) + endif () + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_compile_options(${BOARD_TARGET} PUBLIC + -msmall-data-limit=8 + -mno-save-restore + -fmessage-length=0 + -fsigned-char + ) + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + message(FATAL_ERROR "Clang is not supported for MSP432E4") + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/debug_uart.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_CH32V307) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/wch/dcd_ch32_usbhs.c + ${TOP}/src/portable/wch/dcd_ch32_usbfs.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_openocd_wch(${TARGET}) +endfunction() diff --git a/hw/bsp/ch32v30x/family.mk b/hw/bsp/ch32v30x/family.mk new file mode 100644 index 000000000..bf2732106 --- /dev/null +++ b/hw/bsp/ch32v30x/family.mk @@ -0,0 +1,64 @@ +# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable +#CROSS_COMPILE ?= riscv32-unknown-elf- + +# Toolchain from https://nucleisys.com/download.php +#CROSS_COMPILE ?= riscv-nuclei-elf- + +# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack +CROSS_COMPILE ?= riscv-none-elf- + +CH32_FAMILY = ch32v30x +SDK_DIR = hw/mcu/wch/ch32v307 +SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= rv32imac-ilp32 + +# default to use high speed port, unless specified in board.mk or command line +SPEED ?= high + +CFLAGS += \ + -flto \ + -msmall-data-limit=8 \ + -mno-save-restore \ + -fmessage-length=0 \ + -fsigned-char \ + -DCFG_TUSB_MCU=OPT_MCU_CH32V307 \ + +# https://github.com/openwch/ch32v307/pull/90 +CFLAGS += -Wno-error=strict-prototypes + +ifeq ($(SPEED),high) + $(info "Using USBHS driver for HighSpeed mode") + CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1 +else + $(info "Using USBFS driver for FullSpeed mode") + CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1 +endif + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs \ + +SRC_C += \ + src/portable/wch/dcd_ch32_usbhs.c \ + src/portable/wch/dcd_ch32_usbfs.c \ + $(SDK_SRC_DIR)/Core/core_riscv.c \ + $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \ + $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \ + $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \ + $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c + +SRC_S += \ + $(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_D8C.S + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(SDK_SRC_DIR)/Core \ + $(TOP)/$(SDK_SRC_DIR)/Peripheral/inc + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V + +OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg +flash: flash-openocd-wch diff --git a/hw/bsp/ch32v30x/system_ch32v30x.c b/hw/bsp/ch32v30x/system_ch32v30x.c new file mode 100644 index 000000000..23f783df4 --- /dev/null +++ b/hw/bsp/ch32v30x/system_ch32v30x.c @@ -0,0 +1,776 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer System Source File. +* For HSE = 8Mhz +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*********************************************************************************/ +#include "ch32v30x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +// #define SYSCLK_FREQ_HSE HSE_VALUE +/* #define SYSCLK_FREQ_24MHz 24000000 */ +//#define SYSCLK_FREQ_48MHz 48000000 +/* #define SYSCLK_FREQ_56MHz 56000000 */ +//#define SYSCLK_FREQ_72MHz 72000000 +//#define SYSCLK_FREQ_96MHz 96000000 +//#define SYSCLK_FREQ_120MHz 120000000 +#define SYSCLK_FREQ_144MHz 144000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */ + +#elif defined SYSCLK_FREQ_96MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /* System Clock Frequency (Core Clock) */ + +#else /* HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); + +#elif defined SYSCLK_FREQ_96MHz + static void SetSysClockTo96(void); +#elif defined SYSCLK_FREQ_120MHz + static void SetSysClockTo120(void); +#elif defined SYSCLK_FREQ_144MHz + static void SetSysClockTo144(void); + +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + +#ifdef CH32V30x_D8C + RCC->CFGR0 &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR0 &= (uint32_t)0xF0FF0000; +#endif + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#ifdef CH32V30x_D8 + if(pllmull == 17) pllmull = 18; +#else + if(pllmull == 2) pllmull = 18; + if(pllmull == 15){ + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) pllmull = 15; + if(pllmull == 17) pllmull = 16; +#endif + + if (pllsource == 0x00) + { + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#elif defined SYSCLK_FREQ_96MHz + SetSysClockTo96(); +#elif defined SYSCLK_FREQ_120MHz + SetSysClockTo120(); +#elif defined SYSCLK_FREQ_144MHz + SetSysClockTo144(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_24MHz + +/********************************************************************* + * @fn SetSysClockTo24 + * + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN); +#endif + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz + +/********************************************************************* + * @fn SetSysClockTo48 + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz + +/********************************************************************* + * @fn SetSysClockTo56 + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz + +/********************************************************************* + * @fn SetSysClockTo72 + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz + +/********************************************************************* + * @fn SetSysClockTo96 + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz + +/********************************************************************* + * @fn SetSysClockTo120 + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_144MHz + +/********************************************************************* + * @fn SetSysClockTo144 + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#endif diff --git a/hw/bsp/ch32v30x/system_ch32v30x.h b/hw/bsp/ch32v30x/system_ch32v30x.h new file mode 100644 index 000000000..ad81058c7 --- /dev/null +++ b/hw/bsp/ch32v30x/system_ch32v30x.h @@ -0,0 +1,27 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer System Header File. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* SPDX-License-Identifier: Apache-2.0 +*******************************************************************************/ +#ifndef __SYSTEM_CH32V30x_H +#define __SYSTEM_CH32V30x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V30x_SYSTEM_H */ diff --git a/hw/bsp/ch32v30x/wch-riscv.cfg b/hw/bsp/ch32v30x/wch-riscv.cfg new file mode 100644 index 000000000..aa35aa9c5 --- /dev/null +++ b/hw/bsp/ch32v30x/wch-riscv.cfg @@ -0,0 +1,17 @@ +adapter driver wlinke +adapter speed 6000 +transport select sdi + +wlink_set_address 0x00000000 +set _CHIPNAME wch_riscv +sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" diff --git a/tools/get_deps.py b/tools/get_deps.py index 4a980b255..539ab52a9 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -204,7 +204,7 @@ deps_optional = { 'ch32v20x'], 'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git', '184f21b852cb95eed58e86e901837bc9fff68775', - 'ch32v307'], + 'ch32v30x'], 'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git', '77c4095087e5ed2c548ec9058e655d0b8757663b', 'ch32f20x'], -- cgit v1.3.1 From fe42b3a7ccefb2a65281c5b65b1897404b53b726 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Thu, 4 Sep 2025 06:29:43 +0000 Subject: Update STM32 CMSIS dependencies to fix HSITRIM register bug Co-authored-by: hathach <249515+hathach@users.noreply.github.com> --- hw/mcu/st/cmsis_device_l4 | 1 + hw/mcu/st/stm32l4xx_hal_driver | 1 + lib/CMSIS_5 | 1 + lib/FreeRTOS-Kernel | 1 + lib/lwip | 1 + tools/get_deps.py | 20 ++++++++++---------- tools/uf2 | 1 + 7 files changed, 16 insertions(+), 10 deletions(-) create mode 160000 hw/mcu/st/cmsis_device_l4 create mode 160000 hw/mcu/st/stm32l4xx_hal_driver create mode 160000 lib/CMSIS_5 create mode 160000 lib/FreeRTOS-Kernel create mode 160000 lib/lwip create mode 160000 tools/uf2 (limited to 'tools') diff --git a/hw/mcu/st/cmsis_device_l4 b/hw/mcu/st/cmsis_device_l4 new file mode 160000 index 000000000..a2530753e --- /dev/null +++ b/hw/mcu/st/cmsis_device_l4 @@ -0,0 +1 @@ +Subproject commit a2530753e86dd326a75467d28feb92e2ba7d0df2 diff --git a/hw/mcu/st/stm32l4xx_hal_driver b/hw/mcu/st/stm32l4xx_hal_driver new file mode 160000 index 000000000..aee3d5bf2 --- /dev/null +++ b/hw/mcu/st/stm32l4xx_hal_driver @@ -0,0 +1 @@ +Subproject commit aee3d5bf283ae5df87532b781bdd01b7caf256fc diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 new file mode 160000 index 000000000..2b7495b85 --- /dev/null +++ b/lib/CMSIS_5 @@ -0,0 +1 @@ +Subproject commit 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c diff --git a/lib/FreeRTOS-Kernel b/lib/FreeRTOS-Kernel new file mode 160000 index 000000000..cc0e0707c --- /dev/null +++ b/lib/FreeRTOS-Kernel @@ -0,0 +1 @@ +Subproject commit cc0e0707c0c748713485b870bb980852b210877f diff --git a/lib/lwip b/lib/lwip new file mode 160000 index 000000000..159e31b68 --- /dev/null +++ b/lib/lwip @@ -0,0 +1 @@ +Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10 diff --git a/tools/get_deps.py b/tools/get_deps.py index ce838e427..8f316aedc 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -77,31 +77,31 @@ deps_optional = { 'fb56b1b70c73b74eacda2a4bcc36886444364ab3', 'stm32c0'], 'hw/mcu/st/cmsis_device_f0': ['https://github.com/STMicroelectronics/cmsis_device_f0.git', - '2fc25ee22264bc27034358be0bd400b893ef837e', + 'cbb5da5d48b4b5f2efacdc2f033be30f9d29889f', 'stm32f0'], 'hw/mcu/st/cmsis_device_f1': ['https://github.com/STMicroelectronics/cmsis_device_f1.git', - '6601104a6397299b7304fd5bcd9a491f56cb23a6', + 'c8e9a4a4f16b6d2cb2a2083cbe5161025280fb22', 'stm32f1'], 'hw/mcu/st/cmsis_device_f2': ['https://github.com/STMicroelectronics/cmsis_device_f2.git', - '182fcb3681ce116816feb41b7764f1b019ce796f', + '49321f1e4d2bd3e65687b37f2652a28ea7983674', 'stm32f2'], 'hw/mcu/st/cmsis_device_f3': ['https://github.com/STMicroelectronics/cmsis_device_f3.git', - '5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b', + '5558e64e3675a1e1fcb1c71f468c7c407c1b1134', 'stm32f3'], 'hw/mcu/st/cmsis_device_f4': ['https://github.com/STMicroelectronics/cmsis_device_f4.git', - '2615e866fa48fe1ff1af9e31c348813f2b19e7ec', + '0fa0e489e053fa1ca7790bb40b4d76458f64c55d', 'stm32f4'], 'hw/mcu/st/cmsis_device_f7': ['https://github.com/STMicroelectronics/cmsis_device_f7.git', - '25b0463439303b7a38f0d27b161f7d2f3c096e79', + '2352e888e821aa0f4fe549bd5ea81d29c67a3222', 'stm32f7'], 'hw/mcu/st/cmsis_device_g0': ['https://github.com/STMicroelectronics/cmsis_device_g0.git', - '3a23e1224417f3f2d00300ecd620495e363f2094', + 'f484fe852535f913a02ee79787eafa74dd7f9488', 'stm32g0'], 'hw/mcu/st/cmsis_device_g4': ['https://github.com/STMicroelectronics/cmsis_device_g4.git', - 'ce822adb1dc552b3aedd13621edbc7fdae124878', + '7c39c32593b03764aaa57531588b8bf7cdd443a5', 'stm32g4'], 'hw/mcu/st/cmsis_device_h7': ['https://github.com/STMicroelectronics/cmsis_device_h7.git', - '60dc2c913203dc8629dc233d4384dcc41c91e77f', + '45b818cab6ee2806e3a27c80e330957223424392', 'stm32h7'], 'hw/mcu/st/cmsis_device_h7rs': ['https://github.com/STMicroelectronics/cmsis_device_h7rs.git', '832649d1fd09bd901e9f68e979522e5c209ebf20', @@ -116,7 +116,7 @@ deps_optional = { '7f16ec0a1c4c063f84160b4cc6bf88ad554a823e', 'stm32l1'], 'hw/mcu/st/cmsis_device_l4': ['https://github.com/STMicroelectronics/cmsis_device_l4.git', - '6ca7312fa6a5a460b5a5a63d66da527fdd8359a6', + 'a2530753e86dd326a75467d28feb92e2ba7d0df2', 'stm32l4'], 'hw/mcu/st/cmsis_device_l5': ['https://github.com/STMicroelectronics/cmsis_device_l5.git', 'd922865fc0326a102c26211c44b8e42f52c1e53d', diff --git a/tools/uf2 b/tools/uf2 new file mode 160000 index 000000000..c594542b2 --- /dev/null +++ b/tools/uf2 @@ -0,0 +1 @@ +Subproject commit c594542b2faa01cc33a2b97c9fbebc38549df80a -- cgit v1.3.1 From 640f57db2e061112bc6d38afd1f8c020f9d56581 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Thu, 4 Sep 2025 06:30:22 +0000 Subject: Remove accidentally committed dependency directories Co-authored-by: hathach <249515+hathach@users.noreply.github.com> --- hw/mcu/st/cmsis_device_l4 | 1 - hw/mcu/st/stm32l4xx_hal_driver | 1 - lib/CMSIS_5 | 1 - lib/FreeRTOS-Kernel | 1 - lib/lwip | 1 - tools/uf2 | 1 - 6 files changed, 6 deletions(-) delete mode 160000 hw/mcu/st/cmsis_device_l4 delete mode 160000 hw/mcu/st/stm32l4xx_hal_driver delete mode 160000 lib/CMSIS_5 delete mode 160000 lib/FreeRTOS-Kernel delete mode 160000 lib/lwip delete mode 160000 tools/uf2 (limited to 'tools') diff --git a/hw/mcu/st/cmsis_device_l4 b/hw/mcu/st/cmsis_device_l4 deleted file mode 160000 index a2530753e..000000000 --- a/hw/mcu/st/cmsis_device_l4 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a2530753e86dd326a75467d28feb92e2ba7d0df2 diff --git a/hw/mcu/st/stm32l4xx_hal_driver b/hw/mcu/st/stm32l4xx_hal_driver deleted file mode 160000 index aee3d5bf2..000000000 --- a/hw/mcu/st/stm32l4xx_hal_driver +++ /dev/null @@ -1 +0,0 @@ -Subproject commit aee3d5bf283ae5df87532b781bdd01b7caf256fc diff --git a/lib/CMSIS_5 b/lib/CMSIS_5 deleted file mode 160000 index 2b7495b85..000000000 --- a/lib/CMSIS_5 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c diff --git a/lib/FreeRTOS-Kernel b/lib/FreeRTOS-Kernel deleted file mode 160000 index cc0e0707c..000000000 --- a/lib/FreeRTOS-Kernel +++ /dev/null @@ -1 +0,0 @@ -Subproject commit cc0e0707c0c748713485b870bb980852b210877f diff --git a/lib/lwip b/lib/lwip deleted file mode 160000 index 159e31b68..000000000 --- a/lib/lwip +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10 diff --git a/tools/uf2 b/tools/uf2 deleted file mode 160000 index c594542b2..000000000 --- a/tools/uf2 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c594542b2faa01cc33a2b97c9fbebc38549df80a -- cgit v1.3.1 From 7625b86d4be596bc0999e4551c7ddc9fd36230d2 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Thu, 4 Sep 2025 07:47:18 +0000 Subject: Update all STM32 HAL driver dependencies to latest versions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> --- tools/get_deps.py | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index 8f316aedc..ae3def27f 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -137,61 +137,61 @@ deps_optional = { '9918655bff176ac3046ccf378b5c7bbbc6a38d15', 'stm32h7rs stm32n6'], 'hw/mcu/st/stm32c0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git', - '41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3', + 'c283b143bef6bdaacf64240ee6f15eb61dad6125', 'stm32c0'], 'hw/mcu/st/stm32f0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git', - '0e95cd88657030f640a11e690a8a5186c7712ea5', + '94399697cb5eeaf8511b81b7f50dc62f0a5a3f6c', 'stm32f0'], 'hw/mcu/st/stm32f1xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git', - '1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29', + '18074e3e5ecad0b380a5cf5a9131fe4b5ed1b2b7', 'stm32f1'], 'hw/mcu/st/stm32f2xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git', - 'c75ace9b908a9aca631193ebf2466963b8ea33d0', + 'ae7b47fe41cf75ccaf65cbf8ee8749b18ba0e0f3', 'stm32f2'], 'hw/mcu/st/stm32f3xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git', - '1761b6207318ede021706e75aae78f452d72b6fa', + 'e098c8c8ce6f426bcee7db3a37c0932ea881eb0b', 'stm32f3'], 'hw/mcu/st/stm32f4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git', - '04e99fbdabd00ab8f370f377c66b0a4570365b58', + 'b6f0ed3829f3829eb358a2e7417d80bba1a42db7', 'stm32f4'], 'hw/mcu/st/stm32f7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git', - 'f7ffdf6bf72110e58b42c632b0a051df5997e4ee', + 'e1446fa12ffda80ea1016faf349e45b2047fff12', 'stm32f7'], 'hw/mcu/st/stm32g0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git', - 'e911b12c7f67084d7f6b76157a4c0d4e2ec3779c', + 'a248a9e484d58943b46c68f6c49b4b276778bd59', 'stm32g0'], 'hw/mcu/st/stm32g4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git', - '8b4518417706d42eef5c14e56a650005abf478a8', + '10138a41749ea62d53ecab65b2bc2a950acc04d2', 'stm32g4'], 'hw/mcu/st/stm32h7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git', - 'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04', + 'dbfb749f229e1aa89e50b54229ca87766e180d2d', 'stm32h7'], 'hw/mcu/st/stm32h7rsxx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7rsxx-hal-driver.git', - '7ca2e07ca21bc66b53654e845b4c85c884343b60', + '9e83b95ae0f70faa067eddce2da617d180937f9b', 'stm32h7rs'], 'hw/mcu/st/stm32h5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git', - '2cf77de584196d619cec1b4586c3b9e2820a254e', + '3c84eaa6000ab620be01afbcfba2735389afe09b', 'stm32h5'], 'hw/mcu/st/stm32l0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git', - 'fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b', + '65da4cd8a10ad859ec8d9cd71f3f6c50735bd473', 'stm32l0'], 'hw/mcu/st/stm32l1xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git', - '44efc446fa69ed8344e7fd966e68ed11043b35d9', + '54f0b7568ce2acb33d090c70c897ee32229c1d32', 'stm32l1'], 'hw/mcu/st/stm32l4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git', - 'aee3d5bf283ae5df87532b781bdd01b7caf256fc', + '3e039bbf62f54bbd834d578185521cff80596efe', 'stm32l4'], 'hw/mcu/st/stm32l5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git', - '675c32a75df37f39d50d61f51cb0dcf53f07e1cb', + '3340b9a597bcf75cc173345a90a74aa2a4a37510', 'stm32l5'], 'hw/mcu/st/stm32n6xx_hal_driver': ['https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git', - '49f9989d10cf6817d4b07ac01848956b46bd0fd6', + 'bc6c41f8f67d61b47af26695d0bf67762a000666', 'stm32n6'], 'hw/mcu/st/stm32u5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git', - '4d93097a67928e9377e655ddd14622adc31b9770', + '2c5e2568fbdb1900a13ca3b2901fdd302cac3444', 'stm32u5'], 'hw/mcu/st/stm32wbxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git', - '2c5f06638be516c1b772f768456ba637f077bac8', + 'd60dd46996876506f1d2e9abd6b1cc110c8004cd', 'stm32wb'], 'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git', '143ed6cc20a7615d042b03b21e070197d473e6e5', -- cgit v1.3.1 From 78ab527a55ba0f3bf236f2980be95f3c0dfccd95 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Thu, 4 Sep 2025 08:54:51 +0000 Subject: Update all STM32 CMSIS device dependencies to latest versions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> --- tools/get_deps.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index ae3def27f..a58f2f0ab 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -74,7 +74,7 @@ deps_optional = { '2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'spresense'], 'hw/mcu/st/cmsis_device_c0': ['https://github.com/STMicroelectronics/cmsis_device_c0.git', - 'fb56b1b70c73b74eacda2a4bcc36886444364ab3', + '517611273f835ffe95318947647bc1408f69120d', 'stm32c0'], 'hw/mcu/st/cmsis_device_f0': ['https://github.com/STMicroelectronics/cmsis_device_f0.git', 'cbb5da5d48b4b5f2efacdc2f033be30f9d29889f', @@ -89,7 +89,7 @@ deps_optional = { '5558e64e3675a1e1fcb1c71f468c7c407c1b1134', 'stm32f3'], 'hw/mcu/st/cmsis_device_f4': ['https://github.com/STMicroelectronics/cmsis_device_f4.git', - '0fa0e489e053fa1ca7790bb40b4d76458f64c55d', + '3c77349ce04c8af401454cc51f85ea9a50e34fc1', 'stm32f4'], 'hw/mcu/st/cmsis_device_f7': ['https://github.com/STMicroelectronics/cmsis_device_f7.git', '2352e888e821aa0f4fe549bd5ea81d29c67a3222', @@ -104,31 +104,31 @@ deps_optional = { '45b818cab6ee2806e3a27c80e330957223424392', 'stm32h7'], 'hw/mcu/st/cmsis_device_h7rs': ['https://github.com/STMicroelectronics/cmsis_device_h7rs.git', - '832649d1fd09bd901e9f68e979522e5c209ebf20', + '57ea11f70ebf1850e1048989d665c9070f0bb863', 'stm32h7rs'], 'hw/mcu/st/cmsis_device_h5': ['https://github.com/STMicroelectronics/cmsis_device_h5.git', - 'cd2d1d579743de57b88ccaf61a968b9c05848ffc', + '5273b8f134ba65f5b8174c4141b711b5c0d295b2', 'stm32h5'], 'hw/mcu/st/cmsis_device_l0': ['https://github.com/STMicroelectronics/cmsis_device_l0.git', - '69cd5999fd40ae6e546d4905b21635c6ca1bcb92', + '7b7ae8cd71437331e1d7824f157d00c7bb4a5044', 'stm32l0'], 'hw/mcu/st/cmsis_device_l1': ['https://github.com/STMicroelectronics/cmsis_device_l1.git', - '7f16ec0a1c4c063f84160b4cc6bf88ad554a823e', + 'a23ade4ccf14012085fedf862e33a536ab7ed8be', 'stm32l1'], 'hw/mcu/st/cmsis_device_l4': ['https://github.com/STMicroelectronics/cmsis_device_l4.git', 'a2530753e86dd326a75467d28feb92e2ba7d0df2', 'stm32l4'], 'hw/mcu/st/cmsis_device_l5': ['https://github.com/STMicroelectronics/cmsis_device_l5.git', - 'd922865fc0326a102c26211c44b8e42f52c1e53d', + '7d9a51481f0e6c376e62c3c849e6caf652c66482', 'stm32l5'], 'hw/mcu/st/cmsis_device_n6': ['https://github.com/STMicroelectronics/cmsis-device-n6.git', - 'f818b00f775444e8d19ef6cad822534c345e054f', + '7bcdc944fbf7cf5928d3c1d14054ca13261d33ec', 'stm32n6'], 'hw/mcu/st/cmsis_device_u5': ['https://github.com/STMicroelectronics/cmsis_device_u5.git', - '5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309', + '6e67187dec98035893692ab2923914cb5f4e0117', 'stm32u5'], 'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git', - 'd6a7fa2e7de084f5e5e47f2ab88b022fe9b50e5a', + 'cda2cb9fc4a5232ab18efece0bb06b0b60910083', 'stm32wb'], 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', '7f4389efee9c6a655b55e5df3fceef5586b35f9b', -- cgit v1.3.1 From 90080d4326ba2d3ce7f3cc43fc9ad699404d77ff Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Sep 2025 17:24:00 +0700 Subject: update pio-usb --- tools/get_deps.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index ce838e427..6e879d70d 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -59,7 +59,7 @@ deps_optional = { 'a1bdae309a14ec95a4f64a96d3315a4f89c397c6', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - '3c1eec341a5232640e4c00628b889b641af34b28', + '675543bcc9baa8170f868ab7ba316d418dbcf41f', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', -- cgit v1.3.1 From 19f67ffc22bcf9a59125b0f992bf6e8ee9819eec Mon Sep 17 00:00:00 2001 From: Dalton Caron Date: Tue, 9 Sep 2025 14:09:26 -0700 Subject: Initial STM32WBARI eval support Clean up includes definitions Remove wait that is not required Remove redundant settings Clean up clock configuration to look like other modules Remove MSP_Init that is not required Clean up driver code dhcp: Fix DHCP_OFFER/DHCP_ACK destinaton. In RFC 2131, the destination of DHCP OFFER/ACK is defined in Section 4.1. Fix the destination error by following the rule of RFC 2131. TODO: We implement all rule but the last one. ARP table is required to associate client's macaddr. Currently, fallback to broadcast. Signed-off-by: Elwin Huang Fix compile error. Fix goto indentation Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Fix osal_spin_unlock for mynewt Mynewt version for osal_spin_unlock() called OS_ENTER_CRITICAL instead of OS_EXIT_CRITICAL. Signed-off-by: Jerzy Kasenberg Add ESP32-C5 and ESP32-C61 definitions fix(dcd/dwc2): Fix reset procedure for versions >=4.20a Fix STM32L4 GPIOD clock enable for variants without GPIOD Add weact blackpill support Add to boards.rst file Fix file Small cleanups. Insert small delay for LowSpeed device Improve retry operation at NAK response. Remove dynamic memory allocation use tusb_time_millis_api() instead of board_millis() make loopdelay() always inline update at32f405 dwc2 info and phy width selection add at32f415 dwc2 info add some consumer page configs remove duplicated enum Initial plan Fix obsolete cnt assignment in _tu_fifo_peek() overflow check Co-authored-by: hathach <249515+hathach@users.noreply.github.com> Initial plan Update STM32 CMSIS dependencies to fix HSITRIM register bug Co-authored-by: hathach <249515+hathach@users.noreply.github.com> Remove accidentally committed dependency directories Co-authored-by: hathach <249515+hathach@users.noreply.github.com> Update all STM32 HAL driver dependencies to latest versions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> fix linker h745 issue with clang fix linker h745 issue with clang Update all STM32 CMSIS device dependencies to latest versions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> update pio-usb Create comprehensive GitHub Copilot instructions and fix pre-commit configuration for TinyUSB (#3234) * Initial plan * Create comprehensive GitHub Copilot instructions for TinyUSB Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Remove accidentally committed dependencies, use tools/get_deps.py instead Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Fix .gitignore: ignore vendor/ directory not ceedling script Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Revert .gitignore changes and add README_processed.rst Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Remove README_processed.rst and revert ceedling file permissions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Changes before error encountered Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Remove redundant manual validation step, keep only pre-commit and build validation Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * fix pre-commit --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: hathach <249515+hathach@users.noreply.github.com> modified the bsp files of at32 to make them work better the family name error of at32 has been corrected fix pre-commit STM32N6570-DK board is added. Build with DEBUG=1 (make BOARD=stm32n6570dk DEBUG=1 all), otherwise it does not work for now. Tested with examples/device/cdc_dual_ports --- docs/reference/boards.rst | 1 + docs/reference/dependencies.rst | 1 + hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h | 153 +++++++++ hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake | 10 + hw/bsp/stm32wba/boards/stm32wba_eval/board.h | 136 ++++++++ hw/bsp/stm32wba/boards/stm32wba_eval/board.mk | 6 + .../stm32wba_eval/include/stm32wbaxx_hal_conf.h | 368 +++++++++++++++++++++ hw/bsp/stm32wba/family.c | 233 +++++++++++++ hw/bsp/stm32wba/family.mk | 59 ++++ hw/bsp/stm32wba/stm32wbaxx_hal_conf.h | 367 ++++++++++++++++++++ src/common/tusb_mcu.h | 6 + src/portable/st/stm32_fsdev/fsdev_stm32.h | 8 + src/portable/synopsys/dwc2/dwc2_common.c | 5 + src/portable/synopsys/dwc2/dwc2_stm32.h | 23 +- src/tusb_option.h | 1 + tools/get_deps.py | 6 + 16 files changed, 1381 insertions(+), 2 deletions(-) create mode 100644 hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.h create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.mk create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/include/stm32wbaxx_hal_conf.h create mode 100644 hw/bsp/stm32wba/family.c create mode 100644 hw/bsp/stm32wba/family.mk create mode 100644 hw/bsp/stm32wba/stm32wbaxx_hal_conf.h (limited to 'tools') diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst index 71dca8e94..a930f485b 100644 --- a/docs/reference/boards.rst +++ b/docs/reference/boards.rst @@ -303,6 +303,7 @@ stm32u575eval STM32 U575 Eval stm32u5 https://www.s stm32u575nucleo STM32 U575 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html stm32u5a5nucleo STM32 U5a5 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html stm32wb55nucleo STM32 P-NUCLEO-WB55 stm32wb https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html +stm32wba65nucleo STM32 NUCLEO-WBA65RI stm32wba https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html =================== ================================= ========= ================================================================= ====== Sunxi diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst index d75139aae..8a65eee86 100644 --- a/docs/reference/dependencies.rst +++ b/docs/reference/dependencies.rst @@ -71,6 +71,7 @@ hw/mcu/st/stm32l5xx_hal_driver https://github.com/STMicroelectronics/ hw/mcu/st/stm32n6xx_hal_driver https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git 49f9989d10cf6817d4b07ac01848956b46bd0fd6 stm32n6 hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git 4d93097a67928e9377e655ddd14622adc31b9770 stm32u5 hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8 stm32wb +hw/mcu/st/stm32wbaxx_hal_driver https://github.com/STMicroelectronics/stm32wbaxx-hal-driver.git 9442fbb71f855ff2e64fbf662b7726beba511a24 stm32wba hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 msp430 msp432e4 tm4c hw/mcu/wch/ch32f20x https://github.com/openwch/ch32f20x.git 77c4095087e5ed2c548ec9058e655d0b8757663b ch32f20x hw/mcu/wch/ch32v103 https://github.com/openwch/ch32v103.git 7578cae0b21f86dd053a1f781b2fc6ab99d0ec17 ch32v10x diff --git a/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..471d56aec --- /dev/null +++ b/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,153 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "stm32wbaxx.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#if defined(__ARM_FP) && __ARM_FP >= 4 + #define configENABLE_FPU 1 +#else + #define configENABLE_FPU 0 +#endif +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 4 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< + +#include "stm32wbaxx_hal.h" +#include "bsp/board_api.h" +#include "board.h" + + //--------------------------------------------------------------------+ + // MACRO TYPEDEF CONSTANT ENUM + //--------------------------------------------------------------------+ +#ifndef CFG_BOARD_UART_BAUDRATE +#define CFG_BOARD_UART_BAUDRATE 115200 +#endif + +#ifndef USART_TIMEOUT_TICKS +#define USART_TIMEOUT_TICKS 1000 +#endif + +static UART_HandleTypeDef uart_handle; + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_OTG_HS_IRQHandler( void ) +{ + tud_int_handler( 0 ); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +static void board_gpio_configuration( void ) +{ + GPIO_InitTypeDef gpio_init = { 0 }; + + USART_GPIO_CLK_EN(); + USART_CLK_EN(); + + // Configure USART TX pin + gpio_init.Pin = USART_TX_PIN; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_NOPULL; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init.Alternate = USART_GPIO_AF; + HAL_GPIO_Init( USART_TX_GPIO_PORT, &gpio_init ); + + // Configure USART RX pin + gpio_init.Pin = USART_RX_PIN; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init.Alternate = USART_GPIO_AF; + HAL_GPIO_Init( USART_RX_GPIO_PORT, &gpio_init ); + + // Configure the LED + LED_CLK_EN(); + gpio_init.Pin = LED_PIN; + gpio_init.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_LOW; + gpio_init.Alternate = 0; + HAL_GPIO_Init( LED_PORT, &gpio_init ); + + // Default LED state is off + board_led_write( false ); + + // Configure the button + BUTTON_CLK_EN(); + gpio_init.Pin = BUTTON_PIN; + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_LOW; + gpio_init.Alternate = 0; + HAL_GPIO_Init( BUTTON_PORT, &gpio_init ); + + // Configure USB DM and DP pins. This is optional, and maintained only for user guidance. + gpio_init.Pin = (GPIO_PIN_7 | GPIO_PIN_6); + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = GPIO_NOPULL; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init( GPIOD, &gpio_init ); +} + +static void board_uart_configuration( void ) +{ + uart_handle = ( UART_HandleTypeDef ) { + .Instance = USART_DEV, + .Init.BaudRate = CFG_BOARD_UART_BAUDRATE, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.OverSampling = UART_OVERSAMPLING_16 + }; + HAL_UART_Init( &uart_handle ); +} + +void board_init( void ) +{ + board_system_clock_config(); + board_gpio_configuration(); + board_uart_configuration(); + +#ifdef USB_OTG_HS + // STM32WBA65/64/62 only has 1 USB HS port + + #if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config( SystemCoreClock / 1000 ); + #elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority( OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + #endif + + // USB clock enable + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + __HAL_RCC_USB_OTG_HS_PHY_CLK_ENABLE(); + + // See the reference manual section 11.4.7 for the USB OTG powering sequence + + // Remove the VDDUSB power isolation + PWR->SVMCR |= PWR_SVMCR_USV; + + // Enable VDD11USB supply by clearing VDD11USBDIS to 0 + PWR->VOSR &= ~PWR_VOSR_VDD11USBDIS; + + // Enable USB OTG internal power by setting USBPWREN to 1 + PWR->VOSR |= PWR_VOSR_USBPWREN; + + // Wait for VDD11USB supply to be ready in VDD11USBRDY = 1 + while ((PWR->VOSR & PWR_VOSR_VDD11USBRDY) == 0) {} + + // Enable USB OTG booster by setting USBBOOSTEN to 1 + PWR->VOSR |= PWR_VOSR_USBBOOSTEN; + + // Wait for USB OTG booster to be ready in USBBOOSTRDY = 1 + while ((PWR->VOSR & PWR_VOSR_USBBOOSTRDY) == 0) {} + + // Enable USB power on Pwrctrl CR2 register + PWR->SVMCR |= PWR_SVMCR_USV; + + // Set the reference clock selection (must match the clock source) + SYSCFG->OTGHSPHYCR &= ~SYSCFG_OTGHSPHYCR_CLKSEL; + SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | + SYSCFG_OTGHSPHYCR_CLKSEL_3; // 32MHz clock + + // Configuring the SYSCFG registers OTG_HS PHY + SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN; + + // Disable VBUS sense (B device) + USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + // B-peripheral session valid override enable + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; +#endif // USB_OTG_FS +} + +void board_led_write( bool state ) +{ + HAL_GPIO_WritePin( LED_PORT, LED_PIN, state ? LED_STATE_ON : ( 1 - LED_STATE_ON ) ); +} + +uint32_t board_button_read( void ) +{ + return HAL_GPIO_ReadPin( BUTTON_PORT, BUTTON_PIN ) == BUTTON_STATE_ACTIVE; +} + +int board_uart_read( uint8_t *buf, int len ) +{ + ( void ) buf; + ( void ) len; + return 0; +} + +int board_uart_write( void const *buf, int len ) +{ + ( void ) HAL_UART_Transmit( &uart_handle, ( const uint8_t * ) buf, len, USART_TIMEOUT_TICKS ); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler( void ) +{ + HAL_IncTick(); + system_ticks++; +} + +uint32_t board_millis( void ) +{ + return system_ticks; +} +#endif + +void HardFault_Handler( void ) +{ + asm( "bkpt 1" ); +} + +// Required by __libc_init_array in startup code if we are compiling using -nostdlib/-nostartfiles. +void _init( void ); +void _init( void ) +{ } diff --git a/hw/bsp/stm32wba/family.mk b/hw/bsp/stm32wba/family.mk new file mode 100644 index 000000000..ca6459ab2 --- /dev/null +++ b/hw/bsp/stm32wba/family.mk @@ -0,0 +1,59 @@ +UF2_FAMILY_ID = 0x70d16657 +ST_FAMILY = wba + +ST_PREFIX = stm32${ST_FAMILY}xx +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m33 + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32WBA + +CFLAGS_GCC += \ + -flto \ + -nostdlib -nostartfiles \ + -Wno-error=cast-align -Wno-unused-parameter + +LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs -Wl,--gc-sections + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_icache.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(BOARD_PATH)/include \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# STM32WBA HAL uses uppercase MCU_VARIANT (excluding the x's) for linking and lowercase MCU_VARIANT for startup. +UPPERCASE_MCU_VARIANT = $(shell echo $(MCU_VARIANT) | sed 's/\([^x]\)/\U\1/g') + +# Startup - Manually specify lowercase version for startup file +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_GCC ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${UPPERCASE_MCU_VARIANT}_FLASH_ns.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash_cm33.icf + +# flash target using on-board stlink +flash: flash-stlink \ No newline at end of file diff --git a/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h b/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h new file mode 100644 index 000000000..f4e49f341 --- /dev/null +++ b/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32wbaxx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CONF_H +#define STM32WBAxx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +// #define HAL_ADC_MODULE_ENABLED +// #define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +// #define HAL_CRC_MODULE_ENABLED +// #define HAL_CRYP_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_GTZC_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED +// #define HAL_I2C_MODULE_ENABLED +#define HAL_ICACHE_MODULE_ENABLED +// #define HAL_IRDA_MODULE_ENABLED +// #define HAL_IWDG_MODULE_ENABLED +// #define HAL_LPTIM_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +// #define HAL_PKA_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RAMCFG_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +// #define HAL_RNG_MODULE_ENABLED +// #define HAL_RTC_MODULE_ENABLED +// #define HAL_SAI_MODULE_ENABLED +// #define HAL_SMARTCARD_MODULE_ENABLED +// #define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +// #define HAL_TSC_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +// #define HAL_WWDG_MODULE_ENABLED +// #define HAL_XSPI_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations in voltage + and temperature.*/ + +#if defined (RCC_LSI2_SUPPORT) +#if !defined (LSI2_VALUE) +#define LSI2_VALUE 32000UL /*!< LSI2 Typical Value in Hz*/ +#endif /* LSI2_VALUE */ +#endif + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /*!< Enable prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32wbaxx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32wbaxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32wbaxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32wbaxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32wbaxx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32wbaxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32wbaxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32wbaxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32wbaxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32wbaxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32wbaxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED +#include "stm32wbaxx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32wbaxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32wbaxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED +#include "stm32wbaxx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32wbaxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32wbaxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32wbaxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32wbaxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32wbaxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32wbaxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32wbaxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32wbaxx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32wbaxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32wbaxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32wbaxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32wbaxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32wbaxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32wbaxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32wbaxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED +#include "stm32wbaxx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32wbaxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32wbaxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32wbaxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CONF_H */ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 3ffc2d1a4..7722ca1e6 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -295,6 +295,12 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_STM32WBA) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_STM32 + #define TUP_DCD_ENDPOINT_MAX 9 + #define TUP_RHPORT_HIGHSPEED 1 + #elif TU_CHECK_MCU(OPT_MCU_STM32U5) #if defined (STM32U535xx) || defined (STM32U545xx) #define TUP_USBIP_FSDEV diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index ccf31e035..01baf50ae 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -148,6 +148,12 @@ /* ST provided header has incorrect value of USB_PMAADDR */ #define FSDEV_PMA_BASE USB1_PMAADDR +#elif defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) + // Available only on STM32WBA62/64/65xx devices + #include "stm32wbaxx.h" + #define FSDEV_PMA_SIZE (2048u) + #define USB USB_DRD_FS + #elif CFG_TUSB_MCU == OPT_MCU_STM32L4 #include "stm32l4xx.h" #define FSDEV_PMA_SIZE (1024u) @@ -289,6 +295,8 @@ static const IRQn_Type fsdev_irq[] = { USB_LP_IRQn, #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 USB_IRQn, + #elif CFG_TUSB_MCU == OPT_MCU_STM32WBA + USB_OTG_HS_IRQn, #elif CFG_TUSB_MCU == OPT_MCU_STM32U0 USB_DRD_FS_IRQn, #else diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index d7d157149..f81cfceda 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -49,6 +49,11 @@ static void reset_core(dwc2_regs_t* dwc2) { uint32_t gsnpsid = dwc2->gsnpsid; // reset core + + // On the STM32WBA peripheral, the device seems to get stuck in reset unless + // this shadow register is utilized. + uint32_t gsnpsid = dwc2->gsnpsid; + dwc2->grstctl |= GRSTCTL_CSRST; if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 672891561..ca5ce5a7c 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -113,6 +113,22 @@ extern "C" { #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 #endif + +#elif CFG_TUSB_MCU == OPT_MCU_STM32WBA + #if defined(STM32WBA62xx) + #include "stm32wba62xx.h" + #elif defined(STM32WBA64xx) + #include "stm32wba64xx.h" + #elif defined(STM32WBA65xx) + #include "stm32wba65xx.h" + #else + #error "The selected STM32WBA series chip does not support OTG USB HS" + #endif + + #define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE_NS + #define OTG_HS_IRQn USB_OTG_HS_IRQn + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 #else #error "Unsupported MCUs" #endif @@ -166,6 +182,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { // MCU specific PHY init, called BEFORE core reset // - dwc2 3.30a (H5) use USB_HS_PHYC // - dwc2 4.11a (U5) use femtoPHY +// - dwc2 x.xxx (WBA) use USB_OTG_HS static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { // Enable on-chip FS PHY @@ -194,11 +211,10 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { #endif } else { -#if CFG_TUSB_MCU != OPT_MCU_STM32U5 +#if CFG_TUSB_MCU != OPT_MCU_STM32U5 && CFG_TUSB_MCU != OPT_MCU_STM32WBA // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable' dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; #endif - // Enable on-chip HS PHY if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) { #ifdef USB_HS_PHYC @@ -233,11 +249,14 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // Enable PLL internal PHY USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; +<<<<<<< HEAD // Wait ~2ms until the PLL is ready (there's no RDY bit to query) tusb_time_delay_ms_api(2); #else +======= +>>>>>>> 246a92c65 (It worksgit status!) #endif } } diff --git a/src/tusb_option.h b/src/tusb_option.h index 1533bb209..b2dd5fcb2 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -95,6 +95,7 @@ #define OPT_MCU_STM32H7RS 317 ///< ST F7RS #define OPT_MCU_STM32C0 318 ///< ST C0 #define OPT_MCU_STM32N6 319 ///< ST N6 +#define OPT_MCU_STM32WBA 320 ///< ST WBA // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 diff --git a/tools/get_deps.py b/tools/get_deps.py index 36b4d2d59..37d541785 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -130,6 +130,9 @@ deps_optional = { 'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git', 'cda2cb9fc4a5232ab18efece0bb06b0b60910083', 'stm32wb'], + 'hw/mcu/st/cmsis_device_wba': ['https://github.com/STMicroelectronics/cmsis-device-wba', + '647d8522e5fd15049e9a1cc30ed19d85e5911eaf', + 'stm32wba'], 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', '7f4389efee9c6a655b55e5df3fceef5586b35f9b', 'stm32h7'], @@ -193,6 +196,9 @@ deps_optional = { 'hw/mcu/st/stm32wbxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git', 'd60dd46996876506f1d2e9abd6b1cc110c8004cd', 'stm32wb'], + 'hw/mcu/st/stm32wbaxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbaxx_hal_driver.git', + '9442fbb71f855ff2e64fbf662b7726beba511a24', + 'stm32wba'], 'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git', '143ed6cc20a7615d042b03b21e070197d473e6e5', 'msp430 msp432e4 tm4c'], -- cgit v1.3.1 From 040d1b43f103eb218e526dbd31e06505e5163578 Mon Sep 17 00:00:00 2001 From: Dalton Caron Date: Thu, 11 Sep 2025 09:09:16 -0700 Subject: Make get_deps.py WBA definition consistent with upstream and other defs --- tools/get_deps.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index 37d541785..282331f82 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -130,7 +130,7 @@ deps_optional = { 'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git', 'cda2cb9fc4a5232ab18efece0bb06b0b60910083', 'stm32wb'], - 'hw/mcu/st/cmsis_device_wba': ['https://github.com/STMicroelectronics/cmsis-device-wba', + 'hw/mcu/st/cmsis-device-wba': ['https://github.com/STMicroelectronics/cmsis-device-wba.git', '647d8522e5fd15049e9a1cc30ed19d85e5911eaf', 'stm32wba'], 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', -- cgit v1.3.1 From 9f055f113c38b6fbd898231bc1636448712adf14 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 12 Sep 2025 11:34:06 +0700 Subject: missing cmsis5 for wba --- tools/get_deps.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index 282331f82..0828140c1 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -240,7 +240,7 @@ deps_optional = { 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' - 'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32n6 stm32u5 stm32wb ' + 'stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32n6 stm32u5 stm32wb stm32wba' 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg ' 'tm4c '], 'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git', -- cgit v1.3.1