From 161c95f1b7d63394b184a351f7bbaa54841c02f6 Mon Sep 17 00:00:00 2001 From: Martino Facchin Date: Thu, 4 May 2023 14:42:32 +0200 Subject: renesas: update fsp to 4.0.0 --- tools/get_deps.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/get_deps.py b/tools/get_deps.py index d8b044343..4f2f7b089 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -27,7 +27,7 @@ deps_optional = { 'hw/mcu/nxp/mcux-sdk' : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git' ], 'hw/mcu/nxp/nxp_sdk' : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git' ], 'hw/mcu/raspberry_pi/Pico-PIO-USB' : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git' ], - 'hw/mcu/renesas/fsp' : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git' ], + 'hw/mcu/renesas/fsp' : ['9860fae1f180340a0e3c097dc6e91323cf83b926', 'https://github.com/renesas/fsp.git' ], 'hw/mcu/renesas/rx' : ['706b4e0cf485605c32351e2f90f5698267996023', 'https://github.com/kkitayam/rx_device.git' ], 'hw/mcu/silabs/cmsis-dfp-efm32gg12b' : ['f1c31b7887669cb230b3ea63f9b56769078960bc', 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git' ], 'hw/mcu/sony/cxd56/spresense-exported-sdk' : ['2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'https://github.com/sonydevworld/spresense-exported-sdk.git' ], -- cgit v1.3.1 From 071c30f381074c780bfb068cd31ed0801336bea6 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 4 Jul 2023 19:27:37 +0700 Subject: update fsp to version 4.5, correct RA BSP. Fix ETM Trace with 6m5 by lowering PLL to 128Mhz. --- hw/bsp/family_support.cmake | 4 ++ hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 6 -- hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h | 2 +- hw/bsp/ra/boards/ra6m1_ek/board.h | 10 ++-- hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h | 7 --- hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h | 2 +- hw/bsp/ra/boards/ra6m5_ek/board.h | 16 +++--- hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h | 70 +++++++++++++---------- hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 70 +++++++++++++++++++++++ hw/bsp/ra/family.c | 15 ++--- hw/bsp/ra/family.cmake | 8 +-- tools/get_deps.py | 2 +- 12 files changed, 142 insertions(+), 70 deletions(-) (limited to 'tools') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index b2e61a824..5b97eb5e4 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -227,6 +227,10 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) if (DEFINED LOG) target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) + if (LOG STREQUAL "3") + # no inline for debug level 3 + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=) + endif () endif() if (RTOS STREQUAL "freertos") diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h index 700d9b29f..19bb473eb 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -31,12 +31,6 @@ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0 - -#define BSP_FEATURE_TFU_SUPPORTED 0 -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) - // for SystemInit() void bsp_init(void * p_args); diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h index 930fa3547..554126523 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_8_0) /* PLL Mul x8 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h index 2765a6a5f..f73a08fc0 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.h +++ b/hw/bsp/ra/boards/ra6m1_ek/board.h @@ -38,12 +38,10 @@ extern "C" { #define BUTTON_STATE_ACTIVE 0 static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, + { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT }, + { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, + // USB FS + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS }, }; #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h index c2b23b16c..75a331fc2 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -60,13 +60,6 @@ extern "C" { #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0 -#define BSP_FEATURE_TFU_SUPPORTED 0 -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) - -#define BSP_CFG_USE_LOW_VOLTAGE_MODE 0 - // for SystemInit() void bsp_init(void * p_args); diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h index 1cdfae949..945a6010b 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h index c88e9a0a2..779f71810 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.h +++ b/hw/bsp/ra/boards/ra6m5_ek/board.h @@ -41,22 +41,24 @@ static const ioport_pin_cfg_t board_pin_cfg[] = { { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - // USB FS D+, D-, VBus + // USB FS { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - // USB HS D+, D-, VBus + // USB HS { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, // ETM Trace - { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, - { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE }, + #ifdef TRACE_ETM + { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + #endif }; #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h index 77ac41d0a..9bb496dd6 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h @@ -1,35 +1,45 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CLOCK_CFG_H_ #define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) + +#define BSP_CFG_CLOCKS_SECURE (0) #define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ -#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */ -#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ -#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ -#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */ -#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ -#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ -#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ + +#ifdef TRACE_ETM +// Due to ozone fixed trace clock div = 1, PLL is limited around 100Mhz. This use 128 Mhz +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(16U,0U)) /* PLL Mul x16.0 */ +#else +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ +#endif + +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ + + #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug index fa55d40b2..8a1262138 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug +++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug @@ -33,3 +33,73 @@ void BeforeTargetConnect (void) { // Trace pin init is done by J-Link script file as J-Link script files are IDE independent // } + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetReset (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr != 0xFFFFFFFF) { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + } else { + Util.Log("Project file error: failed to get program base"); + } + + PC = Elf.GetEntryPointPC(); + + if (PC != 0xFFFFFFFF) { + Target.SetReg("PC", PC); + } else if (VectorTableAddr != 0xFFFFFFFF) { + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + + if (VectorTableAddr != 0xFFFFFFFF) { + SP = Target.ReadU32(VectorTableAddr); + Target.SetReg("SP", SP); + } else { + Util.Log("Project file error: failed to get program base"); + } + + PC = Elf.GetEntryPointPC(); + + if (PC != 0xFFFFFFFF) { + Target.SetReg("PC", PC); + } else if (VectorTableAddr != 0xFFFFFFFF) { + PC = Target.ReadU32(VectorTableAddr + 4); + Target.SetReg("PC", PC); + } +} diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 08823dd52..769678954 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -36,15 +36,14 @@ #endif #include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" +#include "renesas.h" #ifdef __GNUC__ #pragma GCC diagnostic pop #endif -#include "r_ioport.h" -#include "r_ioport_api.h" -#include "renesas.h" - #include "bsp/board.h" #include "board.h" @@ -86,15 +85,17 @@ void board_init(void) R_IOPORT_Open(&port_ctrl, &family_pin_cfg); #ifdef TRACE_ETM - // Enable trace clock with div 1 (100 Mhz) - R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk; + // Enable trace clock (max 100Mhz) = PLL / div + // Somehow ozone/jtrace always fixed trace div to 1 therefore for ETM tracing working reliably + // PLL is limited around 100Mhz + R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01; #endif // Enable USB module R_MSTP->MSTPCRB &= ~(1U << 11U); // FS #ifdef R_USB_HS0_BASE - R_MSTP->MSTPCRB &= ~(1U << 12U); // HS +// R_MSTP->MSTPCRB &= ~(1U << 12U); // HS #endif #if CFG_TUSB_OS == OPT_OS_FREERTOS diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 828559e5e..f4e978230 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -37,14 +37,14 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all/bsp_security.c ${FSP_RA}/src/r_ioport/r_ioport.c ) - target_compile_definitions(${BOARD_TARGET} PUBLIC - _RA_TZ_NONSECURE - ) + # ETM Trace option + if (TRACE_ETM STREQUAL "1") + target_compile_definitions(${BOARD_TARGET} PUBLIC TRACE_ETM) + endif () target_compile_options(${BOARD_TARGET} PUBLIC -ffreestanding ) - target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} diff --git a/tools/get_deps.py b/tools/get_deps.py index fa47a8067..21ad539c4 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -57,7 +57,7 @@ deps_optional = { '58879cfa0eca5725d8db6443ec17f8896a321042', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', - '9860fae1f180340a0e3c097dc6e91323cf83b926', + 'd52e5a6a59b7c638da860c2bb309b6e78e752ff8', 'ra'], 'hw/mcu/renesas/rx': ['https://github.com/kkitayam/rx_device.git', '706b4e0cf485605c32351e2f90f5698267996023', -- cgit v1.3.1 From f295aaf1851eb270070af7292d1f100f7172daf4 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Jul 2023 11:55:54 +0700 Subject: add hcd abort xfer for rp2040 pio usb --- hw/bsp/rp2040/board.h | 12 ++++++------ src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 7 ++----- tools/get_deps.py | 2 +- 3 files changed, 9 insertions(+), 12 deletions(-) (limited to 'tools') diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h index 934e1c7ae..063c9580e 100644 --- a/hw/bsp/rp2040/board.h +++ b/hw/bsp/rp2040/board.h @@ -54,19 +54,19 @@ // default to pin on Adafruit Feather rp2040 USB Host or Tester if defined //--------------------------------------------------------------------+ -// #define USE_ADAFRUIT_RP2040_TESTER -#ifdef USE_ADAFRUIT_RP2040_TESTER -#define PICO_DEFAULT_PIO_USB_DP_PIN 20 -#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 +// #define USE_ADAFRUIT_FEATHER_RP2040_USBHOST +#ifdef USE_ADAFRUIT_FEATHER_RP2040_USBHOST +#define PICO_DEFAULT_PIO_USB_DP_PIN 16 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 #endif #ifndef PICO_DEFAULT_PIO_USB_DP_PIN -#define PICO_DEFAULT_PIO_USB_DP_PIN 16 +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 #endif // VBUS enable pin and its active state #ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN -#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 #endif // VBUS enable state diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index fa285327c..bb41ad638 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -139,11 +139,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * } bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - // TODO not implemented yet - return false; + uint8_t const pio_rhport = RHPORT_PIO(rhport); + return pio_usb_host_endpoint_abort_transfer(pio_rhport, dev_addr, ep_addr); } bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) diff --git a/tools/get_deps.py b/tools/get_deps.py index 9b89c5e4c..d6505a1d9 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -54,7 +54,7 @@ deps_optional = { '950819b7de9b32f92c3edf396bc5ffb8d66e7009', 'kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - '58879cfa0eca5725d8db6443ec17f8896a321042', + 'd00a10a8c425d0d40f81b87169102944b01f3bb3', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', '8dc14709f2a6518b43f71efad70d900b7718d9f1', -- cgit v1.3.1 From 789e478d4d47cca9bd1cf7983a49c13476c54b78 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Aug 2023 13:16:37 +0700 Subject: add portenta c33 bsp, add flash by dfu-util --- examples/rules.mk | 15 +- hw/bsp/family_support.cmake | 12 + hw/bsp/ra/boards/portenta_c33/board.cmake | 25 ++ hw/bsp/ra/boards/portenta_c33/board.h | 68 ++++ hw/bsp/ra/boards/portenta_c33/board.mk | 12 + .../ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h | 63 ++++ .../portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 387 +++++++++++++++++++++ .../ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h | 37 ++ hw/bsp/ra/boards/portenta_c33/portenta_c33.ld | 25 ++ hw/bsp/ra/family.cmake | 5 + hw/bsp/ra/family.mk | 2 + tools/make/toolchain/arm_gcc_rules.mk | 3 +- 14 files changed, 665 insertions(+), 5 deletions(-) create mode 100644 hw/bsp/ra/boards/portenta_c33/board.cmake create mode 100644 hw/bsp/ra/boards/portenta_c33/board.h create mode 100644 hw/bsp/ra/boards/portenta_c33/board.mk create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/portenta_c33.ld (limited to 'tools') diff --git a/examples/rules.mk b/examples/rules.mk index 44698b019..44d6b84c8 100644 --- a/examples/rules.mk +++ b/examples/rules.mk @@ -88,7 +88,7 @@ linkermap: $(BUILD)/$(PROJECT).elf # Flash Targets # --------------------------------------- -# Jlink binary +# --------------- Jlink ----------------- ifeq ($(OS),Windows_NT) JLINKEXE = JLink.exe else @@ -110,10 +110,12 @@ $(BUILD)/$(BOARD).jlink: $(BUILD)/$(PROJECT).hex flash-jlink: $(BUILD)/$(BOARD).jlink $(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $< +# --------------- stm32 cube programmer ----------------- # Flash STM32 MCU using stlink with STM32 Cube Programmer CLI flash-stlink: $(BUILD)/$(PROJECT).elf STM32_Programmer_CLI --connect port=swd --write $< --go +# --------------- xfel ----------------- $(BUILD)/$(PROJECT)-sunxi.bin: $(BUILD)/$(PROJECT).bin $(PYTHON) $(TOP)/tools/mksunxi.py $< $@ @@ -121,18 +123,23 @@ flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin xfel spinor write 0 $< xfel reset -# Flash using pyocd +# --------------- pyocd ----------------- PYOCD_OPTION ?= flash-pyocd: $(BUILD)/$(PROJECT).hex pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $< #pyocd reset -t $(PYOCD_TARGET) -# Flash using openocd +# --------------- openocd ----------------- OPENOCD_OPTION ?= flash-openocd: $(BUILD)/$(PROJECT).elf openocd $(OPENOCD_OPTION) -c "program $< verify reset exit" -# flash with Black Magic Probe +# --------------- dfu-util ----------------- +DFU_UTIL_OPTION ?= -a 0 +flash-dfu-util: $(BUILD)/$(PROJECT).bin + dfu-util -R $(DFU_UTIL_OPTION) -D $< + +# --------------- Black Magic ----------------- # This symlink is created by https://github.com/blacksphere/blackmagic/blob/master/driver/99-blackmagic.rules BMP ?= /dev/ttyBmpGdb diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 8cc7a1420..529bdb8f3 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -407,6 +407,18 @@ function(family_flash_nxplink TARGET) endfunction() +function(family_flash_dfu_util TARGET OPTION) + if (NOT DEFINED DFU_UTIL) + set(DFU_UTIL dfu-util) + endif () + + add_custom_target(${TARGET}-dfu-util + DEPENDS ${TARGET} + COMMAND ${DFU_UTIL} -R -d ${DFU_UTIL_VID_PID} -a 0 -D $/${TARGET}.bin + VERBATIM + ) +endfunction() + #---------------------------------- # Family specific #---------------------------------- diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake new file mode 100644 index 000000000..1837d8450 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/board.cmake @@ -0,0 +1,25 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra6m5) + +set(JLINK_DEVICE R7FA6M5BH) +set(DFU_UTIL_VID_PID 2341:0368) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) + +# Device port default to PORT1 Highspeed +if (NOT DEFINED PORT) +set(PORT 1) +endif() + +# Host port will be the other port +set(HOST_PORT $) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + BOARD_TUD_RHPORT=${PORT} + BOARD_TUH_RHPORT=${HOST_PORT} + # port 0 is fullspeed, port 1 is highspeed + BOARD_TUD_MAX_SPEED=$ + BOARD_TUH_MAX_SPEED=$ + ) +endfunction() diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h new file mode 100644 index 000000000..7841ec8b8 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/board.h @@ -0,0 +1,68 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED +#define LED_STATE_ON 1 + +#define SW1 BSP_IO_PORT_04_PIN_08 // D12 +#define BUTTON_STATE_ACTIVE 0 + +static const ioport_pin_cfg_t board_pin_cfg[] = { + { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, + { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, + + // USB FS + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, + { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, + { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, + + // USB HS + { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, + { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, + { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, + + // ETM Trace + #ifdef TRACE_ETM + { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, + #endif +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk new file mode 100644 index 000000000..6a5c2ffce --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/board.mk @@ -0,0 +1,12 @@ +CPU_CORE = cortex-m33 +MCU_VARIANT = ra6m5 + +LD_FILE = ${BOARD_PATH}/${BOARD}.ld + +# Port 1 is highspeed +PORT ?= 1 + +JLINK_DEVICE = R7FA6M5BH +DFU_UTIL_OPTION = -d 2341:0368 -a 0 + +flash: flash-dfu-util diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..33d381850 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,63 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (2) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) +#else + #define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..bd6a901c3 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..6845183db --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5BH3CFC +#define BSP_MCU_FEATURE_SET ('B') +#define BSP_ROM_SIZE_BYTES (2097152) +#define BSP_RAM_SIZE_BYTES (524288) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..d5428540f --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,387 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA6M5 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h new file mode 100644 index 000000000..0eb5e0516 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h @@ -0,0 +1,37 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ + +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ + +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld new file mode 100644 index 000000000..ba15588e6 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld @@ -0,0 +1,25 @@ +RAM_START = 0x20000000; +RAM_LENGTH = 0x80000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x200000; +DATA_FLASH_START = 0x08000000; +DATA_FLASH_LENGTH = 0x2000; +OPTION_SETTING_START = 0x0100A100; +OPTION_SETTING_LENGTH = 0x100; +OPTION_SETTING_S_START = 0x0100A200; +OPTION_SETTING_S_LENGTH = 0x100; +ID_CODE_START = 0x00000000; +ID_CODE_LENGTH = 0x0; +SDRAM_START = 0x80010000; +SDRAM_LENGTH = 0x0; +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x4000000; +OSPI_DEVICE_0_START = 0x68000000; +OSPI_DEVICE_0_LENGTH = 0x8000000; +OSPI_DEVICE_1_START = 0x70000000; +OSPI_DEVICE_1_LENGTH = 0x10000000; + +/* Board has bootloader */ +FLASH_IMAGE_START = 0x10000; + +INCLUDE fsp.ld diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 2c45b8d71..307e01da8 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -124,4 +124,9 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + + if (DEFINED DFU_UTIL_VID_PID) + family_add_bin_hex(${TARGET}) + family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID}) + endif () endfunction() diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index a5325306d..cf8e5d9e9 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -3,6 +3,8 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk +OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss + # Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk PORT ?= 0 diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/tools/make/toolchain/arm_gcc_rules.mk index f3482b9a8..b76d4aec3 100644 --- a/tools/make/toolchain/arm_gcc_rules.mk +++ b/tools/make/toolchain/arm_gcc_rules.mk @@ -65,9 +65,10 @@ $(BUILD)/obj/%_asm.o: %.S @echo AS $(notdir $@) @$(AS) $(ASFLAGS) -c -o $@ $< +OBJCOPY_BIN_OPTION ?= $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf @echo CREATE $@ - @$(OBJCOPY) -O binary $^ $@ + $(OBJCOPY) -O binary $(OBJCOPY_BIN_OPTION) $^ $@ $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf @echo CREATE $@ -- cgit v1.3.1 From 868d52f3a87d4404b0e93e49781d4190589599b9 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 2 Aug 2023 15:52:06 +0700 Subject: move codespell folder to tools --- .codespell/exclude-file.txt | 0 .codespell/ignore-words.txt | 13 ------------- .codespellrc | 4 ++-- tools/codespell/exclude-file.txt | 0 tools/codespell/ignore-words.txt | 13 +++++++++++++ 5 files changed, 15 insertions(+), 15 deletions(-) delete mode 100644 .codespell/exclude-file.txt delete mode 100644 .codespell/ignore-words.txt create mode 100644 tools/codespell/exclude-file.txt create mode 100644 tools/codespell/ignore-words.txt (limited to 'tools') diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt deleted file mode 100644 index e69de29bb..000000000 diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt deleted file mode 100644 index 2513691cb..000000000 --- a/.codespell/ignore-words.txt +++ /dev/null @@ -1,13 +0,0 @@ -synopsys -sie -tre -thre -hsi -fro -dout -mot -te -attch -endianess -pris -busses diff --git a/.codespellrc b/.codespellrc index dc089903c..1f06e0c5c 100644 --- a/.codespellrc +++ b/.codespellrc @@ -2,8 +2,8 @@ [codespell] # In the event of a false positive, add the problematic word, in all lowercase, to 'ignore-words.txt' (one word per line). # Or copy & paste the whole problematic line to 'exclude-file.txt' -ignore-words = .codespell/ignore-words.txt -exclude-file = .codespell/exclude-file.txt +ignore-words = tools/codespell/ignore-words.txt +exclude-file = tools/codespell/exclude-file.txt check-filenames = check-hidden = count = diff --git a/tools/codespell/exclude-file.txt b/tools/codespell/exclude-file.txt new file mode 100644 index 000000000..e69de29bb diff --git a/tools/codespell/ignore-words.txt b/tools/codespell/ignore-words.txt new file mode 100644 index 000000000..2513691cb --- /dev/null +++ b/tools/codespell/ignore-words.txt @@ -0,0 +1,13 @@ +synopsys +sie +tre +thre +hsi +fro +dout +mot +te +attch +endianess +pris +busses -- cgit v1.3.1 From 088180e3d86cc51472dcd06ae42c613b534bf71c Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 14 Aug 2023 20:58:00 +0700 Subject: add iar support for lpc43, add lpcxpresso43s67 to hil farm --- .github/workflows/build_iar.yml | 81 +------------------------- examples/host/msc_file_explorer/CMakeLists.txt | 12 ++-- hw/bsp/lpc43/family.c | 18 +++++- hw/bsp/lpc43/family.cmake | 75 +++++++++++++----------- test/hil/hil_hfp.json | 7 +++ tools/get_deps.py | 2 +- 6 files changed, 71 insertions(+), 124 deletions(-) (limited to 'tools') diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml index 48fdd6a8a..1eacf90c9 100644 --- a/.github/workflows/build_iar.yml +++ b/.github/workflows/build_iar.yml @@ -32,7 +32,7 @@ jobs: # Alphabetical order # Note: bundle multiple families into a matrix since there is only one self-hosted instance can # run IAR build. Too many matrix can hurt due to setup/teardown overhead. - - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4' + - 'lpc43 stm32f0 stm32f1 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4' steps: - name: Clean workspace run: | @@ -52,82 +52,3 @@ jobs: - name: Test on actual hardware (hardware in the loop) run: | python3 test/hil/hil_test.py hil_hfp.json - -# # Upload binaries for hardware test with self-hosted -# - name: Prepare stm32l412nucleo Artifacts -# if: contains(matrix.family, 'stm32l4') -# working-directory: ${{github.workspace}}/cmake-build/cmake-build-stm32l412nucleo -# run: | -# find device/ -name "*.elf" -exec mv {} ../../ \; -# -# - name: Upload Artifacts for stm32l412nucleo -# if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach' -# uses: actions/upload-artifact@v3 -# with: -# name: stm32l4 -# path: | -# *.elf - - # --------------------------------------- - # Hardware in the loop (HIL) - # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user - # --------------------------------------- -# hw-stm32l412nucleo-test: -# needs: cmake -# runs-on: [self-hosted, Linux, X64, hifiphile] -# -# steps: -# - name: Clean workspace -# run: | -# echo "Cleaning up previous run" -# rm -rf "${{ github.workspace }}" -# mkdir -p "${{ github.workspace }}" -# -# - name: Download stm32l4 Artifacts -# uses: actions/download-artifact@v3 -# with: -# name: stm32l4 -# -# - name: Create flash.sh -# run: | -# echo > flash.sh 'echo halt > flash.jlink' -# echo >> flash.sh 'echo r >> flash.jlink' -# echo >> flash.sh 'echo loadfile $1 >> flash.jlink' -# echo >> flash.sh 'echo r >> flash.jlink' -# echo >> flash.sh 'echo go >> flash.jlink' -# echo >> flash.sh 'echo exit >> flash.jlink' -# echo >> flash.sh 'cmdout=$(JLinkExe -USB 774470029 -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)' -# echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi' -# chmod +x flash.sh -# -# - name: Test cdc_dual_ports -# run: | -# ./flash.sh cdc_dual_ports.elf -# while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done -# test -e /dev/ttyACM1 && echo "ttyACM1 exists" -# test -e /dev/ttyACM2 && echo "ttyACM2 exists" -# -# # Debian does not auto mount usb drive. skip this test for now -# - name: Test cdc_msc -# if: false -# run: | -# ./flash.sh cdc_msc.elf -# readme='/media/pi/TinyUSB MSC/README.TXT' -# while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done -# test -e /dev/ttyACM1 && echo "ttyACM1 exists" -# test -f "$readme" && echo "$readme exists" -# cat "$readme" -# -# - name: Test dfu -# run: | -# ./flash.sh dfu.elf -# while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done -# dfu-util -d cafe -a 0 -U dfu0 -# dfu-util -d cafe -a 1 -U dfu1 -# grep "TinyUSB DFU! - Partition 0" dfu0 -# grep "TinyUSB DFU! - Partition 1" dfu1 -# -# - name: Test dfu_runtime -# run: | -# ./flash.sh dfu_runtime.elf -# while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt index a35a7f0fb..1868b632e 100644 --- a/examples/host/msc_file_explorer/CMakeLists.txt +++ b/examples/host/msc_file_explorer/CMakeLists.txt @@ -22,11 +22,13 @@ target_sources(${PROJECT} PUBLIC ) # Suppress warnings on fatfs -set_source_files_properties( - ${TOP}/lib/fatfs/source/ff.c - PROPERTIES - COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual" -) +if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + set_source_files_properties( + ${TOP}/lib/fatfs/source/ff.c + PROPERTIES + COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual" + ) +endif () # Example include target_include_directories(${PROJECT} PUBLIC diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c index 8d80bf951..d52c1a071 100644 --- a/hw/bsp/lpc43/family.c +++ b/hw/bsp/lpc43/family.c @@ -63,13 +63,25 @@ const uint32_t ExtRateIn = 0; void SystemInit(void) { #ifdef __USE_LPCOPEN - extern void (* const g_pfnVectors[])(void); unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; + +#ifdef __ICCARM__ + extern void *__vector_table; + *pSCB_VTOR = (unsigned int) &__vector_table; + +#elif defined(__ARMCC_VERSION) + extern void *__Vectors; + *pSCB_VTOR = (unsigned int) &__Vectors; + +#else // other compoiler using cr_startup_lpc43xx.c + extern void (* const g_pfnVectors[])(void); *pSCB_VTOR = (unsigned int) g_pfnVectors; +#endif - #if __FPU_USED == 1 +#if __FPU_USED == 1 fpuInit(); - #endif +#endif + #endif /* Setup system level pin muxing */ diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake index e79004686..608fc4ca3 100644 --- a/hw/bsp/lpc43/family.cmake +++ b/hw/bsp/lpc43/family.cmake @@ -17,43 +17,48 @@ set(FAMILY_MCUS LPC43XX CACHE INTERNAL "") #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) - if (NOT TARGET ${BOARD_TARGET}) - add_library(${BOARD_TARGET} STATIC - ${SDK_DIR}/../gcc/cr_startup_lpc43xx.c - ${SDK_DIR}/src/chip_18xx_43xx.c - ${SDK_DIR}/src/clock_18xx_43xx.c - ${SDK_DIR}/src/fpu_init.c - ${SDK_DIR}/src/gpio_18xx_43xx.c - ${SDK_DIR}/src/iap_18xx_43xx.c - ${SDK_DIR}/src/sysinit_18xx_43xx.c - ${SDK_DIR}/src/uart_18xx_43xx.c - ) - target_compile_options(${BOARD_TARGET} PUBLIC - -nostdlib - ) - target_compile_definitions(${BOARD_TARGET} PUBLIC - __USE_LPCOPEN - CORE_M4 + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${SDK_DIR}/../gcc/cr_startup_lpc43xx.c) + set(STARTUP_FILE_IAR ${SDK_DIR}/../iar/iar_startup_lpc18xx43xx.s) + set(LD_FILE_IAR ${SDK_DIR}/../iar/linker/lpc18xx_43xx_ldscript_iflash.icf) + + add_library(${BOARD_TARGET} STATIC + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ${SDK_DIR}/src/chip_18xx_43xx.c + ${SDK_DIR}/src/clock_18xx_43xx.c + ${SDK_DIR}/src/fpu_init.c + ${SDK_DIR}/src/gpio_18xx_43xx.c + ${SDK_DIR}/src/iap_18xx_43xx.c + ${SDK_DIR}/src/sysinit_18xx_43xx.c + ${SDK_DIR}/src/uart_18xx_43xx.c + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + __USE_LPCOPEN + CORE_M4 + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${SDK_DIR}/inc + ${SDK_DIR}/inc/config_43xx + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib) + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + # nanolib + --specs=nosys.specs + --specs=nano.specs ) - target_include_directories(${BOARD_TARGET} PUBLIC - ${SDK_DIR}/inc - ${SDK_DIR}/inc/config_43xx + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" ) - - update_board(${BOARD_TARGET}) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--script=${LD_FILE_GNU}" - # nanolib - --specs=nosys.specs - --specs=nano.specs - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) - endif () endif () endfunction() diff --git a/test/hil/hil_hfp.json b/test/hil/hil_hfp.json index 7912af245..58f550901 100644 --- a/test/hil/hil_hfp.json +++ b/test/hil/hil_hfp.json @@ -13,6 +13,13 @@ "debugger": "jlink", "debugger_sn": "770935966", "cpu": "STM32F746NG" + }, + { + "name": "lpcxpresso43s67", + "uid": "08F000044528BAAA8D858F58C50700F5", + "debugger": "jlink", + "debugger_sn": "728973776", + "cpu": "LPC43S67_M4" } ] } diff --git a/tools/get_deps.py b/tools/get_deps.py index 82f756f64..1fac291a3 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -48,7 +48,7 @@ deps_optional = { '2204191ec76283371419fbcec207da02e1bc22fa', 'nuc'], 'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git', - '43c45c85405a5dd114fff0ea95cca62837740c13', + '84e0bd3e43910aaf71eefd62075cf57495418312', 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'], 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', '950819b7de9b32f92c3edf396bc5ffb8d66e7009', -- cgit v1.3.1