u-boot.git, branch v2009.01-rc2 Unnamed repository; edit this file 'description' to name the repository. Prepare 2009.01-rc2 2009-01-14T22:26:05+00:00 Wolfgang Denk wd@denx.de 2009-01-14T22:26:05+00:00 0e3ece33801e377be67ffa29f083421ad820f28b Update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de> 
Update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
cpu/mpc824x/Makefile: fix warning with parallel builds 2009-01-14T21:35:30+00:00 Wolfgang Denk wd@denx.de 2009-01-14T21:35:30+00:00 e92c9a860e44c14513c8909ce4299e253a775eeb Parallel builds would occasionally issue this build warning: ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists Use "ln -sf" as quick work around for the issue. Signed-off-by: Wolfgang Denk <wd@denx.de> 
Parallel builds would occasionally issue this build warning:

    ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists

Use "ln -sf" as quick work around for the issue.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Merge branch 'master' of /home/wd/git/u-boot/custodians 2009-01-13T23:27:06+00:00 Wolfgang Denk wd@denx.de 2009-01-13T23:27:06+00:00 5f01ea63a6c263767f548b4f61880b08f7850ffc 






Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
2009-01-13T23:26:48+00:00

Wolfgang Denk
wd@denx.de

2009-01-13T23:26:48+00:00

bae6d5e4122882fdeeefdd0358ec592c01abe138












Some changes of TLB entry setting for MPC8572DS
2009-01-13T22:58:46+00:00

Haiying Wang
Haiying.Wang@freescale.com

2009-01-13T21:29:28+00:00

b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6

- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>





- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>







Change DDR tlb start entry to CONFIG param for 85xx
2009-01-13T22:47:07+00:00

Haiying Wang
Haiying.Wang@freescale.com

2009-01-13T21:29:22+00:00

950264317eb9594b2b5ee2fb65206200a1c6007a

So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>





So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>







Change PCIE1&2 deciide logic on MPC8544DS board more readable
2009-01-13T22:32:53+00:00

Roy Zang
tie-fei.zang@freescale.com

2009-01-09T08:02:35+00:00

6d3a10f73ece7ffb736890c10e023222612a4aa0

The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>





The IO port selection for MPC8544DS board:
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
 PCIE2		0x4, 0x5, 0x6, 0x7
 PCIE3		0x6, 0x7
 This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>







PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit
2009-01-13T22:32:52+00:00

Roy Zang
tie-fei.zang@freescale.com

2009-01-09T08:01:52+00:00

028e116811d28a031660f1ad9e20ac1293b3c5c7

PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>





PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>







Fix IO port selection issue on MPC8544DS and MPC8572DS boards
2009-01-13T22:32:52+00:00

Roy Zang
tie-fei.zang@freescale.com

2009-01-09T08:00:55+00:00

9afc2ef0307aecf52482df67c31b75d5f9e66b47

The IO port selection is not correct on MPC8572DS and MPC8544DS board.
 This patch fixes this issue.
 For MPC8572
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x7, 0xb, 0xc, 0xf
 PCIE2		0x3, 0x7
 PCIE3		0x7

For MPC8544
Port			cfg_io_ports
PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2		0x4, 0x5, 0x6, 0x7
PCIE3		0x6, 0x7
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>





The IO port selection is not correct on MPC8572DS and MPC8544DS board.
 This patch fixes this issue.
 For MPC8572
 Port			cfg_io_ports
 PCIE1		0x2, 0x3, 0x7, 0xb, 0xc, 0xf
 PCIE2		0x3, 0x7
 PCIE3		0x7

For MPC8544
Port			cfg_io_ports
PCIE1		0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2		0x4, 0x5, 0x6, 0x7
PCIE3		0x6, 0x7
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>







mpc8610hpcd: Fix PCI mapping concepts
2009-01-13T21:27:46+00:00

Becky Bruce
beckyb@kernel.crashing.org

2008-12-04T04:36:44+00:00

3e3fffe3baf3befde287fec1fcbfe55052fb8946

Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>





Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately.  This makes the code easier to read
and understand, and facilitates mapping changes going forward.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>