Signed-off-by: Wolfgang Denk <wd@denx.de>

As this seems unclear, document how the flow of setting up
the MAC address is correct.

Signed-off-by: Heiko Schocher <hs@denx.de>

Text changed slightly, adding input from Mike Frysinger.

Signed-off-by: Wolfgang Denk <wd@denx.de>

Only fill the device enetaddr with the contents of the eeprom,
do not program it in MAC address registers

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Ben Warren <biggerbadderben@gmail.com>

The ramdisk sections in doc/uImage.FIT/multi.its lack
load address and entry point properties. Using examples
from this file will result in unbootable image, u-boot
will issue the following error messages:

Can't get ramdisk subimage load address!
Ramdisk image is corrupt or invalid

This patch adds missing properties to ramdisk sections.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>

$ ./MAKEALL suen3
jffs2_1pass.c: In function 'get_fl_mem':
jffs2_1pass.c:399: warning: unused variable 'id'
jffs2_1pass.c: In function 'get_node_mem':
jffs2_1pass.c:423: warning: unused variable 'id'

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tom <Tom.Rix@windriver.com>

After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly.  This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.

On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way.  If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation.  The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).

Currently we are limited to power of two sized DDR since we only use a
single bat.  If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

This patch fixes a problem introduced with patch eb5eb2b0
[ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C
base address to the "i2c" pointer inside of the controller loop.
Otherwise controller 0 is initialized multiple times instead of
initializing each I2C controller sequentially.

Tested on Katmai.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>