u-boot.git, branch v2015.04-rc1

Prepare v2015.04-rc1

2015-02-02T17:39:29+00:00

Signed-off-by: Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-ti

2015-02-02T17:37:34+00:00

Merge branch 'master' of git://git.denx.de/u-boot-blackfin

2015-02-02T16:51:58+00:00

Merge branch 'master' of git://git.denx.de/u-boot-sunxi

2015-02-02T15:11:44+00:00

sunxi: mmc: Add 'sunxi_' prefix to the static functions

2015-02-02T13:04:28+00:00

This results in a much more readable callgraph, because now they
can't be confused with the function having exactly the same name
in the generic mmc code.

Signed-off-by: Siarhei Siamashka 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

sunxi: dram: Support more sun[457]i dram parameters in Kconfig

2015-02-02T13:04:23+00:00

This patch allows to configure all the important DRAM parameters in Kconfig.

Signed-off-by: Siarhei Siamashka 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

sunxi: dram: Optionally use standard JEDEC timings for sun[457]i

2015-02-02T13:04:15+00:00

In addition to the current Android magic settings, allow to optionally use
DDR3 timing parameters, which are tailored for different clock frequencies
and JEDEC speed bins. This should improve reliability and performance.

Adding '+S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y' to the board defconfig
allows to use timings, which are calculated for the DDR3-1066F speed bin.
A lot of DDR3 chips, which are used in real Allwinner based devices,
support DDR3-1066F speed bin timings.

And adding '+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y' should work
with any DDR3 chips, because this targets the slowest JEDEC speed bins.

The vendor magic values are still used by default for DRAM, but board
maintainers now have more flexibility in DRAM timings selection.

Signed-off-by: Siarhei Siamashka 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

sunxi: video: Force h/vsync active high when using ext. vga dac on some boards

2015-02-02T12:57:16+00:00

On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used.

The problem seems to be specific to the OLinuxIno A13 (normal & micro)
boards. I've just looked up the schematics and they use an opendrain driver
for the vga sync lines, and with sync pulses it is the logical high->low
edge of the pulse which counts for the timing, which with an active low
sync is being driven by the pull-up, and that simply seems to not drive
it hard enough to get a stable image.

So force v and hsync active high on these boards. independent of what the
modeline says. This fixes the unstable image.

Signed-off-by: Hans de Goede 
Acked-by: Ian Campbell

sunxi: Add Inet 86VS support

2015-02-02T12:57:16+00:00

Signed-off-by: Michal Suchanek 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede

sunxi: TZX-Q8-713B7 support

2015-02-02T12:57:16+00:00

Signed-off-by: Paul Kocialkowski 
Acked-by: Hans de Goede 
Signed-off-by: Hans de Goede