u-boot.git, branch v2015.10-rc2

Prepare v2015.10-rc2

2015-08-17T21:32:23+00:00

Signed-off-by: Tom Rini

Merge git://git.denx.de/u-boot-marvell

2015-08-17T21:19:40+00:00

Revert "Align global_data to a 16-byte boundary"

2015-08-17T21:19:18+00:00

This causes widespread breakage due to the operation of the low-level code
in crt0.S and cro0_64.S for ARM at least.

The fix is not complicated but it seems safer to revert this for now.

This reverts commit 2afddae07523f23f77acd066ad1719f53d289f98.
Signed-off-by: Simon Glass

arm: mvebu: db-88f6820-gp: Enable PCI support

2015-08-17T16:49:52+00:00

This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.

Signed-off-by: Stefan Roese 
Cc: Anton Schubert 
Cc: Luka Perkov 
Cc: Dirk Eibach

arm: mvebu: db-mv784mp-gp: Enable PCI support

2015-08-17T16:49:47+00:00

This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.

Signed-off-by: Stefan Roese 
Cc: Anton Schubert 
Cc: Luka Perkov

pci: mvebu: Add PCIe driver

2015-08-17T16:49:43+00:00

This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.

Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.

Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.

This port was done in cooperation with Anton Schubert.

Signed-off-by: Anton Schubert 
Signed-off-by: Stefan Roese 
Cc: Luka Perkov 
Cc: Dirk Eibach

arm: mvebu: Add complete SDRAM ECC scrubbing

2015-08-17T16:49:33+00:00

This patch introduces the SDRAM scrubbing for ECC enabled board
to fill/initialize the ECC bytes. This is done via the XOR engine
to speed up the process. The scrubbing is a 2-stage process:

1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot
2) U-Boot scrubs the remaining SDRAM area(s)

Signed-off-by: Stefan Roese 
Cc: Luka Perkov

arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize()

2015-08-17T16:49:29+00:00

Rework these functions so that dram_init_banksize() does not call
dram_init() again. It only needs to set the banksize values in the
bdinfo struct.

Make sure to also clip the size of the last bank if it exceeds the
maximum allowed value of 3 GiB (0xc000.0000). Otherwise other
address windows (e.g. PCIe) will overlap with this memory window.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov

arm: mvebu: Move CONFIG_SYS_TEXT_BASE to an address < 16 MiB

2015-08-17T16:49:25+00:00

This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada
XP / 38x boards in mainline U-Boot. This is done in preparation for
the ECC SDRAM scrubbing that needs to be done in the main U-Boot.
The SPL (previously bin_hdr) has already scrubbed the area:
  0x0000.0000 - 0x0100.0000

In this area this main U-Boot needs to get loaded. The main U-Boot
then can scrub the remaining SDRAM area while running from this
location.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov

arm: mvebu: Display ECC enabled / disabled upon bootup

2015-08-17T16:49:19+00:00

This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM
bootup text. Making it easier for board with SPD DIMM's to see,
if ECC is enabled or not.

Signed-off-by: Stefan Roese 
Cc: Luka Perkov