u-boot.git, branch v2017.01-rc1

Prepare v2017.01-rc1

2016-12-05T23:36:23+00:00

Signed-off-by: Tom Rini

Merge git://git.denx.de/u-boot-fsl-qoriq

2016-12-05T22:00:23+00:00

armv8: QSPI: Add AHB bus 16MB+ size support

2016-12-05T16:32:43+00:00

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao 
Reviewed-by: York Sun

fsl/usb: enable the errata-a005697 for ls1012a

2016-12-05T16:31:45+00:00

Enable the errata-a005697 for ls1012a

Signed-off-by: Changming Huang 
Reviewed-by: York Sun

ls1021a: QSPI: update the node for QSPI support

2016-12-05T16:31:45+00:00

Add the name for register space and memory space.
<0x1550000 0x10000 > is the QSPI register space.
<0x40000000 0x4000000> is the QSPI memory space.

Signed-off-by: Yuan Yao 
Reviewed-by: York Sun

armv8: ls2080a: Add serdes1 protocol 0x3b support

2016-12-05T16:31:45+00:00

Signed-off-by: Priyanka Jain 
Reviewed-by: York Sun

fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum

2016-12-05T16:31:45+00:00

- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu 
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun

fsl/ddr: Fix compiling warning

2016-12-05T16:31:45+00:00

Fix following warning in case multiple erratum macro was not defined.
warning: unused variable 'tmp'
warning: unused variable 'ddr_freq'

Signed-off-by: Shengzhou Liu 
Reviewed-by: York Sun

travis-ci: Build mvebu boards (arm & aarch64) in separate job

2016-12-05T16:04:42+00:00

Its easier to watch the output of the build process when the platforms
specific boards are grouped in a separate job. This patch adds a job
for all mvebu boards (arm and aarch64).

Signed-off-by: Stefan Roese 
Cc: Tom Rini 
Reviewed-by: Tom Rini

davinci: omapl138_lcdk: increase PLL0 frequency

2016-12-05T16:04:42+00:00

The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.

Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.

Signed-off-by: Bartosz Golaszewski 
Reviewed-by: Tom Rini