u-boot.git, branch v2021.07-rc2 Unnamed repository; edit this file 'description' to name the repository. Prepare v2021.07-rc2 2021-05-10T21:03:22+00:00 Tom Rini trini@konsulko.com 2021-05-10T21:03:22+00:00 b107761b817c421fb8eadee739656e1db38686c3 Signed-off-by: Tom Rini <trini@konsulko.com> 
Signed-off-by: Tom Rini <trini@konsulko.com>
Merge https://source.denx.de/u-boot/custodians/u-boot-x86 2021-05-10T12:02:00+00:00 Tom Rini trini@konsulko.com 2021-05-10T12:02:00+00:00 3ee71c57295dd64295b2ac1b2cb53918e803990f - x86: correct regwidth prompt in cbsysinfo - virtio: convert README.virtio to reST 
- x86: correct regwidth prompt in cbsysinfo
- virtio: convert README.virtio to reST
MAINTAINERS: Add an entry for VirtIO 2021-05-10T05:56:12+00:00 Bin Meng bmeng.cn@gmail.com 2021-04-29T09:40:08+00:00 200fdd3bff569369f9264e648ddc9c02547b6186 This was missed when VirtIO support was initially brought to U-Boot back in 2018. Add an entry for it and list myself as the maintainer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 
This was missed when VirtIO support was initially brought to U-Boot
back in 2018. Add an entry for it and list myself as the maintainer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
doc: develop: Convert README.virtio to reST 2021-05-10T05:56:12+00:00 Bin Meng bmeng.cn@gmail.com 2021-04-29T09:40:07+00:00 9cea9abbe4f3c2ccc69e621d39a19338815e9827 This converts the existing README.virtio to reST, and puts it under the develop/driver-model/ directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 
This converts the existing README.virtio to reST, and puts it under
the develop/driver-model/ directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
x86: Correct regwidth prompt in cbsysinfo 2021-05-10T05:56:12+00:00 Simon Glass sjg@chromium.org 2021-04-23T22:04:57+00:00 b8db1c138861b7d35d2206af6a555bab05a096a0 This should be 'regwidth', not 'baud'. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This should be 'regwidth', not 'baud'. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-05-07T12:57:32+00:00 Tom Rini trini@konsulko.com 2021-05-07T12:57:32+00:00 07b53103b7a6c228ae8b74ae720b9c5d219ee7fd 






Merge branch '2021-05-06-misc-updates'
2021-05-06T15:00:07+00:00

Tom Rini
trini@konsulko.com

2021-05-06T15:00:07+00:00

1b8ad819cead7020d35f6251ef0cf3f393c61e51

- Allow for boards to update bootargs before booting the OS (helpful in
  some forms of secure boot).
- Enhance GPT write support.
- gpio-sysinfo updates
- Allow env to be appended from dtb





- Allow for boards to update bootargs before booting the OS (helpful in
  some forms of secure boot).
- Enhance GPT write support.
- gpio-sysinfo updates
- Allow env to be appended from dtb







cmd/exception: support ebreak exception on RISC-V
2021-05-05T08:13:12+00:00

Heinrich Schuchardt
xypron.glpk@gmx.de

2021-04-09T10:48:14+00:00

91e4b7516d84cefab7324765b3c8d6a909185ce2

The ebreak instruction should generate a breakpoint exception.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>





The ebreak instruction should generate a breakpoint exception.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>







atcspi200: Add timeout mechanism in spi_xfer()
2021-05-05T08:12:14+00:00

Dylan Jhong
dylan@andestech.com

2021-04-01T08:48:51+00:00

1412b8d48a920f1a4f5eac256814d25c320fb9b6

Adding timeout mechanism to avoid spi driver from stucking
in the while loop in __atcspi200_spi_xfer().

Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>





Adding timeout mechanism to avoid spi driver from stucking
in the while loop in __atcspi200_spi_xfer().

Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>







riscv: cpu: fu740: clear feature disable CSR
2021-05-05T08:11:27+00:00

Green Wan
green.wan@sifive.com

2021-05-03T06:23:05+00:00

bc8bbb77f74f21582b3bfd790334397757f88575

Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>





Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>