u-boot.git, branch v2021.10-rc1 Unnamed repository; edit this file 'description' to name the repository. Prepare v2021.10-rc1 2021-07-27T00:57:18+00:00 Tom Rini trini@konsulko.com 2021-07-27T00:57:18+00:00 b70b9b07463db2f6937c7ea6d7fb5122feb7ba1b Signed-off-by: Tom Rini <trini@konsulko.com> 
Signed-off-by: Tom Rini <trini@konsulko.com>
Merge tag 'xilinx-for-v2021.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze 2021-07-26T16:09:32+00:00 Tom Rini trini@konsulko.com 2021-07-26T16:09:32+00:00 e013b727010699c085b329050369871a0ae433b2 Xilinx changes for v2021.10-rc1 xilinx: - Use default ENVL_NOWHERE configuration - Add support for handling compressed kernels zynqmp: - SPL malloc size extension - USB2.0 for zc1751 dc2 - Fix USB3.0 nodes - Handle lpd_lsbus clock - Cleanup macros around SYSRESET versal: - Remove PBSIZE macro zynq_sdhci: - Tap delay fixups net: - Add support for MRMAC 
Xilinx changes for v2021.10-rc1

xilinx:
- Use default ENVL_NOWHERE configuration
- Add support for handling compressed kernels

zynqmp:
- SPL malloc size extension
- USB2.0 for zc1751 dc2
- Fix USB3.0 nodes
- Handle lpd_lsbus clock
- Cleanup macros around SYSRESET

versal:
- Remove PBSIZE macro

zynq_sdhci:
- Tap delay fixups

net:
- Add support for MRMAC
arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB node 2021-07-26T07:26:41+00:00 Manish Narani manish.narani@xilinx.com 2021-07-14T12:17:19+00:00 15ca9ebb074e9eca5a8264c93f5678df240fa54d Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This PHY initialization should be handled from Xilinx USB core as the prerequisite register configurations are done here only. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here
the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This
PHY initialization should be handled from Xilinx USB core as the
prerequisite register configurations are done here only.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
xilinx: Define kernel_comp_addr_r,kernel_comp_size env variables 2021-07-26T07:18:45+00:00 Raju Kumar Pothuraju raju.kumar-pothuraju@xilinx.com 2021-07-12T14:49:04+00:00 3965d13f933d5aa670f833eb9584f119e4a11d62 Add kernel_comp_addr_r, kernel_comp_size env variables for zynqmp and versal to be able to use the compressed kernel Image(.gz,.bz2,.lzma,.lzo) using booti command. Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Add kernel_comp_addr_r, kernel_comp_size env variables for zynqmp and
versal to be able to use the compressed kernel Image(.gz,.bz2,.lzma,.lzo)
using booti command.

Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: versal: Drop default definitions of CONFIG_SYS_PBSIZE 2021-07-26T07:18:45+00:00 Michal Simek michal.simek@xilinx.com 2021-07-14T07:07:04+00:00 9ca09621760453dc452244498fdbcd52e3e2f71d It is default value which had been converted by commit 432e39806805 ("include/configs: drop default definitions of CONFIG_SYS_PBSIZE"). That's why also remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
It is default value which had been converted by commit 432e39806805
("include/configs: drop default definitions of CONFIG_SYS_PBSIZE"). That's
why also remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Enable reset and poweroff via sysreset framework 2021-07-26T07:18:45+00:00 Michal Simek michal.simek@xilinx.com 2021-07-13T14:49:04+00:00 a9558b45a4ba3c4ceeb084532209eab553a2327e reset and poweroff are called via hooks in psci driver which is going around sysreset framework that's why enable sysreset drivers and do reset and poweroff via this framework. Using this flow will allow us to call SYSTEM_WARM_RESET based on psci 1.1 spec which can be calles with reset -w command. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
reset and poweroff are called via hooks in psci driver which is going
around sysreset framework that's why enable sysreset drivers and do reset
and poweroff via this framework. Using this flow will allow us to call
SYSTEM_WARM_RESET based on psci 1.1 spec which can be calles with reset -w
command.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Do not define do_reset() if sysreset is enabled 2021-07-26T07:18:45+00:00 Michal Simek michal.simek@xilinx.com 2021-07-13T14:39:26+00:00 f1bc214b0024b8d9585d83a42999a40980728303 The SPL can also be compiled with sysreset drivers just fine, so update the condition to cater for that option. The same change was done by commit efa1a62ad2dd ("ARM: imx8m: Do not define do_reset() if sysreset is enabled"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
The SPL can also be compiled with sysreset drivers just fine, so
update the condition to cater for that option.
The same change was done by commit efa1a62ad2dd ("ARM: imx8m: Do not define
do_reset() if sysreset is enabled").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
psci: Do not define do_poweroff() if CONFIG_SYSRESET_CMD_POWEROFF is enabled 2021-07-26T07:18:45+00:00 Michal Simek michal.simek@xilinx.com 2021-07-13T14:53:46+00:00 bfc05d7e2af334c5907c38a94eddb18b5e92faaf CONFIG_SYSRESET_CMD_POWEROFF defines do_poweroff() in sysreset-uclass.c that's why don't define it twice when both CONFIG_SYSRESET_CMD_POWEROFF and CONFIG_CMD_POWEROFF are enabled. CONFIG_SYSRESET_CMD_POWEROFF depends on CONFIG_CMD_POWEROFF. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
CONFIG_SYSRESET_CMD_POWEROFF defines do_poweroff() in sysreset-uclass.c
that's why don't define it twice when both CONFIG_SYSRESET_CMD_POWEROFF and
CONFIG_CMD_POWEROFF are enabled. CONFIG_SYSRESET_CMD_POWEROFF depends on
CONFIG_CMD_POWEROFF.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
xilinx: versal: Enable Xilinx AXI MRMAC 2021-07-26T07:18:45+00:00 Ashok Reddy Soma ashok.reddy.soma@xilinx.com 2021-07-02T10:40:35+00:00 bc579291e2292c80e6018826fa5eefa453756b17 Enable Xilinx AXI MRMAC for Versal platforms. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Enable Xilinx AXI MRMAC for Versal platforms.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xilinx: axi_mrmac: Add MRMAC driver 2021-07-26T07:18:45+00:00 Ashok Reddy Soma ashok.reddy.soma@xilinx.com 2021-07-02T10:40:34+00:00 258ce79cfce4b17b4afe867353c0365cc3c26b46 Add support for xilinx multirate(MRMAC) ethernet driver. This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC. Added support for 4 ports of MRMAC for speeds 10G and 25G. MCDMA supports upto 16 channels but in this driver we have setup only one channel which is enough. Tested 10G and 25G on all 4 ports. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Add support for xilinx multirate(MRMAC) ethernet driver.
This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
Added support for 4 ports of MRMAC for speeds 10G and 25G.
MCDMA supports upto 16 channels but in this driver we have setup only
one channel which is enough.

Tested 10G and 25G on all 4 ports.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>