Signed-off-by: Tom Rini <trini@konsulko.com>

Signed-off-by: Tom Rini <trini@konsulko.com>

This reverts commit 380ddb473c6bdf87e66c0fb93e256d1e233c6f5b.

Signed-off-by: Tom Rini <trini@konsulko.com>

With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version
v1.7.2-35-g52f07dcca47c") we now require the correct, 8 byte alignment
of a device tree in order to work with it ourselves. This has exposed a
number of issues. In the case of using arch/arm/cpu/u-boot-spl.lds for
an xPL phase and having the BSS be overlayed with the dynamic
relocations sections (here, .rel.dyn) we had missed adding the comment
about our asm memset requirements. Then, when adjusting ALIGN statements
we later missed this one. In turn, when we use objcopy to create our
binary image we end up in the situation where

where the BSS must start out 8 byte aligned as
well as end 8 byte aligned because for appended device tree the
requirement is that the whole BSS (which we add as padding to the
binary) must be 8 byte aligned. Otherwise we end up with the situation
where __bss_end (where we look for the device tree at run time) is
aligned but the size of the BSS we add

Fixes: 7828a1eeb2a1 ("arm: remove redundant section alignments")
Fixes: 52caad0d14a3 ("ARM: Align image end to 8 bytes to fit DT alignment")
Reported-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Marek Vasut <marek.vasut@mailbox.org>

Some improvements for some boards' DRAM setup, to allow boards with
"odd" DRAM sizes (1.5GB or 3GB), and to support the T113-s4 with double
the co-packaged DRAM. Support for a new board (X96Q TV box), and a fix
for the DT name prefix. Also we support the new AXP318W PMIC, which is
used on new boards with the A733 SoC. There are some preliminary support
patches for this SoC, but they are not quite ready yet - though maybe I
push some uncontroversial ones a bit later still.

The X96Q is a set-top box with an H313 SoC, AXP305 PMIC, 1 or 2 GiB RAM,
8 or 16 GiB eMMC flash, 2x USB A, Micro-SD, HDMI, Ethernet, audio/video
output, and infrared input.

  https://x96mini.com/products/x96q-tv-box-android-10-set-top-box

This commit adds a defconfig and some documentation. The devicetree is
already in dts/upstream.

The CONFIG_DRAM_SUNXI_* settings are chosen such that the register
values in the DRAM PHY's MMIO space are as close as possible to those
observed when booting with the preinstalled vendor U-Boot. The DRAM
clock frequency of 600 MHz was reported in the vendor U-Boot's output.

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Add the descriptions for the DC/DC regulators of the AXP318W, and enable
it when CONFIG_AXP318W_POWER is enabled.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

The PMIC is also known as AXP819 in vendor pmu code

For DCDC6, 8, 9, the underlying hardware support more than two levels
voltage step tuning, but for now only first two levels are implemented
in this driver, hence highest voltage will be limited at seccond level.
It actual meets board requirement in current design, and we've verified
it in Radxa Cubie A7A board.

Following are detail explanation of voltage tuning stpes for those DCDCs:

DCDC | voltage range  | units | steps | implemented
 6   | 0.5   -  1.2   | 10 mV | 71    | Y
 .   | 1.22  -  1.54  | 20 mV | 17    | Y
 .   | 1.8   -  2.4   | 20 mV | 31    | N
 .   | 2.44  -  2.76  | 40 mV | 9     | N
 --------------------------------------------------
 8/9 | 0.5   -  1.2   | 10 mV | 71    | Y
 .   | 1.22  -  1.84  | 20 mV | 32    | Y
 .   | 1.9   -  3.4   | 100mV | 16    | N

Signed-off-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

When CONFIG_OF_UPSTREAM is enabled, the device tree name provided by SPL
already includes the vendor directory (e.g., "allwinner/board-name").

The existing logic in misc_init_r() unconditionally prepends "allwinner/"
for ARM64 builds, resulting in an incorrect path like
"allwinner/allwinner/board-name.dtb".

This patch modifies the logic to only prepend the vendor prefix if
CONFIG_OF_UPSTREAM is NOT enabled. This ensures compatibility with both
legacy builds and the new upstream devicetree structure.

Signed-off-by: Bohdan Chubuk <chbgdn@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Some boards feature an "odd" DRAM size, where the total RAM is 1.5GB or
3GB. Our existing DRAM size detection routines can only detect power-of-2
sized configuration, and on those boards the DRAM size is overestimated,
so this typically breaks the boot quite early.

There doesn't seem to be an easy explicit way to detect those odd-sized
chips, but we can test whether the later part of the memory behaves like
memory, by verifying that a written pattern can be read back.
Experiments show that there is no aliasing effect here, as all locations
in the unimplemented range always return some fixed pattern, and cannot
be changed.

Also so far all those boards use a factor of 3 of some lower power-of-2
number, or 3/4th of some higher number. The size detection routine
discovers the higher number, so we can check for some memory cells beyond
75% of the detected size to be legit.

Add a routine the inverts all bits at a given location in memory, and
reads that back to prove that the new value was stored.
Then test the memory cell at exactly 3/4th of the detected size, and cap
the size of the memory to 75% when this test fails. For good measure
also make sure that memory just below the assumed memory end really
works.

This enables boards which ship with such odd memory sizes.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>