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<title>u-boot.git/Makefile, branch v2019.07-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/Makefile?h=v2019.07-rc3</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/Makefile?h=v2019.07-rc3'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2019-05-27T18:29:39Z</updated>
<entry>
<title>Prepare v2019.07-rc3</title>
<updated>2019-05-27T18:29:39Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-27T18:29:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7c7919cd07b34a784ab321ab7578106c9e9bd753'/>
<id>urn:sha1:7c7919cd07b34a784ab321ab7578106c9e9bd753</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ARM: rmobile: Add recovery SPL for R-Car Gen3</title>
<updated>2019-05-21T20:15:31Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-10-03T10:44:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5602330df0306a44d78c1ba67ab7e15aa6f3fc41'/>
<id>urn:sha1:5602330df0306a44d78c1ba67ab7e15aa6f3fc41</id>
<content type='text'>
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.

The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.

However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>Revert "Makefile: Prioritize external dtb if defined"</title>
<updated>2019-05-19T22:09:35Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-19T22:09:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=748198cb8d32d41bc35e6f492bac9948f339bece'/>
<id>urn:sha1:748198cb8d32d41bc35e6f492bac9948f339bece</id>
<content type='text'>
This is causing unexpected size growth in the normal case and is likely
to have been mis-applied by myself.

This reverts commit 3eaf6dcd9362b56e3217559401287dd8fa35b5b2.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Makefile: Prioritize external dtb if defined</title>
<updated>2019-05-18T16:31:58Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2019-03-25T14:55:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3eaf6dcd9362b56e3217559401287dd8fa35b5b2'/>
<id>urn:sha1:3eaf6dcd9362b56e3217559401287dd8fa35b5b2</id>
<content type='text'>
Prioritize external dtb if its passed via EXT_DTB
than the dtb that was built in the tree. With this
patch it appends the specified external dtb to
the u-boot image.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Prepare v2019.07-rc2</title>
<updated>2019-05-15T19:58:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-15T19:58:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5b4b680cfe29a67171ccbe439c66374cb31faca3'/>
<id>urn:sha1:5b4b680cfe29a67171ccbe439c66374cb31faca3</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Set time and umask on fit-dtb.blob to ensure reproducibile builds.</title>
<updated>2019-05-10T00:22:04Z</updated>
<author>
<name>Vagrant Cascadian</name>
<email>vagrant@reproducible-builds.org</email>
</author>
<published>2019-05-02T18:14:12Z</published>
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<id>urn:sha1:878e2a50b50199cb06ee28df53151e396a29d838</id>
<content type='text'>
Support for compressed fit-dtb.blob was added in:

  commit 95f4bbd581cf ("lib: fdt: Allow LZO and GZIP DT compression in
  U-Boot")

When building compressed (lzop, gzip) fit-dtb.blob images, the
compression tool may embed the time or umask in the image.

Work around this by manually setting the time of the source file using
SOURCE_DATE_EPOCH and a hard-coded 0600 umask.

With gzip, this could be accomplished by using -n/--no-name, but lzop
has no current workaround:

  https://bugs.debian.org/896520

This is essentially the same fix applied to multi-dtb fit SPL images in:

  commit 8664ab7debab ("Set time and umask on multi-dtb fit images to
  ensure reproducibile builds.")

Signed-off-by: Vagrant Cascadian &lt;vagrant@reproducible-builds.org&gt;
</content>
</entry>
<entry>
<title>Remove fit-dtb.blob* in clean target.</title>
<updated>2019-05-10T00:22:04Z</updated>
<author>
<name>Vagrant Cascadian</name>
<email>vagrant@reproducible-builds.org</email>
</author>
<published>2019-05-02T18:14:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3ee8d913283f724dbf9401088decee806246b6db'/>
<id>urn:sha1:3ee8d913283f724dbf9401088decee806246b6db</id>
<content type='text'>
Support for compressed fit-dtb.blob was added in:

  commit 95f4bbd581cf ("lib: fdt: Allow LZO and GZIP DT compression in
  U-Boot")

Adjust Makefile to also clean compressed blobs.

Signed-off-by: Vagrant Cascadian &lt;vagrant@reproducible-builds.org&gt;
</content>
</entry>
<entry>
<title>dm: MIGRATION: Add migration plan for WDT (DM watchdog support)</title>
<updated>2019-05-09T23:52:55Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2019-05-09T08:16:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=80af0fed237aca17e1d32625a77426dbd49cf47f'/>
<id>urn:sha1:80af0fed237aca17e1d32625a77426dbd49cf47f</id>
<content type='text'>
As much of the watchdog system has been migrated to DM now, formalize a
deadline for migration.

Please note that the old CONFIG_HW_WATCHDOG macro should be removed
completely at some point.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>x86: Allow 16-bit init to be in TPL</title>
<updated>2019-05-08T05:02:13Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-04-26T03:58:53Z</published>
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<id>urn:sha1:d68574a72da5376784cbf3a553d82c6acfcd6824</id>
<content type='text'>
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>ddr: altera: Compile ALTERA SDRAM in SPL only</title>
<updated>2019-05-06T10:44:17Z</updated>
<author>
<name>Ley Foon Tan</name>
<email>ley.foon.tan@intel.com</email>
</author>
<published>2019-05-06T01:55:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5918afda9d43106dd540c04bb05b7718e5f82171'/>
<id>urn:sha1:5918afda9d43106dd540c04bb05b7718e5f82171</id>
<content type='text'>
Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.

Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
</entry>
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