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<title>u-boot.git/README, branch v1.3.3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Fix some typos</title>
<updated>2008-05-09T18:53:52+00:00</updated>
<author>
<name>Adrian Filipi</name>
<email>adrian.filipi@eurotech.com</email>
</author>
<published>2008-05-06T20:46:37+00:00</published>
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This patch fixes three typos.
The first is a repetition of CONFIG_CMD_BSP.
The second makes the #endif comment match its #if.
The third is a spelling error.

Signed-off-by: Adrian Filipi &lt;adrian.filipi@eurotech.com&gt;
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<pre>
This patch fixes three typos.
The first is a repetition of CONFIG_CMD_BSP.
The second makes the #endif comment match its #if.
The third is a spelling error.

Signed-off-by: Adrian Filipi &lt;adrian.filipi@eurotech.com&gt;
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</entry>
<entry>
<title>net: make ARP timeout configurable</title>
<updated>2008-04-29T05:23:21+00:00</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>lg@denx.de</email>
</author>
<published>2008-04-03T15:04:19+00:00</published>
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Currently the timeout waiting for an ARP reply is hard set to 5 seconds.
On i.MX31ADS due to a hardware "strangeness" up to four first IP packets
to the boards get lost, which typically are ARP replies. By configuring
the timeout to a lower value we significantly improve the first network
transfer time on this board. The timeout is specified in milliseconds,
later internally it is converted to deciseconds, because it has to be
converted to hardware ticks, and CFG_HZ ranges from 900 to 27000000 on
different boards.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Currently the timeout waiting for an ARP reply is hard set to 5 seconds.
On i.MX31ADS due to a hardware "strangeness" up to four first IP packets
to the boards get lost, which typically are ARP replies. By configuring
the timeout to a lower value we significantly improve the first network
transfer time on this board. The timeout is specified in milliseconds,
later internally it is converted to deciseconds, because it has to be
converted to hardware ticks, and CFG_HZ ranges from 900 to 27000000 on
different boards.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>RTC driver for MC13783</title>
<updated>2008-04-18T07:43:50+00:00</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>lg@denx.de</email>
</author>
<published>2008-04-15T12:15:30+00:00</published>
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MC13783 is a multifunction IS with an SPI interface to the host. This
driver handles the RTC controller in this chip.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
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<pre>
MC13783 is a multifunction IS with an SPI interface to the host. This
driver handles the RTC controller in this chip.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>New i.MX31 SPI driver</title>
<updated>2008-04-18T07:43:23+00:00</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>lg@denx.de</email>
</author>
<published>2008-04-15T12:14:25+00:00</published>
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<content type='text'>
This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far
only implemented and tested on i.MX31, can with a modified register layout
and definitions be used for i.MX27, I think, MXC CPUs have similar SPI
controllers too.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
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<pre>
This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far
only implemented and tested on i.MX31, can with a modified register layout
and definitions be used for i.MX27, I think, MXC CPUs have similar SPI
controllers too.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
</pre>
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</entry>
<entry>
<title>Boot-related documentation update</title>
<updated>2008-04-18T06:35:23+00:00</updated>
<author>
<name>Bartlomiej Sieka</name>
<email>tur@semihalf.com</email>
</author>
<published>2008-04-14T13:44:16+00:00</published>
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<content type='text'>
- document 'bootm_low' and 'bootm_size' environment variables
- update inaccurate CFG_BOOTMAPSZ entry

Signed-off-by: Bartlomiej Sieka &lt;tur@semihalf.com&gt;
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<pre>
- document 'bootm_low' and 'bootm_size' environment variables
- update inaccurate CFG_BOOTMAPSZ entry

Signed-off-by: Bartlomiej Sieka &lt;tur@semihalf.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash</title>
<updated>2008-04-13T16:40:35+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2008-04-13T16:40:35+00:00</published>
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</entry>
<entry>
<title>cfi_flash: Support buffered writes on non-standard Spansion NOR flash</title>
<updated>2008-04-12T06:59:09+00:00</updated>
<author>
<name>Guennadi Liakhovetski</name>
<email>lg@denx.de</email>
</author>
<published>2008-04-03T11:36:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=96ef831f713289afba19da0c8f905e99da2b23e0'/>
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Some NOR flash chip from Spansion, for example, the s29ws-n MirrorBit
series require different addresses for buffered write commands. Define a
configuration option to support buffered writes on those chips. A more
elegant solution would be to automatically detect those chips by parsing
their CFI records, but that would require introduction of a fixup table
into the cfi_flash driver.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
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<pre>
Some NOR flash chip from Spansion, for example, the s29ws-n MirrorBit
series require different addresses for buffered write commands. Define a
configuration option to support buffered writes on those chips. A more
elegant solution would be to automatically detect those chips by parsing
their CFI records, but that would require introduction of a fixup table
into the cfi_flash driver.

Signed-off-by: Guennadi Liakhovetski &lt;lg@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>SPARC: Added support for SPARC LEON2 SOC Processor.</title>
<updated>2008-04-08T07:58:32+00:00</updated>
<author>
<name>Daniel Hellstrom</name>
<email>daniel@gaisler.com</email>
</author>
<published>2008-03-28T09:00:33+00:00</published>
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<content type='text'>
Signed-off-by: Daniel Hellstrom &lt;daniel@gaisler.com&gt;
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<pre>
Signed-off-by: Daniel Hellstrom &lt;daniel@gaisler.com&gt;
</pre>
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</entry>
<entry>
<title>SPARC: Added support for SPARC LEON3 SOC processor.</title>
<updated>2008-04-08T07:58:32+00:00</updated>
<author>
<name>Daniel Hellstrom</name>
<email>daniel@gaisler.com</email>
</author>
<published>2008-03-26T21:51:29+00:00</published>
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Signed-off-by: Daniel Hellstrom &lt;daniel@gaisler.com&gt;
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<pre>
Signed-off-by: Daniel Hellstrom &lt;daniel@gaisler.com&gt;
</pre>
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</entry>
<entry>
<title>SPARC: Added generic support for SPARC architecture.</title>
<updated>2008-04-08T07:58:32+00:00</updated>
<author>
<name>Daniel Hellstrom</name>
<email>daniel@gaisler.com</email>
</author>
<published>2008-03-28T08:47:00+00:00</published>
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Signed-off-by: Daniel Hellstrom &lt;daniel@gaisler.com&gt;
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<pre>
Signed-off-by: Daniel Hellstrom &lt;daniel@gaisler.com&gt;
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