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<title>u-boot.git/README, branch v2013.07-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>README: align default commands with code</title>
<updated>2013-06-26T14:26:06+00:00</updated>
<author>
<name>Vincent Stehlé</name>
<email>vincent.stehle@freescale.com</email>
</author>
<published>2013-06-20T16:14:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4d98b5c8a51d2bdbb49aaa0189a47ab050c678b3'/>
<id>4d98b5c8a51d2bdbb49aaa0189a47ab050c678b3</id>
<content type='text'>
Align the list of default commands mentioned in the configuration options
paragraph of the README with the actual definitions found in
include/config_cmd_default.h

Signed-off-by: Vincent Stehlé &lt;vincent.stehle@freescale.com&gt;
</content>
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<pre>
Align the list of default commands mentioned in the configuration options
paragraph of the README with the actual definitions found in
include/config_cmd_default.h

Signed-off-by: Vincent Stehlé &lt;vincent.stehle@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>image: Add RSA support for image signing</title>
<updated>2013-06-26T14:18:56+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-06-13T22:10:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=19c402afa2e1190f596f35a84ac049b10d814f1f'/>
<id>19c402afa2e1190f596f35a84ac049b10d814f1f</id>
<content type='text'>
RSA provides a public key encryption facility which is ideal for image
signing and verification.

Images are signed using a private key by mkimage. Then at run-time, the
images are verified using a private key.

This implementation uses openssl for the host part (mkimage). To avoid
bringing large libraries into the U-Boot binary, the RSA public key
is encoded using a simple numeric representation in the device tree.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
RSA provides a public key encryption facility which is ideal for image
signing and verification.

Images are signed using a private key by mkimage. Then at run-time, the
images are verified using a private key.

This implementation uses openssl for the host part (mkimage). To avoid
bringing large libraries into the U-Boot binary, the RSA public key
is encoded using a simple numeric representation in the device tree.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>image: Add signing infrastructure</title>
<updated>2013-06-26T14:18:56+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-06-13T22:10:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3e569a6b1eb7ef0c8144f8c243f9e33c834bf003'/>
<id>3e569a6b1eb7ef0c8144f8c243f9e33c834bf003</id>
<content type='text'>
Add a structure to describe an algorithm which can sign and (later) verify
images.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Add a structure to describe an algorithm which can sign and (later) verify
images.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cros: adds cros_ec keyboard driver</title>
<updated>2013-06-26T14:13:31+00:00</updated>
<author>
<name>Hung-ying Tyan</name>
<email>tyanh@chromium.org</email>
</author>
<published>2013-05-15T10:27:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=713cb68045c6e7fc32c79ab4e922fb3a7548fd2f'/>
<id>713cb68045c6e7fc32c79ab4e922fb3a7548fd2f</id>
<content type='text'>
This patch adds the driver for keyboard that's controlled by ChromeOS EC.

Signed-off-by: Randall Spangler &lt;rspangler@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Vincent Palatin &lt;vpalatin@chromium.org&gt;
Signed-off-by: Hung-ying Tyan &lt;tyanh@chromium.org&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
This patch adds the driver for keyboard that's controlled by ChromeOS EC.

Signed-off-by: Randall Spangler &lt;rspangler@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Vincent Palatin &lt;vpalatin@chromium.org&gt;
Signed-off-by: Hung-ying Tyan &lt;tyanh@chromium.org&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-spi</title>
<updated>2013-06-24T20:37:01+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2013-06-24T20:37:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f9c1456cf632175afb7d6b27f42f1aab8432be0f'/>
<id>f9c1456cf632175afb7d6b27f42f1aab8432be0f</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>sf: Add bank addr code in CONFIG_SPI_FLASH_BAR</title>
<updated>2013-06-23T16:32:50+00:00</updated>
<author>
<name>Jagannadha Sutradharudu Teki</name>
<email>jaganna@xilinx.com</email>
</author>
<published>2013-06-19T10:03:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1dcd6d03811d4f30052a5e24377b378867211b05'/>
<id>1dcd6d03811d4f30052a5e24377b378867211b05</id>
<content type='text'>
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has &lt; 16Mbytes SPI flashes.

It's upto user which has provision to use the bank addr code for
flashes which has &gt; 16Mbytes.

Signed-off-by: Jagannadha Sutradharudu Teki &lt;jaganna@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has &lt; 16Mbytes SPI flashes.

It's upto user which has provision to use the bank addr code for
flashes which has &gt; 16Mbytes.

Signed-off-by: Jagannadha Sutradharudu Teki &lt;jaganna@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL</title>
<updated>2013-06-20T22:08:51+00:00</updated>
<author>
<name>Ying Zhang</name>
<email>b40530@freescale.com</email>
</author>
<published>2013-05-20T06:07:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba1bee43ec3fd314e3216cecdafd45747e46e223'/>
<id>ba1bee43ec3fd314e3216cecdafd45747e46e223</id>
<content type='text'>
There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).

Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.

Signed-off-by: Ying Zhang &lt;b40530@freescale.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
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<pre>
There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).

Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.

Signed-off-by: Ying Zhang &lt;b40530@freescale.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: support application without resetvec segment in the linker script</title>
<updated>2013-06-20T22:08:50+00:00</updated>
<author>
<name>Ying Zhang</name>
<email>b40530@freescale.com</email>
</author>
<published>2013-05-20T06:07:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5df572f0131cf5e0abd8ce4e8f57841b790c40d4'/>
<id>5df572f0131cf5e0abd8ce4e8f57841b790c40d4</id>
<content type='text'>
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang &lt;b40530@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
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<pre>
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang &lt;b40530@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/boot: Change the macro of Boot from SRIO and PCIE master module</title>
<updated>2013-06-20T22:08:48+00:00</updated>
<author>
<name>Liu Gang</name>
<email>Gang.Liu@freescale.com</email>
</author>
<published>2013-05-07T08:30:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c8b281524bf98ee5a52db7da71bccdea002df3f5'/>
<id>c8b281524bf98ee5a52db7da71bccdea002df3f5</id>
<content type='text'>
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
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<pre>
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board/bsc9131rdb: Add DSP side tlb and laws</title>
<updated>2013-06-20T21:09:08+00:00</updated>
<author>
<name>Priyanka Jain</name>
<email>Priyanka.Jain@freescale.com</email>
</author>
<published>2013-04-04T04:01:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=765b0bdb899d614d0455f19548901b79f2baa66c'/>
<id>765b0bdb899d614d0455f19548901b79f2baa66c</id>
<content type='text'>
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain &lt;Priyanka.Jain@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
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<pre>
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain &lt;Priyanka.Jain@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
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