<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/README, branch v2015.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Introduce CONFIG_SPL_PANIC_ON_RAW_IMAGE</title>
<updated>2015-04-10T12:23:37+00:00</updated>
<author>
<name>Albert ARIBAUD \(3ADEV\)</name>
<email>albert.aribaud@3adev.fr</email>
</author>
<published>2015-03-31T09:40:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8c80eb3b533c73a4b4a505fbaf925cdaafe0b5d2'/>
<id>8c80eb3b533c73a4b4a505fbaf925cdaafe0b5d2</id>
<content type='text'>
introduce CONFIG_SPL_PANIC_ON_RAW_IMAGE.
An SPL which define this will panic() if the
image it has loaded does not have a mkimage
signature.

Signed-off-by: Albert ARIBAUD (3ADEV) &lt;albert.aribaud@3adev.fr&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
introduce CONFIG_SPL_PANIC_ON_RAW_IMAGE.
An SPL which define this will panic() if the
image it has loaded does not have a mkimage
signature.

Signed-off-by: Albert ARIBAUD (3ADEV) &lt;albert.aribaud@3adev.fr&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nand: Remove CONFIG_MTD_NAND_VERIFY_WRITE</title>
<updated>2015-03-31T04:24:39+00:00</updated>
<author>
<name>Peter Tyser</name>
<email>ptyser@xes-inc.com</email>
</author>
<published>2015-02-03T17:58:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=073adf987e8251ad934fcac4fd1bf20d4f34f96e'/>
<id>073adf987e8251ad934fcac4fd1bf20d4f34f96e</id>
<content type='text'>
The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some
time and a more generic method of NAND verification now exists in U-Boot.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Heiko Schocher &lt;hs@denx.de&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some
time and a more generic method of NAND verification now exists in U-Boot.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Tested-by: Heiko Schocher &lt;hs@denx.de&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig</title>
<updated>2015-03-28T13:03:08+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-03-19T10:42:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0a12e6872ea2b79c9b3862e7b6c08cc4c1889408'/>
<id>0a12e6872ea2b79c9b3862e7b6c08cc4c1889408</id>
<content type='text'>
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>README: remove description about driver model configuration options (again)</title>
<updated>2015-03-13T13:29:36+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2015-03-11T08:34:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3bde6888c0d74d716af7381c2ad9faee77aaec8f'/>
<id>3bde6888c0d74d716af7381c2ad9faee77aaec8f</id>
<content type='text'>
The Driver Model description in README was removed by commit
65eb659e56fa (README: remove description about driver model
configuration options), and was revived by mistake by commit
b79dadf846e5 when resolving the conflict.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Driver Model description in README was removed by commit
65eb659e56fa (README: remove description about driver model
configuration options), and was revived by mistake by commit
b79dadf846e5 when resolving the conflict.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Introduce erratum workaround for 621766</title>
<updated>2015-03-13T13:28:53+00:00</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2015-03-09T22:12:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9b4d65f918dd84a479552b86ef2cde389926738f'/>
<id>9b4d65f918dd84a479552b86ef2cde389926738f</id>
<content type='text'>
621766: Under a specific set of conditions, executing a sequence of
	NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
621766: Under a specific set of conditions, executing a sequence of
	NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Introduce erratum workaround for 430973</title>
<updated>2015-03-13T13:28:52+00:00</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2015-03-09T22:12:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5902f4ce0f2bd1411e40dc0ece3598a0fc19b2ae'/>
<id>5902f4ce0f2bd1411e40dc0ece3598a0fc19b2ae</id>
<content type='text'>
430973: Stale prediction on replaced inter working branch causes
	Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
430973: Stale prediction on replaced inter working branch causes
	Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Introduce erratum workaround for 454179</title>
<updated>2015-03-13T13:28:48+00:00</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2015-03-09T22:12:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b45c48a7c30734272371fede01e96f499a314664'/>
<id>b45c48a7c30734272371fede01e96f499a314664</id>
<content type='text'>
454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
454179: Stale prediction may inhibit target address misprediction on
	next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around:  Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Introduce erratum workaround for 798870</title>
<updated>2015-03-13T13:28:29+00:00</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2015-03-09T22:11:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c616a0df297e886f09bf88523bcd03a86bdf8704'/>
<id>c616a0df297e886f09bf88523bcd03a86bdf8704</id>
<content type='text'>
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
Tested-by: Matt Porter &lt;mporter@konsulko.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-tegra</title>
<updated>2015-03-10T23:09:18+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-03-10T23:09:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b79dadf846e5e140e261bbfa4decd024357702d7'/>
<id>b79dadf846e5e140e261bbfa4decd024357702d7</id>
<content type='text'>
Conflicts:
	README

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Conflicts:
	README

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>README: remove description about driver model configuration options</title>
<updated>2015-03-06T02:13:43+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2015-02-25T07:54:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65eb659e56fadf8183532d95db1d06fb63c60f9f'/>
<id>65eb659e56fadf8183532d95db1d06fb63c60f9f</id>
<content type='text'>
All the DM-related configuration options are described in Kconfig
helps.  They should not be duplicated in README.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All the DM-related configuration options are described in Kconfig
helps.  They should not be duplicated in README.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
