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<title>u-boot.git/arch/Kconfig, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/Kconfig?h=v2020.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/Kconfig?h=v2020.01'/>
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<updated>2019-09-02T15:38:43Z</updated>
<entry>
<title>sh: r2dplus: Enable OF control</title>
<updated>2019-09-02T15:38:43Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2019-08-31T16:27:58Z</published>
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<id>urn:sha1:8c2c46350d937bae357dc3f69adcbff0022f70ec</id>
<content type='text'>
Enable OF control for SH4 R2Dplus board. This is necessary, because
the PCI uclass is designed in a way that makes it depend on DT and
disallows instanciating devices without DT (e.g. with platdata).

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>riscv: add SPL support</title>
<updated>2019-08-26T08:07:42Z</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-08-21T19:14:45Z</published>
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<id>urn:sha1:8c59f2023cc8d4ab32b3988193ff2eb116df5995</id>
<content type='text'>
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>sysreset: move stm32mp sysreset poweroff implementation to sysreset uclass</title>
<updated>2019-08-19T04:43:26Z</updated>
<author>
<name>Urja Rannikko</name>
<email>urjaman@gmail.com</email>
</author>
<published>2019-05-16T21:48:42Z</published>
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<id>urn:sha1:b8050511c6ee4ab60ef4248dff42aff187696249</id>
<content type='text'>
This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF
to signal when we need it. Enable it from the STPMIC1 config and in
sandbox.

The config flag is transitionary, that is it can be removed after all
poweroff implementations use sysreset, and just have CMD_POWEROFF depend
on sysreset.

Signed-off-by: Urja Rannikko &lt;urjaman@gmail.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
Tested-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>test: dm: add a test for MDIO MUX DM uclass</title>
<updated>2019-07-18T21:37:13Z</updated>
<author>
<name>Alex Marginean</name>
<email>alexandru.marginean@nxp.com</email>
</author>
<published>2019-07-12T07:13:53Z</published>
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<id>urn:sha1:c3d9f3f899038e21a66e1e4a685abc0a5a1d5d9c</id>
<content type='text'>
Adds a test using a makeshift MDIO MUX.  The test is based on the existing
MDIO test.  It uses the last emulated PHY register to verify MUX selection.

Signed-off-by: Alex Marginean &lt;alexm.osslist@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>test: dm: add MDIO test</title>
<updated>2019-07-15T18:32:25Z</updated>
<author>
<name>Alex Marginean</name>
<email>alexm.osslist@gmail.com</email>
</author>
<published>2019-06-03T16:12:28Z</published>
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<id>urn:sha1:ec9594a50f02944944dcc76a6cffce9861e8614d</id>
<content type='text'>
A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.

Signed-off-by: Alex Marginean &lt;alexm.osslist@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>pci_ep: add pci endpoint sandbox driver</title>
<updated>2019-07-11T14:05:15Z</updated>
<author>
<name>Ramon Fried</name>
<email>ramon.fried@gmail.com</email>
</author>
<published>2019-04-27T08:15:23Z</published>
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<id>urn:sha1:bb413337826ef1a1445ff9fb33424fd231430228</id>
<content type='text'>
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.

Signed-off-by: Ramon Fried &lt;ramon.fried@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Kconfig: Add SPI / SPI_FLASH as dependencies</title>
<updated>2019-06-13T07:21:06Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-29T21:01:28Z</published>
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<id>urn:sha1:a4298ddaf8bbccf8a14acb6be33764eecbea9abd</id>
<content type='text'>
In order to use CMD_SF / CMD_SPI / ENV_IS_IN_SPI_FLASH we need to have
the SPI (or SPI_FLASH/DM_SPI_FLASH, for CMD_SF) enabled.  Express this
in the Kconfigs.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
</content>
</entry>
<entry>
<title>m68k: add OF control support to m68k</title>
<updated>2019-05-24T12:11:58Z</updated>
<author>
<name>Angelo Dureghello</name>
<email>angelo@sysam.it</email>
</author>
<published>2019-03-13T20:46:51Z</published>
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<id>urn:sha1:abe0f879996b3bf7bc3bfdb35b83a8dd8ee3ea7d</id>
<content type='text'>
Add SUPPORT_OF_CONTROL at this stage, to avoid to break build
bisectability.

Signed-off-by: Angelo Dureghello &lt;angelo@sysam.it&gt;
</content>
</entry>
<entry>
<title>Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchip</title>
<updated>2019-05-09T16:36:17Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-09T11:12:51Z</published>
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<id>urn:sha1:f30f268a07b0c9e4418366debc9ad0100a47cea4</id>
<content type='text'>
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
</content>
</entry>
<entry>
<title>sysreset: enable driver support in SPL/TPL</title>
<updated>2019-05-08T09:34:12Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2019-04-02T12:41:25Z</published>
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<id>urn:sha1:09259fce1e8b4ac34a47d4590f42878a38b42826</id>
<content type='text'>
SPL/TPL also need use sysreset for some feature like panic callback.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
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