<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/Kconfig, branch v2020.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/Kconfig?h=v2020.04</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/Kconfig?h=v2020.04'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2019-12-15T03:44:24Z</updated>
<entry>
<title>x86: Enable pinctrl in SPL and TPL</title>
<updated>2019-12-15T03:44:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:42:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e556d3d630d31fd966eb676fbe43a90bf06e6d29'/>
<id>urn:sha1:e556d3d630d31fd966eb676fbe43a90bf06e6d29</id>
<content type='text'>
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Don't imply libfdt or SPI flash in TPL</title>
<updated>2019-12-15T03:44:15Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:42:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=69b1e9f4f83ec30d6e010312e932928132a2324e'/>
<id>urn:sha1:69b1e9f4f83ec30d6e010312e932928132a2324e</id>
<content type='text'>
We don't want to pull in libfdt if of-platdata is being used, since it
reduces the available code-size saves. Also, SPI flash is seldom needed
in TPL.

Drop these options.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move UCLASS_IRQ into a separate file</title>
<updated>2019-12-15T03:44:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:41:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79d66a6ac117dc4978c3ee66e342ad06411d390c'/>
<id>urn:sha1:79d66a6ac117dc4978c3ee66e342ad06411d390c</id>
<content type='text'>
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: sandbox: Add a PMC emulator and test</title>
<updated>2019-12-15T03:44:11Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:41:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3b65ee34b908ce0c495c25987f5feb37ac163eab'/>
<id>urn:sha1:3b65ee34b908ce0c495c25987f5feb37ac163eab</id>
<content type='text'>
Add a simple PMC for sandbox to permit tests to run.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>sh: r2dplus: Enable OF control</title>
<updated>2019-09-02T15:38:43Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2019-08-31T16:27:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8c2c46350d937bae357dc3f69adcbff0022f70ec'/>
<id>urn:sha1:8c2c46350d937bae357dc3f69adcbff0022f70ec</id>
<content type='text'>
Enable OF control for SH4 R2Dplus board. This is necessary, because
the PCI uclass is designed in a way that makes it depend on DT and
disallows instanciating devices without DT (e.g. with platdata).

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>riscv: add SPL support</title>
<updated>2019-08-26T08:07:42Z</updated>
<author>
<name>Lukas Auer</name>
<email>lukas.auer@aisec.fraunhofer.de</email>
</author>
<published>2019-08-21T19:14:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8c59f2023cc8d4ab32b3988193ff2eb116df5995'/>
<id>urn:sha1:8c59f2023cc8d4ab32b3988193ff2eb116df5995</id>
<content type='text'>
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly
jumping to the image and via OpenSBI firmware. In the first case, both
U-Boot SPL and proper must be compiled to run in the same privilege
mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine
mode and U-Boot proper for supervisor mode.

To be able to use SPL, boards have to provide a supported SPL boot
device.

Signed-off-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
<entry>
<title>sysreset: move stm32mp sysreset poweroff implementation to sysreset uclass</title>
<updated>2019-08-19T04:43:26Z</updated>
<author>
<name>Urja Rannikko</name>
<email>urjaman@gmail.com</email>
</author>
<published>2019-05-16T21:48:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b8050511c6ee4ab60ef4248dff42aff187696249'/>
<id>urn:sha1:b8050511c6ee4ab60ef4248dff42aff187696249</id>
<content type='text'>
This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF
to signal when we need it. Enable it from the STPMIC1 config and in
sandbox.

The config flag is transitionary, that is it can be removed after all
poweroff implementations use sysreset, and just have CMD_POWEROFF depend
on sysreset.

Signed-off-by: Urja Rannikko &lt;urjaman@gmail.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
Tested-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>test: dm: add a test for MDIO MUX DM uclass</title>
<updated>2019-07-18T21:37:13Z</updated>
<author>
<name>Alex Marginean</name>
<email>alexandru.marginean@nxp.com</email>
</author>
<published>2019-07-12T07:13:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c3d9f3f899038e21a66e1e4a685abc0a5a1d5d9c'/>
<id>urn:sha1:c3d9f3f899038e21a66e1e4a685abc0a5a1d5d9c</id>
<content type='text'>
Adds a test using a makeshift MDIO MUX.  The test is based on the existing
MDIO test.  It uses the last emulated PHY register to verify MUX selection.

Signed-off-by: Alex Marginean &lt;alexm.osslist@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>test: dm: add MDIO test</title>
<updated>2019-07-15T18:32:25Z</updated>
<author>
<name>Alex Marginean</name>
<email>alexm.osslist@gmail.com</email>
</author>
<published>2019-06-03T16:12:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ec9594a50f02944944dcc76a6cffce9861e8614d'/>
<id>urn:sha1:ec9594a50f02944944dcc76a6cffce9861e8614d</id>
<content type='text'>
A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.

Signed-off-by: Alex Marginean &lt;alexm.osslist@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>pci_ep: add pci endpoint sandbox driver</title>
<updated>2019-07-11T14:05:15Z</updated>
<author>
<name>Ramon Fried</name>
<email>ramon.fried@gmail.com</email>
</author>
<published>2019-04-27T08:15:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bb413337826ef1a1445ff9fb33424fd231430228'/>
<id>urn:sha1:bb413337826ef1a1445ff9fb33424fd231430228</id>
<content type='text'>
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.

Signed-off-by: Ramon Fried &lt;ramon.fried@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
