u-boot.git/arch/arc/include/asm, branch v2018.05-rc2

ARC: Implement a function to sync and cleanup caches

2018-03-21T14:06:54Z

Implement specialized function to clenup caches (and therefore sync instruction and data caches) which can be used for cleanup before linux launch or to sync caches during U-Boot self-relocation. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Move IOC enabling to compile-time options

2018-03-21T14:06:54Z

Use CONFIG_ARC_DBG_IOC_ENABLE Kconfig option instead of ioc_enable global variable. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Move cache global variables to arch_global_data

2018-03-21T14:06:54Z

There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initialization, so these variables get overwritten when we copy .data section from ROM. Instead we move these global variables into our "global data" structure so that we may really start from ROM. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Move BCR encodings to separate header file

2018-03-21T14:06:54Z

We're starting to use more and more BCRs and having their definitions in-lined in sources becomes a bit annoying so we move it all to a separate header. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Flush & invalidate D$ with a single command

2018-03-21T14:06:49Z

We don't implement separate flush_dcache_all() intentionally as entire data cache invalidation is dangerous operation even if we flush data cache right before invalidation. There is the real example: We may get stuck in the following code if we store any context (like BLINK register) on stack in invalidate_dcache_all() function. BLINK register is the register where return address is automatically saved when we do function call with instructions like 'bl'. void flush_dcache_all() { __dc_entire_op(OP_FLUSH); // Other code // } void invalidate_dcache_all() { __dc_entire_op(OP_INV); // Other code // } void foo(void) { flush_dcache_all(); invalidate_dcache_all(); } Now let's see what really happens during that code execution: foo() |->> call flush_dcache_all [return address is saved to BLINK register] [push BLINK] (save to stack) ![point 1] |->> call __dc_entire_op(OP_FLUSH) [return address is saved to BLINK register] [flush L1 D$] return [jump to BLINK] <<------ [other flush_dcache_all code] [pop BLINK] (get from stack) return [jump to BLINK] <<------ |->> call invalidate_dcache_all [return address is saved to BLINK register] [push BLINK] (save to stack) ![point 2] |->> call __dc_entire_op(OP_FLUSH) [return address is saved to BLINK register] [invalidate L1 D$] ![point 3] // Oops!!! // We lose return address from invalidate_dcache_all function: // we save it to stack and invalidate L1 D$ after that! return [jump to BLINK] <<------ [other invalidate_dcache_all code] [pop BLINK] (get from stack) // we don't have this data in L1 dcache as we invalidated it in [point 3] // so we get it from next memory level (for example DDR memory) // but in the memory we have value which we save in [point 1], which // is return address from flush_dcache_all function (instead of // address from current invalidate_dcache_all function which we // saved in [point 2] !) return [jump to BLINK] <<------ // As BLINK points to invalidate_dcache_all, we call it again and // loop forever. Fortunately we may do flush and invalidation of D$ with a single one instruction which automatically mitigates a situation described above. And because invalidate_dcache_all() isn't used in common U-Boot code we implement "flush and invalidate dcache all" instead. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Introduce is_isa_X() functions

2018-03-21T14:06:49Z

Introduce is_isa_arcv2() and is_isa_arcompact() functions. These functions only check configuration options and return compile-time constant so they can be used instead of #ifdef's to to write cleaner code. Now we can write: -------------->8--------------- if (is_isa_arcv2()) ioc_configure(); -------------->8--------------- instead of: -------------->8--------------- ifdef CONFIG_ISA_ARCV2 ioc_configure(); endif -------------->8--------------- Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

arc: Fine-tune implementation of memory barriers

2018-03-21T13:21:34Z

We improve on 2 things: 1. Only ARC HS family has "dmb" instructions so do compile-time check for automatically defined macro __ARCHS__. Previous check for ARCv2 ISA was not good enough because ARC EM family is v2 ISA as well but still "dmb" instaruction is not supported in EM family. 2. Still if there's no dedicated instruction for memory barrier let's at least insert compile-time barrier to make sure compiler deosn't reorder critical memory operations. Signed-off-by: Alexey Brodkin

arc: Get rid of handwritten string routines

2018-03-21T13:21:34Z

U-Boot is a bit special piese of software because it is being only executed once on power-on as compared to operating system for example. That's why we don't care much about performance optimizations instead we're more concerned about size. And up-to-date compilers might produce much smaller code compared to performance-optimized routines copy-pasted from the Linux kernel. Here's an example: ------------------------------->8-------------------------- --- size_asm_strings.txt +++ size_c_strings.txt @@ -1,2 +1,2 @@ text data bss dec hex filename - 121260 3784 3308 128352 1f560 u-boot + 120448 3784 3308 127540 1f234 u-boot ------------------------------->8-------------------------- See we were able to shave off ~800 bytes of .text section. Also usage of string routines implemented in C gives us an ability to support more HW flavors for free: generated instructions will match our target as long as correct compiler option is used. Signed-off-by: Alexey Brodkin

ARC: ARCv2: Cache: Fixed operation without IOC

2018-01-19T14:59:34Z

Previous SLC management implementation is broken. Seems like it was never sufficiently tested probably because most of the time IOC was used instead (i.e. no manual cache operations were done). Now if we disable IOC in U-boot we'll get a lot of errors while using DMA-enabled peripherals. This time we fix it by substitution of broken per-line SLC operations region operations as it is done in the Linux kernel (we took it from v4.14 which is the latest stable as of today). Among other things this implementation might be a bit faster because instead of iteration over each and every cache line we're taking care about entire region in one go. Main changes: * Replaced __slc_line_op (per line operations) by __slc_rgn_op (region operations). * Reworked __slc_entire_op to get rid of __after_slc_op and __before_slc_op functions. Note flush fix (flush only instead of flush-n-inv when OP_FLUSH is used, see [1] for more details) is already incorporated here. * Added SLC invalidation to invalidate_icache_all(). * Added (start >= end) check to invalidate_dcache_range() and flush_dcache_range() as some buggy drivers pass region start == end. * Added read-out of MMU BCR so we may know if PAE40 exists in HW and then act on a particular AUX regs accordingly. [1] http://lists.infradead.org/pipermail/linux-snps-arc/2018-January/003357.html Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: add defines of some cache and xCCM AUX registers

2017-12-11T08:36:22Z

Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin