u-boot.git/arch/arc/include, branch v2016.01

arc: add empty asm/processor.h to satisfy compilation of USB code

2015-11-17T21:39:22+00:00

common/usb.c unconditionally includes 
And now to allow USB support on ARC boards we have to have that header.

Signed-off-by: Alexey Brodkin

arc: add stubs for map_physmem() and unmap_physmem()

2015-11-17T21:38:35+00:00

Up until now there was no need in those stubs.

But since following commit compilation of U-Boot on ARC is broken:
------------------------>8----------------------
commit 7861204c9af7fec1ea9b41541c272516235a6c93
Author: Stephen Warren 
Date:   Sat Oct 3 13:56:46 2015 -0600

    itest: make memory access work under sandbox

    itest accesses memory, and hence must map/unmap it. Without doing so, it
    accesses invalid addresses and crashes.

    Signed-off-by: Stephen Warren 
    Reviewed-by: Simon Glass 
------------------------>8----------------------

That's because CMD_ITEST is enabled by default in common/Kconfig and now
map_physmem()/unmap_physmem() is used there.

So this patch adds missing stubs for ARC.

Signed-off-by: Alexey Brodkin 
Reviewed-by: Simon Glass 
Cc: Stephen Warren

arc: Use the generic bitops headers

2015-11-05T15:52:29+00:00

The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam

arc: significant cache rework

2015-07-01T14:17:27+00:00

[1] Align cache management functions to those in Linux kernel. I.e.:
    a) Use the same functions for all cache ops (D$ Inv/Flush)
    b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.

 [2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.

 [3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).

Signed-off-by: Alexey Brodkin

arc: add support for SLC (System Level Cache, AKA L2-cache)

2015-04-03T06:47:50+00:00

ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
 * slc_enable/disable
 * slc_flush/invalidate

For now we just disable SLC to escape DMA coherency issues until either:
 * SLC flush/invalidate is supported in DMA APIin U-Boot
 * hardware DMA coherency is implemented (that might be board specific
   so probably we'll need to have a separate Kconfig option for
   controlling SLC explicitly)

Signed-off-by: Alexey Brodkin

arc: get rid of CONFIG_SYS_GENERIC_GLOBAL_DATA

2015-04-03T06:47:49+00:00

As discussed on mailing list we're drifting away from
CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem()
for global data.

So do this for ARC architecture.

Signed-off-by: Alexey Brodkin

arc: clean-up init procedure

2015-04-03T06:47:49+00:00

Intention behind this work was elimination of as much assembly-written
code as it is possible.

In case of ARC we already have relocation fix-up implemented in C so why
don't we use C for U-Boot copying, .bss zeroing etc.

It turned out x86 uses pretty similar approach so we re-used parts of
code in "board_f.c" initially implemented for x86.

Now assembly usage during init is limited to stack- and frame-pointer
setup before and after relocation.

Signed-off-by: Alexey Brodkin 
Cc: Simon Glass

generic-board: select SYS_GENERIC_BOARD for some architectures

2015-03-28T13:03:08+00:00

We have done with the generic board conversion for all the boards
of ARC, Blackfin, M68000, MicroBlaze, MIPS, NIOS2, Sandbox, X86.

Let's select SYS_GENERIC_BOARD for those architectures, so we can
tell which architecture has finished the conversion at a glance.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass 
Reviewed-by: Alexey Brodkin

use ASM_NL instead of '; ' for assembler new line character in the macro

2015-03-06T01:49:43+00:00

For some assemblers, they use another character as newline in a macro
(e.g. arc uses '`'), so for generic assembly code, need use ASM_NL (a
macro) instead of ';' for it.

Basically this is the same patch as applied to Linux kernel -
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/include/linux/linkage.h?id=9df62f054406992ce41ec4558fca6a0fa56fffeb

but modified a bit to fit in U-Boot.

Signed-off-by: Chen Gang 
Signed-off-by: Alexey Brodkin 
Cc: Masahiro Yamada 
Cc: Simon Glass 
Cc: Tom Rini

arc: introduce U-Boot port for ARCv2 ISA

2015-02-13T06:17:51+00:00

ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).

Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.

In v1 it is implemented in the same way as on many other architectures -
as a special location where user may put whether code executed in place
(if machine word of space is enough) or jump to a full-scale interrupt
handler.

In v2 interrupt table is just an array of adresses of real interrupt
handlers. That requires a separate section for IVT that is not encoded
as code by assembler.

This change adds support for following cores:
 * ARC EM6 (simple 32-bit microcontroller without MMU)
 * ARC HS36 (advanced 32-bit microcontroller without MMU)
 * ARC HS38 (advanced 32-bit microcontroller with MMU)

As a part of ARC HS38 new version of MMU (v4) was introduced.

Also this change adds AXS131 board which is the same DW ARC SDP base board but
with ARC HS38 CPU tile.

Signed-off-by: Alexey Brodkin