u-boot.git/arch/arc/lib, branch v2017.05

board_f: Rename initdram() to dram_init()

2017-04-13T13:40:57+00:00

This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.

Signed-off-by: Simon Glass 
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini

ARCv2: SLC: Make sure busy bit is set properly on SLC flushing

2017-04-11T14:54:31+00:00

As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)

Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.

Same fix made in Linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854

Signed-off-by: Alexey Brodkin

arcv2: Halt non-master cores

2017-03-31T19:09:36+00:00

Even though we expect only master core to execute U-Boot code
let's make sure even if for some reason slave cores attempt to
execute U-Boot in parallel with master they get halted very early.

If platform wants it may kick-start slave cores before passing control
to say Linux kernel or any other application that want to see all cores
of SMP SoC up and running.

Signed-off-by: Alexey Brodkin

arc: use timer driver for ARC boards

2017-03-24T11:47:52+00:00

This commit replaces legacy timer code with usage of arc timer
driver.

It removes arch/arc/lib/time.c file and selects CONFIG_CLK,
CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default.
Therefore we remove CONFIG_CLK option from less common axs101 and
axs103 defconfigs.

Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from
axs10x.h, tb100.h and nsim.h configs files as it is no longer required.

Signed-off-by: Vlad Zakharov 
Reviewed-by: Simon Glass

libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORY

2016-12-03T03:54:34+00:00

Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.

This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt().  It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.

Signed-off-by: Masahiro Yamada 
Acked-by: Alexey Brodkin 
Acked-by: Simon Glass 
Fixed build error for x86:
Signed-off-by: Simon Glass

arc: No need in sections defined in sources with newer tools

2016-08-05T09:50:25+00:00

Starting from arc-2016.03 GNU tools linker properly works with
symbols defined in linker script and so external declarations
are no longer required, dump them.

Signed-off-by: Alexey Brodkin

arc: Update exception & interrupt handling for ARCv2

2016-08-05T09:50:25+00:00

Initially IVT for ARCv2 was simply copypasted from ARCompact
with some selected fixes so basic stuff works.

Now we update it with more ARCv2 specific vectors like
 * Software Interrupt
 * Division by zero
 * Data cache consistency error
 * Misaligned access

Also normal interrupts are now implemented properly and extened to
all possible 240 items.

Signed-off-by: Alexey Brodkin

arc: Add debug messages during relocation fixups

2016-08-05T09:50:25+00:00

This might be useful to make sure relocation fixups really
happen. And since this info gets printed only in DEBUG
build it doesn't really hurt normal execution.

Signed-off-by: Alexey Brodkin

arc/cache: Flush & invalidate all caches right before enabling IOC

2016-06-13T12:38:05+00:00

According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.

But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.

Signed-off-by: Alexey Brodkin

arc/cache: really do invalidate_dcache_all() even if IOC exists

2016-06-13T12:38:05+00:00

invalidate_dcache_all() could be used in different use-cases
and what is especially important most of those cases won't be
related to DMAed data to or from peripherals, i.e. we'll be doing
invalidation of data used purely by CPU cores.

Given that IOC engine only snoops data that goes through DMA
we need to care ourselves about data used only by CPU cores
and so remove dependency on IOC from invalidate_dcache_all()
and always do real invalidation.

Signed-off-by: Alexey Brodkin