u-boot.git/arch/arc/lib, branch v2018.05-rc2

ARC: bootm: Refactor GO and PREP subcommands implementation

2018-03-23T12:57:51Z

Refactor GO and PREP subcommands implementation for a simpler override in the boards platform code. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Refactor arc_ioc_setup()

2018-03-21T14:06:55Z

Move all checks before cache flush and IOC setup. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Add missing cache cleanup before cache disable

2018-03-21T14:06:55Z

Add missing cache cleanup before cache disable: * Flush and invalidate L1 D$ before disabling. Flush and invalidate SLC before L1 D$ disabling (as it will be bypassed for data) Otherwise we can lose some data when we disable L1 D$ if this data isn't flushed to next level cache. Or we can get wrong data if L1 D$ has some entries after enable which we modified when the L1 D$ was disabled. * Invalidate L1 I$ before disabling. Otherwise we can execute wrong instructions after L1 I$ enable if we modified any code when L1 I$ was disabled. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Add more HW configuration checks

2018-03-21T14:06:55Z

Add additional cache configuration checks and note about supported configurations. It is unlikely to face some configuration in real life but it's better to be prepared and refuse to work on those. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Implement a function to sync and cleanup caches

2018-03-21T14:06:54Z

Implement specialized function to clenup caches (and therefore sync instruction and data caches) which can be used for cleanup before linux launch or to sync caches during U-Boot self-relocation. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Fix SLC operations when SLC is bypassed for data

2018-03-21T14:06:54Z

If L1 D$ is disabled SLC is bypassed for data and all load/store requests are sent directly to main memory. If L1 I$ is disabled SLC is NOT bypassed for instructions and all instruction requests are fetched through SLC. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Implement [i,d]cache_enabled() as separate functions

2018-03-21T14:06:54Z

Implement icache_enabled() and dcache_enabled() as separate functions which can be used with "inline" attribute. This is a preparation to make them always_inline. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Move IOC enabling to compile-time options

2018-03-21T14:06:54Z

Use CONFIG_ARC_DBG_IOC_ENABLE Kconfig option instead of ioc_enable global variable. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Move PAE exists check into slc_upper_region_init()

2018-03-21T14:06:54Z

Move check for PAE existence into slc_upper_region_init() instead of its caller as more appropriate place. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Move cache global variables to arch_global_data

2018-03-21T14:06:54Z

There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initialization, so these variables get overwritten when we copy .data section from ROM. Instead we move these global variables into our "global data" structure so that we may really start from ROM. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin