u-boot.git/arch/arc/lib, branch v2018.07

ARC: Reset: Implement weak reset_cpu()

2018-05-31T17:13:29+00:00

This will allow for board-specific implementation of reset.
Default version will just stop execution with help of BRK instruction.

Signed-off-by: Alexey Brodkin

ARC: Reset: Use __builtin_arc_brk() instead of open-coded ASM

2018-05-31T17:13:29+00:00

For quite some time we have a GCC's built-in which inserts BRK
instruction so let's use it instead of simple insertion of in-line
assembly.

Signed-off-by: Alexey Brodkin

ARC: Improve relocation fix-ups

2018-05-31T17:13:29+00:00

We used to have the one and only linker script for all ARC boards
and so we relied on a particular order of symbols there.

Because of that we used __ivt_end as the marker of the end of all the
code which won't be true any longer if we move .ivt section to any other
place. That said we'd better check for each section separately.

A couple of other improvements:
 1. There's no point to include the marker of section end in interested
    range because its address is beyond the section, i.e. we should
    compare with "<" but not "<=".

 2. .ivt section for ARCv2 cores is just an array of 32-bit ints and
    they are not swapped even on little-endia cores while in case of
    ARCompact cores .ivt contains valid code so swapping is required.

 3. Just in case add check for ARC600 which is also ARCompact
    and its .ivt is normal code.

Signed-off-by: Alexey Brodkin

ARC: Cache: Don't compare I$ and D$ line lengths

2018-05-31T17:13:29+00:00

We don't care much about I$ line length really as there're
no per-line ops on I$ instead we only do full invalidation of it
on occasion of relocation and right before jumping to the OS.

Also as compared to Linux kernel where we don't support different
lengths of I$ and D$ lines in U-Boot we have to deal with such an
exotic configs if the target board is not supposed to run Linux kernel.

Signed-off-by: Alexey Brodkin

ARC: init debug uart in early common arc code

2018-05-24T12:59:17+00:00

The debug UART is intended for use very early in U-Boot to debug
problems before serial drivers are up.

Call debug_uart_init right before board_init_f.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Alexey Brodkin

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12+00:00

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini

ARC: Remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.c

2018-04-17T17:52:17+00:00

"Global data" structure "gd" is not used in init_helpers.c
thus DECLARE_GLOBAL_DATA_PTR might be safely removed.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Alexey Brodkin

ARC: bootm: Refactor GO and PREP subcommands implementation

2018-03-23T12:57:51+00:00

Refactor GO and PREP subcommands implementation for a simpler
override in the boards platform code.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Alexey Brodkin

ARC: Cache: Refactor arc_ioc_setup()

2018-03-21T14:06:55+00:00

Move all checks before cache flush and IOC setup.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Alexey Brodkin

ARC: Cache: Add missing cache cleanup before cache disable

2018-03-21T14:06:55+00:00

Add missing cache cleanup before cache disable:
 * Flush and invalidate L1 D$ before disabling. Flush and invalidate
   SLC before L1 D$ disabling (as it will be bypassed for data)
   Otherwise we can lose some data when we disable L1 D$ if this data
   isn't flushed to next level cache. Or we can get wrong data if L1 D$
   has some entries after enable which we modified when the L1 D$ was
   disabled.
 * Invalidate L1 I$ before disabling. Otherwise we can execute wrong
   instructions after L1 I$ enable if we modified any code when
   L1 I$ was disabled.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Alexey Brodkin