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<title>u-boot.git/arch/arc, branch v2015.04-rc2</title>
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<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arc?h=v2015.04-rc2</id>
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<updated>2015-02-13T06:17:51Z</updated>
<entry>
<title>arc: introduce U-Boot port for ARCv2 ISA</title>
<updated>2015-02-13T06:17:51Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-01-13T15:35:46Z</published>
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<id>urn:sha1:f13606b77d32344d35f6430eb45cffd47302e244</id>
<content type='text'>
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary
incompatible with ISAv1 (AKA ARCompact).

Significant difference between ISAv2 and v1 is implementation of
interrupt vector table.

In v1 it is implemented in the same way as on many other architectures -
as a special location where user may put whether code executed in place
(if machine word of space is enough) or jump to a full-scale interrupt
handler.

In v2 interrupt table is just an array of adresses of real interrupt
handlers. That requires a separate section for IVT that is not encoded
as code by assembler.

This change adds support for following cores:
 * ARC EM6 (simple 32-bit microcontroller without MMU)
 * ARC HS36 (advanced 32-bit microcontroller without MMU)
 * ARC HS38 (advanced 32-bit microcontroller with MMU)

As a part of ARC HS38 new version of MMU (v4) was introduced.

Also this change adds AXS131 board which is the same DW ARC SDP base board but
with ARC HS38 CPU tile.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: build libgcc in U-Boot</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:20Z</published>
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<id>urn:sha1:a67ef280f46803e319639f5380ff8da6c6b7fbe7</id>
<content type='text'>
This way we may have very limited set of functions implemented so we
save some space.

Also it allows us to build U-Boot for any ARC core with the same one
toolchain because we don't rely on pre-built libgcc.

For example:
 * we may use little-endian toolchain but build U-Boot for ether
endianess
 * we may use non-multilibbed uClibc toolchain but build U-Boot for
whatever ARC CPU flavour that current GCC supports

Private libgcc built from generic C implementation contributes only 144
bytes to .text section so we don't see significant degradation of size:
---&gt;8---
$ arc-linux-size u-boot.libgcc-prebuilt
   text	   data	    bss	    dec	    hex	filename
 222217	  24912	 214820	 461949	  70c7d	u-boot.libgcc-prebuilt

$ arc-linux-size u-boot.libgcc-private
   text	   data	    bss	    dec	    hex	filename
 222361	  24912	 214820	 462093	  70d0d	u-boot.libgcc-private
---&gt;8---

Also I don't notice visible performance degradation compared to
pre-built libgcc (where at least "*div*" functions are had-written in
assembly) on typical operations of downloading 10Mb uImage over TFTP and
bootm.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: move CPU flags selection to the main "config.mk"</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:19Z</published>
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<id>urn:sha1:51f4999bc5ad5f8430da0297d12c1abef9c05568</id>
<content type='text'>
As a preparation to ARCv2 port submission we're moving CPU slection
flags to a common location.
Also it will allow us to have more flexible CPU specification, not only
ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.h</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:17Z</published>
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<id>urn:sha1:a1dbe57d2d45d311e402c357831bbf5c5157a32c</id>
<content type='text'>
Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards
so there's no sense in separate per-board definitions.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.h</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:15Z</published>
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<id>urn:sha1:6eb651ad29636682067f76de4f40c45119269f8b</id>
<content type='text'>
There're no other options for ARC except "generic board" so ther's no
point to define CONFIG_SYS_GENERIC_BOARD per board.

We now have it set fo all ARC boards.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: add selection of endianess in Kconfig</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:14Z</published>
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<id>urn:sha1:1f9ad44546ea872fc6671602eb411377dd424c9e</id>
<content type='text'>
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: select cache settings via menuconfig</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:13Z</published>
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<id>urn:sha1:205e7a7b77726abeff57576e2ecf2c6d4dc07ccf</id>
<content type='text'>
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: define and use PTAG AUX regs for MMUv3 only</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:12Z</published>
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<id>urn:sha1:5ff40f3d4226d45c78f3bb9db276f6685b24a89a</id>
<content type='text'>
DC_PTAG and IC_PTAG registers only exist in MMUv3.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: add more flavours of ARC700 series CPU</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2015-02-03T10:58:11Z</published>
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<id>urn:sha1:812980bdd6c9112014f3946d1cb2728a2121ba34</id>
<content type='text'>
Now we may select a particular version of ARC700:
 * ARC750D or
 * ARC770D

It allows more flexible (or more fine tuned) configuration of U-Boot.
Before that change we relied on minimal configuration but now we may
use specific features of each CPU.

Moreover allows us to escape manual selection of options that
exist in both CPUs but may have say different version like MMUv2 in
ARC750D vs MMUv3 in ARC770D.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arc: memcmp - fix zero-delay loop utilization</title>
<updated>2015-02-09T13:41:20Z</updated>
<author>
<name>Igor Guryanov</name>
<email>guryanov@synopsys.com</email>
</author>
<published>2015-02-03T10:58:09Z</published>
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<id>urn:sha1:f958a91fa5cefd0cda76c887ee0488fb9158496e</id>
<content type='text'>
It's prohibited to put branch instruction in the very end of zero-delay
loop. On execution this causes "Illegal instruction" exception.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
Signed-off-by: Igor Guryanov &lt;guryanov@synopsys.com&gt;
</content>
</entry>
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