u-boot.git/arch/arc, branch v2018.05-rc2

ARC: HSDK: Enable SPI flash support

2018-04-02T09:27:56Z

HSDK board has sst26wf016 SPI flash IC which we want to support. Add SPI controller, CS-gpio and SPI flash nodes to hsdk device tree. Enable corresponding options in hsdk defconfig. For SPI write functionality to work we need [1] which adds support of sst26xxx ICs. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=35796 Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: HSDK: Add platform-specific commands

2018-04-02T09:27:56Z

This patch add support of hsdk platform-specific commands: hsdk_clock set - set clock from axi_freq, cpu_freq and tun_freq environment variables/command line arguments hsdk_clock get - save clock frequencies to axi_freq, cpu_freq and tun_freq environment variables hsdk_clock print - show CPU, AXI, DDR and TUNNEL current clock frequencies. hsdk_clock print_all - show all currently used clock frequencies. hsdk_init - setup board HW in one of pre-defined configuration (hsdk_hs34 / hsdk_hs36 / hsdk_hs36_ccm / hsdk_hs38 / hsdk_hs38_ccm / hsdk_hs38x2 / hsdk_hs38x3 / hsdk_hs38x4) hsdk_go - run baremetal application on hsdk configured by hsdk_init command. This patch changes default behaviour of 'bootm' command: now we are able to set number of CPUs to be kicked by setting 'core_mask' environment variable before 'bootm' command run. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: AXS10x: DTS: Remove unused interrupt properties

2018-04-02T09:26:13Z

Some device tree nodes (like ethernet, ohci, ehci) in axs10x_mb.dtsi were copied from linux device tree, so they have interrupts properties. As we don't use interrupts in uboot we don't have interrupt controller node in AXS10x device tree. In result we get warnings when we compile such device tree. So remove unused interrupts properties to get rid of this warnings. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: bootm: Refactor GO and PREP subcommands implementation

2018-03-23T12:57:51Z

Refactor GO and PREP subcommands implementation for a simpler override in the boards platform code. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Refactor arc_ioc_setup()

2018-03-21T14:06:55Z

Move all checks before cache flush and IOC setup. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Add missing cache cleanup before cache disable

2018-03-21T14:06:55Z

Add missing cache cleanup before cache disable: * Flush and invalidate L1 D$ before disabling. Flush and invalidate SLC before L1 D$ disabling (as it will be bypassed for data) Otherwise we can lose some data when we disable L1 D$ if this data isn't flushed to next level cache. Or we can get wrong data if L1 D$ has some entries after enable which we modified when the L1 D$ was disabled. * Invalidate L1 I$ before disabling. Otherwise we can execute wrong instructions after L1 I$ enable if we modified any code when L1 I$ was disabled. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Add more HW configuration checks

2018-03-21T14:06:55Z

Add additional cache configuration checks and note about supported configurations. It is unlikely to face some configuration in real life but it's better to be prepared and refuse to work on those. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Implement a function to sync and cleanup caches

2018-03-21T14:06:54Z

Implement specialized function to clenup caches (and therefore sync instruction and data caches) which can be used for cleanup before linux launch or to sync caches during U-Boot self-relocation. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Fix SLC operations when SLC is bypassed for data

2018-03-21T14:06:54Z

If L1 D$ is disabled SLC is bypassed for data and all load/store requests are sent directly to main memory. If L1 I$ is disabled SLC is NOT bypassed for instructions and all instruction requests are fetched through SLC. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin

ARC: Cache: Implement [i,d]cache_enabled() as separate functions

2018-03-21T14:06:54Z

Implement icache_enabled() and dcache_enabled() as separate functions which can be used with "inline" attribute. This is a preparation to make them always_inline. Signed-off-by: Eugeniy Paltsev Signed-off-by: Alexey Brodkin