u-boot.git/arch/arc, branch v2018.09 Unnamed repository; edit this file 'description' to name the repository. ARC: HSDK: Fix timer frequency value 2018-09-05T15:11:45+00:00 Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com 2018-09-05T11:27:10+00:00 13e57722fe7a96f23b09d3407f871f43aa3b096e CPU (and hence cpu timers) on HSDK board runs at 500MHz after preloader so fix wrong CPU frequency value in hsdk.dts Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 
CPU (and hence cpu timers) on HSDK board runs at 500MHz after
preloader so fix wrong CPU frequency value in hsdk.dts

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
ARC: Enable unaligned access in hardware if compiler uses it 2018-07-31T04:49:47+00:00 Alexey Brodkin abrodkin@synopsys.com 2018-07-29T06:47:52+00:00 8f590063ba635264303b1713c421df331743fd46 Even if ARC core might handle unaligned access to data this hardware feature by default is disabled. But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores. Which leads to quite strange and fatal run-time failures like the one below if HW is not configured properly: | hsdk# sf probe | Misaligned data access exception @ 0xbff794d4 | ECR: 0x000d0000 | RET: 0xbff794d4 | BLINK: 0xbff79644 | STAT32: 0x00000800 | GP: 0x1003e000 r25: 0xbfd58f08 | BTA: 0xbff794a4 SP: 0xbfd58cd4 FP: 0xbfd58ef0 | LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000 | r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf | r03: 0x00000000 r04: 0x00000100 r05: 0x00000000 | r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500 | r09: 0x00000000 r10: 0x00200000 r11: 0x00000000 | r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68 | r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000 | r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40 | r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000 | r24: 0xbfd59ba8 | Resetting CPU ... Now we're checking for __ARC_UNALIGNED__ define emitted by the compiler if it's going to use unaligned access and then we force-enable it in hardware too. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> 
Even if ARC core might handle unaligned access to data this
hardware feature by default is disabled.

But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores.
Which leads to quite strange and fatal run-time failures like the one
below if HW is not configured properly:
| hsdk# sf probe
| Misaligned data access exception @ 0xbff794d4
| ECR:    0x000d0000
| RET:    0xbff794d4
| BLINK:  0xbff79644
| STAT32: 0x00000800
| GP: 0x1003e000   r25: 0xbfd58f08
| BTA: 0xbff794a4  SP: 0xbfd58cd4  FP: 0xbfd58ef0
| LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000
| r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf
| r03: 0x00000000 r04: 0x00000100 r05: 0x00000000
| r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500
| r09: 0x00000000 r10: 0x00200000 r11: 0x00000000
| r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68
| r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000
| r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40
| r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000
| r24: 0xbfd59ba8
| Resetting CPU ...

Now we're checking for __ARC_UNALIGNED__ define emitted by the
compiler if it's going to use unaligned access and then we
force-enable it in hardware too.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
AXS10x: add spi flash support 2018-07-31T04:49:47+00:00 Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com 2018-06-08T15:52:14+00:00 cdfe6913c113ced9a0aa0a7dc48d037046c980e3 AXS10x boards have n25q512 spi flash IC, so add corresponding nodes to device tree and enaple corresponding options in defconfig. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> 
AXS10x boards have n25q512 spi flash IC, so add corresponding
nodes to device tree and enaple corresponding options in
defconfig.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
GPIO: CREG: improve flexibility of hsdk-creg-gpio driver 2018-07-31T04:49:47+00:00 Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com 2018-06-08T14:58:23+00:00 fe3eb7a88720fc33d92ed712c56c62cfcdffc0ca CREG GPIO is a driver for weird soc-specific output ports, which are controlled by some fields in memory mapped register. Example: 31 9 7 5 0 < bit number | | | | | [ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register ^ ^ | | write 0x2 == set output to "1" (activate) write 0x3 == set output to "0" (deactivate) As of tooday we only support fixed (hardcoded) bit per gpio line, activate / deactivatei and shift values. Fix that by read them from device tree to be able to use this driver for other boards. Remove "hsdk" prefix from compatible string as this driver can be used with different boards like HSDK, AXS101, AXS103, etc. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> 
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.

Example:

31                 9        7        5           0   < bit number
|                  |        |        |           |
[     not used     | gpio-1 | gpio-0 | <-shift-> ]   < 32 bit register
                       ^        ^
                       |        |
                write 0x2 == set output to "1" (activate)
                write 0x3 == set output to "0" (deactivate)

As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.

Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Kconfig: Sort bool, default, select and imply options 2018-07-30T11:18:48+00:00 Michal Simek michal.simek@xilinx.com 2018-07-23T13:55:15+00:00 58008cbab55688a986e40b644b9142f072285819 Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> 
Another round of sorting Kconfig entries aplhabetically.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore 2018-06-18T18:43:12+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2018-06-11T07:21:50+00:00 28b538b69dd44b5f4ea595059612115069ace96b Follow Linux commit 10b62a2f785a (".gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
Follow Linux commit 10b62a2f785a (".gitignore: move *.dtb and *.dtb.S
patterns to the top-level .gitignore").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
ARC: Add support for EM Development Kit board 2018-05-31T17:13:29+00:00 Alexey Brodkin abrodkin@synopsys.com 2018-05-28T12:27:43+00:00 2c3f9261c80e8171ba813f8baef958c1edac3f0d Synopsys DesignWare ARC EM Development Kit (ARC EMDK) is an FPGA-based development platform from Synopsys aimed to speed-up development of software for ARC EM cores and entire subsystems based on ARC EM like Data Fusion, Secure and Sensor & Control subsystems. U-Boot is supposed to be used as a primary bootloader on EMDK allowing users to easily load and start their application from micro-SD card. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> 
Synopsys DesignWare ARC EM Development Kit (ARC EMDK) is
an FPGA-based development platform from Synopsys aimed to speed-up
development of software for ARC EM cores and entire subsystems based on
ARC EM like Data Fusion, Secure and Sensor & Control subsystems.

U-Boot is supposed to be used as a primary bootloader on EMDK allowing
users to easily load and start their application from micro-SD card.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
ARC: Use elf32-bigarc in case of -EB 2018-05-31T17:13:29+00:00 Alexey Brodkin abrodkin@synopsys.com 2018-05-30T16:03:39+00:00 7af51f12bc41c38c537f2b049db21fb4554657b5 As it is stated in LD manual [1] the second entry in OUTPUT_FORMAT corresponds to "-EB" command-line option which for us is "elf32-bigarc". [1] https://sourceware.org/binutils/docs/ld/Format-Commands.html#Format-Commands Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> 
As it is stated in LD manual [1] the second entry in OUTPUT_FORMAT
corresponds to "-EB" command-line option which for us is "elf32-bigarc".

[1] https://sourceware.org/binutils/docs/ld/Format-Commands.html#Format-Commands

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
ARC: Reset: Implement weak reset_cpu() 2018-05-31T17:13:29+00:00 Alexey Brodkin abrodkin@synopsys.com 2018-05-30T09:19:54+00:00 eb5c853938cb784bbf83ab87847e94764c3cd00a This will allow for board-specific implementation of reset. Default version will just stop execution with help of BRK instruction. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> 
This will allow for board-specific implementation of reset.
Default version will just stop execution with help of BRK instruction.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
ARC: Reset: Use __builtin_arc_brk() instead of open-coded ASM 2018-05-31T17:13:29+00:00 Alexey Brodkin abrodkin@synopsys.com 2018-05-30T08:31:07+00:00 8f187142e51634d6887ef397cd6abaa7fab14b21 For quite some time we have a GCC's built-in which inserts BRK instruction so let's use it instead of simple insertion of in-line assembly. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> 
For quite some time we have a GCC's built-in which inserts BRK
instruction so let's use it instead of simple insertion of in-line
assembly.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>