<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/Makefile, branch v2018.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/Makefile?h=v2018.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/Makefile?h=v2018.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-07-10T20:55:57Z</updated>
<entry>
<title>board: arm: Add support for Broadcom BCM7445</title>
<updated>2018-07-10T20:55:57Z</updated>
<author>
<name>Thomas Fitzsimmons</name>
<email>fitzsim@fitzsim.org</email>
</author>
<published>2018-06-08T21:59:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=894c3ad27fa940beb7fdc07d01dcfe81c03d0481'/>
<id>urn:sha1:894c3ad27fa940beb7fdc07d01dcfe81c03d0481</id>
<content type='text'>
Add support for loading U-Boot on the Broadcom 7445 SoC.  This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.

Signed-off-by: Thomas Fitzsimmons &lt;fitzsim@fitzsim.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Cc: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm: Add support for Actions Semi OWL SoC family</title>
<updated>2018-07-09T19:25:15Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2018-06-14T18:08:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=97775d26c272d8c7d79afdb27112b2d6b110d786'/>
<id>urn:sha1:97775d26c272d8c7d79afdb27112b2d6b110d786</id>
<content type='text'>
This commit adds Actions Semi OWL SoC family support with S900 as the
first target SoC.

Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm: armv7m: Clean up some thumb / compiler flag options</title>
<updated>2018-05-23T17:03:42Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-08T00:46:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ea37f0b3129bb21c5d4bd11a14bfcf2537e8ec29'/>
<id>urn:sha1:ea37f0b3129bb21c5d4bd11a14bfcf2537e8ec29</id>
<content type='text'>
- The correct way to build with thumb mode is to select SYS_THUMB_BUILD
- We should be setting -march=armv7-m in arch/arm/Makefile not the
  sub-config.mk file.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: zynqmp: Add ZynqMP minimal R5 support</title>
<updated>2018-05-11T07:38:23Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-04-12T15:39:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1d6c54ecb39b8591a98f02f9b47af225ff07cd0b'/>
<id>urn:sha1:1d6c54ecb39b8591a98f02f9b47af225ff07cd0b</id>
<content type='text'>
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driver and the first Cadence Triple
Timer Counter is used for time.

This configuration with uart1 was tested on zcu100-revC.

U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200)

Model: Xilinx ZynqMP R5
DRAM:  512 MiB
WARNING: Caches not enabled
MMC:
In:    serial@ff010000
Out:   serial@ff010000
Err:   serial@ff010000
Net:   Net Initialization Skipped
No ethernet found.
ZynqMP r5&gt;

There are two ways how to run this on ZynqMP.
1. Run from ZynqMP arm64
tftpb 20000000 u-boot-r5.elf
setenv autostart no &amp;&amp; bootelf -p 20000000
cpu 4 disable &amp;&amp; cpu 4 release 10000000 lockstep
or
cpu 4 disable &amp;&amp; cpu 4 release 10000000 split

2. Load via jtag when directly to R5

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm: v7R: Add initial support</title>
<updated>2018-05-07T19:53:28Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-04-26T12:51:29Z</published>
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<id>urn:sha1:4bbd6b1d946ab6165bff8aeae6f252faa07ce85a</id>
<content type='text'>
The Cortex-R* processors are a mid-range CPUs for use in deeply-embedded,
real-time systems. It implements the ARMv7-R architecture, and includes
Thumb-2 technology for optimum code density and processing throughput.

Except for MPU(Memory Protection Unit) and few CP15 registers, most of the
features are compatible with v7 architecture. So,reuse the same armv7
folder and introduce a new config CPU_V7R in order to differentiate
from v7 based platforms.

Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A</title>
<updated>2018-05-07T19:53:24Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2018-04-26T12:51:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=acf1500138bb6b0496fe09d6bffdf8eac3d6ecab'/>
<id>urn:sha1:acf1500138bb6b0496fe09d6bffdf8eac3d6ecab</id>
<content type='text'>
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Tested-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Suggested-by: Alexander Graf &lt;agraf@suse.de&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83d290c56fab2d38cd1ab4c4cc7099559c1d5046'/>
<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: stm32: add new architecture for STM32MP family</title>
<updated>2018-03-19T20:14:21Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-03-12T09:46:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2514c2d0e6abe98157c1de83bce5c8bb69ac3a77'/>
<id>urn:sha1:2514c2d0e6abe98157c1de83bce5c8bb69ac3a77</id>
<content type='text'>
- add new arch stm32mp for STM32 MPU/Soc based on Cortex A
- support for stm32mp157 SOC
- SPL is used as first boot stage loader
- using driver model for all the drivers, even in SPL
- all security feature are deactivated (ETZC and TZC)
- reused STM32 MCU drivers when it is possible

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>imx: add i.MX8M into Kconfig</title>
<updated>2018-02-04T11:00:58Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2018-01-10T05:20:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7a7391fd7e9e3dd2db0de46a1cb33ea6902746d2'/>
<id>urn:sha1:7a7391fd7e9e3dd2db0de46a1cb33ea6902746d2</id>
<content type='text'>
Add i.MX8M into Kconfig, create a new folder mx8m
dedicated for i.MX8M.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: reorganize IMX code as other SOCs</title>
<updated>2017-07-12T08:17:44Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2017-06-29T08:16:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=552a848e4f75e224515269a84a1155c84b762bc7'/>
<id>urn:sha1:552a848e4f75e224515269a84a1155c84b762bc7</id>
<content type='text'>
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/&lt;SOC&gt;.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;

CC: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
CC: Akshay Bhat &lt;akshaybhat@timesys.com&gt;
CC: Ken Lin &lt;Ken.Lin@advantech.com.tw&gt;
CC: Marek Vasut &lt;marek.vasut@gmail.com&gt;
CC: Heiko Schocher &lt;hs@denx.de&gt;
CC: "Sébastien Szymanski" &lt;sebastien.szymanski@armadeus.com&gt;
CC: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
CC: Stefan Roese &lt;sr@denx.de&gt;
CC: Patrick Bruenn &lt;p.bruenn@beckhoff.com&gt;
CC: Troy Kisky &lt;troy.kisky@boundarydevices.com&gt;
CC: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
CC: Otavio Salvador &lt;otavio@ossystems.com.br&gt;
CC: "Eric Bénard" &lt;eric@eukrea.com&gt;
CC: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
CC: Ye Li &lt;ye.li@nxp.com&gt;
CC: Peng Fan &lt;peng.fan@nxp.com&gt;
CC: Adrian Alonso &lt;adrian.alonso@nxp.com&gt;
CC: Alison Wang &lt;b18965@freescale.com&gt;
CC: Tim Harvey &lt;tharvey@gateworks.com&gt;
CC: Martin Donnelly &lt;martin.donnelly@ge.com&gt;
CC: Marcin Niestroj &lt;m.niestroj@grinn-global.com&gt;
CC: Lukasz Majewski &lt;lukma@denx.de&gt;
CC: Adam Ford &lt;aford173@gmail.com&gt;
CC: "Albert ARIBAUD (3ADEV)" &lt;albert.aribaud@3adev.fr&gt;
CC: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
CC: Soeren Moch &lt;smoch@web.de&gt;
CC: Richard Hu &lt;richard.hu@technexion.com&gt;
CC: Wig Cheng &lt;wig.cheng@technexion.com&gt;
CC: Vanessa Maegima &lt;vanessa.maegima@nxp.com&gt;
CC: Max Krummenacher &lt;max.krummenacher@toradex.com&gt;
CC: Stefan Agner &lt;stefan.agner@toradex.com&gt;
CC: Markus Niebel &lt;Markus.Niebel@tq-group.com&gt;
CC: Breno Lima &lt;breno.lima@nxp.com&gt;
CC: Francesco Montefoschi &lt;francesco.montefoschi@udoo.org&gt;
CC: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
CC: Scott Wood &lt;oss@buserror.net&gt;
CC: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
CC: Anatolij Gustschin &lt;agust@denx.de&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
CC: "Andrew F. Davis" &lt;afd@ti.com&gt;
CC: "Łukasz Majewski" &lt;l.majewski@samsung.com&gt;
CC: Patrice Chotard &lt;patrice.chotard@st.com&gt;
CC: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
CC: Hans de Goede &lt;hdegoede@redhat.com&gt;
CC: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
CC: Stephen Warren &lt;swarren@nvidia.com&gt;
CC: Andre Przywara &lt;andre.przywara@arm.com&gt;
CC: "Álvaro Fernández Rojas" &lt;noltari@gmail.com&gt;
CC: York Sun &lt;york.sun@nxp.com&gt;
CC: Xiaoliang Yang &lt;xiaoliang.yang@nxp.com&gt;
CC: Chen-Yu Tsai &lt;wens@csie.org&gt;
CC: George McCollister &lt;george.mccollister@gmail.com&gt;
CC: Sven Ebenfeld &lt;sven.ebenfeld@gmail.com&gt;
CC: Filip Brozovic &lt;fbrozovic@gmail.com&gt;
CC: Petr Kulhavy &lt;brain@jikos.cz&gt;
CC: Eric Nelson &lt;eric@nelint.com&gt;
CC: Bai Ping &lt;ping.bai@nxp.com&gt;
CC: Anson Huang &lt;Anson.Huang@nxp.com&gt;
CC: Sanchayan Maity &lt;maitysanchayan@gmail.com&gt;
CC: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
CC: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
CC: Gary Bisson &lt;gary.bisson@boundarydevices.com&gt;
CC: Alexander Graf &lt;agraf@suse.de&gt;
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</content>
</entry>
</feed>
