u-boot.git/arch/arm/cpu/arm1136/cpu.c, branch master

arm1136/arm1176: Merge cache handling code

2015-08-13T00:47:41Z

As both cores are similar merge the cache handling code for both CPUs to arm11 directory. Signed-off-by: Alexander Stein Acked-by: Stephen Warren Tested-by: Stephen Warren [trini: Add hunk to arch/arm/cpu/arm1136/Makefile] Signed-off-by: Tom Rini

arm1136: Remove dead code

2015-08-13T00:47:40Z

Apparently lcd_panel_disable is not defined anywhere, so no config for an arm1136 board would have set CONFIG_LCD. Remove the unused code. Signed-off-by: Alexander Stein Acked-by: Stephen Warren Tested-by: Stephen Warren

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

arm1136: Fix enable_caches()

2012-11-10T11:28:22Z

enable_caches() did not enable icache if CONFIG_SYS_ICACHE_OFF was not defined but CONFIG_SYS_DCACHE_OFF was. Signed-off-by: Benoît Thébaudeau Cc: Albert Aribaud

ARM1136: Fix cache range checks

2012-07-21T21:24:25Z

bad_cache_range actually returned true if the range was OK, but it was used according to its name, which resulted in all valid dcache range invalidate/flush operations being dropped. Hence, most DMA transfers resulted in garbage data. This patch renames this function according to what it does, and it fixes the interpretation of its return value by other functions. The chosen naming is the same as for ARM926EJ-S in order to be consistent. Signed-off-by: Benoît Thébaudeau Cc: Albert Aribaud Acked-by: Stefano Babic

ARM1136: MX35: Make asm routines volatile in cache ops

2012-04-16T12:53:59Z

As well as pushed for ARM926EJS, we certainly don't want the compiler to reorganise the code for dcache flushing Fix checkpatch warnings as well. Signed-off-by: Stefano Babic CC: Marek Vasut CC: Albert Aribaud

ARM1136: add cache flush and invalidate operations

2012-04-16T12:53:58Z

Since commit 5c1ad3e6f8ae578bbe30e09652f1531e9bc22031 (net: fec_mxc: allow use with cache enabled) the FEC_MXC driver uses flush_dcache_range() and invalidate_dcache_range() functions. This driver is also configured for ARM1136 based 'flea3' and 'mx35pdk' boards which currently do not build as there are no ARM1136 specific flush_dcache_range() and invalidate_dcache_range() functions. Add various ARM1136 cache functions to fix building for 'flea3' and 'mx35pdk'. Signed-off-by: Anatolij Gustschin Signed-off-by: Stefano Babic Cc: Fabio Estevam CC: Mike Frysinger CC: Marek Vasut Acked-by: Marek Vasut

ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments

2010-06-01T11:44:09Z

The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis

arm: Move cpu/$CPU to arch/arm/cpu/$CPU

2010-04-13T07:13:24Z

Signed-off-by: Peter Tyser