u-boot.git/arch/arm/cpu/arm926ejs/cache.c, branch v2016.09

ARM: Move SYS_CACHELINE_SIZE over to Kconfig

2016-08-26T21:04:46Z

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud Cc: Marek Vasut Cc: Stefano Babic Cc: Prafulla Wadaskar Cc: Luka Perkov Cc: Stefan Roese Cc: Nagendra T S Cc: Vaibhav Hiremath Acked-by: Lokesh Vutla Cc: Steve Rae Cc: Igor Grinberg Cc: Nikita Kiryanov Cc: Stefan Agner Acked-by: Heiko Schocher Cc: Mateusz Kulikowski Cc: Peter Griffin Acked-by: Paul Kocialkowski Cc: Anatolij Gustschin Acked-by: "Pali Rohár" Cc: Adam Ford Cc: Steve Sakoman Cc: Grazvydas Ignotas Cc: Nishanth Menon Cc: Stephen Warren Cc: Robert Baldyga Cc: Minkyu Kang Cc: Thomas Weber Cc: Masahiro Yamada Cc: David Feng Cc: Alison Wang Cc: Michal Simek Cc: Simon Glass Cc: York Sun Cc: Shengzhou Liu Cc: Mingkai Hu Cc: Prabhakar Kushwaha Cc: Aneesh Bansal Cc: Saksham Jain Cc: Qianyu Gong Cc: Wang Dongsheng Cc: Alex Porosanu Cc: Hongbo Zhang Cc: tang yuantian Cc: Rajesh Bhagat Cc: Josh Wu Cc: Bo Shen Cc: Viresh Kumar Cc: Hannes Schmelzer Cc: Thomas Chou Cc: Joe Hershberger Cc: Sam Protsenko Cc: Bin Meng Cc: Christophe Ricard Cc: Anand Moon Cc: Beniamino Galvani Cc: Carlo Caione Cc: huang lin Cc: Sjoerd Simons Cc: Xu Ziyuan Cc: "jk.kernel@gmail.com" Cc: "Ariel D'Alessandro" Cc: Kever Yang Cc: Samuel Egli Cc: Chin Liang See Cc: Dinh Nguyen Cc: Hans de Goede Cc: Ian Campbell Cc: Siarhei Siamashka Cc: Boris Brezillon Cc: Andre Przywara Cc: Bernhard Nortmann Cc: Wolfgang Denk Cc: Ben Whitten Cc: Tom Warren Cc: Alexander Graf Cc: Sekhar Nori Cc: Vitaly Andrianov Cc: "Andrew F. Davis" Cc: Murali Karicheri Cc: Carlos Hernandez Cc: Ladislav Michl Cc: Ash Charles Cc: Mugunthan V N Cc: Daniel Allred Cc: Gong Qianyu Signed-off-by: Tom Rini Acked-by: Masahiro Yamada Acked-by: Chin Liang See Tested-by: Stephen Warren Acked-by: Paul Kocialkowski

arm: Move check_cache_range() into a common place

2016-07-14T22:33:09Z

This code is common, so move it into a common file. Signed-off-by: Simon Glass Reviewed-by: Marek Vasut

arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD

2015-11-10T14:03:48Z

When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD

ARM: cache: implement a default weak flush_cache() function

2015-08-13T00:47:48Z

Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu

ARM: cache: add an empty stub function for invalidate/flush dcache

2015-08-13T00:47:47Z

Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu Reviewed-by: York Sun

arm926ejs: cache: use __weak

2014-11-04T20:01:04Z

Cc: Albert Aribaud Signed-off-by: Jeroen Hofstee

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

ARM926EJS: Fix cache.c to comply with checkpatch.pl

2012-04-16T20:12:01Z

Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Albert ARIBAUD

ARM926EJS: Make asm routines volatile in cache ops

2012-04-16T20:11:57Z

We certainly don't want the compiler to reorganise the code for dcache flushing. Signed-off-by: Marek Vasut Cc: Stefano Babic Cc: Albert ARIBAUD Acked-by: Mike Frysinger Acked-by: Stefano Babic

ARM: 926ejs: use debug() for misaligned addresses

2012-04-16T12:53:59Z

Misaligned warnings are useful to debug faulty drivers. A misaligned warning is printed also when the driver is correct - use debug() instead of printf(). Signed-off-by: Stefano Babic CC: Albert Aribaud CC: Mike Frysinger CC: Marek Vasut Acked-by: Marek Vasut