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<title>u-boot.git/arch/arm/cpu/arm926ejs, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/arm926ejs?h=v2016.09</id>
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<updated>2016-08-26T21:04:46Z</updated>
<entry>
<title>ARM: Move SYS_CACHELINE_SIZE over to Kconfig</title>
<updated>2016-08-26T21:04:46Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-22T12:22:17Z</published>
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<id>urn:sha1:067716bac59716b07f1ee70d9bf6e5528289bb45</id>
<content type='text'>
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Steve Rae &lt;steve.rae@raedomain.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: "Pali Rohár" &lt;pali.rohar@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Grazvydas Ignotas &lt;notasas@gmail.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: David Feng &lt;fenghua@phytium.com.cn&gt;
Cc: Alison Wang &lt;b18965@freescale.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Cc: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Cc: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.com&gt;
Cc: Qianyu Gong &lt;qianyu.gong@nxp.com&gt;
Cc: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Cc: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Cc: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Cc: tang yuantian &lt;Yuantian.Tang@freescale.com&gt;
Cc: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Cc: Josh Wu &lt;josh.wu@atmel.com&gt;
Cc: Bo Shen &lt;voice.shen@atmel.com&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Christophe Ricard &lt;christophe-h.ricard@st.com&gt;
Cc: Anand Moon &lt;linux.amoon@gmail.com&gt;
Cc: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Cc: Carlo Caione &lt;carlo@endlessm.com&gt;
Cc: huang lin &lt;hl@rock-chips.com&gt;
Cc: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Cc: Xu Ziyuan &lt;xzy.xu@rock-chips.com&gt;
Cc: "jk.kernel@gmail.com" &lt;jk.kernel@gmail.com&gt;
Cc: "Ariel D'Alessandro" &lt;ariel@vanguardiasur.com.ar&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Cc: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Cc: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Andre Przywara &lt;andre.przywara@arm.com&gt;
Cc: Bernhard Nortmann &lt;bernhard.nortmann@web.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Alexander Graf &lt;agraf@suse.de&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Cc: "Andrew F. Davis" &lt;afd@ti.com&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Carlos Hernandez &lt;ceh@ti.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Cc: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Chin Liang See &lt;clsee@altera.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</content>
</entry>
<entry>
<title>arm: Move check_cache_range() into a common place</title>
<updated>2016-07-14T22:33:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-06-20T01:43:01Z</published>
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<id>urn:sha1:397b5697ad242408979a00dda14138aa1439f52b</id>
<content type='text'>
This code is common, so move it into a common file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-atmel</title>
<updated>2016-06-13T12:50:58Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-06-13T12:50:58Z</published>
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<id>urn:sha1:fd9102dafea5c6959401d0dbc5293a56d2261878</id>
<content type='text'>
</content>
</entry>
<entry>
<title>arm: Allow skipping of low-level init with I-cache on</title>
<updated>2016-06-12T21:49:38Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-05T13:28:06Z</published>
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<id>urn:sha1:b5bd09820c79dc92b3e5fb5be4b47ce22c731443</id>
<content type='text'>
At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
lowlevel_init(). This means that the instruction cache is not enabled and
the board runs very slowly.

What is really needed in many cases is to skip the call to lowlevel_init()
but still perform CP15 init. Add an option to handle this.

Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Andreas Bießmann &lt;andreas@biessmann.org&gt;
</content>
</entry>
<entry>
<title>arm: mxs: Remove misleading comments</title>
<updated>2016-06-07T16:23:51Z</updated>
<author>
<name>Michael Heimpold</name>
<email>michael.heimpold@i2se.com</email>
</author>
<published>2016-06-06T12:26:39Z</published>
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<id>urn:sha1:d2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4</id>
<content type='text'>
Both comments look like being copy &amp; paste errors.

Signed-off-by: Michael Heimpold &lt;michael.heimpold@i2se.com&gt;
Cc: Peng Fan &lt;Peng.Fan@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>mx27: 16-bit wide watchdog registers</title>
<updated>2016-03-25T13:03:28Z</updated>
<author>
<name>Leonid Iziumtsev</name>
<email>leonid.iziumtsev@se.atlascopco.com</email>
</author>
<published>2016-03-20T13:10:55Z</published>
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<id>urn:sha1:f7440928e609734f6d24d6769927539762270e1e</id>
<content type='text'>
Make the watchdog registers 16-bit wide, as they are according to TRM.

Signed-off-by: Leonid Iziumtsev &lt;leonid.iziumtsev@se.atlascopco.com&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>ARM: Various: Future-proof serial platdata</title>
<updated>2016-03-14T23:18:48Z</updated>
<author>
<name>Adam Ford</name>
<email>aford173@gmail.com</email>
</author>
<published>2016-03-08T03:08:49Z</published>
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<id>urn:sha1:2f6ed3b89a1760ffa73123fb266de3d56eb5d88e</id>
<content type='text'>
A few boards still use ns16550_platdata structures, but assume the structure
is going to be in a specific order. By explicitly naming each entry,
this should also help 'future-proof' in the event the structure changes.

Tested on the Logic PD Torpedo + Wireless.

I only changed a handful of devices that used the same syntax as the Logic
board.  Appologies if I missed one or stepped on toes.  Thanks to Derald Woods
and Alexander Graf.

Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;

V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c

V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c

V4: Fix subject heading

V3: Remove  reg_offset out in all the structs. It was reverted out, and and if
it did exist, it would get initialized to 0 by default.

V2: I hastily copy-pasted the boards without looking at the UART number.
This addresses 3 boards that use UART3 and not UART1.
Reviewed-by: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ARM: start.S: fix typo</title>
<updated>2016-02-29T19:49:35Z</updated>
<author>
<name>Yuichiro Goto</name>
<email>goto.yuichiro@espark.co.jp</email>
</author>
<published>2016-02-25T01:23:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba10b852fe3a5d6188dfa43cced4bfbaf3515df1'/>
<id>urn:sha1:ba10b852fe3a5d6188dfa43cced4bfbaf3515df1</id>
<content type='text'>
Fix typo in comment about position of 'A' bit in several start.S.

Signed-off-by: Yuichiro Goto &lt;goto.yuichiro@espark.co.jp&gt;
</content>
</entry>
<entry>
<title>Use correct spelling of "U-Boot"</title>
<updated>2016-02-06T11:00:59Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-06T03:30:11Z</published>
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<id>urn:sha1:a187559e3d586891c917279044c5386d1b2adc6e</id>
<content type='text'>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>arm: lpc32xx: switch SPL builds to driver model</title>
<updated>2016-01-14T02:05:22Z</updated>
<author>
<name>Vladimir Zapolskiy</name>
<email>vz@mleia.com</email>
</author>
<published>2015-12-19T21:29:26Z</published>
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<id>urn:sha1:1222305b55e2809ee9f7945ecc1f776e08943728</id>
<content type='text'>
For NXP LPC32xx boards the change enables SPL_DM option, this allows
to use any driver model UART driver in SPL images, hence a restriction
on HSUART in SPL image is removed and well as definitions for non-DM
NS16550 driver, its DM version is used instead.

Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE
for LPC32xx boards.

The change adds about 5KB to the resulting SPL image (for devkit3250
board SPL image is increased from 10672 to 15608 bytes).

Signed-off-by: Vladimir Zapolskiy &lt;vz@mleia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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