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<title>u-boot.git/arch/arm/cpu/armv7/Kconfig, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv7/Kconfig?h=master</id>
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<updated>2025-11-11T17:54:56Z</updated>
<entry>
<title>ARM: Fix HAS_ARMV7_SECURE_BASE help text</title>
<updated>2025-11-11T17:54:56Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2025-11-09T18:45:41Z</published>
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<id>urn:sha1:aa99fc54ed6177f25a6d987dfc8def813784de50</id>
<content type='text'>
Drop the 'a' from 'ahardware', no functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>ARM: stm32: Fix SYSRAM size on STM32MP13xx</title>
<updated>2025-06-11T07:42:55Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@mailbox.org</email>
</author>
<published>2025-05-12T16:44:04Z</published>
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<id>urn:sha1:380d6f8c1951c7a3bc9628ffdb70e7fcf89b61e8</id>
<content type='text'>
The STM32MP13xx has only 128 kiB of SYSRAM starting at address 0x2ffe0000 .
The STM32MP15xx has 256 kiB of SYSRAM starting at address 0x2ffc0000 . Make
sure both SoCs configure ARMV7_SECURE_BASE correctly . Define the SYSRAM
base in stm32.h to be consistent with the STM32MP15xx macro.

Signed-off-by: Marek Vasut &lt;marek.vasut@mailbox.org&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>sunxi: psci: implement PSCI on R528</title>
<updated>2023-10-22T22:41:52Z</updated>
<author>
<name>Sam Edwards</name>
<email>cfsworks@gmail.com</email>
</author>
<published>2023-10-12T01:47:56Z</published>
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<id>urn:sha1:352ba256daafcd9b11d8196e662168558033b091</id>
<content type='text'>
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.

Signed-off-by: Sam Edwards &lt;CFSworks@gmail.com&gt;
Tested-by: Maksim Kiselev &lt;bigunclemax@gmail.com&gt;
Tested-by: Kevin Amadiva &lt;kevin.amadiva@mec.at&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>ARM: psci: move GIC address override to Kconfig</title>
<updated>2023-10-11T17:22:32Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2023-10-01T22:52:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3d5e52bd97f747694fac9259b4d2879a48256a7b'/>
<id>urn:sha1:3d5e52bd97f747694fac9259b4d2879a48256a7b</id>
<content type='text'>
As the code to switch an ARM core from secure to the non-secure state
needs to know the base address of the Generic Interrupt Controller
(GIC), we read an Arm Cortex defined system register that is supposed to
hold that base address. However there are SoCs out there that get this
wrong, and this CBAR register either reads as 0 or points to the wrong
address. To accommodate those systems, so far we use a macro defined in
some platform specific header files, for affected boards.

To simplify future extensions, replace that macro with a Kconfig variable
that holds this override address, and define a default value for SoCs
that need it.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Sam Edwards &lt;CFSworks@gmail.com&gt;
</content>
</entry>
<entry>
<title>global: Use proper project name U-Boot</title>
<updated>2023-06-12T11:24:31Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2023-05-17T07:17:16Z</published>
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<id>urn:sha1:1be82afa807cc3cfacab29e3de0975d2cd99fa5d</id>
<content type='text'>
Use proper project name in comments, Kconfig, readmes.

Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Acked-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Qu Wenruo &lt;wqu@suse.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
</content>
</entry>
<entry>
<title>ARM: armv7: add non-SPL enable for Cortex SMPEN</title>
<updated>2023-05-13T02:01:30Z</updated>
<author>
<name>Ralph Siemsen</name>
<email>ralph.siemsen@linaro.org</email>
</author>
<published>2023-05-13T01:36:49Z</published>
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<id>urn:sha1:54232a705729f26bf569ee6d314f96b7acdb485e</id>
<content type='text'>
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_ARMV7_SECURE_BASE et al to Kconfig</title>
<updated>2022-03-18T12:43:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-03-11T14:11:56Z</published>
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<id>urn:sha1:0da35fa8d67415c7d595f6a74952905decc2a911</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_ARMV7_SECURE_BASE
   CONFIG_ARMV7_SECURE_MAX_SIZE
   CONFIG_ARMV7_SECURE_RESERVE_SIZE

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>sunxi: move Cortex SMPEN setting into start.S</title>
<updated>2022-02-04T00:09:36Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-01-23T00:27:19Z</published>
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<id>urn:sha1:2564fce7eea33f8828e132d966236e9621bea3cb</id>
<content type='text'>
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.

This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR
very early in start.S, and moves sunxi boards over to use that instead
of the custom code we had in our board.c file (where it was called
technically too late).

In practice we got away with this so far, because at this point all the
other cores were still in reset, so any broadcasting would have been
ignored anyway. But it is architecturally cleaner to do it early, and
we move a core specific piece of code out of board.c.

This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few
years back, and moves the respective logic into the new Kconfig entry.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>ARM: add Kconfig option for PSCI 0.1</title>
<updated>2020-08-05T12:18:34Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2020-07-31T18:56:45Z</published>
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<id>urn:sha1:7f772fbcc04b8f70a70b79f869b03c2897ba0651</id>
<content type='text'>
We still have some platforms that only implements functionalities in
PSCI 0.1 (e.g. Allwinner ARMv7 SoCs).

Add a Kconfig option for exporting only PSCI 0.1. The code to export
PSCI 0.1 is still available and gets activated by this patch.

In addition, default ARCH_SUNXI U-Boot PSCI implementation to export
PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core
ARMv7 SoCs.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
</content>
</entry>
<entry>
<title>Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig</title>
<updated>2020-07-17T12:51:29Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2020-06-17T16:19:18Z</published>
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<id>urn:sha1:b4d14bc81ad580000277deae5d51e3e3ef09875f</id>
<content type='text'>
This converts the following to Kconfig:
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_PSCI_0_2

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
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