u-boot.git/arch/arm/cpu/armv7/cache_v7.c, branch v2012.04

armv7: cache: remove flush on un-aligned invalidate

2011-09-04T09:36:16Z

Remove the flush of boundary cache-lines done as part of invalidate on a non cache-line boundary aligned buffer Also, print a warning when this situation is recognized. Signed-off-by: Aneesh V

armv7: stronger barrier for cache-maintenance operations

2011-09-04T09:36:16Z

set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V

armv7: cache maintenance operations for armv7

2011-07-04T08:55:25Z

- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V