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<title>u-boot.git/arch/arm/cpu/armv7/cpu.c, branch v2011.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv7/cpu.c?h=v2011.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv7/cpu.c?h=v2011.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2011-08-03T10:49:20Z</updated>
<entry>
<title>omap: add MMC and FAT support to SPL</title>
<updated>2011-08-03T10:49:20Z</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-07-21T13:10:27Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8cf686e19b6922a2a6b401af188dfb83414c3c04'/>
<id>urn:sha1:8cf686e19b6922a2a6b401af188dfb83414c3c04</id>
<content type='text'>
- Add MMC raw and FAT mode boot support for OMAP
- Provide a means by which parameters passed by ROM-code
  can be saved in u-boot.
- Save boot mode related information passed by OMAP4 ROM-code
  and use it to determine where to load the u-boot from
- Assumes that the image has a mkimage header. Gets the
  payload size and load address from this header. If the
  header is not detected assume u-boot.bin as payload

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
Signed-off-by: Sandeep Paulraj &lt;s-paulraj@ti.com&gt;
</content>
</entry>
<entry>
<title>armv7: integrate cache maintenance support</title>
<updated>2011-07-04T08:55:25Z</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-06-16T23:30:49Z</published>
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<id>urn:sha1:c2dd0d45540397704de9b13287417d21049d34c6</id>
<content type='text'>
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
	- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
	- Make changes according to the new framework

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
</content>
</entry>
<entry>
<title>armv7: rename cache related CONFIG flags</title>
<updated>2011-07-04T08:55:25Z</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-06-16T23:30:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e47f2db5371047eb9bcd115fee084e6a8a92a239'/>
<id>urn:sha1:e47f2db5371047eb9bcd115fee084e6a8a92a239</id>
<content type='text'>
Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:

CONFIG_L2_OFF	     -&gt; CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -&gt; CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -&gt; CONFIG_SYS_DCACHE_OFF

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
V2:
 * Changed CONFIG_L2_OFF -&gt; CONFIG_SYS_NO_L2CACHE
V4:
 * Changed all three flags to the final names suggested as above
   and accordingly changed the commit message
</content>
</entry>
<entry>
<title>ARM: Rename arch/arm/cpu/arm_cortexa8 to armv7</title>
<updated>2010-07-05T23:59:55Z</updated>
<author>
<name>Steve Sakoman</name>
<email>steve@sakoman.com</email>
</author>
<published>2010-06-18T04:50:01Z</published>
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<id>urn:sha1:f56348af5d255f6dc2a8bcd7d798ab5edf8fba25</id>
<content type='text'>
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9

Cortex A8 and A9 both belong to the armv7 architecture, hence the name change.

The two architectures are similar enough that substantial code can be shared.

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
Signed-off-by: Steve Sakoman &lt;steve@sakoman.com&gt;
Signed-off-by: Sandeep Paulraj &lt;s-paulraj@ti.com&gt;
</content>
</entry>
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