u-boot.git/arch/arm/cpu/armv7/mx5/lowlevel_init.S, branch master

imx: reorganize IMX code as other SOCs

2017-07-12T08:17:44+00:00

Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic 

CC: Fabio Estevam 
CC: Akshay Bhat 
CC: Ken Lin 
CC: Marek Vasut 
CC: Heiko Schocher 
CC: "Sébastien Szymanski" 
CC: Christian Gmeiner 
CC: Stefan Roese 
CC: Patrick Bruenn 
CC: Troy Kisky 
CC: Nikita Kiryanov 
CC: Otavio Salvador 
CC: "Eric Bénard" 
CC: Jagan Teki 
CC: Ye Li 
CC: Peng Fan 
CC: Adrian Alonso 
CC: Alison Wang 
CC: Tim Harvey 
CC: Martin Donnelly 
CC: Marcin Niestroj 
CC: Lukasz Majewski 
CC: Adam Ford 
CC: "Albert ARIBAUD (3ADEV)" 
CC: Boris Brezillon 
CC: Soeren Moch 
CC: Richard Hu 
CC: Wig Cheng 
CC: Vanessa Maegima 
CC: Max Krummenacher 
CC: Stefan Agner 
CC: Markus Niebel 
CC: Breno Lima 
CC: Francesco Montefoschi 
CC: Jaehoon Chung 
CC: Scott Wood 
CC: Joe Hershberger 
CC: Anatolij Gustschin 
CC: Simon Glass 
CC: "Andrew F. Davis" 
CC: "Łukasz Majewski" 
CC: Patrice Chotard 
CC: Nobuhiro Iwamatsu 
CC: Hans de Goede 
CC: Masahiro Yamada 
CC: Stephen Warren 
CC: Andre Przywara 
CC: "Álvaro Fernández Rojas" 
CC: York Sun 
CC: Xiaoliang Yang 
CC: Chen-Yu Tsai 
CC: George McCollister 
CC: Sven Ebenfeld 
CC: Filip Brozovic 
CC: Petr Kulhavy 
CC: Eric Nelson 
CC: Bai Ping 
CC: Anson Huang 
CC: Sanchayan Maity 
CC: Lokesh Vutla 
CC: Patrick Delaunay 
CC: Gary Bisson 
CC: Alexander Graf 
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam 
Reviewed-by: Christian Gmeiner

mx5: lowlevel_init: Remove unused macro

2013-10-31T16:54:03+00:00

setup_wdog macro is not used anywhere, so just remove it.

Signed-off-by: Fabio Estevam 
Acked-by: Stefano Babic

ARM: mx5: Enable L2 cache

2013-10-31T16:54:03+00:00

Enable L2 cache for improving the system performance.

Signed-off-by: Fabio Estevam

Coding Style cleanup: replace leading SPACEs by TABs

2013-10-14T20:06:54+00:00

Signed-off-by: Wolfgang Denk 
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38+00:00

Signed-off-by: Wolfgang Denk 
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini

imx: mx5: lowlevel_init: Simplify code

2013-04-12T05:55:04+00:00

Don't use several instructions to build constant values.

Signed-off-by: Benoît Thébaudeau 
Acked-by: Stefano Babic

mx5: Mark lowlevel_init board-specific code

2012-11-19T07:56:27+00:00

The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.

Signed-off-by: Benoît Thébaudeau 
Cc: Stefano Babic 
Cc: Matt Sealey 
Acked-by: Stefano Babic

mx5: Add workaround for ARM erratum ID 468414

2012-10-17T16:25:12+00:00

Add the software workaround for ARM erratum ID 468414.

According to mx53/mx51 errata document:

"ENGcm11133 - ARM: NEON load data can be incorrectly forwarded to a
subsequent request

Description:

Under very specific set of conditions, data from a Neon load request can be incorrectly forwarded
to a subsequent, unrelated memory request.
The conditions are as follows:
• Neon loads and stores must be in use
• Neon L1 caching must be disabled
• Trustzone must be configured and in use
• The secure memory address space and the non-secure memory address space both use the same
physical addresses, either as an alias or the same memory location or for separate memory
locations
The issue is reported by ARM, erratum ID 468414, Category 2"

Signed-off-by: Fabio Estevam

mx5: lowlevel_init.S: Fix PLL settings for mx53

2012-10-17T16:09:34+00:00

Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.

Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.

Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.

Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.

Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.

Signed-off-by: Fabio Estevam

mx5: lowlevel_init.S: Split init_clock macro

2012-10-17T16:09:34+00:00

init_clock is currently shared between mx51 and mx53 and it contains lots of
ifdef's which makes it really hard to follow the code.

Split the init_clock between mx51 and mx53 to allow easier readability.

No functional changes are made.

Signed-off-by: Fabio Estevam