u-boot.git/arch/arm/cpu/armv7/mx6/clock.c, branch v2016.03

imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation

2016-02-02T20:25:50Z

The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li Reviewed-by: Stefano Babic

imx: mx6sx: Fix issue in LCDIF clock enablement

2016-02-02T20:25:05Z

Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always enter the -EINVAL return. Signed-off-by: Ye Li Reviewed-by: Stefano Babic

imx: mx6ul/sx: fix mmdc_ch0 clk calculation

2016-01-24T11:13:21Z

Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan Cc: Stefano Babic

imx: mx6: add missing return value

2015-12-07T13:59:25Z

cc: Peng Fan Signed-off-by: Jeroen Hofstee Reviewed-by: Peng Fan Reviewed-by: Stefano Babic

mx6: clock: Modify GPMI clock to support mx6sx

2015-11-25T10:40:04Z

On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li

imx: mx6: add clock api for lcdif

2015-11-12T16:40:53Z

Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video. The three API can be used to configure lcdif related clock when CONFIG_VIDEO_MXS enabled. Signed-off-by: Peng Fan Cc: Stefano Babic

imx: mx6: correct enable_fec_anatop_clock

2015-10-02T08:42:31Z

We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, otherwise we may overridden configuration before enable_fec_anatop_clock. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Cc: Fabio Estevam

imx: clock support enet2 anatop clock support

2015-09-02T13:29:14Z

To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan Cc: Heiko Schocher Cc: Fabio Estevam Cc: Stefan Roese Cc: Nikolaos Pasaloukos Cc: Stefano Babic Reviewed-by: Stefan Roese

imx:mx6ul add clock support

2015-08-02T09:05:07Z

1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li Signed-off-by: Peng Fan

imx: mx6qp Enable PRG clock for IPU

2015-08-02T08:46:34Z

The i.MX6DQP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan Signed-off-by: Brown Oliver Signed-off-by: Ye.Li Reviewed-by: Fabio Estevam Acked-by: Stefano Babic