u-boot.git/arch/arm/cpu/armv7/mx6/clock.c, branch v2016.09

mx6: clock: Fix the logic for reading axi_alt_sel

2016-07-20T16:26:37Z

According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam

imx6: clock: typo fix

2016-07-12T15:58:50Z

Typo fix, "PPL2 -> PLL2" Signed-off-by: Peng Fan Cc: Stefano Babic

imx: mx6: use simpler runtime cpu dection macros

2016-05-24T12:59:56Z

Use simpler runtime cpu dection macros. i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl. Signed-off-by: Peng Fan Cc: Stefano Babic

imx: mx6: support i.MX6SOLO when enable/disable_ldb_di_clock_sources

2016-05-24T12:59:56Z

i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support when enable/disable_ldb_di_clock_sources. Signed-off-by: Peng Fan Cc: Stefano Babic

imx: mx6: Fix procedure to switch the parent of LDB_DI_CLK

2016-04-19T14:05:12Z

Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. This patch was ported from the 3.10.17 NXP kernel http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d NXP errata number: ERR009219, EB821 Signed-off-by: Akshay Bhat Cc: Stefano Babic Cc: Fabio Estevam

imx: print ARM clock for clocks command

2016-03-25T12:57:19Z

Default print ARM clock for clocks command. Test on i.MX6UL 14x14 evk board: " => clocks PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz ARM 396000 kHz " Signed-off-by: Peng Fan Cc: Stefano Babic

imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation

2016-02-02T20:25:50Z

The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li Reviewed-by: Stefano Babic

imx: mx6sx: Fix issue in LCDIF clock enablement

2016-02-02T20:25:05Z

Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always enter the -EINVAL return. Signed-off-by: Ye Li Reviewed-by: Stefano Babic

imx: mx6ul/sx: fix mmdc_ch0 clk calculation

2016-01-24T11:13:21Z

Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan Cc: Stefano Babic

imx: mx6: add missing return value

2015-12-07T13:59:25Z

cc: Peng Fan Signed-off-by: Jeroen Hofstee Reviewed-by: Peng Fan Reviewed-by: Stefano Babic