u-boot.git/arch/arm/cpu/armv7/mx6, branch v2012.07

No need to define CONFIG_ARCH_CPU_INIT.

2012-07-07T12:07:44Z

All mx6 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam Acked-by: Marek Vasut

i.MX6: add enable_sata_clock()

2012-05-15T06:31:33Z

Signed-off-by: Eric Nelson Signed-off-by: Stefano Babic

i.MX6: Add ANATOP regulator init

2012-05-15T06:31:33Z

Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter. Note: This should be but can't be done in the DCD. The bootloader prevents access to the ANATOP registers. Signed-off-by: Dirk Behme CC: Jason Chen CC: Jason Liu CC: Ranjani Vaidyanathan CC: Stefano Babic CC: Fabio Estevam

imx-common: Factor out get_ahb_clk()

2012-05-15T06:31:32Z

get_ahb_clk() is a common function between mx5 and mx6. Place it into imx-common directory. Cc: Dirk Behme Signed-off-by: Fabio Estevam

armv7: add appropriate headers for assembly functions

2012-05-15T06:31:26Z

Use ENTRY and ENDPROC with assembly functions to ensure necessary assembler directives for all functions. Signed-off-by: Aneesh V Acked-by: Mike Frysinger

i.MX6: implement enable_caches()

2012-04-16T12:53:58Z

disabled by default until drivers are fixed Signed-off-by: Eric Nelson Acked-by: Marek Vasut

mx6: Read silicon revision from register

2012-03-27T07:41:16Z

Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam Acked-by: Stefano Babic Acked-by: Jason Liu

usb/ehci: Add USB support for the MX6Q

2012-03-26T21:09:23Z

Currently, only USB Host 1 is supported. Cc: Remy Bohmer Signed-off-by: Wolfgang Grandegger

imx: mx6q: add aipstz init for off platform periph

2012-01-16T07:40:10Z

Init peripheral access control register of AIPSTZ OPACRx: Buffer Writes(BW): 0 -> not bufferable, Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses. Write Protect(WP): 0 -> allows write accesses. Trusted Protect(TP): 0 -> allows unstrusted master Signed-off-by: Jason Liu Cc: Stefano Babic

i.mx6:imx6q: allign MAC address with burned-in ordering

2012-01-16T07:40:09Z

For the i.mx6q, the burned-in MAC address will be the following odering, fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5] fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4] fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3] fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2] fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1] fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0] This patch also fix the error caculation for the fuse bank[0] address Signed-off-by: Jason Liu Cc: Stefano Babic