<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/cpu/armv7/mx6, branch v2016.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv7/mx6?h=v2016.05</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv7/mx6?h=v2016.05'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-04-19T14:37:36Z</updated>
<entry>
<title>Add initial support for Technexion's PICO-IMX6UL-EMMC board</title>
<updated>2016-04-19T14:37:36Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2016-04-18T12:56:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=69cc7dbf1f62492788ab810db7d8444a623c23c2'/>
<id>urn:sha1:69cc7dbf1f62492788ab810db7d8444a623c23c2</id>
<content type='text'>
Add support for Technexion's PICO-IMX6UL-EMMC board.

For information about this board, please visit:
http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc

Signed-off-by: Richard Hu &lt;richard.hu@technexion.com&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: mx6: Fix procedure to switch the parent of LDB_DI_CLK</title>
<updated>2016-04-19T14:05:12Z</updated>
<author>
<name>Akshay Bhat</name>
<email>akshay.bhat@timesys.com</email>
</author>
<published>2016-04-12T22:13:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=90d7cc42b31251548b3cfb0e65a266020159784d'/>
<id>urn:sha1:90d7cc42b31251548b3cfb0e65a266020159784d</id>
<content type='text'>
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.

To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.

This patch was ported from the 3.10.17 NXP kernel
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&amp;id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d

NXP errata number: ERR009219, EB821

Signed-off-by: Akshay Bhat &lt;akshay.bhat@timesys.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>imx: mx6sx: move MX6SX to Kconfig entry</title>
<updated>2016-03-26T13:16:12Z</updated>
<author>
<name>Peng Fan</name>
<email>van.freenix@gmail.com</email>
</author>
<published>2016-03-03T07:56:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9131c18cfa23c1eae8d77b6fcfa2f5e16698d949'/>
<id>urn:sha1:9131c18cfa23c1eae8d77b6fcfa2f5e16698d949</id>
<content type='text'>
If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX6SX" to boards using i.MX6 SoloX.

Signed-off-by: Peng Fan &lt;van.freenix@gmail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: mx6: Add CCV xPress board support</title>
<updated>2016-03-26T13:16:12Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2016-02-10T10:41:26Z</published>
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<id>urn:sha1:a7f480d92df8a7e525a4b619b09f40f73222647f</id>
<content type='text'>
This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:

- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB

This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: imx6: Switch DDR3 calibration to wait_for_bit()</title>
<updated>2016-03-25T13:01:29Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-03-02T13:49:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b10d93ee9e56ff1848aaf739d19dd9bd43af4ce9'/>
<id>urn:sha1:b10d93ee9e56ff1848aaf739d19dd9bd43af4ce9</id>
<content type='text'>
Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit()
to generic implementation of wait_for_bit().

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Reviewed-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: print ARM clock for clocks command</title>
<updated>2016-03-25T12:57:19Z</updated>
<author>
<name>Peng Fan</name>
<email>van.freenix@gmail.com</email>
</author>
<published>2016-03-09T08:44:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d78e7f2794f7ae380c0c25027b7872d4f4cca322'/>
<id>urn:sha1:d78e7f2794f7ae380c0c25027b7872d4f4cca322</id>
<content type='text'>
Default print ARM clock for clocks command.
Test on i.MX6UL 14x14 evk board:
"
=&gt; clocks
PLL_SYS         792 MHz
PLL_BUS         528 MHz
PLL_OTG         480 MHz
PLL_NET          50 MHz

ARM          396000 kHz
"

Signed-off-by: Peng Fan &lt;van.freenix@gmail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: mx6ul configure the PMIC_STBY_REQ pin as open drain</title>
<updated>2016-03-25T12:56:55Z</updated>
<author>
<name>Peng Fan</name>
<email>van.freenix@gmail.com</email>
</author>
<published>2016-03-09T08:44:37Z</published>
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<id>urn:sha1:7082d879164fe7af549ca911a7b675ce698186e1</id>
<content type='text'>
Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.

Signed-off-by: Peng Fan &lt;van.freenix@gmail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: mx6ul: skip setting ahb rate</title>
<updated>2016-03-25T12:56:40Z</updated>
<author>
<name>Peng Fan</name>
<email>van.freenix@gmail.com</email>
</author>
<published>2016-03-09T08:44:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e4dc3fc0681bd205b1db6336b0ea3849b5c683e9'/>
<id>urn:sha1:e4dc3fc0681bd205b1db6336b0ea3849b5c683e9</id>
<content type='text'>
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.

Signed-off-by: Peng Fan &lt;van.freenix@gmail.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask</title>
<updated>2016-03-25T12:55:54Z</updated>
<author>
<name>Ye Li</name>
<email>ye.li@nxp.com</email>
</author>
<published>2016-03-09T08:13:48Z</published>
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<id>urn:sha1:b777789ebd193587a8e4700dce656523df821370</id>
<content type='text'>
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li &lt;ye.li@nxp.com&gt;
Signed-off-by: Peng Fan &lt;van.freenix@gmail.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'next'</title>
<updated>2016-03-20T21:04:29Z</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2016-03-20T21:04:29Z</published>
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<id>urn:sha1:312a6c016a2d81aa3fbc605f5c0c315b6a4e3464</id>
<content type='text'>
</content>
</entry>
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