imx: imx7d: fix ahb clock mux 1

2016-05-17T15:52:20Z

The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner

imx: imx7d: clock control module support

2015-09-13T08:11:53Z

* Add Clock control module (CCM) support * iMX7D SoC introduces 3 main clock sysmtem abstraction for clock root frequency generation denominated clock slices. Core clock slice: hihg speed clock for ARM core Bus clock slice: for bus clocks IP clock slice: Peripheral clocks * At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET In u-boot, we have to: - Configure PFD3- PFD7 for freq we needed in u-boot - Set clock root for peripherals (ip channel) Signed-off-by: Adrian Alonso Signed-off-by: Peng Fan Signed-off-by: Ye.Li

u-boot.git/arch/arm/cpu/armv7/mx7/clock_slice.c, branch v2016.09

imx: imx7d: fix ahb clock mux 1

imx: imx7d: clock control module support