u-boot.git/arch/arm/cpu/armv7/omap3/cache.S, branch master Unnamed repository; edit this file 'description' to name the repository. armv7: adapt omap3 to the new cache maintenance framework 2011-07-04T08:55:25+00:00 Aneesh V aneesh@ti.com 2011-06-16T23:30:53+00:00 45bf05854bc94ed8bae9e9114292895b990327ea adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com> 
adapt omap3 to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>
ARM V7 (OMAP): add data cache support, test on Beagle board 2010-09-19T17:29:51+00:00 Heiko Schocher hs@denx.de 2010-09-17T11:10:31+00:00 95c6f6d34d4ff23f4d005488d84682eec5fa9ec8 Add data cache support for ARM V7 systems. Used cache flush functions from linux:arch/arm/mm/cache-v7.S developed from Catalin Marinas. Enable "cache" command on Beagle board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- Beagle (Cortex A8) 116s 106s 30.3s = x 3.8 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- Beagle (Cortex A8) 1.84s 1.64s 0.12s = x 15.3 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Ben Gardiner<bengardiner@nanometrics.ca> 
Add data cache support for ARM V7 systems. Used cache flush
functions from linux:arch/arm/mm/cache-v7.S developed from
Catalin Marinas.

Enable "cache" command on Beagle board and test performance.

    Test 1: Loading 127 MB of data from NAND flash into RAM:

    Instr. Cache	off	on	on
      Data Cache	off	off	on
    --------------------------------------------------
    Beagle (Cortex A8)	116s	106s	30.3s	= x 3.8

    Test 2: uncompressing a gzipped image from RAM to RAM
            (size compressed: 6.5 MiB, uncompressed: 35 MiB):

    Instr. Cache	off	on	on
      Data Cache	off	off	on
    --------------------------------------------------
    Beagle (Cortex A8)	1.84s	1.64s	0.12s	= x 15.3

Portions of this work were supported by funding from
the CE Linux Forum.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Ben Gardiner<bengardiner@nanometrics.ca>
Prepare v2010.09-rc1 2010-09-09T22:16:19+00:00 Wolfgang Denk wd@denx.de 2010-09-09T22:16:19+00:00 2d941de9d5c7ba00dc19787dfa0aac2949fd00fb Coding style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de> 
Coding style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>
ARMV7: OMAP3: Apply Cortex-A8 errata workarounds only on affected revisions 2010-09-08T18:51:13+00:00 Mans Rullgard mans@mansr.com 2010-04-14T15:10:28+00:00 0c0a0e07811965188d5f64cdbc186331c0598fa6 The workarounds for errata 621766 and 725233 should only be applied on affected Cortex-A8 revisions. Recent chips use r3px cores where these have been fixed. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
The workarounds for errata 621766 and 725233 should only be applied
on affected Cortex-A8 revisions.  Recent chips use r3px cores where
these have been fixed.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
ARMV7: OMAP3: Convert setup_auxcr() to pure asm 2010-09-08T18:51:09+00:00 Mans Rullgard mans@mansr.com 2010-04-14T14:49:57+00:00 096ca838b514be0a20e62500413e42f0a2bb7481 This function consists entirely of inline asm statements, so writing it directly in a .S file is simpler. Additionally, the inline asm is not safe as is, since registers are not guaranteed to be preserved between asm() statements. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
This function consists entirely of inline asm statements, so writing
it directly in a .S file is simpler. Additionally, the inline asm is
not safe as is, since registers are not guaranteed to be preserved
between asm() statements.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
ARMV7: OMAP3: Fix and clean up L2 cache enable/disable functions 2010-09-08T18:51:04+00:00 Mans Rullgard mans@mansr.com 2010-04-14T10:08:00+00:00 29844707469854d9fab181edd6abe2f25fb5d208 On OMAP34xx ES1.0, the L2 enable bit can only be set in secure mode, so an SMC call to the ROM monitor is required. On later versions, and on newer devices, this bit is banked and we can set it directly. The code checked only the ES revision of the chip, and hence incorrectly used the ROM call on ES1.0 versions of other devices. This patch adds a check for chip family as well as revision, and also removes some code duplication between the enable and disable functions. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
On OMAP34xx ES1.0, the L2 enable bit can only be set in secure mode,
so an SMC call to the ROM monitor is required.  On later versions,
and on newer devices, this bit is banked and we can set it directly.

The code checked only the ES revision of the chip, and hence incorrectly
used the ROM call on ES1.0 versions of other devices.

This patch adds a check for chip family as well as revision, and also
removes some code duplication between the enable and disable functions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
ARM: Rename arch/arm/cpu/arm_cortexa8 to armv7 2010-07-05T23:59:55+00:00 Steve Sakoman steve@sakoman.com 2010-06-18T04:50:01+00:00 f56348af5d255f6dc2a8bcd7d798ab5edf8fba25 The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9 Cortex A8 and A9 both belong to the armv7 architecture, hence the name change. The two architectures are similar enough that substantial code can be shared. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9

Cortex A8 and A9 both belong to the armv7 architecture, hence the name change.

The two architectures are similar enough that substantial code can be shared.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>