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<title>u-boot.git/arch/arm/cpu/armv8, branch v2016.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv8?h=v2016.07</id>
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<updated>2016-07-08T21:16:49Z</updated>
<entry>
<title>armv8: Enable CPUECTLR.SMPEN for coherency</title>
<updated>2016-07-08T21:16:49Z</updated>
<author>
<name>Mingkai Hu</name>
<email>mingkai.hu@nxp.com</email>
</author>
<published>2016-07-07T04:22:12Z</published>
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<id>urn:sha1:d73718f3236c520a92efa401084c658e6cc067f3</id>
<content type='text'>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@nxp.com&gt;
Reviewed-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-06-28T19:59:05Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-06-28T19:59:05Z</published>
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<id>urn:sha1:44faff24f58859bdc1acf28ac739020b5091678a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs</title>
<updated>2016-06-28T19:08:53Z</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar.kushwaha@nxp.com</email>
</author>
<published>2016-06-24T08:18:13Z</published>
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<id>urn:sha1:49cdce163519ad760ca7769be64dd2a6133a5c11</id>
<content type='text'>
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.

So append "A" to SoC names.

Signed-off-by: Pratiyush Mohan Srivastava &lt;pratiyush.srivastava@nxp.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>common: Pass the boot device into spl_boot_mode()</title>
<updated>2016-06-26T18:17:22Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2016-05-14T21:42:07Z</published>
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<id>urn:sha1:2b1cdafa9fdd0c88eb1bc96e9330e252c9795689</id>
<content type='text'>
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.

The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Andreas Bießmann &lt;andreas@biessmann.org&gt;
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann &lt;andreas@biessmann.org&gt;
</content>
</entry>
<entry>
<title>arm64: optimize smp_kick_all_cpus</title>
<updated>2016-06-24T21:23:12Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-06-17T09:32:47Z</published>
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<id>urn:sha1:afedf5488de99925f00ead847e40d7ba0d508f0e</id>
<content type='text'>
gic_kick_secondary_cpus can directly return to the caller of
smp_kick_all_cpus.  We do not have to use x29 register here.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8/fsl_lsch2: Correct the cores frequency initialization</title>
<updated>2016-06-24T15:33:08Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2016-06-12T06:42:04Z</published>
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<id>urn:sha1:f3acaf438de74a0b278abc71fb2aca7e7aa86ffa</id>
<content type='text'>
The register CLKCNCSR controls the frequency of all cores in the same
cluster.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-usb</title>
<updated>2016-06-19T03:46:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-06-19T03:46:21Z</published>
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<id>urn:sha1:a10a31ec91ad2ee514a42baea9314553aa972676</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;

Conflicts:
	arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
</content>
</entry>
<entry>
<title>armv8/ls2080: Remove workaround for erratum A008751</title>
<updated>2016-06-13T13:16:38Z</updated>
<author>
<name>Sriram Dash</name>
<email>sriram.dash@nxp.com</email>
</author>
<published>2016-06-13T04:28:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=32fbd46f38ed183ae92aabc0a2abd7847bc3363e'/>
<id>urn:sha1:32fbd46f38ed183ae92aabc0a2abd7847bc3363e</id>
<content type='text'>
This errata a008751 is applied on Soc specific file currently.This will be
moved to a file where all the errata implementation will take place for usb
for fsl. This patch removes the errata workaround from soc specific file
for LS2080.

Signed-off-by: Sriram Dash &lt;sriram.dash@nxp.com&gt;
Signed-off-by: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper</title>
<updated>2016-06-13T13:16:38Z</updated>
<author>
<name>Sriram Dash</name>
<email>sriram.dash@nxp.com</email>
</author>
<published>2016-06-13T04:28:32Z</published>
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<id>urn:sha1:6fb522dc774db981e1c8463e71898287e039c5f4</id>
<content type='text'>
Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.

Signed-off-by: Sriram Dash &lt;sriram.dash@nxp.com&gt;
Signed-off-by: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: s32v234: Introduce basic support for s32v234evb</title>
<updated>2016-06-13T12:56:35Z</updated>
<author>
<name>Eddy Petrișor</name>
<email>eddy.petrisor@gmail.com</email>
</author>
<published>2016-06-05T00:43:00Z</published>
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<id>urn:sha1:9702ec00e95dbc1fd66ef8e9624c649e1ee818e5</id>
<content type='text'>
Add initial support for NXP's S32V234 SoC and S32V234EVB board.

The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.

Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan &lt;cosminstefan.stoica@freescale.com&gt;
Original-signed-off-by: Mihaela Martinas &lt;Mihaela.Martinas@freescale.com&gt;
Original-signed-off-by: Eddy Petrișor &lt;eddy.petrisor@gmail.com&gt;

Signed-off-by: Eddy Petrișor &lt;eddy.petrisor@nxp.com&gt;
</content>
</entry>
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