<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/cpu/armv8, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv8?h=v2016.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/armv8?h=v2016.09'/>
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<updated>2016-08-12T13:23:49Z</updated>
<entry>
<title>kconfig: use bool instead of boolean for type definition attributes</title>
<updated>2016-08-12T13:23:49Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-08-12T01:26:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ab65006b08c5a2d022b1ce43581e555c82926cd4'/>
<id>urn:sha1:ab65006b08c5a2d022b1ce43581e555c82926cd4</id>
<content type='text'>
Linux stopped the use of keyword 'boolean' in Kconfig.

Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>armv8: mmu: Detect page table overflow in emergency pt creation</title>
<updated>2016-08-06T00:55:18Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2016-07-30T21:13:03Z</published>
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<id>urn:sha1:0e1709476bd4cbff2c0808c87867b6cd5286818f</id>
<content type='text'>
We create 2 sets of page tables: One for normal operation, one for
emergency (used while modifying the former).

Because the page tables grow dynamically, we have code that checks
for overflow. Unfortunately we didn't adjust the available space
variable while creating the emergency tables, so potentially someone
might run into an overflow there (not seen in real world yet though!).

Fix it by properly adjusting the size as well as the base offset in
emergency page table creation.

Reported-by: York Sun &lt;york.sun@nxp.com&gt;
Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP</title>
<updated>2016-08-02T16:51:29Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2016-07-29T11:26:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ab01ef5fa617444fd95543ee04ea53ccda273269'/>
<id>urn:sha1:ab01ef5fa617444fd95543ee04ea53ccda273269</id>
<content type='text'>
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Abhimanyu Saini &lt;abhimanyu.saini@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>zynq: Increase the early malloc() size</title>
<updated>2016-07-27T20:15:54Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-05T23:10:13Z</published>
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<id>urn:sha1:04e38905d72e4b35fade1be4b83100a257d465a5</id>
<content type='text'>
This is needed to support driver-model conversion of USB and block devices.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>armv8: fsl-layerscape: mmu: Fix enabling MMU</title>
<updated>2016-07-26T16:03:06Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-07-22T17:52:23Z</published>
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<id>urn:sha1:ed7a3943d580f4cf72e5ef8a20c43fa93e889d14</id>
<content type='text'>
MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: fsl_lsch2: Add LS1046A SoC support</title>
<updated>2016-07-26T16:02:23Z</updated>
<author>
<name>Mingkai Hu</name>
<email>mingkai.hu@nxp.com</email>
</author>
<published>2016-07-05T08:01:55Z</published>
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<id>urn:sha1:b528b9377df0e738c6904a639a1e78810936f825</id>
<content type='text'>
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Mihai Bantea &lt;mihai.bantea@freescale.com&gt;
Signed-off-by: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: fsl_lsch2: Add SerDes 2 support</title>
<updated>2016-07-26T16:02:16Z</updated>
<author>
<name>Qianyu Gong</name>
<email>qianyu.gong@nxp.com</email>
</author>
<published>2016-07-05T08:01:54Z</published>
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<id>urn:sha1:da4d620c90eb6dd9466a89837ab8667048d856e3</id>
<content type='text'>
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.

Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: fsl-layerscape: Add A72 core detection</title>
<updated>2016-07-26T16:02:00Z</updated>
<author>
<name>Alison Wang</name>
<email>b18965@freescale.com</email>
</author>
<published>2016-07-05T08:01:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79119a4d1930468c47da5d000c41751a92bcaa62'/>
<id>urn:sha1:79119a4d1930468c47da5d000c41751a92bcaa62</id>
<content type='text'>
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Signed-off-by: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Signed-off-by: Gong Qianyu &lt;Qianyu.Gong@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze</title>
<updated>2016-07-22T13:22:26Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-07-22T13:22:26Z</published>
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<id>urn:sha1:9f03247edc7761b608db31104821b4518a70e691</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM64: zynqmp: Remove get_uart_clk()</title>
<updated>2016-07-22T12:04:41Z</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2016-07-14T12:41:28Z</published>
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<id>urn:sha1:23ffd36a5295354af2dee22c00b08addd9c8a2ed</id>
<content type='text'>
ZynqMP will use reading clock freq directly from DT.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
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