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<title>u-boot.git/arch/arm/cpu/at91-common, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2015-02-21T13:23:51Z</updated>
<entry>
<title>ARM: at91: collect SoC sources into mach-at91</title>
<updated>2015-02-21T13:23:51Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2015-02-20T08:04:03Z</published>
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<id>urn:sha1:620118403e1521b4c883848a84d2fb68e3fa1aa0</id>
<content type='text'>
This commit moves source files as follows:

  arch/arm/cpu/arm920t/at91/*   -&gt; arch/arm/mach-at91/arm920t/*
  arch/arm/cpu/arm926ejs/at91/* -&gt; arch/arm/mach-at91/arm926ejs/*
  arch/arm/cpu/armv7/at91/*     -&gt; arch/arm/mach-at91/armv7/*
  arch/arm/cpu/at91-common/*    -&gt; arch/arm/mach-at91/*

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Andreas Bießmann &lt;andreas.devel@googlemail.co&gt;
</content>
</entry>
<entry>
<title>arm, at91, wdt: do not disable WDT in SPL</title>
<updated>2015-02-07T22:43:07Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2015-01-21T07:38:20Z</published>
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<id>urn:sha1:49b461f34a29fa88565c8cffa57a42a04ff36848</id>
<content type='text'>
if CONFIG_AT91SAM9_WATCHDOG is set, do not disable WDT in
SPL

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
<entry>
<title>ARM: atmel: sama5d4: build related file when enable SPL</title>
<updated>2015-02-07T22:42:52Z</updated>
<author>
<name>Bo Shen</name>
<email>voice.shen@atmel.com</email>
</author>
<published>2014-12-15T05:24:37Z</published>
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<id>urn:sha1:01c073c013551aa3461a96a23617e2179bda1f5b</id>
<content type='text'>
Signed-off-by: Bo Shen &lt;voice.shen@atmel.com&gt;
</content>
</entry>
<entry>
<title>ARM: atmel: sama5d4: can access DDR in interleave mode</title>
<updated>2015-02-07T22:42:51Z</updated>
<author>
<name>Bo Shen</name>
<email>voice.shen@atmel.com</email>
</author>
<published>2014-12-15T05:24:36Z</published>
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<id>urn:sha1:b54dd1b3adad4613bb8aa471b12f88bede699775</id>
<content type='text'>
The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen &lt;voice.shen@atmel.com&gt;
</content>
</entry>
<entry>
<title>ARM: atmel: spl: can not disable osc for sama5d4</title>
<updated>2015-02-07T22:42:47Z</updated>
<author>
<name>Bo Shen</name>
<email>voice.shen@atmel.com</email>
</author>
<published>2014-12-15T05:24:32Z</published>
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<id>urn:sha1:0246b7c3b7b974182cc5795b01261d6dd24dde71</id>
<content type='text'>
The SAMA5D4 SoC on chip rc oscillator can not be disabled.

Signed-off-by: Bo Shen &lt;voice.shen@atmel.com&gt;
</content>
</entry>
<entry>
<title>ARM: atmel: spl: add saic to aic redirect function</title>
<updated>2015-02-07T22:42:46Z</updated>
<author>
<name>Bo Shen</name>
<email>voice.shen@atmel.com</email>
</author>
<published>2014-12-15T05:24:31Z</published>
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<id>urn:sha1:4514b5f46a27df0843a8504273ee0cb0749ea86e</id>
<content type='text'>
Some SoC need to redirect the saic to aic to make the interrupt to
work, here add a weak function to be replaced by real function.

Signed-off-by: Bo Shen &lt;voice.shen@atmel.com&gt;
</content>
</entry>
<entry>
<title>ARM: atmel: spl: add weak bus matrix init function</title>
<updated>2015-02-07T22:42:45Z</updated>
<author>
<name>Bo Shen</name>
<email>voice.shen@atmel.com</email>
</author>
<published>2014-12-15T05:24:30Z</published>
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<id>urn:sha1:433be902f3a7e8b40b349e3d9dacdf0a69982ede</id>
<content type='text'>
Some SoC need to configure the bus matrix, add an weak function
to be replace by real function.

Signed-off-by: Bo Shen &lt;voice.shen@atmel.com&gt;
</content>
</entry>
<entry>
<title>arm, spl, at91: add at91sam9260 and at91sam9g45 spl support</title>
<updated>2014-11-17T13:47:17Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2014-10-31T07:31:04Z</published>
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<id>urn:sha1:5abc00d02082056765a8029675e7b05ab6c35263</id>
<content type='text'>
add support for using spl code on at91sam9260 and at91sam9g45
based boards.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Bo Shen &lt;voice.shen@atmel.com&gt;
Reviewed-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
[adopt Bo's change in spl.c]
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</content>
</entry>
<entry>
<title>arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45</title>
<updated>2014-11-17T13:47:16Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2014-10-31T07:30:58Z</published>
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<id>urn:sha1:7dd5891061763b92e41a8e451a43be3d14ac9b4e</id>
<content type='text'>
- compile mpddrc ram init code also for AT91SAM9M10G45
  based boards.
- in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
  in the cr configuration

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Reviewed-by: Bo Shen &lt;voice.shen@atmel.com&gt;
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</content>
</entry>
<entry>
<title>arm, at91, mpddrc: fix typo in ddr2_init()</title>
<updated>2014-11-17T13:47:16Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2014-10-31T07:30:57Z</published>
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<id>urn:sha1:341f548ee9f95150e64ed114361cfd5b0088f6ff</id>
<content type='text'>
use the configure value for computing the ba_off value
not the value from the cr register. This leaded in a
wrong ram configuration on the upcoming corvus spl board
support.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</content>
</entry>
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