<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/arm/cpu/pxa, branch v2016.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/pxa?h=v2016.11</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu/pxa?h=v2016.11'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-08-26T21:04:46Z</updated>
<entry>
<title>ARM: Move SYS_CACHELINE_SIZE over to Kconfig</title>
<updated>2016-08-26T21:04:46Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-22T12:22:17Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=067716bac59716b07f1ee70d9bf6e5528289bb45'/>
<id>urn:sha1:067716bac59716b07f1ee70d9bf6e5528289bb45</id>
<content type='text'>
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Prafulla Wadaskar &lt;prafulla@marvell.com&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nagendra T S &lt;nagendra@mistralsolutions.com&gt;
Cc: Vaibhav Hiremath &lt;hvaibhav@ti.com&gt;
Acked-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Cc: Steve Rae &lt;steve.rae@raedomain.com&gt;
Cc: Igor Grinberg &lt;grinberg@compulab.co.il&gt;
Cc: Nikita Kiryanov &lt;nikita@compulab.co.il&gt;
Cc: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Cc: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: "Pali Rohár" &lt;pali.rohar@gmail.com&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Cc: Steve Sakoman &lt;sakoman@gmail.com&gt;
Cc: Grazvydas Ignotas &lt;notasas@gmail.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Thomas Weber &lt;weber@corscience.de&gt;
Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: David Feng &lt;fenghua@phytium.com.cn&gt;
Cc: Alison Wang &lt;b18965@freescale.com&gt;
Cc: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Shengzhou Liu &lt;Shengzhou.Liu@nxp.com&gt;
Cc: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
Cc: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Cc: Aneesh Bansal &lt;aneesh.bansal@freescale.com&gt;
Cc: Saksham Jain &lt;saksham.jain@nxp.com&gt;
Cc: Qianyu Gong &lt;qianyu.gong@nxp.com&gt;
Cc: Wang Dongsheng &lt;dongsheng.wang@nxp.com&gt;
Cc: Alex Porosanu &lt;alexandru.porosanu@freescale.com&gt;
Cc: Hongbo Zhang &lt;hongbo.zhang@nxp.com&gt;
Cc: tang yuantian &lt;Yuantian.Tang@freescale.com&gt;
Cc: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
Cc: Josh Wu &lt;josh.wu@atmel.com&gt;
Cc: Bo Shen &lt;voice.shen@atmel.com&gt;
Cc: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Cc: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
Cc: Thomas Chou &lt;thomas@wytron.com.tw&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Christophe Ricard &lt;christophe-h.ricard@st.com&gt;
Cc: Anand Moon &lt;linux.amoon@gmail.com&gt;
Cc: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Cc: Carlo Caione &lt;carlo@endlessm.com&gt;
Cc: huang lin &lt;hl@rock-chips.com&gt;
Cc: Sjoerd Simons &lt;sjoerd.simons@collabora.co.uk&gt;
Cc: Xu Ziyuan &lt;xzy.xu@rock-chips.com&gt;
Cc: "jk.kernel@gmail.com" &lt;jk.kernel@gmail.com&gt;
Cc: "Ariel D'Alessandro" &lt;ariel@vanguardiasur.com.ar&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Samuel Egli &lt;samuel.egli@siemens.com&gt;
Cc: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@opensource.altera.com&gt;
Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Cc: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Cc: Boris Brezillon &lt;boris.brezillon@free-electrons.com&gt;
Cc: Andre Przywara &lt;andre.przywara@arm.com&gt;
Cc: Bernhard Nortmann &lt;bernhard.nortmann@web.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Ben Whitten &lt;ben.whitten@gmail.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Alexander Graf &lt;agraf@suse.de&gt;
Cc: Sekhar Nori &lt;nsekhar@ti.com&gt;
Cc: Vitaly Andrianov &lt;vitalya@ti.com&gt;
Cc: "Andrew F. Davis" &lt;afd@ti.com&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Carlos Hernandez &lt;ceh@ti.com&gt;
Cc: Ladislav Michl &lt;ladis@linux-mips.org&gt;
Cc: Ash Charles &lt;ashcharles@gmail.com&gt;
Cc: Mugunthan V N &lt;mugunthanvnm@ti.com&gt;
Cc: Daniel Allred &lt;d-allred@ti.com&gt;
Cc: Gong Qianyu &lt;Qianyu.Gong@freescale.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Acked-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Chin Liang See &lt;clsee@altera.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Paul Kocialkowski &lt;contact@paulk.fr&gt;
</content>
</entry>
<entry>
<title>pxa: add support for D- and I- caches</title>
<updated>2016-03-27T13:13:00Z</updated>
<author>
<name>Vasily Khoruzhick</name>
<email>anarsoul@gmail.com</email>
</author>
<published>2016-03-21T01:37:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9cfc05985319c52933d84a7609fc8b143b1ff18a'/>
<id>urn:sha1:9cfc05985319c52933d84a7609fc8b143b1ff18a</id>
<content type='text'>
Tested with OHCI and pxafb drivers - no issues found

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
</content>
</entry>
<entry>
<title>pxa: start.S: enable SRAM clock</title>
<updated>2016-03-27T13:12:59Z</updated>
<author>
<name>Vasily Khoruzhick</name>
<email>anarsoul@gmail.com</email>
</author>
<published>2016-03-21T01:37:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9ddde3e6ce8abd97d397e3915204a6981d287e42'/>
<id>urn:sha1:9ddde3e6ce8abd97d397e3915204a6981d287e42</id>
<content type='text'>
SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend.

Signed-off-by: Vasily Khoruzhick &lt;anarsoul@gmail.com&gt;
</content>
</entry>
<entry>
<title>ARM: start.S: fix typo</title>
<updated>2016-02-29T19:49:35Z</updated>
<author>
<name>Yuichiro Goto</name>
<email>goto.yuichiro@espark.co.jp</email>
</author>
<published>2016-02-25T01:23:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba10b852fe3a5d6188dfa43cced4bfbaf3515df1'/>
<id>urn:sha1:ba10b852fe3a5d6188dfa43cced4bfbaf3515df1</id>
<content type='text'>
Fix typo in comment about position of 'A' bit in several start.S.

Signed-off-by: Yuichiro Goto &lt;goto.yuichiro@espark.co.jp&gt;
</content>
</entry>
<entry>
<title>arm: pxa: clean-up include file order</title>
<updated>2015-08-24T18:30:37Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel@ziswiler.com</email>
</author>
<published>2015-08-16T02:16:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=67b855fe54730c16702dda0a5b2d53ab6b01500f'/>
<id>urn:sha1:67b855fe54730c16702dda0a5b2d53ab6b01500f</id>
<content type='text'>
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.

Signed-off-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
</content>
</entry>
<entry>
<title>arm: pxa: use common timer functions</title>
<updated>2015-08-24T18:30:37Z</updated>
<author>
<name>Andrew Ruder</name>
<email>andrew.ruder@elecsyscorp.com</email>
</author>
<published>2015-08-12T18:18:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7d211fec96d1d6b6d828f3bb4abc59180f6e3556'/>
<id>urn:sha1:7d211fec96d1d6b6d828f3bb4abc59180f6e3556</id>
<content type='text'>
This patch moves pxa to the common timer functions added in commit

  8dfafdd - Introduce common timer functions &lt;Rob Herring&gt;

The (removed) pxa timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks().  get_ticks() returned a 32-bit value
cast up to a 64-bit value.  If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locked the processor.  Rather than patch the specific pxa issues, simply
move everything over to the common code.

Signed-off-by: Andrew Ruder &lt;andrew.ruder@elecsyscorp.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Tom Rini &lt;trini@konsuiko.com&gt;
</content>
</entry>
<entry>
<title>pxa: Fix boot hang by avoiding vector relocation</title>
<updated>2015-08-24T18:30:37Z</updated>
<author>
<name>Andrew Ruder</name>
<email>andrew.ruder@elecsyscorp.com</email>
</author>
<published>2015-08-12T17:55:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=07a8e6d6ee04de7c95de9824e3d1821744f92970'/>
<id>urn:sha1:07a8e6d6ee04de7c95de9824e3d1821744f92970</id>
<content type='text'>
Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors")
pxa does not boot anymore.

Add a specific relocate_vectors macro that skips the vector relocation,
as the pxa SoC does not provide RAM at the high vectors address
(0xFFFF0000), and (0x00000000) maps to ROM.

This allows pxa to boot again.

Cc: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Andrew Ruder &lt;andrew.ruder@elecsyscorp.com&gt;
</content>
</entry>
<entry>
<title>ARM: move -march=* and -mtune= options to arch/arm/Makefile</title>
<updated>2015-03-27T15:55:22Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2015-02-26T17:40:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79d75d752717fb4106ec49abaddbd7744c775a35'/>
<id>urn:sha1:79d75d752717fb4106ec49abaddbd7744c775a35</id>
<content type='text'>
My main motivations for this commit are:

[1] Follow the arch/arm/Makefile style of Linux Kernel

[2] Maintain compiler options systematically
  Currently, we give -march=* and -mtune=* options inconsistently:
  Only some of the CPUs pass -march=* and -mtune=* options.
  By collecting such options into the single place arch/arm/Makefile
  we can tell which options are missing at a glance.

[3] Prepare for deprecating arch/*/cpu/*/config.mk

Note:
  This commit just moves the compiler options so as not to change
  the behavior at all.  It does not care about the correctness of
  the given options.  Fox example, "-march=armv5te" might be better
  than "-march=armv4" for ARM946EJS, but it is beyond the scope this
  commit.  Also, filling the missing -march=* and -tune=* is left
  to follow-up patches.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>remove unnecessary version.h includes</title>
<updated>2015-03-24T14:50:50Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2015-03-17T20:28:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7682a99826a624d3764656b5bb31f88e2f8b235b'/>
<id>urn:sha1:7682a99826a624d3764656b5bb31f88e2f8b235b</id>
<content type='text'>
Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
Cc: Michal Simek &lt;monstr@monstr.eu&gt;
Cc: Macpaul Lin &lt;macpaul@andestech.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: York Sun &lt;yorksun@freescale.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Philippe Reynes &lt;tremyfr@yahoo.fr&gt;
Cc: Eric Jarrige &lt;eric.jarrige@armadeus.org&gt;
Cc: "David Müller" &lt;d.mueller@elsoft.ch&gt;
Cc: Phil Edworthy &lt;phil.edworthy@renesas.com&gt;
Cc: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Cc: Torsten Koschorrek &lt;koschorrek@synertronixx.de&gt;
Cc: Anatolij Gustschin &lt;agust@denx.de&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Reviewed-by: Łukasz Majewski &lt;l.majewski@samsung.com&gt;
</content>
</entry>
<entry>
<title>arm: pxa: introducing cpuinfo display for marvell pxa270m</title>
<updated>2015-03-05T14:24:10Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel@ziswiler.com</email>
</author>
<published>2015-03-04T13:57:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=901f79e4de19af20abf9b2f2353f1750ccba5b69'/>
<id>urn:sha1:901f79e4de19af20abf9b2f2353f1750ccba5b69</id>
<content type='text'>
According to table 2-3 on page 87 of Marvell's latest PXA270
Specification Update Rev. I from 2010.04.19 [1] there exists a breed of
chips with a new CPU ID for PXA270M A1 stepping which our latest
Colibri PXA270 V2.4A modules actually have assembled. This patch helps
in correctly identifying those chips upon boot as well which then looks
as follows:

CPU: Marvell PXA27xM rev. A1

[1] http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf

Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
</feed>
