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<title>u-boot.git/arch/arm/cpu/tegra20-common/clock.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2015-02-21T13:23:51Z</updated>
<entry>
<title>ARM: tegra: collect SoC sources into mach-tegra</title>
<updated>2015-02-21T13:23:51Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2015-02-20T08:04:04Z</published>
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<id>urn:sha1:09f455dca74973ef5e42311162c8dff7e83d44a2</id>
<content type='text'>
This commit moves files as follows:

 arch/arm/cpu/arm720t/tegra20/*      -&gt; arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/arm720t/tegra30/*      -&gt; arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/arm720t/tegra114/*     -&gt; arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/arm720t/tegra124*      -&gt; arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/arm720t/tegra-common/* -&gt; arch/arm/mach-tegra/*
 arch/arm/cpu/armv7/tegra20/*        -&gt; arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/armv7/tegra30/*        -&gt; arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/armv7/tegra114/*       -&gt; arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/armv7/tegra124/*       -&gt; arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/armv7/tegra-common/*   -&gt; arch/arm/mach-tegra/*
 arch/arm/cpu/tegra20-common/*       -&gt; arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/tegra30-common/*       -&gt; arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/tegra114-common/*      -&gt; arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/tegra124-common/*      -&gt; arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/tegra-common/*         -&gt; arch/arm/mach-tegra/*

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt; [ on nyan-big ]
Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Provide PCIEXCLK reset ID</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:07Z</published>
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<id>urn:sha1:59cb3bf4c6d87448b4fb4e0fd386ac6d170a19b6</id>
<content type='text'>
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Implement tegra_plle_enable()</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:06Z</published>
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<id>urn:sha1:a7230745504552095594362b81caaa33b5d7da5e</id>
<content type='text'>
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: use MASK_BITS_* macros everywhere</title>
<updated>2014-02-03T16:46:45Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-01-24T17:16:20Z</published>
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<id>urn:sha1:54d2e182925de2be7018535ca5123e2566617540</id>
<content type='text'>
Not all code that set or interpreted "mux_bits" was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.

Replace the integer constants with the equivalent macro definitions so
that everything is nicely tied together.

Note that I'm not convinced all the code was using the correct integer
constants, and hence I'm not convinced that all the code is now using
the desired macros. However, this change is a purely mechanical
replacement and should have no functional change. Fixing any bugs will
come later, separately.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;treding@nvidia.com&gt;
Tested-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>Tegra114: Initialize System Counter (TSC) with osc frequency</title>
<updated>2013-04-15T18:01:38Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-04-01T22:48:54Z</published>
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<id>urn:sha1:b40f734af9fdc47a0993f1f94f32d40a86f30587</id>
<content type='text'>
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c</title>
<updated>2013-02-11T17:35:24Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2013-01-23T21:01:01Z</published>
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<id>urn:sha1:f29f086a098a8462f8b375da0509246843f7fdd1</id>
<content type='text'>
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c

Some T30 tables needed whitespace fixes due to checkpatch complaints.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra20: add clock_set_pllout function</title>
<updated>2012-10-15T18:54:07Z</updated>
<author>
<name>Lucas Stach</name>
<email>dev@lynxeye.de</email>
</author>
<published>2012-09-25T20:21:13Z</published>
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<id>urn:sha1:65530a842eeaf7ad07e0613ac6f883f2f1f1e33f</id>
<content type='text'>
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.

This function adds a clean way to do so.

Signed-off-by: Lucas Stach &lt;dev@lynxeye.de&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>tegra20: complete periph_id enum</title>
<updated>2012-10-15T18:54:06Z</updated>
<author>
<name>Lucas Stach</name>
<email>dev@lynxeye.de</email>
</author>
<published>2012-09-25T09:59:12Z</published>
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<id>urn:sha1:3f44e44f33899821c4703c3bd5f9c117bb328e8b</id>
<content type='text'>
Most Tegra boards output the ULPI reference clock on pad DEV2.

Complete the periph_id enum so that we are able to enable this
clock output circuit.

Signed-off-by: Lucas Stach &lt;dev@lynxeye.de&gt;
Acked-by: Stephen Warren &lt;swarren@wwwdotorg.org&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Tegra20: Move some include files to arch-tegra for sharing with Tegra30</title>
<updated>2012-10-15T18:54:06Z</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2012-09-19T22:50:56Z</published>
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<id>urn:sha1:150c24936b70ce36e11069038ba8e955704cab3a</id>
<content type='text'>
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h.
Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines &amp; structs
that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20'
'root' file.

All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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