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<title>u-boot.git/arch/arm/cpu/tegra20-common, branch master</title>
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<updated>2015-02-21T13:23:51Z</updated>
<entry>
<title>ARM: tegra: collect SoC sources into mach-tegra</title>
<updated>2015-02-21T13:23:51Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2015-02-20T08:04:04Z</published>
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<id>urn:sha1:09f455dca74973ef5e42311162c8dff7e83d44a2</id>
<content type='text'>
This commit moves files as follows:

 arch/arm/cpu/arm720t/tegra20/*      -&gt; arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/arm720t/tegra30/*      -&gt; arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/arm720t/tegra114/*     -&gt; arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/arm720t/tegra124*      -&gt; arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/arm720t/tegra-common/* -&gt; arch/arm/mach-tegra/*
 arch/arm/cpu/armv7/tegra20/*        -&gt; arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/armv7/tegra30/*        -&gt; arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/armv7/tegra114/*       -&gt; arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/armv7/tegra124/*       -&gt; arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/armv7/tegra-common/*   -&gt; arch/arm/mach-tegra/*
 arch/arm/cpu/tegra20-common/*       -&gt; arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/tegra30-common/*       -&gt; arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/tegra114-common/*      -&gt; arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/tegra124-common/*      -&gt; arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/tegra-common/*         -&gt; arch/arm/mach-tegra/*

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt; [ on nyan-big ]
Cc: Stephen Warren &lt;swarren@nvidia.com&gt;
Cc: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: i2c: Provide an offset length parameter where needed</title>
<updated>2015-01-30T00:09:53Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-25T15:26:55Z</published>
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<id>urn:sha1:25ab4b0303f2df5e6b94ed92e37875a7c98f4de3</id>
<content type='text'>
Rather than assuming that the chip offset length is 1, allow it to be
provided. This allows chips that don't use the default offset length to
be used (at present they are only supported by the command line 'i2c'
command which sets the offset length explicitly).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Provide PCIEXCLK reset ID</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:07Z</published>
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<id>urn:sha1:59cb3bf4c6d87448b4fb4e0fd386ac6d170a19b6</id>
<content type='text'>
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Implement tegra_plle_enable()</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:06Z</published>
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<id>urn:sha1:a7230745504552095594362b81caaa33b5d7da5e</id>
<content type='text'>
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: i2c: tegra: Convert to driver model</title>
<updated>2014-12-11T20:18:44Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-12-10T15:55:57Z</published>
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<id>urn:sha1:b0e6ef46405353270595ffa35c21f4334c541189</id>
<content type='text'>
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher &lt;hs@denx.de&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'u-boot/master'</title>
<updated>2014-05-09T09:50:14Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-05-09T08:47:05Z</published>
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<id>urn:sha1:d2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19</id>
<content type='text'>
Conflicts:
	drivers/net/Makefile

(trivial merge)
</content>
</entry>
<entry>
<title>ARM:tegra20: Remove aes debug prints</title>
<updated>2014-04-18T20:14:17Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-04-18T12:18:23Z</published>
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<id>urn:sha1:b149c4c399b111cec1ff7505ca9fabbeeb4fe394</id>
<content type='text'>
In 6e7b9f4 some of the debug prints for AES code moved into the generic
code, so we remove these additional calls.

Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
Acked-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>aes: make apply_cbc_chain_data non-static</title>
<updated>2014-04-18T20:14:17Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-04-18T16:28:58Z</published>
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<id>urn:sha1:53eb768dfb97269ccec60d34321252b1ee1850d9</id>
<content type='text'>
Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart
code. This function was recently moved into the core aes.c and made
static, which prevents the Tegra code from compiling. Make it public
again to avoid the compile errors:

arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’:
arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration]
arch/arm/cpu/built-in.o: In function `sign_object':
.../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data'
.../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data'

Fixes: 6e7b9f4fa0ae ("aes: Move the AES-128-CBC encryption function to common code")
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>Merge branch 'next'</title>
<updated>2014-04-17T18:33:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-04-17T18:33:25Z</published>
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<id>urn:sha1:0f507779ca00d90cdd4bcc8252630370339b7ea6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: tegra: Tegra20 pinmux cleanup</title>
<updated>2014-04-17T15:41:05Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-03-21T18:28:58Z</published>
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<id>urn:sha1:70ad375ee444645001d3ca78bb17790b50232999</id>
<content type='text'>
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
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