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<title>u-boot.git/arch/arm/cpu, branch v2014.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu?h=v2014.07</id>
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<updated>2014-07-09T13:21:51Z</updated>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2014-07-09T13:21:51Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-07-09T13:21:51Z</published>
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<id>urn:sha1:22692ec0fbdb455ca16d4d0e27768c6b6deb4243</id>
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<entry>
<title>mx6: soc: Update the comments of set_ldo_voltage()</title>
<updated>2014-07-09T13:10:10Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2014-06-13T04:42:37Z</published>
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<id>urn:sha1:157f45da91b306d71dbf3a51325352dc11bf16d1</id>
<content type='text'>
Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.

Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.

Update the comments to align with the new set_ldo_voltage() implementation.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>MX6: Correct calculation of PLL_SYS</title>
<updated>2014-07-09T12:55:30Z</updated>
<author>
<name>Andre Renaud</name>
<email>andre@bluewatersys.com</email>
</author>
<published>2014-06-09T20:47:13Z</published>
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<id>urn:sha1:2eb268f6fd236a5ad9d51e7e47190d7994b3920f</id>
<content type='text'>
DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors

Signed-off-by: Andre Renaud &lt;andre@bluewatersys.com&gt;
</content>
</entry>
<entry>
<title>am43xx: Tune the system to avoid DSS underflows</title>
<updated>2014-07-07T23:42:34Z</updated>
<author>
<name>Cooper Jr., Franklin</name>
<email>fcooper@ti.com</email>
</author>
<published>2014-06-27T18:31:15Z</published>
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<id>urn:sha1:8038b497e742af2845523ed09b560bfc8cb42089</id>
<content type='text'>
* This is done by limiting the ARM's bandwidth and setting DSS priority in
  the EMIF controller to ensure underflows do not occur.
</content>
</entry>
<entry>
<title>ARM: emif4: wait for CM_DLL_READYST to be set</title>
<updated>2014-07-07T23:42:33Z</updated>
<author>
<name>Jeroen Hofstee</name>
<email>jeroen@myspectrum.nl</email>
</author>
<published>2014-06-18T19:22:35Z</published>
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<id>urn:sha1:878cae6b0263576317fcd77bf903cb9e503e6cc7</id>
<content type='text'>
The code intends for the CM_DLL_READYST to be set, but
actually polls till any bit is set since the logical
AND is used instead of the bitwise one is used. Fix it.

cc: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Signed-off-by: Jeroen Hofstee &lt;jeroen@myspectrum.nl&gt;
</content>
</entry>
<entry>
<title>socfpga: Relocate arch common functions away from board</title>
<updated>2014-07-05T08:14:46Z</updated>
<author>
<name>Chin Liang See</name>
<email>clsee@altera.com</email>
</author>
<published>2014-06-10T07:23:45Z</published>
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<id>urn:sha1:23f23f23d509e8e873797884456070c8a47d72b2</id>
<content type='text'>
To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Detlev Zundel &lt;dzu@denx.de&gt;
Cc: Pavel Machek &lt;pavel@denx.de&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Acked-by: Detlev Zundel &lt;dzu@denx.de&gt;
</content>
</entry>
<entry>
<title>socfpga: Adding Scan Manager driver</title>
<updated>2014-07-04T22:27:27Z</updated>
<author>
<name>Chin Liang See</name>
<email>clsee@altera.com</email>
</author>
<published>2014-06-10T06:17:42Z</published>
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<id>urn:sha1:dc4d4aa14be278eaf7354c2916da6c5e7a538828</id>
<content type='text'>
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings

Signed-off-by: Chin Liang See &lt;clsee@altera.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@altera.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
CC: Pavel Machek &lt;pavel@denx.de&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
</content>
</entry>
<entry>
<title>arm: ep9315: Return back Cirrus Logic EDB9315A board support</title>
<updated>2014-07-04T21:45:48Z</updated>
<author>
<name>Sergey Kostanbaev</name>
<email>sergey.kostanbaev@gmail.com</email>
</author>
<published>2014-06-25T19:44:29Z</published>
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<id>urn:sha1:7237d22baac9ebeffc946dfd30b9f61aaf0bfdbc</id>
<content type='text'>
This patch returns back support for old ep93xx processors family

Signed-off-by: Sergey Kostanbaev &lt;sergey.kostanbaev@gmail.com&gt;
Cc: albert.u.boot@aribaud.net
</content>
</entry>
<entry>
<title>ARM: cache_v7: use __weak</title>
<updated>2014-07-04T17:57:22Z</updated>
<author>
<name>Jeroen Hofstee</name>
<email>jeroen@myspectrum.nl</email>
</author>
<published>2014-06-23T20:07:04Z</published>
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<id>urn:sha1:fcfddfd50472d7ce84ef4e2853242bbeb7b37325</id>
<content type='text'>
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.

cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Signed-off-by: Jeroen Hofstee &lt;jeroen@myspectrum.nl&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support</title>
<updated>2014-07-04T17:48:41Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2014-06-23T22:15:56Z</published>
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<id>urn:sha1:f749db3a75ec483692d7bb6d46a1fbecb65c38ba</id>
<content type='text'>
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Arnab Basu &lt;arnab.basu@freescale.com&gt;
Signed-off-by: J. German Rivera &lt;German.Rivera@freescale.com&gt;
Signed-off-by: Bhupesh Sharma &lt;bhupesh.sharma@freescale.com&gt;
</content>
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