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<title>u-boot.git/arch/arm/cpu, branch v2014.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu?h=v2014.10</id>
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<updated>2014-10-10T23:20:30Z</updated>
<entry>
<title>Merge branch 'u-boot/master' into 'u-boot-arm/master'</title>
<updated>2014-10-10T23:20:30Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-10-10T23:20:30Z</published>
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<id>urn:sha1:790af815436bc6a93e4c581840be2419897f23b1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: OMAP5+: sata: Move scsi_scan() to the right place</title>
<updated>2014-10-10T13:44:42Z</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2014-09-23T15:07:03Z</published>
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<id>urn:sha1:d59baeb76f911d0391e73e5f6068e55ea48514f8</id>
<content type='text'>
scsi_scan() must be called as part of scsi_init() and not
as part of sata_init().

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
</entry>
<entry>
<title>OMAP5+: sata/scsi: Implement scsi_init()</title>
<updated>2014-10-10T13:44:42Z</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2014-09-23T15:07:02Z</published>
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<id>urn:sha1:3160b1b98603cba3c480f70e153b259171d3e4a6</id>
<content type='text'>
On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().

Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'</title>
<updated>2014-10-10T06:56:01Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-10-10T06:56:01Z</published>
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<id>urn:sha1:ebf8644a113a36b163c2e06fe1e081c73f563c3a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>arm: rmobile: r8a7794: Skip initialize L2 cache</title>
<updated>2014-10-09T05:45:03Z</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>nobuhiro.iwamatsu.yj@renesas.com</email>
</author>
<published>2014-08-07T23:44:02Z</published>
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<id>urn:sha1:88982893c4d50692b80a2155146cda9e42266c6b</id>
<content type='text'>
rmobile/lowlevel_init_ca15.S are common in r8a7790, r8a7791 and r8a7794 of
rmobile SoCs.  The initialize L2 cache in lowlevel_init_ca15.S only needed
for Cortex-A15. The r8a7794 is Cortex-A7, not Cortex-A15.
This adds Skip to initialize L2 cache when r8a7794.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
</content>
</entry>
<entry>
<title>arm: rmobile: r8a7791: Fix initialize L2 cache</title>
<updated>2014-10-09T05:45:03Z</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>nobuhiro.iwamatsu.yj@renesas.com</email>
</author>
<published>2014-08-07T23:41:15Z</published>
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<id>urn:sha1:237faf095fb43abbed6e40266ef7efccc8b9308b</id>
<content type='text'>
rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of
rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5].
This adds fix to set L2CTLR [5] only when the r8a7790.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
</content>
</entry>
<entry>
<title>arm: rmobile: Remove unnecessary initialization for l2ctlr</title>
<updated>2014-10-09T05:45:03Z</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>nobuhiro.iwamatsu.yj@renesas.com</email>
</author>
<published>2014-08-07T00:10:45Z</published>
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<id>urn:sha1:7d835803640e743a60572b49a736370c75f9cb44</id>
<content type='text'>
This removes duplicate initialization of l2ctlr.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'u-boot-imx/master'</title>
<updated>2014-10-08T19:20:49Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-10-08T19:20:49Z</published>
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<id>urn:sha1:4b19b7448e63bab8af17abbb30acff00d8f0dc99</id>
<content type='text'>
The single file conflict below is actually trivial.

Conflicts:
	board/boundary/nitrogen6x/nitrogen6x.c
</content>
</entry>
<entry>
<title>armv7: s5pc1xx: improve cache handling</title>
<updated>2014-10-08T10:42:04Z</updated>
<author>
<name>Robert Baldyga</name>
<email>r.baldyga@samsung.com</email>
</author>
<published>2014-09-19T10:17:55Z</published>
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<id>urn:sha1:dab067c32307d7f78ab00ef19690fecbc3ad607a</id>
<content type='text'>
Move cache handling code to C file, and add enable_caches() and
disable_caches() functions.

Signed-off-by: Robert Baldyga &lt;r.baldyga@samsung.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>samsung: Enable device tree for smdkc100</title>
<updated>2014-10-08T08:25:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-10-08T04:01:51Z</published>
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<id>urn:sha1:93327f69769d9fe09ef25efd6ca9182f1095a417</id>
<content type='text'>
Change this board to add a device tree.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
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