u-boot.git/arch/arm/cpu, branch v2015.10

armv8/mmu: Set bits marked RES1 in TCR

2015-10-15T12:46:43Z

For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud Cc: Marc Zyngier Signed-off-by: Thierry Reding

Merge remote-tracking branch 'u-boot/master'

2015-10-14T08:46:36Z

ls102xa: Fix reset hang

2015-10-12T16:56:32Z

Since commit 623d96e89aca6("imx: wdog: correct wcr register settings") issuing a 'reset' command causes the system to hang. Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian. This means that the watchdog on LS1021 has been working by accident as it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c. Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only revelead the endianness problem on LS102x. In order to fix the reset hang, introduce a reset_cpu() implementation that is specific for ls102x, which accesses the watchdog WCR register in big-endian format. All that is required to reset LS102x is to clear the SRS bit. This approach is a temporary workaround to avoid a regression for LS102x in the 2015.10 release. The proper fix is to make the watchdog driver endian-aware, so that it can work for i.MX, Vybrid and LS102x. Reported-by: Sinan Akman Tested-by: Sinan Akman Reviewed-by: Wolfgang Denk Signed-off-by: Fabio Estevam

lpc32xx: fix calculation of HCLK PLL output clock

2015-10-11T21:12:13Z

Execution branches on feedback mode are swapped, this has no effect if default direct mode is on (then p_div is equal to 1 and Fout equals to Fcco), that's why the problem remained unnoticed for a long time. Signed-off-by: Vladimir Zapolskiy

arndale: Apply Cortex-A15 errata #773022 and #774769

2015-10-11T21:12:11Z

We run 4 Arndale boards in our automated test framework, they have been running quite happily for quite some time using a Debian Wheezy userspace. However when upgrading to a Debian Jessie we started seeing frequent segmentation faults from gcc when building the kernel, to the extent that it is unable to successfully build the kernel twice in a row, and often fails on the first attempt. Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417 which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html and CPU Errata 773022 and 774769. This errata needs to be applied to all processors in an SMP system, meaning that the usual strategy of applying them in arch/arm/cpu/armv7/start.S is not appropriate (since that applies to the boot processor only). Instead we apply these errata in the secure monitor which is code that is traversed by all processors as they are brought up. The net affect on Arndale is that ACTLR changes from 0x40 to 0x2000042. I ran 17 kernel compile iterations overnight with no segfaults. Runtime testing was done on our v2014.10 based branch and forward ported (with only minimal and trivial contextual conflicts) to current master, where it has been build tested only. I suppose in theory these errata apply to any Exynos5250 based boards, but Arndale is the only one I have access to and I have therefore chosen to be conservative and only apply it there. Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list numerically sorted. Signed-off-by: Ian Campbell

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

2015-10-02T13:38:44Z

imx: mx6: correct enable_fec_anatop_clock

2015-10-02T08:42:31Z

We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, otherwise we may overridden configuration before enable_fec_anatop_clock. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Cc: Fabio Estevam

sunxi: retrieve FEL-provided values to environment variables

2015-09-29T09:50:07Z

This patch extends the misc_init_r() function on sunxi boards to test for the presence of a suitable "sunxi" SPL header. If found, and the loader ("fel" utility) provided a non-zero value for the boot.scr address, then the corresponding environment variable fel_scriptaddr gets set. misc_init_r() also sets (or clears) the "fel_booted" variable depending on the active boot device, using the same logic as spl_boot_device(). The goal is to provide sufficient information (within the U-Boot environment) to make intelligent decisions on how to continue the boot process, allowing specific customizations for the "FEL boot" case. Signed-off-by: Bernhard Nortmann Acked-by: Hans de Goede Signed-off-by: Hans de Goede

sunxi: Simplify spl board_init_f function

2015-09-29T09:50:07Z

crt0.S will both memset the bss sectioan and call board_init_r for us, so there is no need to do either ourselves. Signed-off-by: Hans de Goede Acked-by: Ian Campbell

imx: fix coding style

2015-09-24T09:32:38Z

Fix coding style. Signed-off-by: Peng Fan Cc: Stefano Babic