u-boot.git/arch/arm/cpu, branch v2016.01-rc2

am33xx: Update serial pdata

2015-12-06T21:38:05Z

We now want to make sure that we have the platform data for NS16550 when we do not have OF_CONTROL set. Signed-off-by: Tom Rini Reviewed-by: Simon Glass

Change e-mail address of Kamil Lulko

2015-12-05T23:22:32Z

Signed-off-by: Kamil Lulko

arch/arm/cpu/arm920t/ep93xx/led.c: Mark inline functions as static inline

2015-12-05T23:22:28Z

With gcc-5.x we get warning about inline non-static functions referring to static elements. Signed-off-by: Tom Rini Reviewed-by: Bin Meng

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

2015-12-04T13:21:28Z

ARM: mxs: fix VDDD brownout setting

2015-12-01T15:05:24Z

At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value. Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV. Register content calculation: (1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14 Register takes only 3 bits, that is 0x4. But 0x4 * 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V. Minimum possible BO level is 1500 [mV] - 0x7 * 25 [mV] = 1315 [mV]. So lets use this value as desired BO value (which is also the same as FSL bootlets use). Signed-off-by: Michael Heimpold Cc: Marek Vasut Cc: Otavio Salvador Cc: Fabio Estevam Acked-by: Marek Vasut

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

2015-11-30T20:18:30Z

armv8: ls2085a: Add workaround of errata A009635

2015-11-30T17:11:12Z

If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun

armv8: fsl-layerscape: Fix "cpu release" command

2015-11-30T17:11:12Z

When one core is released, other cores may not have valid entry address. Those cores are trapped by "wfe" and wait for further instruction. When their address is set, they need to be kicked off by "sev". Signed-off-by: York Sun

armv8/layerscape: Update MMU table with execute-never bits

2015-11-30T17:11:11Z

For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun Signed-off-by: Alison Wang Reported-by: Zhichun Hua

armv8/fsl-layerscape: Remove reference to gdata

2015-11-30T17:11:10Z

The global_data pointer (gd) has been set earlier in crt0_64.S. So there's no need to assign it again. Remove gdata since it is going away in U-Boot. Signed-off-by: Gong Qianyu Reviewed-by: York Sun