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<title>u-boot.git/arch/arm/cpu, branch v2016.11-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/arm/cpu?h=v2016.11-rc2</id>
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<updated>2016-10-14T20:18:34Z</updated>
<entry>
<title>ARM: create .secure_stack section only for PSCI</title>
<updated>2016-10-14T20:18:34Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-26T05:21:30Z</published>
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<id>urn:sha1:2fe1281c79cb8232cf0ca1c441db66e576a9acf4</id>
<content type='text'>
Jon Master reports that QEMU refuses to load a U-Boot image built
with CONFIG_ARMV7_NONSEC, but without CONFIG_ARMV7_PSCI since
commit 5a3aae68c74e ("ARM: armv7: guard memory reserve for PSCI
with #ifdef CONFIG_ARMV7_PSCI").

It looks like only PSCI that needs the Secure stack, so move
the #ifdef to guard the whole of .secure_stack allocation in order
not to create the empty section.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reported-by: Jon Masters &lt;jcm@redhat.com&gt;
Link: http://patchwork.ozlabs.org/patch/664025/
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-10-12T12:29:42Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-10-12T12:29:42Z</published>
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<id>urn:sha1:711b534120c0a5f73cdb9a25eb91f9aa0c5e09ab</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;

Conflicts:
	include/configs/ls1021aqds.h
	include/configs/ls1021atwr.h
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2016-10-08T13:33:37Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-10-08T02:02:10Z</published>
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<id>urn:sha1:f5fd45ff64e28a73499548358e3d1ceda0de7daf</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: AM437X: Add Silicon ID support</title>
<updated>2016-10-08T13:33:36Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2016-10-04T04:04:50Z</published>
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<id>urn:sha1:1f957708072e153637718497f7a1a6e364220337</id>
<content type='text'>
Add silicon ID code for AM437x silicon. This can be used to print
the cpu info using CONFIG_DISPLAY_CPUINFO.
Also printing "CPU :" along with cpu name in order to be consistent
with other OMAP platforms.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: vf610: use strcpy for soc environment variable</title>
<updated>2016-10-07T13:56:52Z</updated>
<author>
<name>Stefan Agner</name>
<email>stefan.agner@toradex.com</email>
</author>
<published>2016-09-28T09:29:28Z</published>
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<id>urn:sha1:d7255e8ddbfe76d7b0d18247d35742596c85ad93</id>
<content type='text'>
To create the soc environment variable we concatenate two strings
on the stack. So far, strcat has been used for the first string as
well as for the second string. Since the variable on the stack is
not initialized, the first strcat may not start using the first
entry in the character array. This then could lead to an buffer
overflow on the stack.

Signed-off-by: Stefan Agner &lt;stefan.agner@toradex.com&gt;
Acked-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
</content>
</entry>
<entry>
<title>ARM: OMAP5+: Override switch_to_hypervisor function</title>
<updated>2016-10-07T00:58:16Z</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2016-09-14T05:13:33Z</published>
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<id>urn:sha1:1dbc40e7d2c87f40addbfd6b7a2f119493133d22</id>
<content type='text'>
Override the switch_to_hypervisor function to switch cpu to hypervisor
mode using the available ROM code hook early in the boot phase before
the boot loader checks for HYP mode.

Based on the work done by Jonathan Bergsagel jbergsagel@ti.com.

Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ARM: Introduce function to switch to hypervisor mode</title>
<updated>2016-10-07T00:58:16Z</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2016-09-14T05:13:32Z</published>
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<id>urn:sha1:d31d4a2d7523c73b5da03a1697b6438e1fe1b027</id>
<content type='text'>
On some of the SoCs one cannot enable hypervisor mode directly from the
u-boot because the ROM code puts the chip to supervisor mode after it
jumps to boot loader. Hence introduce a weak function which can be
overridden based on the SoC type and switch to hypervisor mode in a
custom way.

Cc: beagleboard-x15@googlegroups.com
Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>omap: Set appropriate cache configuration for LPAE and non-LAPE cases</title>
<updated>2016-10-07T00:57:44Z</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2016-09-14T05:13:29Z</published>
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<id>urn:sha1:859c70df231981b1baafb79a0139515c8bde016c</id>
<content type='text'>
Cache configuration methods is different for LPAE and non-LPAE cases.
Hence the bits and the interpretaion is different for two cases.
In case of non-LPAE mode short descriptor format is used and we need
to set Cache and Buffer bits.

In the case of LPAE the cache configuration happens via MAIR0 lookup.

Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>omap: Remove hardcoding of mmu section shift to 20</title>
<updated>2016-10-07T00:57:43Z</updated>
<author>
<name>Keerthy</name>
<email>j-keerthy@ti.com</email>
</author>
<published>2016-09-14T05:13:28Z</published>
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<id>urn:sha1:c268a9bde00898acd8580f721a741dea1af871db</id>
<content type='text'>
As of now the mmu section shift is hardcoded to 20 but with LPAE
coming into picture this can be different. Hence replacing 20 with
MMU_SECTION_SHIFT macro.

Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>ARMv8/sec-firmware: fix a compile error</title>
<updated>2016-10-07T00:57:36Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2016-09-06T06:23:07Z</published>
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<id>urn:sha1:81049ba8f43618a85867d88bb612fb5106f41dad</id>
<content type='text'>
When enabled sec firmware framework, but lack of definition of
the marco SEC_FIRMWARE_FIT_IMAGE, SEC_FIRMEWARE_FIT_CNF_NAME
and SEC_FIRMWARE_TARGET_EL, there will be some build errors,
so give a default definition.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
</content>
</entry>
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